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drm/i915: convert HDMI driver to new encoder/connector structure
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
29#include "drmP.h"
30#include "drm.h"
31#include "drm_crtc.h"
32#include "drm_crtc_helper.h"
33#include "intel_drv.h"
34#include "i915_drm.h"
35#include "i915_drv.h"
ab2c0672 36#include "drm_dp_helper.h"
a4fc5ed6 37
ae266c98 38
a4fc5ed6
KP		 39#define DP_LINK_STATUS_SIZE 6
40#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
41
42#define DP_LINK_CONFIGURATION_SIZE 9
43
32f9d658
ZW		 44#define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
45
a4fc5ed6
KP		 46struct intel_dp_priv {
47 uint32_t output_reg;
48 uint32_t DP;
49 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
a4fc5ed6 50 bool has_audio;
c8110e52 51 int dpms_mode;
a4fc5ed6
KP		 52 uint8_t link_bw;
53 uint8_t lane_count;
54 uint8_t dpcd[4];
21d40d37 55 struct intel_encoder *intel_encoder;
a4fc5ed6
KP		 56 struct i2c_adapter adapter;
57 struct i2c_algo_dp_aux_data algo;
58};
59
60static void
21d40d37 61intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
a4fc5ed6
KP		 62 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
63
64static void
21d40d37 65intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP);
a4fc5ed6 66
32f9d658 67void
21d40d37 68intel_edp_link_config (struct intel_encoder *intel_encoder,
32f9d658
ZW		 69 int *lane_num, int *link_bw)
70{
21d40d37 71 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
32f9d658
ZW		 72
73 *lane_num = dp_priv->lane_count;
74 if (dp_priv->link_bw == DP_LINK_BW_1_62)
75 *link_bw = 162000;
76 else if (dp_priv->link_bw == DP_LINK_BW_2_7)
77 *link_bw = 270000;
78}
79
a4fc5ed6 80static int
21d40d37 81intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
a4fc5ed6 82{
21d40d37 83 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 84 int max_lane_count = 4;
85
86 if (dp_priv->dpcd[0] >= 0x11) {
87 max_lane_count = dp_priv->dpcd[2] & 0x1f;
88 switch (max_lane_count) {
89 case 1: case 2: case 4:
90 break;
91 default:
92 max_lane_count = 4;
93 }
94 }
95 return max_lane_count;
96}
97
98static int
21d40d37 99intel_dp_max_link_bw(struct intel_encoder *intel_encoder)
a4fc5ed6 100{
21d40d37 101 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 102 int max_link_bw = dp_priv->dpcd[1];
103
104 switch (max_link_bw) {
105 case DP_LINK_BW_1_62:
106 case DP_LINK_BW_2_7:
107 break;
108 default:
109 max_link_bw = DP_LINK_BW_1_62;
110 break;
111 }
112 return max_link_bw;
113}
114
115static int
116intel_dp_link_clock(uint8_t link_bw)
117{
118 if (link_bw == DP_LINK_BW_2_7)
119 return 270000;
120 else
121 return 162000;
122}
123
124/* I think this is a fiction */
125static int
885a5fb5 126intel_dp_link_required(struct drm_device *dev,
21d40d37 127 struct intel_encoder *intel_encoder, int pixel_clock)
a4fc5ed6 128{
885a5fb5
ZW		 129 struct drm_i915_private *dev_priv = dev->dev_private;
130
21d40d37 131 if (IS_eDP(intel_encoder))
885a5fb5
ZW		 132 return (pixel_clock * dev_priv->edp_bpp) / 8;
133 else
134 return pixel_clock * 3;
a4fc5ed6
KP		 135}
136
137static int
138intel_dp_mode_valid(struct drm_connector *connector,
139 struct drm_display_mode *mode)
140{
21d40d37
EA		 141 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
142 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
143 int max_lanes = intel_dp_max_lane_count(intel_encoder);
a4fc5ed6 144
21d40d37 145 if (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
885a5fb5 146 > max_link_clock * max_lanes)
a4fc5ed6
KP		 147 return MODE_CLOCK_HIGH;
148
149 if (mode->clock < 10000)
150 return MODE_CLOCK_LOW;
151
152 return MODE_OK;
153}
154
155static uint32_t
156pack_aux(uint8_t *src, int src_bytes)
157{
158 int i;
159 uint32_t v = 0;
160
161 if (src_bytes > 4)
162 src_bytes = 4;
163 for (i = 0; i < src_bytes; i++)
164 v |= ((uint32_t) src[i]) << ((3-i) * 8);
165 return v;
166}
167
168static void
169unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
170{
171 int i;
172 if (dst_bytes > 4)
173 dst_bytes = 4;
174 for (i = 0; i < dst_bytes; i++)
175 dst[i] = src >> ((3-i) * 8);
176}
177
fb0f8fbf
KP		 178/* hrawclock is 1/4 the FSB frequency */
179static int
180intel_hrawclk(struct drm_device *dev)
181{
182 struct drm_i915_private *dev_priv = dev->dev_private;
183 uint32_t clkcfg;
184
185 clkcfg = I915_READ(CLKCFG);
186 switch (clkcfg & CLKCFG_FSB_MASK) {
187 case CLKCFG_FSB_400:
188 return 100;
189 case CLKCFG_FSB_533:
190 return 133;
191 case CLKCFG_FSB_667:
192 return 166;
193 case CLKCFG_FSB_800:
194 return 200;
195 case CLKCFG_FSB_1067:
196 return 266;
197 case CLKCFG_FSB_1333:
198 return 333;
199 /* these two are just a guess; one of them might be right */
200 case CLKCFG_FSB_1600:
201 case CLKCFG_FSB_1600_ALT:
202 return 400;
203 default:
204 return 133;
205 }
206}
207
a4fc5ed6 208static int
21d40d37 209intel_dp_aux_ch(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 210 uint8_t *send, int send_bytes,
211 uint8_t *recv, int recv_size)
212{
21d40d37 213 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6 214 uint32_t output_reg = dp_priv->output_reg;
21d40d37 215 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6
KP		 216 struct drm_i915_private *dev_priv = dev->dev_private;
217 uint32_t ch_ctl = output_reg + 0x10;
218 uint32_t ch_data = ch_ctl + 4;
219 int i;
220 int recv_bytes;
221 uint32_t ctl;
222 uint32_t status;
fb0f8fbf 223 uint32_t aux_clock_divider;
e3421a18 224 int try, precharge;
a4fc5ed6
KP		 225
226 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 227 * and would like to run at 2MHz. So, take the
228 * hrawclk value and divide by 2 and use that
a4fc5ed6 229 */
e3421a18
ZW		 230 if (IS_eDP(intel_encoder)) {
231 if (IS_GEN6(dev))
232 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
233 else
234 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
235 } else if (HAS_PCH_SPLIT(dev))
f2b115e6 236 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 237 else
238 aux_clock_divider = intel_hrawclk(dev) / 2;
239
e3421a18
ZW		 240 if (IS_GEN6(dev))
241 precharge = 3;
242 else
243 precharge = 5;
244
fb0f8fbf
KP		 245 /* Must try at least 3 times according to DP spec */
246 for (try = 0; try < 5; try++) {
247 /* Load the send data into the aux channel data registers */
248 for (i = 0; i < send_bytes; i += 4) {
a419aef8 249 uint32_t d = pack_aux(send + i, send_bytes - i);
fb0f8fbf
KP		 250
251 I915_WRITE(ch_data + i, d);
252 }
253
254 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
255 DP_AUX_CH_CTL_TIME_OUT_400us |
256 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
e3421a18 257 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
fb0f8fbf
KP		 258 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
259 DP_AUX_CH_CTL_DONE |
260 DP_AUX_CH_CTL_TIME_OUT_ERROR |
261 DP_AUX_CH_CTL_RECEIVE_ERROR);
262
263 /* Send the command and wait for it to complete */
264 I915_WRITE(ch_ctl, ctl);
265 (void) I915_READ(ch_ctl);
266 for (;;) {
267 udelay(100);
268 status = I915_READ(ch_ctl);
269 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
270 break;
271 }
272
273 /* Clear done status and any errors */
eebc863e 274 I915_WRITE(ch_ctl, (status |
fb0f8fbf
KP		 275 DP_AUX_CH_CTL_DONE |
276 DP_AUX_CH_CTL_TIME_OUT_ERROR |
277 DP_AUX_CH_CTL_RECEIVE_ERROR));
278 (void) I915_READ(ch_ctl);
279 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
a4fc5ed6
KP		 280 break;
281 }
282
a4fc5ed6 283 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 284 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 285 return -EBUSY;
a4fc5ed6
KP		 286 }
287
288 /* Check for timeout or receive error.
289 * Timeouts occur when the sink is not connected
290 */
a5b3da54 291 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 292 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 293 return -EIO;
294 }
1ae8c0a5
KP		 295
296 /* Timeouts occur when the device isn't connected, so they're
297 * "normal" -- don't fill the kernel log with these */
a5b3da54 298 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 299 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 300 return -ETIMEDOUT;
a4fc5ed6
KP		 301 }
302
303 /* Unload any bytes sent back from the other side */
304 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
305 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
306
307 if (recv_bytes > recv_size)
308 recv_bytes = recv_size;
309
310 for (i = 0; i < recv_bytes; i += 4) {
311 uint32_t d = I915_READ(ch_data + i);
312
313 unpack_aux(d, recv + i, recv_bytes - i);
314 }
315
316 return recv_bytes;
317}
318
319/* Write data to the aux channel in native mode */
320static int
21d40d37 321intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 322 uint16_t address, uint8_t *send, int send_bytes)
323{
324 int ret;
325 uint8_t msg[20];
326 int msg_bytes;
327 uint8_t ack;
328
329 if (send_bytes > 16)
330 return -1;
331 msg[0] = AUX_NATIVE_WRITE << 4;
332 msg[1] = address >> 8;
eebc863e 333 msg[2] = address & 0xff;
a4fc5ed6
KP		 334 msg[3] = send_bytes - 1;
335 memcpy(&msg[4], send, send_bytes);
336 msg_bytes = send_bytes + 4;
337 for (;;) {
21d40d37 338 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 339 if (ret < 0)
340 return ret;
341 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
342 break;
343 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
344 udelay(100);
345 else
a5b3da54 346 return -EIO;
a4fc5ed6
KP		 347 }
348 return send_bytes;
349}
350
351/* Write a single byte to the aux channel in native mode */
352static int
21d40d37 353intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 354 uint16_t address, uint8_t byte)
355{
21d40d37 356 return intel_dp_aux_native_write(intel_encoder, address, &byte, 1);
a4fc5ed6
KP		 357}
358
359/* read bytes from a native aux channel */
360static int
21d40d37 361intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 362 uint16_t address, uint8_t *recv, int recv_bytes)
363{
364 uint8_t msg[4];
365 int msg_bytes;
366 uint8_t reply[20];
367 int reply_bytes;
368 uint8_t ack;
369 int ret;
370
371 msg[0] = AUX_NATIVE_READ << 4;
372 msg[1] = address >> 8;
373 msg[2] = address & 0xff;
374 msg[3] = recv_bytes - 1;
375
376 msg_bytes = 4;
377 reply_bytes = recv_bytes + 1;
378
379 for (;;) {
21d40d37 380 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes,
a4fc5ed6 381 reply, reply_bytes);
a5b3da54
KP		 382 if (ret == 0)
383 return -EPROTO;
384 if (ret < 0)
a4fc5ed6
KP		 385 return ret;
386 ack = reply[0];
387 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
388 memcpy(recv, reply + 1, ret - 1);
389 return ret - 1;
390 }
391 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
392 udelay(100);
393 else
a5b3da54 394 return -EIO;
a4fc5ed6
KP		 395 }
396}
397
398static int
ab2c0672
DA		 399intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
400 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 401{
ab2c0672 402 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
a4fc5ed6
KP		 403 struct intel_dp_priv *dp_priv = container_of(adapter,
404 struct intel_dp_priv,
405 adapter);
21d40d37 406 struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
ab2c0672
DA		 407 uint16_t address = algo_data->address;
408 uint8_t msg[5];
409 uint8_t reply[2];
410 int msg_bytes;
411 int reply_bytes;
412 int ret;
413
414 /* Set up the command byte */
415 if (mode & MODE_I2C_READ)
416 msg[0] = AUX_I2C_READ << 4;
417 else
418 msg[0] = AUX_I2C_WRITE << 4;
419
420 if (!(mode & MODE_I2C_STOP))
421 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 422
ab2c0672
DA		 423 msg[1] = address >> 8;
424 msg[2] = address;
425
426 switch (mode) {
427 case MODE_I2C_WRITE:
428 msg[3] = 0;
429 msg[4] = write_byte;
430 msg_bytes = 5;
431 reply_bytes = 1;
432 break;
433 case MODE_I2C_READ:
434 msg[3] = 0;
435 msg_bytes = 4;
436 reply_bytes = 2;
437 break;
438 default:
439 msg_bytes = 3;
440 reply_bytes = 1;
441 break;
442 }
443
444 for (;;) {
21d40d37 445 ret = intel_dp_aux_ch(intel_encoder,
ab2c0672
DA		 446 msg, msg_bytes,
447 reply, reply_bytes);
448 if (ret < 0) {
3ff99164 449 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 450 return ret;
451 }
452 switch (reply[0] & AUX_I2C_REPLY_MASK) {
453 case AUX_I2C_REPLY_ACK:
454 if (mode == MODE_I2C_READ) {
455 *read_byte = reply[1];
456 }
457 return reply_bytes - 1;
458 case AUX_I2C_REPLY_NACK:
3ff99164 459 DRM_DEBUG_KMS("aux_ch nack\n");
ab2c0672
DA		 460 return -EREMOTEIO;
461 case AUX_I2C_REPLY_DEFER:
3ff99164 462 DRM_DEBUG_KMS("aux_ch defer\n");
ab2c0672
DA		 463 udelay(100);
464 break;
465 default:
466 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
467 return -EREMOTEIO;
468 }
469 }
a4fc5ed6
KP		 470}
471
472static int
21d40d37 473intel_dp_i2c_init(struct intel_encoder *intel_encoder, const char *name)
a4fc5ed6 474{
21d40d37 475 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6 476
d54e9d28 477 DRM_DEBUG_KMS("i2c_init %s\n", name);
a4fc5ed6
KP		 478 dp_priv->algo.running = false;
479 dp_priv->algo.address = 0;
480 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
481
482 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
483 dp_priv->adapter.owner = THIS_MODULE;
484 dp_priv->adapter.class = I2C_CLASS_DDC;
eebc863e
ZW		 485 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
486 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
a4fc5ed6 487 dp_priv->adapter.algo_data = &dp_priv->algo;
21d40d37 488 dp_priv->adapter.dev.parent = &intel_encoder->base.kdev;
a4fc5ed6
KP		 489
490 return i2c_dp_aux_add_bus(&dp_priv->adapter);
491}
492
493static bool
494intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
495 struct drm_display_mode *adjusted_mode)
496{
21d40d37
EA		 497 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
498 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6 499 int lane_count, clock;
21d40d37
EA		 500 int max_lane_count = intel_dp_max_lane_count(intel_encoder);
501 int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
a4fc5ed6
KP		 502 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
503
504 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
505 for (clock = 0; clock <= max_clock; clock++) {
506 int link_avail = intel_dp_link_clock(bws[clock]) * lane_count;
507
21d40d37 508 if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
885a5fb5 509 <= link_avail) {
a4fc5ed6
KP		 510 dp_priv->link_bw = bws[clock];
511 dp_priv->lane_count = lane_count;
512 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
28c97730
ZY		 513 DRM_DEBUG_KMS("Display port link bw %02x lane "
514 "count %d clock %d\n",
a4fc5ed6
KP		 515 dp_priv->link_bw, dp_priv->lane_count,
516 adjusted_mode->clock);
517 return true;
518 }
519 }
520 }
521 return false;
522}
523
524struct intel_dp_m_n {
525 uint32_t tu;
526 uint32_t gmch_m;
527 uint32_t gmch_n;
528 uint32_t link_m;
529 uint32_t link_n;
530};
531
532static void
533intel_reduce_ratio(uint32_t *num, uint32_t *den)
534{
535 while (*num > 0xffffff || *den > 0xffffff) {
536 *num >>= 1;
537 *den >>= 1;
538 }
539}
540
541static void
542intel_dp_compute_m_n(int bytes_per_pixel,
543 int nlanes,
544 int pixel_clock,
545 int link_clock,
546 struct intel_dp_m_n *m_n)
547{
548 m_n->tu = 64;
549 m_n->gmch_m = pixel_clock * bytes_per_pixel;
550 m_n->gmch_n = link_clock * nlanes;
551 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
552 m_n->link_m = pixel_clock;
553 m_n->link_n = link_clock;
554 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
555}
556
557void
558intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
559 struct drm_display_mode *adjusted_mode)
560{
561 struct drm_device *dev = crtc->dev;
562 struct drm_mode_config *mode_config = &dev->mode_config;
563 struct drm_connector *connector;
564 struct drm_i915_private *dev_priv = dev->dev_private;
565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
566 int lane_count = 4;
567 struct intel_dp_m_n m_n;
568
569 /*
21d40d37 570 * Find the lane count in the intel_encoder private
a4fc5ed6
KP		 571 */
572 list_for_each_entry(connector, &mode_config->connector_list, head) {
21d40d37
EA		 573 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
574 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 575
576 if (!connector->encoder || connector->encoder->crtc != crtc)
577 continue;
578
21d40d37 579 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
a4fc5ed6
KP		 580 lane_count = dp_priv->lane_count;
581 break;
582 }
583 }
584
585 /*
586 * Compute the GMCH and Link ratios. The '3' here is
587 * the number of bytes_per_pixel post-LUT, which we always
588 * set up for 8-bits of R/G/B, or 3 bytes total.
589 */
590 intel_dp_compute_m_n(3, lane_count,
591 mode->clock, adjusted_mode->clock, &m_n);
592
c619eed4 593 if (HAS_PCH_SPLIT(dev)) {
5eb08b69
ZW		 594 if (intel_crtc->pipe == 0) {
595 I915_WRITE(TRANSA_DATA_M1,
596 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
597 m_n.gmch_m);
598 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
599 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
600 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
601 } else {
602 I915_WRITE(TRANSB_DATA_M1,
603 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
604 m_n.gmch_m);
605 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
606 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
607 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
608 }
a4fc5ed6 609 } else {
5eb08b69
ZW		 610 if (intel_crtc->pipe == 0) {
611 I915_WRITE(PIPEA_GMCH_DATA_M,
612 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
613 m_n.gmch_m);
614 I915_WRITE(PIPEA_GMCH_DATA_N,
615 m_n.gmch_n);
616 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
617 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
618 } else {
619 I915_WRITE(PIPEB_GMCH_DATA_M,
620 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
621 m_n.gmch_m);
622 I915_WRITE(PIPEB_GMCH_DATA_N,
623 m_n.gmch_n);
624 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
625 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
626 }
a4fc5ed6
KP		 627 }
628}
629
630static void
631intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
632 struct drm_display_mode *adjusted_mode)
633{
e3421a18 634 struct drm_device *dev = encoder->dev;
21d40d37
EA		 635 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
636 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
637 struct drm_crtc *crtc = intel_encoder->enc.crtc;
a4fc5ed6
KP		 638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
639
e3421a18 640 dp_priv->DP = (DP_VOLTAGE_0_4 |
9c9e7927
AJ		 641 DP_PRE_EMPHASIS_0);
642
643 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
644 dp_priv->DP |= DP_SYNC_HS_HIGH;
645 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
646 dp_priv->DP |= DP_SYNC_VS_HIGH;
a4fc5ed6 647
e3421a18
ZW		 648 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
649 dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT;
650 else
651 dp_priv->DP |= DP_LINK_TRAIN_OFF;
652
a4fc5ed6
KP		 653 switch (dp_priv->lane_count) {
654 case 1:
655 dp_priv->DP |= DP_PORT_WIDTH_1;
656 break;
657 case 2:
658 dp_priv->DP |= DP_PORT_WIDTH_2;
659 break;
660 case 4:
661 dp_priv->DP |= DP_PORT_WIDTH_4;
662 break;
663 }
664 if (dp_priv->has_audio)
665 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
666
667 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
668 dp_priv->link_configuration[0] = dp_priv->link_bw;
669 dp_priv->link_configuration[1] = dp_priv->lane_count;
670
671 /*
672 * Check for DPCD version > 1.1,
673 * enable enahanced frame stuff in that case
674 */
675 if (dp_priv->dpcd[0] >= 0x11) {
676 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
677 dp_priv->DP |= DP_ENHANCED_FRAMING;
678 }
679
e3421a18
ZW		 680 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
681 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
a4fc5ed6 682 dp_priv->DP |= DP_PIPEB_SELECT;
32f9d658 683
21d40d37 684 if (IS_eDP(intel_encoder)) {
32f9d658
ZW		 685 /* don't miss out required setting for eDP */
686 dp_priv->DP |= DP_PLL_ENABLE;
687 if (adjusted_mode->clock < 200000)
688 dp_priv->DP |= DP_PLL_FREQ_160MHZ;
689 else
690 dp_priv->DP |= DP_PLL_FREQ_270MHZ;
691 }
a4fc5ed6
KP		 692}
693
f2b115e6 694static void ironlake_edp_backlight_on (struct drm_device *dev)
32f9d658
ZW		 695{
696 struct drm_i915_private *dev_priv = dev->dev_private;
697 u32 pp;
698
28c97730 699 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 700 pp = I915_READ(PCH_PP_CONTROL);
701 pp |= EDP_BLC_ENABLE;
702 I915_WRITE(PCH_PP_CONTROL, pp);
703}
704
f2b115e6 705static void ironlake_edp_backlight_off (struct drm_device *dev)
32f9d658
ZW		 706{
707 struct drm_i915_private *dev_priv = dev->dev_private;
708 u32 pp;
709
28c97730 710 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 711 pp = I915_READ(PCH_PP_CONTROL);
712 pp &= ~EDP_BLC_ENABLE;
713 I915_WRITE(PCH_PP_CONTROL, pp);
714}
a4fc5ed6
KP		 715
716static void
717intel_dp_dpms(struct drm_encoder *encoder, int mode)
718{
21d40d37
EA		 719 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
720 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
721 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6
KP		 722 struct drm_i915_private *dev_priv = dev->dev_private;
723 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
724
725 if (mode != DRM_MODE_DPMS_ON) {
32f9d658 726 if (dp_reg & DP_PORT_EN) {
21d40d37
EA		 727 intel_dp_link_down(intel_encoder, dp_priv->DP);
728 if (IS_eDP(intel_encoder))
f2b115e6 729 ironlake_edp_backlight_off(dev);
32f9d658 730 }
a4fc5ed6 731 } else {
32f9d658 732 if (!(dp_reg & DP_PORT_EN)) {
21d40d37
EA		 733 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
734 if (IS_eDP(intel_encoder))
f2b115e6 735 ironlake_edp_backlight_on(dev);
32f9d658 736 }
a4fc5ed6 737 }
c8110e52 738 dp_priv->dpms_mode = mode;
a4fc5ed6
KP		 739}
740
741/*
742 * Fetch AUX CH registers 0x202 - 0x207 which contain
743 * link status information
744 */
745static bool
21d40d37 746intel_dp_get_link_status(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 747 uint8_t link_status[DP_LINK_STATUS_SIZE])
748{
749 int ret;
750
21d40d37 751 ret = intel_dp_aux_native_read(intel_encoder,
a4fc5ed6
KP		 752 DP_LANE0_1_STATUS,
753 link_status, DP_LINK_STATUS_SIZE);
754 if (ret != DP_LINK_STATUS_SIZE)
755 return false;
756 return true;
757}
758
759static uint8_t
760intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
761 int r)
762{
763 return link_status[r - DP_LANE0_1_STATUS];
764}
765
a4fc5ed6
KP		 766static uint8_t
767intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
768 int lane)
769{
770 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
771 int s = ((lane & 1) ?
772 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
773 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
774 uint8_t l = intel_dp_link_status(link_status, i);
775
776 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
777}
778
779static uint8_t
780intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
781 int lane)
782{
783 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
784 int s = ((lane & 1) ?
785 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
786 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
787 uint8_t l = intel_dp_link_status(link_status, i);
788
789 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
790}
791
792
793#if 0
794static char *voltage_names[] = {
795 "0.4V", "0.6V", "0.8V", "1.2V"
796};
797static char *pre_emph_names[] = {
798 "0dB", "3.5dB", "6dB", "9.5dB"
799};
800static char *link_train_names[] = {
801 "pattern 1", "pattern 2", "idle", "off"
802};
803#endif
804
805/*
806 * These are source-specific values; current Intel hardware supports
807 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
808 */
809#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
810
811static uint8_t
812intel_dp_pre_emphasis_max(uint8_t voltage_swing)
813{
814 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
815 case DP_TRAIN_VOLTAGE_SWING_400:
816 return DP_TRAIN_PRE_EMPHASIS_6;
817 case DP_TRAIN_VOLTAGE_SWING_600:
818 return DP_TRAIN_PRE_EMPHASIS_6;
819 case DP_TRAIN_VOLTAGE_SWING_800:
820 return DP_TRAIN_PRE_EMPHASIS_3_5;
821 case DP_TRAIN_VOLTAGE_SWING_1200:
822 default:
823 return DP_TRAIN_PRE_EMPHASIS_0;
824 }
825}
826
827static void
21d40d37 828intel_get_adjust_train(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 829 uint8_t link_status[DP_LINK_STATUS_SIZE],
830 int lane_count,
831 uint8_t train_set[4])
832{
833 uint8_t v = 0;
834 uint8_t p = 0;
835 int lane;
836
837 for (lane = 0; lane < lane_count; lane++) {
838 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
839 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
840
841 if (this_v > v)
842 v = this_v;
843 if (this_p > p)
844 p = this_p;
845 }
846
847 if (v >= I830_DP_VOLTAGE_MAX)
848 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
849
850 if (p >= intel_dp_pre_emphasis_max(v))
851 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
852
853 for (lane = 0; lane < 4; lane++)
854 train_set[lane] = v | p;
855}
856
857static uint32_t
858intel_dp_signal_levels(uint8_t train_set, int lane_count)
859{
860 uint32_t signal_levels = 0;
861
862 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
863 case DP_TRAIN_VOLTAGE_SWING_400:
864 default:
865 signal_levels |= DP_VOLTAGE_0_4;
866 break;
867 case DP_TRAIN_VOLTAGE_SWING_600:
868 signal_levels |= DP_VOLTAGE_0_6;
869 break;
870 case DP_TRAIN_VOLTAGE_SWING_800:
871 signal_levels |= DP_VOLTAGE_0_8;
872 break;
873 case DP_TRAIN_VOLTAGE_SWING_1200:
874 signal_levels |= DP_VOLTAGE_1_2;
875 break;
876 }
877 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
878 case DP_TRAIN_PRE_EMPHASIS_0:
879 default:
880 signal_levels |= DP_PRE_EMPHASIS_0;
881 break;
882 case DP_TRAIN_PRE_EMPHASIS_3_5:
883 signal_levels |= DP_PRE_EMPHASIS_3_5;
884 break;
885 case DP_TRAIN_PRE_EMPHASIS_6:
886 signal_levels |= DP_PRE_EMPHASIS_6;
887 break;
888 case DP_TRAIN_PRE_EMPHASIS_9_5:
889 signal_levels |= DP_PRE_EMPHASIS_9_5;
890 break;
891 }
892 return signal_levels;
893}
894
e3421a18
ZW		 895/* Gen6's DP voltage swing and pre-emphasis control */
896static uint32_t
897intel_gen6_edp_signal_levels(uint8_t train_set)
898{
899 switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
900 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
901 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
902 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
903 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
904 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
905 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
906 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
907 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
908 default:
909 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
910 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
911 }
912}
913
a4fc5ed6
KP		 914static uint8_t
915intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
916 int lane)
917{
918 int i = DP_LANE0_1_STATUS + (lane >> 1);
919 int s = (lane & 1) * 4;
920 uint8_t l = intel_dp_link_status(link_status, i);
921
922 return (l >> s) & 0xf;
923}
924
925/* Check for clock recovery is done on all channels */
926static bool
927intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
928{
929 int lane;
930 uint8_t lane_status;
931
932 for (lane = 0; lane < lane_count; lane++) {
933 lane_status = intel_get_lane_status(link_status, lane);
934 if ((lane_status & DP_LANE_CR_DONE) == 0)
935 return false;
936 }
937 return true;
938}
939
940/* Check to see if channel eq is done on all channels */
941#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
942 DP_LANE_CHANNEL_EQ_DONE|\
943 DP_LANE_SYMBOL_LOCKED)
944static bool
945intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
946{
947 uint8_t lane_align;
948 uint8_t lane_status;
949 int lane;
950
951 lane_align = intel_dp_link_status(link_status,
952 DP_LANE_ALIGN_STATUS_UPDATED);
953 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
954 return false;
955 for (lane = 0; lane < lane_count; lane++) {
956 lane_status = intel_get_lane_status(link_status, lane);
957 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
958 return false;
959 }
960 return true;
961}
962
963static bool
21d40d37 964intel_dp_set_link_train(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 965 uint32_t dp_reg_value,
966 uint8_t dp_train_pat,
967 uint8_t train_set[4],
968 bool first)
969{
21d40d37 970 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 971 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 972 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 973 int ret;
974
975 I915_WRITE(dp_priv->output_reg, dp_reg_value);
976 POSTING_READ(dp_priv->output_reg);
977 if (first)
978 intel_wait_for_vblank(dev);
979
21d40d37 980 intel_dp_aux_native_write_1(intel_encoder,
a4fc5ed6
KP		 981 DP_TRAINING_PATTERN_SET,
982 dp_train_pat);
983
21d40d37 984 ret = intel_dp_aux_native_write(intel_encoder,
a4fc5ed6
KP		 985 DP_TRAINING_LANE0_SET, train_set, 4);
986 if (ret != 4)
987 return false;
988
989 return true;
990}
991
992static void
21d40d37 993intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
a4fc5ed6
KP		 994 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
995{
21d40d37 996 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 997 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 998 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 999 uint8_t train_set[4];
1000 uint8_t link_status[DP_LINK_STATUS_SIZE];
1001 int i;
1002 uint8_t voltage;
1003 bool clock_recovery = false;
1004 bool channel_eq = false;
1005 bool first = true;
1006 int tries;
e3421a18 1007 u32 reg;
a4fc5ed6
KP		 1008
1009 /* Write the link configuration data */
ab00a9ef 1010 intel_dp_aux_native_write(intel_encoder, DP_LINK_BW_SET,
a4fc5ed6
KP		 1011 link_configuration, DP_LINK_CONFIGURATION_SIZE);
1012
1013 DP |= DP_PORT_EN;
e3421a18
ZW		 1014 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1015 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1016 else
1017 DP &= ~DP_LINK_TRAIN_MASK;
a4fc5ed6
KP		 1018 memset(train_set, 0, 4);
1019 voltage = 0xff;
1020 tries = 0;
1021 clock_recovery = false;
1022 for (;;) {
1023 /* Use train_set[0] to set the voltage and pre emphasis values */
e3421a18
ZW		 1024 uint32_t signal_levels;
1025 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1026 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1027 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1028 } else {
1029 signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1030 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1031 }
a4fc5ed6 1032
e3421a18
ZW		 1033 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1034 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1035 else
1036 reg = DP | DP_LINK_TRAIN_PAT_1;
1037
1038 if (!intel_dp_set_link_train(intel_encoder, reg,
a4fc5ed6
KP		 1039 DP_TRAINING_PATTERN_1, train_set, first))
1040 break;
1041 first = false;
1042 /* Set training pattern 1 */
1043
1044 udelay(100);
21d40d37 1045 if (!intel_dp_get_link_status(intel_encoder, link_status))
a4fc5ed6
KP		 1046 break;
1047
1048 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
1049 clock_recovery = true;
1050 break;
1051 }
1052
1053 /* Check to see if we've tried the max voltage */
1054 for (i = 0; i < dp_priv->lane_count; i++)
1055 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1056 break;
1057 if (i == dp_priv->lane_count)
1058 break;
1059
1060 /* Check to see if we've tried the same voltage 5 times */
1061 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1062 ++tries;
1063 if (tries == 5)
1064 break;
1065 } else
1066 tries = 0;
1067 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1068
1069 /* Compute new train_set as requested by target */
21d40d37 1070 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
a4fc5ed6
KP		 1071 }
1072
1073 /* channel equalization */
1074 tries = 0;
1075 channel_eq = false;
1076 for (;;) {
1077 /* Use train_set[0] to set the voltage and pre emphasis values */
e3421a18
ZW		 1078 uint32_t signal_levels;
1079
1080 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1081 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1082 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1083 } else {
1084 signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1085 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1086 }
1087
1088 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1089 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1090 else
1091 reg = DP | DP_LINK_TRAIN_PAT_2;
a4fc5ed6
KP		 1092
1093 /* channel eq pattern */
e3421a18 1094 if (!intel_dp_set_link_train(intel_encoder, reg,
a4fc5ed6
KP		 1095 DP_TRAINING_PATTERN_2, train_set,
1096 false))
1097 break;
1098
1099 udelay(400);
21d40d37 1100 if (!intel_dp_get_link_status(intel_encoder, link_status))
a4fc5ed6
KP		 1101 break;
1102
1103 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
1104 channel_eq = true;
1105 break;
1106 }
1107
1108 /* Try 5 times */
1109 if (tries > 5)
1110 break;
1111
1112 /* Compute new train_set as requested by target */
21d40d37 1113 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
a4fc5ed6
KP		 1114 ++tries;
1115 }
1116
e3421a18
ZW		 1117 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1118 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1119 else
1120 reg = DP | DP_LINK_TRAIN_OFF;
1121
1122 I915_WRITE(dp_priv->output_reg, reg);
a4fc5ed6 1123 POSTING_READ(dp_priv->output_reg);
21d40d37 1124 intel_dp_aux_native_write_1(intel_encoder,
a4fc5ed6
KP		 1125 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1126}
1127
1128static void
21d40d37 1129intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
a4fc5ed6 1130{
21d40d37 1131 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 1132 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 1133 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6 1134
28c97730 1135 DRM_DEBUG_KMS("\n");
32f9d658 1136
21d40d37 1137 if (IS_eDP(intel_encoder)) {
32f9d658
ZW		 1138 DP &= ~DP_PLL_ENABLE;
1139 I915_WRITE(dp_priv->output_reg, DP);
1140 POSTING_READ(dp_priv->output_reg);
1141 udelay(100);
1142 }
1143
e3421a18
ZW		 1144 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) {
1145 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1146 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1147 POSTING_READ(dp_priv->output_reg);
1148 } else {
1149 DP &= ~DP_LINK_TRAIN_MASK;
1150 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1151 POSTING_READ(dp_priv->output_reg);
1152 }
5eb08b69
ZW		 1153
1154 udelay(17000);
1155
21d40d37 1156 if (IS_eDP(intel_encoder))
32f9d658 1157 DP |= DP_LINK_TRAIN_OFF;
a4fc5ed6
KP		 1158 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1159 POSTING_READ(dp_priv->output_reg);
1160}
1161
a4fc5ed6
KP		 1162/*
1163 * According to DP spec
1164 * 5.1.2:
1165 * 1. Read DPCD
1166 * 2. Configure link according to Receiver Capabilities
1167 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1168 * 4. Check link status on receipt of hot-plug interrupt
1169 */
1170
1171static void
21d40d37 1172intel_dp_check_link_status(struct intel_encoder *intel_encoder)
a4fc5ed6 1173{
21d40d37 1174 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 1175 uint8_t link_status[DP_LINK_STATUS_SIZE];
1176
21d40d37 1177 if (!intel_encoder->enc.crtc)
a4fc5ed6
KP		 1178 return;
1179
21d40d37
EA		 1180 if (!intel_dp_get_link_status(intel_encoder, link_status)) {
1181 intel_dp_link_down(intel_encoder, dp_priv->DP);
a4fc5ed6
KP		 1182 return;
1183 }
1184
1185 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
21d40d37 1186 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
a4fc5ed6 1187}
a4fc5ed6 1188
5eb08b69 1189static enum drm_connector_status
f2b115e6 1190ironlake_dp_detect(struct drm_connector *connector)
5eb08b69 1191{
21d40d37
EA		 1192 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1193 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
5eb08b69
ZW		 1194 enum drm_connector_status status;
1195
1196 status = connector_status_disconnected;
21d40d37 1197 if (intel_dp_aux_native_read(intel_encoder,
5eb08b69
ZW		 1198 0x000, dp_priv->dpcd,
1199 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1200 {
1201 if (dp_priv->dpcd[0] != 0)
1202 status = connector_status_connected;
1203 }
1204 return status;
1205}
1206
a4fc5ed6
KP		 1207/**
1208 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1209 *
1210 * \return true if DP port is connected.
1211 * \return false if DP port is disconnected.
1212 */
1213static enum drm_connector_status
1214intel_dp_detect(struct drm_connector *connector)
1215{
21d40d37
EA		 1216 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1217 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 1218 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 1219 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 1220 uint32_t temp, bit;
1221 enum drm_connector_status status;
1222
1223 dp_priv->has_audio = false;
1224
c619eed4 1225 if (HAS_PCH_SPLIT(dev))
f2b115e6 1226 return ironlake_dp_detect(connector);
5eb08b69 1227
a4fc5ed6
KP		 1228 temp = I915_READ(PORT_HOTPLUG_EN);
1229
1230 I915_WRITE(PORT_HOTPLUG_EN,
1231 temp |
1232 DPB_HOTPLUG_INT_EN |
1233 DPC_HOTPLUG_INT_EN |
1234 DPD_HOTPLUG_INT_EN);
1235
1236 POSTING_READ(PORT_HOTPLUG_EN);
1237
1238 switch (dp_priv->output_reg) {
1239 case DP_B:
1240 bit = DPB_HOTPLUG_INT_STATUS;
1241 break;
1242 case DP_C:
1243 bit = DPC_HOTPLUG_INT_STATUS;
1244 break;
1245 case DP_D:
1246 bit = DPD_HOTPLUG_INT_STATUS;
1247 break;
1248 default:
1249 return connector_status_unknown;
1250 }
1251
1252 temp = I915_READ(PORT_HOTPLUG_STAT);
1253
1254 if ((temp & bit) == 0)
1255 return connector_status_disconnected;
1256
1257 status = connector_status_disconnected;
21d40d37 1258 if (intel_dp_aux_native_read(intel_encoder,
a4fc5ed6
KP		 1259 0x000, dp_priv->dpcd,
1260 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1261 {
1262 if (dp_priv->dpcd[0] != 0)
1263 status = connector_status_connected;
1264 }
1265 return status;
1266}
1267
1268static int intel_dp_get_modes(struct drm_connector *connector)
1269{
21d40d37
EA		 1270 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
1271 struct drm_device *dev = intel_encoder->base.dev;
32f9d658
ZW		 1272 struct drm_i915_private *dev_priv = dev->dev_private;
1273 int ret;
a4fc5ed6
KP		 1274
1275 /* We should parse the EDID data and find out if it has an audio sink
1276 */
1277
335af9a2 1278 ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
32f9d658
ZW		 1279 if (ret)
1280 return ret;
1281
1282 /* if eDP has no EDID, try to use fixed panel mode from VBT */
21d40d37 1283 if (IS_eDP(intel_encoder)) {
32f9d658
ZW		 1284 if (dev_priv->panel_fixed_mode != NULL) {
1285 struct drm_display_mode *mode;
1286 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1287 drm_mode_probed_add(connector, mode);
1288 return 1;
1289 }
1290 }
1291 return 0;
a4fc5ed6
KP		 1292}
1293
1294static void
1295intel_dp_destroy (struct drm_connector *connector)
1296{
21d40d37 1297 struct intel_encoder *intel_encoder = to_intel_encoder(connector);
a4fc5ed6 1298
21d40d37
EA		 1299 if (intel_encoder->i2c_bus)
1300 intel_i2c_destroy(intel_encoder->i2c_bus);
a4fc5ed6
KP		 1301 drm_sysfs_connector_remove(connector);
1302 drm_connector_cleanup(connector);
21d40d37 1303 kfree(intel_encoder);
a4fc5ed6
KP		 1304}
1305
1306static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1307 .dpms = intel_dp_dpms,
1308 .mode_fixup = intel_dp_mode_fixup,
1309 .prepare = intel_encoder_prepare,
1310 .mode_set = intel_dp_mode_set,
1311 .commit = intel_encoder_commit,
1312};
1313
1314static const struct drm_connector_funcs intel_dp_connector_funcs = {
1315 .dpms = drm_helper_connector_dpms,
a4fc5ed6
KP		 1316 .detect = intel_dp_detect,
1317 .fill_modes = drm_helper_probe_single_connector_modes,
1318 .destroy = intel_dp_destroy,
1319};
1320
1321static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1322 .get_modes = intel_dp_get_modes,
1323 .mode_valid = intel_dp_mode_valid,
1324 .best_encoder = intel_best_encoder,
1325};
1326
1327static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1328{
1329 drm_encoder_cleanup(encoder);
1330}
1331
1332static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1333 .destroy = intel_dp_enc_destroy,
1334};
1335
c8110e52 1336void
21d40d37 1337intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 1338{
21d40d37 1339 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
c8110e52
KP		 1340
1341 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
21d40d37 1342 intel_dp_check_link_status(intel_encoder);
c8110e52 1343}
6207937d 1344
e3421a18
ZW		 1345/* Return which DP Port should be selected for Transcoder DP control */
1346int
1347intel_trans_dp_port_sel (struct drm_crtc *crtc)
1348{
1349 struct drm_device *dev = crtc->dev;
1350 struct drm_mode_config *mode_config = &dev->mode_config;
1351 struct drm_encoder *encoder;
1352 struct intel_encoder *intel_encoder = NULL;
1353
1354 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1355 if (!encoder || encoder->crtc != crtc)
1356 continue;
1357
1358 intel_encoder = enc_to_intel_encoder(encoder);
1359 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1360 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1361 return dp_priv->output_reg;
1362 }
1363 }
1364 return -1;
1365}
1366
a4fc5ed6
KP		 1367void
1368intel_dp_init(struct drm_device *dev, int output_reg)
1369{
1370 struct drm_i915_private *dev_priv = dev->dev_private;
1371 struct drm_connector *connector;
21d40d37 1372 struct intel_encoder *intel_encoder;
a4fc5ed6 1373 struct intel_dp_priv *dp_priv;
5eb08b69 1374 const char *name = NULL;
a4fc5ed6 1375
21d40d37 1376 intel_encoder = kcalloc(sizeof(struct intel_encoder) +
a4fc5ed6 1377 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
21d40d37 1378 if (!intel_encoder)
a4fc5ed6
KP		 1379 return;
1380
21d40d37 1381 dp_priv = (struct intel_dp_priv *)(intel_encoder + 1);
a4fc5ed6 1382
21d40d37 1383 connector = &intel_encoder->base;
a4fc5ed6
KP		 1384 drm_connector_init(dev, connector, &intel_dp_connector_funcs,
1385 DRM_MODE_CONNECTOR_DisplayPort);
1386 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1387
32f9d658 1388 if (output_reg == DP_A)
21d40d37 1389 intel_encoder->type = INTEL_OUTPUT_EDP;
32f9d658 1390 else
21d40d37 1391 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a4fc5ed6 1392
652af9d7 1393 if (output_reg == DP_B || output_reg == PCH_DP_B)
21d40d37 1394 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 1395 else if (output_reg == DP_C || output_reg == PCH_DP_C)
21d40d37 1396 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 1397 else if (output_reg == DP_D || output_reg == PCH_DP_D)
21d40d37 1398 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
f8aed700 1399
21d40d37
EA		 1400 if (IS_eDP(intel_encoder))
1401 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
6251ec0a 1402
21d40d37 1403 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
a4fc5ed6
KP		 1404 connector->interlace_allowed = true;
1405 connector->doublescan_allowed = 0;
1406
21d40d37 1407 dp_priv->intel_encoder = intel_encoder;
a4fc5ed6
KP		 1408 dp_priv->output_reg = output_reg;
1409 dp_priv->has_audio = false;
c8110e52 1410 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
21d40d37 1411 intel_encoder->dev_priv = dp_priv;
a4fc5ed6 1412
21d40d37 1413 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
a4fc5ed6 1414 DRM_MODE_ENCODER_TMDS);
21d40d37 1415 drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
a4fc5ed6 1416
21d40d37
EA		 1417 drm_mode_connector_attach_encoder(&intel_encoder->base,
1418 &intel_encoder->enc);
a4fc5ed6
KP		 1419 drm_sysfs_connector_add(connector);
1420
1421 /* Set up the DDC bus. */
5eb08b69 1422 switch (output_reg) {
32f9d658
ZW		 1423 case DP_A:
1424 name = "DPDDC-A";
1425 break;
5eb08b69
ZW		 1426 case DP_B:
1427 case PCH_DP_B:
b01f2c3a
JB		 1428 dev_priv->hotplug_supported_mask |=
1429 HDMIB_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1430 name = "DPDDC-B";
1431 break;
1432 case DP_C:
1433 case PCH_DP_C:
b01f2c3a
JB		 1434 dev_priv->hotplug_supported_mask |=
1435 HDMIC_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1436 name = "DPDDC-C";
1437 break;
1438 case DP_D:
1439 case PCH_DP_D:
b01f2c3a
JB		 1440 dev_priv->hotplug_supported_mask |=
1441 HDMID_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1442 name = "DPDDC-D";
1443 break;
1444 }
1445
21d40d37 1446 intel_dp_i2c_init(intel_encoder, name);
32f9d658 1447
21d40d37
EA		 1448 intel_encoder->ddc_bus = &dp_priv->adapter;
1449 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 1450
32f9d658
ZW		 1451 if (output_reg == DP_A) {
1452 /* initialize panel mode from VBT if available for eDP */
1453 if (dev_priv->lfp_lvds_vbt_mode) {
1454 dev_priv->panel_fixed_mode =
1455 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1456 if (dev_priv->panel_fixed_mode) {
1457 dev_priv->panel_fixed_mode->type |=
1458 DRM_MODE_TYPE_PREFERRED;
1459 }
1460 }
1461 }
1462
a4fc5ed6
KP		 1463 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1464 * 0xd. Failure to do so will result in spurious interrupts being
1465 * generated on the port when a cable is not attached.
1466 */
1467 if (IS_G4X(dev) && !IS_GM45(dev)) {
1468 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1469 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1470 }
1471}
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