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drm/i915: Unduplicate VLV phy pre pll enabling code
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf 50struct dp_link_dpll {
840b32b7 51 int clock;
9dd4ffdf
CML		 52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
840b32b7 56 { 162000,
9dd4ffdf 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
840b32b7 58 { 270000,
9dd4ffdf
CML		 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
840b32b7 63 { 162000,
9dd4ffdf 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
840b32b7 65 { 270000,
9dd4ffdf
CML		 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5 69static const struct dp_link_dpll vlv_dpll[] = {
840b32b7 70 { 162000,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
840b32b7 72 { 270000,
65ce4bf5
CML		 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
840b32b7 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
ef9348c8 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
840b32b7 88 { 270000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
840b32b7 90 { 540000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8
CML		 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15
VS		 97 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 99
cfcb0fc9
JB		 100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
da63a9f2
PZ		 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 112}
113
68b4d824 114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 115{
68b4d824
ID		 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 119}
120
df0e9248
CW		 121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
fa90ecef 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 124}
125
ea5b213a 126static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
f21a2198 132static void intel_dp_unset_edid(struct intel_dp *intel_dp);
a4fc5ed6 133
ed4e9c1d
VS		 134static int
135intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 136{
7183dc29 137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 138
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
141 case DP_LINK_BW_2_7:
1db10e28 142 case DP_LINK_BW_5_4:
d4eead50 143 break;
a4fc5ed6 144 default:
d4eead50
ID		 145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
146 max_link_bw);
a4fc5ed6
KP		 147 max_link_bw = DP_LINK_BW_1_62;
148 break;
149 }
150 return max_link_bw;
151}
152
eeb6324d
PZ		 153static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
154{
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
eeb6324d
PZ		 156 u8 source_max, sink_max;
157
ccb1a831 158 source_max = intel_dig_port->max_lanes;
eeb6324d
PZ		 159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
160
161 return min(source_max, sink_max);
162}
163
cd9dde44
AJ		 164/*
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
167 *
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
169 *
170 * 270000 * 1 * 8 / 10 == 216000
171 *
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
176 *
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
179 */
180
a4fc5ed6 181static int
c898261c 182intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 183{
cd9dde44 184 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 185}
186
fe27d53e
DA		 187static int
188intel_dp_max_data_rate(int max_link_clock, int max_lanes)
189{
190 return (max_link_clock * max_lanes * 8) / 10;
191}
192
c19de8eb 193static enum drm_mode_status
a4fc5ed6
KP		 194intel_dp_mode_valid(struct drm_connector *connector,
195 struct drm_display_mode *mode)
196{
df0e9248 197 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 198 struct intel_connector *intel_connector = to_intel_connector(connector);
199 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 200 int target_clock = mode->clock;
201 int max_rate, mode_rate, max_lanes, max_link_clock;
799487f5 202 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
a4fc5ed6 203
dd06f90e
JN		 204 if (is_edp(intel_dp) && fixed_mode) {
205 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 206 return MODE_PANEL;
207
dd06f90e 208 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 209 return MODE_PANEL;
03afc4a2
DV		 210
211 target_clock = fixed_mode->clock;
7de56f43
ZY		 212 }
213
50fec21a 214 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 215 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 216
217 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
218 mode_rate = intel_dp_link_required(target_clock, 18);
219
799487f5 220 if (mode_rate > max_rate || target_clock > max_dotclk)
c4867936 221 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 222
223 if (mode->clock < 10000)
224 return MODE_CLOCK_LOW;
225
0af78a2b
DV		 226 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
227 return MODE_H_ILLEGAL;
228
a4fc5ed6
KP		 229 return MODE_OK;
230}
231
a4f1289e 232uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 233{
234 int i;
235 uint32_t v = 0;
236
237 if (src_bytes > 4)
238 src_bytes = 4;
239 for (i = 0; i < src_bytes; i++)
240 v |= ((uint32_t) src[i]) << ((3-i) * 8);
241 return v;
242}
243
c2af70e2 244static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 245{
246 int i;
247 if (dst_bytes > 4)
248 dst_bytes = 4;
249 for (i = 0; i < dst_bytes; i++)
250 dst[i] = src >> ((3-i) * 8);
251}
252
bf13e81b
JN		 253static void
254intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 255 struct intel_dp *intel_dp);
bf13e81b
JN		 256static void
257intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 258 struct intel_dp *intel_dp);
bf13e81b 259
773538e8
VS		 260static void pps_lock(struct intel_dp *intel_dp)
261{
262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
263 struct intel_encoder *encoder = &intel_dig_port->base;
264 struct drm_device *dev = encoder->base.dev;
265 struct drm_i915_private *dev_priv = dev->dev_private;
266 enum intel_display_power_domain power_domain;
267
268 /*
269 * See vlv_power_sequencer_reset() why we need
270 * a power domain reference here.
271 */
25f78f58 272 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 273 intel_display_power_get(dev_priv, power_domain);
274
275 mutex_lock(&dev_priv->pps_mutex);
276}
277
278static void pps_unlock(struct intel_dp *intel_dp)
279{
280 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
281 struct intel_encoder *encoder = &intel_dig_port->base;
282 struct drm_device *dev = encoder->base.dev;
283 struct drm_i915_private *dev_priv = dev->dev_private;
284 enum intel_display_power_domain power_domain;
285
286 mutex_unlock(&dev_priv->pps_mutex);
287
25f78f58 288 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 289 intel_display_power_put(dev_priv, power_domain);
290}
291
961a0db0
VS		 292static void
293vlv_power_sequencer_kick(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct drm_device *dev = intel_dig_port->base.base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum pipe pipe = intel_dp->pps_pipe;
0047eedc
VS		 299 bool pll_enabled, release_cl_override = false;
300 enum dpio_phy phy = DPIO_PHY(pipe);
301 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
961a0db0
VS		 302 uint32_t DP;
303
304 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
305 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
306 pipe_name(pipe), port_name(intel_dig_port->port)))
307 return;
308
309 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
310 pipe_name(pipe), port_name(intel_dig_port->port));
311
312 /* Preserve the BIOS-computed detected bit. This is
313 * supposed to be read-only.
314 */
315 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
316 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
317 DP |= DP_PORT_WIDTH(1);
318 DP |= DP_LINK_TRAIN_PAT_1;
319
320 if (IS_CHERRYVIEW(dev))
321 DP |= DP_PIPE_SELECT_CHV(pipe);
322 else if (pipe == PIPE_B)
323 DP |= DP_PIPEB_SELECT;
324
d288f65f
VS		 325 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
326
327 /*
328 * The DPLL for the pipe must be enabled for this to work.
329 * So enable temporarily it if it's not already enabled.
330 */
0047eedc
VS		 331 if (!pll_enabled) {
332 release_cl_override = IS_CHERRYVIEW(dev) &&
333 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
334
3f36b937
TU		 335 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
336 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
337 DRM_ERROR("Failed to force on pll for pipe %c!\n",
338 pipe_name(pipe));
339 return;
340 }
0047eedc 341 }
d288f65f 342
961a0db0
VS		 343 /*
344 * Similar magic as in intel_dp_enable_port().
345 * We _must_ do this port enable + disable trick
346 * to make this power seqeuencer lock onto the port.
347 * Otherwise even VDD force bit won't work.
348 */
349 I915_WRITE(intel_dp->output_reg, DP);
350 POSTING_READ(intel_dp->output_reg);
351
352 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
353 POSTING_READ(intel_dp->output_reg);
354
355 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
356 POSTING_READ(intel_dp->output_reg);
d288f65f 357
0047eedc 358 if (!pll_enabled) {
d288f65f 359 vlv_force_pll_off(dev, pipe);
0047eedc
VS		 360
361 if (release_cl_override)
362 chv_phy_powergate_ch(dev_priv, phy, ch, false);
363 }
961a0db0
VS		 364}
365
bf13e81b
JN		 366static enum pipe
367vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
368{
369 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 370 struct drm_device *dev = intel_dig_port->base.base.dev;
371 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 372 struct intel_encoder *encoder;
373 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 374 enum pipe pipe;
bf13e81b 375
e39b999a 376 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 377
a8c3344e
VS		 378 /* We should never land here with regular DP ports */
379 WARN_ON(!is_edp(intel_dp));
380
a4a5d2f8
VS		 381 if (intel_dp->pps_pipe != INVALID_PIPE)
382 return intel_dp->pps_pipe;
383
384 /*
385 * We don't have power sequencer currently.
386 * Pick one that's not used by other ports.
387 */
19c8054c 388 for_each_intel_encoder(dev, encoder) {
a4a5d2f8
VS		 389 struct intel_dp *tmp;
390
391 if (encoder->type != INTEL_OUTPUT_EDP)
392 continue;
393
394 tmp = enc_to_intel_dp(&encoder->base);
395
396 if (tmp->pps_pipe != INVALID_PIPE)
397 pipes &= ~(1 << tmp->pps_pipe);
398 }
399
400 /*
401 * Didn't find one. This should not happen since there
402 * are two power sequencers and up to two eDP ports.
403 */
404 if (WARN_ON(pipes == 0))
a8c3344e
VS		 405 pipe = PIPE_A;
406 else
407 pipe = ffs(pipes) - 1;
a4a5d2f8 408
a8c3344e
VS		 409 vlv_steal_power_sequencer(dev, pipe);
410 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 411
412 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
413 pipe_name(intel_dp->pps_pipe),
414 port_name(intel_dig_port->port));
415
416 /* init power sequencer on this pipe and port */
36b5f425
VS		 417 intel_dp_init_panel_power_sequencer(dev, intel_dp);
418 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 419
961a0db0
VS		 420 /*
421 * Even vdd force doesn't work until we've made
422 * the power sequencer lock in on the port.
423 */
424 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 425
426 return intel_dp->pps_pipe;
427}
428
6491ab27
VS		 429typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
430 enum pipe pipe);
431
432static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
433 enum pipe pipe)
434{
435 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
436}
437
438static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
439 enum pipe pipe)
440{
441 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
442}
443
444static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
445 enum pipe pipe)
446{
447 return true;
448}
bf13e81b 449
a4a5d2f8 450static enum pipe
6491ab27
VS		 451vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
452 enum port port,
453 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 454{
455 enum pipe pipe;
bf13e81b 456
bf13e81b
JN		 457 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
458 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
459 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 460
461 if (port_sel != PANEL_PORT_SELECT_VLV(port))
462 continue;
463
6491ab27
VS		 464 if (!pipe_check(dev_priv, pipe))
465 continue;
466
a4a5d2f8 467 return pipe;
bf13e81b
JN		 468 }
469
a4a5d2f8
VS		 470 return INVALID_PIPE;
471}
472
473static void
474vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
475{
476 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
477 struct drm_device *dev = intel_dig_port->base.base.dev;
478 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 479 enum port port = intel_dig_port->port;
480
481 lockdep_assert_held(&dev_priv->pps_mutex);
482
483 /* try to find a pipe with this port selected */
6491ab27
VS		 484 /* first pick one where the panel is on */
485 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
486 vlv_pipe_has_pp_on);
487 /* didn't find one? pick one where vdd is on */
488 if (intel_dp->pps_pipe == INVALID_PIPE)
489 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
490 vlv_pipe_has_vdd_on);
491 /* didn't find one? pick one with just the correct port */
492 if (intel_dp->pps_pipe == INVALID_PIPE)
493 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
494 vlv_pipe_any);
a4a5d2f8
VS		 495
496 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
497 if (intel_dp->pps_pipe == INVALID_PIPE) {
498 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
499 port_name(port));
500 return;
bf13e81b
JN		 501 }
502
a4a5d2f8
VS		 503 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
504 port_name(port), pipe_name(intel_dp->pps_pipe));
505
36b5f425
VS		 506 intel_dp_init_panel_power_sequencer(dev, intel_dp);
507 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 508}
509
773538e8
VS		 510void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
511{
512 struct drm_device *dev = dev_priv->dev;
513 struct intel_encoder *encoder;
514
666a4537 515 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)))
773538e8
VS		 516 return;
517
518 /*
519 * We can't grab pps_mutex here due to deadlock with power_domain
520 * mutex when power_domain functions are called while holding pps_mutex.
521 * That also means that in order to use pps_pipe the code needs to
522 * hold both a power domain reference and pps_mutex, and the power domain
523 * reference get/put must be done while _not_ holding pps_mutex.
524 * pps_{lock,unlock}() do these steps in the correct order, so one
525 * should use them always.
526 */
527
19c8054c 528 for_each_intel_encoder(dev, encoder) {
773538e8
VS		 529 struct intel_dp *intel_dp;
530
531 if (encoder->type != INTEL_OUTPUT_EDP)
532 continue;
533
534 intel_dp = enc_to_intel_dp(&encoder->base);
535 intel_dp->pps_pipe = INVALID_PIPE;
536 }
bf13e81b
JN		 537}
538
f0f59a00
VS		 539static i915_reg_t
540_pp_ctrl_reg(struct intel_dp *intel_dp)
bf13e81b
JN		 541{
542 struct drm_device *dev = intel_dp_to_dev(intel_dp);
543
b0a08bec
VK		 544 if (IS_BROXTON(dev))
545 return BXT_PP_CONTROL(0);
546 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 547 return PCH_PP_CONTROL;
548 else
549 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
550}
551
f0f59a00
VS		 552static i915_reg_t
553_pp_stat_reg(struct intel_dp *intel_dp)
bf13e81b
JN		 554{
555 struct drm_device *dev = intel_dp_to_dev(intel_dp);
556
b0a08bec
VK		 557 if (IS_BROXTON(dev))
558 return BXT_PP_STATUS(0);
559 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 560 return PCH_PP_STATUS;
561 else
562 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
563}
564
01527b31
CT		 565/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
566 This function only applicable when panel PM state is not to be tracked */
567static int edp_notify_handler(struct notifier_block *this, unsigned long code,
568 void *unused)
569{
570 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
571 edp_notifier);
572 struct drm_device *dev = intel_dp_to_dev(intel_dp);
573 struct drm_i915_private *dev_priv = dev->dev_private;
01527b31
CT		 574
575 if (!is_edp(intel_dp) || code != SYS_RESTART)
576 return 0;
577
773538e8 578 pps_lock(intel_dp);
e39b999a 579
666a4537 580 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e39b999a 581 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
f0f59a00 582 i915_reg_t pp_ctrl_reg, pp_div_reg;
649636ef 583 u32 pp_div;
e39b999a 584
01527b31
CT		 585 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
586 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
587 pp_div = I915_READ(pp_div_reg);
588 pp_div &= PP_REFERENCE_DIVIDER_MASK;
589
590 /* 0x1F write to PP_DIV_REG sets max cycle delay */
591 I915_WRITE(pp_div_reg, pp_div | 0x1F);
592 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
593 msleep(intel_dp->panel_power_cycle_delay);
594 }
595
773538e8 596 pps_unlock(intel_dp);
e39b999a 597
01527b31
CT		 598 return 0;
599}
600
4be73780 601static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 602{
30add22d 603 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 604 struct drm_i915_private *dev_priv = dev->dev_private;
605
e39b999a
VS		 606 lockdep_assert_held(&dev_priv->pps_mutex);
607
666a4537 608 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 609 intel_dp->pps_pipe == INVALID_PIPE)
610 return false;
611
bf13e81b 612 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 613}
614
4be73780 615static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 616{
30add22d 617 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 618 struct drm_i915_private *dev_priv = dev->dev_private;
619
e39b999a
VS		 620 lockdep_assert_held(&dev_priv->pps_mutex);
621
666a4537 622 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 623 intel_dp->pps_pipe == INVALID_PIPE)
624 return false;
625
773538e8 626 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 627}
628
9b984dae
KP		 629static void
630intel_dp_check_edp(struct intel_dp *intel_dp)
631{
30add22d 632 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 633 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 634
9b984dae
KP		 635 if (!is_edp(intel_dp))
636 return;
453c5420 637
4be73780 638 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 639 WARN(1, "eDP powered off while attempting aux channel communication.\n");
640 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 641 I915_READ(_pp_stat_reg(intel_dp)),
642 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 643 }
644}
645
9ee32fea
DV		 646static uint32_t
647intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
648{
649 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
650 struct drm_device *dev = intel_dig_port->base.base.dev;
651 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 652 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 653 uint32_t status;
654 bool done;
655
ef04f00d 656#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 657 if (has_aux_irq)
b18ac466 658 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 659 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 660 else
661 done = wait_for_atomic(C, 10) == 0;
662 if (!done)
663 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
664 has_aux_irq);
665#undef C
666
667 return status;
668}
669
6ffb1be7 670static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 671{
174edf1f 672 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
e7dc33f3 673 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
9ee32fea 674
a457f54b
VS		 675 if (index)
676 return 0;
677
ec5b01dd
DL		 678 /*
679 * The clock divider is based off the hrawclk, and would like to run at
a457f54b 680 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
a4fc5ed6 681 */
a457f54b 682 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 683}
684
685static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
686{
687 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 688 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd
DL		 689
690 if (index)
691 return 0;
692
a457f54b
VS		 693 /*
694 * The clock divider is based off the cdclk or PCH rawclk, and would
695 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
696 * divide by 2000 and use that
697 */
e7dc33f3 698 if (intel_dig_port->port == PORT_A)
fce18c4c 699 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
e7dc33f3
VS		 700 else
701 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 702}
703
704static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
705{
706 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 707 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd 708
a457f54b 709 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
2c55c336 710 /* Workaround for non-ULT HSW */
bc86625a
CW		 711 switch (index) {
712 case 0: return 63;
713 case 1: return 72;
714 default: return 0;
715 }
2c55c336 716 }
a457f54b
VS		 717
718 return ilk_get_aux_clock_divider(intel_dp, index);
b84a1cf8
RV		 719}
720
b6b5e383
DL		 721static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
722{
723 /*
724 * SKL doesn't need us to program the AUX clock divider (Hardware will
725 * derive the clock from CDCLK automatically). We still implement the
726 * get_aux_clock_divider vfunc to plug-in into the existing code.
727 */
728 return index ? 0 : 1;
729}
730
6ffb1be7
VS		 731static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
732 bool has_aux_irq,
733 int send_bytes,
734 uint32_t aux_clock_divider)
5ed12a19
DL		 735{
736 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
737 struct drm_device *dev = intel_dig_port->base.base.dev;
738 uint32_t precharge, timeout;
739
740 if (IS_GEN6(dev))
741 precharge = 3;
742 else
743 precharge = 5;
744
f3c6a3a7 745 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
5ed12a19
DL		 746 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
747 else
748 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
749
750 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 751 DP_AUX_CH_CTL_DONE |
5ed12a19 752 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 753 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 754 timeout |
788d4433 755 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 756 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
757 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 758 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 759}
760
b9ca5fad
DL		 761static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
762 bool has_aux_irq,
763 int send_bytes,
764 uint32_t unused)
765{
766 return DP_AUX_CH_CTL_SEND_BUSY |
767 DP_AUX_CH_CTL_DONE |
768 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
769 DP_AUX_CH_CTL_TIME_OUT_ERROR |
770 DP_AUX_CH_CTL_TIME_OUT_1600us |
771 DP_AUX_CH_CTL_RECEIVE_ERROR |
772 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
773 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
774}
775
b84a1cf8
RV		 776static int
777intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 778 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 779 uint8_t *recv, int recv_size)
780{
781 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
782 struct drm_device *dev = intel_dig_port->base.base.dev;
783 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 784 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
bc86625a 785 uint32_t aux_clock_divider;
b84a1cf8
RV		 786 int i, ret, recv_bytes;
787 uint32_t status;
5ed12a19 788 int try, clock = 0;
4e6b788c 789 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 790 bool vdd;
791
773538e8 792 pps_lock(intel_dp);
e39b999a 793
72c3500a
VS		 794 /*
795 * We will be called with VDD already enabled for dpcd/edid/oui reads.
796 * In such cases we want to leave VDD enabled and it's up to upper layers
797 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
798 * ourselves.
799 */
1e0560e0 800 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 801
802 /* dp aux is extremely sensitive to irq latency, hence request the
803 * lowest possible wakeup latency and so prevent the cpu from going into
804 * deep sleep states.
805 */
806 pm_qos_update_request(&dev_priv->pm_qos, 0);
807
808 intel_dp_check_edp(intel_dp);
5eb08b69 809
11bee43e
JB		 810 /* Try to wait for any previous AUX channel activity */
811 for (try = 0; try < 3; try++) {
ef04f00d 812 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 813 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
814 break;
815 msleep(1);
816 }
817
818 if (try == 3) {
02196c77
MK		 819 static u32 last_status = -1;
820 const u32 status = I915_READ(ch_ctl);
821
822 if (status != last_status) {
823 WARN(1, "dp_aux_ch not started status 0x%08x\n",
824 status);
825 last_status = status;
826 }
827
9ee32fea
DV		 828 ret = -EBUSY;
829 goto out;
4f7f7b7e
CW		 830 }
831
46a5ae9f
PZ		 832 /* Only 5 data registers! */
833 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
834 ret = -E2BIG;
835 goto out;
836 }
837
ec5b01dd 838 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 839 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
840 has_aux_irq,
841 send_bytes,
842 aux_clock_divider);
5ed12a19 843
bc86625a
CW		 844 /* Must try at least 3 times according to DP spec */
845 for (try = 0; try < 5; try++) {
846 /* Load the send data into the aux channel data registers */
847 for (i = 0; i < send_bytes; i += 4)
330e20ec 848 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
a4f1289e
RV		 849 intel_dp_pack_aux(send + i,
850 send_bytes - i));
bc86625a
CW		 851
852 /* Send the command and wait for it to complete */
5ed12a19 853 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 854
855 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
856
857 /* Clear done status and any errors */
858 I915_WRITE(ch_ctl,
859 status |
860 DP_AUX_CH_CTL_DONE |
861 DP_AUX_CH_CTL_TIME_OUT_ERROR |
862 DP_AUX_CH_CTL_RECEIVE_ERROR);
863
74ebf294 864 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 865 continue;
74ebf294
TP		 866
867 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
868 * 400us delay required for errors and timeouts
869 * Timeout errors from the HW already meet this
870 * requirement so skip to next iteration
871 */
872 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
873 usleep_range(400, 500);
bc86625a 874 continue;
74ebf294 875 }
bc86625a 876 if (status & DP_AUX_CH_CTL_DONE)
e058c945 877 goto done;
bc86625a 878 }
a4fc5ed6
KP		 879 }
880
a4fc5ed6 881 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 882 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 883 ret = -EBUSY;
884 goto out;
a4fc5ed6
KP		 885 }
886
e058c945 887done:
a4fc5ed6
KP		 888 /* Check for timeout or receive error.
889 * Timeouts occur when the sink is not connected
890 */
a5b3da54 891 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 892 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 893 ret = -EIO;
894 goto out;
a5b3da54 895 }
1ae8c0a5
KP		 896
897 /* Timeouts occur when the device isn't connected, so they're
898 * "normal" -- don't fill the kernel log with these */
a5b3da54 899 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 900 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 901 ret = -ETIMEDOUT;
902 goto out;
a4fc5ed6
KP		 903 }
904
905 /* Unload any bytes sent back from the other side */
906 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
907 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
14e01889
RV		 908
909 /*
910 * By BSpec: "Message sizes of 0 or >20 are not allowed."
911 * We have no idea of what happened so we return -EBUSY so
912 * drm layer takes care for the necessary retries.
913 */
914 if (recv_bytes == 0 || recv_bytes > 20) {
915 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
916 recv_bytes);
917 /*
918 * FIXME: This patch was created on top of a series that
919 * organize the retries at drm level. There EBUSY should
920 * also take care for 1ms wait before retrying.
921 * That aux retries re-org is still needed and after that is
922 * merged we remove this sleep from here.
923 */
924 usleep_range(1000, 1500);
925 ret = -EBUSY;
926 goto out;
927 }
928
a4fc5ed6
KP		 929 if (recv_bytes > recv_size)
930 recv_bytes = recv_size;
0206e353 931
4f7f7b7e 932 for (i = 0; i < recv_bytes; i += 4)
330e20ec 933 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
a4f1289e 934 recv + i, recv_bytes - i);
a4fc5ed6 935
9ee32fea
DV		 936 ret = recv_bytes;
937out:
938 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
939
884f19e9
JN		 940 if (vdd)
941 edp_panel_vdd_off(intel_dp, false);
942
773538e8 943 pps_unlock(intel_dp);
e39b999a 944
9ee32fea 945 return ret;
a4fc5ed6
KP		 946}
947
a6c8aff0
JN		 948#define BARE_ADDRESS_SIZE 3
949#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 950static ssize_t
951intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 952{
9d1a1031
JN		 953 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
954 uint8_t txbuf[20], rxbuf[20];
955 size_t txsize, rxsize;
a4fc5ed6 956 int ret;
a4fc5ed6 957
d2d9cbbd
VS		 958 txbuf[0] = (msg->request << 4) |
959 ((msg->address >> 16) & 0xf);
960 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 961 txbuf[2] = msg->address & 0xff;
962 txbuf[3] = msg->size - 1;
46a5ae9f 963
9d1a1031
JN		 964 switch (msg->request & ~DP_AUX_I2C_MOT) {
965 case DP_AUX_NATIVE_WRITE:
966 case DP_AUX_I2C_WRITE:
c1e74122 967 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
a6c8aff0 968 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 969 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 970
9d1a1031
JN		 971 if (WARN_ON(txsize > 20))
972 return -E2BIG;
a4fc5ed6 973
d81a67cc
ID		 974 if (msg->buffer)
975 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
976 else
977 WARN_ON(msg->size);
a4fc5ed6 978
9d1a1031
JN		 979 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
980 if (ret > 0) {
981 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 982
a1ddefd8
JN		 983 if (ret > 1) {
984 /* Number of bytes written in a short write. */
985 ret = clamp_t(int, rxbuf[1], 0, msg->size);
986 } else {
987 /* Return payload size. */
988 ret = msg->size;
989 }
9d1a1031
JN		 990 }
991 break;
46a5ae9f 992
9d1a1031
JN		 993 case DP_AUX_NATIVE_READ:
994 case DP_AUX_I2C_READ:
a6c8aff0 995 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 996 rxsize = msg->size + 1;
a4fc5ed6 997
9d1a1031
JN		 998 if (WARN_ON(rxsize > 20))
999 return -E2BIG;
a4fc5ed6 1000
9d1a1031
JN		 1001 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1002 if (ret > 0) {
1003 msg->reply = rxbuf[0] >> 4;
1004 /*
1005 * Assume happy day, and copy the data. The caller is
1006 * expected to check msg->reply before touching it.
1007 *
1008 * Return payload size.
1009 */
1010 ret--;
1011 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1012 }
9d1a1031
JN		 1013 break;
1014
1015 default:
1016 ret = -EINVAL;
1017 break;
a4fc5ed6 1018 }
f51a44b9 1019
9d1a1031 1020 return ret;
a4fc5ed6
KP		 1021}
1022
f0f59a00
VS		 1023static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1024 enum port port)
da00bdcf
VS		 1025{
1026 switch (port) {
1027 case PORT_B:
1028 case PORT_C:
1029 case PORT_D:
1030 return DP_AUX_CH_CTL(port);
1031 default:
1032 MISSING_CASE(port);
1033 return DP_AUX_CH_CTL(PORT_B);
1034 }
1035}
1036
f0f59a00
VS		 1037static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1038 enum port port, int index)
330e20ec
VS		 1039{
1040 switch (port) {
1041 case PORT_B:
1042 case PORT_C:
1043 case PORT_D:
1044 return DP_AUX_CH_DATA(port, index);
1045 default:
1046 MISSING_CASE(port);
1047 return DP_AUX_CH_DATA(PORT_B, index);
1048 }
1049}
1050
f0f59a00
VS		 1051static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1052 enum port port)
da00bdcf
VS		 1053{
1054 switch (port) {
1055 case PORT_A:
1056 return DP_AUX_CH_CTL(port);
1057 case PORT_B:
1058 case PORT_C:
1059 case PORT_D:
1060 return PCH_DP_AUX_CH_CTL(port);
1061 default:
1062 MISSING_CASE(port);
1063 return DP_AUX_CH_CTL(PORT_A);
1064 }
1065}
1066
f0f59a00
VS		 1067static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1068 enum port port, int index)
330e20ec
VS		 1069{
1070 switch (port) {
1071 case PORT_A:
1072 return DP_AUX_CH_DATA(port, index);
1073 case PORT_B:
1074 case PORT_C:
1075 case PORT_D:
1076 return PCH_DP_AUX_CH_DATA(port, index);
1077 default:
1078 MISSING_CASE(port);
1079 return DP_AUX_CH_DATA(PORT_A, index);
1080 }
1081}
1082
da00bdcf
VS		 1083/*
1084 * On SKL we don't have Aux for port E so we rely
1085 * on VBT to set a proper alternate aux channel.
1086 */
1087static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1088{
1089 const struct ddi_vbt_port_info *info =
1090 &dev_priv->vbt.ddi_port_info[PORT_E];
1091
1092 switch (info->alternate_aux_channel) {
1093 case DP_AUX_A:
1094 return PORT_A;
1095 case DP_AUX_B:
1096 return PORT_B;
1097 case DP_AUX_C:
1098 return PORT_C;
1099 case DP_AUX_D:
1100 return PORT_D;
1101 default:
1102 MISSING_CASE(info->alternate_aux_channel);
1103 return PORT_A;
1104 }
1105}
1106
f0f59a00
VS		 1107static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1108 enum port port)
da00bdcf
VS		 1109{
1110 if (port == PORT_E)
1111 port = skl_porte_aux_port(dev_priv);
1112
1113 switch (port) {
1114 case PORT_A:
1115 case PORT_B:
1116 case PORT_C:
1117 case PORT_D:
1118 return DP_AUX_CH_CTL(port);
1119 default:
1120 MISSING_CASE(port);
1121 return DP_AUX_CH_CTL(PORT_A);
1122 }
1123}
1124
f0f59a00
VS		 1125static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1126 enum port port, int index)
330e20ec
VS		 1127{
1128 if (port == PORT_E)
1129 port = skl_porte_aux_port(dev_priv);
1130
1131 switch (port) {
1132 case PORT_A:
1133 case PORT_B:
1134 case PORT_C:
1135 case PORT_D:
1136 return DP_AUX_CH_DATA(port, index);
1137 default:
1138 MISSING_CASE(port);
1139 return DP_AUX_CH_DATA(PORT_A, index);
1140 }
1141}
1142
f0f59a00
VS		 1143static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1144 enum port port)
330e20ec
VS		 1145{
1146 if (INTEL_INFO(dev_priv)->gen >= 9)
1147 return skl_aux_ctl_reg(dev_priv, port);
1148 else if (HAS_PCH_SPLIT(dev_priv))
1149 return ilk_aux_ctl_reg(dev_priv, port);
1150 else
1151 return g4x_aux_ctl_reg(dev_priv, port);
1152}
1153
f0f59a00
VS		 1154static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1155 enum port port, int index)
330e20ec
VS		 1156{
1157 if (INTEL_INFO(dev_priv)->gen >= 9)
1158 return skl_aux_data_reg(dev_priv, port, index);
1159 else if (HAS_PCH_SPLIT(dev_priv))
1160 return ilk_aux_data_reg(dev_priv, port, index);
1161 else
1162 return g4x_aux_data_reg(dev_priv, port, index);
1163}
1164
1165static void intel_aux_reg_init(struct intel_dp *intel_dp)
1166{
1167 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1168 enum port port = dp_to_dig_port(intel_dp)->port;
1169 int i;
1170
1171 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1172 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1173 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1174}
1175
9d1a1031 1176static void
a121f4e5
VS		 1177intel_dp_aux_fini(struct intel_dp *intel_dp)
1178{
1179 drm_dp_aux_unregister(&intel_dp->aux);
1180 kfree(intel_dp->aux.name);
1181}
1182
1183static int
9d1a1031
JN		 1184intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1185{
33ad6626
JN		 1186 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1187 enum port port = intel_dig_port->port;
ab2c0672
DA		 1188 int ret;
1189
330e20ec 1190 intel_aux_reg_init(intel_dp);
8316f337 1191
a121f4e5
VS		 1192 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1193 if (!intel_dp->aux.name)
1194 return -ENOMEM;
1195
4d32c0d8 1196 intel_dp->aux.dev = connector->base.kdev;
9d1a1031 1197 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1198
a121f4e5
VS		 1199 DRM_DEBUG_KMS("registering %s bus for %s\n",
1200 intel_dp->aux.name,
0b99836f 1201 connector->base.kdev->kobj.name);
8316f337 1202
4f71d0cb 1203 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1204 if (ret < 0) {
4f71d0cb 1205 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
a121f4e5
VS		 1206 intel_dp->aux.name, ret);
1207 kfree(intel_dp->aux.name);
1208 return ret;
ab2c0672 1209 }
8a5e6aeb 1210
a121f4e5 1211 return 0;
a4fc5ed6
KP		 1212}
1213
80f65de3
ID		 1214static void
1215intel_dp_connector_unregister(struct intel_connector *intel_connector)
1216{
1217 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1218
4d32c0d8 1219 intel_dp_aux_fini(intel_dp);
80f65de3
ID		 1220 intel_connector_unregister(intel_connector);
1221}
1222
fc0f8e25 1223static int
12f6a2e2 1224intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1225{
94ca719e
VS		 1226 if (intel_dp->num_sink_rates) {
1227 *sink_rates = intel_dp->sink_rates;
1228 return intel_dp->num_sink_rates;
fc0f8e25 1229 }
12f6a2e2
VS		 1230
1231 *sink_rates = default_rates;
1232
1233 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1234}
1235
e588fa18 1236bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
ed63baaf 1237{
e588fa18
ACO		 1238 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1239 struct drm_device *dev = dig_port->base.base.dev;
1240
ed63baaf 1241 /* WaDisableHBR2:skl */
e87a005d 1242 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
ed63baaf
TS		 1243 return false;
1244
1245 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1246 (INTEL_INFO(dev)->gen >= 9))
1247 return true;
1248 else
1249 return false;
1250}
1251
a8f3ef61 1252static int
e588fa18 1253intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
a8f3ef61 1254{
e588fa18
ACO		 1255 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1256 struct drm_device *dev = dig_port->base.base.dev;
af7080f5
TS		 1257 int size;
1258
64987fc5
SJ		 1259 if (IS_BROXTON(dev)) {
1260 *source_rates = bxt_rates;
af7080f5 1261 size = ARRAY_SIZE(bxt_rates);
ef11bdb3 1262 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
637a9c63 1263 *source_rates = skl_rates;
af7080f5
TS		 1264 size = ARRAY_SIZE(skl_rates);
1265 } else {
1266 *source_rates = default_rates;
1267 size = ARRAY_SIZE(default_rates);
a8f3ef61 1268 }
636280ba 1269
ed63baaf 1270 /* This depends on the fact that 5.4 is last value in the array */
e588fa18 1271 if (!intel_dp_source_supports_hbr2(intel_dp))
af7080f5 1272 size--;
636280ba 1273
af7080f5 1274 return size;
a8f3ef61
SJ		 1275}
1276
c6bb3538
DV		 1277static void
1278intel_dp_set_clock(struct intel_encoder *encoder,
840b32b7 1279 struct intel_crtc_state *pipe_config)
c6bb3538
DV		 1280{
1281 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1282 const struct dp_link_dpll *divisor = NULL;
1283 int i, count = 0;
c6bb3538
DV		 1284
1285 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1286 divisor = gen4_dpll;
1287 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1288 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1289 divisor = pch_dpll;
1290 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1291 } else if (IS_CHERRYVIEW(dev)) {
1292 divisor = chv_dpll;
1293 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1294 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1295 divisor = vlv_dpll;
1296 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1297 }
9dd4ffdf
CML		 1298
1299 if (divisor && count) {
1300 for (i = 0; i < count; i++) {
840b32b7 1301 if (pipe_config->port_clock == divisor[i].clock) {
9dd4ffdf
CML		 1302 pipe_config->dpll = divisor[i].dpll;
1303 pipe_config->clock_set = true;
1304 break;
1305 }
1306 }
c6bb3538
DV		 1307 }
1308}
1309
2ecae76a
VS		 1310static int intersect_rates(const int *source_rates, int source_len,
1311 const int *sink_rates, int sink_len,
94ca719e 1312 int *common_rates)
a8f3ef61
SJ		 1313{
1314 int i = 0, j = 0, k = 0;
1315
a8f3ef61
SJ		 1316 while (i < source_len && j < sink_len) {
1317 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1318 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1319 return k;
94ca719e 1320 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1321 ++k;
1322 ++i;
1323 ++j;
1324 } else if (source_rates[i] < sink_rates[j]) {
1325 ++i;
1326 } else {
1327 ++j;
1328 }
1329 }
1330 return k;
1331}
1332
94ca719e
VS		 1333static int intel_dp_common_rates(struct intel_dp *intel_dp,
1334 int *common_rates)
2ecae76a 1335{
2ecae76a
VS		 1336 const int *source_rates, *sink_rates;
1337 int source_len, sink_len;
1338
1339 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
e588fa18 1340 source_len = intel_dp_source_rates(intel_dp, &source_rates);
2ecae76a
VS		 1341
1342 return intersect_rates(source_rates, source_len,
1343 sink_rates, sink_len,
94ca719e 1344 common_rates);
2ecae76a
VS		 1345}
1346
0336400e
VS		 1347static void snprintf_int_array(char *str, size_t len,
1348 const int *array, int nelem)
1349{
1350 int i;
1351
1352 str[0] = '\0';
1353
1354 for (i = 0; i < nelem; i++) {
b2f505be 1355 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1356 if (r >= len)
1357 return;
1358 str += r;
1359 len -= r;
1360 }
1361}
1362
1363static void intel_dp_print_rates(struct intel_dp *intel_dp)
1364{
0336400e 1365 const int *source_rates, *sink_rates;
94ca719e
VS		 1366 int source_len, sink_len, common_len;
1367 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1368 char str[128]; /* FIXME: too big for stack? */
1369
1370 if ((drm_debug & DRM_UT_KMS) == 0)
1371 return;
1372
e588fa18 1373 source_len = intel_dp_source_rates(intel_dp, &source_rates);
0336400e
VS		 1374 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1375 DRM_DEBUG_KMS("source rates: %s\n", str);
1376
1377 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1378 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1379 DRM_DEBUG_KMS("sink rates: %s\n", str);
1380
94ca719e
VS		 1381 common_len = intel_dp_common_rates(intel_dp, common_rates);
1382 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1383 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1384}
1385
f4896f15 1386static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1387{
1388 int i = 0;
1389
1390 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1391 if (find == rates[i])
1392 break;
1393
1394 return i;
1395}
1396
50fec21a
VS		 1397int
1398intel_dp_max_link_rate(struct intel_dp *intel_dp)
1399{
1400 int rates[DP_MAX_SUPPORTED_RATES] = {};
1401 int len;
1402
94ca719e 1403 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1404 if (WARN_ON(len <= 0))
1405 return 162000;
1406
1407 return rates[rate_to_index(0, rates) - 1];
1408}
1409
ed4e9c1d
VS		 1410int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1411{
94ca719e 1412 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1413}
1414
94223d04
ACO		 1415void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1416 uint8_t *link_bw, uint8_t *rate_select)
04a60f9f
VS		 1417{
1418 if (intel_dp->num_sink_rates) {
1419 *link_bw = 0;
1420 *rate_select =
1421 intel_dp_rate_select(intel_dp, port_clock);
1422 } else {
1423 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1424 *rate_select = 0;
1425 }
1426}
1427
00c09d70 1428bool
5bfe2ac0 1429intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1430 struct intel_crtc_state *pipe_config)
a4fc5ed6 1431{
5bfe2ac0 1432 struct drm_device *dev = encoder->base.dev;
36008365 1433 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1434 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1435 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1436 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1437 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1438 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1439 int lane_count, clock;
56071a20 1440 int min_lane_count = 1;
eeb6324d 1441 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1442 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1443 int min_clock = 0;
a8f3ef61 1444 int max_clock;
083f9560 1445 int bpp, mode_rate;
ff9a6750 1446 int link_avail, link_clock;
94ca719e
VS		 1447 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1448 int common_len;
04a60f9f 1449 uint8_t link_bw, rate_select;
a8f3ef61 1450
94ca719e 1451 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1452
1453 /* No common link rates between source and sink */
94ca719e 1454 WARN_ON(common_len <= 0);
a8f3ef61 1455
94ca719e 1456 max_clock = common_len - 1;
a4fc5ed6 1457
bc7d38a4 1458 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1459 pipe_config->has_pch_encoder = true;
1460
03afc4a2 1461 pipe_config->has_dp_encoder = true;
f769cd24 1462 pipe_config->has_drrs = false;
9fcb1704 1463 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1464
dd06f90e
JN		 1465 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1466 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1467 adjusted_mode);
a1b2278e
CK		 1468
1469 if (INTEL_INFO(dev)->gen >= 9) {
1470 int ret;
e435d6e5 1471 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1472 if (ret)
1473 return ret;
1474 }
1475
b5667627 1476 if (HAS_GMCH_DISPLAY(dev))
2dd24552
JB		 1477 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1478 intel_connector->panel.fitting_mode);
1479 else
b074cec8
JB		 1480 intel_pch_panel_fitting(intel_crtc, pipe_config,
1481 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1482 }
1483
cb1793ce 1484 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1485 return false;
1486
083f9560 1487 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1488 "max bw %d pixel clock %iKHz\n",
94ca719e 1489 max_lane_count, common_rates[max_clock],
241bfc38 1490 adjusted_mode->crtc_clock);
083f9560 1491
36008365
DV		 1492 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1493 * bpc in between. */
3e7ca985 1494 bpp = pipe_config->pipe_bpp;
56071a20 1495 if (is_edp(intel_dp)) {
22ce5628
TS		 1496
1497 /* Get bpp from vbt only for panels that dont have bpp in edid */
1498 if (intel_connector->base.display_info.bpc == 0 &&
6aa23e65 1499 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
56071a20 1500 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
6aa23e65
JN		 1501 dev_priv->vbt.edp.bpp);
1502 bpp = dev_priv->vbt.edp.bpp;
56071a20
JN		 1503 }
1504
344c5bbc
JN		 1505 /*
1506 * Use the maximum clock and number of lanes the eDP panel
1507 * advertizes being capable of. The panels are generally
1508 * designed to support only a single clock and lane
1509 * configuration, and typically these values correspond to the
1510 * native resolution of the panel.
1511 */
1512 min_lane_count = max_lane_count;
1513 min_clock = max_clock;
7984211e 1514 }
657445fe 1515
36008365 1516 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1517 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1518 bpp);
36008365 1519
c6930992 1520 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1521 for (lane_count = min_lane_count;
1522 lane_count <= max_lane_count;
1523 lane_count <<= 1) {
1524
94ca719e 1525 link_clock = common_rates[clock];
36008365
DV		 1526 link_avail = intel_dp_max_data_rate(link_clock,
1527 lane_count);
1528
1529 if (mode_rate <= link_avail) {
1530 goto found;
1531 }
1532 }
1533 }
1534 }
c4867936 1535
36008365 1536 return false;
3685a8f3 1537
36008365 1538found:
55bc60db
VS		 1539 if (intel_dp->color_range_auto) {
1540 /*
1541 * See:
1542 * CEA-861-E - 5.1 Default Encoding Parameters
1543 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1544 */
0f2a2a75
VS		 1545 pipe_config->limited_color_range =
1546 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1547 } else {
1548 pipe_config->limited_color_range =
1549 intel_dp->limited_color_range;
55bc60db
VS		 1550 }
1551
90a6b7b0 1552 pipe_config->lane_count = lane_count;
a8f3ef61 1553
657445fe 1554 pipe_config->pipe_bpp = bpp;
94ca719e 1555 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1556
04a60f9f
VS		 1557 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1558 &link_bw, &rate_select);
1559
1560 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1561 link_bw, rate_select, pipe_config->lane_count,
ff9a6750 1562 pipe_config->port_clock, bpp);
36008365
DV		 1563 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1564 mode_rate, link_avail);
a4fc5ed6 1565
03afc4a2 1566 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1567 adjusted_mode->crtc_clock,
1568 pipe_config->port_clock,
03afc4a2 1569 &pipe_config->dp_m_n);
9d1a455b 1570
439d7ac0 1571 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1572 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1573 pipe_config->has_drrs = true;
439d7ac0
PB		 1574 intel_link_compute_m_n(bpp, lane_count,
1575 intel_connector->panel.downclock_mode->clock,
1576 pipe_config->port_clock,
1577 &pipe_config->dp_m2_n2);
1578 }
1579
a3c988ea 1580 if (!HAS_DDI(dev))
840b32b7 1581 intel_dp_set_clock(encoder, pipe_config);
c6bb3538 1582
03afc4a2 1583 return true;
a4fc5ed6
KP		 1584}
1585
901c2daf
VS		 1586void intel_dp_set_link_params(struct intel_dp *intel_dp,
1587 const struct intel_crtc_state *pipe_config)
1588{
1589 intel_dp->link_rate = pipe_config->port_clock;
1590 intel_dp->lane_count = pipe_config->lane_count;
1591}
1592
8ac33ed3 1593static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1594{
b934223d 1595 struct drm_device *dev = encoder->base.dev;
417e822d 1596 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1597 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1598 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1599 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
7c5f93b0 1600 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1601
901c2daf
VS		 1602 intel_dp_set_link_params(intel_dp, crtc->config);
1603
417e822d 1604 /*
1a2eb460 1605 * There are four kinds of DP registers:
417e822d
KP		 1606 *
1607 * IBX PCH
1a2eb460
KP		 1608 * SNB CPU
1609 * IVB CPU
417e822d
KP		 1610 * CPT PCH
1611 *
1612 * IBX PCH and CPU are the same for almost everything,
1613 * except that the CPU DP PLL is configured in this
1614 * register
1615 *
1616 * CPT PCH is quite different, having many bits moved
1617 * to the TRANS_DP_CTL register instead. That
1618 * configuration happens (oddly) in ironlake_pch_enable
1619 */
9c9e7927 1620
417e822d
KP		 1621 /* Preserve the BIOS-computed detected bit. This is
1622 * supposed to be read-only.
1623 */
1624 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1625
417e822d 1626 /* Handle DP bits in common between all three register formats */
417e822d 1627 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
90a6b7b0 1628 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
a4fc5ed6 1629
417e822d 1630 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1631
39e5fa88 1632 if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1633 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1634 intel_dp->DP |= DP_SYNC_HS_HIGH;
1635 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1636 intel_dp->DP |= DP_SYNC_VS_HIGH;
1637 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1638
6aba5b6c 1639 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1640 intel_dp->DP |= DP_ENHANCED_FRAMING;
1641
7c62a164 1642 intel_dp->DP |= crtc->pipe << 29;
39e5fa88 1643 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
e3ef4479
VS		 1644 u32 trans_dp;
1645
39e5fa88 1646 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1647
1648 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1649 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1650 trans_dp |= TRANS_DP_ENH_FRAMING;
1651 else
1652 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1653 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1654 } else {
0f2a2a75 1655 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 1656 !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
0f2a2a75 1657 intel_dp->DP |= DP_COLOR_RANGE_16_235;
417e822d
KP		 1658
1659 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1660 intel_dp->DP |= DP_SYNC_HS_HIGH;
1661 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1662 intel_dp->DP |= DP_SYNC_VS_HIGH;
1663 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1664
6aba5b6c 1665 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1666 intel_dp->DP |= DP_ENHANCED_FRAMING;
1667
39e5fa88 1668 if (IS_CHERRYVIEW(dev))
44f37d1f 1669 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1670 else if (crtc->pipe == PIPE_B)
1671 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1672 }
a4fc5ed6
KP		 1673}
1674
ffd6749d
PZ		 1675#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1676#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1677
1a5ef5b7
PZ		 1678#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1679#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1680
ffd6749d
PZ		 1681#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1682#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1683
4be73780 1684static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1685 u32 mask,
1686 u32 value)
bd943159 1687{
30add22d 1688 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1689 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 1690 i915_reg_t pp_stat_reg, pp_ctrl_reg;
453c5420 1691
e39b999a
VS		 1692 lockdep_assert_held(&dev_priv->pps_mutex);
1693
bf13e81b
JN		 1694 pp_stat_reg = _pp_stat_reg(intel_dp);
1695 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1696
99ea7127 1697 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1698 mask, value,
1699 I915_READ(pp_stat_reg),
1700 I915_READ(pp_ctrl_reg));
32ce697c 1701
3f177625
TU		 1702 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value,
1703 5 * USEC_PER_SEC, 10 * USEC_PER_MSEC))
99ea7127 1704 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1705 I915_READ(pp_stat_reg),
1706 I915_READ(pp_ctrl_reg));
54c136d4
CW		 1707
1708 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1709}
32ce697c 1710
4be73780 1711static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1712{
1713 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1714 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1715}
1716
4be73780 1717static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1718{
1719 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1720 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1721}
1722
4be73780 1723static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127 1724{
d28d4731
AK		 1725 ktime_t panel_power_on_time;
1726 s64 panel_power_off_duration;
1727
99ea7127 1728 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c 1729
d28d4731
AK		 1730 /* take the difference of currrent time and panel power off time
1731 * and then make panel wait for t11_t12 if needed. */
1732 panel_power_on_time = ktime_get_boottime();
1733 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1734
dce56b3c
PZ		 1735 /* When we disable the VDD override bit last we have to do the manual
1736 * wait. */
d28d4731
AK		 1737 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1738 wait_remaining_ms_from_jiffies(jiffies,
1739 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
dce56b3c 1740
4be73780 1741 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1742}
1743
4be73780 1744static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1745{
1746 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1747 intel_dp->backlight_on_delay);
1748}
1749
4be73780 1750static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1751{
1752 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1753 intel_dp->backlight_off_delay);
1754}
99ea7127 1755
832dd3c1
KP		 1756/* Read the current pp_control value, unlocking the register if it
1757 * is locked
1758 */
1759
453c5420 1760static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1761{
453c5420
JB		 1762 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1763 struct drm_i915_private *dev_priv = dev->dev_private;
1764 u32 control;
832dd3c1 1765
e39b999a
VS		 1766 lockdep_assert_held(&dev_priv->pps_mutex);
1767
bf13e81b 1768 control = I915_READ(_pp_ctrl_reg(intel_dp));
b0a08bec
VK		 1769 if (!IS_BROXTON(dev)) {
1770 control &= ~PANEL_UNLOCK_MASK;
1771 control |= PANEL_UNLOCK_REGS;
1772 }
832dd3c1 1773 return control;
bd943159
KP		 1774}
1775
951468f3
VS		 1776/*
1777 * Must be paired with edp_panel_vdd_off().
1778 * Must hold pps_mutex around the whole on/off sequence.
1779 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1780 */
1e0560e0 1781static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1782{
30add22d 1783 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1784 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1785 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1786 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1787 enum intel_display_power_domain power_domain;
5d613501 1788 u32 pp;
f0f59a00 1789 i915_reg_t pp_stat_reg, pp_ctrl_reg;
adddaaf4 1790 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1791
e39b999a
VS		 1792 lockdep_assert_held(&dev_priv->pps_mutex);
1793
97af61f5 1794 if (!is_edp(intel_dp))
adddaaf4 1795 return false;
bd943159 1796
2c623c11 1797 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1798 intel_dp->want_panel_vdd = true;
99ea7127 1799
4be73780 1800 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1801 return need_to_disable;
b0665d57 1802
25f78f58 1803 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 1804 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1805
3936fcf4
VS		 1806 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1807 port_name(intel_dig_port->port));
bd943159 1808
4be73780
DV		 1809 if (!edp_have_panel_power(intel_dp))
1810 wait_panel_power_cycle(intel_dp);
99ea7127 1811
453c5420 1812 pp = ironlake_get_pp_control(intel_dp);
5d613501 1813 pp |= EDP_FORCE_VDD;
ebf33b18 1814
bf13e81b
JN		 1815 pp_stat_reg = _pp_stat_reg(intel_dp);
1816 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1817
1818 I915_WRITE(pp_ctrl_reg, pp);
1819 POSTING_READ(pp_ctrl_reg);
1820 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1821 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1822 /*
1823 * If the panel wasn't on, delay before accessing aux channel
1824 */
4be73780 1825 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1826 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1827 port_name(intel_dig_port->port));
f01eca2e 1828 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1829 }
adddaaf4
JN		 1830
1831 return need_to_disable;
1832}
1833
951468f3
VS		 1834/*
1835 * Must be paired with intel_edp_panel_vdd_off() or
1836 * intel_edp_panel_off().
1837 * Nested calls to these functions are not allowed since
1838 * we drop the lock. Caller must use some higher level
1839 * locking to prevent nested calls from other threads.
1840 */
b80d6c78 1841void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1842{
c695b6b6 1843 bool vdd;
adddaaf4 1844
c695b6b6
VS		 1845 if (!is_edp(intel_dp))
1846 return;
1847
773538e8 1848 pps_lock(intel_dp);
c695b6b6 1849 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1850 pps_unlock(intel_dp);
c695b6b6 1851
e2c719b7 1852 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1853 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1854}
1855
4be73780 1856static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1857{
30add22d 1858 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1859 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1860 struct intel_digital_port *intel_dig_port =
1861 dp_to_dig_port(intel_dp);
1862 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1863 enum intel_display_power_domain power_domain;
5d613501 1864 u32 pp;
f0f59a00 1865 i915_reg_t pp_stat_reg, pp_ctrl_reg;
5d613501 1866
e39b999a 1867 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1868
15e899a0 1869 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1870
15e899a0 1871 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1872 return;
b0665d57 1873
3936fcf4
VS		 1874 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1875 port_name(intel_dig_port->port));
bd943159 1876
be2c9196
VS		 1877 pp = ironlake_get_pp_control(intel_dp);
1878 pp &= ~EDP_FORCE_VDD;
453c5420 1879
be2c9196
VS		 1880 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1881 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1882
be2c9196
VS		 1883 I915_WRITE(pp_ctrl_reg, pp);
1884 POSTING_READ(pp_ctrl_reg);
90791a5c 1885
be2c9196
VS		 1886 /* Make sure sequencer is idle before allowing subsequent activity */
1887 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1888 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1889
be2c9196 1890 if ((pp & POWER_TARGET_ON) == 0)
d28d4731 1891 intel_dp->panel_power_off_time = ktime_get_boottime();
e9cb81a2 1892
25f78f58 1893 power_domain = intel_display_port_aux_power_domain(intel_encoder);
be2c9196 1894 intel_display_power_put(dev_priv, power_domain);
bd943159 1895}
5d613501 1896
4be73780 1897static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1898{
1899 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1900 struct intel_dp, panel_vdd_work);
bd943159 1901
773538e8 1902 pps_lock(intel_dp);
15e899a0
VS		 1903 if (!intel_dp->want_panel_vdd)
1904 edp_panel_vdd_off_sync(intel_dp);
773538e8 1905 pps_unlock(intel_dp);
bd943159
KP		 1906}
1907
aba86890
ID		 1908static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1909{
1910 unsigned long delay;
1911
1912 /*
1913 * Queue the timer to fire a long time from now (relative to the power
1914 * down delay) to keep the panel power up across a sequence of
1915 * operations.
1916 */
1917 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1918 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1919}
1920
951468f3
VS		 1921/*
1922 * Must be paired with edp_panel_vdd_on().
1923 * Must hold pps_mutex around the whole on/off sequence.
1924 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1925 */
4be73780 1926static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1927{
e39b999a
VS		 1928 struct drm_i915_private *dev_priv =
1929 intel_dp_to_dev(intel_dp)->dev_private;
1930
1931 lockdep_assert_held(&dev_priv->pps_mutex);
1932
97af61f5
KP		 1933 if (!is_edp(intel_dp))
1934 return;
5d613501 1935
e2c719b7 1936 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1937 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1938
bd943159
KP		 1939 intel_dp->want_panel_vdd = false;
1940
aba86890 1941 if (sync)
4be73780 1942 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1943 else
1944 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1945}
1946
9f0fb5be 1947static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1948{
30add22d 1949 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1950 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1951 u32 pp;
f0f59a00 1952 i915_reg_t pp_ctrl_reg;
9934c132 1953
9f0fb5be
VS		 1954 lockdep_assert_held(&dev_priv->pps_mutex);
1955
97af61f5 1956 if (!is_edp(intel_dp))
bd943159 1957 return;
99ea7127 1958
3936fcf4
VS		 1959 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1960 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1961
e7a89ace
VS		 1962 if (WARN(edp_have_panel_power(intel_dp),
1963 "eDP port %c panel power already on\n",
1964 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1965 return;
9934c132 1966
4be73780 1967 wait_panel_power_cycle(intel_dp);
37c6c9b0 1968
bf13e81b 1969 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1970 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1971 if (IS_GEN5(dev)) {
1972 /* ILK workaround: disable reset around power sequence */
1973 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1974 I915_WRITE(pp_ctrl_reg, pp);
1975 POSTING_READ(pp_ctrl_reg);
05ce1a49 1976 }
37c6c9b0 1977
1c0ae80a 1978 pp |= POWER_TARGET_ON;
99ea7127
KP		 1979 if (!IS_GEN5(dev))
1980 pp |= PANEL_POWER_RESET;
1981
453c5420
JB		 1982 I915_WRITE(pp_ctrl_reg, pp);
1983 POSTING_READ(pp_ctrl_reg);
9934c132 1984
4be73780 1985 wait_panel_on(intel_dp);
dce56b3c 1986 intel_dp->last_power_on = jiffies;
9934c132 1987
05ce1a49
KP		 1988 if (IS_GEN5(dev)) {
1989 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1990 I915_WRITE(pp_ctrl_reg, pp);
1991 POSTING_READ(pp_ctrl_reg);
05ce1a49 1992 }
9f0fb5be 1993}
e39b999a 1994
9f0fb5be
VS		 1995void intel_edp_panel_on(struct intel_dp *intel_dp)
1996{
1997 if (!is_edp(intel_dp))
1998 return;
1999
2000 pps_lock(intel_dp);
2001 edp_panel_on(intel_dp);
773538e8 2002 pps_unlock(intel_dp);
9934c132
JB		 2003}
2004
9f0fb5be
VS		 2005
2006static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 2007{
4e6e1a54
ID		 2008 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2009 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 2010 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 2011 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 2012 enum intel_display_power_domain power_domain;
99ea7127 2013 u32 pp;
f0f59a00 2014 i915_reg_t pp_ctrl_reg;
9934c132 2015
9f0fb5be
VS		 2016 lockdep_assert_held(&dev_priv->pps_mutex);
2017
97af61f5
KP		 2018 if (!is_edp(intel_dp))
2019 return;
37c6c9b0 2020
3936fcf4
VS		 2021 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2022 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 2023
3936fcf4
VS		 2024 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2025 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 2026
453c5420 2027 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 2028 /* We need to switch off panel power _and_ force vdd, for otherwise some
2029 * panels get very unhappy and cease to work. */
b3064154
PJ		 2030 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2031 EDP_BLC_ENABLE);
453c5420 2032
bf13e81b 2033 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2034
849e39f5
PZ		 2035 intel_dp->want_panel_vdd = false;
2036
453c5420
JB		 2037 I915_WRITE(pp_ctrl_reg, pp);
2038 POSTING_READ(pp_ctrl_reg);
9934c132 2039
d28d4731 2040 intel_dp->panel_power_off_time = ktime_get_boottime();
4be73780 2041 wait_panel_off(intel_dp);
849e39f5
PZ		 2042
2043 /* We got a reference when we enabled the VDD. */
25f78f58 2044 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 2045 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 2046}
e39b999a 2047
9f0fb5be
VS		 2048void intel_edp_panel_off(struct intel_dp *intel_dp)
2049{
2050 if (!is_edp(intel_dp))
2051 return;
e39b999a 2052
9f0fb5be
VS		 2053 pps_lock(intel_dp);
2054 edp_panel_off(intel_dp);
773538e8 2055 pps_unlock(intel_dp);
9934c132
JB		 2056}
2057
1250d107
JN		 2058/* Enable backlight in the panel power control. */
2059static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2060{
da63a9f2
PZ		 2061 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2062 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 2063 struct drm_i915_private *dev_priv = dev->dev_private;
2064 u32 pp;
f0f59a00 2065 i915_reg_t pp_ctrl_reg;
32f9d658 2066
01cb9ea6
JB		 2067 /*
2068 * If we enable the backlight right away following a panel power
2069 * on, we may see slight flicker as the panel syncs with the eDP
2070 * link. So delay a bit to make sure the image is solid before
2071 * allowing it to appear.
2072 */
4be73780 2073 wait_backlight_on(intel_dp);
e39b999a 2074
773538e8 2075 pps_lock(intel_dp);
e39b999a 2076
453c5420 2077 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2078 pp |= EDP_BLC_ENABLE;
453c5420 2079
bf13e81b 2080 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2081
2082 I915_WRITE(pp_ctrl_reg, pp);
2083 POSTING_READ(pp_ctrl_reg);
e39b999a 2084
773538e8 2085 pps_unlock(intel_dp);
32f9d658
ZW		 2086}
2087
1250d107
JN		 2088/* Enable backlight PWM and backlight PP control. */
2089void intel_edp_backlight_on(struct intel_dp *intel_dp)
2090{
2091 if (!is_edp(intel_dp))
2092 return;
2093
2094 DRM_DEBUG_KMS("\n");
2095
2096 intel_panel_enable_backlight(intel_dp->attached_connector);
2097 _intel_edp_backlight_on(intel_dp);
2098}
2099
2100/* Disable backlight in the panel power control. */
2101static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2102{
30add22d 2103 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 2104 struct drm_i915_private *dev_priv = dev->dev_private;
2105 u32 pp;
f0f59a00 2106 i915_reg_t pp_ctrl_reg;
32f9d658 2107
f01eca2e
KP		 2108 if (!is_edp(intel_dp))
2109 return;
2110
773538e8 2111 pps_lock(intel_dp);
e39b999a 2112
453c5420 2113 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2114 pp &= ~EDP_BLC_ENABLE;
453c5420 2115
bf13e81b 2116 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2117
2118 I915_WRITE(pp_ctrl_reg, pp);
2119 POSTING_READ(pp_ctrl_reg);
f7d2323c 2120
773538e8 2121 pps_unlock(intel_dp);
e39b999a
VS		 2122
2123 intel_dp->last_backlight_off = jiffies;
f7d2323c 2124 edp_wait_backlight_off(intel_dp);
1250d107 2125}
f7d2323c 2126
1250d107
JN		 2127/* Disable backlight PP control and backlight PWM. */
2128void intel_edp_backlight_off(struct intel_dp *intel_dp)
2129{
2130 if (!is_edp(intel_dp))
2131 return;
2132
2133 DRM_DEBUG_KMS("\n");
f7d2323c 2134
1250d107 2135 _intel_edp_backlight_off(intel_dp);
f7d2323c 2136 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2137}
a4fc5ed6 2138
73580fb7
JN		 2139/*
2140 * Hook for controlling the panel power control backlight through the bl_power
2141 * sysfs attribute. Take care to handle multiple calls.
2142 */
2143static void intel_edp_backlight_power(struct intel_connector *connector,
2144 bool enable)
2145{
2146 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2147 bool is_enabled;
2148
773538e8 2149 pps_lock(intel_dp);
e39b999a 2150 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2151 pps_unlock(intel_dp);
73580fb7
JN		 2152
2153 if (is_enabled == enable)
2154 return;
2155
23ba9373
JN		 2156 DRM_DEBUG_KMS("panel power control backlight %s\n",
2157 enable ? "enable" : "disable");
73580fb7
JN		 2158
2159 if (enable)
2160 _intel_edp_backlight_on(intel_dp);
2161 else
2162 _intel_edp_backlight_off(intel_dp);
2163}
2164
64e1077a
VS		 2165static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2166{
2167 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2168 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2169 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2170
2171 I915_STATE_WARN(cur_state != state,
2172 "DP port %c state assertion failure (expected %s, current %s)\n",
2173 port_name(dig_port->port),
87ad3212 2174 onoff(state), onoff(cur_state));
64e1077a
VS		 2175}
2176#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2177
2178static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2179{
2180 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2181
2182 I915_STATE_WARN(cur_state != state,
2183 "eDP PLL state assertion failure (expected %s, current %s)\n",
87ad3212 2184 onoff(state), onoff(cur_state));
64e1077a
VS		 2185}
2186#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2187#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2188
2bd2ad64 2189static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2190{
da63a9f2 2191 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2192 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2193 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2194
64e1077a
VS		 2195 assert_pipe_disabled(dev_priv, crtc->pipe);
2196 assert_dp_port_disabled(intel_dp);
2197 assert_edp_pll_disabled(dev_priv);
2bd2ad64 2198
abfce949
VS		 2199 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2200 crtc->config->port_clock);
2201
2202 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2203
2204 if (crtc->config->port_clock == 162000)
2205 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2206 else
2207 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2208
2209 I915_WRITE(DP_A, intel_dp->DP);
2210 POSTING_READ(DP_A);
2211 udelay(500);
2212
6b23f3e8
VS		 2213 /*
2214 * [DevILK] Work around required when enabling DP PLL
2215 * while a pipe is enabled going to FDI:
2216 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2217 * 2. Program DP PLL enable
2218 */
2219 if (IS_GEN5(dev_priv))
2220 intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe);
2221
0767935e 2222 intel_dp->DP |= DP_PLL_ENABLE;
6fec7662 2223
0767935e 2224 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2225 POSTING_READ(DP_A);
2226 udelay(200);
d240f20f
JB		 2227}
2228
2bd2ad64 2229static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2230{
da63a9f2 2231 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2232 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2233 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2234
64e1077a
VS		 2235 assert_pipe_disabled(dev_priv, crtc->pipe);
2236 assert_dp_port_disabled(intel_dp);
2237 assert_edp_pll_enabled(dev_priv);
2bd2ad64 2238
abfce949
VS		 2239 DRM_DEBUG_KMS("disabling eDP PLL\n");
2240
6fec7662 2241 intel_dp->DP &= ~DP_PLL_ENABLE;
0767935e 2242
6fec7662 2243 I915_WRITE(DP_A, intel_dp->DP);
1af5fa1b 2244 POSTING_READ(DP_A);
d240f20f
JB		 2245 udelay(200);
2246}
2247
c7ad3810 2248/* If the sink supports it, try to set the power state appropriately */
c19b0669 2249void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2250{
2251 int ret, i;
2252
2253 /* Should have a valid DPCD by this point */
2254 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2255 return;
2256
2257 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2258 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2259 DP_SET_POWER_D3);
c7ad3810
JB		 2260 } else {
2261 /*
2262 * When turning on, we need to retry for 1ms to give the sink
2263 * time to wake up.
2264 */
2265 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2266 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2267 DP_SET_POWER_D0);
c7ad3810
JB		 2268 if (ret == 1)
2269 break;
2270 msleep(1);
2271 }
2272 }
f9cac721
JN		 2273
2274 if (ret != 1)
2275 DRM_DEBUG_KMS("failed to %s sink power state\n",
2276 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2277}
2278
19d8fe15
DV		 2279static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2280 enum pipe *pipe)
d240f20f 2281{
19d8fe15 2282 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2283 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2284 struct drm_device *dev = encoder->base.dev;
2285 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2286 enum intel_display_power_domain power_domain;
2287 u32 tmp;
6fa9a5ec 2288 bool ret;
6d129bea
ID		 2289
2290 power_domain = intel_display_port_power_domain(encoder);
6fa9a5ec 2291 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 2292 return false;
2293
6fa9a5ec
ID		 2294 ret = false;
2295
6d129bea 2296 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2297
2298 if (!(tmp & DP_PORT_EN))
6fa9a5ec 2299 goto out;
19d8fe15 2300
39e5fa88 2301 if (IS_GEN7(dev) && port == PORT_A) {
19d8fe15 2302 *pipe = PORT_TO_PIPE_CPT(tmp);
39e5fa88 2303 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
adc289d7 2304 enum pipe p;
19d8fe15 2305
adc289d7
VS		 2306 for_each_pipe(dev_priv, p) {
2307 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2308 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2309 *pipe = p;
6fa9a5ec
ID		 2310 ret = true;
2311
2312 goto out;
19d8fe15
DV		 2313 }
2314 }
19d8fe15 2315
4a0833ec 2316 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
f0f59a00 2317 i915_mmio_reg_offset(intel_dp->output_reg));
39e5fa88
VS		 2318 } else if (IS_CHERRYVIEW(dev)) {
2319 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2320 } else {
2321 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2322 }
d240f20f 2323
6fa9a5ec
ID		 2324 ret = true;
2325
2326out:
2327 intel_display_power_put(dev_priv, power_domain);
2328
2329 return ret;
19d8fe15 2330}
d240f20f 2331
045ac3b5 2332static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2333 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2334{
2335 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2336 u32 tmp, flags = 0;
63000ef6
XZ		 2337 struct drm_device *dev = encoder->base.dev;
2338 struct drm_i915_private *dev_priv = dev->dev_private;
2339 enum port port = dp_to_dig_port(intel_dp)->port;
2340 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 2341
9ed109a7 2342 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2343
2344 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2345
39e5fa88 2346 if (HAS_PCH_CPT(dev) && port != PORT_A) {
b81e34c2
VS		 2347 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2348
2349 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2350 flags |= DRM_MODE_FLAG_PHSYNC;
2351 else
2352 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2353
b81e34c2 2354 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2355 flags |= DRM_MODE_FLAG_PVSYNC;
2356 else
2357 flags |= DRM_MODE_FLAG_NVSYNC;
2358 } else {
39e5fa88 2359 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2360 flags |= DRM_MODE_FLAG_PHSYNC;
2361 else
2362 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2363
39e5fa88 2364 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2365 flags |= DRM_MODE_FLAG_PVSYNC;
2366 else
2367 flags |= DRM_MODE_FLAG_NVSYNC;
2368 }
045ac3b5 2369
2d112de7 2370 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2371
8c875fca 2372 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 2373 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
8c875fca
VS		 2374 pipe_config->limited_color_range = true;
2375
eb14cb74
VS		 2376 pipe_config->has_dp_encoder = true;
2377
90a6b7b0
VS		 2378 pipe_config->lane_count =
2379 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2380
eb14cb74
VS		 2381 intel_dp_get_m_n(crtc, pipe_config);
2382
18442d08 2383 if (port == PORT_A) {
b377e0df 2384 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
f1f644dc
JB		 2385 pipe_config->port_clock = 162000;
2386 else
2387 pipe_config->port_clock = 270000;
2388 }
18442d08 2389
e3b247da
VS		 2390 pipe_config->base.adjusted_mode.crtc_clock =
2391 intel_dotclock_calculate(pipe_config->port_clock,
2392 &pipe_config->dp_m_n);
7f16e5c1 2393
6aa23e65
JN		 2394 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2395 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
c6cd2ee2
JN		 2396 /*
2397 * This is a big fat ugly hack.
2398 *
2399 * Some machines in UEFI boot mode provide us a VBT that has 18
2400 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2401 * unknown we fail to light up. Yet the same BIOS boots up with
2402 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2403 * max, not what it tells us to use.
2404 *
2405 * Note: This will still be broken if the eDP panel is not lit
2406 * up by the BIOS, and thus we can't get the mode at module
2407 * load.
2408 */
2409 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2410 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2411 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
c6cd2ee2 2412 }
045ac3b5
JB		 2413}
2414
e8cb4558 2415static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2416{
e8cb4558 2417 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2418 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2419 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2420
6e3c9717 2421 if (crtc->config->has_audio)
495a5bb8 2422 intel_audio_codec_disable(encoder);
6cb49835 2423
b32c6f48
RV		 2424 if (HAS_PSR(dev) && !HAS_DDI(dev))
2425 intel_psr_disable(intel_dp);
2426
6cb49835
DV		 2427 /* Make sure the panel is off before trying to change the mode. But also
2428 * ensure that we have vdd while we switch off the panel. */
24f3e092 2429 intel_edp_panel_vdd_on(intel_dp);
4be73780 2430 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2431 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2432 intel_edp_panel_off(intel_dp);
3739850b 2433
08aff3fe
VS		 2434 /* disable the port before the pipe on g4x */
2435 if (INTEL_INFO(dev)->gen < 5)
3739850b 2436 intel_dp_link_down(intel_dp);
d240f20f
JB		 2437}
2438
08aff3fe 2439static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2440{
2bd2ad64 2441 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2442 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2443
49277c31 2444 intel_dp_link_down(intel_dp);
abfce949
VS		 2445
2446 /* Only ilk+ has port A */
08aff3fe
VS		 2447 if (port == PORT_A)
2448 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2449}
2450
2451static void vlv_post_disable_dp(struct intel_encoder *encoder)
2452{
2453 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2454
2455 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2456}
2457
a8f327fb
VS		 2458static void chv_post_disable_dp(struct intel_encoder *encoder)
2459{
2460 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2461 struct drm_device *dev = encoder->base.dev;
2462 struct drm_i915_private *dev_priv = dev->dev_private;
97fd4d5c 2463
a8f327fb
VS		 2464 intel_dp_link_down(intel_dp);
2465
2466 mutex_lock(&dev_priv->sb_lock);
2467
2468 /* Assert data lane reset */
2469 chv_data_lane_soft_reset(encoder, true);
580d3811 2470
a580516d 2471 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2472}
2473
7b13b58a
VS		 2474static void
2475_intel_dp_set_link_train(struct intel_dp *intel_dp,
2476 uint32_t *DP,
2477 uint8_t dp_train_pat)
2478{
2479 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2480 struct drm_device *dev = intel_dig_port->base.base.dev;
2481 struct drm_i915_private *dev_priv = dev->dev_private;
2482 enum port port = intel_dig_port->port;
2483
2484 if (HAS_DDI(dev)) {
2485 uint32_t temp = I915_READ(DP_TP_CTL(port));
2486
2487 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2488 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2489 else
2490 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2491
2492 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2493 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2494 case DP_TRAINING_PATTERN_DISABLE:
2495 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2496
2497 break;
2498 case DP_TRAINING_PATTERN_1:
2499 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2500 break;
2501 case DP_TRAINING_PATTERN_2:
2502 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2503 break;
2504 case DP_TRAINING_PATTERN_3:
2505 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2506 break;
2507 }
2508 I915_WRITE(DP_TP_CTL(port), temp);
2509
39e5fa88
VS		 2510 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2511 (HAS_PCH_CPT(dev) && port != PORT_A)) {
7b13b58a
VS		 2512 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2513
2514 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2515 case DP_TRAINING_PATTERN_DISABLE:
2516 *DP |= DP_LINK_TRAIN_OFF_CPT;
2517 break;
2518 case DP_TRAINING_PATTERN_1:
2519 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2520 break;
2521 case DP_TRAINING_PATTERN_2:
2522 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2523 break;
2524 case DP_TRAINING_PATTERN_3:
2525 DRM_ERROR("DP training pattern 3 not supported\n");
2526 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2527 break;
2528 }
2529
2530 } else {
2531 if (IS_CHERRYVIEW(dev))
2532 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2533 else
2534 *DP &= ~DP_LINK_TRAIN_MASK;
2535
2536 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2537 case DP_TRAINING_PATTERN_DISABLE:
2538 *DP |= DP_LINK_TRAIN_OFF;
2539 break;
2540 case DP_TRAINING_PATTERN_1:
2541 *DP |= DP_LINK_TRAIN_PAT_1;
2542 break;
2543 case DP_TRAINING_PATTERN_2:
2544 *DP |= DP_LINK_TRAIN_PAT_2;
2545 break;
2546 case DP_TRAINING_PATTERN_3:
2547 if (IS_CHERRYVIEW(dev)) {
2548 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2549 } else {
2550 DRM_ERROR("DP training pattern 3 not supported\n");
2551 *DP |= DP_LINK_TRAIN_PAT_2;
2552 }
2553 break;
2554 }
2555 }
2556}
2557
2558static void intel_dp_enable_port(struct intel_dp *intel_dp)
2559{
2560 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2561 struct drm_i915_private *dev_priv = dev->dev_private;
6fec7662
VS		 2562 struct intel_crtc *crtc =
2563 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
7b13b58a 2564
7b13b58a
VS		 2565 /* enable with pattern 1 (as per spec) */
2566 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2567 DP_TRAINING_PATTERN_1);
2568
2569 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2570 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2571
2572 /*
2573 * Magic for VLV/CHV. We _must_ first set up the register
2574 * without actually enabling the port, and then do another
2575 * write to enable the port. Otherwise link training will
2576 * fail when the power sequencer is freshly used for this port.
2577 */
2578 intel_dp->DP |= DP_PORT_EN;
6fec7662
VS		 2579 if (crtc->config->has_audio)
2580 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
7b713f50
VS		 2581
2582 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2583 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2584}
2585
e8cb4558 2586static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2587{
e8cb4558
DV		 2588 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2589 struct drm_device *dev = encoder->base.dev;
2590 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2591 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2592 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
d6fbdd15 2593 enum pipe pipe = crtc->pipe;
5d613501 2594
0c33d8d7
DV		 2595 if (WARN_ON(dp_reg & DP_PORT_EN))
2596 return;
5d613501 2597
093e3f13
VS		 2598 pps_lock(intel_dp);
2599
666a4537 2600 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
093e3f13
VS		 2601 vlv_init_panel_power_sequencer(intel_dp);
2602
7b13b58a 2603 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2604
2605 edp_panel_vdd_on(intel_dp);
2606 edp_panel_on(intel_dp);
2607 edp_panel_vdd_off(intel_dp, true);
2608
2609 pps_unlock(intel_dp);
2610
666a4537 2611 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e0fce78f
VS		 2612 unsigned int lane_mask = 0x0;
2613
2614 if (IS_CHERRYVIEW(dev))
2615 lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2616
9b6de0a1
VS		 2617 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2618 lane_mask);
e0fce78f 2619 }
61234fa5 2620
f01eca2e 2621 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2622 intel_dp_start_link_train(intel_dp);
3ab9c637 2623 intel_dp_stop_link_train(intel_dp);
c1dec79a 2624
6e3c9717 2625 if (crtc->config->has_audio) {
c1dec79a 2626 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
d6fbdd15 2627 pipe_name(pipe));
c1dec79a
JN		 2628 intel_audio_codec_enable(encoder);
2629 }
ab1f90f9 2630}
89b667f8 2631
ecff4f3b
JN		 2632static void g4x_enable_dp(struct intel_encoder *encoder)
2633{
828f5c6e
JN		 2634 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2635
ecff4f3b 2636 intel_enable_dp(encoder);
4be73780 2637 intel_edp_backlight_on(intel_dp);
ab1f90f9 2638}
89b667f8 2639
ab1f90f9
JN		 2640static void vlv_enable_dp(struct intel_encoder *encoder)
2641{
828f5c6e
JN		 2642 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2643
4be73780 2644 intel_edp_backlight_on(intel_dp);
b32c6f48 2645 intel_psr_enable(intel_dp);
d240f20f
JB		 2646}
2647
ecff4f3b 2648static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2649{
2650 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6fbdd15 2651 enum port port = dp_to_dig_port(intel_dp)->port;
ab1f90f9 2652
8ac33ed3
DV		 2653 intel_dp_prepare(encoder);
2654
d41f1efb 2655 /* Only ilk+ has port A */
abfce949 2656 if (port == PORT_A)
ab1f90f9
JN		 2657 ironlake_edp_pll_on(intel_dp);
2658}
2659
83b84597
VS		 2660static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2661{
2662 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2663 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2664 enum pipe pipe = intel_dp->pps_pipe;
f0f59a00 2665 i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
83b84597
VS		 2666
2667 edp_panel_vdd_off_sync(intel_dp);
2668
2669 /*
2670 * VLV seems to get confused when multiple power seqeuencers
2671 * have the same port selected (even if only one has power/vdd
2672 * enabled). The failure manifests as vlv_wait_port_ready() failing
2673 * CHV on the other hand doesn't seem to mind having the same port
2674 * selected in multiple power seqeuencers, but let's clear the
2675 * port select always when logically disconnecting a power sequencer
2676 * from a port.
2677 */
2678 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2679 pipe_name(pipe), port_name(intel_dig_port->port));
2680 I915_WRITE(pp_on_reg, 0);
2681 POSTING_READ(pp_on_reg);
2682
2683 intel_dp->pps_pipe = INVALID_PIPE;
2684}
2685
a4a5d2f8
VS		 2686static void vlv_steal_power_sequencer(struct drm_device *dev,
2687 enum pipe pipe)
2688{
2689 struct drm_i915_private *dev_priv = dev->dev_private;
2690 struct intel_encoder *encoder;
2691
2692 lockdep_assert_held(&dev_priv->pps_mutex);
2693
ac3c12e4
VS		 2694 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2695 return;
2696
19c8054c 2697 for_each_intel_encoder(dev, encoder) {
a4a5d2f8 2698 struct intel_dp *intel_dp;
773538e8 2699 enum port port;
a4a5d2f8
VS		 2700
2701 if (encoder->type != INTEL_OUTPUT_EDP)
2702 continue;
2703
2704 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2705 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2706
2707 if (intel_dp->pps_pipe != pipe)
2708 continue;
2709
2710 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2711 pipe_name(pipe), port_name(port));
a4a5d2f8 2712
e02f9a06 2713 WARN(encoder->base.crtc,
034e43c6
VS		 2714 "stealing pipe %c power sequencer from active eDP port %c\n",
2715 pipe_name(pipe), port_name(port));
a4a5d2f8 2716
a4a5d2f8 2717 /* make sure vdd is off before we steal it */
83b84597 2718 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2719 }
2720}
2721
2722static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2723{
2724 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2725 struct intel_encoder *encoder = &intel_dig_port->base;
2726 struct drm_device *dev = encoder->base.dev;
2727 struct drm_i915_private *dev_priv = dev->dev_private;
2728 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2729
2730 lockdep_assert_held(&dev_priv->pps_mutex);
2731
093e3f13
VS		 2732 if (!is_edp(intel_dp))
2733 return;
2734
a4a5d2f8
VS		 2735 if (intel_dp->pps_pipe == crtc->pipe)
2736 return;
2737
2738 /*
2739 * If another power sequencer was being used on this
2740 * port previously make sure to turn off vdd there while
2741 * we still have control of it.
2742 */
2743 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2744 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2745
2746 /*
2747 * We may be stealing the power
2748 * sequencer from another port.
2749 */
2750 vlv_steal_power_sequencer(dev, crtc->pipe);
2751
2752 /* now it's all ours */
2753 intel_dp->pps_pipe = crtc->pipe;
2754
2755 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2756 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2757
2758 /* init power sequencer on this pipe and port */
36b5f425
VS		 2759 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2760 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2761}
2762
ab1f90f9 2763static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2764{
2bd2ad64 2765 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2766 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2767 struct drm_device *dev = encoder->base.dev;
89b667f8 2768 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2769 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2770 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2771 int pipe = intel_crtc->pipe;
2772 u32 val;
a4fc5ed6 2773
a580516d 2774 mutex_lock(&dev_priv->sb_lock);
89b667f8 2775
ab3c759a 2776 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2777 val = 0;
2778 if (pipe)
2779 val |= (1<<21);
2780 else
2781 val &= ~(1<<21);
2782 val |= 0x001000c4;
ab3c759a
CML		 2783 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2784 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2785 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2786
a580516d 2787 mutex_unlock(&dev_priv->sb_lock);
ab1f90f9
JN		 2788
2789 intel_enable_dp(encoder);
89b667f8
JB		 2790}
2791
ecff4f3b 2792static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8 2793{
8ac33ed3
DV		 2794 intel_dp_prepare(encoder);
2795
6da2e616 2796 vlv_phy_pre_pll_enable(encoder);
a4fc5ed6
KP		 2797}
2798
e4a1d846
CML		 2799static void chv_pre_enable_dp(struct intel_encoder *encoder)
2800{
e7d2a717 2801 chv_phy_pre_encoder_enable(encoder);
e4a1d846 2802
e4a1d846 2803 intel_enable_dp(encoder);
b0b33846
VS		 2804
2805 /* Second common lane will stay alive on its own now */
e7d2a717 2806 chv_phy_release_cl2_override(encoder);
e4a1d846
CML		 2807}
2808
9197c88b
VS		 2809static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2810{
625695f8
VS		 2811 intel_dp_prepare(encoder);
2812
419b1b7a 2813 chv_phy_pre_pll_enable(encoder);
9197c88b
VS		 2814}
2815
d6db995f
VS		 2816static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
2817{
204970b5 2818 chv_phy_post_pll_disable(encoder);
d6db995f
VS		 2819}
2820
a4fc5ed6 2821/*
df0c237d
JB		 2822 * Native read with retry for link status and receiver capability reads for
2823 * cases where the sink may still be asleep.
9d1a1031
JN		 2824 *
2825 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2826 * supposed to retry 3 times per the spec.
a4fc5ed6 2827 */
9d1a1031
JN		 2828static ssize_t
2829intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2830 void *buffer, size_t size)
a4fc5ed6 2831{
9d1a1031
JN		 2832 ssize_t ret;
2833 int i;
61da5fab 2834
f6a19066
VS		 2835 /*
2836 * Sometime we just get the same incorrect byte repeated
2837 * over the entire buffer. Doing just one throw away read
2838 * initially seems to "solve" it.
2839 */
2840 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2841
61da5fab 2842 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2843 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2844 if (ret == size)
2845 return ret;
61da5fab
JB		 2846 msleep(1);
2847 }
a4fc5ed6 2848
9d1a1031 2849 return ret;
a4fc5ed6
KP		 2850}
2851
2852/*
2853 * Fetch AUX CH registers 0x202 - 0x207 which contain
2854 * link status information
2855 */
94223d04 2856bool
93f62dad 2857intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2858{
9d1a1031
JN		 2859 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2860 DP_LANE0_1_STATUS,
2861 link_status,
2862 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2863}
2864
1100244e 2865/* These are source-specific values. */
94223d04 2866uint8_t
1a2eb460 2867intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2868{
30add22d 2869 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 2870 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 2871 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2872
9314726b
VK		 2873 if (IS_BROXTON(dev))
2874 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2875 else if (INTEL_INFO(dev)->gen >= 9) {
06411f08 2876 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
7ad14a29 2877 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2878 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
666a4537 2879 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
bd60018a 2880 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2881 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2882 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2883 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2884 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2885 else
bd60018a 2886 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2887}
2888
94223d04 2889uint8_t
1a2eb460
KP		 2890intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2891{
30add22d 2892 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2893 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2894
5a9d1f1a
DL		 2895 if (INTEL_INFO(dev)->gen >= 9) {
2896 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2897 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2898 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2899 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2900 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2901 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2902 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 2903 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2904 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 2905 default:
2906 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2907 }
2908 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2909 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2910 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2911 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2912 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2913 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2914 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2915 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2916 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2917 default:
bd60018a 2918 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2919 }
666a4537 2920 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e2fa6fba 2921 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2922 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2923 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2924 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2925 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2926 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2927 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2928 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2929 default:
bd60018a 2930 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2931 }
bc7d38a4 2932 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2933 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2934 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2935 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2936 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2938 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2939 default:
bd60018a 2940 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2941 }
2942 } else {
2943 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2944 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2945 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2946 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2947 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2949 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2950 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2951 default:
bd60018a 2952 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2953 }
a4fc5ed6
KP		 2954 }
2955}
2956
5829975c 2957static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba 2958{
53d98725 2959 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
e2fa6fba
P		 2960 unsigned long demph_reg_value, preemph_reg_value,
2961 uniqtranscale_reg_value;
2962 uint8_t train_set = intel_dp->train_set[0];
e2fa6fba
P		 2963
2964 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2965 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2966 preemph_reg_value = 0x0004000;
2967 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2968 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2969 demph_reg_value = 0x2B405555;
2970 uniqtranscale_reg_value = 0x552AB83A;
2971 break;
bd60018a 2972 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2973 demph_reg_value = 0x2B404040;
2974 uniqtranscale_reg_value = 0x5548B83A;
2975 break;
bd60018a 2976 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2977 demph_reg_value = 0x2B245555;
2978 uniqtranscale_reg_value = 0x5560B83A;
2979 break;
bd60018a 2980 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2981 demph_reg_value = 0x2B405555;
2982 uniqtranscale_reg_value = 0x5598DA3A;
2983 break;
2984 default:
2985 return 0;
2986 }
2987 break;
bd60018a 2988 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2989 preemph_reg_value = 0x0002000;
2990 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2991 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2992 demph_reg_value = 0x2B404040;
2993 uniqtranscale_reg_value = 0x5552B83A;
2994 break;
bd60018a 2995 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2996 demph_reg_value = 0x2B404848;
2997 uniqtranscale_reg_value = 0x5580B83A;
2998 break;
bd60018a 2999 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3000 demph_reg_value = 0x2B404040;
3001 uniqtranscale_reg_value = 0x55ADDA3A;
3002 break;
3003 default:
3004 return 0;
3005 }
3006 break;
bd60018a 3007 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3008 preemph_reg_value = 0x0000000;
3009 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3010 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3011 demph_reg_value = 0x2B305555;
3012 uniqtranscale_reg_value = 0x5570B83A;
3013 break;
bd60018a 3014 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3015 demph_reg_value = 0x2B2B4040;
3016 uniqtranscale_reg_value = 0x55ADDA3A;
3017 break;
3018 default:
3019 return 0;
3020 }
3021 break;
bd60018a 3022 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3023 preemph_reg_value = 0x0006000;
3024 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3025 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3026 demph_reg_value = 0x1B405555;
3027 uniqtranscale_reg_value = 0x55ADDA3A;
3028 break;
3029 default:
3030 return 0;
3031 }
3032 break;
3033 default:
3034 return 0;
3035 }
3036
53d98725
ACO		 3037 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3038 uniqtranscale_reg_value, 0);
e2fa6fba
P		 3039
3040 return 0;
3041}
3042
5829975c 3043static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846 3044{
b7fa22d8
ACO		 3045 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3046 u32 deemph_reg_value, margin_reg_value;
3047 bool uniq_trans_scale = false;
e4a1d846 3048 uint8_t train_set = intel_dp->train_set[0];
e4a1d846
CML		 3049
3050 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3051 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3052 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3053 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3054 deemph_reg_value = 128;
3055 margin_reg_value = 52;
3056 break;
bd60018a 3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3058 deemph_reg_value = 128;
3059 margin_reg_value = 77;
3060 break;
bd60018a 3061 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3062 deemph_reg_value = 128;
3063 margin_reg_value = 102;
3064 break;
bd60018a 3065 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3066 deemph_reg_value = 128;
3067 margin_reg_value = 154;
b7fa22d8 3068 uniq_trans_scale = true;
e4a1d846
CML		 3069 break;
3070 default:
3071 return 0;
3072 }
3073 break;
bd60018a 3074 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3075 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3076 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3077 deemph_reg_value = 85;
3078 margin_reg_value = 78;
3079 break;
bd60018a 3080 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3081 deemph_reg_value = 85;
3082 margin_reg_value = 116;
3083 break;
bd60018a 3084 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3085 deemph_reg_value = 85;
3086 margin_reg_value = 154;
3087 break;
3088 default:
3089 return 0;
3090 }
3091 break;
bd60018a 3092 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3093 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3094 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3095 deemph_reg_value = 64;
3096 margin_reg_value = 104;
3097 break;
bd60018a 3098 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3099 deemph_reg_value = 64;
3100 margin_reg_value = 154;
3101 break;
3102 default:
3103 return 0;
3104 }
3105 break;
bd60018a 3106 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3107 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3108 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3109 deemph_reg_value = 43;
3110 margin_reg_value = 154;
3111 break;
3112 default:
3113 return 0;
3114 }
3115 break;
3116 default:
3117 return 0;
3118 }
3119
b7fa22d8
ACO		 3120 chv_set_phy_signal_level(encoder, deemph_reg_value,
3121 margin_reg_value, uniq_trans_scale);
e4a1d846
CML		 3122
3123 return 0;
3124}
3125
a4fc5ed6 3126static uint32_t
5829975c 3127gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3128{
3cf2efb1 3129 uint32_t signal_levels = 0;
a4fc5ed6 3130
3cf2efb1 3131 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3132 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3133 default:
3134 signal_levels |= DP_VOLTAGE_0_4;
3135 break;
bd60018a 3136 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3137 signal_levels |= DP_VOLTAGE_0_6;
3138 break;
bd60018a 3139 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3140 signal_levels |= DP_VOLTAGE_0_8;
3141 break;
bd60018a 3142 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3143 signal_levels |= DP_VOLTAGE_1_2;
3144 break;
3145 }
3cf2efb1 3146 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3147 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3148 default:
3149 signal_levels |= DP_PRE_EMPHASIS_0;
3150 break;
bd60018a 3151 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3152 signal_levels |= DP_PRE_EMPHASIS_3_5;
3153 break;
bd60018a 3154 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3155 signal_levels |= DP_PRE_EMPHASIS_6;
3156 break;
bd60018a 3157 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3158 signal_levels |= DP_PRE_EMPHASIS_9_5;
3159 break;
3160 }
3161 return signal_levels;
3162}
3163
e3421a18
ZW		 3164/* Gen6's DP voltage swing and pre-emphasis control */
3165static uint32_t
5829975c 3166gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3167{
3c5a62b5
YL		 3168 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3169 DP_TRAIN_PRE_EMPHASIS_MASK);
3170 switch (signal_levels) {
bd60018a
SJ		 3171 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3172 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3173 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3174 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3175 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3176 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3178 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3179 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3181 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3182 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3183 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3184 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3185 default:
3c5a62b5
YL		 3186 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3187 "0x%x\n", signal_levels);
3188 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3189 }
3190}
3191
1a2eb460
KP		 3192/* Gen7's DP voltage swing and pre-emphasis control */
3193static uint32_t
5829975c 3194gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3195{
3196 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3197 DP_TRAIN_PRE_EMPHASIS_MASK);
3198 switch (signal_levels) {
bd60018a 3199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3200 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3202 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3204 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3205
bd60018a 3206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3207 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3209 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3210
bd60018a 3211 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3212 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3214 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3215
3216 default:
3217 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3218 "0x%x\n", signal_levels);
3219 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3220 }
3221}
3222
94223d04 3223void
f4eb692e 3224intel_dp_set_signal_levels(struct intel_dp *intel_dp)
f0a3424e
PZ		 3225{
3226 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3227 enum port port = intel_dig_port->port;
f0a3424e 3228 struct drm_device *dev = intel_dig_port->base.base.dev;
b905a915 3229 struct drm_i915_private *dev_priv = to_i915(dev);
f8896f5d 3230 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3231 uint8_t train_set = intel_dp->train_set[0];
3232
f8896f5d
DW		 3233 if (HAS_DDI(dev)) {
3234 signal_levels = ddi_signal_levels(intel_dp);
3235
3236 if (IS_BROXTON(dev))
3237 signal_levels = 0;
3238 else
3239 mask = DDI_BUF_EMP_MASK;
e4a1d846 3240 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3241 signal_levels = chv_signal_levels(intel_dp);
e2fa6fba 3242 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3243 signal_levels = vlv_signal_levels(intel_dp);
bc7d38a4 3244 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3245 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3246 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3247 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3248 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3249 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3250 } else {
5829975c 3251 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3252 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3253 }
3254
96fb9f9b
VK		 3255 if (mask)
3256 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3257
3258 DRM_DEBUG_KMS("Using vswing level %d\n",
3259 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3260 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3261 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3262 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e 3263
f4eb692e 3264 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
b905a915
ACO		 3265
3266 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3267 POSTING_READ(intel_dp->output_reg);
f0a3424e
PZ		 3268}
3269
94223d04 3270void
e9c176d5
ACO		 3271intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3272 uint8_t dp_train_pat)
a4fc5ed6 3273{
174edf1f 3274 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3275 struct drm_i915_private *dev_priv =
3276 to_i915(intel_dig_port->base.base.dev);
a4fc5ed6 3277
f4eb692e 3278 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
47ea7542 3279
f4eb692e 3280 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
ea5b213a 3281 POSTING_READ(intel_dp->output_reg);
e9c176d5
ACO		 3282}
3283
94223d04 3284void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3ab9c637
ID		 3285{
3286 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3287 struct drm_device *dev = intel_dig_port->base.base.dev;
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 enum port port = intel_dig_port->port;
3290 uint32_t val;
3291
3292 if (!HAS_DDI(dev))
3293 return;
3294
3295 val = I915_READ(DP_TP_CTL(port));
3296 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3297 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3298 I915_WRITE(DP_TP_CTL(port), val);
3299
3300 /*
3301 * On PORT_A we can have only eDP in SST mode. There the only reason
3302 * we need to set idle transmission mode is to work around a HW issue
3303 * where we enable the pipe while not in idle link-training mode.
3304 * In this case there is requirement to wait for a minimum number of
3305 * idle patterns to be sent.
3306 */
3307 if (port == PORT_A)
3308 return;
3309
3310 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3311 1))
3312 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3313}
3314
a4fc5ed6 3315static void
ea5b213a 3316intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3317{
da63a9f2 3318 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3319 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3320 enum port port = intel_dig_port->port;
da63a9f2 3321 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3322 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3323 uint32_t DP = intel_dp->DP;
a4fc5ed6 3324
bc76e320 3325 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3326 return;
3327
0c33d8d7 3328 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3329 return;
3330
28c97730 3331 DRM_DEBUG_KMS("\n");
32f9d658 3332
39e5fa88
VS		 3333 if ((IS_GEN7(dev) && port == PORT_A) ||
3334 (HAS_PCH_CPT(dev) && port != PORT_A)) {
e3421a18 3335 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3336 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3337 } else {
aad3d14d
VS		 3338 if (IS_CHERRYVIEW(dev))
3339 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3340 else
3341 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3342 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3343 }
1612c8bd 3344 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3345 POSTING_READ(intel_dp->output_reg);
5eb08b69 3346
1612c8bd
VS		 3347 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3348 I915_WRITE(intel_dp->output_reg, DP);
3349 POSTING_READ(intel_dp->output_reg);
3350
3351 /*
3352 * HW workaround for IBX, we need to move the port
3353 * to transcoder A after disabling it to allow the
3354 * matching HDMI port to be enabled on transcoder A.
3355 */
3356 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
0c241d5b
VS		 3357 /*
3358 * We get CPU/PCH FIFO underruns on the other pipe when
3359 * doing the workaround. Sweep them under the rug.
3360 */
3361 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3362 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3363
1612c8bd
VS		 3364 /* always enable with pattern 1 (as per spec) */
3365 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3366 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3367 I915_WRITE(intel_dp->output_reg, DP);
3368 POSTING_READ(intel_dp->output_reg);
3369
3370 DP &= ~DP_PORT_EN;
5bddd17f 3371 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3372 POSTING_READ(intel_dp->output_reg);
0c241d5b
VS		 3373
3374 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3375 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3376 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5bddd17f
EA		 3377 }
3378
f01eca2e 3379 msleep(intel_dp->panel_power_down_delay);
6fec7662
VS		 3380
3381 intel_dp->DP = DP;
a4fc5ed6
KP		 3382}
3383
26d61aad
KP		 3384static bool
3385intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3386{
a031d709
RV		 3387 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3388 struct drm_device *dev = dig_port->base.base.dev;
3389 struct drm_i915_private *dev_priv = dev->dev_private;
3390
9d1a1031
JN		 3391 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3392 sizeof(intel_dp->dpcd)) < 0)
edb39244 3393 return false; /* aux transfer failed */
92fd8fd1 3394
a8e98153 3395 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3396
edb39244
AJ		 3397 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3398 return false; /* DPCD not present */
3399
30d9aa42
SS		 3400 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3401 &intel_dp->sink_count, 1) < 0)
3402 return false;
3403
3404 /*
3405 * Sink count can change between short pulse hpd hence
3406 * a member variable in intel_dp will track any changes
3407 * between short pulse interrupts.
3408 */
3409 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3410
3411 /*
3412 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3413 * a dongle is present but no display. Unless we require to know
3414 * if a dongle is present or not, we don't need to update
3415 * downstream port information. So, an early return here saves
3416 * time from performing other operations which are not required.
3417 */
1034ce70 3418 if (!is_edp(intel_dp) && !intel_dp->sink_count)
30d9aa42
SS		 3419 return false;
3420
2293bb5c
SK		 3421 /* Check if the panel supports PSR */
3422 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3423 if (is_edp(intel_dp)) {
9d1a1031
JN		 3424 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3425 intel_dp->psr_dpcd,
3426 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3427 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3428 dev_priv->psr.sink_support = true;
50003939 3429 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3430 }
474d1ec4
SJ		 3431
3432 if (INTEL_INFO(dev)->gen >= 9 &&
3433 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3434 uint8_t frame_sync_cap;
3435
3436 dev_priv->psr.sink_support = true;
3437 intel_dp_dpcd_read_wake(&intel_dp->aux,
3438 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3439 &frame_sync_cap, 1);
3440 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3441 /* PSR2 needs frame sync as well */
3442 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3443 DRM_DEBUG_KMS("PSR2 %s on sink",
3444 dev_priv->psr.psr2_support ? "supported" : "not supported");
3445 }
86ee27b5
YA		 3446
3447 /* Read the eDP Display control capabilities registers */
3448 memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
3449 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3450 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV,
3451 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3452 sizeof(intel_dp->edp_dpcd)))
3453 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3454 intel_dp->edp_dpcd);
50003939
JN		 3455 }
3456
bc5133d5 3457 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
e588fa18 3458 yesno(intel_dp_source_supports_hbr2(intel_dp)),
742f491d 3459 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
06ea66b6 3460
fc0f8e25 3461 /* Intermediate frequency support */
86ee27b5 3462 if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */
94ca719e 3463 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3464 int i;
3465
fc0f8e25
SJ		 3466 intel_dp_dpcd_read_wake(&intel_dp->aux,
3467 DP_SUPPORTED_LINK_RATES,
94ca719e
VS		 3468 sink_rates,
3469 sizeof(sink_rates));
ea2d8a42 3470
94ca719e
VS		 3471 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3472 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3473
3474 if (val == 0)
3475 break;
3476
af77b974
SJ		 3477 /* Value read is in kHz while drm clock is saved in deca-kHz */
3478 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3479 }
94ca719e 3480 intel_dp->num_sink_rates = i;
fc0f8e25 3481 }
0336400e
VS		 3482
3483 intel_dp_print_rates(intel_dp);
3484
edb39244
AJ		 3485 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3486 DP_DWN_STRM_PORT_PRESENT))
3487 return true; /* native DP sink */
3488
3489 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3490 return true; /* no per-port downstream info */
3491
9d1a1031
JN		 3492 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3493 intel_dp->downstream_ports,
3494 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3495 return false; /* downstream port status fetch failed */
3496
3497 return true;
92fd8fd1
KP		 3498}
3499
0d198328
AJ		 3500static void
3501intel_dp_probe_oui(struct intel_dp *intel_dp)
3502{
3503 u8 buf[3];
3504
3505 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3506 return;
3507
9d1a1031 3508 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3509 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3510 buf[0], buf[1], buf[2]);
3511
9d1a1031 3512 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3513 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3514 buf[0], buf[1], buf[2]);
3515}
3516
0e32b39c
DA		 3517static bool
3518intel_dp_probe_mst(struct intel_dp *intel_dp)
3519{
3520 u8 buf[1];
3521
7cc96139
NS		 3522 if (!i915.enable_dp_mst)
3523 return false;
3524
0e32b39c
DA		 3525 if (!intel_dp->can_mst)
3526 return false;
3527
3528 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3529 return false;
3530
0e32b39c
DA		 3531 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3532 if (buf[0] & DP_MST_CAP) {
3533 DRM_DEBUG_KMS("Sink is MST capable\n");
3534 intel_dp->is_mst = true;
3535 } else {
3536 DRM_DEBUG_KMS("Sink is not MST capable\n");
3537 intel_dp->is_mst = false;
3538 }
3539 }
0e32b39c
DA		 3540
3541 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3542 return intel_dp->is_mst;
3543}
3544
e5a1cab5 3545static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
d2e216d0 3546{
082dcc7c 3547 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3548 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c 3549 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
ad9dc91b 3550 u8 buf;
e5a1cab5 3551 int ret = 0;
c6297843
RV		 3552 int count = 0;
3553 int attempts = 10;
d2e216d0 3554
082dcc7c
RV		 3555 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3556 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3557 ret = -EIO;
3558 goto out;
4373f0f2
PZ		 3559 }
3560
082dcc7c 3561 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
e5a1cab5 3562 buf & ~DP_TEST_SINK_START) < 0) {
082dcc7c 3563 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3564 ret = -EIO;
3565 goto out;
3566 }
d2e216d0 3567
c6297843
RV		 3568 do {
3569 intel_wait_for_vblank(dev, intel_crtc->pipe);
3570
3571 if (drm_dp_dpcd_readb(&intel_dp->aux,
3572 DP_TEST_SINK_MISC, &buf) < 0) {
3573 ret = -EIO;
3574 goto out;
3575 }
3576 count = buf & DP_TEST_COUNT_MASK;
3577 } while (--attempts && count);
3578
3579 if (attempts == 0) {
dc5a9037 3580 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
c6297843
RV		 3581 ret = -ETIMEDOUT;
3582 }
3583
e5a1cab5 3584 out:
082dcc7c 3585 hsw_enable_ips(intel_crtc);
e5a1cab5 3586 return ret;
082dcc7c
RV		 3587}
3588
3589static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3590{
3591 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3592 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c
RV		 3593 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3594 u8 buf;
e5a1cab5
RV		 3595 int ret;
3596
082dcc7c
RV		 3597 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3598 return -EIO;
3599
3600 if (!(buf & DP_TEST_CRC_SUPPORTED))
3601 return -ENOTTY;
3602
3603 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3604 return -EIO;
3605
6d8175da
RV		 3606 if (buf & DP_TEST_SINK_START) {
3607 ret = intel_dp_sink_crc_stop(intel_dp);
3608 if (ret)
3609 return ret;
3610 }
3611
082dcc7c 3612 hsw_disable_ips(intel_crtc);
1dda5f93 3613
9d1a1031 3614 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
082dcc7c
RV		 3615 buf | DP_TEST_SINK_START) < 0) {
3616 hsw_enable_ips(intel_crtc);
3617 return -EIO;
4373f0f2
PZ		 3618 }
3619
d72f9d91 3620 intel_wait_for_vblank(dev, intel_crtc->pipe);
082dcc7c
RV		 3621 return 0;
3622}
3623
3624int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3625{
3626 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3627 struct drm_device *dev = dig_port->base.base.dev;
3628 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3629 u8 buf;
621d4c76 3630 int count, ret;
082dcc7c 3631 int attempts = 6;
082dcc7c
RV		 3632
3633 ret = intel_dp_sink_crc_start(intel_dp);
3634 if (ret)
3635 return ret;
3636
ad9dc91b 3637 do {
621d4c76
RV		 3638 intel_wait_for_vblank(dev, intel_crtc->pipe);
3639
1dda5f93 3640 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 3641 DP_TEST_SINK_MISC, &buf) < 0) {
3642 ret = -EIO;
afe0d67e 3643 goto stop;
4373f0f2 3644 }
621d4c76 3645 count = buf & DP_TEST_COUNT_MASK;
aabc95dc 3646
7e38eeff 3647 } while (--attempts && count == 0);
ad9dc91b
RV		 3648
3649 if (attempts == 0) {
7e38eeff
RV		 3650 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3651 ret = -ETIMEDOUT;
3652 goto stop;
3653 }
3654
3655 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3656 ret = -EIO;
3657 goto stop;
ad9dc91b 3658 }
d2e216d0 3659
afe0d67e 3660stop:
082dcc7c 3661 intel_dp_sink_crc_stop(intel_dp);
4373f0f2 3662 return ret;
d2e216d0
RV		 3663}
3664
a60f0e38
JB		 3665static bool
3666intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3667{
9d1a1031
JN		 3668 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3669 DP_DEVICE_SERVICE_IRQ_VECTOR,
3670 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3671}
3672
0e32b39c
DA		 3673static bool
3674intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3675{
3676 int ret;
3677
3678 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3679 DP_SINK_COUNT_ESI,
3680 sink_irq_vector, 14);
3681 if (ret != 14)
3682 return false;
3683
3684 return true;
3685}
3686
c5d5ab7a
TP		 3687static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3688{
3689 uint8_t test_result = DP_TEST_ACK;
3690 return test_result;
3691}
3692
3693static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3694{
3695 uint8_t test_result = DP_TEST_NAK;
3696 return test_result;
3697}
3698
3699static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 3700{
c5d5ab7a 3701 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 3702 struct intel_connector *intel_connector = intel_dp->attached_connector;
3703 struct drm_connector *connector = &intel_connector->base;
3704
3705 if (intel_connector->detect_edid == NULL ||
ac6f2e29 3706 connector->edid_corrupt ||
559be30c
TP		 3707 intel_dp->aux.i2c_defer_count > 6) {
3708 /* Check EDID read for NACKs, DEFERs and corruption
3709 * (DP CTS 1.2 Core r1.1)
3710 * 4.2.2.4 : Failed EDID read, I2C_NAK
3711 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3712 * 4.2.2.6 : EDID corruption detected
3713 * Use failsafe mode for all cases
3714 */
3715 if (intel_dp->aux.i2c_nack_count > 0 ||
3716 intel_dp->aux.i2c_defer_count > 0)
3717 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3718 intel_dp->aux.i2c_nack_count,
3719 intel_dp->aux.i2c_defer_count);
3720 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3721 } else {
f79b468e
TS		 3722 struct edid *block = intel_connector->detect_edid;
3723
3724 /* We have to write the checksum
3725 * of the last block read
3726 */
3727 block += intel_connector->detect_edid->extensions;
3728
559be30c
TP		 3729 if (!drm_dp_dpcd_write(&intel_dp->aux,
3730 DP_TEST_EDID_CHECKSUM,
f79b468e 3731 &block->checksum,
5a1cc655 3732 1))
559be30c
TP		 3733 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3734
3735 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3736 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3737 }
3738
3739 /* Set test active flag here so userspace doesn't interrupt things */
3740 intel_dp->compliance_test_active = 1;
3741
c5d5ab7a
TP		 3742 return test_result;
3743}
3744
3745static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 3746{
c5d5ab7a
TP		 3747 uint8_t test_result = DP_TEST_NAK;
3748 return test_result;
3749}
3750
3751static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3752{
3753 uint8_t response = DP_TEST_NAK;
3754 uint8_t rxdata = 0;
3755 int status = 0;
3756
c5d5ab7a
TP		 3757 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3758 if (status <= 0) {
3759 DRM_DEBUG_KMS("Could not read test request from sink\n");
3760 goto update_status;
3761 }
3762
3763 switch (rxdata) {
3764 case DP_TEST_LINK_TRAINING:
3765 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3766 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3767 response = intel_dp_autotest_link_training(intel_dp);
3768 break;
3769 case DP_TEST_LINK_VIDEO_PATTERN:
3770 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3771 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3772 response = intel_dp_autotest_video_pattern(intel_dp);
3773 break;
3774 case DP_TEST_LINK_EDID_READ:
3775 DRM_DEBUG_KMS("EDID test requested\n");
3776 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3777 response = intel_dp_autotest_edid(intel_dp);
3778 break;
3779 case DP_TEST_LINK_PHY_TEST_PATTERN:
3780 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3781 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3782 response = intel_dp_autotest_phy_pattern(intel_dp);
3783 break;
3784 default:
3785 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3786 break;
3787 }
3788
3789update_status:
3790 status = drm_dp_dpcd_write(&intel_dp->aux,
3791 DP_TEST_RESPONSE,
3792 &response, 1);
3793 if (status <= 0)
3794 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 3795}
3796
0e32b39c
DA		 3797static int
3798intel_dp_check_mst_status(struct intel_dp *intel_dp)
3799{
3800 bool bret;
3801
3802 if (intel_dp->is_mst) {
3803 u8 esi[16] = { 0 };
3804 int ret = 0;
3805 int retry;
3806 bool handled;
3807 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3808go_again:
3809 if (bret == true) {
3810
3811 /* check link status - esi[10] = 0x200c */
90a6b7b0 3812 if (intel_dp->active_mst_links &&
901c2daf 3813 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
0e32b39c
DA		 3814 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3815 intel_dp_start_link_train(intel_dp);
0e32b39c
DA		 3816 intel_dp_stop_link_train(intel_dp);
3817 }
3818
6f34cc39 3819 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 3820 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3821
3822 if (handled) {
3823 for (retry = 0; retry < 3; retry++) {
3824 int wret;
3825 wret = drm_dp_dpcd_write(&intel_dp->aux,
3826 DP_SINK_COUNT_ESI+1,
3827 &esi[1], 3);
3828 if (wret == 3) {
3829 break;
3830 }
3831 }
3832
3833 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3834 if (bret == true) {
6f34cc39 3835 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 3836 goto go_again;
3837 }
3838 } else
3839 ret = 0;
3840
3841 return ret;
3842 } else {
3843 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3844 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3845 intel_dp->is_mst = false;
3846 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3847 /* send a hotplug event */
3848 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3849 }
3850 }
3851 return -EINVAL;
3852}
3853
5c9114d0
SS		 3854static void
3855intel_dp_check_link_status(struct intel_dp *intel_dp)
3856{
3857 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3858 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3859 u8 link_status[DP_LINK_STATUS_SIZE];
3860
3861 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3862
3863 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3864 DRM_ERROR("Failed to get link status\n");
3865 return;
3866 }
3867
3868 if (!intel_encoder->base.crtc)
3869 return;
3870
3871 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3872 return;
3873
3874 /* if link training is requested we should perform it always */
3875 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
3876 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
3877 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3878 intel_encoder->base.name);
3879 intel_dp_start_link_train(intel_dp);
3880 intel_dp_stop_link_train(intel_dp);
3881 }
3882}
3883
a4fc5ed6
KP		 3884/*
3885 * According to DP spec
3886 * 5.1.2:
3887 * 1. Read DPCD
3888 * 2. Configure link according to Receiver Capabilities
3889 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3890 * 4. Check link status on receipt of hot-plug interrupt
39ff747b
SS		 3891 *
3892 * intel_dp_short_pulse - handles short pulse interrupts
3893 * when full detection is not required.
3894 * Returns %true if short pulse is handled and full detection
3895 * is NOT required and %false otherwise.
a4fc5ed6 3896 */
39ff747b 3897static bool
5c9114d0 3898intel_dp_short_pulse(struct intel_dp *intel_dp)
a4fc5ed6 3899{
5b215bcf 3900 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a60f0e38 3901 u8 sink_irq_vector;
39ff747b
SS		 3902 u8 old_sink_count = intel_dp->sink_count;
3903 bool ret;
5b215bcf 3904
4df6960e
SS		 3905 /*
3906 * Clearing compliance test variables to allow capturing
3907 * of values for next automated test request.
3908 */
3909 intel_dp->compliance_test_active = 0;
3910 intel_dp->compliance_test_type = 0;
3911 intel_dp->compliance_test_data = 0;
3912
39ff747b
SS		 3913 /*
3914 * Now read the DPCD to see if it's actually running
3915 * If the current value of sink count doesn't match with
3916 * the value that was stored earlier or dpcd read failed
3917 * we need to do full detection
3918 */
3919 ret = intel_dp_get_dpcd(intel_dp);
3920
3921 if ((old_sink_count != intel_dp->sink_count) || !ret) {
3922 /* No need to proceed if we are going to do full detect */
3923 return false;
59cd09e1
JB		 3924 }
3925
a60f0e38
JB		 3926 /* Try to read the source of the interrupt */
3927 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3928 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3929 /* Clear interrupt source */
9d1a1031
JN		 3930 drm_dp_dpcd_writeb(&intel_dp->aux,
3931 DP_DEVICE_SERVICE_IRQ_VECTOR,
3932 sink_irq_vector);
a60f0e38
JB		 3933
3934 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 3935 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 3936 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3937 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3938 }
3939
5c9114d0
SS		 3940 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3941 intel_dp_check_link_status(intel_dp);
3942 drm_modeset_unlock(&dev->mode_config.connection_mutex);
39ff747b
SS		 3943
3944 return true;
a4fc5ed6 3945}
a4fc5ed6 3946
caf9ab24 3947/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3948static enum drm_connector_status
26d61aad 3949intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3950{
caf9ab24 3951 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3952 uint8_t type;
3953
3954 if (!intel_dp_get_dpcd(intel_dp))
3955 return connector_status_disconnected;
3956
1034ce70
SS		 3957 if (is_edp(intel_dp))
3958 return connector_status_connected;
3959
caf9ab24
AJ		 3960 /* if there's no downstream port, we're done */
3961 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3962 return connector_status_connected;
caf9ab24
AJ		 3963
3964 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3965 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3966 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
9d1a1031 3967
30d9aa42
SS		 3968 return intel_dp->sink_count ?
3969 connector_status_connected : connector_status_disconnected;
caf9ab24
AJ		 3970 }
3971
3972 /* If no HPD, poke DDC gently */
0b99836f 3973 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3974 return connector_status_connected;
caf9ab24
AJ		 3975
3976 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3977 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3978 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3979 if (type == DP_DS_PORT_TYPE_VGA ||
3980 type == DP_DS_PORT_TYPE_NON_EDID)
3981 return connector_status_unknown;
3982 } else {
3983 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3984 DP_DWN_STRM_PORT_TYPE_MASK;
3985 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3986 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3987 return connector_status_unknown;
3988 }
caf9ab24
AJ		 3989
3990 /* Anything else is out of spec, warn and ignore */
3991 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3992 return connector_status_disconnected;
71ba9000
AJ		 3993}
3994
d410b56d
CW		 3995static enum drm_connector_status
3996edp_detect(struct intel_dp *intel_dp)
3997{
3998 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3999 enum drm_connector_status status;
4000
4001 status = intel_panel_detect(dev);
4002 if (status == connector_status_unknown)
4003 status = connector_status_connected;
4004
4005 return status;
4006}
4007
b93433cc
JN		 4008static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4009 struct intel_digital_port *port)
5eb08b69 4010{
b93433cc 4011 u32 bit;
01cb9ea6 4012
0df53b77
JN		 4013 switch (port->port) {
4014 case PORT_A:
4015 return true;
4016 case PORT_B:
4017 bit = SDE_PORTB_HOTPLUG;
4018 break;
4019 case PORT_C:
4020 bit = SDE_PORTC_HOTPLUG;
4021 break;
4022 case PORT_D:
4023 bit = SDE_PORTD_HOTPLUG;
4024 break;
4025 default:
4026 MISSING_CASE(port->port);
4027 return false;
4028 }
4029
4030 return I915_READ(SDEISR) & bit;
4031}
4032
4033static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4034 struct intel_digital_port *port)
4035{
4036 u32 bit;
4037
4038 switch (port->port) {
4039 case PORT_A:
4040 return true;
4041 case PORT_B:
4042 bit = SDE_PORTB_HOTPLUG_CPT;
4043 break;
4044 case PORT_C:
4045 bit = SDE_PORTC_HOTPLUG_CPT;
4046 break;
4047 case PORT_D:
4048 bit = SDE_PORTD_HOTPLUG_CPT;
4049 break;
a78695d3
JN		 4050 case PORT_E:
4051 bit = SDE_PORTE_HOTPLUG_SPT;
4052 break;
0df53b77
JN		 4053 default:
4054 MISSING_CASE(port->port);
4055 return false;
b93433cc 4056 }
1b469639 4057
b93433cc 4058 return I915_READ(SDEISR) & bit;
5eb08b69
ZW		 4059}
4060
7e66bcf2 4061static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
1d245987 4062 struct intel_digital_port *port)
a4fc5ed6 4063{
9642c81c 4064 u32 bit;
5eb08b69 4065
9642c81c
JN		 4066 switch (port->port) {
4067 case PORT_B:
4068 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4069 break;
4070 case PORT_C:
4071 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4072 break;
4073 case PORT_D:
4074 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4075 break;
4076 default:
4077 MISSING_CASE(port->port);
4078 return false;
4079 }
4080
4081 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4082}
4083
0780cd36
VS		 4084static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4085 struct intel_digital_port *port)
9642c81c
JN		 4086{
4087 u32 bit;
4088
4089 switch (port->port) {
4090 case PORT_B:
0780cd36 4091 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4092 break;
4093 case PORT_C:
0780cd36 4094 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4095 break;
4096 case PORT_D:
0780cd36 4097 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4098 break;
4099 default:
4100 MISSING_CASE(port->port);
4101 return false;
a4fc5ed6
KP		 4102 }
4103
1d245987 4104 return I915_READ(PORT_HOTPLUG_STAT) & bit;
2a592bec
DA		 4105}
4106
e464bfde 4107static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
e2ec35a5 4108 struct intel_digital_port *intel_dig_port)
e464bfde 4109{
e2ec35a5
SJ		 4110 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4111 enum port port;
e464bfde
JN		 4112 u32 bit;
4113
e2ec35a5
SJ		 4114 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4115 switch (port) {
e464bfde
JN		 4116 case PORT_A:
4117 bit = BXT_DE_PORT_HP_DDIA;
4118 break;
4119 case PORT_B:
4120 bit = BXT_DE_PORT_HP_DDIB;
4121 break;
4122 case PORT_C:
4123 bit = BXT_DE_PORT_HP_DDIC;
4124 break;
4125 default:
e2ec35a5 4126 MISSING_CASE(port);
e464bfde
JN		 4127 return false;
4128 }
4129
4130 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4131}
4132
7e66bcf2
JN		 4133/*
4134 * intel_digital_port_connected - is the specified port connected?
4135 * @dev_priv: i915 private structure
4136 * @port: the port to test
4137 *
4138 * Return %true if @port is connected, %false otherwise.
4139 */
237ed86c 4140bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
7e66bcf2
JN		 4141 struct intel_digital_port *port)
4142{
0df53b77 4143 if (HAS_PCH_IBX(dev_priv))
7e66bcf2 4144 return ibx_digital_port_connected(dev_priv, port);
22824fac 4145 else if (HAS_PCH_SPLIT(dev_priv))
0df53b77 4146 return cpt_digital_port_connected(dev_priv, port);
e464bfde
JN		 4147 else if (IS_BROXTON(dev_priv))
4148 return bxt_digital_port_connected(dev_priv, port);
0780cd36
VS		 4149 else if (IS_GM45(dev_priv))
4150 return gm45_digital_port_connected(dev_priv, port);
7e66bcf2
JN		 4151 else
4152 return g4x_digital_port_connected(dev_priv, port);
4153}
4154
8c241fef 4155static struct edid *
beb60608 4156intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4157{
beb60608 4158 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4159
9cd300e0
JN		 4160 /* use cached edid if we have one */
4161 if (intel_connector->edid) {
9cd300e0
JN		 4162 /* invalid edid */
4163 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4164 return NULL;
4165
55e9edeb 4166 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4167 } else
4168 return drm_get_edid(&intel_connector->base,
4169 &intel_dp->aux.ddc);
4170}
8c241fef 4171
beb60608
CW		 4172static void
4173intel_dp_set_edid(struct intel_dp *intel_dp)
4174{
4175 struct intel_connector *intel_connector = intel_dp->attached_connector;
4176 struct edid *edid;
8c241fef 4177
f21a2198 4178 intel_dp_unset_edid(intel_dp);
beb60608
CW		 4179 edid = intel_dp_get_edid(intel_dp);
4180 intel_connector->detect_edid = edid;
4181
4182 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4183 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4184 else
4185 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4186}
4187
beb60608
CW		 4188static void
4189intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4190{
beb60608 4191 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4192
beb60608
CW		 4193 kfree(intel_connector->detect_edid);
4194 intel_connector->detect_edid = NULL;
9cd300e0 4195
beb60608
CW		 4196 intel_dp->has_audio = false;
4197}
d6f24d0f 4198
f21a2198
SS		 4199static void
4200intel_dp_long_pulse(struct intel_connector *intel_connector)
a9756bb5 4201{
f21a2198 4202 struct drm_connector *connector = &intel_connector->base;
a9756bb5 4203 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4204 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4205 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4206 struct drm_device *dev = connector->dev;
a9756bb5 4207 enum drm_connector_status status;
671dedd2 4208 enum intel_display_power_domain power_domain;
0e32b39c 4209 bool ret;
09b1eb13 4210 u8 sink_irq_vector;
a9756bb5 4211
25f78f58
VS		 4212 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4213 intel_display_power_get(to_i915(dev), power_domain);
a9756bb5 4214
d410b56d
CW		 4215 /* Can't disconnect eDP, but you can close the lid... */
4216 if (is_edp(intel_dp))
4217 status = edp_detect(intel_dp);
c555a81d
ACO		 4218 else if (intel_digital_port_connected(to_i915(dev),
4219 dp_to_dig_port(intel_dp)))
4220 status = intel_dp_detect_dpcd(intel_dp);
a9756bb5 4221 else
c555a81d
ACO		 4222 status = connector_status_disconnected;
4223
4df6960e
SS		 4224 if (status != connector_status_connected) {
4225 intel_dp->compliance_test_active = 0;
4226 intel_dp->compliance_test_type = 0;
4227 intel_dp->compliance_test_data = 0;
4228
0e505a08 4229 if (intel_dp->is_mst) {
4230 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4231 intel_dp->is_mst,
4232 intel_dp->mst_mgr.mst_state);
4233 intel_dp->is_mst = false;
4234 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4235 intel_dp->is_mst);
4236 }
4237
c8c8fb33 4238 goto out;
4df6960e 4239 }
a9756bb5 4240
f21a2198
SS		 4241 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4242 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4243
0d198328
AJ		 4244 intel_dp_probe_oui(intel_dp);
4245
0e32b39c
DA		 4246 ret = intel_dp_probe_mst(intel_dp);
4247 if (ret) {
f21a2198
SS		 4248 /*
4249 * If we are in MST mode then this connector
4250 * won't appear connected or have anything
4251 * with EDID on it
4252 */
0e32b39c
DA		 4253 status = connector_status_disconnected;
4254 goto out;
7d23e3c3
SS		 4255 } else if (connector->status == connector_status_connected) {
4256 /*
4257 * If display was connected already and is still connected
4258 * check links status, there has been known issues of
4259 * link loss triggerring long pulse!!!!
4260 */
4261 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4262 intel_dp_check_link_status(intel_dp);
4263 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4264 goto out;
0e32b39c
DA		 4265 }
4266
4df6960e
SS		 4267 /*
4268 * Clearing NACK and defer counts to get their exact values
4269 * while reading EDID which are required by Compliance tests
4270 * 4.2.2.4 and 4.2.2.5
4271 */
4272 intel_dp->aux.i2c_nack_count = 0;
4273 intel_dp->aux.i2c_defer_count = 0;
4274
beb60608 4275 intel_dp_set_edid(intel_dp);
a9756bb5 4276
c8c8fb33 4277 status = connector_status_connected;
7d23e3c3 4278 intel_dp->detect_done = true;
c8c8fb33 4279
09b1eb13
TP		 4280 /* Try to read the source of the interrupt */
4281 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4282 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4283 /* Clear interrupt source */
4284 drm_dp_dpcd_writeb(&intel_dp->aux,
4285 DP_DEVICE_SERVICE_IRQ_VECTOR,
4286 sink_irq_vector);
4287
4288 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4289 intel_dp_handle_test_request(intel_dp);
4290 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4291 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4292 }
4293
c8c8fb33 4294out:
0e505a08 4295 if ((status != connector_status_connected) &&
4296 (intel_dp->is_mst == false))
f21a2198 4297 intel_dp_unset_edid(intel_dp);
7d23e3c3 4298
25f78f58 4299 intel_display_power_put(to_i915(dev), power_domain);
f21a2198
SS		 4300 return;
4301}
4302
4303static enum drm_connector_status
4304intel_dp_detect(struct drm_connector *connector, bool force)
4305{
4306 struct intel_dp *intel_dp = intel_attached_dp(connector);
4307 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4308 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4309 struct intel_connector *intel_connector = to_intel_connector(connector);
4310
4311 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4312 connector->base.id, connector->name);
4313
4314 if (intel_dp->is_mst) {
4315 /* MST devices are disconnected from a monitor POV */
4316 intel_dp_unset_edid(intel_dp);
4317 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4318 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4319 return connector_status_disconnected;
4320 }
4321
7d23e3c3
SS		 4322 /* If full detect is not performed yet, do a full detect */
4323 if (!intel_dp->detect_done)
4324 intel_dp_long_pulse(intel_dp->attached_connector);
4325
4326 intel_dp->detect_done = false;
f21a2198
SS		 4327
4328 if (intel_connector->detect_edid)
4329 return connector_status_connected;
4330 else
4331 return connector_status_disconnected;
a4fc5ed6
KP		 4332}
4333
beb60608
CW		 4334static void
4335intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4336{
df0e9248 4337 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4338 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
25f78f58 4339 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
671dedd2 4340 enum intel_display_power_domain power_domain;
a4fc5ed6 4341
beb60608
CW		 4342 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4343 connector->base.id, connector->name);
4344 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4345
beb60608
CW		 4346 if (connector->status != connector_status_connected)
4347 return;
671dedd2 4348
25f78f58
VS		 4349 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4350 intel_display_power_get(dev_priv, power_domain);
beb60608
CW		 4351
4352 intel_dp_set_edid(intel_dp);
4353
25f78f58 4354 intel_display_power_put(dev_priv, power_domain);
beb60608
CW		 4355
4356 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4357 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4358}
4359
4360static int intel_dp_get_modes(struct drm_connector *connector)
4361{
4362 struct intel_connector *intel_connector = to_intel_connector(connector);
4363 struct edid *edid;
4364
4365 edid = intel_connector->detect_edid;
4366 if (edid) {
4367 int ret = intel_connector_update_modes(connector, edid);
4368 if (ret)
4369 return ret;
4370 }
32f9d658 4371
f8779fda 4372 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4373 if (is_edp(intel_attached_dp(connector)) &&
4374 intel_connector->panel.fixed_mode) {
f8779fda 4375 struct drm_display_mode *mode;
beb60608
CW		 4376
4377 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4378 intel_connector->panel.fixed_mode);
f8779fda 4379 if (mode) {
32f9d658
ZW		 4380 drm_mode_probed_add(connector, mode);
4381 return 1;
4382 }
4383 }
beb60608 4384
32f9d658 4385 return 0;
a4fc5ed6
KP		 4386}
4387
1aad7ac0
CW		 4388static bool
4389intel_dp_detect_audio(struct drm_connector *connector)
4390{
1aad7ac0 4391 bool has_audio = false;
beb60608 4392 struct edid *edid;
1aad7ac0 4393
beb60608
CW		 4394 edid = to_intel_connector(connector)->detect_edid;
4395 if (edid)
1aad7ac0 4396 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4397
1aad7ac0
CW		 4398 return has_audio;
4399}
4400
f684960e
CW		 4401static int
4402intel_dp_set_property(struct drm_connector *connector,
4403 struct drm_property *property,
4404 uint64_t val)
4405{
e953fd7b 4406 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4407 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4408 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4409 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4410 int ret;
4411
662595df 4412 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4413 if (ret)
4414 return ret;
4415
3f43c48d 4416 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4417 int i = val;
4418 bool has_audio;
4419
4420 if (i == intel_dp->force_audio)
f684960e
CW		 4421 return 0;
4422
1aad7ac0 4423 intel_dp->force_audio = i;
f684960e 4424
c3e5f67b 4425 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4426 has_audio = intel_dp_detect_audio(connector);
4427 else
c3e5f67b 4428 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4429
4430 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4431 return 0;
4432
1aad7ac0 4433 intel_dp->has_audio = has_audio;
f684960e
CW		 4434 goto done;
4435 }
4436
e953fd7b 4437 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 4438 bool old_auto = intel_dp->color_range_auto;
0f2a2a75 4439 bool old_range = intel_dp->limited_color_range;
ae4edb80 4440
55bc60db
VS		 4441 switch (val) {
4442 case INTEL_BROADCAST_RGB_AUTO:
4443 intel_dp->color_range_auto = true;
4444 break;
4445 case INTEL_BROADCAST_RGB_FULL:
4446 intel_dp->color_range_auto = false;
0f2a2a75 4447 intel_dp->limited_color_range = false;
55bc60db
VS		 4448 break;
4449 case INTEL_BROADCAST_RGB_LIMITED:
4450 intel_dp->color_range_auto = false;
0f2a2a75 4451 intel_dp->limited_color_range = true;
55bc60db
VS		 4452 break;
4453 default:
4454 return -EINVAL;
4455 }
ae4edb80
DV		 4456
4457 if (old_auto == intel_dp->color_range_auto &&
0f2a2a75 4458 old_range == intel_dp->limited_color_range)
ae4edb80
DV		 4459 return 0;
4460
e953fd7b
CW		 4461 goto done;
4462 }
4463
53b41837
YN		 4464 if (is_edp(intel_dp) &&
4465 property == connector->dev->mode_config.scaling_mode_property) {
4466 if (val == DRM_MODE_SCALE_NONE) {
4467 DRM_DEBUG_KMS("no scaling not supported\n");
4468 return -EINVAL;
4469 }
234126c6
VS		 4470 if (HAS_GMCH_DISPLAY(dev_priv) &&
4471 val == DRM_MODE_SCALE_CENTER) {
4472 DRM_DEBUG_KMS("centering not supported\n");
4473 return -EINVAL;
4474 }
53b41837
YN		 4475
4476 if (intel_connector->panel.fitting_mode == val) {
4477 /* the eDP scaling property is not changed */
4478 return 0;
4479 }
4480 intel_connector->panel.fitting_mode = val;
4481
4482 goto done;
4483 }
4484
f684960e
CW		 4485 return -EINVAL;
4486
4487done:
c0c36b94
CW		 4488 if (intel_encoder->base.crtc)
4489 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4490
4491 return 0;
4492}
4493
a4fc5ed6 4494static void
73845adf 4495intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4496{
1d508706 4497 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4498
10e972d3 4499 kfree(intel_connector->detect_edid);
beb60608 4500
9cd300e0
JN		 4501 if (!IS_ERR_OR_NULL(intel_connector->edid))
4502 kfree(intel_connector->edid);
4503
acd8db10
PZ		 4504 /* Can't call is_edp() since the encoder may have been destroyed
4505 * already. */
4506 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4507 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4508
a4fc5ed6 4509 drm_connector_cleanup(connector);
55f78c43 4510 kfree(connector);
a4fc5ed6
KP		 4511}
4512
00c09d70 4513void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4514{
da63a9f2
PZ		 4515 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4516 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4517
0e32b39c 4518 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4519 if (is_edp(intel_dp)) {
4520 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4521 /*
4522 * vdd might still be enabled do to the delayed vdd off.
4523 * Make sure vdd is actually turned off here.
4524 */
773538e8 4525 pps_lock(intel_dp);
4be73780 4526 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4527 pps_unlock(intel_dp);
4528
01527b31
CT		 4529 if (intel_dp->edp_notifier.notifier_call) {
4530 unregister_reboot_notifier(&intel_dp->edp_notifier);
4531 intel_dp->edp_notifier.notifier_call = NULL;
4532 }
bd943159 4533 }
c8bd0e49 4534 drm_encoder_cleanup(encoder);
da63a9f2 4535 kfree(intel_dig_port);
24d05927
DV		 4536}
4537
bf93ba67 4538void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
07f9cd0b
ID		 4539{
4540 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4541
4542 if (!is_edp(intel_dp))
4543 return;
4544
951468f3
VS		 4545 /*
4546 * vdd might still be enabled do to the delayed vdd off.
4547 * Make sure vdd is actually turned off here.
4548 */
afa4e53a 4549 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4550 pps_lock(intel_dp);
07f9cd0b 4551 edp_panel_vdd_off_sync(intel_dp);
773538e8 4552 pps_unlock(intel_dp);
07f9cd0b
ID		 4553}
4554
49e6bc51
VS		 4555static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4556{
4557 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4558 struct drm_device *dev = intel_dig_port->base.base.dev;
4559 struct drm_i915_private *dev_priv = dev->dev_private;
4560 enum intel_display_power_domain power_domain;
4561
4562 lockdep_assert_held(&dev_priv->pps_mutex);
4563
4564 if (!edp_have_panel_vdd(intel_dp))
4565 return;
4566
4567 /*
4568 * The VDD bit needs a power domain reference, so if the bit is
4569 * already enabled when we boot or resume, grab this reference and
4570 * schedule a vdd off, so we don't hold on to the reference
4571 * indefinitely.
4572 */
4573 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
25f78f58 4574 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
49e6bc51
VS		 4575 intel_display_power_get(dev_priv, power_domain);
4576
4577 edp_panel_vdd_schedule_off(intel_dp);
4578}
4579
bf93ba67 4580void intel_dp_encoder_reset(struct drm_encoder *encoder)
6d93c0c4 4581{
49e6bc51
VS		 4582 struct intel_dp *intel_dp;
4583
4584 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4585 return;
4586
4587 intel_dp = enc_to_intel_dp(encoder);
4588
4589 pps_lock(intel_dp);
4590
4591 /*
4592 * Read out the current power sequencer assignment,
4593 * in case the BIOS did something with it.
4594 */
666a4537 4595 if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
49e6bc51
VS		 4596 vlv_initial_power_sequencer_setup(intel_dp);
4597
4598 intel_edp_panel_vdd_sanitize(intel_dp);
4599
4600 pps_unlock(intel_dp);
6d93c0c4
ID		 4601}
4602
a4fc5ed6 4603static const struct drm_connector_funcs intel_dp_connector_funcs = {
4d688a2a 4604 .dpms = drm_atomic_helper_connector_dpms,
a4fc5ed6 4605 .detect = intel_dp_detect,
beb60608 4606 .force = intel_dp_force,
a4fc5ed6 4607 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4608 .set_property = intel_dp_set_property,
2545e4a6 4609 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4610 .destroy = intel_dp_connector_destroy,
c6f95f27 4611 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4612 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4613};
4614
4615static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4616 .get_modes = intel_dp_get_modes,
4617 .mode_valid = intel_dp_mode_valid,
df0e9248 4618 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4619};
4620
a4fc5ed6 4621static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4622 .reset = intel_dp_encoder_reset,
24d05927 4623 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4624};
4625
b2c5c181 4626enum irqreturn
13cf5504
DA		 4627intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4628{
4629 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4630 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4631 struct drm_device *dev = intel_dig_port->base.base.dev;
4632 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4633 enum intel_display_power_domain power_domain;
b2c5c181 4634 enum irqreturn ret = IRQ_NONE;
1c767b33 4635
2540058f
TI		 4636 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4637 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
0e32b39c 4638 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4639
7a7f84cc
VS		 4640 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4641 /*
4642 * vdd off can generate a long pulse on eDP which
4643 * would require vdd on to handle it, and thus we
4644 * would end up in an endless cycle of
4645 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4646 */
4647 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4648 port_name(intel_dig_port->port));
a8b3d52f 4649 return IRQ_HANDLED;
7a7f84cc
VS		 4650 }
4651
26fbb774
VS		 4652 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4653 port_name(intel_dig_port->port),
0e32b39c 4654 long_hpd ? "long" : "short");
13cf5504 4655
25f78f58 4656 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1c767b33
ID		 4657 intel_display_power_get(dev_priv, power_domain);
4658
0e32b39c 4659 if (long_hpd) {
5fa836a9
MK		 4660 /* indicate that we need to restart link training */
4661 intel_dp->train_set_valid = false;
2a592bec 4662
7d23e3c3
SS		 4663 intel_dp_long_pulse(intel_dp->attached_connector);
4664 if (intel_dp->is_mst)
4665 ret = IRQ_HANDLED;
4666 goto put_power;
0e32b39c 4667
0e32b39c
DA		 4668 } else {
4669 if (intel_dp->is_mst) {
7d23e3c3
SS		 4670 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4671 /*
4672 * If we were in MST mode, and device is not
4673 * there, get out of MST mode
4674 */
4675 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4676 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4677 intel_dp->is_mst = false;
4678 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4679 intel_dp->is_mst);
4680 goto put_power;
4681 }
0e32b39c
DA		 4682 }
4683
39ff747b
SS		 4684 if (!intel_dp->is_mst) {
4685 if (!intel_dp_short_pulse(intel_dp)) {
4686 intel_dp_long_pulse(intel_dp->attached_connector);
4687 goto put_power;
4688 }
4689 }
0e32b39c 4690 }
b2c5c181
DV		 4691
4692 ret = IRQ_HANDLED;
4693
1c767b33
ID		 4694put_power:
4695 intel_display_power_put(dev_priv, power_domain);
4696
4697 return ret;
13cf5504
DA		 4698}
4699
477ec328 4700/* check the VBT to see whether the eDP is on another port */
5d8a7752 4701bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4702{
4703 struct drm_i915_private *dev_priv = dev->dev_private;
36e83a18 4704
53ce81a7
VS		 4705 /*
4706 * eDP not supported on g4x. so bail out early just
4707 * for a bit extra safety in case the VBT is bonkers.
4708 */
4709 if (INTEL_INFO(dev)->gen < 5)
4710 return false;
4711
3b32a35b
VS		 4712 if (port == PORT_A)
4713 return true;
4714
951d9efe 4715 return intel_bios_is_port_edp(dev_priv, port);
36e83a18
ZY		 4716}
4717
0e32b39c 4718void
f684960e
CW		 4719intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4720{
53b41837
YN		 4721 struct intel_connector *intel_connector = to_intel_connector(connector);
4722
3f43c48d 4723 intel_attach_force_audio_property(connector);
e953fd7b 4724 intel_attach_broadcast_rgb_property(connector);
55bc60db 4725 intel_dp->color_range_auto = true;
53b41837
YN		 4726
4727 if (is_edp(intel_dp)) {
4728 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4729 drm_object_attach_property(
4730 &connector->base,
53b41837 4731 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4732 DRM_MODE_SCALE_ASPECT);
4733 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4734 }
f684960e
CW		 4735}
4736
dada1a9f
ID		 4737static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4738{
d28d4731 4739 intel_dp->panel_power_off_time = ktime_get_boottime();
dada1a9f
ID		 4740 intel_dp->last_power_on = jiffies;
4741 intel_dp->last_backlight_off = jiffies;
4742}
4743
67a54566
DV		 4744static void
4745intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4746 struct intel_dp *intel_dp)
67a54566
DV		 4747{
4748 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4749 struct edp_power_seq cur, vbt, spec,
4750 *final = &intel_dp->pps_delays;
b0a08bec 4751 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
f0f59a00 4752 i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4753
e39b999a
VS		 4754 lockdep_assert_held(&dev_priv->pps_mutex);
4755
81ddbc69
VS		 4756 /* already initialized? */
4757 if (final->t11_t12 != 0)
4758 return;
4759
b0a08bec
VK		 4760 if (IS_BROXTON(dev)) {
4761 /*
4762 * TODO: BXT has 2 sets of PPS registers.
4763 * Correct Register for Broxton need to be identified
4764 * using VBT. hardcoding for now
4765 */
4766 pp_ctrl_reg = BXT_PP_CONTROL(0);
4767 pp_on_reg = BXT_PP_ON_DELAYS(0);
4768 pp_off_reg = BXT_PP_OFF_DELAYS(0);
4769 } else if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4770 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4771 pp_on_reg = PCH_PP_ON_DELAYS;
4772 pp_off_reg = PCH_PP_OFF_DELAYS;
4773 pp_div_reg = PCH_PP_DIVISOR;
4774 } else {
bf13e81b
JN		 4775 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4776
4777 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4778 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4779 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4780 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4781 }
67a54566
DV		 4782
4783 /* Workaround: Need to write PP_CONTROL with the unlock key as
4784 * the very first thing. */
b0a08bec 4785 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 4786
453c5420
JB		 4787 pp_on = I915_READ(pp_on_reg);
4788 pp_off = I915_READ(pp_off_reg);
b0a08bec
VK		 4789 if (!IS_BROXTON(dev)) {
4790 I915_WRITE(pp_ctrl_reg, pp_ctl);
4791 pp_div = I915_READ(pp_div_reg);
4792 }
67a54566
DV		 4793
4794 /* Pull timing values out of registers */
4795 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4796 PANEL_POWER_UP_DELAY_SHIFT;
4797
4798 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4799 PANEL_LIGHT_ON_DELAY_SHIFT;
4800
4801 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4802 PANEL_LIGHT_OFF_DELAY_SHIFT;
4803
4804 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4805 PANEL_POWER_DOWN_DELAY_SHIFT;
4806
b0a08bec
VK		 4807 if (IS_BROXTON(dev)) {
4808 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4809 BXT_POWER_CYCLE_DELAY_SHIFT;
4810 if (tmp > 0)
4811 cur.t11_t12 = (tmp - 1) * 1000;
4812 else
4813 cur.t11_t12 = 0;
4814 } else {
4815 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 4816 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 4817 }
67a54566
DV		 4818
4819 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4820 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4821
6aa23e65 4822 vbt = dev_priv->vbt.edp.pps;
67a54566
DV		 4823
4824 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4825 * our hw here, which are all in 100usec. */
4826 spec.t1_t3 = 210 * 10;
4827 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4828 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4829 spec.t10 = 500 * 10;
4830 /* This one is special and actually in units of 100ms, but zero
4831 * based in the hw (so we need to add 100 ms). But the sw vbt
4832 * table multiplies it with 1000 to make it in units of 100usec,
4833 * too. */
4834 spec.t11_t12 = (510 + 100) * 10;
4835
4836 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4837 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4838
4839 /* Use the max of the register settings and vbt. If both are
4840 * unset, fall back to the spec limits. */
36b5f425 4841#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4842 spec.field : \
4843 max(cur.field, vbt.field))
4844 assign_final(t1_t3);
4845 assign_final(t8);
4846 assign_final(t9);
4847 assign_final(t10);
4848 assign_final(t11_t12);
4849#undef assign_final
4850
36b5f425 4851#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4852 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4853 intel_dp->backlight_on_delay = get_delay(t8);
4854 intel_dp->backlight_off_delay = get_delay(t9);
4855 intel_dp->panel_power_down_delay = get_delay(t10);
4856 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4857#undef get_delay
4858
f30d26e4
JN		 4859 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4860 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4861 intel_dp->panel_power_cycle_delay);
4862
4863 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4864 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4865}
4866
4867static void
4868intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4869 struct intel_dp *intel_dp)
f30d26e4
JN		 4870{
4871 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 4872 u32 pp_on, pp_off, pp_div, port_sel = 0;
e7dc33f3 4873 int div = dev_priv->rawclk_freq / 1000;
f0f59a00 4874 i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg;
ad933b56 4875 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4876 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4877
e39b999a 4878 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 4879
b0a08bec
VK		 4880 if (IS_BROXTON(dev)) {
4881 /*
4882 * TODO: BXT has 2 sets of PPS registers.
4883 * Correct Register for Broxton need to be identified
4884 * using VBT. hardcoding for now
4885 */
4886 pp_ctrl_reg = BXT_PP_CONTROL(0);
4887 pp_on_reg = BXT_PP_ON_DELAYS(0);
4888 pp_off_reg = BXT_PP_OFF_DELAYS(0);
4889
4890 } else if (HAS_PCH_SPLIT(dev)) {
453c5420
JB		 4891 pp_on_reg = PCH_PP_ON_DELAYS;
4892 pp_off_reg = PCH_PP_OFF_DELAYS;
4893 pp_div_reg = PCH_PP_DIVISOR;
4894 } else {
bf13e81b
JN		 4895 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4896
4897 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4898 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4899 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4900 }
4901
b2f19d1a
PZ		 4902 /*
4903 * And finally store the new values in the power sequencer. The
4904 * backlight delays are set to 1 because we do manual waits on them. For
4905 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4906 * we'll end up waiting for the backlight off delay twice: once when we
4907 * do the manual sleep, and once when we disable the panel and wait for
4908 * the PP_STATUS bit to become zero.
4909 */
f30d26e4 4910 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4911 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4912 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4913 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4914 /* Compute the divisor for the pp clock, simply match the Bspec
4915 * formula. */
b0a08bec
VK		 4916 if (IS_BROXTON(dev)) {
4917 pp_div = I915_READ(pp_ctrl_reg);
4918 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
4919 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
4920 << BXT_POWER_CYCLE_DELAY_SHIFT);
4921 } else {
4922 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4923 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4924 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4925 }
67a54566
DV		 4926
4927 /* Haswell doesn't have any port selection bits for the panel
4928 * power sequencer any more. */
666a4537 4929 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
ad933b56 4930 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4931 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4932 if (port == PORT_A)
a24c144c 4933 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4934 else
a24c144c 4935 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4936 }
4937
453c5420
JB		 4938 pp_on |= port_sel;
4939
4940 I915_WRITE(pp_on_reg, pp_on);
4941 I915_WRITE(pp_off_reg, pp_off);
b0a08bec
VK		 4942 if (IS_BROXTON(dev))
4943 I915_WRITE(pp_ctrl_reg, pp_div);
4944 else
4945 I915_WRITE(pp_div_reg, pp_div);
67a54566 4946
67a54566 4947 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4948 I915_READ(pp_on_reg),
4949 I915_READ(pp_off_reg),
b0a08bec
VK		 4950 IS_BROXTON(dev) ?
4951 (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
453c5420 4952 I915_READ(pp_div_reg));
f684960e
CW		 4953}
4954
b33a2815
VK		 4955/**
4956 * intel_dp_set_drrs_state - program registers for RR switch to take effect
4957 * @dev: DRM device
4958 * @refresh_rate: RR to be programmed
4959 *
4960 * This function gets called when refresh rate (RR) has to be changed from
4961 * one frequency to another. Switches can be between high and low RR
4962 * supported by the panel or to any other RR based on media playback (in
4963 * this case, RR value needs to be passed from user space).
4964 *
4965 * The caller of this function needs to take a lock on dev_priv->drrs.
4966 */
96178eeb 4967static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 4968{
4969 struct drm_i915_private *dev_priv = dev->dev_private;
4970 struct intel_encoder *encoder;
96178eeb
VK		 4971 struct intel_digital_port *dig_port = NULL;
4972 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 4973 struct intel_crtc_state *config = NULL;
439d7ac0 4974 struct intel_crtc *intel_crtc = NULL;
96178eeb 4975 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 4976
4977 if (refresh_rate <= 0) {
4978 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4979 return;
4980 }
4981
96178eeb
VK		 4982 if (intel_dp == NULL) {
4983 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 4984 return;
4985 }
4986
1fcc9d1c 4987 /*
e4d59f6b
RV		 4988 * FIXME: This needs proper synchronization with psr state for some
4989 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 4990 */
439d7ac0 4991
96178eeb
VK		 4992 dig_port = dp_to_dig_port(intel_dp);
4993 encoder = &dig_port->base;
723f9aab 4994 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 4995
4996 if (!intel_crtc) {
4997 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4998 return;
4999 }
5000
6e3c9717 5001 config = intel_crtc->config;
439d7ac0 5002
96178eeb 5003 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5004 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5005 return;
5006 }
5007
96178eeb
VK		 5008 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5009 refresh_rate)
439d7ac0
PB		 5010 index = DRRS_LOW_RR;
5011
96178eeb 5012 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5013 DRM_DEBUG_KMS(
5014 "DRRS requested for previously set RR...ignoring\n");
5015 return;
5016 }
5017
5018 if (!intel_crtc->active) {
5019 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5020 return;
5021 }
5022
44395bfe 5023 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5024 switch (index) {
5025 case DRRS_HIGH_RR:
5026 intel_dp_set_m_n(intel_crtc, M1_N1);
5027 break;
5028 case DRRS_LOW_RR:
5029 intel_dp_set_m_n(intel_crtc, M2_N2);
5030 break;
5031 case DRRS_MAX_RR:
5032 default:
5033 DRM_ERROR("Unsupported refreshrate type\n");
5034 }
5035 } else if (INTEL_INFO(dev)->gen > 6) {
f0f59a00 5036 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
649636ef 5037 u32 val;
a4c30b1d 5038
649636ef 5039 val = I915_READ(reg);
439d7ac0 5040 if (index > DRRS_HIGH_RR) {
666a4537 5041 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6fa7aec1
VK		 5042 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5043 else
5044 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5045 } else {
666a4537 5046 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6fa7aec1
VK		 5047 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5048 else
5049 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5050 }
5051 I915_WRITE(reg, val);
5052 }
5053
4e9ac947
VK		 5054 dev_priv->drrs.refresh_rate_type = index;
5055
5056 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5057}
5058
b33a2815
VK		 5059/**
5060 * intel_edp_drrs_enable - init drrs struct if supported
5061 * @intel_dp: DP struct
5062 *
5063 * Initializes frontbuffer_bits and drrs.dp
5064 */
c395578e
VK		 5065void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5066{
5067 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5068 struct drm_i915_private *dev_priv = dev->dev_private;
5069 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5070 struct drm_crtc *crtc = dig_port->base.base.crtc;
5071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5072
5073 if (!intel_crtc->config->has_drrs) {
5074 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5075 return;
5076 }
5077
5078 mutex_lock(&dev_priv->drrs.mutex);
5079 if (WARN_ON(dev_priv->drrs.dp)) {
5080 DRM_ERROR("DRRS already enabled\n");
5081 goto unlock;
5082 }
5083
5084 dev_priv->drrs.busy_frontbuffer_bits = 0;
5085
5086 dev_priv->drrs.dp = intel_dp;
5087
5088unlock:
5089 mutex_unlock(&dev_priv->drrs.mutex);
5090}
5091
b33a2815
VK		 5092/**
5093 * intel_edp_drrs_disable - Disable DRRS
5094 * @intel_dp: DP struct
5095 *
5096 */
c395578e
VK		 5097void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5098{
5099 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5100 struct drm_i915_private *dev_priv = dev->dev_private;
5101 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5102 struct drm_crtc *crtc = dig_port->base.base.crtc;
5103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5104
5105 if (!intel_crtc->config->has_drrs)
5106 return;
5107
5108 mutex_lock(&dev_priv->drrs.mutex);
5109 if (!dev_priv->drrs.dp) {
5110 mutex_unlock(&dev_priv->drrs.mutex);
5111 return;
5112 }
5113
5114 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5115 intel_dp_set_drrs_state(dev_priv->dev,
5116 intel_dp->attached_connector->panel.
5117 fixed_mode->vrefresh);
5118
5119 dev_priv->drrs.dp = NULL;
5120 mutex_unlock(&dev_priv->drrs.mutex);
5121
5122 cancel_delayed_work_sync(&dev_priv->drrs.work);
5123}
5124
4e9ac947
VK		 5125static void intel_edp_drrs_downclock_work(struct work_struct *work)
5126{
5127 struct drm_i915_private *dev_priv =
5128 container_of(work, typeof(*dev_priv), drrs.work.work);
5129 struct intel_dp *intel_dp;
5130
5131 mutex_lock(&dev_priv->drrs.mutex);
5132
5133 intel_dp = dev_priv->drrs.dp;
5134
5135 if (!intel_dp)
5136 goto unlock;
5137
439d7ac0 5138 /*
4e9ac947
VK		 5139 * The delayed work can race with an invalidate hence we need to
5140 * recheck.
439d7ac0
PB		 5141 */
5142
4e9ac947
VK		 5143 if (dev_priv->drrs.busy_frontbuffer_bits)
5144 goto unlock;
439d7ac0 5145
4e9ac947
VK		 5146 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5147 intel_dp_set_drrs_state(dev_priv->dev,
5148 intel_dp->attached_connector->panel.
5149 downclock_mode->vrefresh);
439d7ac0 5150
4e9ac947 5151unlock:
4e9ac947 5152 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5153}
5154
b33a2815 5155/**
0ddfd203 5156 * intel_edp_drrs_invalidate - Disable Idleness DRRS
b33a2815
VK		 5157 * @dev: DRM device
5158 * @frontbuffer_bits: frontbuffer plane tracking bits
5159 *
0ddfd203
R		 5160 * This function gets called everytime rendering on the given planes start.
5161 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5162 *
5163 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5164 */
a93fad0f
VK		 5165void intel_edp_drrs_invalidate(struct drm_device *dev,
5166 unsigned frontbuffer_bits)
5167{
5168 struct drm_i915_private *dev_priv = dev->dev_private;
5169 struct drm_crtc *crtc;
5170 enum pipe pipe;
5171
9da7d693 5172 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5173 return;
5174
88f933a8 5175 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5176
a93fad0f 5177 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5178 if (!dev_priv->drrs.dp) {
5179 mutex_unlock(&dev_priv->drrs.mutex);
5180 return;
5181 }
5182
a93fad0f
VK		 5183 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5184 pipe = to_intel_crtc(crtc)->pipe;
5185
c1d038c6
DV		 5186 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5187 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5188
0ddfd203 5189 /* invalidate means busy screen hence upclock */
c1d038c6 5190 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
a93fad0f
VK		 5191 intel_dp_set_drrs_state(dev_priv->dev,
5192 dev_priv->drrs.dp->attached_connector->panel.
5193 fixed_mode->vrefresh);
a93fad0f 5194
a93fad0f
VK		 5195 mutex_unlock(&dev_priv->drrs.mutex);
5196}
5197
b33a2815 5198/**
0ddfd203 5199 * intel_edp_drrs_flush - Restart Idleness DRRS
b33a2815
VK		 5200 * @dev: DRM device
5201 * @frontbuffer_bits: frontbuffer plane tracking bits
5202 *
0ddfd203
R		 5203 * This function gets called every time rendering on the given planes has
5204 * completed or flip on a crtc is completed. So DRRS should be upclocked
5205 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5206 * if no other planes are dirty.
b33a2815
VK		 5207 *
5208 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5209 */
a93fad0f
VK		 5210void intel_edp_drrs_flush(struct drm_device *dev,
5211 unsigned frontbuffer_bits)
5212{
5213 struct drm_i915_private *dev_priv = dev->dev_private;
5214 struct drm_crtc *crtc;
5215 enum pipe pipe;
5216
9da7d693 5217 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5218 return;
5219
88f933a8 5220 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5221
a93fad0f 5222 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5223 if (!dev_priv->drrs.dp) {
5224 mutex_unlock(&dev_priv->drrs.mutex);
5225 return;
5226 }
5227
a93fad0f
VK		 5228 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5229 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5230
5231 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5232 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5233
0ddfd203 5234 /* flush means busy screen hence upclock */
c1d038c6 5235 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
0ddfd203
R		 5236 intel_dp_set_drrs_state(dev_priv->dev,
5237 dev_priv->drrs.dp->attached_connector->panel.
5238 fixed_mode->vrefresh);
5239
5240 /*
5241 * flush also means no more activity hence schedule downclock, if all
5242 * other fbs are quiescent too
5243 */
5244 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5245 schedule_delayed_work(&dev_priv->drrs.work,
5246 msecs_to_jiffies(1000));
5247 mutex_unlock(&dev_priv->drrs.mutex);
5248}
5249
b33a2815
VK		 5250/**
5251 * DOC: Display Refresh Rate Switching (DRRS)
5252 *
5253 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5254 * which enables swtching between low and high refresh rates,
5255 * dynamically, based on the usage scenario. This feature is applicable
5256 * for internal panels.
5257 *
5258 * Indication that the panel supports DRRS is given by the panel EDID, which
5259 * would list multiple refresh rates for one resolution.
5260 *
5261 * DRRS is of 2 types - static and seamless.
5262 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5263 * (may appear as a blink on screen) and is used in dock-undock scenario.
5264 * Seamless DRRS involves changing RR without any visual effect to the user
5265 * and can be used during normal system usage. This is done by programming
5266 * certain registers.
5267 *
5268 * Support for static/seamless DRRS may be indicated in the VBT based on
5269 * inputs from the panel spec.
5270 *
5271 * DRRS saves power by switching to low RR based on usage scenarios.
5272 *
5273 * eDP DRRS:-
5274 * The implementation is based on frontbuffer tracking implementation.
5275 * When there is a disturbance on the screen triggered by user activity or a
5276 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5277 * When there is no movement on screen, after a timeout of 1 second, a switch
5278 * to low RR is made.
5279 * For integration with frontbuffer tracking code,
5280 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5281 *
5282 * DRRS can be further extended to support other internal panels and also
5283 * the scenario of video playback wherein RR is set based on the rate
5284 * requested by userspace.
5285 */
5286
5287/**
5288 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5289 * @intel_connector: eDP connector
5290 * @fixed_mode: preferred mode of panel
5291 *
5292 * This function is called only once at driver load to initialize basic
5293 * DRRS stuff.
5294 *
5295 * Returns:
5296 * Downclock mode if panel supports it, else return NULL.
5297 * DRRS support is determined by the presence of downclock mode (apart
5298 * from VBT setting).
5299 */
4f9db5b5 5300static struct drm_display_mode *
96178eeb
VK		 5301intel_dp_drrs_init(struct intel_connector *intel_connector,
5302 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5303{
5304 struct drm_connector *connector = &intel_connector->base;
96178eeb 5305 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5306 struct drm_i915_private *dev_priv = dev->dev_private;
5307 struct drm_display_mode *downclock_mode = NULL;
5308
9da7d693
DV		 5309 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5310 mutex_init(&dev_priv->drrs.mutex);
5311
4f9db5b5
PB		 5312 if (INTEL_INFO(dev)->gen <= 6) {
5313 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5314 return NULL;
5315 }
5316
5317 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5318 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5319 return NULL;
5320 }
5321
5322 downclock_mode = intel_find_panel_downclock
5323 (dev, fixed_mode, connector);
5324
5325 if (!downclock_mode) {
a1d26342 5326 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5327 return NULL;
5328 }
5329
96178eeb 5330 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5331
96178eeb 5332 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5333 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5334 return downclock_mode;
5335}
5336
ed92f0b2 5337static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5338 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5339{
5340 struct drm_connector *connector = &intel_connector->base;
5341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5342 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5343 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5344 struct drm_i915_private *dev_priv = dev->dev_private;
5345 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5346 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5347 bool has_dpcd;
5348 struct drm_display_mode *scan;
5349 struct edid *edid;
6517d273 5350 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5351
5352 if (!is_edp(intel_dp))
5353 return true;
5354
49e6bc51
VS		 5355 pps_lock(intel_dp);
5356 intel_edp_panel_vdd_sanitize(intel_dp);
5357 pps_unlock(intel_dp);
63635217 5358
ed92f0b2 5359 /* Cache DPCD and EDID for edp. */
ed92f0b2 5360 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5361
5362 if (has_dpcd) {
5363 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5364 dev_priv->no_aux_handshake =
5365 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5366 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5367 } else {
5368 /* if this fails, presume the device is a ghost */
5369 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5370 return false;
5371 }
5372
5373 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5374 pps_lock(intel_dp);
36b5f425 5375 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5376 pps_unlock(intel_dp);
ed92f0b2 5377
060c8778 5378 mutex_lock(&dev->mode_config.mutex);
0b99836f 5379 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5380 if (edid) {
5381 if (drm_add_edid_modes(connector, edid)) {
5382 drm_mode_connector_update_edid_property(connector,
5383 edid);
5384 drm_edid_to_eld(connector, edid);
5385 } else {
5386 kfree(edid);
5387 edid = ERR_PTR(-EINVAL);
5388 }
5389 } else {
5390 edid = ERR_PTR(-ENOENT);
5391 }
5392 intel_connector->edid = edid;
5393
5394 /* prefer fixed mode from EDID if available */
5395 list_for_each_entry(scan, &connector->probed_modes, head) {
5396 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5397 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5398 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5399 intel_connector, fixed_mode);
ed92f0b2
PZ		 5400 break;
5401 }
5402 }
5403
5404 /* fallback to VBT if available for eDP */
5405 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5406 fixed_mode = drm_mode_duplicate(dev,
5407 dev_priv->vbt.lfp_lvds_vbt_mode);
5408 if (fixed_mode)
5409 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5410 }
060c8778 5411 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5412
666a4537 5413 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
01527b31
CT		 5414 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5415 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5416
5417 /*
5418 * Figure out the current pipe for the initial backlight setup.
5419 * If the current pipe isn't valid, try the PPS pipe, and if that
5420 * fails just assume pipe A.
5421 */
5422 if (IS_CHERRYVIEW(dev))
5423 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5424 else
5425 pipe = PORT_TO_PIPE(intel_dp->DP);
5426
5427 if (pipe != PIPE_A && pipe != PIPE_B)
5428 pipe = intel_dp->pps_pipe;
5429
5430 if (pipe != PIPE_A && pipe != PIPE_B)
5431 pipe = PIPE_A;
5432
5433 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5434 pipe_name(pipe));
01527b31
CT		 5435 }
5436
4f9db5b5 5437 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5507faeb 5438 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6517d273 5439 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5440
5441 return true;
5442}
5443
16c25533 5444bool
f0fec3f2
PZ		 5445intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5446 struct intel_connector *intel_connector)
a4fc5ed6 5447{
f0fec3f2
PZ		 5448 struct drm_connector *connector = &intel_connector->base;
5449 struct intel_dp *intel_dp = &intel_dig_port->dp;
5450 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5451 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5452 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5453 enum port port = intel_dig_port->port;
a121f4e5 5454 int type, ret;
a4fc5ed6 5455
ccb1a831
VS		 5456 if (WARN(intel_dig_port->max_lanes < 1,
5457 "Not enough lanes (%d) for DP on port %c\n",
5458 intel_dig_port->max_lanes, port_name(port)))
5459 return false;
5460
a4a5d2f8
VS		 5461 intel_dp->pps_pipe = INVALID_PIPE;
5462
ec5b01dd 5463 /* intel_dp vfuncs */
b6b5e383
DL		 5464 if (INTEL_INFO(dev)->gen >= 9)
5465 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
ec5b01dd
DL		 5466 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5467 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5468 else if (HAS_PCH_SPLIT(dev))
5469 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5470 else
6ffb1be7 5471 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
ec5b01dd 5472
b9ca5fad
DL		 5473 if (INTEL_INFO(dev)->gen >= 9)
5474 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5475 else
6ffb1be7 5476 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
153b1100 5477
ad64217b
ACO		 5478 if (HAS_DDI(dev))
5479 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5480
0767935e
DV		 5481 /* Preserve the current hw state. */
5482 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5483 intel_dp->attached_connector = intel_connector;
3d3dc149 5484
3b32a35b 5485 if (intel_dp_is_edp(dev, port))
b329530c 5486 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5487 else
5488 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5489
f7d24902
ID		 5490 /*
5491 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5492 * for DP the encoder type can be set by the caller to
5493 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5494 */
5495 if (type == DRM_MODE_CONNECTOR_eDP)
5496 intel_encoder->type = INTEL_OUTPUT_EDP;
5497
c17ed5b5 5498 /* eDP only on port B and/or C on vlv/chv */
666a4537
WB		 5499 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5500 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
c17ed5b5
VS		 5501 return false;
5502
e7281eab
ID		 5503 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5504 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5505 port_name(port));
5506
b329530c 5507 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5508 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5509
a4fc5ed6
KP		 5510 connector->interlace_allowed = true;
5511 connector->doublescan_allowed = 0;
5512
f0fec3f2 5513 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5514 edp_panel_vdd_work);
a4fc5ed6 5515
df0e9248 5516 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5517 drm_connector_register(connector);
a4fc5ed6 5518
affa9354 5519 if (HAS_DDI(dev))
bcbc889b
PZ		 5520 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5521 else
5522 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5523 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5524
0b99836f 5525 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5526 switch (port) {
5527 case PORT_A:
1d843f9d 5528 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5529 break;
5530 case PORT_B:
1d843f9d 5531 intel_encoder->hpd_pin = HPD_PORT_B;
e87a005d 5532 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
cf1d5883 5533 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5534 break;
5535 case PORT_C:
1d843f9d 5536 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5537 break;
5538 case PORT_D:
1d843f9d 5539 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30 5540 break;
26951caf
XZ		 5541 case PORT_E:
5542 intel_encoder->hpd_pin = HPD_PORT_E;
5543 break;
ab9d7c30 5544 default:
ad1c0b19 5545 BUG();
5eb08b69
ZW		 5546 }
5547
dada1a9f 5548 if (is_edp(intel_dp)) {
773538e8 5549 pps_lock(intel_dp);
1e74a324 5550 intel_dp_init_panel_power_timestamps(intel_dp);
666a4537 5551 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
a4a5d2f8 5552 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5553 else
36b5f425 5554 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5555 pps_unlock(intel_dp);
dada1a9f 5556 }
0095e6dc 5557
a121f4e5
VS		 5558 ret = intel_dp_aux_init(intel_dp, intel_connector);
5559 if (ret)
5560 goto fail;
c1f05264 5561
0e32b39c 5562 /* init MST on ports that can support it */
0c9b3715
JN		 5563 if (HAS_DP_MST(dev) &&
5564 (port == PORT_B || port == PORT_C || port == PORT_D))
5565 intel_dp_mst_encoder_init(intel_dig_port,
5566 intel_connector->base.base.id);
0e32b39c 5567
36b5f425 5568 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
a121f4e5
VS		 5569 intel_dp_aux_fini(intel_dp);
5570 intel_dp_mst_encoder_cleanup(intel_dig_port);
5571 goto fail;
b2f246a8 5572 }
32f9d658 5573
f684960e
CW		 5574 intel_dp_add_properties(intel_dp, connector);
5575
a4fc5ed6
KP		 5576 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5577 * 0xd. Failure to do so will result in spurious interrupts being
5578 * generated on the port when a cable is not attached.
5579 */
5580 if (IS_G4X(dev) && !IS_GM45(dev)) {
5581 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5582 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5583 }
16c25533 5584
aa7471d2
JN		 5585 i915_debugfs_connector_add(connector);
5586
16c25533 5587 return true;
a121f4e5
VS		 5588
5589fail:
5590 if (is_edp(intel_dp)) {
5591 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5592 /*
5593 * vdd might still be enabled do to the delayed vdd off.
5594 * Make sure vdd is actually turned off here.
5595 */
5596 pps_lock(intel_dp);
5597 edp_panel_vdd_off_sync(intel_dp);
5598 pps_unlock(intel_dp);
5599 }
5600 drm_connector_unregister(connector);
5601 drm_connector_cleanup(connector);
5602
5603 return false;
a4fc5ed6 5604}
f0fec3f2
PZ		 5605
5606void
f0f59a00
VS		 5607intel_dp_init(struct drm_device *dev,
5608 i915_reg_t output_reg, enum port port)
f0fec3f2 5609{
13cf5504 5610 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5611 struct intel_digital_port *intel_dig_port;
5612 struct intel_encoder *intel_encoder;
5613 struct drm_encoder *encoder;
5614 struct intel_connector *intel_connector;
5615
b14c5679 5616 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5617 if (!intel_dig_port)
5618 return;
5619
08d9bc92 5620 intel_connector = intel_connector_alloc();
11aee0f6
SM		 5621 if (!intel_connector)
5622 goto err_connector_alloc;
f0fec3f2
PZ		 5623
5624 intel_encoder = &intel_dig_port->base;
5625 encoder = &intel_encoder->base;
5626
893da0c9 5627 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
ade1ba73 5628 DRM_MODE_ENCODER_TMDS, NULL))
893da0c9 5629 goto err_encoder_init;
f0fec3f2 5630
5bfe2ac0 5631 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5632 intel_encoder->disable = intel_disable_dp;
00c09d70 5633 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5634 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5635 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5636 if (IS_CHERRYVIEW(dev)) {
9197c88b 5637 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5638 intel_encoder->pre_enable = chv_pre_enable_dp;
5639 intel_encoder->enable = vlv_enable_dp;
580d3811 5640 intel_encoder->post_disable = chv_post_disable_dp;
d6db995f 5641 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
e4a1d846 5642 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5643 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5644 intel_encoder->pre_enable = vlv_pre_enable_dp;
5645 intel_encoder->enable = vlv_enable_dp;
49277c31 5646 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5647 } else {
ecff4f3b
JN		 5648 intel_encoder->pre_enable = g4x_pre_enable_dp;
5649 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5650 if (INTEL_INFO(dev)->gen >= 5)
5651 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5652 }
f0fec3f2 5653
174edf1f 5654 intel_dig_port->port = port;
f0fec3f2 5655 intel_dig_port->dp.output_reg = output_reg;
ccb1a831 5656 intel_dig_port->max_lanes = 4;
f0fec3f2 5657
00c09d70 5658 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5659 if (IS_CHERRYVIEW(dev)) {
5660 if (port == PORT_D)
5661 intel_encoder->crtc_mask = 1 << 2;
5662 else
5663 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5664 } else {
5665 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5666 }
bc079e8b 5667 intel_encoder->cloneable = 0;
f0fec3f2 5668
13cf5504 5669 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 5670 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 5671
11aee0f6
SM		 5672 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5673 goto err_init_connector;
5674
5675 return;
5676
5677err_init_connector:
5678 drm_encoder_cleanup(encoder);
893da0c9 5679err_encoder_init:
11aee0f6
SM		 5680 kfree(intel_connector);
5681err_connector_alloc:
5682 kfree(intel_dig_port);
5683
5684 return;
f0fec3f2 5685}
0e32b39c
DA		 5686
5687void intel_dp_mst_suspend(struct drm_device *dev)
5688{
5689 struct drm_i915_private *dev_priv = dev->dev_private;
5690 int i;
5691
5692 /* disable MST */
5693 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5694 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 5695 if (!intel_dig_port)
5696 continue;
5697
5698 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5699 if (!intel_dig_port->dp.can_mst)
5700 continue;
5701 if (intel_dig_port->dp.is_mst)
5702 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5703 }
5704 }
5705}
5706
5707void intel_dp_mst_resume(struct drm_device *dev)
5708{
5709 struct drm_i915_private *dev_priv = dev->dev_private;
5710 int i;
5711
5712 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5713 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 5714 if (!intel_dig_port)
5715 continue;
5716 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5717 int ret;
5718
5719 if (!intel_dig_port->dp.can_mst)
5720 continue;
5721
5722 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5723 if (ret != 0) {
5724 intel_dp_check_mst_status(&intel_dig_port->dp);
5725 }
5726 }
5727 }
5728}
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