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drm/i915: Add HSW CRT output readout support
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
68b4d824 55static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 56{
68b4d824
ID		 57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
58
59 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 60}
61
df0e9248
CW		 62static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
63{
fa90ecef 64 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 65}
66
ea5b213a 67static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 68
a4fc5ed6 69static int
ea5b213a 70intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 71{
7183dc29 72 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 73
74 switch (max_link_bw) {
75 case DP_LINK_BW_1_62:
76 case DP_LINK_BW_2_7:
77 break;
d4eead50
ID		 78 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
79 max_link_bw = DP_LINK_BW_2_7;
80 break;
a4fc5ed6 81 default:
d4eead50
ID		 82 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
83 max_link_bw);
a4fc5ed6
KP		 84 max_link_bw = DP_LINK_BW_1_62;
85 break;
86 }
87 return max_link_bw;
88}
89
cd9dde44
AJ		 90/*
91 * The units on the numbers in the next two are... bizarre. Examples will
92 * make it clearer; this one parallels an example in the eDP spec.
93 *
94 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
95 *
96 * 270000 * 1 * 8 / 10 == 216000
97 *
98 * The actual data capacity of that configuration is 2.16Gbit/s, so the
99 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
100 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
101 * 119000. At 18bpp that's 2142000 kilobits per second.
102 *
103 * Thus the strange-looking division by 10 in intel_dp_link_required, to
104 * get the result in decakilobits instead of kilobits.
105 */
106
a4fc5ed6 107static int
c898261c 108intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 109{
cd9dde44 110 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 111}
112
fe27d53e
DA		 113static int
114intel_dp_max_data_rate(int max_link_clock, int max_lanes)
115{
116 return (max_link_clock * max_lanes * 8) / 10;
117}
118
a4fc5ed6
KP		 119static int
120intel_dp_mode_valid(struct drm_connector *connector,
121 struct drm_display_mode *mode)
122{
df0e9248 123 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 124 struct intel_connector *intel_connector = to_intel_connector(connector);
125 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 126 int target_clock = mode->clock;
127 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 128
dd06f90e
JN		 129 if (is_edp(intel_dp) && fixed_mode) {
130 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 131 return MODE_PANEL;
132
dd06f90e 133 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 134 return MODE_PANEL;
03afc4a2
DV		 135
136 target_clock = fixed_mode->clock;
7de56f43
ZY		 137 }
138
36008365
DV		 139 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
140 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
141
142 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
143 mode_rate = intel_dp_link_required(target_clock, 18);
144
145 if (mode_rate > max_rate)
c4867936 146 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 147
148 if (mode->clock < 10000)
149 return MODE_CLOCK_LOW;
150
0af78a2b
DV		 151 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
152 return MODE_H_ILLEGAL;
153
a4fc5ed6
KP		 154 return MODE_OK;
155}
156
157static uint32_t
158pack_aux(uint8_t *src, int src_bytes)
159{
160 int i;
161 uint32_t v = 0;
162
163 if (src_bytes > 4)
164 src_bytes = 4;
165 for (i = 0; i < src_bytes; i++)
166 v |= ((uint32_t) src[i]) << ((3-i) * 8);
167 return v;
168}
169
170static void
171unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
172{
173 int i;
174 if (dst_bytes > 4)
175 dst_bytes = 4;
176 for (i = 0; i < dst_bytes; i++)
177 dst[i] = src >> ((3-i) * 8);
178}
179
fb0f8fbf
KP		 180/* hrawclock is 1/4 the FSB frequency */
181static int
182intel_hrawclk(struct drm_device *dev)
183{
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
9473c8f4
VP		 187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
fb0f8fbf
KP		 191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212}
213
ebf33b18
KP		 214static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
215{
30add22d 216 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 217 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 218 u32 pp_stat_reg;
ebf33b18 219
453c5420
JB		 220 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
221 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
ebf33b18
KP		 222}
223
224static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
225{
30add22d 226 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 227 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 228 u32 pp_ctrl_reg;
ebf33b18 229
453c5420
JB		 230 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
231 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 232}
233
9b984dae
KP		 234static void
235intel_dp_check_edp(struct intel_dp *intel_dp)
236{
30add22d 237 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 238 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 239 u32 pp_stat_reg, pp_ctrl_reg;
ebf33b18 240
9b984dae
KP		 241 if (!is_edp(intel_dp))
242 return;
453c5420
JB		 243
244 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
245 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
246
ebf33b18 247 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 248 WARN(1, "eDP powered off while attempting aux channel communication.\n");
249 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
453c5420
JB		 250 I915_READ(pp_stat_reg),
251 I915_READ(pp_ctrl_reg));
9b984dae
KP		 252 }
253}
254
9ee32fea
DV		 255static uint32_t
256intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
257{
258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
259 struct drm_device *dev = intel_dig_port->base.base.dev;
260 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 261 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 262 uint32_t status;
263 bool done;
264
ef04f00d 265#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 266 if (has_aux_irq)
b18ac466 267 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 268 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 269 else
270 done = wait_for_atomic(C, 10) == 0;
271 if (!done)
272 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
273 has_aux_irq);
274#undef C
275
276 return status;
277}
278
bc86625a
CW		 279static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
280 int index)
a4fc5ed6 281{
174edf1f
PZ		 282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
283 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 284 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 285
a4fc5ed6 286 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 287 * and would like to run at 2MHz. So, take the
288 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 289 *
290 * Note that PCH attached eDP panels should use a 125MHz input
291 * clock divider.
a4fc5ed6 292 */
a62d0834 293 if (IS_VALLEYVIEW(dev)) {
bc86625a 294 return index ? 0 : 100;
a62d0834 295 } else if (intel_dig_port->port == PORT_A) {
bc86625a
CW		 296 if (index)
297 return 0;
affa9354 298 if (HAS_DDI(dev))
bc86625a 299 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 300 else if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 301 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 302 else
b84a1cf8 303 return 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 304 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
305 /* Workaround for non-ULT HSW */
bc86625a
CW		 306 switch (index) {
307 case 0: return 63;
308 case 1: return 72;
309 default: return 0;
310 }
2c55c336 311 } else if (HAS_PCH_SPLIT(dev)) {
bc86625a 312 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 313 } else {
bc86625a 314 return index ? 0 :intel_hrawclk(dev) / 2;
2c55c336 315 }
b84a1cf8
RV		 316}
317
318static int
319intel_dp_aux_ch(struct intel_dp *intel_dp,
320 uint8_t *send, int send_bytes,
321 uint8_t *recv, int recv_size)
322{
323 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
324 struct drm_device *dev = intel_dig_port->base.base.dev;
325 struct drm_i915_private *dev_priv = dev->dev_private;
326 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
327 uint32_t ch_data = ch_ctl + 4;
bc86625a 328 uint32_t aux_clock_divider;
b84a1cf8
RV		 329 int i, ret, recv_bytes;
330 uint32_t status;
bc86625a 331 int try, precharge, clock = 0;
b84a1cf8
RV		 332 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
333
334 /* dp aux is extremely sensitive to irq latency, hence request the
335 * lowest possible wakeup latency and so prevent the cpu from going into
336 * deep sleep states.
337 */
338 pm_qos_update_request(&dev_priv->pm_qos, 0);
339
340 intel_dp_check_edp(intel_dp);
5eb08b69 341
6b4e0a93
DV		 342 if (IS_GEN6(dev))
343 precharge = 3;
344 else
345 precharge = 5;
346
c67a470b
PZ		 347 intel_aux_display_runtime_get(dev_priv);
348
11bee43e
JB		 349 /* Try to wait for any previous AUX channel activity */
350 for (try = 0; try < 3; try++) {
ef04f00d 351 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 352 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
353 break;
354 msleep(1);
355 }
356
357 if (try == 3) {
358 WARN(1, "dp_aux_ch not started status 0x%08x\n",
359 I915_READ(ch_ctl));
9ee32fea
DV		 360 ret = -EBUSY;
361 goto out;
4f7f7b7e
CW		 362 }
363
bc86625a
CW		 364 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
365 /* Must try at least 3 times according to DP spec */
366 for (try = 0; try < 5; try++) {
367 /* Load the send data into the aux channel data registers */
368 for (i = 0; i < send_bytes; i += 4)
369 I915_WRITE(ch_data + i,
370 pack_aux(send + i, send_bytes - i));
371
372 /* Send the command and wait for it to complete */
373 I915_WRITE(ch_ctl,
374 DP_AUX_CH_CTL_SEND_BUSY |
375 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
376 DP_AUX_CH_CTL_TIME_OUT_400us |
377 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
378 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
379 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
380 DP_AUX_CH_CTL_DONE |
381 DP_AUX_CH_CTL_TIME_OUT_ERROR |
382 DP_AUX_CH_CTL_RECEIVE_ERROR);
383
384 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
385
386 /* Clear done status and any errors */
387 I915_WRITE(ch_ctl,
388 status |
389 DP_AUX_CH_CTL_DONE |
390 DP_AUX_CH_CTL_TIME_OUT_ERROR |
391 DP_AUX_CH_CTL_RECEIVE_ERROR);
392
393 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
394 DP_AUX_CH_CTL_RECEIVE_ERROR))
395 continue;
396 if (status & DP_AUX_CH_CTL_DONE)
397 break;
398 }
4f7f7b7e 399 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 400 break;
401 }
402
a4fc5ed6 403 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 404 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 405 ret = -EBUSY;
406 goto out;
a4fc5ed6
KP		 407 }
408
409 /* Check for timeout or receive error.
410 * Timeouts occur when the sink is not connected
411 */
a5b3da54 412 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 413 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 414 ret = -EIO;
415 goto out;
a5b3da54 416 }
1ae8c0a5
KP		 417
418 /* Timeouts occur when the device isn't connected, so they're
419 * "normal" -- don't fill the kernel log with these */
a5b3da54 420 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 421 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 422 ret = -ETIMEDOUT;
423 goto out;
a4fc5ed6
KP		 424 }
425
426 /* Unload any bytes sent back from the other side */
427 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
428 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 429 if (recv_bytes > recv_size)
430 recv_bytes = recv_size;
0206e353 431
4f7f7b7e
CW		 432 for (i = 0; i < recv_bytes; i += 4)
433 unpack_aux(I915_READ(ch_data + i),
434 recv + i, recv_bytes - i);
a4fc5ed6 435
9ee32fea
DV		 436 ret = recv_bytes;
437out:
438 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 439 intel_aux_display_runtime_put(dev_priv);
9ee32fea
DV		 440
441 return ret;
a4fc5ed6
KP		 442}
443
444/* Write data to the aux channel in native mode */
445static int
ea5b213a 446intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 447 uint16_t address, uint8_t *send, int send_bytes)
448{
449 int ret;
450 uint8_t msg[20];
451 int msg_bytes;
452 uint8_t ack;
453
9b984dae 454 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 455 if (send_bytes > 16)
456 return -1;
457 msg[0] = AUX_NATIVE_WRITE << 4;
458 msg[1] = address >> 8;
eebc863e 459 msg[2] = address & 0xff;
a4fc5ed6
KP		 460 msg[3] = send_bytes - 1;
461 memcpy(&msg[4], send, send_bytes);
462 msg_bytes = send_bytes + 4;
463 for (;;) {
ea5b213a 464 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 465 if (ret < 0)
466 return ret;
467 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
468 break;
469 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
470 udelay(100);
471 else
a5b3da54 472 return -EIO;
a4fc5ed6
KP		 473 }
474 return send_bytes;
475}
476
477/* Write a single byte to the aux channel in native mode */
478static int
ea5b213a 479intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 480 uint16_t address, uint8_t byte)
481{
ea5b213a 482 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 483}
484
485/* read bytes from a native aux channel */
486static int
ea5b213a 487intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 488 uint16_t address, uint8_t *recv, int recv_bytes)
489{
490 uint8_t msg[4];
491 int msg_bytes;
492 uint8_t reply[20];
493 int reply_bytes;
494 uint8_t ack;
495 int ret;
496
9b984dae 497 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 498 msg[0] = AUX_NATIVE_READ << 4;
499 msg[1] = address >> 8;
500 msg[2] = address & 0xff;
501 msg[3] = recv_bytes - 1;
502
503 msg_bytes = 4;
504 reply_bytes = recv_bytes + 1;
505
506 for (;;) {
ea5b213a 507 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 508 reply, reply_bytes);
a5b3da54
KP		 509 if (ret == 0)
510 return -EPROTO;
511 if (ret < 0)
a4fc5ed6
KP		 512 return ret;
513 ack = reply[0];
514 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
515 memcpy(recv, reply + 1, ret - 1);
516 return ret - 1;
517 }
518 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
519 udelay(100);
520 else
a5b3da54 521 return -EIO;
a4fc5ed6
KP		 522 }
523}
524
525static int
ab2c0672
DA		 526intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
527 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 528{
ab2c0672 529 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 530 struct intel_dp *intel_dp = container_of(adapter,
531 struct intel_dp,
532 adapter);
ab2c0672
DA		 533 uint16_t address = algo_data->address;
534 uint8_t msg[5];
535 uint8_t reply[2];
8316f337 536 unsigned retry;
ab2c0672
DA		 537 int msg_bytes;
538 int reply_bytes;
539 int ret;
540
9b984dae 541 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 542 /* Set up the command byte */
543 if (mode & MODE_I2C_READ)
544 msg[0] = AUX_I2C_READ << 4;
545 else
546 msg[0] = AUX_I2C_WRITE << 4;
547
548 if (!(mode & MODE_I2C_STOP))
549 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 550
ab2c0672
DA		 551 msg[1] = address >> 8;
552 msg[2] = address;
553
554 switch (mode) {
555 case MODE_I2C_WRITE:
556 msg[3] = 0;
557 msg[4] = write_byte;
558 msg_bytes = 5;
559 reply_bytes = 1;
560 break;
561 case MODE_I2C_READ:
562 msg[3] = 0;
563 msg_bytes = 4;
564 reply_bytes = 2;
565 break;
566 default:
567 msg_bytes = 3;
568 reply_bytes = 1;
569 break;
570 }
571
8316f337
DF		 572 for (retry = 0; retry < 5; retry++) {
573 ret = intel_dp_aux_ch(intel_dp,
574 msg, msg_bytes,
575 reply, reply_bytes);
ab2c0672 576 if (ret < 0) {
3ff99164 577 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 578 return ret;
579 }
8316f337
DF		 580
581 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
582 case AUX_NATIVE_REPLY_ACK:
583 /* I2C-over-AUX Reply field is only valid
584 * when paired with AUX ACK.
585 */
586 break;
587 case AUX_NATIVE_REPLY_NACK:
588 DRM_DEBUG_KMS("aux_ch native nack\n");
589 return -EREMOTEIO;
590 case AUX_NATIVE_REPLY_DEFER:
8d16f258
JN		 591 /*
592 * For now, just give more slack to branch devices. We
593 * could check the DPCD for I2C bit rate capabilities,
594 * and if available, adjust the interval. We could also
595 * be more careful with DP-to-Legacy adapters where a
596 * long legacy cable may force very low I2C bit rates.
597 */
598 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
599 DP_DWN_STRM_PORT_PRESENT)
600 usleep_range(500, 600);
601 else
602 usleep_range(300, 400);
8316f337
DF		 603 continue;
604 default:
605 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
606 reply[0]);
607 return -EREMOTEIO;
608 }
609
ab2c0672
DA		 610 switch (reply[0] & AUX_I2C_REPLY_MASK) {
611 case AUX_I2C_REPLY_ACK:
612 if (mode == MODE_I2C_READ) {
613 *read_byte = reply[1];
614 }
615 return reply_bytes - 1;
616 case AUX_I2C_REPLY_NACK:
8316f337 617 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 618 return -EREMOTEIO;
619 case AUX_I2C_REPLY_DEFER:
8316f337 620 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 621 udelay(100);
622 break;
623 default:
8316f337 624 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 625 return -EREMOTEIO;
626 }
627 }
8316f337
DF		 628
629 DRM_ERROR("too many retries, giving up\n");
630 return -EREMOTEIO;
a4fc5ed6
KP		 631}
632
633static int
ea5b213a 634intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 635 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 636{
0b5c541b
KP		 637 int ret;
638
d54e9d28 639 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 640 intel_dp->algo.running = false;
641 intel_dp->algo.address = 0;
642 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
643
0206e353 644 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 645 intel_dp->adapter.owner = THIS_MODULE;
646 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 647 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 648 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
649 intel_dp->adapter.algo_data = &intel_dp->algo;
650 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
651
0b5c541b
KP		 652 ironlake_edp_panel_vdd_on(intel_dp);
653 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 654 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 655 return ret;
a4fc5ed6
KP		 656}
657
c6bb3538
DV		 658static void
659intel_dp_set_clock(struct intel_encoder *encoder,
660 struct intel_crtc_config *pipe_config, int link_bw)
661{
662 struct drm_device *dev = encoder->base.dev;
663
664 if (IS_G4X(dev)) {
665 if (link_bw == DP_LINK_BW_1_62) {
666 pipe_config->dpll.p1 = 2;
667 pipe_config->dpll.p2 = 10;
668 pipe_config->dpll.n = 2;
669 pipe_config->dpll.m1 = 23;
670 pipe_config->dpll.m2 = 8;
671 } else {
672 pipe_config->dpll.p1 = 1;
673 pipe_config->dpll.p2 = 10;
674 pipe_config->dpll.n = 1;
675 pipe_config->dpll.m1 = 14;
676 pipe_config->dpll.m2 = 2;
677 }
678 pipe_config->clock_set = true;
679 } else if (IS_HASWELL(dev)) {
680 /* Haswell has special-purpose DP DDI clocks. */
681 } else if (HAS_PCH_SPLIT(dev)) {
682 if (link_bw == DP_LINK_BW_1_62) {
683 pipe_config->dpll.n = 1;
684 pipe_config->dpll.p1 = 2;
685 pipe_config->dpll.p2 = 10;
686 pipe_config->dpll.m1 = 12;
687 pipe_config->dpll.m2 = 9;
688 } else {
689 pipe_config->dpll.n = 2;
690 pipe_config->dpll.p1 = 1;
691 pipe_config->dpll.p2 = 10;
692 pipe_config->dpll.m1 = 14;
693 pipe_config->dpll.m2 = 8;
694 }
695 pipe_config->clock_set = true;
696 } else if (IS_VALLEYVIEW(dev)) {
697 /* FIXME: Need to figure out optimized DP clocks for vlv. */
698 }
699}
700
00c09d70 701bool
5bfe2ac0
DV		 702intel_dp_compute_config(struct intel_encoder *encoder,
703 struct intel_crtc_config *pipe_config)
a4fc5ed6 704{
5bfe2ac0 705 struct drm_device *dev = encoder->base.dev;
36008365 706 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 707 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 708 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 709 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 710 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 711 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 712 int lane_count, clock;
397fe157 713 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 714 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 715 int bpp, mode_rate;
a4fc5ed6 716 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
ff9a6750 717 int link_avail, link_clock;
a4fc5ed6 718
bc7d38a4 719 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 720 pipe_config->has_pch_encoder = true;
721
03afc4a2 722 pipe_config->has_dp_encoder = true;
a4fc5ed6 723
dd06f90e
JN		 724 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
725 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
726 adjusted_mode);
2dd24552
JB		 727 if (!HAS_PCH_SPLIT(dev))
728 intel_gmch_panel_fitting(intel_crtc, pipe_config,
729 intel_connector->panel.fitting_mode);
730 else
b074cec8
JB		 731 intel_pch_panel_fitting(intel_crtc, pipe_config,
732 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 733 }
734
cb1793ce 735 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 736 return false;
737
083f9560
DV		 738 DRM_DEBUG_KMS("DP link computation with max lane count %i "
739 "max bw %02x pixel clock %iKHz\n",
71244653 740 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 741
36008365
DV		 742 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
743 * bpc in between. */
3e7ca985 744 bpp = pipe_config->pipe_bpp;
7984211e
ID		 745 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
746 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
747 dev_priv->vbt.edp_bpp);
e1b73cba 748 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
7984211e 749 }
657445fe 750
36008365 751 for (; bpp >= 6*3; bpp -= 2*3) {
ff9a6750 752 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
36008365
DV		 753
754 for (clock = 0; clock <= max_clock; clock++) {
755 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
756 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
757 link_avail = intel_dp_max_data_rate(link_clock,
758 lane_count);
759
760 if (mode_rate <= link_avail) {
761 goto found;
762 }
763 }
764 }
765 }
c4867936 766
36008365 767 return false;
3685a8f3 768
36008365 769found:
55bc60db
VS		 770 if (intel_dp->color_range_auto) {
771 /*
772 * See:
773 * CEA-861-E - 5.1 Default Encoding Parameters
774 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
775 */
18316c8c 776 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 777 intel_dp->color_range = DP_COLOR_RANGE_16_235;
778 else
779 intel_dp->color_range = 0;
780 }
781
3685a8f3 782 if (intel_dp->color_range)
50f3b016 783 pipe_config->limited_color_range = true;
a4fc5ed6 784
36008365
DV		 785 intel_dp->link_bw = bws[clock];
786 intel_dp->lane_count = lane_count;
657445fe 787 pipe_config->pipe_bpp = bpp;
ff9a6750 788 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 789
36008365
DV		 790 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
791 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 792 pipe_config->port_clock, bpp);
36008365
DV		 793 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
794 mode_rate, link_avail);
a4fc5ed6 795
03afc4a2 796 intel_link_compute_m_n(bpp, lane_count,
ff9a6750 797 adjusted_mode->clock, pipe_config->port_clock,
03afc4a2 798 &pipe_config->dp_m_n);
9d1a455b 799
c6bb3538
DV		 800 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
801
03afc4a2 802 return true;
a4fc5ed6
KP		 803}
804
247d89f6
PZ		 805void intel_dp_init_link_config(struct intel_dp *intel_dp)
806{
807 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
808 intel_dp->link_configuration[0] = intel_dp->link_bw;
809 intel_dp->link_configuration[1] = intel_dp->lane_count;
810 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
811 /*
812 * Check for DPCD version > 1.1 and enhanced framing support
813 */
814 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
815 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
816 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
817 }
818}
819
7c62a164 820static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 821{
7c62a164
DV		 822 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
823 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
824 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 825 struct drm_i915_private *dev_priv = dev->dev_private;
826 u32 dpa_ctl;
827
ff9a6750 828 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 829 dpa_ctl = I915_READ(DP_A);
830 dpa_ctl &= ~DP_PLL_FREQ_MASK;
831
ff9a6750 832 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 833 /* For a long time we've carried around a ILK-DevA w/a for the
834 * 160MHz clock. If we're really unlucky, it's still required.
835 */
836 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 837 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 838 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 839 } else {
840 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 841 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 842 }
1ce17038 843
ea9b6006
DV		 844 I915_WRITE(DP_A, dpa_ctl);
845
846 POSTING_READ(DP_A);
847 udelay(500);
848}
849
b934223d 850static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 851{
b934223d 852 struct drm_device *dev = encoder->base.dev;
417e822d 853 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 854 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 855 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 856 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
857 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 858
417e822d 859 /*
1a2eb460 860 * There are four kinds of DP registers:
417e822d
KP		 861 *
862 * IBX PCH
1a2eb460
KP		 863 * SNB CPU
864 * IVB CPU
417e822d
KP		 865 * CPT PCH
866 *
867 * IBX PCH and CPU are the same for almost everything,
868 * except that the CPU DP PLL is configured in this
869 * register
870 *
871 * CPT PCH is quite different, having many bits moved
872 * to the TRANS_DP_CTL register instead. That
873 * configuration happens (oddly) in ironlake_pch_enable
874 */
9c9e7927 875
417e822d
KP		 876 /* Preserve the BIOS-computed detected bit. This is
877 * supposed to be read-only.
878 */
879 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 880
417e822d 881 /* Handle DP bits in common between all three register formats */
417e822d 882 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 883 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 884
e0dac65e
WF		 885 if (intel_dp->has_audio) {
886 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 887 pipe_name(crtc->pipe));
ea5b213a 888 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 889 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 890 }
247d89f6
PZ		 891
892 intel_dp_init_link_config(intel_dp);
a4fc5ed6 893
417e822d 894 /* Split out the IBX/CPU vs CPT settings */
32f9d658 895
bc7d38a4 896 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 897 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
898 intel_dp->DP |= DP_SYNC_HS_HIGH;
899 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
900 intel_dp->DP |= DP_SYNC_VS_HIGH;
901 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
902
903 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
904 intel_dp->DP |= DP_ENHANCED_FRAMING;
905
7c62a164 906 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 907 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 908 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 909 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 910
911 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
912 intel_dp->DP |= DP_SYNC_HS_HIGH;
913 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
914 intel_dp->DP |= DP_SYNC_VS_HIGH;
915 intel_dp->DP |= DP_LINK_TRAIN_OFF;
916
917 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
918 intel_dp->DP |= DP_ENHANCED_FRAMING;
919
7c62a164 920 if (crtc->pipe == 1)
417e822d 921 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 922 } else {
923 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 924 }
ea9b6006 925
bc7d38a4 926 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 927 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 928}
929
99ea7127
KP		 930#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
931#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
932
933#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
934#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
935
936#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
937#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
938
939static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
940 u32 mask,
941 u32 value)
bd943159 942{
30add22d 943 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 944 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 945 u32 pp_stat_reg, pp_ctrl_reg;
946
947 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
948 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
32ce697c 949
99ea7127 950 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 951 mask, value,
952 I915_READ(pp_stat_reg),
953 I915_READ(pp_ctrl_reg));
32ce697c 954
453c5420 955 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 956 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 957 I915_READ(pp_stat_reg),
958 I915_READ(pp_ctrl_reg));
32ce697c 959 }
99ea7127 960}
32ce697c 961
99ea7127
KP		 962static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
963{
964 DRM_DEBUG_KMS("Wait for panel power on\n");
965 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 966}
967
99ea7127
KP		 968static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
969{
970 DRM_DEBUG_KMS("Wait for panel power off time\n");
971 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
972}
973
974static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
975{
976 DRM_DEBUG_KMS("Wait for panel power cycle\n");
977 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
978}
979
980
832dd3c1
KP		 981/* Read the current pp_control value, unlocking the register if it
982 * is locked
983 */
984
453c5420 985static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 986{
453c5420
JB		 987 struct drm_device *dev = intel_dp_to_dev(intel_dp);
988 struct drm_i915_private *dev_priv = dev->dev_private;
989 u32 control;
990 u32 pp_ctrl_reg;
991
992 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
993 control = I915_READ(pp_ctrl_reg);
832dd3c1
KP		 994
995 control &= ~PANEL_UNLOCK_MASK;
996 control |= PANEL_UNLOCK_REGS;
997 return control;
bd943159
KP		 998}
999
82a4d9c0 1000void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1001{
30add22d 1002 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1003 struct drm_i915_private *dev_priv = dev->dev_private;
1004 u32 pp;
453c5420 1005 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1006
97af61f5
KP		 1007 if (!is_edp(intel_dp))
1008 return;
f01eca2e 1009 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1010
bd943159
KP		 1011 WARN(intel_dp->want_panel_vdd,
1012 "eDP VDD already requested on\n");
1013
1014 intel_dp->want_panel_vdd = true;
99ea7127 1015
bd943159
KP		 1016 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1017 DRM_DEBUG_KMS("eDP VDD already on\n");
1018 return;
1019 }
1020
99ea7127
KP		 1021 if (!ironlake_edp_have_panel_power(intel_dp))
1022 ironlake_wait_panel_power_cycle(intel_dp);
1023
453c5420 1024 pp = ironlake_get_pp_control(intel_dp);
5d613501 1025 pp |= EDP_FORCE_VDD;
ebf33b18 1026
453c5420
JB		 1027 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1028 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1029
1030 I915_WRITE(pp_ctrl_reg, pp);
1031 POSTING_READ(pp_ctrl_reg);
1032 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1033 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1034 /*
1035 * If the panel wasn't on, delay before accessing aux channel
1036 */
1037 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1038 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1039 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1040 }
5d613501
JB		 1041}
1042
bd943159 1043static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1044{
30add22d 1045 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1046 struct drm_i915_private *dev_priv = dev->dev_private;
1047 u32 pp;
453c5420 1048 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1049
a0e99e68
DV		 1050 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1051
bd943159 1052 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1053 pp = ironlake_get_pp_control(intel_dp);
bd943159 1054 pp &= ~EDP_FORCE_VDD;
bd943159 1055
453c5420
JB		 1056 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1057 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1058
1059 I915_WRITE(pp_ctrl_reg, pp);
1060 POSTING_READ(pp_ctrl_reg);
99ea7127 1061
453c5420
JB		 1062 /* Make sure sequencer is idle before allowing subsequent activity */
1063 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1064 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1065 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1066 }
1067}
5d613501 1068
bd943159
KP		 1069static void ironlake_panel_vdd_work(struct work_struct *__work)
1070{
1071 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1072 struct intel_dp, panel_vdd_work);
30add22d 1073 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1074
627f7675 1075 mutex_lock(&dev->mode_config.mutex);
bd943159 1076 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1077 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1078}
1079
82a4d9c0 1080void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1081{
97af61f5
KP		 1082 if (!is_edp(intel_dp))
1083 return;
5d613501 1084
bd943159
KP		 1085 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1086 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1087
bd943159
KP		 1088 intel_dp->want_panel_vdd = false;
1089
1090 if (sync) {
1091 ironlake_panel_vdd_off_sync(intel_dp);
1092 } else {
1093 /*
1094 * Queue the timer to fire a long
1095 * time from now (relative to the power down delay)
1096 * to keep the panel power up across a sequence of operations
1097 */
1098 schedule_delayed_work(&intel_dp->panel_vdd_work,
1099 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1100 }
5d613501
JB		 1101}
1102
82a4d9c0 1103void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1104{
30add22d 1105 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1106 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1107 u32 pp;
453c5420 1108 u32 pp_ctrl_reg;
9934c132 1109
97af61f5 1110 if (!is_edp(intel_dp))
bd943159 1111 return;
99ea7127
KP		 1112
1113 DRM_DEBUG_KMS("Turn eDP power on\n");
1114
1115 if (ironlake_edp_have_panel_power(intel_dp)) {
1116 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1117 return;
99ea7127 1118 }
9934c132 1119
99ea7127 1120 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1121
453c5420 1122 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1123 if (IS_GEN5(dev)) {
1124 /* ILK workaround: disable reset around power sequence */
1125 pp &= ~PANEL_POWER_RESET;
1126 I915_WRITE(PCH_PP_CONTROL, pp);
1127 POSTING_READ(PCH_PP_CONTROL);
1128 }
37c6c9b0 1129
1c0ae80a 1130 pp |= POWER_TARGET_ON;
99ea7127
KP		 1131 if (!IS_GEN5(dev))
1132 pp |= PANEL_POWER_RESET;
1133
453c5420
JB		 1134 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1135
1136 I915_WRITE(pp_ctrl_reg, pp);
1137 POSTING_READ(pp_ctrl_reg);
9934c132 1138
99ea7127 1139 ironlake_wait_panel_on(intel_dp);
9934c132 1140
05ce1a49
KP		 1141 if (IS_GEN5(dev)) {
1142 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1143 I915_WRITE(PCH_PP_CONTROL, pp);
1144 POSTING_READ(PCH_PP_CONTROL);
1145 }
9934c132
JB		 1146}
1147
82a4d9c0 1148void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1149{
30add22d 1150 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1151 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1152 u32 pp;
453c5420 1153 u32 pp_ctrl_reg;
9934c132 1154
97af61f5
KP		 1155 if (!is_edp(intel_dp))
1156 return;
37c6c9b0 1157
99ea7127 1158 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1159
6cb49835 1160 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1161
453c5420 1162 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1163 /* We need to switch off panel power _and_ force vdd, for otherwise some
1164 * panels get very unhappy and cease to work. */
1165 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420
JB		 1166
1167 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1168
1169 I915_WRITE(pp_ctrl_reg, pp);
1170 POSTING_READ(pp_ctrl_reg);
9934c132 1171
35a38556
DV		 1172 intel_dp->want_panel_vdd = false;
1173
99ea7127 1174 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1175}
1176
d6c50ff8 1177void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1178{
da63a9f2
PZ		 1179 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1180 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1181 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1182 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1183 u32 pp;
453c5420 1184 u32 pp_ctrl_reg;
32f9d658 1185
f01eca2e
KP		 1186 if (!is_edp(intel_dp))
1187 return;
1188
28c97730 1189 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1190 /*
1191 * If we enable the backlight right away following a panel power
1192 * on, we may see slight flicker as the panel syncs with the eDP
1193 * link. So delay a bit to make sure the image is solid before
1194 * allowing it to appear.
1195 */
f01eca2e 1196 msleep(intel_dp->backlight_on_delay);
453c5420 1197 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1198 pp |= EDP_BLC_ENABLE;
453c5420
JB		 1199
1200 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1201
1202 I915_WRITE(pp_ctrl_reg, pp);
1203 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1204
1205 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1206}
1207
d6c50ff8 1208void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1209{
30add22d 1210 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1211 struct drm_i915_private *dev_priv = dev->dev_private;
1212 u32 pp;
453c5420 1213 u32 pp_ctrl_reg;
32f9d658 1214
f01eca2e
KP		 1215 if (!is_edp(intel_dp))
1216 return;
1217
035aa3de
DV		 1218 intel_panel_disable_backlight(dev);
1219
28c97730 1220 DRM_DEBUG_KMS("\n");
453c5420 1221 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1222 pp &= ~EDP_BLC_ENABLE;
453c5420
JB		 1223
1224 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1225
1226 I915_WRITE(pp_ctrl_reg, pp);
1227 POSTING_READ(pp_ctrl_reg);
f01eca2e 1228 msleep(intel_dp->backlight_off_delay);
32f9d658 1229}
a4fc5ed6 1230
2bd2ad64 1231static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1232{
da63a9f2
PZ		 1233 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1234 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1235 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1236 struct drm_i915_private *dev_priv = dev->dev_private;
1237 u32 dpa_ctl;
1238
2bd2ad64
DV		 1239 assert_pipe_disabled(dev_priv,
1240 to_intel_crtc(crtc)->pipe);
1241
d240f20f
JB		 1242 DRM_DEBUG_KMS("\n");
1243 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1244 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1245 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1246
1247 /* We don't adjust intel_dp->DP while tearing down the link, to
1248 * facilitate link retraining (e.g. after hotplug). Hence clear all
1249 * enable bits here to ensure that we don't enable too much. */
1250 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1251 intel_dp->DP |= DP_PLL_ENABLE;
1252 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1253 POSTING_READ(DP_A);
1254 udelay(200);
d240f20f
JB		 1255}
1256
2bd2ad64 1257static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1258{
da63a9f2
PZ		 1259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1261 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1262 struct drm_i915_private *dev_priv = dev->dev_private;
1263 u32 dpa_ctl;
1264
2bd2ad64
DV		 1265 assert_pipe_disabled(dev_priv,
1266 to_intel_crtc(crtc)->pipe);
1267
d240f20f 1268 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1269 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1270 "dp pll off, should be on\n");
1271 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1272
1273 /* We can't rely on the value tracked for the DP register in
1274 * intel_dp->DP because link_down must not change that (otherwise link
1275 * re-training will fail. */
298b0b39 1276 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1277 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1278 POSTING_READ(DP_A);
d240f20f
JB		 1279 udelay(200);
1280}
1281
c7ad3810 1282/* If the sink supports it, try to set the power state appropriately */
c19b0669 1283void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1284{
1285 int ret, i;
1286
1287 /* Should have a valid DPCD by this point */
1288 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1289 return;
1290
1291 if (mode != DRM_MODE_DPMS_ON) {
1292 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1293 DP_SET_POWER_D3);
1294 if (ret != 1)
1295 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1296 } else {
1297 /*
1298 * When turning on, we need to retry for 1ms to give the sink
1299 * time to wake up.
1300 */
1301 for (i = 0; i < 3; i++) {
1302 ret = intel_dp_aux_native_write_1(intel_dp,
1303 DP_SET_POWER,
1304 DP_SET_POWER_D0);
1305 if (ret == 1)
1306 break;
1307 msleep(1);
1308 }
1309 }
1310}
1311
19d8fe15
DV		 1312static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1313 enum pipe *pipe)
d240f20f 1314{
19d8fe15 1315 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1316 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1317 struct drm_device *dev = encoder->base.dev;
1318 struct drm_i915_private *dev_priv = dev->dev_private;
1319 u32 tmp = I915_READ(intel_dp->output_reg);
1320
1321 if (!(tmp & DP_PORT_EN))
1322 return false;
1323
bc7d38a4 1324 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1325 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1326 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1327 *pipe = PORT_TO_PIPE(tmp);
1328 } else {
1329 u32 trans_sel;
1330 u32 trans_dp;
1331 int i;
1332
1333 switch (intel_dp->output_reg) {
1334 case PCH_DP_B:
1335 trans_sel = TRANS_DP_PORT_SEL_B;
1336 break;
1337 case PCH_DP_C:
1338 trans_sel = TRANS_DP_PORT_SEL_C;
1339 break;
1340 case PCH_DP_D:
1341 trans_sel = TRANS_DP_PORT_SEL_D;
1342 break;
1343 default:
1344 return true;
1345 }
1346
1347 for_each_pipe(i) {
1348 trans_dp = I915_READ(TRANS_DP_CTL(i));
1349 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1350 *pipe = i;
1351 return true;
1352 }
1353 }
19d8fe15 1354
4a0833ec
DV		 1355 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1356 intel_dp->output_reg);
1357 }
d240f20f 1358
19d8fe15
DV		 1359 return true;
1360}
d240f20f 1361
045ac3b5
JB		 1362static void intel_dp_get_config(struct intel_encoder *encoder,
1363 struct intel_crtc_config *pipe_config)
1364{
1365 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1366 u32 tmp, flags = 0;
63000ef6
XZ		 1367 struct drm_device *dev = encoder->base.dev;
1368 struct drm_i915_private *dev_priv = dev->dev_private;
1369 enum port port = dp_to_dig_port(intel_dp)->port;
1370 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 1371
63000ef6
XZ		 1372 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1373 tmp = I915_READ(intel_dp->output_reg);
1374 if (tmp & DP_SYNC_HS_HIGH)
1375 flags |= DRM_MODE_FLAG_PHSYNC;
1376 else
1377 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1378
63000ef6
XZ		 1379 if (tmp & DP_SYNC_VS_HIGH)
1380 flags |= DRM_MODE_FLAG_PVSYNC;
1381 else
1382 flags |= DRM_MODE_FLAG_NVSYNC;
1383 } else {
1384 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1385 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1386 flags |= DRM_MODE_FLAG_PHSYNC;
1387 else
1388 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1389
63000ef6
XZ		 1390 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1391 flags |= DRM_MODE_FLAG_PVSYNC;
1392 else
1393 flags |= DRM_MODE_FLAG_NVSYNC;
1394 }
045ac3b5
JB		 1395
1396 pipe_config->adjusted_mode.flags |= flags;
f1f644dc
JB		 1397
1398 if (dp_to_dig_port(intel_dp)->port == PORT_A) {
1399 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1400 pipe_config->port_clock = 162000;
1401 else
1402 pipe_config->port_clock = 270000;
1403 }
045ac3b5
JB		 1404}
1405
2293bb5c
SK		 1406static bool is_edp_psr(struct intel_dp *intel_dp)
1407{
1408 return is_edp(intel_dp) &&
1409 intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1410}
1411
2b28bb1b
RV		 1412static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1413{
1414 struct drm_i915_private *dev_priv = dev->dev_private;
1415
1416 if (!IS_HASWELL(dev))
1417 return false;
1418
1419 return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
1420}
1421
1422static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1423 struct edp_vsc_psr *vsc_psr)
1424{
1425 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1426 struct drm_device *dev = dig_port->base.base.dev;
1427 struct drm_i915_private *dev_priv = dev->dev_private;
1428 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1429 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1430 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1431 uint32_t *data = (uint32_t *) vsc_psr;
1432 unsigned int i;
1433
1434 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1435 the video DIP being updated before program video DIP data buffer
1436 registers for DIP being updated. */
1437 I915_WRITE(ctl_reg, 0);
1438 POSTING_READ(ctl_reg);
1439
1440 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1441 if (i < sizeof(struct edp_vsc_psr))
1442 I915_WRITE(data_reg + i, *data++);
1443 else
1444 I915_WRITE(data_reg + i, 0);
1445 }
1446
1447 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1448 POSTING_READ(ctl_reg);
1449}
1450
1451static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1452{
1453 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1454 struct drm_i915_private *dev_priv = dev->dev_private;
1455 struct edp_vsc_psr psr_vsc;
1456
1457 if (intel_dp->psr_setup_done)
1458 return;
1459
1460 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1461 memset(&psr_vsc, 0, sizeof(psr_vsc));
1462 psr_vsc.sdp_header.HB0 = 0;
1463 psr_vsc.sdp_header.HB1 = 0x7;
1464 psr_vsc.sdp_header.HB2 = 0x2;
1465 psr_vsc.sdp_header.HB3 = 0x8;
1466 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1467
1468 /* Avoid continuous PSR exit by masking memup and hpd */
1469 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1470 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1471
1472 intel_dp->psr_setup_done = true;
1473}
1474
1475static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1476{
1477 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1478 struct drm_i915_private *dev_priv = dev->dev_private;
bc86625a 1479 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
2b28bb1b
RV		 1480 int precharge = 0x3;
1481 int msg_size = 5; /* Header(4) + Message(1) */
1482
1483 /* Enable PSR in sink */
1484 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1485 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1486 DP_PSR_ENABLE &
1487 ~DP_PSR_MAIN_LINK_ACTIVE);
1488 else
1489 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1490 DP_PSR_ENABLE |
1491 DP_PSR_MAIN_LINK_ACTIVE);
1492
1493 /* Setup AUX registers */
1494 I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
1495 I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
1496 I915_WRITE(EDP_PSR_AUX_CTL,
1497 DP_AUX_CH_CTL_TIME_OUT_400us |
1498 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1499 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1500 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1501}
1502
1503static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1504{
1505 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1506 struct drm_i915_private *dev_priv = dev->dev_private;
1507 uint32_t max_sleep_time = 0x1f;
1508 uint32_t idle_frames = 1;
1509 uint32_t val = 0x0;
1510
1511 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1512 val |= EDP_PSR_LINK_STANDBY;
1513 val |= EDP_PSR_TP2_TP3_TIME_0us;
1514 val |= EDP_PSR_TP1_TIME_0us;
1515 val |= EDP_PSR_SKIP_AUX_EXIT;
1516 } else
1517 val |= EDP_PSR_LINK_DISABLE;
1518
1519 I915_WRITE(EDP_PSR_CTL, val |
1520 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1521 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1522 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1523 EDP_PSR_ENABLE);
1524}
1525
3f51e471
RV		 1526static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1527{
1528 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1529 struct drm_device *dev = dig_port->base.base.dev;
1530 struct drm_i915_private *dev_priv = dev->dev_private;
1531 struct drm_crtc *crtc = dig_port->base.base.crtc;
1532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1533 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1534 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1535
1536 if (!IS_HASWELL(dev)) {
1537 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1538 dev_priv->no_psr_reason = PSR_NO_SOURCE;
1539 return false;
1540 }
1541
1542 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1543 (dig_port->port != PORT_A)) {
1544 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1545 dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
1546 return false;
1547 }
1548
1549 if (!is_edp_psr(intel_dp)) {
1550 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1551 dev_priv->no_psr_reason = PSR_NO_SINK;
1552 return false;
1553 }
1554
105b7c11
RV		 1555 if (!i915_enable_psr) {
1556 DRM_DEBUG_KMS("PSR disable by flag\n");
1557 dev_priv->no_psr_reason = PSR_MODULE_PARAM;
1558 return false;
1559 }
1560
cd234b0b
CW		 1561 crtc = dig_port->base.base.crtc;
1562 if (crtc == NULL) {
1563 DRM_DEBUG_KMS("crtc not active for PSR\n");
1564 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1565 return false;
1566 }
1567
1568 intel_crtc = to_intel_crtc(crtc);
3f51e471
RV		 1569 if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) {
1570 DRM_DEBUG_KMS("crtc not active for PSR\n");
1571 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1572 return false;
1573 }
1574
cd234b0b 1575 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1576 if (obj->tiling_mode != I915_TILING_X ||
1577 obj->fence_reg == I915_FENCE_REG_NONE) {
1578 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1579 dev_priv->no_psr_reason = PSR_NOT_TILED;
1580 return false;
1581 }
1582
1583 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1584 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1585 dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
1586 return false;
1587 }
1588
1589 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1590 S3D_ENABLE) {
1591 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1592 dev_priv->no_psr_reason = PSR_S3D_ENABLED;
1593 return false;
1594 }
1595
1596 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
1597 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1598 dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
1599 return false;
1600 }
1601
1602 return true;
1603}
1604
3d739d92 1605static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1606{
1607 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1608
3f51e471
RV		 1609 if (!intel_edp_psr_match_conditions(intel_dp) ||
1610 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1611 return;
1612
1613 /* Setup PSR once */
1614 intel_edp_psr_setup(intel_dp);
1615
1616 /* Enable PSR on the panel */
1617 intel_edp_psr_enable_sink(intel_dp);
1618
1619 /* Enable PSR on the host */
1620 intel_edp_psr_enable_source(intel_dp);
1621}
1622
3d739d92
RV		 1623void intel_edp_psr_enable(struct intel_dp *intel_dp)
1624{
1625 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1626
1627 if (intel_edp_psr_match_conditions(intel_dp) &&
1628 !intel_edp_is_psr_enabled(dev))
1629 intel_edp_psr_do_enable(intel_dp);
1630}
1631
2b28bb1b
RV		 1632void intel_edp_psr_disable(struct intel_dp *intel_dp)
1633{
1634 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1635 struct drm_i915_private *dev_priv = dev->dev_private;
1636
1637 if (!intel_edp_is_psr_enabled(dev))
1638 return;
1639
1640 I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
1641
1642 /* Wait till PSR is idle */
1643 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
1644 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1645 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1646}
1647
3d739d92
RV		 1648void intel_edp_psr_update(struct drm_device *dev)
1649{
1650 struct intel_encoder *encoder;
1651 struct intel_dp *intel_dp = NULL;
1652
1653 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1654 if (encoder->type == INTEL_OUTPUT_EDP) {
1655 intel_dp = enc_to_intel_dp(&encoder->base);
1656
1657 if (!is_edp_psr(intel_dp))
1658 return;
1659
1660 if (!intel_edp_psr_match_conditions(intel_dp))
1661 intel_edp_psr_disable(intel_dp);
1662 else
1663 if (!intel_edp_is_psr_enabled(dev))
1664 intel_edp_psr_do_enable(intel_dp);
1665 }
1666}
1667
e8cb4558 1668static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1669{
e8cb4558 1670 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1671 enum port port = dp_to_dig_port(intel_dp)->port;
1672 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1673
1674 /* Make sure the panel is off before trying to change the mode. But also
1675 * ensure that we have vdd while we switch off the panel. */
1676 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1677 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1678 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1679 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1680
1681 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1682 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1683 intel_dp_link_down(intel_dp);
d240f20f
JB		 1684}
1685
2bd2ad64 1686static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1687{
2bd2ad64 1688 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1689 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1690 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1691
982a3866 1692 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1693 intel_dp_link_down(intel_dp);
b2634017
JB		 1694 if (!IS_VALLEYVIEW(dev))
1695 ironlake_edp_pll_off(intel_dp);
3739850b 1696 }
2bd2ad64
DV		 1697}
1698
e8cb4558 1699static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1700{
e8cb4558
DV		 1701 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1702 struct drm_device *dev = encoder->base.dev;
1703 struct drm_i915_private *dev_priv = dev->dev_private;
1704 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1705
0c33d8d7
DV		 1706 if (WARN_ON(dp_reg & DP_PORT_EN))
1707 return;
5d613501 1708
97af61f5 1709 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1710 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1711 intel_dp_start_link_train(intel_dp);
97af61f5 1712 ironlake_edp_panel_on(intel_dp);
bd943159 1713 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1714 intel_dp_complete_link_train(intel_dp);
3ab9c637 1715 intel_dp_stop_link_train(intel_dp);
f01eca2e 1716 ironlake_edp_backlight_on(intel_dp);
ab1f90f9 1717}
89b667f8 1718
ab1f90f9
JN		 1719static void vlv_enable_dp(struct intel_encoder *encoder)
1720{
d240f20f
JB		 1721}
1722
2bd2ad64 1723static void intel_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1724{
1725 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1726 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1727
1728 if (dport->port == PORT_A)
1729 ironlake_edp_pll_on(intel_dp);
1730}
1731
1732static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1733{
2bd2ad64 1734 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1735 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1736 struct drm_device *dev = encoder->base.dev;
89b667f8 1737 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9
JN		 1738 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1739 int port = vlv_dport_to_channel(dport);
1740 int pipe = intel_crtc->pipe;
1741 u32 val;
a4fc5ed6 1742
ab1f90f9 1743 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1744
ab1f90f9
JN		 1745 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1746 val = 0;
1747 if (pipe)
1748 val |= (1<<21);
1749 else
1750 val &= ~(1<<21);
1751 val |= 0x001000c4;
1752 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1753 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1754 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
89b667f8 1755
ab1f90f9
JN		 1756 mutex_unlock(&dev_priv->dpio_lock);
1757
1758 intel_enable_dp(encoder);
1759
1760 vlv_wait_port_ready(dev_priv, port);
89b667f8
JB		 1761}
1762
1763static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1764{
1765 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1766 struct drm_device *dev = encoder->base.dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 int port = vlv_dport_to_channel(dport);
1769
1770 if (!IS_VALLEYVIEW(dev))
1771 return;
1772
89b667f8 1773 /* Program Tx lane resets to default */
0980a60f 1774 mutex_lock(&dev_priv->dpio_lock);
ae99258f 1775 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
89b667f8
JB		 1776 DPIO_PCS_TX_LANE2_RESET |
1777 DPIO_PCS_TX_LANE1_RESET);
ae99258f 1778 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
89b667f8
JB		 1779 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1780 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1781 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1782 DPIO_PCS_CLK_SOFT_RESET);
1783
1784 /* Fix up inter-pair skew failure */
ae99258f
JN		 1785 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1786 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1787 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
0980a60f 1788 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1789}
1790
1791/*
df0c237d
JB		 1792 * Native read with retry for link status and receiver capability reads for
1793 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1794 */
1795static bool
df0c237d
JB		 1796intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1797 uint8_t *recv, int recv_bytes)
a4fc5ed6 1798{
61da5fab
JB		 1799 int ret, i;
1800
df0c237d
JB		 1801 /*
1802 * Sinks are *supposed* to come up within 1ms from an off state,
1803 * but we're also supposed to retry 3 times per the spec.
1804 */
61da5fab 1805 for (i = 0; i < 3; i++) {
df0c237d
JB		 1806 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1807 recv_bytes);
1808 if (ret == recv_bytes)
61da5fab
JB		 1809 return true;
1810 msleep(1);
1811 }
a4fc5ed6 1812
61da5fab 1813 return false;
a4fc5ed6
KP		 1814}
1815
1816/*
1817 * Fetch AUX CH registers 0x202 - 0x207 which contain
1818 * link status information
1819 */
1820static bool
93f62dad 1821intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1822{
df0c237d
JB		 1823 return intel_dp_aux_native_read_retry(intel_dp,
1824 DP_LANE0_1_STATUS,
93f62dad 1825 link_status,
df0c237d 1826 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1827}
1828
a4fc5ed6
KP		 1829#if 0
1830static char *voltage_names[] = {
1831 "0.4V", "0.6V", "0.8V", "1.2V"
1832};
1833static char *pre_emph_names[] = {
1834 "0dB", "3.5dB", "6dB", "9.5dB"
1835};
1836static char *link_train_names[] = {
1837 "pattern 1", "pattern 2", "idle", "off"
1838};
1839#endif
1840
1841/*
1842 * These are source-specific values; current Intel hardware supports
1843 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1844 */
a4fc5ed6
KP		 1845
1846static uint8_t
1a2eb460 1847intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1848{
30add22d 1849 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1850 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1851
e2fa6fba
P		 1852 if (IS_VALLEYVIEW(dev))
1853 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1854 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1855 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1856 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1857 return DP_TRAIN_VOLTAGE_SWING_1200;
1858 else
1859 return DP_TRAIN_VOLTAGE_SWING_800;
1860}
1861
1862static uint8_t
1863intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1864{
30add22d 1865 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1866 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1867
22b8bf17 1868 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1869 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1870 case DP_TRAIN_VOLTAGE_SWING_400:
1871 return DP_TRAIN_PRE_EMPHASIS_9_5;
1872 case DP_TRAIN_VOLTAGE_SWING_600:
1873 return DP_TRAIN_PRE_EMPHASIS_6;
1874 case DP_TRAIN_VOLTAGE_SWING_800:
1875 return DP_TRAIN_PRE_EMPHASIS_3_5;
1876 case DP_TRAIN_VOLTAGE_SWING_1200:
1877 default:
1878 return DP_TRAIN_PRE_EMPHASIS_0;
1879 }
e2fa6fba
P		 1880 } else if (IS_VALLEYVIEW(dev)) {
1881 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1882 case DP_TRAIN_VOLTAGE_SWING_400:
1883 return DP_TRAIN_PRE_EMPHASIS_9_5;
1884 case DP_TRAIN_VOLTAGE_SWING_600:
1885 return DP_TRAIN_PRE_EMPHASIS_6;
1886 case DP_TRAIN_VOLTAGE_SWING_800:
1887 return DP_TRAIN_PRE_EMPHASIS_3_5;
1888 case DP_TRAIN_VOLTAGE_SWING_1200:
1889 default:
1890 return DP_TRAIN_PRE_EMPHASIS_0;
1891 }
bc7d38a4 1892 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1893 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1894 case DP_TRAIN_VOLTAGE_SWING_400:
1895 return DP_TRAIN_PRE_EMPHASIS_6;
1896 case DP_TRAIN_VOLTAGE_SWING_600:
1897 case DP_TRAIN_VOLTAGE_SWING_800:
1898 return DP_TRAIN_PRE_EMPHASIS_3_5;
1899 default:
1900 return DP_TRAIN_PRE_EMPHASIS_0;
1901 }
1902 } else {
1903 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1904 case DP_TRAIN_VOLTAGE_SWING_400:
1905 return DP_TRAIN_PRE_EMPHASIS_6;
1906 case DP_TRAIN_VOLTAGE_SWING_600:
1907 return DP_TRAIN_PRE_EMPHASIS_6;
1908 case DP_TRAIN_VOLTAGE_SWING_800:
1909 return DP_TRAIN_PRE_EMPHASIS_3_5;
1910 case DP_TRAIN_VOLTAGE_SWING_1200:
1911 default:
1912 return DP_TRAIN_PRE_EMPHASIS_0;
1913 }
a4fc5ed6
KP		 1914 }
1915}
1916
e2fa6fba
P		 1917static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1918{
1919 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1920 struct drm_i915_private *dev_priv = dev->dev_private;
1921 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1922 unsigned long demph_reg_value, preemph_reg_value,
1923 uniqtranscale_reg_value;
1924 uint8_t train_set = intel_dp->train_set[0];
cece5d58 1925 int port = vlv_dport_to_channel(dport);
e2fa6fba
P		 1926
1927 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1928 case DP_TRAIN_PRE_EMPHASIS_0:
1929 preemph_reg_value = 0x0004000;
1930 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1931 case DP_TRAIN_VOLTAGE_SWING_400:
1932 demph_reg_value = 0x2B405555;
1933 uniqtranscale_reg_value = 0x552AB83A;
1934 break;
1935 case DP_TRAIN_VOLTAGE_SWING_600:
1936 demph_reg_value = 0x2B404040;
1937 uniqtranscale_reg_value = 0x5548B83A;
1938 break;
1939 case DP_TRAIN_VOLTAGE_SWING_800:
1940 demph_reg_value = 0x2B245555;
1941 uniqtranscale_reg_value = 0x5560B83A;
1942 break;
1943 case DP_TRAIN_VOLTAGE_SWING_1200:
1944 demph_reg_value = 0x2B405555;
1945 uniqtranscale_reg_value = 0x5598DA3A;
1946 break;
1947 default:
1948 return 0;
1949 }
1950 break;
1951 case DP_TRAIN_PRE_EMPHASIS_3_5:
1952 preemph_reg_value = 0x0002000;
1953 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1954 case DP_TRAIN_VOLTAGE_SWING_400:
1955 demph_reg_value = 0x2B404040;
1956 uniqtranscale_reg_value = 0x5552B83A;
1957 break;
1958 case DP_TRAIN_VOLTAGE_SWING_600:
1959 demph_reg_value = 0x2B404848;
1960 uniqtranscale_reg_value = 0x5580B83A;
1961 break;
1962 case DP_TRAIN_VOLTAGE_SWING_800:
1963 demph_reg_value = 0x2B404040;
1964 uniqtranscale_reg_value = 0x55ADDA3A;
1965 break;
1966 default:
1967 return 0;
1968 }
1969 break;
1970 case DP_TRAIN_PRE_EMPHASIS_6:
1971 preemph_reg_value = 0x0000000;
1972 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1973 case DP_TRAIN_VOLTAGE_SWING_400:
1974 demph_reg_value = 0x2B305555;
1975 uniqtranscale_reg_value = 0x5570B83A;
1976 break;
1977 case DP_TRAIN_VOLTAGE_SWING_600:
1978 demph_reg_value = 0x2B2B4040;
1979 uniqtranscale_reg_value = 0x55ADDA3A;
1980 break;
1981 default:
1982 return 0;
1983 }
1984 break;
1985 case DP_TRAIN_PRE_EMPHASIS_9_5:
1986 preemph_reg_value = 0x0006000;
1987 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1988 case DP_TRAIN_VOLTAGE_SWING_400:
1989 demph_reg_value = 0x1B405555;
1990 uniqtranscale_reg_value = 0x55ADDA3A;
1991 break;
1992 default:
1993 return 0;
1994 }
1995 break;
1996 default:
1997 return 0;
1998 }
1999
0980a60f 2000 mutex_lock(&dev_priv->dpio_lock);
ae99258f
JN		 2001 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
2002 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
2003 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
e2fa6fba 2004 uniqtranscale_reg_value);
ae99258f
JN		 2005 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
2006 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
2007 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
2008 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
0980a60f 2009 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2010
2011 return 0;
2012}
2013
a4fc5ed6 2014static void
93f62dad 2015intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2016{
2017 uint8_t v = 0;
2018 uint8_t p = 0;
2019 int lane;
1a2eb460
KP		 2020 uint8_t voltage_max;
2021 uint8_t preemph_max;
a4fc5ed6 2022
33a34e4e 2023 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2024 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2025 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2026
2027 if (this_v > v)
2028 v = this_v;
2029 if (this_p > p)
2030 p = this_p;
2031 }
2032
1a2eb460 2033 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2034 if (v >= voltage_max)
2035 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2036
1a2eb460
KP		 2037 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2038 if (p >= preemph_max)
2039 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2040
2041 for (lane = 0; lane < 4; lane++)
33a34e4e 2042 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2043}
2044
2045static uint32_t
f0a3424e 2046intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2047{
3cf2efb1 2048 uint32_t signal_levels = 0;
a4fc5ed6 2049
3cf2efb1 2050 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2051 case DP_TRAIN_VOLTAGE_SWING_400:
2052 default:
2053 signal_levels |= DP_VOLTAGE_0_4;
2054 break;
2055 case DP_TRAIN_VOLTAGE_SWING_600:
2056 signal_levels |= DP_VOLTAGE_0_6;
2057 break;
2058 case DP_TRAIN_VOLTAGE_SWING_800:
2059 signal_levels |= DP_VOLTAGE_0_8;
2060 break;
2061 case DP_TRAIN_VOLTAGE_SWING_1200:
2062 signal_levels |= DP_VOLTAGE_1_2;
2063 break;
2064 }
3cf2efb1 2065 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2066 case DP_TRAIN_PRE_EMPHASIS_0:
2067 default:
2068 signal_levels |= DP_PRE_EMPHASIS_0;
2069 break;
2070 case DP_TRAIN_PRE_EMPHASIS_3_5:
2071 signal_levels |= DP_PRE_EMPHASIS_3_5;
2072 break;
2073 case DP_TRAIN_PRE_EMPHASIS_6:
2074 signal_levels |= DP_PRE_EMPHASIS_6;
2075 break;
2076 case DP_TRAIN_PRE_EMPHASIS_9_5:
2077 signal_levels |= DP_PRE_EMPHASIS_9_5;
2078 break;
2079 }
2080 return signal_levels;
2081}
2082
e3421a18
ZW		 2083/* Gen6's DP voltage swing and pre-emphasis control */
2084static uint32_t
2085intel_gen6_edp_signal_levels(uint8_t train_set)
2086{
3c5a62b5
YL		 2087 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2088 DP_TRAIN_PRE_EMPHASIS_MASK);
2089 switch (signal_levels) {
e3421a18 2090 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2091 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2092 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2093 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2094 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2095 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2096 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2097 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2098 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2099 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2100 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2101 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2102 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2103 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2104 default:
3c5a62b5
YL		 2105 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2106 "0x%x\n", signal_levels);
2107 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2108 }
2109}
2110
1a2eb460
KP		 2111/* Gen7's DP voltage swing and pre-emphasis control */
2112static uint32_t
2113intel_gen7_edp_signal_levels(uint8_t train_set)
2114{
2115 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2116 DP_TRAIN_PRE_EMPHASIS_MASK);
2117 switch (signal_levels) {
2118 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2119 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2120 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2121 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2122 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2123 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2124
2125 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2126 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2127 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2128 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2129
2130 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2131 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2132 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2133 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2134
2135 default:
2136 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2137 "0x%x\n", signal_levels);
2138 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2139 }
2140}
2141
d6c0d722
PZ		 2142/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2143static uint32_t
f0a3424e 2144intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2145{
d6c0d722
PZ		 2146 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2147 DP_TRAIN_PRE_EMPHASIS_MASK);
2148 switch (signal_levels) {
2149 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2150 return DDI_BUF_EMP_400MV_0DB_HSW;
2151 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2152 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2153 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2154 return DDI_BUF_EMP_400MV_6DB_HSW;
2155 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2156 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2157
d6c0d722
PZ		 2158 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2159 return DDI_BUF_EMP_600MV_0DB_HSW;
2160 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2161 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2162 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2163 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2164
d6c0d722
PZ		 2165 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2166 return DDI_BUF_EMP_800MV_0DB_HSW;
2167 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2168 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2169 default:
2170 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2171 "0x%x\n", signal_levels);
2172 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2173 }
a4fc5ed6
KP		 2174}
2175
f0a3424e
PZ		 2176/* Properly updates "DP" with the correct signal levels. */
2177static void
2178intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2179{
2180 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2181 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2182 struct drm_device *dev = intel_dig_port->base.base.dev;
2183 uint32_t signal_levels, mask;
2184 uint8_t train_set = intel_dp->train_set[0];
2185
22b8bf17 2186 if (HAS_DDI(dev)) {
f0a3424e
PZ		 2187 signal_levels = intel_hsw_signal_levels(train_set);
2188 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2189 } else if (IS_VALLEYVIEW(dev)) {
2190 signal_levels = intel_vlv_signal_levels(intel_dp);
2191 mask = 0;
bc7d38a4 2192 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2193 signal_levels = intel_gen7_edp_signal_levels(train_set);
2194 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2195 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2196 signal_levels = intel_gen6_edp_signal_levels(train_set);
2197 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2198 } else {
2199 signal_levels = intel_gen4_signal_levels(train_set);
2200 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2201 }
2202
2203 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2204
2205 *DP = (*DP & ~mask) | signal_levels;
2206}
2207
a4fc5ed6 2208static bool
ea5b213a 2209intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 2210 uint32_t dp_reg_value,
58e10eb9 2211 uint8_t dp_train_pat)
a4fc5ed6 2212{
174edf1f
PZ		 2213 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2214 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2215 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2216 enum port port = intel_dig_port->port;
a4fc5ed6
KP		 2217 int ret;
2218
22b8bf17 2219 if (HAS_DDI(dev)) {
3ab9c637 2220 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2221
2222 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2223 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2224 else
2225 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2226
2227 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2228 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2229 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2230 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2231
2232 break;
2233 case DP_TRAINING_PATTERN_1:
2234 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2235 break;
2236 case DP_TRAINING_PATTERN_2:
2237 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2238 break;
2239 case DP_TRAINING_PATTERN_3:
2240 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2241 break;
2242 }
174edf1f 2243 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2244
bc7d38a4 2245 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
47ea7542
PZ		 2246 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
2247
2248 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2249 case DP_TRAINING_PATTERN_DISABLE:
2250 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
2251 break;
2252 case DP_TRAINING_PATTERN_1:
2253 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
2254 break;
2255 case DP_TRAINING_PATTERN_2:
2256 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2257 break;
2258 case DP_TRAINING_PATTERN_3:
2259 DRM_ERROR("DP training pattern 3 not supported\n");
2260 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2261 break;
2262 }
2263
2264 } else {
2265 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2266
2267 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2268 case DP_TRAINING_PATTERN_DISABLE:
2269 dp_reg_value |= DP_LINK_TRAIN_OFF;
2270 break;
2271 case DP_TRAINING_PATTERN_1:
2272 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2273 break;
2274 case DP_TRAINING_PATTERN_2:
2275 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2276 break;
2277 case DP_TRAINING_PATTERN_3:
2278 DRM_ERROR("DP training pattern 3 not supported\n");
2279 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2280 break;
2281 }
2282 }
2283
ea5b213a
CW		 2284 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2285 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2286
ea5b213a 2287 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 2288 DP_TRAINING_PATTERN_SET,
2289 dp_train_pat);
2290
47ea7542
PZ		 2291 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2292 DP_TRAINING_PATTERN_DISABLE) {
2293 ret = intel_dp_aux_native_write(intel_dp,
2294 DP_TRAINING_LANE0_SET,
2295 intel_dp->train_set,
2296 intel_dp->lane_count);
2297 if (ret != intel_dp->lane_count)
2298 return false;
2299 }
a4fc5ed6
KP		 2300
2301 return true;
2302}
2303
3ab9c637
ID		 2304static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2305{
2306 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2307 struct drm_device *dev = intel_dig_port->base.base.dev;
2308 struct drm_i915_private *dev_priv = dev->dev_private;
2309 enum port port = intel_dig_port->port;
2310 uint32_t val;
2311
2312 if (!HAS_DDI(dev))
2313 return;
2314
2315 val = I915_READ(DP_TP_CTL(port));
2316 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2317 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2318 I915_WRITE(DP_TP_CTL(port), val);
2319
2320 /*
2321 * On PORT_A we can have only eDP in SST mode. There the only reason
2322 * we need to set idle transmission mode is to work around a HW issue
2323 * where we enable the pipe while not in idle link-training mode.
2324 * In this case there is requirement to wait for a minimum number of
2325 * idle patterns to be sent.
2326 */
2327 if (port == PORT_A)
2328 return;
2329
2330 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2331 1))
2332 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2333}
2334
33a34e4e 2335/* Enable corresponding port and start training pattern 1 */
c19b0669 2336void
33a34e4e 2337intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2338{
da63a9f2 2339 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2340 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2341 int i;
2342 uint8_t voltage;
cdb0e95b 2343 int voltage_tries, loop_tries;
ea5b213a 2344 uint32_t DP = intel_dp->DP;
a4fc5ed6 2345
affa9354 2346 if (HAS_DDI(dev))
c19b0669
PZ		 2347 intel_ddi_prepare_link_retrain(encoder);
2348
3cf2efb1
CW		 2349 /* Write the link configuration data */
2350 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2351 intel_dp->link_configuration,
2352 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 2353
2354 DP |= DP_PORT_EN;
1a2eb460 2355
33a34e4e 2356 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 2357 voltage = 0xff;
cdb0e95b
KP		 2358 voltage_tries = 0;
2359 loop_tries = 0;
a4fc5ed6 2360 for (;;) {
33a34e4e 2361 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 2362 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 2363
2364 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 2365
a7c9655f 2366 /* Set training pattern 1 */
47ea7542 2367 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2368 DP_TRAINING_PATTERN_1 |
2369 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 2370 break;
a4fc5ed6 2371
a7c9655f 2372 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2373 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2374 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2375 break;
93f62dad 2376 }
a4fc5ed6 2377
01916270 2378 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2379 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2380 break;
2381 }
2382
2383 /* Check to see if we've tried the max voltage */
2384 for (i = 0; i < intel_dp->lane_count; i++)
2385 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2386 break;
3b4f819d 2387 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2388 ++loop_tries;
2389 if (loop_tries == 5) {
cdb0e95b
KP		 2390 DRM_DEBUG_KMS("too many full retries, give up\n");
2391 break;
2392 }
2393 memset(intel_dp->train_set, 0, 4);
2394 voltage_tries = 0;
2395 continue;
2396 }
a4fc5ed6 2397
3cf2efb1 2398 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2399 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2400 ++voltage_tries;
b06fbda3
DV		 2401 if (voltage_tries == 5) {
2402 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2403 break;
2404 }
2405 } else
2406 voltage_tries = 0;
2407 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2408
3cf2efb1 2409 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2410 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 2411 }
2412
33a34e4e
JB		 2413 intel_dp->DP = DP;
2414}
2415
c19b0669 2416void
33a34e4e
JB		 2417intel_dp_complete_link_train(struct intel_dp *intel_dp)
2418{
33a34e4e 2419 bool channel_eq = false;
37f80975 2420 int tries, cr_tries;
33a34e4e
JB		 2421 uint32_t DP = intel_dp->DP;
2422
a4fc5ed6
KP		 2423 /* channel equalization */
2424 tries = 0;
37f80975 2425 cr_tries = 0;
a4fc5ed6
KP		 2426 channel_eq = false;
2427 for (;;) {
93f62dad 2428 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2429
37f80975
JB		 2430 if (cr_tries > 5) {
2431 DRM_ERROR("failed to train DP, aborting\n");
2432 intel_dp_link_down(intel_dp);
2433 break;
2434 }
2435
f0a3424e 2436 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 2437
a4fc5ed6 2438 /* channel eq pattern */
47ea7542 2439 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2440 DP_TRAINING_PATTERN_2 |
2441 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 2442 break;
2443
a7c9655f 2444 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2445 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2446 break;
a4fc5ed6 2447
37f80975 2448 /* Make sure clock is still ok */
01916270 2449 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2450 intel_dp_start_link_train(intel_dp);
2451 cr_tries++;
2452 continue;
2453 }
2454
1ffdff13 2455 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2456 channel_eq = true;
2457 break;
2458 }
a4fc5ed6 2459
37f80975
JB		 2460 /* Try 5 times, then try clock recovery if that fails */
2461 if (tries > 5) {
2462 intel_dp_link_down(intel_dp);
2463 intel_dp_start_link_train(intel_dp);
2464 tries = 0;
2465 cr_tries++;
2466 continue;
2467 }
a4fc5ed6 2468
3cf2efb1 2469 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2470 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2471 ++tries;
869184a6 2472 }
3cf2efb1 2473
3ab9c637
ID		 2474 intel_dp_set_idle_link_train(intel_dp);
2475
2476 intel_dp->DP = DP;
2477
d6c0d722 2478 if (channel_eq)
07f42258 2479 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2480
3ab9c637
ID		 2481}
2482
2483void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2484{
2485 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2486 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2487}
2488
2489static void
ea5b213a 2490intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2491{
da63a9f2 2492 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2493 enum port port = intel_dig_port->port;
da63a9f2 2494 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2495 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2496 struct intel_crtc *intel_crtc =
2497 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2498 uint32_t DP = intel_dp->DP;
a4fc5ed6 2499
c19b0669
PZ		 2500 /*
2501 * DDI code has a strict mode set sequence and we should try to respect
2502 * it, otherwise we might hang the machine in many different ways. So we
2503 * really should be disabling the port only on a complete crtc_disable
2504 * sequence. This function is just called under two conditions on DDI
2505 * code:
2506 * - Link train failed while doing crtc_enable, and on this case we
2507 * really should respect the mode set sequence and wait for a
2508 * crtc_disable.
2509 * - Someone turned the monitor off and intel_dp_check_link_status
2510 * called us. We don't need to disable the whole port on this case, so
2511 * when someone turns the monitor on again,
2512 * intel_ddi_prepare_link_retrain will take care of redoing the link
2513 * train.
2514 */
affa9354 2515 if (HAS_DDI(dev))
c19b0669
PZ		 2516 return;
2517
0c33d8d7 2518 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2519 return;
2520
28c97730 2521 DRM_DEBUG_KMS("\n");
32f9d658 2522
bc7d38a4 2523 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2524 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2525 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2526 } else {
2527 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2528 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2529 }
fe255d00 2530 POSTING_READ(intel_dp->output_reg);
5eb08b69 2531
ab527efc
DV		 2532 /* We don't really know why we're doing this */
2533 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2534
493a7081 2535 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2536 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2537 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2538
5bddd17f
EA		 2539 /* Hardware workaround: leaving our transcoder select
2540 * set to transcoder B while it's off will prevent the
2541 * corresponding HDMI output on transcoder A.
2542 *
2543 * Combine this with another hardware workaround:
2544 * transcoder select bit can only be cleared while the
2545 * port is enabled.
2546 */
2547 DP &= ~DP_PIPEB_SELECT;
2548 I915_WRITE(intel_dp->output_reg, DP);
2549
2550 /* Changes to enable or select take place the vblank
2551 * after being written.
2552 */
ff50afe9
DV		 2553 if (WARN_ON(crtc == NULL)) {
2554 /* We should never try to disable a port without a crtc
2555 * attached. For paranoia keep the code around for a
2556 * bit. */
31acbcc4
CW		 2557 POSTING_READ(intel_dp->output_reg);
2558 msleep(50);
2559 } else
ab527efc 2560 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2561 }
2562
832afda6 2563 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2564 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2565 POSTING_READ(intel_dp->output_reg);
f01eca2e 2566 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2567}
2568
26d61aad
KP		 2569static bool
2570intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2571{
577c7a50
DL		 2572 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2573
92fd8fd1 2574 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2575 sizeof(intel_dp->dpcd)) == 0)
2576 return false; /* aux transfer failed */
92fd8fd1 2577
577c7a50
DL		 2578 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2579 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2580 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2581
edb39244
AJ		 2582 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2583 return false; /* DPCD not present */
2584
2293bb5c
SK		 2585 /* Check if the panel supports PSR */
2586 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2587 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2588 intel_dp->psr_dpcd,
2589 sizeof(intel_dp->psr_dpcd));
2590 if (is_edp_psr(intel_dp))
2591 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
edb39244
AJ		 2592 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2593 DP_DWN_STRM_PORT_PRESENT))
2594 return true; /* native DP sink */
2595
2596 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2597 return true; /* no per-port downstream info */
2598
2599 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2600 intel_dp->downstream_ports,
2601 DP_MAX_DOWNSTREAM_PORTS) == 0)
2602 return false; /* downstream port status fetch failed */
2603
2604 return true;
92fd8fd1
KP		 2605}
2606
0d198328
AJ		 2607static void
2608intel_dp_probe_oui(struct intel_dp *intel_dp)
2609{
2610 u8 buf[3];
2611
2612 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2613 return;
2614
351cfc34
DV		 2615 ironlake_edp_panel_vdd_on(intel_dp);
2616
0d198328
AJ		 2617 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2618 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2619 buf[0], buf[1], buf[2]);
2620
2621 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2622 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2623 buf[0], buf[1], buf[2]);
351cfc34
DV		 2624
2625 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2626}
2627
a60f0e38
JB		 2628static bool
2629intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2630{
2631 int ret;
2632
2633 ret = intel_dp_aux_native_read_retry(intel_dp,
2634 DP_DEVICE_SERVICE_IRQ_VECTOR,
2635 sink_irq_vector, 1);
2636 if (!ret)
2637 return false;
2638
2639 return true;
2640}
2641
2642static void
2643intel_dp_handle_test_request(struct intel_dp *intel_dp)
2644{
2645 /* NAK by default */
9324cf7f 2646 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2647}
2648
a4fc5ed6
KP		 2649/*
2650 * According to DP spec
2651 * 5.1.2:
2652 * 1. Read DPCD
2653 * 2. Configure link according to Receiver Capabilities
2654 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2655 * 4. Check link status on receipt of hot-plug interrupt
2656 */
2657
00c09d70 2658void
ea5b213a 2659intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2660{
da63a9f2 2661 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2662 u8 sink_irq_vector;
93f62dad 2663 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2664
da63a9f2 2665 if (!intel_encoder->connectors_active)
d2b996ac 2666 return;
59cd09e1 2667
da63a9f2 2668 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2669 return;
2670
92fd8fd1 2671 /* Try to read receiver status if the link appears to be up */
93f62dad 2672 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2673 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2674 return;
2675 }
2676
92fd8fd1 2677 /* Now read the DPCD to see if it's actually running */
26d61aad 2678 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2679 intel_dp_link_down(intel_dp);
2680 return;
2681 }
2682
a60f0e38
JB		 2683 /* Try to read the source of the interrupt */
2684 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2685 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2686 /* Clear interrupt source */
2687 intel_dp_aux_native_write_1(intel_dp,
2688 DP_DEVICE_SERVICE_IRQ_VECTOR,
2689 sink_irq_vector);
2690
2691 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2692 intel_dp_handle_test_request(intel_dp);
2693 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2694 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2695 }
2696
1ffdff13 2697 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2698 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2699 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2700 intel_dp_start_link_train(intel_dp);
2701 intel_dp_complete_link_train(intel_dp);
3ab9c637 2702 intel_dp_stop_link_train(intel_dp);
33a34e4e 2703 }
a4fc5ed6 2704}
a4fc5ed6 2705
caf9ab24 2706/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2707static enum drm_connector_status
26d61aad 2708intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2709{
caf9ab24
AJ		 2710 uint8_t *dpcd = intel_dp->dpcd;
2711 bool hpd;
2712 uint8_t type;
2713
2714 if (!intel_dp_get_dpcd(intel_dp))
2715 return connector_status_disconnected;
2716
2717 /* if there's no downstream port, we're done */
2718 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2719 return connector_status_connected;
caf9ab24
AJ		 2720
2721 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2722 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2723 if (hpd) {
23235177 2724 uint8_t reg;
caf9ab24 2725 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2726 &reg, 1))
caf9ab24 2727 return connector_status_unknown;
23235177
AJ		 2728 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2729 : connector_status_disconnected;
caf9ab24
AJ		 2730 }
2731
2732 /* If no HPD, poke DDC gently */
2733 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2734 return connector_status_connected;
caf9ab24
AJ		 2735
2736 /* Well we tried, say unknown for unreliable port types */
2737 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2738 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2739 return connector_status_unknown;
2740
2741 /* Anything else is out of spec, warn and ignore */
2742 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2743 return connector_status_disconnected;
71ba9000
AJ		 2744}
2745
5eb08b69 2746static enum drm_connector_status
a9756bb5 2747ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2748{
30add22d 2749 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2750 struct drm_i915_private *dev_priv = dev->dev_private;
2751 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2752 enum drm_connector_status status;
2753
fe16d949
CW		 2754 /* Can't disconnect eDP, but you can close the lid... */
2755 if (is_edp(intel_dp)) {
30add22d 2756 status = intel_panel_detect(dev);
fe16d949
CW		 2757 if (status == connector_status_unknown)
2758 status = connector_status_connected;
2759 return status;
2760 }
01cb9ea6 2761
1b469639
DL		 2762 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2763 return connector_status_disconnected;
2764
26d61aad 2765 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2766}
2767
a4fc5ed6 2768static enum drm_connector_status
a9756bb5 2769g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2770{
30add22d 2771 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2772 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2773 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2774 uint32_t bit;
5eb08b69 2775
35aad75f
JB		 2776 /* Can't disconnect eDP, but you can close the lid... */
2777 if (is_edp(intel_dp)) {
2778 enum drm_connector_status status;
2779
2780 status = intel_panel_detect(dev);
2781 if (status == connector_status_unknown)
2782 status = connector_status_connected;
2783 return status;
2784 }
2785
34f2be46
VS		 2786 switch (intel_dig_port->port) {
2787 case PORT_B:
26739f12 2788 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2789 break;
34f2be46 2790 case PORT_C:
26739f12 2791 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2792 break;
34f2be46 2793 case PORT_D:
26739f12 2794 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2795 break;
2796 default:
2797 return connector_status_unknown;
2798 }
2799
10f76a38 2800 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2801 return connector_status_disconnected;
2802
26d61aad 2803 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2804}
2805
8c241fef
KP		 2806static struct edid *
2807intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2808{
9cd300e0 2809 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2810
9cd300e0
JN		 2811 /* use cached edid if we have one */
2812 if (intel_connector->edid) {
2813 struct edid *edid;
2814 int size;
2815
2816 /* invalid edid */
2817 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2818 return NULL;
2819
9cd300e0 2820 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
edbe1581 2821 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
d6f24d0f
JB		 2822 if (!edid)
2823 return NULL;
2824
d6f24d0f
JB		 2825 return edid;
2826 }
8c241fef 2827
9cd300e0 2828 return drm_get_edid(connector, adapter);
8c241fef
KP		 2829}
2830
2831static int
2832intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2833{
9cd300e0 2834 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2835
9cd300e0
JN		 2836 /* use cached edid if we have one */
2837 if (intel_connector->edid) {
2838 /* invalid edid */
2839 if (IS_ERR(intel_connector->edid))
2840 return 0;
2841
2842 return intel_connector_update_modes(connector,
2843 intel_connector->edid);
d6f24d0f
JB		 2844 }
2845
9cd300e0 2846 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2847}
2848
a9756bb5
ZW		 2849static enum drm_connector_status
2850intel_dp_detect(struct drm_connector *connector, bool force)
2851{
2852 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2853 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2854 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2855 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2856 enum drm_connector_status status;
2857 struct edid *edid = NULL;
2858
164c8598
CW		 2859 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2860 connector->base.id, drm_get_connector_name(connector));
2861
a9756bb5
ZW		 2862 intel_dp->has_audio = false;
2863
2864 if (HAS_PCH_SPLIT(dev))
2865 status = ironlake_dp_detect(intel_dp);
2866 else
2867 status = g4x_dp_detect(intel_dp);
1b9be9d0 2868
a9756bb5
ZW		 2869 if (status != connector_status_connected)
2870 return status;
2871
0d198328
AJ		 2872 intel_dp_probe_oui(intel_dp);
2873
c3e5f67b
DV		 2874 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2875 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2876 } else {
8c241fef 2877 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2878 if (edid) {
2879 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2880 kfree(edid);
2881 }
a9756bb5
ZW		 2882 }
2883
d63885da
PZ		 2884 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2885 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2886 return connector_status_connected;
a4fc5ed6
KP		 2887}
2888
2889static int intel_dp_get_modes(struct drm_connector *connector)
2890{
df0e9248 2891 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2892 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2893 struct drm_device *dev = connector->dev;
32f9d658 2894 int ret;
a4fc5ed6
KP		 2895
2896 /* We should parse the EDID data and find out if it has an audio sink
2897 */
2898
8c241fef 2899 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2900 if (ret)
32f9d658
ZW		 2901 return ret;
2902
f8779fda 2903 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2904 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2905 struct drm_display_mode *mode;
dd06f90e
JN		 2906 mode = drm_mode_duplicate(dev,
2907 intel_connector->panel.fixed_mode);
f8779fda 2908 if (mode) {
32f9d658
ZW		 2909 drm_mode_probed_add(connector, mode);
2910 return 1;
2911 }
2912 }
2913 return 0;
a4fc5ed6
KP		 2914}
2915
1aad7ac0
CW		 2916static bool
2917intel_dp_detect_audio(struct drm_connector *connector)
2918{
2919 struct intel_dp *intel_dp = intel_attached_dp(connector);
2920 struct edid *edid;
2921 bool has_audio = false;
2922
8c241fef 2923 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2924 if (edid) {
2925 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2926 kfree(edid);
2927 }
2928
2929 return has_audio;
2930}
2931
f684960e
CW		 2932static int
2933intel_dp_set_property(struct drm_connector *connector,
2934 struct drm_property *property,
2935 uint64_t val)
2936{
e953fd7b 2937 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2938 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2939 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2940 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2941 int ret;
2942
662595df 2943 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2944 if (ret)
2945 return ret;
2946
3f43c48d 2947 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2948 int i = val;
2949 bool has_audio;
2950
2951 if (i == intel_dp->force_audio)
f684960e
CW		 2952 return 0;
2953
1aad7ac0 2954 intel_dp->force_audio = i;
f684960e 2955
c3e5f67b 2956 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2957 has_audio = intel_dp_detect_audio(connector);
2958 else
c3e5f67b 2959 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2960
2961 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2962 return 0;
2963
1aad7ac0 2964 intel_dp->has_audio = has_audio;
f684960e
CW		 2965 goto done;
2966 }
2967
e953fd7b 2968 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2969 bool old_auto = intel_dp->color_range_auto;
2970 uint32_t old_range = intel_dp->color_range;
2971
55bc60db
VS		 2972 switch (val) {
2973 case INTEL_BROADCAST_RGB_AUTO:
2974 intel_dp->color_range_auto = true;
2975 break;
2976 case INTEL_BROADCAST_RGB_FULL:
2977 intel_dp->color_range_auto = false;
2978 intel_dp->color_range = 0;
2979 break;
2980 case INTEL_BROADCAST_RGB_LIMITED:
2981 intel_dp->color_range_auto = false;
2982 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2983 break;
2984 default:
2985 return -EINVAL;
2986 }
ae4edb80
DV		 2987
2988 if (old_auto == intel_dp->color_range_auto &&
2989 old_range == intel_dp->color_range)
2990 return 0;
2991
e953fd7b
CW		 2992 goto done;
2993 }
2994
53b41837
YN		 2995 if (is_edp(intel_dp) &&
2996 property == connector->dev->mode_config.scaling_mode_property) {
2997 if (val == DRM_MODE_SCALE_NONE) {
2998 DRM_DEBUG_KMS("no scaling not supported\n");
2999 return -EINVAL;
3000 }
3001
3002 if (intel_connector->panel.fitting_mode == val) {
3003 /* the eDP scaling property is not changed */
3004 return 0;
3005 }
3006 intel_connector->panel.fitting_mode = val;
3007
3008 goto done;
3009 }
3010
f684960e
CW		 3011 return -EINVAL;
3012
3013done:
c0c36b94
CW		 3014 if (intel_encoder->base.crtc)
3015 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3016
3017 return 0;
3018}
3019
a4fc5ed6 3020static void
73845adf 3021intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3022{
1d508706 3023 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3024
9cd300e0
JN		 3025 if (!IS_ERR_OR_NULL(intel_connector->edid))
3026 kfree(intel_connector->edid);
3027
acd8db10
PZ		 3028 /* Can't call is_edp() since the encoder may have been destroyed
3029 * already. */
3030 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3031 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3032
a4fc5ed6
KP		 3033 drm_sysfs_connector_remove(connector);
3034 drm_connector_cleanup(connector);
55f78c43 3035 kfree(connector);
a4fc5ed6
KP		 3036}
3037
00c09d70 3038void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3039{
da63a9f2
PZ		 3040 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3041 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3042 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3043
3044 i2c_del_adapter(&intel_dp->adapter);
3045 drm_encoder_cleanup(encoder);
bd943159
KP		 3046 if (is_edp(intel_dp)) {
3047 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3048 mutex_lock(&dev->mode_config.mutex);
bd943159 3049 ironlake_panel_vdd_off_sync(intel_dp);
bd173813 3050 mutex_unlock(&dev->mode_config.mutex);
bd943159 3051 }
da63a9f2 3052 kfree(intel_dig_port);
24d05927
DV		 3053}
3054
a4fc5ed6 3055static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3056 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3057 .detect = intel_dp_detect,
3058 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3059 .set_property = intel_dp_set_property,
73845adf 3060 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3061};
3062
3063static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3064 .get_modes = intel_dp_get_modes,
3065 .mode_valid = intel_dp_mode_valid,
df0e9248 3066 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3067};
3068
a4fc5ed6 3069static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3070 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3071};
3072
995b6762 3073static void
21d40d37 3074intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3075{
fa90ecef 3076 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3077
885a5014 3078 intel_dp_check_link_status(intel_dp);
c8110e52 3079}
6207937d 3080
e3421a18
ZW		 3081/* Return which DP Port should be selected for Transcoder DP control */
3082int
0206e353 3083intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3084{
3085 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3086 struct intel_encoder *intel_encoder;
3087 struct intel_dp *intel_dp;
e3421a18 3088
fa90ecef
PZ		 3089 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3090 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3091
fa90ecef
PZ		 3092 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3093 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3094 return intel_dp->output_reg;
e3421a18 3095 }
ea5b213a 3096
e3421a18
ZW		 3097 return -1;
3098}
3099
36e83a18 3100/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 3101bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 3102{
3103 struct drm_i915_private *dev_priv = dev->dev_private;
3104 struct child_device_config *p_child;
3105 int i;
3106
41aa3448 3107 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3108 return false;
3109
41aa3448
RV		 3110 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3111 p_child = dev_priv->vbt.child_dev + i;
36e83a18
ZY		 3112
3113 if (p_child->dvo_port == PORT_IDPD &&
3114 p_child->device_type == DEVICE_TYPE_eDP)
3115 return true;
3116 }
3117 return false;
3118}
3119
f684960e
CW		 3120static void
3121intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3122{
53b41837
YN		 3123 struct intel_connector *intel_connector = to_intel_connector(connector);
3124
3f43c48d 3125 intel_attach_force_audio_property(connector);
e953fd7b 3126 intel_attach_broadcast_rgb_property(connector);
55bc60db 3127 intel_dp->color_range_auto = true;
53b41837
YN		 3128
3129 if (is_edp(intel_dp)) {
3130 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3131 drm_object_attach_property(
3132 &connector->base,
53b41837 3133 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3134 DRM_MODE_SCALE_ASPECT);
3135 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3136 }
f684960e
CW		 3137}
3138
67a54566
DV		 3139static void
3140intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3141 struct intel_dp *intel_dp,
3142 struct edp_power_seq *out)
67a54566
DV		 3143{
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 struct edp_power_seq cur, vbt, spec, final;
3146 u32 pp_on, pp_off, pp_div, pp;
453c5420
JB		 3147 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3148
3149 if (HAS_PCH_SPLIT(dev)) {
3150 pp_control_reg = PCH_PP_CONTROL;
3151 pp_on_reg = PCH_PP_ON_DELAYS;
3152 pp_off_reg = PCH_PP_OFF_DELAYS;
3153 pp_div_reg = PCH_PP_DIVISOR;
3154 } else {
3155 pp_control_reg = PIPEA_PP_CONTROL;
3156 pp_on_reg = PIPEA_PP_ON_DELAYS;
3157 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3158 pp_div_reg = PIPEA_PP_DIVISOR;
3159 }
67a54566
DV		 3160
3161 /* Workaround: Need to write PP_CONTROL with the unlock key as
3162 * the very first thing. */
453c5420
JB		 3163 pp = ironlake_get_pp_control(intel_dp);
3164 I915_WRITE(pp_control_reg, pp);
67a54566 3165
453c5420
JB		 3166 pp_on = I915_READ(pp_on_reg);
3167 pp_off = I915_READ(pp_off_reg);
3168 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3169
3170 /* Pull timing values out of registers */
3171 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3172 PANEL_POWER_UP_DELAY_SHIFT;
3173
3174 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3175 PANEL_LIGHT_ON_DELAY_SHIFT;
3176
3177 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3178 PANEL_LIGHT_OFF_DELAY_SHIFT;
3179
3180 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3181 PANEL_POWER_DOWN_DELAY_SHIFT;
3182
3183 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3184 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3185
3186 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3187 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3188
41aa3448 3189 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3190
3191 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3192 * our hw here, which are all in 100usec. */
3193 spec.t1_t3 = 210 * 10;
3194 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3195 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3196 spec.t10 = 500 * 10;
3197 /* This one is special and actually in units of 100ms, but zero
3198 * based in the hw (so we need to add 100 ms). But the sw vbt
3199 * table multiplies it with 1000 to make it in units of 100usec,
3200 * too. */
3201 spec.t11_t12 = (510 + 100) * 10;
3202
3203 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3204 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3205
3206 /* Use the max of the register settings and vbt. If both are
3207 * unset, fall back to the spec limits. */
3208#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3209 spec.field : \
3210 max(cur.field, vbt.field))
3211 assign_final(t1_t3);
3212 assign_final(t8);
3213 assign_final(t9);
3214 assign_final(t10);
3215 assign_final(t11_t12);
3216#undef assign_final
3217
3218#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3219 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3220 intel_dp->backlight_on_delay = get_delay(t8);
3221 intel_dp->backlight_off_delay = get_delay(t9);
3222 intel_dp->panel_power_down_delay = get_delay(t10);
3223 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3224#undef get_delay
3225
f30d26e4
JN		 3226 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3227 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3228 intel_dp->panel_power_cycle_delay);
3229
3230 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3231 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3232
3233 if (out)
3234 *out = final;
3235}
3236
3237static void
3238intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3239 struct intel_dp *intel_dp,
3240 struct edp_power_seq *seq)
3241{
3242 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3243 u32 pp_on, pp_off, pp_div, port_sel = 0;
3244 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3245 int pp_on_reg, pp_off_reg, pp_div_reg;
3246
3247 if (HAS_PCH_SPLIT(dev)) {
3248 pp_on_reg = PCH_PP_ON_DELAYS;
3249 pp_off_reg = PCH_PP_OFF_DELAYS;
3250 pp_div_reg = PCH_PP_DIVISOR;
3251 } else {
3252 pp_on_reg = PIPEA_PP_ON_DELAYS;
3253 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3254 pp_div_reg = PIPEA_PP_DIVISOR;
3255 }
3256
67a54566 3257 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 3258 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3259 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3260 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3261 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3262 /* Compute the divisor for the pp clock, simply match the Bspec
3263 * formula. */
453c5420 3264 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3265 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3266 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3267
3268 /* Haswell doesn't have any port selection bits for the panel
3269 * power sequencer any more. */
bc7d38a4
ID		 3270 if (IS_VALLEYVIEW(dev)) {
3271 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
3272 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3273 if (dp_to_dig_port(intel_dp)->port == PORT_A)
453c5420 3274 port_sel = PANEL_POWER_PORT_DP_A;
67a54566 3275 else
453c5420 3276 port_sel = PANEL_POWER_PORT_DP_D;
67a54566
DV		 3277 }
3278
453c5420
JB		 3279 pp_on |= port_sel;
3280
3281 I915_WRITE(pp_on_reg, pp_on);
3282 I915_WRITE(pp_off_reg, pp_off);
3283 I915_WRITE(pp_div_reg, pp_div);
67a54566 3284
67a54566 3285 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3286 I915_READ(pp_on_reg),
3287 I915_READ(pp_off_reg),
3288 I915_READ(pp_div_reg));
f684960e
CW		 3289}
3290
ed92f0b2
PZ		 3291static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3292 struct intel_connector *intel_connector)
3293{
3294 struct drm_connector *connector = &intel_connector->base;
3295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3296 struct drm_device *dev = intel_dig_port->base.base.dev;
3297 struct drm_i915_private *dev_priv = dev->dev_private;
3298 struct drm_display_mode *fixed_mode = NULL;
3299 struct edp_power_seq power_seq = { 0 };
3300 bool has_dpcd;
3301 struct drm_display_mode *scan;
3302 struct edid *edid;
3303
3304 if (!is_edp(intel_dp))
3305 return true;
3306
3307 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3308
3309 /* Cache DPCD and EDID for edp. */
3310 ironlake_edp_panel_vdd_on(intel_dp);
3311 has_dpcd = intel_dp_get_dpcd(intel_dp);
3312 ironlake_edp_panel_vdd_off(intel_dp, false);
3313
3314 if (has_dpcd) {
3315 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3316 dev_priv->no_aux_handshake =
3317 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3318 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3319 } else {
3320 /* if this fails, presume the device is a ghost */
3321 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3322 return false;
3323 }
3324
3325 /* We now know it's not a ghost, init power sequence regs. */
3326 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3327 &power_seq);
3328
3329 ironlake_edp_panel_vdd_on(intel_dp);
3330 edid = drm_get_edid(connector, &intel_dp->adapter);
3331 if (edid) {
3332 if (drm_add_edid_modes(connector, edid)) {
3333 drm_mode_connector_update_edid_property(connector,
3334 edid);
3335 drm_edid_to_eld(connector, edid);
3336 } else {
3337 kfree(edid);
3338 edid = ERR_PTR(-EINVAL);
3339 }
3340 } else {
3341 edid = ERR_PTR(-ENOENT);
3342 }
3343 intel_connector->edid = edid;
3344
3345 /* prefer fixed mode from EDID if available */
3346 list_for_each_entry(scan, &connector->probed_modes, head) {
3347 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3348 fixed_mode = drm_mode_duplicate(dev, scan);
3349 break;
3350 }
3351 }
3352
3353 /* fallback to VBT if available for eDP */
3354 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3355 fixed_mode = drm_mode_duplicate(dev,
3356 dev_priv->vbt.lfp_lvds_vbt_mode);
3357 if (fixed_mode)
3358 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3359 }
3360
3361 ironlake_edp_panel_vdd_off(intel_dp, false);
3362
3363 intel_panel_init(&intel_connector->panel, fixed_mode);
3364 intel_panel_setup_backlight(connector);
3365
3366 return true;
3367}
3368
16c25533 3369bool
f0fec3f2
PZ		 3370intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3371 struct intel_connector *intel_connector)
a4fc5ed6 3372{
f0fec3f2
PZ		 3373 struct drm_connector *connector = &intel_connector->base;
3374 struct intel_dp *intel_dp = &intel_dig_port->dp;
3375 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3376 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3377 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3378 enum port port = intel_dig_port->port;
5eb08b69 3379 const char *name = NULL;
b2a14755 3380 int type, error;
a4fc5ed6 3381
0767935e
DV		 3382 /* Preserve the current hw state. */
3383 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3384 intel_dp->attached_connector = intel_connector;
3d3dc149 3385
f7d24902 3386 type = DRM_MODE_CONNECTOR_DisplayPort;
19c03924
GB		 3387 /*
3388 * FIXME : We need to initialize built-in panels before external panels.
3389 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3390 */
f7d24902
ID		 3391 switch (port) {
3392 case PORT_A:
b329530c 3393 type = DRM_MODE_CONNECTOR_eDP;
f7d24902
ID		 3394 break;
3395 case PORT_C:
3396 if (IS_VALLEYVIEW(dev))
3397 type = DRM_MODE_CONNECTOR_eDP;
3398 break;
3399 case PORT_D:
3400 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3401 type = DRM_MODE_CONNECTOR_eDP;
3402 break;
3403 default: /* silence GCC warning */
3404 break;
b329530c
AJ		 3405 }
3406
f7d24902
ID		 3407 /*
3408 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3409 * for DP the encoder type can be set by the caller to
3410 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3411 */
3412 if (type == DRM_MODE_CONNECTOR_eDP)
3413 intel_encoder->type = INTEL_OUTPUT_EDP;
3414
e7281eab
ID		 3415 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3416 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3417 port_name(port));
3418
b329530c 3419 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3420 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3421
a4fc5ed6
KP		 3422 connector->interlace_allowed = true;
3423 connector->doublescan_allowed = 0;
3424
f0fec3f2
PZ		 3425 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3426 ironlake_panel_vdd_work);
a4fc5ed6 3427
df0e9248 3428 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3429 drm_sysfs_connector_add(connector);
3430
affa9354 3431 if (HAS_DDI(dev))
bcbc889b
PZ		 3432 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3433 else
3434 intel_connector->get_hw_state = intel_connector_get_hw_state;
3435
9ed35ab1
PZ		 3436 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3437 if (HAS_DDI(dev)) {
3438 switch (intel_dig_port->port) {
3439 case PORT_A:
3440 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3441 break;
3442 case PORT_B:
3443 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3444 break;
3445 case PORT_C:
3446 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3447 break;
3448 case PORT_D:
3449 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3450 break;
3451 default:
3452 BUG();
3453 }
3454 }
e8cb4558 3455
a4fc5ed6 3456 /* Set up the DDC bus. */
ab9d7c30
PZ		 3457 switch (port) {
3458 case PORT_A:
1d843f9d 3459 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3460 name = "DPDDC-A";
3461 break;
3462 case PORT_B:
1d843f9d 3463 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3464 name = "DPDDC-B";
3465 break;
3466 case PORT_C:
1d843f9d 3467 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3468 name = "DPDDC-C";
3469 break;
3470 case PORT_D:
1d843f9d 3471 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3472 name = "DPDDC-D";
3473 break;
3474 default:
ad1c0b19 3475 BUG();
5eb08b69
ZW		 3476 }
3477
b2a14755
PZ		 3478 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3479 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3480 error, port_name(port));
c1f05264 3481
2b28bb1b
RV		 3482 intel_dp->psr_setup_done = false;
3483
b2f246a8 3484 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
15b1d171
PZ		 3485 i2c_del_adapter(&intel_dp->adapter);
3486 if (is_edp(intel_dp)) {
3487 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3488 mutex_lock(&dev->mode_config.mutex);
3489 ironlake_panel_vdd_off_sync(intel_dp);
3490 mutex_unlock(&dev->mode_config.mutex);
3491 }
b2f246a8
PZ		 3492 drm_sysfs_connector_remove(connector);
3493 drm_connector_cleanup(connector);
16c25533 3494 return false;
b2f246a8 3495 }
32f9d658 3496
f684960e
CW		 3497 intel_dp_add_properties(intel_dp, connector);
3498
a4fc5ed6
KP		 3499 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3500 * 0xd. Failure to do so will result in spurious interrupts being
3501 * generated on the port when a cable is not attached.
3502 */
3503 if (IS_G4X(dev) && !IS_GM45(dev)) {
3504 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3505 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3506 }
16c25533
PZ		 3507
3508 return true;
a4fc5ed6 3509}
f0fec3f2
PZ		 3510
3511void
3512intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3513{
3514 struct intel_digital_port *intel_dig_port;
3515 struct intel_encoder *intel_encoder;
3516 struct drm_encoder *encoder;
3517 struct intel_connector *intel_connector;
3518
3519 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3520 if (!intel_dig_port)
3521 return;
3522
3523 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3524 if (!intel_connector) {
3525 kfree(intel_dig_port);
3526 return;
3527 }
3528
3529 intel_encoder = &intel_dig_port->base;
3530 encoder = &intel_encoder->base;
3531
3532 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3533 DRM_MODE_ENCODER_TMDS);
3534
5bfe2ac0 3535 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3536 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3537 intel_encoder->disable = intel_disable_dp;
3538 intel_encoder->post_disable = intel_post_disable_dp;
3539 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3540 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3541 if (IS_VALLEYVIEW(dev)) {
89b667f8 3542 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
ab1f90f9
JN		 3543 intel_encoder->pre_enable = vlv_pre_enable_dp;
3544 intel_encoder->enable = vlv_enable_dp;
3545 } else {
3546 intel_encoder->pre_enable = intel_pre_enable_dp;
3547 intel_encoder->enable = intel_enable_dp;
3548 }
f0fec3f2 3549
174edf1f 3550 intel_dig_port->port = port;
f0fec3f2
PZ		 3551 intel_dig_port->dp.output_reg = output_reg;
3552
00c09d70 3553 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3554 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3555 intel_encoder->cloneable = false;
3556 intel_encoder->hot_plug = intel_dp_hot_plug;
3557
15b1d171
PZ		 3558 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3559 drm_encoder_cleanup(encoder);
3560 kfree(intel_dig_port);
b2f246a8 3561 kfree(intel_connector);
15b1d171 3562 }
f0fec3f2 3563}
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