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Commit | Line | Data |
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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
a4fc5ed6 | 37 | #include "i915_drv.h" |
a4fc5ed6 | 38 | |
a4fc5ed6 KP |
39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
40 | ||
cfcb0fc9 JB |
41 | /** |
42 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
43 | * @intel_dp: DP struct | |
44 | * | |
45 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
46 | * will return true, and false otherwise. | |
47 | */ | |
48 | static bool is_edp(struct intel_dp *intel_dp) | |
49 | { | |
da63a9f2 PZ |
50 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
51 | ||
52 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
53 | } |
54 | ||
55 | /** | |
56 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? | |
57 | * @intel_dp: DP struct | |
58 | * | |
59 | * Returns true if the given DP struct corresponds to a PCH DP port attached | |
60 | * to an eDP panel, false otherwise. Helpful for determining whether we | |
61 | * may need FDI resources for a given DP output or not. | |
62 | */ | |
63 | static bool is_pch_edp(struct intel_dp *intel_dp) | |
64 | { | |
65 | return intel_dp->is_pch_edp; | |
66 | } | |
67 | ||
1c95822a AJ |
68 | /** |
69 | * is_cpu_edp - is the port on the CPU and attached to an eDP panel? | |
70 | * @intel_dp: DP struct | |
71 | * | |
72 | * Returns true if the given DP struct corresponds to a CPU eDP port. | |
73 | */ | |
74 | static bool is_cpu_edp(struct intel_dp *intel_dp) | |
75 | { | |
76 | return is_edp(intel_dp) && !is_pch_edp(intel_dp); | |
77 | } | |
78 | ||
30add22d | 79 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
ea5b213a | 80 | { |
da63a9f2 PZ |
81 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
82 | ||
83 | return intel_dig_port->base.base.dev; | |
ea5b213a | 84 | } |
a4fc5ed6 | 85 | |
df0e9248 CW |
86 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
87 | { | |
fa90ecef | 88 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
89 | } |
90 | ||
814948ad JB |
91 | /** |
92 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? | |
93 | * @encoder: DRM encoder | |
94 | * | |
95 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed | |
96 | * by intel_display.c. | |
97 | */ | |
98 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) | |
99 | { | |
100 | struct intel_dp *intel_dp; | |
101 | ||
102 | if (!encoder) | |
103 | return false; | |
104 | ||
105 | intel_dp = enc_to_intel_dp(encoder); | |
106 | ||
107 | return is_pch_edp(intel_dp); | |
108 | } | |
109 | ||
ea5b213a | 110 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
a4fc5ed6 | 111 | |
a4fc5ed6 | 112 | static int |
ea5b213a | 113 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 114 | { |
7183dc29 | 115 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
116 | |
117 | switch (max_link_bw) { | |
118 | case DP_LINK_BW_1_62: | |
119 | case DP_LINK_BW_2_7: | |
120 | break; | |
121 | default: | |
122 | max_link_bw = DP_LINK_BW_1_62; | |
123 | break; | |
124 | } | |
125 | return max_link_bw; | |
126 | } | |
127 | ||
cd9dde44 AJ |
128 | /* |
129 | * The units on the numbers in the next two are... bizarre. Examples will | |
130 | * make it clearer; this one parallels an example in the eDP spec. | |
131 | * | |
132 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
133 | * | |
134 | * 270000 * 1 * 8 / 10 == 216000 | |
135 | * | |
136 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
137 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
138 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
139 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
140 | * | |
141 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
142 | * get the result in decakilobits instead of kilobits. | |
143 | */ | |
144 | ||
a4fc5ed6 | 145 | static int |
c898261c | 146 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 147 | { |
cd9dde44 | 148 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
149 | } |
150 | ||
fe27d53e DA |
151 | static int |
152 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
153 | { | |
154 | return (max_link_clock * max_lanes * 8) / 10; | |
155 | } | |
156 | ||
a4fc5ed6 KP |
157 | static int |
158 | intel_dp_mode_valid(struct drm_connector *connector, | |
159 | struct drm_display_mode *mode) | |
160 | { | |
df0e9248 | 161 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
162 | struct intel_connector *intel_connector = to_intel_connector(connector); |
163 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
164 | int target_clock = mode->clock; |
165 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
a4fc5ed6 | 166 | |
dd06f90e JN |
167 | if (is_edp(intel_dp) && fixed_mode) { |
168 | if (mode->hdisplay > fixed_mode->hdisplay) | |
7de56f43 ZY |
169 | return MODE_PANEL; |
170 | ||
dd06f90e | 171 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 172 | return MODE_PANEL; |
03afc4a2 DV |
173 | |
174 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
175 | } |
176 | ||
36008365 DV |
177 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
178 | max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); | |
179 | ||
180 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
181 | mode_rate = intel_dp_link_required(target_clock, 18); | |
182 | ||
183 | if (mode_rate > max_rate) | |
c4867936 | 184 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
185 | |
186 | if (mode->clock < 10000) | |
187 | return MODE_CLOCK_LOW; | |
188 | ||
0af78a2b DV |
189 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
190 | return MODE_H_ILLEGAL; | |
191 | ||
a4fc5ed6 KP |
192 | return MODE_OK; |
193 | } | |
194 | ||
195 | static uint32_t | |
196 | pack_aux(uint8_t *src, int src_bytes) | |
197 | { | |
198 | int i; | |
199 | uint32_t v = 0; | |
200 | ||
201 | if (src_bytes > 4) | |
202 | src_bytes = 4; | |
203 | for (i = 0; i < src_bytes; i++) | |
204 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
205 | return v; | |
206 | } | |
207 | ||
208 | static void | |
209 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
210 | { | |
211 | int i; | |
212 | if (dst_bytes > 4) | |
213 | dst_bytes = 4; | |
214 | for (i = 0; i < dst_bytes; i++) | |
215 | dst[i] = src >> ((3-i) * 8); | |
216 | } | |
217 | ||
fb0f8fbf KP |
218 | /* hrawclock is 1/4 the FSB frequency */ |
219 | static int | |
220 | intel_hrawclk(struct drm_device *dev) | |
221 | { | |
222 | struct drm_i915_private *dev_priv = dev->dev_private; | |
223 | uint32_t clkcfg; | |
224 | ||
9473c8f4 VP |
225 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
226 | if (IS_VALLEYVIEW(dev)) | |
227 | return 200; | |
228 | ||
fb0f8fbf KP |
229 | clkcfg = I915_READ(CLKCFG); |
230 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
231 | case CLKCFG_FSB_400: | |
232 | return 100; | |
233 | case CLKCFG_FSB_533: | |
234 | return 133; | |
235 | case CLKCFG_FSB_667: | |
236 | return 166; | |
237 | case CLKCFG_FSB_800: | |
238 | return 200; | |
239 | case CLKCFG_FSB_1067: | |
240 | return 266; | |
241 | case CLKCFG_FSB_1333: | |
242 | return 333; | |
243 | /* these two are just a guess; one of them might be right */ | |
244 | case CLKCFG_FSB_1600: | |
245 | case CLKCFG_FSB_1600_ALT: | |
246 | return 400; | |
247 | default: | |
248 | return 133; | |
249 | } | |
250 | } | |
251 | ||
ebf33b18 KP |
252 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
253 | { | |
30add22d | 254 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 | 255 | struct drm_i915_private *dev_priv = dev->dev_private; |
453c5420 | 256 | u32 pp_stat_reg; |
ebf33b18 | 257 | |
453c5420 JB |
258 | pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; |
259 | return (I915_READ(pp_stat_reg) & PP_ON) != 0; | |
ebf33b18 KP |
260 | } |
261 | ||
262 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) | |
263 | { | |
30add22d | 264 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 | 265 | struct drm_i915_private *dev_priv = dev->dev_private; |
453c5420 | 266 | u32 pp_ctrl_reg; |
ebf33b18 | 267 | |
453c5420 JB |
268 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; |
269 | return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0; | |
ebf33b18 KP |
270 | } |
271 | ||
9b984dae KP |
272 | static void |
273 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
274 | { | |
30add22d | 275 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9b984dae | 276 | struct drm_i915_private *dev_priv = dev->dev_private; |
453c5420 | 277 | u32 pp_stat_reg, pp_ctrl_reg; |
ebf33b18 | 278 | |
9b984dae KP |
279 | if (!is_edp(intel_dp)) |
280 | return; | |
453c5420 JB |
281 | |
282 | pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; | |
283 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; | |
284 | ||
ebf33b18 | 285 | if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
286 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
287 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
453c5420 JB |
288 | I915_READ(pp_stat_reg), |
289 | I915_READ(pp_ctrl_reg)); | |
9b984dae KP |
290 | } |
291 | } | |
292 | ||
9ee32fea DV |
293 | static uint32_t |
294 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
295 | { | |
296 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
297 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9ed35ab1 | 299 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
300 | uint32_t status; |
301 | bool done; | |
302 | ||
ef04f00d | 303 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 304 | if (has_aux_irq) |
b90f5176 PZ |
305 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
306 | msecs_to_jiffies(10)); | |
9ee32fea DV |
307 | else |
308 | done = wait_for_atomic(C, 10) == 0; | |
309 | if (!done) | |
310 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
311 | has_aux_irq); | |
312 | #undef C | |
313 | ||
314 | return status; | |
315 | } | |
316 | ||
a4fc5ed6 | 317 | static int |
ea5b213a | 318 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
319 | uint8_t *send, int send_bytes, |
320 | uint8_t *recv, int recv_size) | |
321 | { | |
174edf1f PZ |
322 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
323 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
a4fc5ed6 | 324 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ed35ab1 | 325 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
a4fc5ed6 | 326 | uint32_t ch_data = ch_ctl + 4; |
9ee32fea | 327 | int i, ret, recv_bytes; |
a4fc5ed6 | 328 | uint32_t status; |
fb0f8fbf | 329 | uint32_t aux_clock_divider; |
6b4e0a93 | 330 | int try, precharge; |
9ee32fea DV |
331 | bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev); |
332 | ||
333 | /* dp aux is extremely sensitive to irq latency, hence request the | |
334 | * lowest possible wakeup latency and so prevent the cpu from going into | |
335 | * deep sleep states. | |
336 | */ | |
337 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
a4fc5ed6 | 338 | |
9b984dae | 339 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 | 340 | /* The clock divider is based off the hrawclk, |
fb0f8fbf KP |
341 | * and would like to run at 2MHz. So, take the |
342 | * hrawclk value and divide by 2 and use that | |
6176b8f9 JB |
343 | * |
344 | * Note that PCH attached eDP panels should use a 125MHz input | |
345 | * clock divider. | |
a4fc5ed6 | 346 | */ |
1c95822a | 347 | if (is_cpu_edp(intel_dp)) { |
affa9354 | 348 | if (HAS_DDI(dev)) |
b8fc2f6a PZ |
349 | aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1; |
350 | else if (IS_VALLEYVIEW(dev)) | |
9473c8f4 VP |
351 | aux_clock_divider = 100; |
352 | else if (IS_GEN6(dev) || IS_GEN7(dev)) | |
1a2eb460 | 353 | aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ |
e3421a18 ZW |
354 | else |
355 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
2c55c336 JN |
356 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
357 | /* Workaround for non-ULT HSW */ | |
358 | aux_clock_divider = 74; | |
359 | } else if (HAS_PCH_SPLIT(dev)) { | |
6b3ec1c9 | 360 | aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
2c55c336 | 361 | } else { |
5eb08b69 | 362 | aux_clock_divider = intel_hrawclk(dev) / 2; |
2c55c336 | 363 | } |
5eb08b69 | 364 | |
6b4e0a93 DV |
365 | if (IS_GEN6(dev)) |
366 | precharge = 3; | |
367 | else | |
368 | precharge = 5; | |
369 | ||
11bee43e JB |
370 | /* Try to wait for any previous AUX channel activity */ |
371 | for (try = 0; try < 3; try++) { | |
ef04f00d | 372 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
373 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
374 | break; | |
375 | msleep(1); | |
376 | } | |
377 | ||
378 | if (try == 3) { | |
379 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
380 | I915_READ(ch_ctl)); | |
9ee32fea DV |
381 | ret = -EBUSY; |
382 | goto out; | |
4f7f7b7e CW |
383 | } |
384 | ||
fb0f8fbf KP |
385 | /* Must try at least 3 times according to DP spec */ |
386 | for (try = 0; try < 5; try++) { | |
387 | /* Load the send data into the aux channel data registers */ | |
4f7f7b7e CW |
388 | for (i = 0; i < send_bytes; i += 4) |
389 | I915_WRITE(ch_data + i, | |
390 | pack_aux(send + i, send_bytes - i)); | |
0206e353 | 391 | |
fb0f8fbf | 392 | /* Send the command and wait for it to complete */ |
4f7f7b7e CW |
393 | I915_WRITE(ch_ctl, |
394 | DP_AUX_CH_CTL_SEND_BUSY | | |
9ee32fea | 395 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
4f7f7b7e CW |
396 | DP_AUX_CH_CTL_TIME_OUT_400us | |
397 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
398 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
399 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
400 | DP_AUX_CH_CTL_DONE | | |
401 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
402 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
9ee32fea DV |
403 | |
404 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
0206e353 | 405 | |
fb0f8fbf | 406 | /* Clear done status and any errors */ |
4f7f7b7e CW |
407 | I915_WRITE(ch_ctl, |
408 | status | | |
409 | DP_AUX_CH_CTL_DONE | | |
410 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
411 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
d7e96fea AJ |
412 | |
413 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
414 | DP_AUX_CH_CTL_RECEIVE_ERROR)) | |
415 | continue; | |
4f7f7b7e | 416 | if (status & DP_AUX_CH_CTL_DONE) |
a4fc5ed6 KP |
417 | break; |
418 | } | |
419 | ||
a4fc5ed6 | 420 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 421 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
422 | ret = -EBUSY; |
423 | goto out; | |
a4fc5ed6 KP |
424 | } |
425 | ||
426 | /* Check for timeout or receive error. | |
427 | * Timeouts occur when the sink is not connected | |
428 | */ | |
a5b3da54 | 429 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 430 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
431 | ret = -EIO; |
432 | goto out; | |
a5b3da54 | 433 | } |
1ae8c0a5 KP |
434 | |
435 | /* Timeouts occur when the device isn't connected, so they're | |
436 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 437 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 438 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
439 | ret = -ETIMEDOUT; |
440 | goto out; | |
a4fc5ed6 KP |
441 | } |
442 | ||
443 | /* Unload any bytes sent back from the other side */ | |
444 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
445 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
446 | if (recv_bytes > recv_size) |
447 | recv_bytes = recv_size; | |
0206e353 | 448 | |
4f7f7b7e CW |
449 | for (i = 0; i < recv_bytes; i += 4) |
450 | unpack_aux(I915_READ(ch_data + i), | |
451 | recv + i, recv_bytes - i); | |
a4fc5ed6 | 452 | |
9ee32fea DV |
453 | ret = recv_bytes; |
454 | out: | |
455 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
456 | ||
457 | return ret; | |
a4fc5ed6 KP |
458 | } |
459 | ||
460 | /* Write data to the aux channel in native mode */ | |
461 | static int | |
ea5b213a | 462 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
463 | uint16_t address, uint8_t *send, int send_bytes) |
464 | { | |
465 | int ret; | |
466 | uint8_t msg[20]; | |
467 | int msg_bytes; | |
468 | uint8_t ack; | |
469 | ||
9b984dae | 470 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
471 | if (send_bytes > 16) |
472 | return -1; | |
473 | msg[0] = AUX_NATIVE_WRITE << 4; | |
474 | msg[1] = address >> 8; | |
eebc863e | 475 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
476 | msg[3] = send_bytes - 1; |
477 | memcpy(&msg[4], send, send_bytes); | |
478 | msg_bytes = send_bytes + 4; | |
479 | for (;;) { | |
ea5b213a | 480 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
481 | if (ret < 0) |
482 | return ret; | |
483 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
484 | break; | |
485 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
486 | udelay(100); | |
487 | else | |
a5b3da54 | 488 | return -EIO; |
a4fc5ed6 KP |
489 | } |
490 | return send_bytes; | |
491 | } | |
492 | ||
493 | /* Write a single byte to the aux channel in native mode */ | |
494 | static int | |
ea5b213a | 495 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
496 | uint16_t address, uint8_t byte) |
497 | { | |
ea5b213a | 498 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
499 | } |
500 | ||
501 | /* read bytes from a native aux channel */ | |
502 | static int | |
ea5b213a | 503 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
504 | uint16_t address, uint8_t *recv, int recv_bytes) |
505 | { | |
506 | uint8_t msg[4]; | |
507 | int msg_bytes; | |
508 | uint8_t reply[20]; | |
509 | int reply_bytes; | |
510 | uint8_t ack; | |
511 | int ret; | |
512 | ||
9b984dae | 513 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
514 | msg[0] = AUX_NATIVE_READ << 4; |
515 | msg[1] = address >> 8; | |
516 | msg[2] = address & 0xff; | |
517 | msg[3] = recv_bytes - 1; | |
518 | ||
519 | msg_bytes = 4; | |
520 | reply_bytes = recv_bytes + 1; | |
521 | ||
522 | for (;;) { | |
ea5b213a | 523 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 524 | reply, reply_bytes); |
a5b3da54 KP |
525 | if (ret == 0) |
526 | return -EPROTO; | |
527 | if (ret < 0) | |
a4fc5ed6 KP |
528 | return ret; |
529 | ack = reply[0]; | |
530 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
531 | memcpy(recv, reply + 1, ret - 1); | |
532 | return ret - 1; | |
533 | } | |
534 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
535 | udelay(100); | |
536 | else | |
a5b3da54 | 537 | return -EIO; |
a4fc5ed6 KP |
538 | } |
539 | } | |
540 | ||
541 | static int | |
ab2c0672 DA |
542 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
543 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 544 | { |
ab2c0672 | 545 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
546 | struct intel_dp *intel_dp = container_of(adapter, |
547 | struct intel_dp, | |
548 | adapter); | |
ab2c0672 DA |
549 | uint16_t address = algo_data->address; |
550 | uint8_t msg[5]; | |
551 | uint8_t reply[2]; | |
8316f337 | 552 | unsigned retry; |
ab2c0672 DA |
553 | int msg_bytes; |
554 | int reply_bytes; | |
555 | int ret; | |
556 | ||
9b984dae | 557 | intel_dp_check_edp(intel_dp); |
ab2c0672 DA |
558 | /* Set up the command byte */ |
559 | if (mode & MODE_I2C_READ) | |
560 | msg[0] = AUX_I2C_READ << 4; | |
561 | else | |
562 | msg[0] = AUX_I2C_WRITE << 4; | |
563 | ||
564 | if (!(mode & MODE_I2C_STOP)) | |
565 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 566 | |
ab2c0672 DA |
567 | msg[1] = address >> 8; |
568 | msg[2] = address; | |
569 | ||
570 | switch (mode) { | |
571 | case MODE_I2C_WRITE: | |
572 | msg[3] = 0; | |
573 | msg[4] = write_byte; | |
574 | msg_bytes = 5; | |
575 | reply_bytes = 1; | |
576 | break; | |
577 | case MODE_I2C_READ: | |
578 | msg[3] = 0; | |
579 | msg_bytes = 4; | |
580 | reply_bytes = 2; | |
581 | break; | |
582 | default: | |
583 | msg_bytes = 3; | |
584 | reply_bytes = 1; | |
585 | break; | |
586 | } | |
587 | ||
8316f337 DF |
588 | for (retry = 0; retry < 5; retry++) { |
589 | ret = intel_dp_aux_ch(intel_dp, | |
590 | msg, msg_bytes, | |
591 | reply, reply_bytes); | |
ab2c0672 | 592 | if (ret < 0) { |
3ff99164 | 593 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
594 | return ret; |
595 | } | |
8316f337 DF |
596 | |
597 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { | |
598 | case AUX_NATIVE_REPLY_ACK: | |
599 | /* I2C-over-AUX Reply field is only valid | |
600 | * when paired with AUX ACK. | |
601 | */ | |
602 | break; | |
603 | case AUX_NATIVE_REPLY_NACK: | |
604 | DRM_DEBUG_KMS("aux_ch native nack\n"); | |
605 | return -EREMOTEIO; | |
606 | case AUX_NATIVE_REPLY_DEFER: | |
607 | udelay(100); | |
608 | continue; | |
609 | default: | |
610 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", | |
611 | reply[0]); | |
612 | return -EREMOTEIO; | |
613 | } | |
614 | ||
ab2c0672 DA |
615 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
616 | case AUX_I2C_REPLY_ACK: | |
617 | if (mode == MODE_I2C_READ) { | |
618 | *read_byte = reply[1]; | |
619 | } | |
620 | return reply_bytes - 1; | |
621 | case AUX_I2C_REPLY_NACK: | |
8316f337 | 622 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
ab2c0672 DA |
623 | return -EREMOTEIO; |
624 | case AUX_I2C_REPLY_DEFER: | |
8316f337 | 625 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
ab2c0672 DA |
626 | udelay(100); |
627 | break; | |
628 | default: | |
8316f337 | 629 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
ab2c0672 DA |
630 | return -EREMOTEIO; |
631 | } | |
632 | } | |
8316f337 DF |
633 | |
634 | DRM_ERROR("too many retries, giving up\n"); | |
635 | return -EREMOTEIO; | |
a4fc5ed6 KP |
636 | } |
637 | ||
638 | static int | |
ea5b213a | 639 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 640 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 641 | { |
0b5c541b KP |
642 | int ret; |
643 | ||
d54e9d28 | 644 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
645 | intel_dp->algo.running = false; |
646 | intel_dp->algo.address = 0; | |
647 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
648 | ||
0206e353 | 649 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
ea5b213a CW |
650 | intel_dp->adapter.owner = THIS_MODULE; |
651 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
0206e353 | 652 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
ea5b213a CW |
653 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
654 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
655 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
656 | ||
0b5c541b KP |
657 | ironlake_edp_panel_vdd_on(intel_dp); |
658 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); | |
bd943159 | 659 | ironlake_edp_panel_vdd_off(intel_dp, false); |
0b5c541b | 660 | return ret; |
a4fc5ed6 KP |
661 | } |
662 | ||
00c09d70 | 663 | bool |
5bfe2ac0 DV |
664 | intel_dp_compute_config(struct intel_encoder *encoder, |
665 | struct intel_crtc_config *pipe_config) | |
a4fc5ed6 | 666 | { |
5bfe2ac0 | 667 | struct drm_device *dev = encoder->base.dev; |
36008365 | 668 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfe2ac0 DV |
669 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
670 | struct drm_display_mode *mode = &pipe_config->requested_mode; | |
671 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
dd06f90e | 672 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
a4fc5ed6 | 673 | int lane_count, clock; |
397fe157 | 674 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
ea5b213a | 675 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
083f9560 | 676 | int bpp, mode_rate; |
a4fc5ed6 | 677 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
36008365 | 678 | int target_clock, link_avail, link_clock; |
a4fc5ed6 | 679 | |
5bfe2ac0 DV |
680 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp)) |
681 | pipe_config->has_pch_encoder = true; | |
682 | ||
03afc4a2 DV |
683 | pipe_config->has_dp_encoder = true; |
684 | ||
dd06f90e JN |
685 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
686 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
687 | adjusted_mode); | |
53b41837 YN |
688 | intel_pch_panel_fitting(dev, |
689 | intel_connector->panel.fitting_mode, | |
1d8e1c75 | 690 | mode, adjusted_mode); |
0d3a1bee | 691 | } |
36008365 DV |
692 | /* We need to take the panel's fixed mode into account. */ |
693 | target_clock = adjusted_mode->clock; | |
0d3a1bee | 694 | |
cb1793ce | 695 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
696 | return false; |
697 | ||
083f9560 DV |
698 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
699 | "max bw %02x pixel clock %iKHz\n", | |
71244653 | 700 | max_lane_count, bws[max_clock], adjusted_mode->clock); |
083f9560 | 701 | |
36008365 DV |
702 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
703 | * bpc in between. */ | |
03afc4a2 | 704 | bpp = min_t(int, 8*3, pipe_config->pipe_bpp); |
36008365 DV |
705 | for (; bpp >= 6*3; bpp -= 2*3) { |
706 | mode_rate = intel_dp_link_required(target_clock, bpp); | |
707 | ||
708 | for (clock = 0; clock <= max_clock; clock++) { | |
709 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { | |
710 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); | |
711 | link_avail = intel_dp_max_data_rate(link_clock, | |
712 | lane_count); | |
713 | ||
714 | if (mode_rate <= link_avail) { | |
715 | goto found; | |
716 | } | |
717 | } | |
718 | } | |
719 | } | |
c4867936 | 720 | |
36008365 | 721 | return false; |
3685a8f3 | 722 | |
36008365 | 723 | found: |
55bc60db VS |
724 | if (intel_dp->color_range_auto) { |
725 | /* | |
726 | * See: | |
727 | * CEA-861-E - 5.1 Default Encoding Parameters | |
728 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
729 | */ | |
18316c8c | 730 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
55bc60db VS |
731 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
732 | else | |
733 | intel_dp->color_range = 0; | |
734 | } | |
735 | ||
3685a8f3 | 736 | if (intel_dp->color_range) |
50f3b016 | 737 | pipe_config->limited_color_range = true; |
3685a8f3 | 738 | |
36008365 DV |
739 | intel_dp->link_bw = bws[clock]; |
740 | intel_dp->lane_count = lane_count; | |
741 | adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); | |
df92b1e6 | 742 | pipe_config->pixel_target_clock = target_clock; |
fe27d53e | 743 | |
36008365 DV |
744 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
745 | intel_dp->link_bw, intel_dp->lane_count, | |
746 | adjusted_mode->clock, bpp); | |
747 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", | |
748 | mode_rate, link_avail); | |
749 | ||
03afc4a2 DV |
750 | intel_link_compute_m_n(bpp, lane_count, |
751 | target_clock, adjusted_mode->clock, | |
752 | &pipe_config->dp_m_n); | |
a4fc5ed6 | 753 | |
57c21963 DV |
754 | /* |
755 | * XXX: We have a strange regression where using the vbt edp bpp value | |
756 | * for the link bw computation results in black screens, the panel only | |
757 | * works when we do the computation at the usual 24bpp (but still | |
758 | * requires us to use 18bpp). Until that's fully debugged, stay | |
759 | * bug-for-bug compatible with the old code. | |
760 | */ | |
761 | if (is_edp(intel_dp) && dev_priv->edp.bpp) { | |
762 | DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", | |
763 | bpp, dev_priv->edp.bpp); | |
764 | bpp = min_t(int, bpp, dev_priv->edp.bpp); | |
765 | } | |
766 | pipe_config->pipe_bpp = bpp; | |
767 | ||
03afc4a2 | 768 | return true; |
a4fc5ed6 KP |
769 | } |
770 | ||
247d89f6 PZ |
771 | void intel_dp_init_link_config(struct intel_dp *intel_dp) |
772 | { | |
773 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); | |
774 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
775 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
776 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; | |
777 | /* | |
778 | * Check for DPCD version > 1.1 and enhanced framing support | |
779 | */ | |
780 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
781 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { | |
782 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; | |
783 | } | |
784 | } | |
785 | ||
ea9b6006 DV |
786 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
787 | { | |
788 | struct drm_device *dev = crtc->dev; | |
789 | struct drm_i915_private *dev_priv = dev->dev_private; | |
790 | u32 dpa_ctl; | |
791 | ||
792 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); | |
793 | dpa_ctl = I915_READ(DP_A); | |
794 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
795 | ||
796 | if (clock < 200000) { | |
1ce17038 DV |
797 | /* For a long time we've carried around a ILK-DevA w/a for the |
798 | * 160MHz clock. If we're really unlucky, it's still required. | |
799 | */ | |
800 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); | |
ea9b6006 | 801 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
ea9b6006 DV |
802 | } else { |
803 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
804 | } | |
1ce17038 | 805 | |
ea9b6006 DV |
806 | I915_WRITE(DP_A, dpa_ctl); |
807 | ||
808 | POSTING_READ(DP_A); | |
809 | udelay(500); | |
810 | } | |
811 | ||
a4fc5ed6 KP |
812 | static void |
813 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
814 | struct drm_display_mode *adjusted_mode) | |
815 | { | |
e3421a18 | 816 | struct drm_device *dev = encoder->dev; |
417e822d | 817 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 818 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
fa90ecef | 819 | struct drm_crtc *crtc = encoder->crtc; |
a4fc5ed6 KP |
820 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
821 | ||
417e822d | 822 | /* |
1a2eb460 | 823 | * There are four kinds of DP registers: |
417e822d KP |
824 | * |
825 | * IBX PCH | |
1a2eb460 KP |
826 | * SNB CPU |
827 | * IVB CPU | |
417e822d KP |
828 | * CPT PCH |
829 | * | |
830 | * IBX PCH and CPU are the same for almost everything, | |
831 | * except that the CPU DP PLL is configured in this | |
832 | * register | |
833 | * | |
834 | * CPT PCH is quite different, having many bits moved | |
835 | * to the TRANS_DP_CTL register instead. That | |
836 | * configuration happens (oddly) in ironlake_pch_enable | |
837 | */ | |
9c9e7927 | 838 | |
417e822d KP |
839 | /* Preserve the BIOS-computed detected bit. This is |
840 | * supposed to be read-only. | |
841 | */ | |
842 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 843 | |
417e822d | 844 | /* Handle DP bits in common between all three register formats */ |
417e822d | 845 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
a4fc5ed6 | 846 | |
ea5b213a | 847 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 848 | case 1: |
ea5b213a | 849 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
850 | break; |
851 | case 2: | |
ea5b213a | 852 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
853 | break; |
854 | case 4: | |
ea5b213a | 855 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
856 | break; |
857 | } | |
e0dac65e WF |
858 | if (intel_dp->has_audio) { |
859 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", | |
860 | pipe_name(intel_crtc->pipe)); | |
ea5b213a | 861 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
e0dac65e WF |
862 | intel_write_eld(encoder, adjusted_mode); |
863 | } | |
247d89f6 PZ |
864 | |
865 | intel_dp_init_link_config(intel_dp); | |
a4fc5ed6 | 866 | |
417e822d | 867 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 868 | |
19c03924 | 869 | if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
1a2eb460 KP |
870 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
871 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
872 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
873 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
874 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
875 | ||
876 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) | |
877 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
878 | ||
879 | intel_dp->DP |= intel_crtc->pipe << 29; | |
880 | ||
881 | /* don't miss out required setting for eDP */ | |
1a2eb460 KP |
882 | if (adjusted_mode->clock < 200000) |
883 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; | |
884 | else | |
885 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
886 | } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { | |
b2634017 | 887 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) |
3685a8f3 | 888 | intel_dp->DP |= intel_dp->color_range; |
417e822d KP |
889 | |
890 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
891 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
892 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
893 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
894 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
895 | ||
896 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) | |
897 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
898 | ||
899 | if (intel_crtc->pipe == 1) | |
900 | intel_dp->DP |= DP_PIPEB_SELECT; | |
901 | ||
b2634017 | 902 | if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
417e822d | 903 | /* don't miss out required setting for eDP */ |
417e822d KP |
904 | if (adjusted_mode->clock < 200000) |
905 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; | |
906 | else | |
907 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
908 | } | |
909 | } else { | |
910 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
32f9d658 | 911 | } |
ea9b6006 | 912 | |
5d66d5b6 | 913 | if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) |
ea9b6006 | 914 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
a4fc5ed6 KP |
915 | } |
916 | ||
99ea7127 KP |
917 | #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
918 | #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
919 | ||
920 | #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) | |
921 | #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
922 | ||
923 | #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) | |
924 | #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
925 | ||
926 | static void ironlake_wait_panel_status(struct intel_dp *intel_dp, | |
927 | u32 mask, | |
928 | u32 value) | |
bd943159 | 929 | { |
30add22d | 930 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
99ea7127 | 931 | struct drm_i915_private *dev_priv = dev->dev_private; |
453c5420 JB |
932 | u32 pp_stat_reg, pp_ctrl_reg; |
933 | ||
934 | pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; | |
935 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; | |
32ce697c | 936 | |
99ea7127 | 937 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
938 | mask, value, |
939 | I915_READ(pp_stat_reg), | |
940 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 941 | |
453c5420 | 942 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
99ea7127 | 943 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
944 | I915_READ(pp_stat_reg), |
945 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 946 | } |
99ea7127 | 947 | } |
32ce697c | 948 | |
99ea7127 KP |
949 | static void ironlake_wait_panel_on(struct intel_dp *intel_dp) |
950 | { | |
951 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
952 | ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); | |
bd943159 KP |
953 | } |
954 | ||
99ea7127 KP |
955 | static void ironlake_wait_panel_off(struct intel_dp *intel_dp) |
956 | { | |
957 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
958 | ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); | |
959 | } | |
960 | ||
961 | static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) | |
962 | { | |
963 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); | |
964 | ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); | |
965 | } | |
966 | ||
967 | ||
832dd3c1 KP |
968 | /* Read the current pp_control value, unlocking the register if it |
969 | * is locked | |
970 | */ | |
971 | ||
453c5420 | 972 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 973 | { |
453c5420 JB |
974 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
975 | struct drm_i915_private *dev_priv = dev->dev_private; | |
976 | u32 control; | |
977 | u32 pp_ctrl_reg; | |
978 | ||
979 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; | |
980 | control = I915_READ(pp_ctrl_reg); | |
832dd3c1 KP |
981 | |
982 | control &= ~PANEL_UNLOCK_MASK; | |
983 | control |= PANEL_UNLOCK_REGS; | |
984 | return control; | |
bd943159 KP |
985 | } |
986 | ||
82a4d9c0 | 987 | void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 988 | { |
30add22d | 989 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5d613501 JB |
990 | struct drm_i915_private *dev_priv = dev->dev_private; |
991 | u32 pp; | |
453c5420 | 992 | u32 pp_stat_reg, pp_ctrl_reg; |
5d613501 | 993 | |
97af61f5 KP |
994 | if (!is_edp(intel_dp)) |
995 | return; | |
f01eca2e | 996 | DRM_DEBUG_KMS("Turn eDP VDD on\n"); |
5d613501 | 997 | |
bd943159 KP |
998 | WARN(intel_dp->want_panel_vdd, |
999 | "eDP VDD already requested on\n"); | |
1000 | ||
1001 | intel_dp->want_panel_vdd = true; | |
99ea7127 | 1002 | |
bd943159 KP |
1003 | if (ironlake_edp_have_panel_vdd(intel_dp)) { |
1004 | DRM_DEBUG_KMS("eDP VDD already on\n"); | |
1005 | return; | |
1006 | } | |
1007 | ||
99ea7127 KP |
1008 | if (!ironlake_edp_have_panel_power(intel_dp)) |
1009 | ironlake_wait_panel_power_cycle(intel_dp); | |
1010 | ||
453c5420 | 1011 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 1012 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 1013 | |
453c5420 JB |
1014 | pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; |
1015 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; | |
1016 | ||
1017 | I915_WRITE(pp_ctrl_reg, pp); | |
1018 | POSTING_READ(pp_ctrl_reg); | |
1019 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1020 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
1021 | /* |
1022 | * If the panel wasn't on, delay before accessing aux channel | |
1023 | */ | |
1024 | if (!ironlake_edp_have_panel_power(intel_dp)) { | |
bd943159 | 1025 | DRM_DEBUG_KMS("eDP was not running\n"); |
f01eca2e | 1026 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 1027 | } |
5d613501 JB |
1028 | } |
1029 | ||
bd943159 | 1030 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 1031 | { |
30add22d | 1032 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5d613501 JB |
1033 | struct drm_i915_private *dev_priv = dev->dev_private; |
1034 | u32 pp; | |
453c5420 | 1035 | u32 pp_stat_reg, pp_ctrl_reg; |
5d613501 | 1036 | |
a0e99e68 DV |
1037 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
1038 | ||
bd943159 | 1039 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
453c5420 | 1040 | pp = ironlake_get_pp_control(intel_dp); |
bd943159 | 1041 | pp &= ~EDP_FORCE_VDD; |
bd943159 | 1042 | |
453c5420 JB |
1043 | pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; |
1044 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; | |
1045 | ||
1046 | I915_WRITE(pp_ctrl_reg, pp); | |
1047 | POSTING_READ(pp_ctrl_reg); | |
99ea7127 | 1048 | |
453c5420 JB |
1049 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1050 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1051 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
99ea7127 | 1052 | msleep(intel_dp->panel_power_down_delay); |
bd943159 KP |
1053 | } |
1054 | } | |
5d613501 | 1055 | |
bd943159 KP |
1056 | static void ironlake_panel_vdd_work(struct work_struct *__work) |
1057 | { | |
1058 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
1059 | struct intel_dp, panel_vdd_work); | |
30add22d | 1060 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bd943159 | 1061 | |
627f7675 | 1062 | mutex_lock(&dev->mode_config.mutex); |
bd943159 | 1063 | ironlake_panel_vdd_off_sync(intel_dp); |
627f7675 | 1064 | mutex_unlock(&dev->mode_config.mutex); |
bd943159 KP |
1065 | } |
1066 | ||
82a4d9c0 | 1067 | void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 1068 | { |
97af61f5 KP |
1069 | if (!is_edp(intel_dp)) |
1070 | return; | |
5d613501 | 1071 | |
bd943159 KP |
1072 | DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); |
1073 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); | |
f2e8b18a | 1074 | |
bd943159 KP |
1075 | intel_dp->want_panel_vdd = false; |
1076 | ||
1077 | if (sync) { | |
1078 | ironlake_panel_vdd_off_sync(intel_dp); | |
1079 | } else { | |
1080 | /* | |
1081 | * Queue the timer to fire a long | |
1082 | * time from now (relative to the power down delay) | |
1083 | * to keep the panel power up across a sequence of operations | |
1084 | */ | |
1085 | schedule_delayed_work(&intel_dp->panel_vdd_work, | |
1086 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
1087 | } | |
5d613501 JB |
1088 | } |
1089 | ||
82a4d9c0 | 1090 | void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 1091 | { |
30add22d | 1092 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1093 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1094 | u32 pp; |
453c5420 | 1095 | u32 pp_ctrl_reg; |
9934c132 | 1096 | |
97af61f5 | 1097 | if (!is_edp(intel_dp)) |
bd943159 | 1098 | return; |
99ea7127 KP |
1099 | |
1100 | DRM_DEBUG_KMS("Turn eDP power on\n"); | |
1101 | ||
1102 | if (ironlake_edp_have_panel_power(intel_dp)) { | |
1103 | DRM_DEBUG_KMS("eDP power already on\n"); | |
7d639f35 | 1104 | return; |
99ea7127 | 1105 | } |
9934c132 | 1106 | |
99ea7127 | 1107 | ironlake_wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 1108 | |
453c5420 | 1109 | pp = ironlake_get_pp_control(intel_dp); |
05ce1a49 KP |
1110 | if (IS_GEN5(dev)) { |
1111 | /* ILK workaround: disable reset around power sequence */ | |
1112 | pp &= ~PANEL_POWER_RESET; | |
1113 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1114 | POSTING_READ(PCH_PP_CONTROL); | |
1115 | } | |
37c6c9b0 | 1116 | |
1c0ae80a | 1117 | pp |= POWER_TARGET_ON; |
99ea7127 KP |
1118 | if (!IS_GEN5(dev)) |
1119 | pp |= PANEL_POWER_RESET; | |
1120 | ||
453c5420 JB |
1121 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; |
1122 | ||
1123 | I915_WRITE(pp_ctrl_reg, pp); | |
1124 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1125 | |
99ea7127 | 1126 | ironlake_wait_panel_on(intel_dp); |
9934c132 | 1127 | |
05ce1a49 KP |
1128 | if (IS_GEN5(dev)) { |
1129 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
1130 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1131 | POSTING_READ(PCH_PP_CONTROL); | |
1132 | } | |
9934c132 JB |
1133 | } |
1134 | ||
82a4d9c0 | 1135 | void ironlake_edp_panel_off(struct intel_dp *intel_dp) |
9934c132 | 1136 | { |
30add22d | 1137 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1138 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1139 | u32 pp; |
453c5420 | 1140 | u32 pp_ctrl_reg; |
9934c132 | 1141 | |
97af61f5 KP |
1142 | if (!is_edp(intel_dp)) |
1143 | return; | |
37c6c9b0 | 1144 | |
99ea7127 | 1145 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
37c6c9b0 | 1146 | |
6cb49835 | 1147 | WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); |
37c6c9b0 | 1148 | |
453c5420 | 1149 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
1150 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
1151 | * panels get very unhappy and cease to work. */ | |
1152 | pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); | |
453c5420 JB |
1153 | |
1154 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; | |
1155 | ||
1156 | I915_WRITE(pp_ctrl_reg, pp); | |
1157 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1158 | |
35a38556 DV |
1159 | intel_dp->want_panel_vdd = false; |
1160 | ||
99ea7127 | 1161 | ironlake_wait_panel_off(intel_dp); |
9934c132 JB |
1162 | } |
1163 | ||
d6c50ff8 | 1164 | void ironlake_edp_backlight_on(struct intel_dp *intel_dp) |
32f9d658 | 1165 | { |
da63a9f2 PZ |
1166 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1167 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
32f9d658 | 1168 | struct drm_i915_private *dev_priv = dev->dev_private; |
da63a9f2 | 1169 | int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe; |
32f9d658 | 1170 | u32 pp; |
453c5420 | 1171 | u32 pp_ctrl_reg; |
32f9d658 | 1172 | |
f01eca2e KP |
1173 | if (!is_edp(intel_dp)) |
1174 | return; | |
1175 | ||
28c97730 | 1176 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
1177 | /* |
1178 | * If we enable the backlight right away following a panel power | |
1179 | * on, we may see slight flicker as the panel syncs with the eDP | |
1180 | * link. So delay a bit to make sure the image is solid before | |
1181 | * allowing it to appear. | |
1182 | */ | |
f01eca2e | 1183 | msleep(intel_dp->backlight_on_delay); |
453c5420 | 1184 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 1185 | pp |= EDP_BLC_ENABLE; |
453c5420 JB |
1186 | |
1187 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; | |
1188 | ||
1189 | I915_WRITE(pp_ctrl_reg, pp); | |
1190 | POSTING_READ(pp_ctrl_reg); | |
035aa3de DV |
1191 | |
1192 | intel_panel_enable_backlight(dev, pipe); | |
32f9d658 ZW |
1193 | } |
1194 | ||
d6c50ff8 | 1195 | void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
32f9d658 | 1196 | { |
30add22d | 1197 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
32f9d658 ZW |
1198 | struct drm_i915_private *dev_priv = dev->dev_private; |
1199 | u32 pp; | |
453c5420 | 1200 | u32 pp_ctrl_reg; |
32f9d658 | 1201 | |
f01eca2e KP |
1202 | if (!is_edp(intel_dp)) |
1203 | return; | |
1204 | ||
035aa3de DV |
1205 | intel_panel_disable_backlight(dev); |
1206 | ||
28c97730 | 1207 | DRM_DEBUG_KMS("\n"); |
453c5420 | 1208 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 1209 | pp &= ~EDP_BLC_ENABLE; |
453c5420 JB |
1210 | |
1211 | pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; | |
1212 | ||
1213 | I915_WRITE(pp_ctrl_reg, pp); | |
1214 | POSTING_READ(pp_ctrl_reg); | |
f01eca2e | 1215 | msleep(intel_dp->backlight_off_delay); |
32f9d658 | 1216 | } |
a4fc5ed6 | 1217 | |
2bd2ad64 | 1218 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
d240f20f | 1219 | { |
da63a9f2 PZ |
1220 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1221 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
1222 | struct drm_device *dev = crtc->dev; | |
d240f20f JB |
1223 | struct drm_i915_private *dev_priv = dev->dev_private; |
1224 | u32 dpa_ctl; | |
1225 | ||
2bd2ad64 DV |
1226 | assert_pipe_disabled(dev_priv, |
1227 | to_intel_crtc(crtc)->pipe); | |
1228 | ||
d240f20f JB |
1229 | DRM_DEBUG_KMS("\n"); |
1230 | dpa_ctl = I915_READ(DP_A); | |
0767935e DV |
1231 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
1232 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); | |
1233 | ||
1234 | /* We don't adjust intel_dp->DP while tearing down the link, to | |
1235 | * facilitate link retraining (e.g. after hotplug). Hence clear all | |
1236 | * enable bits here to ensure that we don't enable too much. */ | |
1237 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); | |
1238 | intel_dp->DP |= DP_PLL_ENABLE; | |
1239 | I915_WRITE(DP_A, intel_dp->DP); | |
298b0b39 JB |
1240 | POSTING_READ(DP_A); |
1241 | udelay(200); | |
d240f20f JB |
1242 | } |
1243 | ||
2bd2ad64 | 1244 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 1245 | { |
da63a9f2 PZ |
1246 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1247 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
1248 | struct drm_device *dev = crtc->dev; | |
d240f20f JB |
1249 | struct drm_i915_private *dev_priv = dev->dev_private; |
1250 | u32 dpa_ctl; | |
1251 | ||
2bd2ad64 DV |
1252 | assert_pipe_disabled(dev_priv, |
1253 | to_intel_crtc(crtc)->pipe); | |
1254 | ||
d240f20f | 1255 | dpa_ctl = I915_READ(DP_A); |
0767935e DV |
1256 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
1257 | "dp pll off, should be on\n"); | |
1258 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); | |
1259 | ||
1260 | /* We can't rely on the value tracked for the DP register in | |
1261 | * intel_dp->DP because link_down must not change that (otherwise link | |
1262 | * re-training will fail. */ | |
298b0b39 | 1263 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 1264 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 1265 | POSTING_READ(DP_A); |
d240f20f JB |
1266 | udelay(200); |
1267 | } | |
1268 | ||
c7ad3810 | 1269 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 1270 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
1271 | { |
1272 | int ret, i; | |
1273 | ||
1274 | /* Should have a valid DPCD by this point */ | |
1275 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
1276 | return; | |
1277 | ||
1278 | if (mode != DRM_MODE_DPMS_ON) { | |
1279 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, | |
1280 | DP_SET_POWER_D3); | |
1281 | if (ret != 1) | |
1282 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
1283 | } else { | |
1284 | /* | |
1285 | * When turning on, we need to retry for 1ms to give the sink | |
1286 | * time to wake up. | |
1287 | */ | |
1288 | for (i = 0; i < 3; i++) { | |
1289 | ret = intel_dp_aux_native_write_1(intel_dp, | |
1290 | DP_SET_POWER, | |
1291 | DP_SET_POWER_D0); | |
1292 | if (ret == 1) | |
1293 | break; | |
1294 | msleep(1); | |
1295 | } | |
1296 | } | |
1297 | } | |
1298 | ||
19d8fe15 DV |
1299 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
1300 | enum pipe *pipe) | |
d240f20f | 1301 | { |
19d8fe15 DV |
1302 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1303 | struct drm_device *dev = encoder->base.dev; | |
1304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1305 | u32 tmp = I915_READ(intel_dp->output_reg); | |
1306 | ||
1307 | if (!(tmp & DP_PORT_EN)) | |
1308 | return false; | |
1309 | ||
5d66d5b6 | 1310 | if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
19d8fe15 DV |
1311 | *pipe = PORT_TO_PIPE_CPT(tmp); |
1312 | } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { | |
1313 | *pipe = PORT_TO_PIPE(tmp); | |
1314 | } else { | |
1315 | u32 trans_sel; | |
1316 | u32 trans_dp; | |
1317 | int i; | |
1318 | ||
1319 | switch (intel_dp->output_reg) { | |
1320 | case PCH_DP_B: | |
1321 | trans_sel = TRANS_DP_PORT_SEL_B; | |
1322 | break; | |
1323 | case PCH_DP_C: | |
1324 | trans_sel = TRANS_DP_PORT_SEL_C; | |
1325 | break; | |
1326 | case PCH_DP_D: | |
1327 | trans_sel = TRANS_DP_PORT_SEL_D; | |
1328 | break; | |
1329 | default: | |
1330 | return true; | |
1331 | } | |
1332 | ||
1333 | for_each_pipe(i) { | |
1334 | trans_dp = I915_READ(TRANS_DP_CTL(i)); | |
1335 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { | |
1336 | *pipe = i; | |
1337 | return true; | |
1338 | } | |
1339 | } | |
19d8fe15 | 1340 | |
4a0833ec DV |
1341 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
1342 | intel_dp->output_reg); | |
1343 | } | |
d240f20f | 1344 | |
2af8898b | 1345 | return true; |
19d8fe15 | 1346 | } |
d240f20f | 1347 | |
e8cb4558 | 1348 | static void intel_disable_dp(struct intel_encoder *encoder) |
d240f20f | 1349 | { |
e8cb4558 | 1350 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
6cb49835 DV |
1351 | |
1352 | /* Make sure the panel is off before trying to change the mode. But also | |
1353 | * ensure that we have vdd while we switch off the panel. */ | |
1354 | ironlake_edp_panel_vdd_on(intel_dp); | |
21264c63 | 1355 | ironlake_edp_backlight_off(intel_dp); |
c7ad3810 | 1356 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
35a38556 | 1357 | ironlake_edp_panel_off(intel_dp); |
3739850b DV |
1358 | |
1359 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ | |
1360 | if (!is_cpu_edp(intel_dp)) | |
1361 | intel_dp_link_down(intel_dp); | |
d240f20f JB |
1362 | } |
1363 | ||
2bd2ad64 | 1364 | static void intel_post_disable_dp(struct intel_encoder *encoder) |
d240f20f | 1365 | { |
2bd2ad64 | 1366 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
b2634017 | 1367 | struct drm_device *dev = encoder->base.dev; |
2bd2ad64 | 1368 | |
3739850b DV |
1369 | if (is_cpu_edp(intel_dp)) { |
1370 | intel_dp_link_down(intel_dp); | |
b2634017 JB |
1371 | if (!IS_VALLEYVIEW(dev)) |
1372 | ironlake_edp_pll_off(intel_dp); | |
3739850b | 1373 | } |
2bd2ad64 DV |
1374 | } |
1375 | ||
e8cb4558 | 1376 | static void intel_enable_dp(struct intel_encoder *encoder) |
d240f20f | 1377 | { |
e8cb4558 DV |
1378 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1379 | struct drm_device *dev = encoder->base.dev; | |
1380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1381 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); | |
5d613501 | 1382 | |
0c33d8d7 DV |
1383 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
1384 | return; | |
5d613501 | 1385 | |
97af61f5 | 1386 | ironlake_edp_panel_vdd_on(intel_dp); |
f01eca2e | 1387 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 1388 | intel_dp_start_link_train(intel_dp); |
97af61f5 | 1389 | ironlake_edp_panel_on(intel_dp); |
bd943159 | 1390 | ironlake_edp_panel_vdd_off(intel_dp, true); |
33a34e4e | 1391 | intel_dp_complete_link_train(intel_dp); |
f01eca2e | 1392 | ironlake_edp_backlight_on(intel_dp); |
89b667f8 JB |
1393 | |
1394 | if (IS_VALLEYVIEW(dev)) { | |
1395 | struct intel_digital_port *dport = | |
1396 | enc_to_dig_port(&encoder->base); | |
1397 | int channel = vlv_dport_to_channel(dport); | |
1398 | ||
1399 | vlv_wait_port_ready(dev_priv, channel); | |
1400 | } | |
d240f20f JB |
1401 | } |
1402 | ||
2bd2ad64 | 1403 | static void intel_pre_enable_dp(struct intel_encoder *encoder) |
a4fc5ed6 | 1404 | { |
2bd2ad64 | 1405 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
b2634017 | 1406 | struct drm_device *dev = encoder->base.dev; |
89b667f8 | 1407 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 | 1408 | |
b2634017 | 1409 | if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) |
2bd2ad64 | 1410 | ironlake_edp_pll_on(intel_dp); |
89b667f8 JB |
1411 | |
1412 | if (IS_VALLEYVIEW(dev)) { | |
1413 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1414 | struct intel_crtc *intel_crtc = | |
1415 | to_intel_crtc(encoder->base.crtc); | |
1416 | int port = vlv_dport_to_channel(dport); | |
1417 | int pipe = intel_crtc->pipe; | |
1418 | u32 val; | |
1419 | ||
1420 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); | |
1421 | ||
1422 | val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port)); | |
1423 | val = 0; | |
1424 | if (pipe) | |
1425 | val |= (1<<21); | |
1426 | else | |
1427 | val &= ~(1<<21); | |
1428 | val |= 0x001000c4; | |
1429 | intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val); | |
1430 | ||
1431 | intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), | |
1432 | 0x00760018); | |
1433 | intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), | |
1434 | 0x00400888); | |
1435 | } | |
1436 | } | |
1437 | ||
1438 | static void intel_dp_pre_pll_enable(struct intel_encoder *encoder) | |
1439 | { | |
1440 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1441 | struct drm_device *dev = encoder->base.dev; | |
1442 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1443 | int port = vlv_dport_to_channel(dport); | |
1444 | ||
1445 | if (!IS_VALLEYVIEW(dev)) | |
1446 | return; | |
1447 | ||
1448 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); | |
1449 | ||
1450 | /* Program Tx lane resets to default */ | |
1451 | intel_dpio_write(dev_priv, DPIO_PCS_TX(port), | |
1452 | DPIO_PCS_TX_LANE2_RESET | | |
1453 | DPIO_PCS_TX_LANE1_RESET); | |
1454 | intel_dpio_write(dev_priv, DPIO_PCS_CLK(port), | |
1455 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | | |
1456 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1457 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1458 | DPIO_PCS_CLK_SOFT_RESET); | |
1459 | ||
1460 | /* Fix up inter-pair skew failure */ | |
1461 | intel_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00); | |
1462 | intel_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500); | |
1463 | intel_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000); | |
a4fc5ed6 KP |
1464 | } |
1465 | ||
1466 | /* | |
df0c237d JB |
1467 | * Native read with retry for link status and receiver capability reads for |
1468 | * cases where the sink may still be asleep. | |
a4fc5ed6 KP |
1469 | */ |
1470 | static bool | |
df0c237d JB |
1471 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
1472 | uint8_t *recv, int recv_bytes) | |
a4fc5ed6 | 1473 | { |
61da5fab JB |
1474 | int ret, i; |
1475 | ||
df0c237d JB |
1476 | /* |
1477 | * Sinks are *supposed* to come up within 1ms from an off state, | |
1478 | * but we're also supposed to retry 3 times per the spec. | |
1479 | */ | |
61da5fab | 1480 | for (i = 0; i < 3; i++) { |
df0c237d JB |
1481 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
1482 | recv_bytes); | |
1483 | if (ret == recv_bytes) | |
61da5fab JB |
1484 | return true; |
1485 | msleep(1); | |
1486 | } | |
a4fc5ed6 | 1487 | |
61da5fab | 1488 | return false; |
a4fc5ed6 KP |
1489 | } |
1490 | ||
1491 | /* | |
1492 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
1493 | * link status information | |
1494 | */ | |
1495 | static bool | |
93f62dad | 1496 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 1497 | { |
df0c237d JB |
1498 | return intel_dp_aux_native_read_retry(intel_dp, |
1499 | DP_LANE0_1_STATUS, | |
93f62dad | 1500 | link_status, |
df0c237d | 1501 | DP_LINK_STATUS_SIZE); |
a4fc5ed6 KP |
1502 | } |
1503 | ||
a4fc5ed6 KP |
1504 | #if 0 |
1505 | static char *voltage_names[] = { | |
1506 | "0.4V", "0.6V", "0.8V", "1.2V" | |
1507 | }; | |
1508 | static char *pre_emph_names[] = { | |
1509 | "0dB", "3.5dB", "6dB", "9.5dB" | |
1510 | }; | |
1511 | static char *link_train_names[] = { | |
1512 | "pattern 1", "pattern 2", "idle", "off" | |
1513 | }; | |
1514 | #endif | |
1515 | ||
1516 | /* | |
1517 | * These are source-specific values; current Intel hardware supports | |
1518 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1519 | */ | |
a4fc5ed6 KP |
1520 | |
1521 | static uint8_t | |
1a2eb460 | 1522 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 1523 | { |
30add22d | 1524 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1a2eb460 | 1525 | |
e2fa6fba P |
1526 | if (IS_VALLEYVIEW(dev)) |
1527 | return DP_TRAIN_VOLTAGE_SWING_1200; | |
1528 | else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) | |
1a2eb460 KP |
1529 | return DP_TRAIN_VOLTAGE_SWING_800; |
1530 | else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) | |
1531 | return DP_TRAIN_VOLTAGE_SWING_1200; | |
1532 | else | |
1533 | return DP_TRAIN_VOLTAGE_SWING_800; | |
1534 | } | |
1535 | ||
1536 | static uint8_t | |
1537 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) | |
1538 | { | |
30add22d | 1539 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1a2eb460 | 1540 | |
22b8bf17 | 1541 | if (HAS_DDI(dev)) { |
d6c0d722 PZ |
1542 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1543 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1544 | return DP_TRAIN_PRE_EMPHASIS_9_5; | |
1545 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1546 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1547 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1548 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1549 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1550 | default: | |
1551 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1552 | } | |
e2fa6fba P |
1553 | } else if (IS_VALLEYVIEW(dev)) { |
1554 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1555 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1556 | return DP_TRAIN_PRE_EMPHASIS_9_5; | |
1557 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1558 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1559 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1560 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1561 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1562 | default: | |
1563 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1564 | } | |
1565 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { | |
1a2eb460 KP |
1566 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1567 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1568 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1569 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1570 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1571 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1572 | default: | |
1573 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1574 | } | |
1575 | } else { | |
1576 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1577 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1578 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1579 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1580 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1581 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1582 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1583 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1584 | default: | |
1585 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1586 | } | |
a4fc5ed6 KP |
1587 | } |
1588 | } | |
1589 | ||
e2fa6fba P |
1590 | static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) |
1591 | { | |
1592 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1594 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
1595 | unsigned long demph_reg_value, preemph_reg_value, | |
1596 | uniqtranscale_reg_value; | |
1597 | uint8_t train_set = intel_dp->train_set[0]; | |
cece5d58 | 1598 | int port = vlv_dport_to_channel(dport); |
e2fa6fba | 1599 | |
89b667f8 JB |
1600 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
1601 | ||
e2fa6fba P |
1602 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
1603 | case DP_TRAIN_PRE_EMPHASIS_0: | |
1604 | preemph_reg_value = 0x0004000; | |
1605 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1606 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1607 | demph_reg_value = 0x2B405555; | |
1608 | uniqtranscale_reg_value = 0x552AB83A; | |
1609 | break; | |
1610 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1611 | demph_reg_value = 0x2B404040; | |
1612 | uniqtranscale_reg_value = 0x5548B83A; | |
1613 | break; | |
1614 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1615 | demph_reg_value = 0x2B245555; | |
1616 | uniqtranscale_reg_value = 0x5560B83A; | |
1617 | break; | |
1618 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1619 | demph_reg_value = 0x2B405555; | |
1620 | uniqtranscale_reg_value = 0x5598DA3A; | |
1621 | break; | |
1622 | default: | |
1623 | return 0; | |
1624 | } | |
1625 | break; | |
1626 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1627 | preemph_reg_value = 0x0002000; | |
1628 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1629 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1630 | demph_reg_value = 0x2B404040; | |
1631 | uniqtranscale_reg_value = 0x5552B83A; | |
1632 | break; | |
1633 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1634 | demph_reg_value = 0x2B404848; | |
1635 | uniqtranscale_reg_value = 0x5580B83A; | |
1636 | break; | |
1637 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1638 | demph_reg_value = 0x2B404040; | |
1639 | uniqtranscale_reg_value = 0x55ADDA3A; | |
1640 | break; | |
1641 | default: | |
1642 | return 0; | |
1643 | } | |
1644 | break; | |
1645 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1646 | preemph_reg_value = 0x0000000; | |
1647 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1648 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1649 | demph_reg_value = 0x2B305555; | |
1650 | uniqtranscale_reg_value = 0x5570B83A; | |
1651 | break; | |
1652 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1653 | demph_reg_value = 0x2B2B4040; | |
1654 | uniqtranscale_reg_value = 0x55ADDA3A; | |
1655 | break; | |
1656 | default: | |
1657 | return 0; | |
1658 | } | |
1659 | break; | |
1660 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1661 | preemph_reg_value = 0x0006000; | |
1662 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1663 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1664 | demph_reg_value = 0x1B405555; | |
1665 | uniqtranscale_reg_value = 0x55ADDA3A; | |
1666 | break; | |
1667 | default: | |
1668 | return 0; | |
1669 | } | |
1670 | break; | |
1671 | default: | |
1672 | return 0; | |
1673 | } | |
1674 | ||
e2fa6fba P |
1675 | intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000); |
1676 | intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value); | |
1677 | intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port), | |
1678 | uniqtranscale_reg_value); | |
1679 | intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040); | |
1680 | intel_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000); | |
1681 | intel_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value); | |
1682 | intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000); | |
e2fa6fba P |
1683 | |
1684 | return 0; | |
1685 | } | |
1686 | ||
a4fc5ed6 | 1687 | static void |
93f62dad | 1688 | intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 KP |
1689 | { |
1690 | uint8_t v = 0; | |
1691 | uint8_t p = 0; | |
1692 | int lane; | |
1a2eb460 KP |
1693 | uint8_t voltage_max; |
1694 | uint8_t preemph_max; | |
a4fc5ed6 | 1695 | |
33a34e4e | 1696 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
0f037bde DV |
1697 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
1698 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); | |
a4fc5ed6 KP |
1699 | |
1700 | if (this_v > v) | |
1701 | v = this_v; | |
1702 | if (this_p > p) | |
1703 | p = this_p; | |
1704 | } | |
1705 | ||
1a2eb460 | 1706 | voltage_max = intel_dp_voltage_max(intel_dp); |
417e822d KP |
1707 | if (v >= voltage_max) |
1708 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; | |
a4fc5ed6 | 1709 | |
1a2eb460 KP |
1710 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
1711 | if (p >= preemph_max) | |
1712 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
a4fc5ed6 KP |
1713 | |
1714 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 1715 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
1716 | } |
1717 | ||
1718 | static uint32_t | |
f0a3424e | 1719 | intel_gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 1720 | { |
3cf2efb1 | 1721 | uint32_t signal_levels = 0; |
a4fc5ed6 | 1722 | |
3cf2efb1 | 1723 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
1724 | case DP_TRAIN_VOLTAGE_SWING_400: |
1725 | default: | |
1726 | signal_levels |= DP_VOLTAGE_0_4; | |
1727 | break; | |
1728 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1729 | signal_levels |= DP_VOLTAGE_0_6; | |
1730 | break; | |
1731 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1732 | signal_levels |= DP_VOLTAGE_0_8; | |
1733 | break; | |
1734 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1735 | signal_levels |= DP_VOLTAGE_1_2; | |
1736 | break; | |
1737 | } | |
3cf2efb1 | 1738 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
1739 | case DP_TRAIN_PRE_EMPHASIS_0: |
1740 | default: | |
1741 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1742 | break; | |
1743 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1744 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1745 | break; | |
1746 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1747 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1748 | break; | |
1749 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1750 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1751 | break; | |
1752 | } | |
1753 | return signal_levels; | |
1754 | } | |
1755 | ||
e3421a18 ZW |
1756 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1757 | static uint32_t | |
1758 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1759 | { | |
3c5a62b5 YL |
1760 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1761 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1762 | switch (signal_levels) { | |
e3421a18 | 1763 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1764 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
1765 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
1766 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1767 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 1768 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
1769 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
1770 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 1771 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
1772 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
1773 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 1774 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1775 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
1776 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 1777 | default: |
3c5a62b5 YL |
1778 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
1779 | "0x%x\n", signal_levels); | |
1780 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
1781 | } |
1782 | } | |
1783 | ||
1a2eb460 KP |
1784 | /* Gen7's DP voltage swing and pre-emphasis control */ |
1785 | static uint32_t | |
1786 | intel_gen7_edp_signal_levels(uint8_t train_set) | |
1787 | { | |
1788 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
1789 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1790 | switch (signal_levels) { | |
1791 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
1792 | return EDP_LINK_TRAIN_400MV_0DB_IVB; | |
1793 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1794 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; | |
1795 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
1796 | return EDP_LINK_TRAIN_400MV_6DB_IVB; | |
1797 | ||
1798 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: | |
1799 | return EDP_LINK_TRAIN_600MV_0DB_IVB; | |
1800 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1801 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; | |
1802 | ||
1803 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | |
1804 | return EDP_LINK_TRAIN_800MV_0DB_IVB; | |
1805 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1806 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; | |
1807 | ||
1808 | default: | |
1809 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
1810 | "0x%x\n", signal_levels); | |
1811 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
1812 | } | |
1813 | } | |
1814 | ||
d6c0d722 PZ |
1815 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
1816 | static uint32_t | |
f0a3424e | 1817 | intel_hsw_signal_levels(uint8_t train_set) |
a4fc5ed6 | 1818 | { |
d6c0d722 PZ |
1819 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1820 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1821 | switch (signal_levels) { | |
1822 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
1823 | return DDI_BUF_EMP_400MV_0DB_HSW; | |
1824 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1825 | return DDI_BUF_EMP_400MV_3_5DB_HSW; | |
1826 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
1827 | return DDI_BUF_EMP_400MV_6DB_HSW; | |
1828 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: | |
1829 | return DDI_BUF_EMP_400MV_9_5DB_HSW; | |
a4fc5ed6 | 1830 | |
d6c0d722 PZ |
1831 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
1832 | return DDI_BUF_EMP_600MV_0DB_HSW; | |
1833 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1834 | return DDI_BUF_EMP_600MV_3_5DB_HSW; | |
1835 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: | |
1836 | return DDI_BUF_EMP_600MV_6DB_HSW; | |
a4fc5ed6 | 1837 | |
d6c0d722 PZ |
1838 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
1839 | return DDI_BUF_EMP_800MV_0DB_HSW; | |
1840 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1841 | return DDI_BUF_EMP_800MV_3_5DB_HSW; | |
1842 | default: | |
1843 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
1844 | "0x%x\n", signal_levels); | |
1845 | return DDI_BUF_EMP_400MV_0DB_HSW; | |
a4fc5ed6 | 1846 | } |
a4fc5ed6 KP |
1847 | } |
1848 | ||
f0a3424e PZ |
1849 | /* Properly updates "DP" with the correct signal levels. */ |
1850 | static void | |
1851 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) | |
1852 | { | |
1853 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
1854 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
1855 | uint32_t signal_levels, mask; | |
1856 | uint8_t train_set = intel_dp->train_set[0]; | |
1857 | ||
22b8bf17 | 1858 | if (HAS_DDI(dev)) { |
f0a3424e PZ |
1859 | signal_levels = intel_hsw_signal_levels(train_set); |
1860 | mask = DDI_BUF_EMP_MASK; | |
e2fa6fba P |
1861 | } else if (IS_VALLEYVIEW(dev)) { |
1862 | signal_levels = intel_vlv_signal_levels(intel_dp); | |
1863 | mask = 0; | |
1864 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) { | |
f0a3424e PZ |
1865 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
1866 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; | |
1867 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { | |
1868 | signal_levels = intel_gen6_edp_signal_levels(train_set); | |
1869 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; | |
1870 | } else { | |
1871 | signal_levels = intel_gen4_signal_levels(train_set); | |
1872 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; | |
1873 | } | |
1874 | ||
1875 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
1876 | ||
1877 | *DP = (*DP & ~mask) | signal_levels; | |
1878 | } | |
1879 | ||
a4fc5ed6 | 1880 | static bool |
ea5b213a | 1881 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 | 1882 | uint32_t dp_reg_value, |
58e10eb9 | 1883 | uint8_t dp_train_pat) |
a4fc5ed6 | 1884 | { |
174edf1f PZ |
1885 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1886 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
a4fc5ed6 | 1887 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1888 | enum port port = intel_dig_port->port; |
a4fc5ed6 | 1889 | int ret; |
d6c0d722 | 1890 | uint32_t temp; |
a4fc5ed6 | 1891 | |
22b8bf17 | 1892 | if (HAS_DDI(dev)) { |
174edf1f | 1893 | temp = I915_READ(DP_TP_CTL(port)); |
d6c0d722 PZ |
1894 | |
1895 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
1896 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
1897 | else | |
1898 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
1899 | ||
1900 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
1901 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
1902 | case DP_TRAINING_PATTERN_DISABLE: | |
d6c0d722 | 1903 | |
10aa17c8 PZ |
1904 | if (port != PORT_A) { |
1905 | temp |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
1906 | I915_WRITE(DP_TP_CTL(port), temp); | |
1907 | ||
1908 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & | |
1909 | DP_TP_STATUS_IDLE_DONE), 1)) | |
1910 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); | |
1911 | ||
1912 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
1913 | } | |
d6c0d722 | 1914 | |
d6c0d722 PZ |
1915 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
1916 | ||
1917 | break; | |
1918 | case DP_TRAINING_PATTERN_1: | |
1919 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1920 | break; | |
1921 | case DP_TRAINING_PATTERN_2: | |
1922 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
1923 | break; | |
1924 | case DP_TRAINING_PATTERN_3: | |
1925 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
1926 | break; | |
1927 | } | |
174edf1f | 1928 | I915_WRITE(DP_TP_CTL(port), temp); |
d6c0d722 PZ |
1929 | |
1930 | } else if (HAS_PCH_CPT(dev) && | |
1931 | (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { | |
47ea7542 PZ |
1932 | dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT; |
1933 | ||
1934 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
1935 | case DP_TRAINING_PATTERN_DISABLE: | |
1936 | dp_reg_value |= DP_LINK_TRAIN_OFF_CPT; | |
1937 | break; | |
1938 | case DP_TRAINING_PATTERN_1: | |
1939 | dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT; | |
1940 | break; | |
1941 | case DP_TRAINING_PATTERN_2: | |
1942 | dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT; | |
1943 | break; | |
1944 | case DP_TRAINING_PATTERN_3: | |
1945 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
1946 | dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT; | |
1947 | break; | |
1948 | } | |
1949 | ||
1950 | } else { | |
1951 | dp_reg_value &= ~DP_LINK_TRAIN_MASK; | |
1952 | ||
1953 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
1954 | case DP_TRAINING_PATTERN_DISABLE: | |
1955 | dp_reg_value |= DP_LINK_TRAIN_OFF; | |
1956 | break; | |
1957 | case DP_TRAINING_PATTERN_1: | |
1958 | dp_reg_value |= DP_LINK_TRAIN_PAT_1; | |
1959 | break; | |
1960 | case DP_TRAINING_PATTERN_2: | |
1961 | dp_reg_value |= DP_LINK_TRAIN_PAT_2; | |
1962 | break; | |
1963 | case DP_TRAINING_PATTERN_3: | |
1964 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
1965 | dp_reg_value |= DP_LINK_TRAIN_PAT_2; | |
1966 | break; | |
1967 | } | |
1968 | } | |
1969 | ||
ea5b213a CW |
1970 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1971 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1972 | |
ea5b213a | 1973 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1974 | DP_TRAINING_PATTERN_SET, |
1975 | dp_train_pat); | |
1976 | ||
47ea7542 PZ |
1977 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) != |
1978 | DP_TRAINING_PATTERN_DISABLE) { | |
1979 | ret = intel_dp_aux_native_write(intel_dp, | |
1980 | DP_TRAINING_LANE0_SET, | |
1981 | intel_dp->train_set, | |
1982 | intel_dp->lane_count); | |
1983 | if (ret != intel_dp->lane_count) | |
1984 | return false; | |
1985 | } | |
a4fc5ed6 KP |
1986 | |
1987 | return true; | |
1988 | } | |
1989 | ||
33a34e4e | 1990 | /* Enable corresponding port and start training pattern 1 */ |
c19b0669 | 1991 | void |
33a34e4e | 1992 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1993 | { |
da63a9f2 | 1994 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
c19b0669 | 1995 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 KP |
1996 | int i; |
1997 | uint8_t voltage; | |
1998 | bool clock_recovery = false; | |
cdb0e95b | 1999 | int voltage_tries, loop_tries; |
ea5b213a | 2000 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 2001 | |
affa9354 | 2002 | if (HAS_DDI(dev)) |
c19b0669 PZ |
2003 | intel_ddi_prepare_link_retrain(encoder); |
2004 | ||
3cf2efb1 CW |
2005 | /* Write the link configuration data */ |
2006 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, | |
2007 | intel_dp->link_configuration, | |
2008 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
2009 | |
2010 | DP |= DP_PORT_EN; | |
1a2eb460 | 2011 | |
33a34e4e | 2012 | memset(intel_dp->train_set, 0, 4); |
a4fc5ed6 | 2013 | voltage = 0xff; |
cdb0e95b KP |
2014 | voltage_tries = 0; |
2015 | loop_tries = 0; | |
a4fc5ed6 KP |
2016 | clock_recovery = false; |
2017 | for (;;) { | |
33a34e4e | 2018 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
93f62dad | 2019 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
f0a3424e PZ |
2020 | |
2021 | intel_dp_set_signal_levels(intel_dp, &DP); | |
a4fc5ed6 | 2022 | |
a7c9655f | 2023 | /* Set training pattern 1 */ |
47ea7542 | 2024 | if (!intel_dp_set_link_train(intel_dp, DP, |
81055854 AJ |
2025 | DP_TRAINING_PATTERN_1 | |
2026 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 | 2027 | break; |
a4fc5ed6 | 2028 | |
a7c9655f | 2029 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
93f62dad KP |
2030 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2031 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 2032 | break; |
93f62dad | 2033 | } |
a4fc5ed6 | 2034 | |
01916270 | 2035 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
93f62dad | 2036 | DRM_DEBUG_KMS("clock recovery OK\n"); |
3cf2efb1 CW |
2037 | clock_recovery = true; |
2038 | break; | |
2039 | } | |
2040 | ||
2041 | /* Check to see if we've tried the max voltage */ | |
2042 | for (i = 0; i < intel_dp->lane_count; i++) | |
2043 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 2044 | break; |
3b4f819d | 2045 | if (i == intel_dp->lane_count) { |
b06fbda3 DV |
2046 | ++loop_tries; |
2047 | if (loop_tries == 5) { | |
cdb0e95b KP |
2048 | DRM_DEBUG_KMS("too many full retries, give up\n"); |
2049 | break; | |
2050 | } | |
2051 | memset(intel_dp->train_set, 0, 4); | |
2052 | voltage_tries = 0; | |
2053 | continue; | |
2054 | } | |
a4fc5ed6 | 2055 | |
3cf2efb1 | 2056 | /* Check to see if we've tried the same voltage 5 times */ |
b06fbda3 | 2057 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
24773670 | 2058 | ++voltage_tries; |
b06fbda3 DV |
2059 | if (voltage_tries == 5) { |
2060 | DRM_DEBUG_KMS("too many voltage retries, give up\n"); | |
2061 | break; | |
2062 | } | |
2063 | } else | |
2064 | voltage_tries = 0; | |
2065 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 2066 | |
3cf2efb1 | 2067 | /* Compute new intel_dp->train_set as requested by target */ |
93f62dad | 2068 | intel_get_adjust_train(intel_dp, link_status); |
a4fc5ed6 KP |
2069 | } |
2070 | ||
33a34e4e JB |
2071 | intel_dp->DP = DP; |
2072 | } | |
2073 | ||
c19b0669 | 2074 | void |
33a34e4e JB |
2075 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
2076 | { | |
33a34e4e | 2077 | bool channel_eq = false; |
37f80975 | 2078 | int tries, cr_tries; |
33a34e4e JB |
2079 | uint32_t DP = intel_dp->DP; |
2080 | ||
a4fc5ed6 KP |
2081 | /* channel equalization */ |
2082 | tries = 0; | |
37f80975 | 2083 | cr_tries = 0; |
a4fc5ed6 KP |
2084 | channel_eq = false; |
2085 | for (;;) { | |
93f62dad | 2086 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
e3421a18 | 2087 | |
37f80975 JB |
2088 | if (cr_tries > 5) { |
2089 | DRM_ERROR("failed to train DP, aborting\n"); | |
2090 | intel_dp_link_down(intel_dp); | |
2091 | break; | |
2092 | } | |
2093 | ||
f0a3424e | 2094 | intel_dp_set_signal_levels(intel_dp, &DP); |
e3421a18 | 2095 | |
a4fc5ed6 | 2096 | /* channel eq pattern */ |
47ea7542 | 2097 | if (!intel_dp_set_link_train(intel_dp, DP, |
81055854 AJ |
2098 | DP_TRAINING_PATTERN_2 | |
2099 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 KP |
2100 | break; |
2101 | ||
a7c9655f | 2102 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
93f62dad | 2103 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
a4fc5ed6 | 2104 | break; |
a4fc5ed6 | 2105 | |
37f80975 | 2106 | /* Make sure clock is still ok */ |
01916270 | 2107 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
37f80975 JB |
2108 | intel_dp_start_link_train(intel_dp); |
2109 | cr_tries++; | |
2110 | continue; | |
2111 | } | |
2112 | ||
1ffdff13 | 2113 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
3cf2efb1 CW |
2114 | channel_eq = true; |
2115 | break; | |
2116 | } | |
a4fc5ed6 | 2117 | |
37f80975 JB |
2118 | /* Try 5 times, then try clock recovery if that fails */ |
2119 | if (tries > 5) { | |
2120 | intel_dp_link_down(intel_dp); | |
2121 | intel_dp_start_link_train(intel_dp); | |
2122 | tries = 0; | |
2123 | cr_tries++; | |
2124 | continue; | |
2125 | } | |
a4fc5ed6 | 2126 | |
3cf2efb1 | 2127 | /* Compute new intel_dp->train_set as requested by target */ |
93f62dad | 2128 | intel_get_adjust_train(intel_dp, link_status); |
3cf2efb1 | 2129 | ++tries; |
869184a6 | 2130 | } |
3cf2efb1 | 2131 | |
d6c0d722 PZ |
2132 | if (channel_eq) |
2133 | DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n"); | |
2134 | ||
47ea7542 | 2135 | intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE); |
a4fc5ed6 KP |
2136 | } |
2137 | ||
2138 | static void | |
ea5b213a | 2139 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 2140 | { |
da63a9f2 PZ |
2141 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2142 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
a4fc5ed6 | 2143 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab527efc DV |
2144 | struct intel_crtc *intel_crtc = |
2145 | to_intel_crtc(intel_dig_port->base.base.crtc); | |
ea5b213a | 2146 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 2147 | |
c19b0669 PZ |
2148 | /* |
2149 | * DDI code has a strict mode set sequence and we should try to respect | |
2150 | * it, otherwise we might hang the machine in many different ways. So we | |
2151 | * really should be disabling the port only on a complete crtc_disable | |
2152 | * sequence. This function is just called under two conditions on DDI | |
2153 | * code: | |
2154 | * - Link train failed while doing crtc_enable, and on this case we | |
2155 | * really should respect the mode set sequence and wait for a | |
2156 | * crtc_disable. | |
2157 | * - Someone turned the monitor off and intel_dp_check_link_status | |
2158 | * called us. We don't need to disable the whole port on this case, so | |
2159 | * when someone turns the monitor on again, | |
2160 | * intel_ddi_prepare_link_retrain will take care of redoing the link | |
2161 | * train. | |
2162 | */ | |
affa9354 | 2163 | if (HAS_DDI(dev)) |
c19b0669 PZ |
2164 | return; |
2165 | ||
0c33d8d7 | 2166 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
2167 | return; |
2168 | ||
28c97730 | 2169 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 2170 | |
1a2eb460 | 2171 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { |
e3421a18 | 2172 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 2173 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
2174 | } else { |
2175 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 2176 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 2177 | } |
fe255d00 | 2178 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 2179 | |
ab527efc DV |
2180 | /* We don't really know why we're doing this */ |
2181 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
5eb08b69 | 2182 | |
493a7081 | 2183 | if (HAS_PCH_IBX(dev) && |
1b39d6f3 | 2184 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
da63a9f2 | 2185 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
31acbcc4 | 2186 | |
5bddd17f EA |
2187 | /* Hardware workaround: leaving our transcoder select |
2188 | * set to transcoder B while it's off will prevent the | |
2189 | * corresponding HDMI output on transcoder A. | |
2190 | * | |
2191 | * Combine this with another hardware workaround: | |
2192 | * transcoder select bit can only be cleared while the | |
2193 | * port is enabled. | |
2194 | */ | |
2195 | DP &= ~DP_PIPEB_SELECT; | |
2196 | I915_WRITE(intel_dp->output_reg, DP); | |
2197 | ||
2198 | /* Changes to enable or select take place the vblank | |
2199 | * after being written. | |
2200 | */ | |
ff50afe9 DV |
2201 | if (WARN_ON(crtc == NULL)) { |
2202 | /* We should never try to disable a port without a crtc | |
2203 | * attached. For paranoia keep the code around for a | |
2204 | * bit. */ | |
31acbcc4 CW |
2205 | POSTING_READ(intel_dp->output_reg); |
2206 | msleep(50); | |
2207 | } else | |
ab527efc | 2208 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
5bddd17f EA |
2209 | } |
2210 | ||
832afda6 | 2211 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
ea5b213a CW |
2212 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
2213 | POSTING_READ(intel_dp->output_reg); | |
f01eca2e | 2214 | msleep(intel_dp->panel_power_down_delay); |
a4fc5ed6 KP |
2215 | } |
2216 | ||
26d61aad KP |
2217 | static bool |
2218 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 2219 | { |
577c7a50 DL |
2220 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
2221 | ||
92fd8fd1 | 2222 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
edb39244 AJ |
2223 | sizeof(intel_dp->dpcd)) == 0) |
2224 | return false; /* aux transfer failed */ | |
92fd8fd1 | 2225 | |
577c7a50 DL |
2226 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
2227 | 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); | |
2228 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); | |
2229 | ||
edb39244 AJ |
2230 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
2231 | return false; /* DPCD not present */ | |
2232 | ||
2233 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
2234 | DP_DWN_STRM_PORT_PRESENT)) | |
2235 | return true; /* native DP sink */ | |
2236 | ||
2237 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
2238 | return true; /* no per-port downstream info */ | |
2239 | ||
2240 | if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, | |
2241 | intel_dp->downstream_ports, | |
2242 | DP_MAX_DOWNSTREAM_PORTS) == 0) | |
2243 | return false; /* downstream port status fetch failed */ | |
2244 | ||
2245 | return true; | |
92fd8fd1 KP |
2246 | } |
2247 | ||
0d198328 AJ |
2248 | static void |
2249 | intel_dp_probe_oui(struct intel_dp *intel_dp) | |
2250 | { | |
2251 | u8 buf[3]; | |
2252 | ||
2253 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
2254 | return; | |
2255 | ||
351cfc34 DV |
2256 | ironlake_edp_panel_vdd_on(intel_dp); |
2257 | ||
0d198328 AJ |
2258 | if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) |
2259 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", | |
2260 | buf[0], buf[1], buf[2]); | |
2261 | ||
2262 | if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) | |
2263 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", | |
2264 | buf[0], buf[1], buf[2]); | |
351cfc34 DV |
2265 | |
2266 | ironlake_edp_panel_vdd_off(intel_dp, false); | |
0d198328 AJ |
2267 | } |
2268 | ||
a60f0e38 JB |
2269 | static bool |
2270 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
2271 | { | |
2272 | int ret; | |
2273 | ||
2274 | ret = intel_dp_aux_native_read_retry(intel_dp, | |
2275 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
2276 | sink_irq_vector, 1); | |
2277 | if (!ret) | |
2278 | return false; | |
2279 | ||
2280 | return true; | |
2281 | } | |
2282 | ||
2283 | static void | |
2284 | intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
2285 | { | |
2286 | /* NAK by default */ | |
9324cf7f | 2287 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); |
a60f0e38 JB |
2288 | } |
2289 | ||
a4fc5ed6 KP |
2290 | /* |
2291 | * According to DP spec | |
2292 | * 5.1.2: | |
2293 | * 1. Read DPCD | |
2294 | * 2. Configure link according to Receiver Capabilities | |
2295 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
2296 | * 4. Check link status on receipt of hot-plug interrupt | |
2297 | */ | |
2298 | ||
00c09d70 | 2299 | void |
ea5b213a | 2300 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 2301 | { |
da63a9f2 | 2302 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
a60f0e38 | 2303 | u8 sink_irq_vector; |
93f62dad | 2304 | u8 link_status[DP_LINK_STATUS_SIZE]; |
a60f0e38 | 2305 | |
da63a9f2 | 2306 | if (!intel_encoder->connectors_active) |
d2b996ac | 2307 | return; |
59cd09e1 | 2308 | |
da63a9f2 | 2309 | if (WARN_ON(!intel_encoder->base.crtc)) |
a4fc5ed6 KP |
2310 | return; |
2311 | ||
92fd8fd1 | 2312 | /* Try to read receiver status if the link appears to be up */ |
93f62dad | 2313 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
ea5b213a | 2314 | intel_dp_link_down(intel_dp); |
a4fc5ed6 KP |
2315 | return; |
2316 | } | |
2317 | ||
92fd8fd1 | 2318 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 2319 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
2320 | intel_dp_link_down(intel_dp); |
2321 | return; | |
2322 | } | |
2323 | ||
a60f0e38 JB |
2324 | /* Try to read the source of the interrupt */ |
2325 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
2326 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
2327 | /* Clear interrupt source */ | |
2328 | intel_dp_aux_native_write_1(intel_dp, | |
2329 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
2330 | sink_irq_vector); | |
2331 | ||
2332 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
2333 | intel_dp_handle_test_request(intel_dp); | |
2334 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
2335 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
2336 | } | |
2337 | ||
1ffdff13 | 2338 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
92fd8fd1 | 2339 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
da63a9f2 | 2340 | drm_get_encoder_name(&intel_encoder->base)); |
33a34e4e JB |
2341 | intel_dp_start_link_train(intel_dp); |
2342 | intel_dp_complete_link_train(intel_dp); | |
2343 | } | |
a4fc5ed6 | 2344 | } |
a4fc5ed6 | 2345 | |
caf9ab24 | 2346 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 2347 | static enum drm_connector_status |
26d61aad | 2348 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 2349 | { |
caf9ab24 AJ |
2350 | uint8_t *dpcd = intel_dp->dpcd; |
2351 | bool hpd; | |
2352 | uint8_t type; | |
2353 | ||
2354 | if (!intel_dp_get_dpcd(intel_dp)) | |
2355 | return connector_status_disconnected; | |
2356 | ||
2357 | /* if there's no downstream port, we're done */ | |
2358 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) | |
26d61aad | 2359 | return connector_status_connected; |
caf9ab24 AJ |
2360 | |
2361 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
2362 | hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD); | |
2363 | if (hpd) { | |
23235177 | 2364 | uint8_t reg; |
caf9ab24 | 2365 | if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, |
23235177 | 2366 | ®, 1)) |
caf9ab24 | 2367 | return connector_status_unknown; |
23235177 AJ |
2368 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
2369 | : connector_status_disconnected; | |
caf9ab24 AJ |
2370 | } |
2371 | ||
2372 | /* If no HPD, poke DDC gently */ | |
2373 | if (drm_probe_ddc(&intel_dp->adapter)) | |
26d61aad | 2374 | return connector_status_connected; |
caf9ab24 AJ |
2375 | |
2376 | /* Well we tried, say unknown for unreliable port types */ | |
2377 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
2378 | if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID) | |
2379 | return connector_status_unknown; | |
2380 | ||
2381 | /* Anything else is out of spec, warn and ignore */ | |
2382 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 2383 | return connector_status_disconnected; |
71ba9000 AJ |
2384 | } |
2385 | ||
5eb08b69 | 2386 | static enum drm_connector_status |
a9756bb5 | 2387 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 2388 | { |
30add22d | 2389 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1b469639 DL |
2390 | struct drm_i915_private *dev_priv = dev->dev_private; |
2391 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
5eb08b69 ZW |
2392 | enum drm_connector_status status; |
2393 | ||
fe16d949 CW |
2394 | /* Can't disconnect eDP, but you can close the lid... */ |
2395 | if (is_edp(intel_dp)) { | |
30add22d | 2396 | status = intel_panel_detect(dev); |
fe16d949 CW |
2397 | if (status == connector_status_unknown) |
2398 | status = connector_status_connected; | |
2399 | return status; | |
2400 | } | |
01cb9ea6 | 2401 | |
1b469639 DL |
2402 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
2403 | return connector_status_disconnected; | |
2404 | ||
26d61aad | 2405 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
2406 | } |
2407 | ||
a4fc5ed6 | 2408 | static enum drm_connector_status |
a9756bb5 | 2409 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 2410 | { |
30add22d | 2411 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
a4fc5ed6 | 2412 | struct drm_i915_private *dev_priv = dev->dev_private; |
34f2be46 | 2413 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
10f76a38 | 2414 | uint32_t bit; |
5eb08b69 | 2415 | |
35aad75f JB |
2416 | /* Can't disconnect eDP, but you can close the lid... */ |
2417 | if (is_edp(intel_dp)) { | |
2418 | enum drm_connector_status status; | |
2419 | ||
2420 | status = intel_panel_detect(dev); | |
2421 | if (status == connector_status_unknown) | |
2422 | status = connector_status_connected; | |
2423 | return status; | |
2424 | } | |
2425 | ||
34f2be46 VS |
2426 | switch (intel_dig_port->port) { |
2427 | case PORT_B: | |
26739f12 | 2428 | bit = PORTB_HOTPLUG_LIVE_STATUS; |
a4fc5ed6 | 2429 | break; |
34f2be46 | 2430 | case PORT_C: |
26739f12 | 2431 | bit = PORTC_HOTPLUG_LIVE_STATUS; |
a4fc5ed6 | 2432 | break; |
34f2be46 | 2433 | case PORT_D: |
26739f12 | 2434 | bit = PORTD_HOTPLUG_LIVE_STATUS; |
a4fc5ed6 KP |
2435 | break; |
2436 | default: | |
2437 | return connector_status_unknown; | |
2438 | } | |
2439 | ||
10f76a38 | 2440 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
a4fc5ed6 KP |
2441 | return connector_status_disconnected; |
2442 | ||
26d61aad | 2443 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
2444 | } |
2445 | ||
8c241fef KP |
2446 | static struct edid * |
2447 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
2448 | { | |
9cd300e0 | 2449 | struct intel_connector *intel_connector = to_intel_connector(connector); |
d6f24d0f | 2450 | |
9cd300e0 JN |
2451 | /* use cached edid if we have one */ |
2452 | if (intel_connector->edid) { | |
2453 | struct edid *edid; | |
2454 | int size; | |
2455 | ||
2456 | /* invalid edid */ | |
2457 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
2458 | return NULL; |
2459 | ||
9cd300e0 | 2460 | size = (intel_connector->edid->extensions + 1) * EDID_LENGTH; |
d6f24d0f JB |
2461 | edid = kmalloc(size, GFP_KERNEL); |
2462 | if (!edid) | |
2463 | return NULL; | |
2464 | ||
9cd300e0 | 2465 | memcpy(edid, intel_connector->edid, size); |
d6f24d0f JB |
2466 | return edid; |
2467 | } | |
8c241fef | 2468 | |
9cd300e0 | 2469 | return drm_get_edid(connector, adapter); |
8c241fef KP |
2470 | } |
2471 | ||
2472 | static int | |
2473 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) | |
2474 | { | |
9cd300e0 | 2475 | struct intel_connector *intel_connector = to_intel_connector(connector); |
8c241fef | 2476 | |
9cd300e0 JN |
2477 | /* use cached edid if we have one */ |
2478 | if (intel_connector->edid) { | |
2479 | /* invalid edid */ | |
2480 | if (IS_ERR(intel_connector->edid)) | |
2481 | return 0; | |
2482 | ||
2483 | return intel_connector_update_modes(connector, | |
2484 | intel_connector->edid); | |
d6f24d0f JB |
2485 | } |
2486 | ||
9cd300e0 | 2487 | return intel_ddc_get_modes(connector, adapter); |
8c241fef KP |
2488 | } |
2489 | ||
a9756bb5 ZW |
2490 | static enum drm_connector_status |
2491 | intel_dp_detect(struct drm_connector *connector, bool force) | |
2492 | { | |
2493 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
d63885da PZ |
2494 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2495 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 2496 | struct drm_device *dev = connector->dev; |
a9756bb5 ZW |
2497 | enum drm_connector_status status; |
2498 | struct edid *edid = NULL; | |
2499 | ||
2500 | intel_dp->has_audio = false; | |
2501 | ||
2502 | if (HAS_PCH_SPLIT(dev)) | |
2503 | status = ironlake_dp_detect(intel_dp); | |
2504 | else | |
2505 | status = g4x_dp_detect(intel_dp); | |
1b9be9d0 | 2506 | |
a9756bb5 ZW |
2507 | if (status != connector_status_connected) |
2508 | return status; | |
2509 | ||
0d198328 AJ |
2510 | intel_dp_probe_oui(intel_dp); |
2511 | ||
c3e5f67b DV |
2512 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
2513 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); | |
f684960e | 2514 | } else { |
8c241fef | 2515 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
f684960e CW |
2516 | if (edid) { |
2517 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
f684960e CW |
2518 | kfree(edid); |
2519 | } | |
a9756bb5 ZW |
2520 | } |
2521 | ||
d63885da PZ |
2522 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
2523 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
a9756bb5 | 2524 | return connector_status_connected; |
a4fc5ed6 KP |
2525 | } |
2526 | ||
2527 | static int intel_dp_get_modes(struct drm_connector *connector) | |
2528 | { | |
df0e9248 | 2529 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e | 2530 | struct intel_connector *intel_connector = to_intel_connector(connector); |
fa90ecef | 2531 | struct drm_device *dev = connector->dev; |
32f9d658 | 2532 | int ret; |
a4fc5ed6 KP |
2533 | |
2534 | /* We should parse the EDID data and find out if it has an audio sink | |
2535 | */ | |
2536 | ||
8c241fef | 2537 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
f8779fda | 2538 | if (ret) |
32f9d658 ZW |
2539 | return ret; |
2540 | ||
f8779fda | 2541 | /* if eDP has no EDID, fall back to fixed mode */ |
dd06f90e | 2542 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
f8779fda | 2543 | struct drm_display_mode *mode; |
dd06f90e JN |
2544 | mode = drm_mode_duplicate(dev, |
2545 | intel_connector->panel.fixed_mode); | |
f8779fda | 2546 | if (mode) { |
32f9d658 ZW |
2547 | drm_mode_probed_add(connector, mode); |
2548 | return 1; | |
2549 | } | |
2550 | } | |
2551 | return 0; | |
a4fc5ed6 KP |
2552 | } |
2553 | ||
1aad7ac0 CW |
2554 | static bool |
2555 | intel_dp_detect_audio(struct drm_connector *connector) | |
2556 | { | |
2557 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
2558 | struct edid *edid; | |
2559 | bool has_audio = false; | |
2560 | ||
8c241fef | 2561 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
1aad7ac0 CW |
2562 | if (edid) { |
2563 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
2564 | kfree(edid); |
2565 | } | |
2566 | ||
2567 | return has_audio; | |
2568 | } | |
2569 | ||
f684960e CW |
2570 | static int |
2571 | intel_dp_set_property(struct drm_connector *connector, | |
2572 | struct drm_property *property, | |
2573 | uint64_t val) | |
2574 | { | |
e953fd7b | 2575 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
53b41837 | 2576 | struct intel_connector *intel_connector = to_intel_connector(connector); |
da63a9f2 PZ |
2577 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
2578 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
f684960e CW |
2579 | int ret; |
2580 | ||
662595df | 2581 | ret = drm_object_property_set_value(&connector->base, property, val); |
f684960e CW |
2582 | if (ret) |
2583 | return ret; | |
2584 | ||
3f43c48d | 2585 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
2586 | int i = val; |
2587 | bool has_audio; | |
2588 | ||
2589 | if (i == intel_dp->force_audio) | |
f684960e CW |
2590 | return 0; |
2591 | ||
1aad7ac0 | 2592 | intel_dp->force_audio = i; |
f684960e | 2593 | |
c3e5f67b | 2594 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
2595 | has_audio = intel_dp_detect_audio(connector); |
2596 | else | |
c3e5f67b | 2597 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
2598 | |
2599 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
2600 | return 0; |
2601 | ||
1aad7ac0 | 2602 | intel_dp->has_audio = has_audio; |
f684960e CW |
2603 | goto done; |
2604 | } | |
2605 | ||
e953fd7b | 2606 | if (property == dev_priv->broadcast_rgb_property) { |
55bc60db VS |
2607 | switch (val) { |
2608 | case INTEL_BROADCAST_RGB_AUTO: | |
2609 | intel_dp->color_range_auto = true; | |
2610 | break; | |
2611 | case INTEL_BROADCAST_RGB_FULL: | |
2612 | intel_dp->color_range_auto = false; | |
2613 | intel_dp->color_range = 0; | |
2614 | break; | |
2615 | case INTEL_BROADCAST_RGB_LIMITED: | |
2616 | intel_dp->color_range_auto = false; | |
2617 | intel_dp->color_range = DP_COLOR_RANGE_16_235; | |
2618 | break; | |
2619 | default: | |
2620 | return -EINVAL; | |
2621 | } | |
e953fd7b CW |
2622 | goto done; |
2623 | } | |
2624 | ||
53b41837 YN |
2625 | if (is_edp(intel_dp) && |
2626 | property == connector->dev->mode_config.scaling_mode_property) { | |
2627 | if (val == DRM_MODE_SCALE_NONE) { | |
2628 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
2629 | return -EINVAL; | |
2630 | } | |
2631 | ||
2632 | if (intel_connector->panel.fitting_mode == val) { | |
2633 | /* the eDP scaling property is not changed */ | |
2634 | return 0; | |
2635 | } | |
2636 | intel_connector->panel.fitting_mode = val; | |
2637 | ||
2638 | goto done; | |
2639 | } | |
2640 | ||
f684960e CW |
2641 | return -EINVAL; |
2642 | ||
2643 | done: | |
c0c36b94 CW |
2644 | if (intel_encoder->base.crtc) |
2645 | intel_crtc_restore_mode(intel_encoder->base.crtc); | |
f684960e CW |
2646 | |
2647 | return 0; | |
2648 | } | |
2649 | ||
a4fc5ed6 | 2650 | static void |
0206e353 | 2651 | intel_dp_destroy(struct drm_connector *connector) |
a4fc5ed6 | 2652 | { |
be3cd5e3 | 2653 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
1d508706 | 2654 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 2655 | |
9cd300e0 JN |
2656 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
2657 | kfree(intel_connector->edid); | |
2658 | ||
dc652f90 | 2659 | if (is_edp(intel_dp)) |
1d508706 | 2660 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 2661 | |
a4fc5ed6 KP |
2662 | drm_sysfs_connector_remove(connector); |
2663 | drm_connector_cleanup(connector); | |
55f78c43 | 2664 | kfree(connector); |
a4fc5ed6 KP |
2665 | } |
2666 | ||
00c09d70 | 2667 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 2668 | { |
da63a9f2 PZ |
2669 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
2670 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
24d05927 DV |
2671 | |
2672 | i2c_del_adapter(&intel_dp->adapter); | |
2673 | drm_encoder_cleanup(encoder); | |
bd943159 KP |
2674 | if (is_edp(intel_dp)) { |
2675 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
2676 | ironlake_panel_vdd_off_sync(intel_dp); | |
2677 | } | |
da63a9f2 | 2678 | kfree(intel_dig_port); |
24d05927 DV |
2679 | } |
2680 | ||
a4fc5ed6 | 2681 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
a4fc5ed6 | 2682 | .mode_set = intel_dp_mode_set, |
a4fc5ed6 KP |
2683 | }; |
2684 | ||
2685 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
2bd2ad64 | 2686 | .dpms = intel_connector_dpms, |
a4fc5ed6 KP |
2687 | .detect = intel_dp_detect, |
2688 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 2689 | .set_property = intel_dp_set_property, |
a4fc5ed6 KP |
2690 | .destroy = intel_dp_destroy, |
2691 | }; | |
2692 | ||
2693 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
2694 | .get_modes = intel_dp_get_modes, | |
2695 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 2696 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
2697 | }; |
2698 | ||
a4fc5ed6 | 2699 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 2700 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
2701 | }; |
2702 | ||
995b6762 | 2703 | static void |
21d40d37 | 2704 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 2705 | { |
fa90ecef | 2706 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
c8110e52 | 2707 | |
885a5014 | 2708 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 2709 | } |
6207937d | 2710 | |
e3421a18 ZW |
2711 | /* Return which DP Port should be selected for Transcoder DP control */ |
2712 | int | |
0206e353 | 2713 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
e3421a18 ZW |
2714 | { |
2715 | struct drm_device *dev = crtc->dev; | |
fa90ecef PZ |
2716 | struct intel_encoder *intel_encoder; |
2717 | struct intel_dp *intel_dp; | |
e3421a18 | 2718 | |
fa90ecef PZ |
2719 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
2720 | intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
e3421a18 | 2721 | |
fa90ecef PZ |
2722 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
2723 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
ea5b213a | 2724 | return intel_dp->output_reg; |
e3421a18 | 2725 | } |
ea5b213a | 2726 | |
e3421a18 ZW |
2727 | return -1; |
2728 | } | |
2729 | ||
36e83a18 | 2730 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 2731 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
2732 | { |
2733 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2734 | struct child_device_config *p_child; | |
2735 | int i; | |
2736 | ||
2737 | if (!dev_priv->child_dev_num) | |
2738 | return false; | |
2739 | ||
2740 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
2741 | p_child = dev_priv->child_dev + i; | |
2742 | ||
2743 | if (p_child->dvo_port == PORT_IDPD && | |
2744 | p_child->device_type == DEVICE_TYPE_eDP) | |
2745 | return true; | |
2746 | } | |
2747 | return false; | |
2748 | } | |
2749 | ||
f684960e CW |
2750 | static void |
2751 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
2752 | { | |
53b41837 YN |
2753 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2754 | ||
3f43c48d | 2755 | intel_attach_force_audio_property(connector); |
e953fd7b | 2756 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 2757 | intel_dp->color_range_auto = true; |
53b41837 YN |
2758 | |
2759 | if (is_edp(intel_dp)) { | |
2760 | drm_mode_create_scaling_mode_property(connector->dev); | |
6de6d846 RC |
2761 | drm_object_attach_property( |
2762 | &connector->base, | |
53b41837 | 2763 | connector->dev->mode_config.scaling_mode_property, |
8e740cd1 YN |
2764 | DRM_MODE_SCALE_ASPECT); |
2765 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
53b41837 | 2766 | } |
f684960e CW |
2767 | } |
2768 | ||
67a54566 DV |
2769 | static void |
2770 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
f30d26e4 JN |
2771 | struct intel_dp *intel_dp, |
2772 | struct edp_power_seq *out) | |
67a54566 DV |
2773 | { |
2774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2775 | struct edp_power_seq cur, vbt, spec, final; | |
2776 | u32 pp_on, pp_off, pp_div, pp; | |
453c5420 JB |
2777 | int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
2778 | ||
2779 | if (HAS_PCH_SPLIT(dev)) { | |
2780 | pp_control_reg = PCH_PP_CONTROL; | |
2781 | pp_on_reg = PCH_PP_ON_DELAYS; | |
2782 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
2783 | pp_div_reg = PCH_PP_DIVISOR; | |
2784 | } else { | |
2785 | pp_control_reg = PIPEA_PP_CONTROL; | |
2786 | pp_on_reg = PIPEA_PP_ON_DELAYS; | |
2787 | pp_off_reg = PIPEA_PP_OFF_DELAYS; | |
2788 | pp_div_reg = PIPEA_PP_DIVISOR; | |
2789 | } | |
67a54566 DV |
2790 | |
2791 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
2792 | * the very first thing. */ | |
453c5420 JB |
2793 | pp = ironlake_get_pp_control(intel_dp); |
2794 | I915_WRITE(pp_control_reg, pp); | |
67a54566 | 2795 | |
453c5420 JB |
2796 | pp_on = I915_READ(pp_on_reg); |
2797 | pp_off = I915_READ(pp_off_reg); | |
2798 | pp_div = I915_READ(pp_div_reg); | |
67a54566 DV |
2799 | |
2800 | /* Pull timing values out of registers */ | |
2801 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
2802 | PANEL_POWER_UP_DELAY_SHIFT; | |
2803 | ||
2804 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
2805 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
2806 | ||
2807 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
2808 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
2809 | ||
2810 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
2811 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
2812 | ||
2813 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
2814 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
2815 | ||
2816 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2817 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
2818 | ||
2819 | vbt = dev_priv->edp.pps; | |
2820 | ||
2821 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
2822 | * our hw here, which are all in 100usec. */ | |
2823 | spec.t1_t3 = 210 * 10; | |
2824 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
2825 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
2826 | spec.t10 = 500 * 10; | |
2827 | /* This one is special and actually in units of 100ms, but zero | |
2828 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
2829 | * table multiplies it with 1000 to make it in units of 100usec, | |
2830 | * too. */ | |
2831 | spec.t11_t12 = (510 + 100) * 10; | |
2832 | ||
2833 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2834 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
2835 | ||
2836 | /* Use the max of the register settings and vbt. If both are | |
2837 | * unset, fall back to the spec limits. */ | |
2838 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ | |
2839 | spec.field : \ | |
2840 | max(cur.field, vbt.field)) | |
2841 | assign_final(t1_t3); | |
2842 | assign_final(t8); | |
2843 | assign_final(t9); | |
2844 | assign_final(t10); | |
2845 | assign_final(t11_t12); | |
2846 | #undef assign_final | |
2847 | ||
2848 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) | |
2849 | intel_dp->panel_power_up_delay = get_delay(t1_t3); | |
2850 | intel_dp->backlight_on_delay = get_delay(t8); | |
2851 | intel_dp->backlight_off_delay = get_delay(t9); | |
2852 | intel_dp->panel_power_down_delay = get_delay(t10); | |
2853 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
2854 | #undef get_delay | |
2855 | ||
f30d26e4 JN |
2856 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
2857 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
2858 | intel_dp->panel_power_cycle_delay); | |
2859 | ||
2860 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
2861 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
2862 | ||
2863 | if (out) | |
2864 | *out = final; | |
2865 | } | |
2866 | ||
2867 | static void | |
2868 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
2869 | struct intel_dp *intel_dp, | |
2870 | struct edp_power_seq *seq) | |
2871 | { | |
2872 | struct drm_i915_private *dev_priv = dev->dev_private; | |
453c5420 JB |
2873 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
2874 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); | |
2875 | int pp_on_reg, pp_off_reg, pp_div_reg; | |
2876 | ||
2877 | if (HAS_PCH_SPLIT(dev)) { | |
2878 | pp_on_reg = PCH_PP_ON_DELAYS; | |
2879 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
2880 | pp_div_reg = PCH_PP_DIVISOR; | |
2881 | } else { | |
2882 | pp_on_reg = PIPEA_PP_ON_DELAYS; | |
2883 | pp_off_reg = PIPEA_PP_OFF_DELAYS; | |
2884 | pp_div_reg = PIPEA_PP_DIVISOR; | |
2885 | } | |
2886 | ||
2887 | if (IS_VALLEYVIEW(dev)) | |
2888 | port_sel = I915_READ(pp_on_reg) & 0xc0000000; | |
f30d26e4 | 2889 | |
67a54566 | 2890 | /* And finally store the new values in the power sequencer. */ |
f30d26e4 JN |
2891 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
2892 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); | |
2893 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
2894 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); | |
67a54566 DV |
2895 | /* Compute the divisor for the pp clock, simply match the Bspec |
2896 | * formula. */ | |
453c5420 | 2897 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
f30d26e4 | 2898 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
67a54566 DV |
2899 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
2900 | ||
2901 | /* Haswell doesn't have any port selection bits for the panel | |
2902 | * power sequencer any more. */ | |
2903 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
2904 | if (is_cpu_edp(intel_dp)) | |
453c5420 | 2905 | port_sel = PANEL_POWER_PORT_DP_A; |
67a54566 | 2906 | else |
453c5420 | 2907 | port_sel = PANEL_POWER_PORT_DP_D; |
67a54566 DV |
2908 | } |
2909 | ||
453c5420 JB |
2910 | pp_on |= port_sel; |
2911 | ||
2912 | I915_WRITE(pp_on_reg, pp_on); | |
2913 | I915_WRITE(pp_off_reg, pp_off); | |
2914 | I915_WRITE(pp_div_reg, pp_div); | |
67a54566 | 2915 | |
67a54566 | 2916 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
453c5420 JB |
2917 | I915_READ(pp_on_reg), |
2918 | I915_READ(pp_off_reg), | |
2919 | I915_READ(pp_div_reg)); | |
f684960e CW |
2920 | } |
2921 | ||
a4fc5ed6 | 2922 | void |
f0fec3f2 PZ |
2923 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
2924 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 2925 | { |
f0fec3f2 PZ |
2926 | struct drm_connector *connector = &intel_connector->base; |
2927 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
2928 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
2929 | struct drm_device *dev = intel_encoder->base.dev; | |
a4fc5ed6 | 2930 | struct drm_i915_private *dev_priv = dev->dev_private; |
f8779fda | 2931 | struct drm_display_mode *fixed_mode = NULL; |
f30d26e4 | 2932 | struct edp_power_seq power_seq = { 0 }; |
174edf1f | 2933 | enum port port = intel_dig_port->port; |
5eb08b69 | 2934 | const char *name = NULL; |
b329530c | 2935 | int type; |
a4fc5ed6 | 2936 | |
0767935e DV |
2937 | /* Preserve the current hw state. */ |
2938 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 2939 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 2940 | |
f0fec3f2 | 2941 | if (HAS_PCH_SPLIT(dev) && port == PORT_D) |
b329530c | 2942 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 2943 | intel_dp->is_pch_edp = true; |
b329530c | 2944 | |
19c03924 GB |
2945 | /* |
2946 | * FIXME : We need to initialize built-in panels before external panels. | |
2947 | * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup | |
2948 | */ | |
f0fec3f2 | 2949 | if (IS_VALLEYVIEW(dev) && port == PORT_C) { |
19c03924 GB |
2950 | type = DRM_MODE_CONNECTOR_eDP; |
2951 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
f0fec3f2 | 2952 | } else if (port == PORT_A || is_pch_edp(intel_dp)) { |
b329530c AJ |
2953 | type = DRM_MODE_CONNECTOR_eDP; |
2954 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
2955 | } else { | |
00c09d70 PZ |
2956 | /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for |
2957 | * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't | |
2958 | * rewrite it. | |
2959 | */ | |
b329530c | 2960 | type = DRM_MODE_CONNECTOR_DisplayPort; |
b329530c AJ |
2961 | } |
2962 | ||
b329530c | 2963 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
2964 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
2965 | ||
a4fc5ed6 KP |
2966 | connector->interlace_allowed = true; |
2967 | connector->doublescan_allowed = 0; | |
2968 | ||
f0fec3f2 PZ |
2969 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
2970 | ironlake_panel_vdd_work); | |
a4fc5ed6 | 2971 | |
df0e9248 | 2972 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
2973 | drm_sysfs_connector_add(connector); |
2974 | ||
affa9354 | 2975 | if (HAS_DDI(dev)) |
bcbc889b PZ |
2976 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
2977 | else | |
2978 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
2979 | ||
9ed35ab1 PZ |
2980 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
2981 | if (HAS_DDI(dev)) { | |
2982 | switch (intel_dig_port->port) { | |
2983 | case PORT_A: | |
2984 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; | |
2985 | break; | |
2986 | case PORT_B: | |
2987 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; | |
2988 | break; | |
2989 | case PORT_C: | |
2990 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; | |
2991 | break; | |
2992 | case PORT_D: | |
2993 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; | |
2994 | break; | |
2995 | default: | |
2996 | BUG(); | |
2997 | } | |
2998 | } | |
e8cb4558 | 2999 | |
a4fc5ed6 | 3000 | /* Set up the DDC bus. */ |
ab9d7c30 PZ |
3001 | switch (port) { |
3002 | case PORT_A: | |
1d843f9d | 3003 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
3004 | name = "DPDDC-A"; |
3005 | break; | |
3006 | case PORT_B: | |
1d843f9d | 3007 | intel_encoder->hpd_pin = HPD_PORT_B; |
ab9d7c30 PZ |
3008 | name = "DPDDC-B"; |
3009 | break; | |
3010 | case PORT_C: | |
1d843f9d | 3011 | intel_encoder->hpd_pin = HPD_PORT_C; |
ab9d7c30 PZ |
3012 | name = "DPDDC-C"; |
3013 | break; | |
3014 | case PORT_D: | |
1d843f9d | 3015 | intel_encoder->hpd_pin = HPD_PORT_D; |
ab9d7c30 PZ |
3016 | name = "DPDDC-D"; |
3017 | break; | |
3018 | default: | |
ad1c0b19 | 3019 | BUG(); |
5eb08b69 ZW |
3020 | } |
3021 | ||
67a54566 | 3022 | if (is_edp(intel_dp)) |
f30d26e4 | 3023 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
c1f05264 DA |
3024 | |
3025 | intel_dp_i2c_init(intel_dp, intel_connector, name); | |
3026 | ||
67a54566 | 3027 | /* Cache DPCD and EDID for edp. */ |
c1f05264 DA |
3028 | if (is_edp(intel_dp)) { |
3029 | bool ret; | |
f8779fda | 3030 | struct drm_display_mode *scan; |
c1f05264 | 3031 | struct edid *edid; |
5d613501 JB |
3032 | |
3033 | ironlake_edp_panel_vdd_on(intel_dp); | |
59f3e272 | 3034 | ret = intel_dp_get_dpcd(intel_dp); |
bd943159 | 3035 | ironlake_edp_panel_vdd_off(intel_dp, false); |
99ea7127 | 3036 | |
59f3e272 | 3037 | if (ret) { |
7183dc29 JB |
3038 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
3039 | dev_priv->no_aux_handshake = | |
3040 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
89667383 JB |
3041 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
3042 | } else { | |
3d3dc149 | 3043 | /* if this fails, presume the device is a ghost */ |
48898b03 | 3044 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
fa90ecef PZ |
3045 | intel_dp_encoder_destroy(&intel_encoder->base); |
3046 | intel_dp_destroy(connector); | |
3d3dc149 | 3047 | return; |
89667383 | 3048 | } |
89667383 | 3049 | |
f30d26e4 JN |
3050 | /* We now know it's not a ghost, init power sequence regs. */ |
3051 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, | |
3052 | &power_seq); | |
3053 | ||
d6f24d0f JB |
3054 | ironlake_edp_panel_vdd_on(intel_dp); |
3055 | edid = drm_get_edid(connector, &intel_dp->adapter); | |
3056 | if (edid) { | |
9cd300e0 JN |
3057 | if (drm_add_edid_modes(connector, edid)) { |
3058 | drm_mode_connector_update_edid_property(connector, edid); | |
3059 | drm_edid_to_eld(connector, edid); | |
3060 | } else { | |
3061 | kfree(edid); | |
3062 | edid = ERR_PTR(-EINVAL); | |
3063 | } | |
3064 | } else { | |
3065 | edid = ERR_PTR(-ENOENT); | |
d6f24d0f | 3066 | } |
9cd300e0 | 3067 | intel_connector->edid = edid; |
f8779fda JN |
3068 | |
3069 | /* prefer fixed mode from EDID if available */ | |
3070 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
3071 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
3072 | fixed_mode = drm_mode_duplicate(dev, scan); | |
3073 | break; | |
3074 | } | |
d6f24d0f | 3075 | } |
f8779fda JN |
3076 | |
3077 | /* fallback to VBT if available for eDP */ | |
3078 | if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) { | |
3079 | fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); | |
3080 | if (fixed_mode) | |
3081 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
3082 | } | |
f8779fda | 3083 | |
d6f24d0f JB |
3084 | ironlake_edp_panel_vdd_off(intel_dp, false); |
3085 | } | |
552fb0b7 | 3086 | |
4d926461 | 3087 | if (is_edp(intel_dp)) { |
dd06f90e | 3088 | intel_panel_init(&intel_connector->panel, fixed_mode); |
0657b6b1 | 3089 | intel_panel_setup_backlight(connector); |
32f9d658 ZW |
3090 | } |
3091 | ||
f684960e CW |
3092 | intel_dp_add_properties(intel_dp, connector); |
3093 | ||
a4fc5ed6 KP |
3094 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
3095 | * 0xd. Failure to do so will result in spurious interrupts being | |
3096 | * generated on the port when a cable is not attached. | |
3097 | */ | |
3098 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
3099 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
3100 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
3101 | } | |
3102 | } | |
f0fec3f2 PZ |
3103 | |
3104 | void | |
3105 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) | |
3106 | { | |
3107 | struct intel_digital_port *intel_dig_port; | |
3108 | struct intel_encoder *intel_encoder; | |
3109 | struct drm_encoder *encoder; | |
3110 | struct intel_connector *intel_connector; | |
3111 | ||
3112 | intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL); | |
3113 | if (!intel_dig_port) | |
3114 | return; | |
3115 | ||
3116 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
3117 | if (!intel_connector) { | |
3118 | kfree(intel_dig_port); | |
3119 | return; | |
3120 | } | |
3121 | ||
3122 | intel_encoder = &intel_dig_port->base; | |
3123 | encoder = &intel_encoder->base; | |
3124 | ||
3125 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, | |
3126 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 3127 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
f0fec3f2 | 3128 | |
5bfe2ac0 | 3129 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 PZ |
3130 | intel_encoder->enable = intel_enable_dp; |
3131 | intel_encoder->pre_enable = intel_pre_enable_dp; | |
3132 | intel_encoder->disable = intel_disable_dp; | |
3133 | intel_encoder->post_disable = intel_post_disable_dp; | |
3134 | intel_encoder->get_hw_state = intel_dp_get_hw_state; | |
89b667f8 JB |
3135 | if (IS_VALLEYVIEW(dev)) |
3136 | intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable; | |
f0fec3f2 | 3137 | |
174edf1f | 3138 | intel_dig_port->port = port; |
f0fec3f2 PZ |
3139 | intel_dig_port->dp.output_reg = output_reg; |
3140 | ||
00c09d70 | 3141 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
f0fec3f2 PZ |
3142 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
3143 | intel_encoder->cloneable = false; | |
3144 | intel_encoder->hot_plug = intel_dp_hot_plug; | |
3145 | ||
3146 | intel_dp_init_connector(intel_dig_port, intel_connector); | |
3147 | } |