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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf
CML		 50struct dp_link_dpll {
51 int link_bw;
52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
63 { DP_LINK_BW_1_62,
64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
65 { DP_LINK_BW_2_7,
66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5
CML		 69static const struct dp_link_dpll vlv_dpll[] = {
70 { DP_LINK_BW_1_62,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 72 { DP_LINK_BW_2_7,
73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
86 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
88 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
90 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15 97 324000, 432000, 540000 };
fe51bfb9
VS		 98static const int chv_rates[] = { 162000, 202500, 210000, 216000,
99 243000, 270000, 324000, 405000,
100 420000, 432000, 540000 };
f4896f15 101static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 102
cfcb0fc9
JB		 103/**
104 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
105 * @intel_dp: DP struct
106 *
107 * If a CPU or PCH DP output is attached to an eDP panel, this function
108 * will return true, and false otherwise.
109 */
110static bool is_edp(struct intel_dp *intel_dp)
111{
da63a9f2
PZ		 112 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
113
114 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 115}
116
68b4d824 117static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 118{
68b4d824
ID		 119 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
120
121 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 122}
123
df0e9248
CW		 124static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
125{
fa90ecef 126 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 127}
128
ea5b213a 129static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 130static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 131static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 132static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 133static void vlv_steal_power_sequencer(struct drm_device *dev,
134 enum pipe pipe);
a4fc5ed6 135
ed4e9c1d
VS		 136static int
137intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 138{
7183dc29 139 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 140
141 switch (max_link_bw) {
142 case DP_LINK_BW_1_62:
143 case DP_LINK_BW_2_7:
1db10e28 144 case DP_LINK_BW_5_4:
d4eead50 145 break;
a4fc5ed6 146 default:
d4eead50
ID		 147 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
148 max_link_bw);
a4fc5ed6
KP		 149 max_link_bw = DP_LINK_BW_1_62;
150 break;
151 }
152 return max_link_bw;
153}
154
eeb6324d
PZ		 155static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
156{
157 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
158 struct drm_device *dev = intel_dig_port->base.base.dev;
159 u8 source_max, sink_max;
160
161 source_max = 4;
162 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
163 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
164 source_max = 2;
165
166 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
167
168 return min(source_max, sink_max);
169}
170
cd9dde44
AJ		 171/*
172 * The units on the numbers in the next two are... bizarre. Examples will
173 * make it clearer; this one parallels an example in the eDP spec.
174 *
175 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
176 *
177 * 270000 * 1 * 8 / 10 == 216000
178 *
179 * The actual data capacity of that configuration is 2.16Gbit/s, so the
180 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
181 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
182 * 119000. At 18bpp that's 2142000 kilobits per second.
183 *
184 * Thus the strange-looking division by 10 in intel_dp_link_required, to
185 * get the result in decakilobits instead of kilobits.
186 */
187
a4fc5ed6 188static int
c898261c 189intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 190{
cd9dde44 191 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 192}
193
fe27d53e
DA		 194static int
195intel_dp_max_data_rate(int max_link_clock, int max_lanes)
196{
197 return (max_link_clock * max_lanes * 8) / 10;
198}
199
c19de8eb 200static enum drm_mode_status
a4fc5ed6
KP		 201intel_dp_mode_valid(struct drm_connector *connector,
202 struct drm_display_mode *mode)
203{
df0e9248 204 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 205 struct intel_connector *intel_connector = to_intel_connector(connector);
206 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 207 int target_clock = mode->clock;
208 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 209
dd06f90e
JN		 210 if (is_edp(intel_dp) && fixed_mode) {
211 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 212 return MODE_PANEL;
213
dd06f90e 214 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 215 return MODE_PANEL;
03afc4a2
DV		 216
217 target_clock = fixed_mode->clock;
7de56f43
ZY		 218 }
219
50fec21a 220 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 221 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 222
223 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
224 mode_rate = intel_dp_link_required(target_clock, 18);
225
226 if (mode_rate > max_rate)
c4867936 227 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 228
229 if (mode->clock < 10000)
230 return MODE_CLOCK_LOW;
231
0af78a2b
DV		 232 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
233 return MODE_H_ILLEGAL;
234
a4fc5ed6
KP		 235 return MODE_OK;
236}
237
a4f1289e 238uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 239{
240 int i;
241 uint32_t v = 0;
242
243 if (src_bytes > 4)
244 src_bytes = 4;
245 for (i = 0; i < src_bytes; i++)
246 v |= ((uint32_t) src[i]) << ((3-i) * 8);
247 return v;
248}
249
c2af70e2 250static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 251{
252 int i;
253 if (dst_bytes > 4)
254 dst_bytes = 4;
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
257}
258
fb0f8fbf
KP		 259/* hrawclock is 1/4 the FSB frequency */
260static int
261intel_hrawclk(struct drm_device *dev)
262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 uint32_t clkcfg;
265
9473c8f4
VP		 266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
268 return 200;
269
fb0f8fbf
KP		 270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
272 case CLKCFG_FSB_400:
273 return 100;
274 case CLKCFG_FSB_533:
275 return 133;
276 case CLKCFG_FSB_667:
277 return 166;
278 case CLKCFG_FSB_800:
279 return 200;
280 case CLKCFG_FSB_1067:
281 return 266;
282 case CLKCFG_FSB_1333:
283 return 333;
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
287 return 400;
288 default:
289 return 133;
290 }
291}
292
bf13e81b
JN		 293static void
294intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 295 struct intel_dp *intel_dp);
bf13e81b
JN		 296static void
297intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 298 struct intel_dp *intel_dp);
bf13e81b 299
773538e8
VS		 300static void pps_lock(struct intel_dp *intel_dp)
301{
302 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
303 struct intel_encoder *encoder = &intel_dig_port->base;
304 struct drm_device *dev = encoder->base.dev;
305 struct drm_i915_private *dev_priv = dev->dev_private;
306 enum intel_display_power_domain power_domain;
307
308 /*
309 * See vlv_power_sequencer_reset() why we need
310 * a power domain reference here.
311 */
312 power_domain = intel_display_port_power_domain(encoder);
313 intel_display_power_get(dev_priv, power_domain);
314
315 mutex_lock(&dev_priv->pps_mutex);
316}
317
318static void pps_unlock(struct intel_dp *intel_dp)
319{
320 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
321 struct intel_encoder *encoder = &intel_dig_port->base;
322 struct drm_device *dev = encoder->base.dev;
323 struct drm_i915_private *dev_priv = dev->dev_private;
324 enum intel_display_power_domain power_domain;
325
326 mutex_unlock(&dev_priv->pps_mutex);
327
328 power_domain = intel_display_port_power_domain(encoder);
329 intel_display_power_put(dev_priv, power_domain);
330}
331
961a0db0
VS		 332static void
333vlv_power_sequencer_kick(struct intel_dp *intel_dp)
334{
335 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
336 struct drm_device *dev = intel_dig_port->base.base.dev;
337 struct drm_i915_private *dev_priv = dev->dev_private;
338 enum pipe pipe = intel_dp->pps_pipe;
d288f65f 339 bool pll_enabled;
961a0db0
VS		 340 uint32_t DP;
341
342 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
343 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
344 pipe_name(pipe), port_name(intel_dig_port->port)))
345 return;
346
347 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
348 pipe_name(pipe), port_name(intel_dig_port->port));
349
350 /* Preserve the BIOS-computed detected bit. This is
351 * supposed to be read-only.
352 */
353 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
354 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
355 DP |= DP_PORT_WIDTH(1);
356 DP |= DP_LINK_TRAIN_PAT_1;
357
358 if (IS_CHERRYVIEW(dev))
359 DP |= DP_PIPE_SELECT_CHV(pipe);
360 else if (pipe == PIPE_B)
361 DP |= DP_PIPEB_SELECT;
362
d288f65f
VS		 363 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
364
365 /*
366 * The DPLL for the pipe must be enabled for this to work.
367 * So enable temporarily it if it's not already enabled.
368 */
369 if (!pll_enabled)
370 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
371 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
372
961a0db0
VS		 373 /*
374 * Similar magic as in intel_dp_enable_port().
375 * We _must_ do this port enable + disable trick
376 * to make this power seqeuencer lock onto the port.
377 * Otherwise even VDD force bit won't work.
378 */
379 I915_WRITE(intel_dp->output_reg, DP);
380 POSTING_READ(intel_dp->output_reg);
381
382 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
383 POSTING_READ(intel_dp->output_reg);
384
385 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
386 POSTING_READ(intel_dp->output_reg);
d288f65f
VS		 387
388 if (!pll_enabled)
389 vlv_force_pll_off(dev, pipe);
961a0db0
VS		 390}
391
bf13e81b
JN		 392static enum pipe
393vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
394{
395 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 396 struct drm_device *dev = intel_dig_port->base.base.dev;
397 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 398 struct intel_encoder *encoder;
399 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 400 enum pipe pipe;
bf13e81b 401
e39b999a 402 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 403
a8c3344e
VS		 404 /* We should never land here with regular DP ports */
405 WARN_ON(!is_edp(intel_dp));
406
a4a5d2f8
VS		 407 if (intel_dp->pps_pipe != INVALID_PIPE)
408 return intel_dp->pps_pipe;
409
410 /*
411 * We don't have power sequencer currently.
412 * Pick one that's not used by other ports.
413 */
414 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
415 base.head) {
416 struct intel_dp *tmp;
417
418 if (encoder->type != INTEL_OUTPUT_EDP)
419 continue;
420
421 tmp = enc_to_intel_dp(&encoder->base);
422
423 if (tmp->pps_pipe != INVALID_PIPE)
424 pipes &= ~(1 << tmp->pps_pipe);
425 }
426
427 /*
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
430 */
431 if (WARN_ON(pipes == 0))
a8c3344e
VS		 432 pipe = PIPE_A;
433 else
434 pipe = ffs(pipes) - 1;
a4a5d2f8 435
a8c3344e
VS		 436 vlv_steal_power_sequencer(dev, pipe);
437 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 438
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp->pps_pipe),
441 port_name(intel_dig_port->port));
442
443 /* init power sequencer on this pipe and port */
36b5f425
VS		 444 intel_dp_init_panel_power_sequencer(dev, intel_dp);
445 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 446
961a0db0
VS		 447 /*
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
450 */
451 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 452
453 return intel_dp->pps_pipe;
454}
455
6491ab27
VS		 456typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
457 enum pipe pipe);
458
459static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
460 enum pipe pipe)
461{
462 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
463}
464
465static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
466 enum pipe pipe)
467{
468 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
469}
470
471static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
472 enum pipe pipe)
473{
474 return true;
475}
bf13e81b 476
a4a5d2f8 477static enum pipe
6491ab27
VS		 478vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
479 enum port port,
480 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 481{
482 enum pipe pipe;
bf13e81b 483
bf13e81b
JN		 484 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
485 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
486 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 487
488 if (port_sel != PANEL_PORT_SELECT_VLV(port))
489 continue;
490
6491ab27
VS		 491 if (!pipe_check(dev_priv, pipe))
492 continue;
493
a4a5d2f8 494 return pipe;
bf13e81b
JN		 495 }
496
a4a5d2f8
VS		 497 return INVALID_PIPE;
498}
499
500static void
501vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
502{
503 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
504 struct drm_device *dev = intel_dig_port->base.base.dev;
505 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 506 enum port port = intel_dig_port->port;
507
508 lockdep_assert_held(&dev_priv->pps_mutex);
509
510 /* try to find a pipe with this port selected */
6491ab27
VS		 511 /* first pick one where the panel is on */
512 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
513 vlv_pipe_has_pp_on);
514 /* didn't find one? pick one where vdd is on */
515 if (intel_dp->pps_pipe == INVALID_PIPE)
516 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
517 vlv_pipe_has_vdd_on);
518 /* didn't find one? pick one with just the correct port */
519 if (intel_dp->pps_pipe == INVALID_PIPE)
520 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
521 vlv_pipe_any);
a4a5d2f8
VS		 522
523 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
524 if (intel_dp->pps_pipe == INVALID_PIPE) {
525 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
526 port_name(port));
527 return;
bf13e81b
JN		 528 }
529
a4a5d2f8
VS		 530 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
531 port_name(port), pipe_name(intel_dp->pps_pipe));
532
36b5f425
VS		 533 intel_dp_init_panel_power_sequencer(dev, intel_dp);
534 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 535}
536
773538e8
VS		 537void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
538{
539 struct drm_device *dev = dev_priv->dev;
540 struct intel_encoder *encoder;
541
542 if (WARN_ON(!IS_VALLEYVIEW(dev)))
543 return;
544
545 /*
546 * We can't grab pps_mutex here due to deadlock with power_domain
547 * mutex when power_domain functions are called while holding pps_mutex.
548 * That also means that in order to use pps_pipe the code needs to
549 * hold both a power domain reference and pps_mutex, and the power domain
550 * reference get/put must be done while _not_ holding pps_mutex.
551 * pps_{lock,unlock}() do these steps in the correct order, so one
552 * should use them always.
553 */
554
555 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
556 struct intel_dp *intel_dp;
557
558 if (encoder->type != INTEL_OUTPUT_EDP)
559 continue;
560
561 intel_dp = enc_to_intel_dp(&encoder->base);
562 intel_dp->pps_pipe = INVALID_PIPE;
563 }
bf13e81b
JN		 564}
565
566static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
567{
568 struct drm_device *dev = intel_dp_to_dev(intel_dp);
569
b0a08bec
VK		 570 if (IS_BROXTON(dev))
571 return BXT_PP_CONTROL(0);
572 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 573 return PCH_PP_CONTROL;
574 else
575 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
576}
577
578static u32 _pp_stat_reg(struct intel_dp *intel_dp)
579{
580 struct drm_device *dev = intel_dp_to_dev(intel_dp);
581
b0a08bec
VK		 582 if (IS_BROXTON(dev))
583 return BXT_PP_STATUS(0);
584 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 585 return PCH_PP_STATUS;
586 else
587 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
588}
589
01527b31
CT		 590/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
591 This function only applicable when panel PM state is not to be tracked */
592static int edp_notify_handler(struct notifier_block *this, unsigned long code,
593 void *unused)
594{
595 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
596 edp_notifier);
597 struct drm_device *dev = intel_dp_to_dev(intel_dp);
598 struct drm_i915_private *dev_priv = dev->dev_private;
599 u32 pp_div;
600 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 601
602 if (!is_edp(intel_dp) || code != SYS_RESTART)
603 return 0;
604
773538e8 605 pps_lock(intel_dp);
e39b999a 606
01527b31 607 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 608 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
609
01527b31
CT		 610 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
611 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
612 pp_div = I915_READ(pp_div_reg);
613 pp_div &= PP_REFERENCE_DIVIDER_MASK;
614
615 /* 0x1F write to PP_DIV_REG sets max cycle delay */
616 I915_WRITE(pp_div_reg, pp_div | 0x1F);
617 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
618 msleep(intel_dp->panel_power_cycle_delay);
619 }
620
773538e8 621 pps_unlock(intel_dp);
e39b999a 622
01527b31
CT		 623 return 0;
624}
625
4be73780 626static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 627{
30add22d 628 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 629 struct drm_i915_private *dev_priv = dev->dev_private;
630
e39b999a
VS		 631 lockdep_assert_held(&dev_priv->pps_mutex);
632
9a42356b
VS		 633 if (IS_VALLEYVIEW(dev) &&
634 intel_dp->pps_pipe == INVALID_PIPE)
635 return false;
636
bf13e81b 637 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 638}
639
4be73780 640static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 641{
30add22d 642 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 643 struct drm_i915_private *dev_priv = dev->dev_private;
644
e39b999a
VS		 645 lockdep_assert_held(&dev_priv->pps_mutex);
646
9a42356b
VS		 647 if (IS_VALLEYVIEW(dev) &&
648 intel_dp->pps_pipe == INVALID_PIPE)
649 return false;
650
773538e8 651 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 652}
653
9b984dae
KP		 654static void
655intel_dp_check_edp(struct intel_dp *intel_dp)
656{
30add22d 657 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 658 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 659
9b984dae
KP		 660 if (!is_edp(intel_dp))
661 return;
453c5420 662
4be73780 663 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 664 WARN(1, "eDP powered off while attempting aux channel communication.\n");
665 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 666 I915_READ(_pp_stat_reg(intel_dp)),
667 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 668 }
669}
670
9ee32fea
DV		 671static uint32_t
672intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
673{
674 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
675 struct drm_device *dev = intel_dig_port->base.base.dev;
676 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 677 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 678 uint32_t status;
679 bool done;
680
ef04f00d 681#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 682 if (has_aux_irq)
b18ac466 683 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 684 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 685 else
686 done = wait_for_atomic(C, 10) == 0;
687 if (!done)
688 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
689 has_aux_irq);
690#undef C
691
692 return status;
693}
694
ec5b01dd 695static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 696{
174edf1f
PZ		 697 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
698 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 699
ec5b01dd
DL		 700 /*
701 * The clock divider is based off the hrawclk, and would like to run at
702 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 703 */
ec5b01dd
DL		 704 return index ? 0 : intel_hrawclk(dev) / 2;
705}
706
707static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
708{
709 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
710 struct drm_device *dev = intel_dig_port->base.base.dev;
469d4b2a 711 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd
DL		 712
713 if (index)
714 return 0;
715
716 if (intel_dig_port->port == PORT_A) {
05024da3
VS		 717 return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);
718
ec5b01dd
DL		 719 } else {
720 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
721 }
722}
723
724static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
725{
726 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
727 struct drm_device *dev = intel_dig_port->base.base.dev;
728 struct drm_i915_private *dev_priv = dev->dev_private;
729
730 if (intel_dig_port->port == PORT_A) {
731 if (index)
732 return 0;
05024da3 733 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
2c55c336
JN		 734 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
735 /* Workaround for non-ULT HSW */
bc86625a
CW		 736 switch (index) {
737 case 0: return 63;
738 case 1: return 72;
739 default: return 0;
740 }
ec5b01dd 741 } else {
bc86625a 742 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 743 }
b84a1cf8
RV		 744}
745
ec5b01dd
DL		 746static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
747{
748 return index ? 0 : 100;
749}
750
b6b5e383
DL		 751static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
752{
753 /*
754 * SKL doesn't need us to program the AUX clock divider (Hardware will
755 * derive the clock from CDCLK automatically). We still implement the
756 * get_aux_clock_divider vfunc to plug-in into the existing code.
757 */
758 return index ? 0 : 1;
759}
760
5ed12a19
DL		 761static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
762 bool has_aux_irq,
763 int send_bytes,
764 uint32_t aux_clock_divider)
765{
766 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
767 struct drm_device *dev = intel_dig_port->base.base.dev;
768 uint32_t precharge, timeout;
769
770 if (IS_GEN6(dev))
771 precharge = 3;
772 else
773 precharge = 5;
774
775 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
776 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
777 else
778 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
779
780 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 781 DP_AUX_CH_CTL_DONE |
5ed12a19 782 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 783 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 784 timeout |
788d4433 785 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 786 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
787 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 788 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 789}
790
b9ca5fad
DL		 791static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
792 bool has_aux_irq,
793 int send_bytes,
794 uint32_t unused)
795{
796 return DP_AUX_CH_CTL_SEND_BUSY |
797 DP_AUX_CH_CTL_DONE |
798 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
799 DP_AUX_CH_CTL_TIME_OUT_ERROR |
800 DP_AUX_CH_CTL_TIME_OUT_1600us |
801 DP_AUX_CH_CTL_RECEIVE_ERROR |
802 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
803 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
804}
805
b84a1cf8
RV		 806static int
807intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 808 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 809 uint8_t *recv, int recv_size)
810{
811 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
812 struct drm_device *dev = intel_dig_port->base.base.dev;
813 struct drm_i915_private *dev_priv = dev->dev_private;
814 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
815 uint32_t ch_data = ch_ctl + 4;
bc86625a 816 uint32_t aux_clock_divider;
b84a1cf8
RV		 817 int i, ret, recv_bytes;
818 uint32_t status;
5ed12a19 819 int try, clock = 0;
4e6b788c 820 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 821 bool vdd;
822
773538e8 823 pps_lock(intel_dp);
e39b999a 824
72c3500a
VS		 825 /*
826 * We will be called with VDD already enabled for dpcd/edid/oui reads.
827 * In such cases we want to leave VDD enabled and it's up to upper layers
828 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
829 * ourselves.
830 */
1e0560e0 831 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 832
833 /* dp aux is extremely sensitive to irq latency, hence request the
834 * lowest possible wakeup latency and so prevent the cpu from going into
835 * deep sleep states.
836 */
837 pm_qos_update_request(&dev_priv->pm_qos, 0);
838
839 intel_dp_check_edp(intel_dp);
5eb08b69 840
c67a470b
PZ		 841 intel_aux_display_runtime_get(dev_priv);
842
11bee43e
JB		 843 /* Try to wait for any previous AUX channel activity */
844 for (try = 0; try < 3; try++) {
ef04f00d 845 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 846 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
847 break;
848 msleep(1);
849 }
850
851 if (try == 3) {
852 WARN(1, "dp_aux_ch not started status 0x%08x\n",
853 I915_READ(ch_ctl));
9ee32fea
DV		 854 ret = -EBUSY;
855 goto out;
4f7f7b7e
CW		 856 }
857
46a5ae9f
PZ		 858 /* Only 5 data registers! */
859 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
860 ret = -E2BIG;
861 goto out;
862 }
863
ec5b01dd 864 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 865 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
866 has_aux_irq,
867 send_bytes,
868 aux_clock_divider);
5ed12a19 869
bc86625a
CW		 870 /* Must try at least 3 times according to DP spec */
871 for (try = 0; try < 5; try++) {
872 /* Load the send data into the aux channel data registers */
873 for (i = 0; i < send_bytes; i += 4)
874 I915_WRITE(ch_data + i,
a4f1289e
RV		 875 intel_dp_pack_aux(send + i,
876 send_bytes - i));
bc86625a
CW		 877
878 /* Send the command and wait for it to complete */
5ed12a19 879 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 880
881 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
882
883 /* Clear done status and any errors */
884 I915_WRITE(ch_ctl,
885 status |
886 DP_AUX_CH_CTL_DONE |
887 DP_AUX_CH_CTL_TIME_OUT_ERROR |
888 DP_AUX_CH_CTL_RECEIVE_ERROR);
889
74ebf294 890 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 891 continue;
74ebf294
TP		 892
893 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
894 * 400us delay required for errors and timeouts
895 * Timeout errors from the HW already meet this
896 * requirement so skip to next iteration
897 */
898 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
899 usleep_range(400, 500);
bc86625a 900 continue;
74ebf294 901 }
bc86625a 902 if (status & DP_AUX_CH_CTL_DONE)
e058c945 903 goto done;
bc86625a 904 }
a4fc5ed6
KP		 905 }
906
a4fc5ed6 907 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 908 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 909 ret = -EBUSY;
910 goto out;
a4fc5ed6
KP		 911 }
912
e058c945 913done:
a4fc5ed6
KP		 914 /* Check for timeout or receive error.
915 * Timeouts occur when the sink is not connected
916 */
a5b3da54 917 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 918 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 919 ret = -EIO;
920 goto out;
a5b3da54 921 }
1ae8c0a5
KP		 922
923 /* Timeouts occur when the device isn't connected, so they're
924 * "normal" -- don't fill the kernel log with these */
a5b3da54 925 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 926 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 927 ret = -ETIMEDOUT;
928 goto out;
a4fc5ed6
KP		 929 }
930
931 /* Unload any bytes sent back from the other side */
932 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
933 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 934 if (recv_bytes > recv_size)
935 recv_bytes = recv_size;
0206e353 936
4f7f7b7e 937 for (i = 0; i < recv_bytes; i += 4)
a4f1289e
RV		 938 intel_dp_unpack_aux(I915_READ(ch_data + i),
939 recv + i, recv_bytes - i);
a4fc5ed6 940
9ee32fea
DV		 941 ret = recv_bytes;
942out:
943 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 944 intel_aux_display_runtime_put(dev_priv);
9ee32fea 945
884f19e9
JN		 946 if (vdd)
947 edp_panel_vdd_off(intel_dp, false);
948
773538e8 949 pps_unlock(intel_dp);
e39b999a 950
9ee32fea 951 return ret;
a4fc5ed6
KP		 952}
953
a6c8aff0
JN		 954#define BARE_ADDRESS_SIZE 3
955#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 956static ssize_t
957intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 958{
9d1a1031
JN		 959 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
960 uint8_t txbuf[20], rxbuf[20];
961 size_t txsize, rxsize;
a4fc5ed6 962 int ret;
a4fc5ed6 963
d2d9cbbd
VS		 964 txbuf[0] = (msg->request << 4) |
965 ((msg->address >> 16) & 0xf);
966 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 967 txbuf[2] = msg->address & 0xff;
968 txbuf[3] = msg->size - 1;
46a5ae9f 969
9d1a1031
JN		 970 switch (msg->request & ~DP_AUX_I2C_MOT) {
971 case DP_AUX_NATIVE_WRITE:
972 case DP_AUX_I2C_WRITE:
a6c8aff0 973 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 974 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 975
9d1a1031
JN		 976 if (WARN_ON(txsize > 20))
977 return -E2BIG;
a4fc5ed6 978
9d1a1031 979 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 980
9d1a1031
JN		 981 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
982 if (ret > 0) {
983 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 984
a1ddefd8
JN		 985 if (ret > 1) {
986 /* Number of bytes written in a short write. */
987 ret = clamp_t(int, rxbuf[1], 0, msg->size);
988 } else {
989 /* Return payload size. */
990 ret = msg->size;
991 }
9d1a1031
JN		 992 }
993 break;
46a5ae9f 994
9d1a1031
JN		 995 case DP_AUX_NATIVE_READ:
996 case DP_AUX_I2C_READ:
a6c8aff0 997 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 998 rxsize = msg->size + 1;
a4fc5ed6 999
9d1a1031
JN		 1000 if (WARN_ON(rxsize > 20))
1001 return -E2BIG;
a4fc5ed6 1002
9d1a1031
JN		 1003 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1004 if (ret > 0) {
1005 msg->reply = rxbuf[0] >> 4;
1006 /*
1007 * Assume happy day, and copy the data. The caller is
1008 * expected to check msg->reply before touching it.
1009 *
1010 * Return payload size.
1011 */
1012 ret--;
1013 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1014 }
9d1a1031
JN		 1015 break;
1016
1017 default:
1018 ret = -EINVAL;
1019 break;
a4fc5ed6 1020 }
f51a44b9 1021
9d1a1031 1022 return ret;
a4fc5ed6
KP		 1023}
1024
9d1a1031
JN		 1025static void
1026intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1027{
1028 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 1029 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1030 enum port port = intel_dig_port->port;
0b99836f 1031 const char *name = NULL;
ab2c0672
DA		 1032 int ret;
1033
33ad6626
JN		 1034 switch (port) {
1035 case PORT_A:
1036 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 1037 name = "DPDDC-A";
ab2c0672 1038 break;
33ad6626
JN		 1039 case PORT_B:
1040 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1041 name = "DPDDC-B";
ab2c0672 1042 break;
33ad6626
JN		 1043 case PORT_C:
1044 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1045 name = "DPDDC-C";
ab2c0672 1046 break;
33ad6626
JN		 1047 case PORT_D:
1048 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1049 name = "DPDDC-D";
33ad6626
JN		 1050 break;
1051 default:
1052 BUG();
ab2c0672
DA		 1053 }
1054
1b1aad75
DL		 1055 /*
1056 * The AUX_CTL register is usually DP_CTL + 0x10.
1057 *
1058 * On Haswell and Broadwell though:
1059 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1060 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1061 *
1062 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1063 */
1064 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1065 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1066
0b99836f 1067 intel_dp->aux.name = name;
9d1a1031
JN		 1068 intel_dp->aux.dev = dev->dev;
1069 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1070
0b99836f
JN		 1071 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1072 connector->base.kdev->kobj.name);
8316f337 1073
4f71d0cb 1074 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1075 if (ret < 0) {
4f71d0cb 1076 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1077 name, ret);
1078 return;
ab2c0672 1079 }
8a5e6aeb 1080
0b99836f
JN		 1081 ret = sysfs_create_link(&connector->base.kdev->kobj,
1082 &intel_dp->aux.ddc.dev.kobj,
1083 intel_dp->aux.ddc.dev.kobj.name);
1084 if (ret < 0) {
1085 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1086 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1087 }
a4fc5ed6
KP		 1088}
1089
80f65de3
ID		 1090static void
1091intel_dp_connector_unregister(struct intel_connector *intel_connector)
1092{
1093 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1094
0e32b39c
DA		 1095 if (!intel_connector->mst_port)
1096 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1097 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1098 intel_connector_unregister(intel_connector);
1099}
1100
5416d871 1101static void
c3346ef6 1102skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
5416d871
DL		 1103{
1104 u32 ctrl1;
1105
dd3cd74a
ACO		 1106 memset(&pipe_config->dpll_hw_state, 0,
1107 sizeof(pipe_config->dpll_hw_state));
1108
5416d871
DL		 1109 pipe_config->ddi_pll_sel = SKL_DPLL0;
1110 pipe_config->dpll_hw_state.cfgcr1 = 0;
1111 pipe_config->dpll_hw_state.cfgcr2 = 0;
1112
1113 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
c3346ef6
SJ		 1114 switch (link_clock / 2) {
1115 case 81000:
71cd8423 1116 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5416d871
DL		 1117 SKL_DPLL0);
1118 break;
c3346ef6 1119 case 135000:
71cd8423 1120 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
5416d871
DL		 1121 SKL_DPLL0);
1122 break;
c3346ef6 1123 case 270000:
71cd8423 1124 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
5416d871
DL		 1125 SKL_DPLL0);
1126 break;
c3346ef6 1127 case 162000:
71cd8423 1128 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
c3346ef6
SJ		 1129 SKL_DPLL0);
1130 break;
1131 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1132 results in CDCLK change. Need to handle the change of CDCLK by
1133 disabling pipes and re-enabling them */
1134 case 108000:
71cd8423 1135 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
c3346ef6
SJ		 1136 SKL_DPLL0);
1137 break;
1138 case 216000:
71cd8423 1139 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
c3346ef6
SJ		 1140 SKL_DPLL0);
1141 break;
1142
5416d871
DL		 1143 }
1144 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1145}
1146
0e50338c 1147static void
5cec258b 1148hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
0e50338c 1149{
ee46f3c7
ACO		 1150 memset(&pipe_config->dpll_hw_state, 0,
1151 sizeof(pipe_config->dpll_hw_state));
1152
0e50338c
DV		 1153 switch (link_bw) {
1154 case DP_LINK_BW_1_62:
1155 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1156 break;
1157 case DP_LINK_BW_2_7:
1158 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1159 break;
1160 case DP_LINK_BW_5_4:
1161 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1162 break;
1163 }
1164}
1165
fc0f8e25 1166static int
12f6a2e2 1167intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1168{
94ca719e
VS		 1169 if (intel_dp->num_sink_rates) {
1170 *sink_rates = intel_dp->sink_rates;
1171 return intel_dp->num_sink_rates;
fc0f8e25 1172 }
12f6a2e2
VS		 1173
1174 *sink_rates = default_rates;
1175
1176 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1177}
1178
a8f3ef61 1179static int
1db10e28 1180intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
a8f3ef61 1181{
64987fc5
SJ		 1182 if (IS_BROXTON(dev)) {
1183 *source_rates = bxt_rates;
1184 return ARRAY_SIZE(bxt_rates);
1185 } else if (IS_SKYLAKE(dev)) {
637a9c63
SJ		 1186 *source_rates = skl_rates;
1187 return ARRAY_SIZE(skl_rates);
fe51bfb9
VS		 1188 } else if (IS_CHERRYVIEW(dev)) {
1189 *source_rates = chv_rates;
1190 return ARRAY_SIZE(chv_rates);
a8f3ef61 1191 }
636280ba
VS		 1192
1193 *source_rates = default_rates;
1194
1db10e28
VS		 1195 if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
1196 /* WaDisableHBR2:skl */
1197 return (DP_LINK_BW_2_7 >> 3) + 1;
1198 else if (INTEL_INFO(dev)->gen >= 8 ||
1199 (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
1200 return (DP_LINK_BW_5_4 >> 3) + 1;
1201 else
1202 return (DP_LINK_BW_2_7 >> 3) + 1;
a8f3ef61
SJ		 1203}
1204
c6bb3538
DV		 1205static void
1206intel_dp_set_clock(struct intel_encoder *encoder,
5cec258b 1207 struct intel_crtc_state *pipe_config, int link_bw)
c6bb3538
DV		 1208{
1209 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1210 const struct dp_link_dpll *divisor = NULL;
1211 int i, count = 0;
c6bb3538
DV		 1212
1213 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1214 divisor = gen4_dpll;
1215 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1216 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1217 divisor = pch_dpll;
1218 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1219 } else if (IS_CHERRYVIEW(dev)) {
1220 divisor = chv_dpll;
1221 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1222 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1223 divisor = vlv_dpll;
1224 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1225 }
9dd4ffdf
CML		 1226
1227 if (divisor && count) {
1228 for (i = 0; i < count; i++) {
1229 if (link_bw == divisor[i].link_bw) {
1230 pipe_config->dpll = divisor[i].dpll;
1231 pipe_config->clock_set = true;
1232 break;
1233 }
1234 }
c6bb3538
DV		 1235 }
1236}
1237
2ecae76a
VS		 1238static int intersect_rates(const int *source_rates, int source_len,
1239 const int *sink_rates, int sink_len,
94ca719e 1240 int *common_rates)
a8f3ef61
SJ		 1241{
1242 int i = 0, j = 0, k = 0;
1243
a8f3ef61
SJ		 1244 while (i < source_len && j < sink_len) {
1245 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1246 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1247 return k;
94ca719e 1248 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1249 ++k;
1250 ++i;
1251 ++j;
1252 } else if (source_rates[i] < sink_rates[j]) {
1253 ++i;
1254 } else {
1255 ++j;
1256 }
1257 }
1258 return k;
1259}
1260
94ca719e
VS		 1261static int intel_dp_common_rates(struct intel_dp *intel_dp,
1262 int *common_rates)
2ecae76a
VS		 1263{
1264 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1265 const int *source_rates, *sink_rates;
1266 int source_len, sink_len;
1267
1268 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1269 source_len = intel_dp_source_rates(dev, &source_rates);
1270
1271 return intersect_rates(source_rates, source_len,
1272 sink_rates, sink_len,
94ca719e 1273 common_rates);
2ecae76a
VS		 1274}
1275
0336400e
VS		 1276static void snprintf_int_array(char *str, size_t len,
1277 const int *array, int nelem)
1278{
1279 int i;
1280
1281 str[0] = '\0';
1282
1283 for (i = 0; i < nelem; i++) {
b2f505be 1284 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1285 if (r >= len)
1286 return;
1287 str += r;
1288 len -= r;
1289 }
1290}
1291
1292static void intel_dp_print_rates(struct intel_dp *intel_dp)
1293{
1294 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1295 const int *source_rates, *sink_rates;
94ca719e
VS		 1296 int source_len, sink_len, common_len;
1297 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1298 char str[128]; /* FIXME: too big for stack? */
1299
1300 if ((drm_debug & DRM_UT_KMS) == 0)
1301 return;
1302
1303 source_len = intel_dp_source_rates(dev, &source_rates);
1304 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1305 DRM_DEBUG_KMS("source rates: %s\n", str);
1306
1307 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1308 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1309 DRM_DEBUG_KMS("sink rates: %s\n", str);
1310
94ca719e
VS		 1311 common_len = intel_dp_common_rates(intel_dp, common_rates);
1312 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1313 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1314}
1315
f4896f15 1316static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1317{
1318 int i = 0;
1319
1320 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1321 if (find == rates[i])
1322 break;
1323
1324 return i;
1325}
1326
50fec21a
VS		 1327int
1328intel_dp_max_link_rate(struct intel_dp *intel_dp)
1329{
1330 int rates[DP_MAX_SUPPORTED_RATES] = {};
1331 int len;
1332
94ca719e 1333 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1334 if (WARN_ON(len <= 0))
1335 return 162000;
1336
1337 return rates[rate_to_index(0, rates) - 1];
1338}
1339
ed4e9c1d
VS		 1340int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1341{
94ca719e 1342 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1343}
1344
00c09d70 1345bool
5bfe2ac0 1346intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1347 struct intel_crtc_state *pipe_config)
a4fc5ed6 1348{
5bfe2ac0 1349 struct drm_device *dev = encoder->base.dev;
36008365 1350 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1351 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1352 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1353 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1354 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1355 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1356 int lane_count, clock;
56071a20 1357 int min_lane_count = 1;
eeb6324d 1358 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1359 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1360 int min_clock = 0;
a8f3ef61 1361 int max_clock;
083f9560 1362 int bpp, mode_rate;
ff9a6750 1363 int link_avail, link_clock;
94ca719e
VS		 1364 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1365 int common_len;
a8f3ef61 1366
94ca719e 1367 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1368
1369 /* No common link rates between source and sink */
94ca719e 1370 WARN_ON(common_len <= 0);
a8f3ef61 1371
94ca719e 1372 max_clock = common_len - 1;
a4fc5ed6 1373
bc7d38a4 1374 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1375 pipe_config->has_pch_encoder = true;
1376
03afc4a2 1377 pipe_config->has_dp_encoder = true;
f769cd24 1378 pipe_config->has_drrs = false;
9fcb1704 1379 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1380
dd06f90e
JN		 1381 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1382 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1383 adjusted_mode);
a1b2278e
CK		 1384
1385 if (INTEL_INFO(dev)->gen >= 9) {
1386 int ret;
e435d6e5 1387 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1388 if (ret)
1389 return ret;
1390 }
1391
2dd24552
JB		 1392 if (!HAS_PCH_SPLIT(dev))
1393 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1394 intel_connector->panel.fitting_mode);
1395 else
b074cec8
JB		 1396 intel_pch_panel_fitting(intel_crtc, pipe_config,
1397 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1398 }
1399
cb1793ce 1400 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1401 return false;
1402
083f9560 1403 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1404 "max bw %d pixel clock %iKHz\n",
94ca719e 1405 max_lane_count, common_rates[max_clock],
241bfc38 1406 adjusted_mode->crtc_clock);
083f9560 1407
36008365
DV		 1408 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1409 * bpc in between. */
3e7ca985 1410 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1411 if (is_edp(intel_dp)) {
1412 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1413 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1414 dev_priv->vbt.edp_bpp);
1415 bpp = dev_priv->vbt.edp_bpp;
1416 }
1417
344c5bbc
JN		 1418 /*
1419 * Use the maximum clock and number of lanes the eDP panel
1420 * advertizes being capable of. The panels are generally
1421 * designed to support only a single clock and lane
1422 * configuration, and typically these values correspond to the
1423 * native resolution of the panel.
1424 */
1425 min_lane_count = max_lane_count;
1426 min_clock = max_clock;
7984211e 1427 }
657445fe 1428
36008365 1429 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1430 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1431 bpp);
36008365 1432
c6930992 1433 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1434 for (lane_count = min_lane_count;
1435 lane_count <= max_lane_count;
1436 lane_count <<= 1) {
1437
94ca719e 1438 link_clock = common_rates[clock];
36008365
DV		 1439 link_avail = intel_dp_max_data_rate(link_clock,
1440 lane_count);
1441
1442 if (mode_rate <= link_avail) {
1443 goto found;
1444 }
1445 }
1446 }
1447 }
c4867936 1448
36008365 1449 return false;
3685a8f3 1450
36008365 1451found:
55bc60db
VS		 1452 if (intel_dp->color_range_auto) {
1453 /*
1454 * See:
1455 * CEA-861-E - 5.1 Default Encoding Parameters
1456 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1457 */
18316c8c 1458 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1459 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1460 else
1461 intel_dp->color_range = 0;
1462 }
1463
3685a8f3 1464 if (intel_dp->color_range)
50f3b016 1465 pipe_config->limited_color_range = true;
a4fc5ed6 1466
36008365 1467 intel_dp->lane_count = lane_count;
a8f3ef61 1468
94ca719e 1469 if (intel_dp->num_sink_rates) {
bc27b7d3 1470 intel_dp->link_bw = 0;
a8f3ef61 1471 intel_dp->rate_select =
94ca719e 1472 intel_dp_rate_select(intel_dp, common_rates[clock]);
bc27b7d3
VS		 1473 } else {
1474 intel_dp->link_bw =
94ca719e 1475 drm_dp_link_rate_to_bw_code(common_rates[clock]);
bc27b7d3 1476 intel_dp->rate_select = 0;
a8f3ef61
SJ		 1477 }
1478
657445fe 1479 pipe_config->pipe_bpp = bpp;
94ca719e 1480 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1481
36008365
DV		 1482 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1483 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1484 pipe_config->port_clock, bpp);
36008365
DV		 1485 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1486 mode_rate, link_avail);
a4fc5ed6 1487
03afc4a2 1488 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1489 adjusted_mode->crtc_clock,
1490 pipe_config->port_clock,
03afc4a2 1491 &pipe_config->dp_m_n);
9d1a455b 1492
439d7ac0 1493 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1494 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1495 pipe_config->has_drrs = true;
439d7ac0
PB		 1496 intel_link_compute_m_n(bpp, lane_count,
1497 intel_connector->panel.downclock_mode->clock,
1498 pipe_config->port_clock,
1499 &pipe_config->dp_m2_n2);
1500 }
1501
5416d871 1502 if (IS_SKYLAKE(dev) && is_edp(intel_dp))
94ca719e 1503 skl_edp_set_pll_config(pipe_config, common_rates[clock]);
977bb38d
S		 1504 else if (IS_BROXTON(dev))
1505 /* handled in ddi */;
5416d871 1506 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1507 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1508 else
1509 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1510
03afc4a2 1511 return true;
a4fc5ed6
KP		 1512}
1513
7c62a164 1514static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1515{
7c62a164
DV		 1516 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1517 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1518 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1519 struct drm_i915_private *dev_priv = dev->dev_private;
1520 u32 dpa_ctl;
1521
6e3c9717
ACO		 1522 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1523 crtc->config->port_clock);
ea9b6006
DV		 1524 dpa_ctl = I915_READ(DP_A);
1525 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1526
6e3c9717 1527 if (crtc->config->port_clock == 162000) {
1ce17038
DV		 1528 /* For a long time we've carried around a ILK-DevA w/a for the
1529 * 160MHz clock. If we're really unlucky, it's still required.
1530 */
1531 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1532 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1533 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1534 } else {
1535 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1536 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1537 }
1ce17038 1538
ea9b6006
DV		 1539 I915_WRITE(DP_A, dpa_ctl);
1540
1541 POSTING_READ(DP_A);
1542 udelay(500);
1543}
1544
8ac33ed3 1545static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1546{
b934223d 1547 struct drm_device *dev = encoder->base.dev;
417e822d 1548 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1549 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1550 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1551 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
6e3c9717 1552 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1553
417e822d 1554 /*
1a2eb460 1555 * There are four kinds of DP registers:
417e822d
KP		 1556 *
1557 * IBX PCH
1a2eb460
KP		 1558 * SNB CPU
1559 * IVB CPU
417e822d
KP		 1560 * CPT PCH
1561 *
1562 * IBX PCH and CPU are the same for almost everything,
1563 * except that the CPU DP PLL is configured in this
1564 * register
1565 *
1566 * CPT PCH is quite different, having many bits moved
1567 * to the TRANS_DP_CTL register instead. That
1568 * configuration happens (oddly) in ironlake_pch_enable
1569 */
9c9e7927 1570
417e822d
KP		 1571 /* Preserve the BIOS-computed detected bit. This is
1572 * supposed to be read-only.
1573 */
1574 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1575
417e822d 1576 /* Handle DP bits in common between all three register formats */
417e822d 1577 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1578 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1579
6e3c9717 1580 if (crtc->config->has_audio)
ea5b213a 1581 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
247d89f6 1582
417e822d 1583 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1584
39e5fa88 1585 if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1586 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1587 intel_dp->DP |= DP_SYNC_HS_HIGH;
1588 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1589 intel_dp->DP |= DP_SYNC_VS_HIGH;
1590 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1591
6aba5b6c 1592 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1593 intel_dp->DP |= DP_ENHANCED_FRAMING;
1594
7c62a164 1595 intel_dp->DP |= crtc->pipe << 29;
39e5fa88 1596 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
e3ef4479
VS		 1597 u32 trans_dp;
1598
39e5fa88 1599 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1600
1601 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1602 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1603 trans_dp |= TRANS_DP_ENH_FRAMING;
1604 else
1605 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1606 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1607 } else {
b2634017 1608 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1609 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1610
1611 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1612 intel_dp->DP |= DP_SYNC_HS_HIGH;
1613 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1614 intel_dp->DP |= DP_SYNC_VS_HIGH;
1615 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1616
6aba5b6c 1617 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1618 intel_dp->DP |= DP_ENHANCED_FRAMING;
1619
39e5fa88 1620 if (IS_CHERRYVIEW(dev))
44f37d1f 1621 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1622 else if (crtc->pipe == PIPE_B)
1623 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1624 }
a4fc5ed6
KP		 1625}
1626
ffd6749d
PZ		 1627#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1628#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1629
1a5ef5b7
PZ		 1630#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1631#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1632
ffd6749d
PZ		 1633#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1634#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1635
4be73780 1636static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1637 u32 mask,
1638 u32 value)
bd943159 1639{
30add22d 1640 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1641 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1642 u32 pp_stat_reg, pp_ctrl_reg;
1643
e39b999a
VS		 1644 lockdep_assert_held(&dev_priv->pps_mutex);
1645
bf13e81b
JN		 1646 pp_stat_reg = _pp_stat_reg(intel_dp);
1647 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1648
99ea7127 1649 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1650 mask, value,
1651 I915_READ(pp_stat_reg),
1652 I915_READ(pp_ctrl_reg));
32ce697c 1653
453c5420 1654 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1655 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1656 I915_READ(pp_stat_reg),
1657 I915_READ(pp_ctrl_reg));
32ce697c 1658 }
54c136d4
CW		 1659
1660 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1661}
32ce697c 1662
4be73780 1663static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1664{
1665 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1666 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1667}
1668
4be73780 1669static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1670{
1671 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1672 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1673}
1674
4be73780 1675static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1676{
1677 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1678
1679 /* When we disable the VDD override bit last we have to do the manual
1680 * wait. */
1681 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1682 intel_dp->panel_power_cycle_delay);
1683
4be73780 1684 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1685}
1686
4be73780 1687static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1688{
1689 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1690 intel_dp->backlight_on_delay);
1691}
1692
4be73780 1693static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1694{
1695 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1696 intel_dp->backlight_off_delay);
1697}
99ea7127 1698
832dd3c1
KP		 1699/* Read the current pp_control value, unlocking the register if it
1700 * is locked
1701 */
1702
453c5420 1703static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1704{
453c5420
JB		 1705 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1706 struct drm_i915_private *dev_priv = dev->dev_private;
1707 u32 control;
832dd3c1 1708
e39b999a
VS		 1709 lockdep_assert_held(&dev_priv->pps_mutex);
1710
bf13e81b 1711 control = I915_READ(_pp_ctrl_reg(intel_dp));
b0a08bec
VK		 1712 if (!IS_BROXTON(dev)) {
1713 control &= ~PANEL_UNLOCK_MASK;
1714 control |= PANEL_UNLOCK_REGS;
1715 }
832dd3c1 1716 return control;
bd943159
KP		 1717}
1718
951468f3
VS		 1719/*
1720 * Must be paired with edp_panel_vdd_off().
1721 * Must hold pps_mutex around the whole on/off sequence.
1722 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1723 */
1e0560e0 1724static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1725{
30add22d 1726 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1727 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1728 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1729 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1730 enum intel_display_power_domain power_domain;
5d613501 1731 u32 pp;
453c5420 1732 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1733 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1734
e39b999a
VS		 1735 lockdep_assert_held(&dev_priv->pps_mutex);
1736
97af61f5 1737 if (!is_edp(intel_dp))
adddaaf4 1738 return false;
bd943159 1739
2c623c11 1740 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1741 intel_dp->want_panel_vdd = true;
99ea7127 1742
4be73780 1743 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1744 return need_to_disable;
b0665d57 1745
4e6e1a54
ID		 1746 power_domain = intel_display_port_power_domain(intel_encoder);
1747 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1748
3936fcf4
VS		 1749 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1750 port_name(intel_dig_port->port));
bd943159 1751
4be73780
DV		 1752 if (!edp_have_panel_power(intel_dp))
1753 wait_panel_power_cycle(intel_dp);
99ea7127 1754
453c5420 1755 pp = ironlake_get_pp_control(intel_dp);
5d613501 1756 pp |= EDP_FORCE_VDD;
ebf33b18 1757
bf13e81b
JN		 1758 pp_stat_reg = _pp_stat_reg(intel_dp);
1759 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1760
1761 I915_WRITE(pp_ctrl_reg, pp);
1762 POSTING_READ(pp_ctrl_reg);
1763 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1764 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1765 /*
1766 * If the panel wasn't on, delay before accessing aux channel
1767 */
4be73780 1768 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1769 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1770 port_name(intel_dig_port->port));
f01eca2e 1771 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1772 }
adddaaf4
JN		 1773
1774 return need_to_disable;
1775}
1776
951468f3
VS		 1777/*
1778 * Must be paired with intel_edp_panel_vdd_off() or
1779 * intel_edp_panel_off().
1780 * Nested calls to these functions are not allowed since
1781 * we drop the lock. Caller must use some higher level
1782 * locking to prevent nested calls from other threads.
1783 */
b80d6c78 1784void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1785{
c695b6b6 1786 bool vdd;
adddaaf4 1787
c695b6b6
VS		 1788 if (!is_edp(intel_dp))
1789 return;
1790
773538e8 1791 pps_lock(intel_dp);
c695b6b6 1792 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1793 pps_unlock(intel_dp);
c695b6b6 1794
e2c719b7 1795 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1796 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1797}
1798
4be73780 1799static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1800{
30add22d 1801 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1802 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1803 struct intel_digital_port *intel_dig_port =
1804 dp_to_dig_port(intel_dp);
1805 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1806 enum intel_display_power_domain power_domain;
5d613501 1807 u32 pp;
453c5420 1808 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1809
e39b999a 1810 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1811
15e899a0 1812 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1813
15e899a0 1814 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1815 return;
b0665d57 1816
3936fcf4
VS		 1817 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1818 port_name(intel_dig_port->port));
bd943159 1819
be2c9196
VS		 1820 pp = ironlake_get_pp_control(intel_dp);
1821 pp &= ~EDP_FORCE_VDD;
453c5420 1822
be2c9196
VS		 1823 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1824 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1825
be2c9196
VS		 1826 I915_WRITE(pp_ctrl_reg, pp);
1827 POSTING_READ(pp_ctrl_reg);
90791a5c 1828
be2c9196
VS		 1829 /* Make sure sequencer is idle before allowing subsequent activity */
1830 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1831 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1832
be2c9196
VS		 1833 if ((pp & POWER_TARGET_ON) == 0)
1834 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1835
be2c9196
VS		 1836 power_domain = intel_display_port_power_domain(intel_encoder);
1837 intel_display_power_put(dev_priv, power_domain);
bd943159 1838}
5d613501 1839
4be73780 1840static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1841{
1842 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1843 struct intel_dp, panel_vdd_work);
bd943159 1844
773538e8 1845 pps_lock(intel_dp);
15e899a0
VS		 1846 if (!intel_dp->want_panel_vdd)
1847 edp_panel_vdd_off_sync(intel_dp);
773538e8 1848 pps_unlock(intel_dp);
bd943159
KP		 1849}
1850
aba86890
ID		 1851static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1852{
1853 unsigned long delay;
1854
1855 /*
1856 * Queue the timer to fire a long time from now (relative to the power
1857 * down delay) to keep the panel power up across a sequence of
1858 * operations.
1859 */
1860 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1861 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1862}
1863
951468f3
VS		 1864/*
1865 * Must be paired with edp_panel_vdd_on().
1866 * Must hold pps_mutex around the whole on/off sequence.
1867 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1868 */
4be73780 1869static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1870{
e39b999a
VS		 1871 struct drm_i915_private *dev_priv =
1872 intel_dp_to_dev(intel_dp)->dev_private;
1873
1874 lockdep_assert_held(&dev_priv->pps_mutex);
1875
97af61f5
KP		 1876 if (!is_edp(intel_dp))
1877 return;
5d613501 1878
e2c719b7 1879 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1880 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1881
bd943159
KP		 1882 intel_dp->want_panel_vdd = false;
1883
aba86890 1884 if (sync)
4be73780 1885 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1886 else
1887 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1888}
1889
9f0fb5be 1890static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1891{
30add22d 1892 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1893 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1894 u32 pp;
453c5420 1895 u32 pp_ctrl_reg;
9934c132 1896
9f0fb5be
VS		 1897 lockdep_assert_held(&dev_priv->pps_mutex);
1898
97af61f5 1899 if (!is_edp(intel_dp))
bd943159 1900 return;
99ea7127 1901
3936fcf4
VS		 1902 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1903 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1904
e7a89ace
VS		 1905 if (WARN(edp_have_panel_power(intel_dp),
1906 "eDP port %c panel power already on\n",
1907 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1908 return;
9934c132 1909
4be73780 1910 wait_panel_power_cycle(intel_dp);
37c6c9b0 1911
bf13e81b 1912 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1913 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1914 if (IS_GEN5(dev)) {
1915 /* ILK workaround: disable reset around power sequence */
1916 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1917 I915_WRITE(pp_ctrl_reg, pp);
1918 POSTING_READ(pp_ctrl_reg);
05ce1a49 1919 }
37c6c9b0 1920
1c0ae80a 1921 pp |= POWER_TARGET_ON;
99ea7127
KP		 1922 if (!IS_GEN5(dev))
1923 pp |= PANEL_POWER_RESET;
1924
453c5420
JB		 1925 I915_WRITE(pp_ctrl_reg, pp);
1926 POSTING_READ(pp_ctrl_reg);
9934c132 1927
4be73780 1928 wait_panel_on(intel_dp);
dce56b3c 1929 intel_dp->last_power_on = jiffies;
9934c132 1930
05ce1a49
KP		 1931 if (IS_GEN5(dev)) {
1932 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1933 I915_WRITE(pp_ctrl_reg, pp);
1934 POSTING_READ(pp_ctrl_reg);
05ce1a49 1935 }
9f0fb5be 1936}
e39b999a 1937
9f0fb5be
VS		 1938void intel_edp_panel_on(struct intel_dp *intel_dp)
1939{
1940 if (!is_edp(intel_dp))
1941 return;
1942
1943 pps_lock(intel_dp);
1944 edp_panel_on(intel_dp);
773538e8 1945 pps_unlock(intel_dp);
9934c132
JB		 1946}
1947
9f0fb5be
VS		 1948
1949static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1950{
4e6e1a54
ID		 1951 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1952 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1953 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1954 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1955 enum intel_display_power_domain power_domain;
99ea7127 1956 u32 pp;
453c5420 1957 u32 pp_ctrl_reg;
9934c132 1958
9f0fb5be
VS		 1959 lockdep_assert_held(&dev_priv->pps_mutex);
1960
97af61f5
KP		 1961 if (!is_edp(intel_dp))
1962 return;
37c6c9b0 1963
3936fcf4
VS		 1964 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1965 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 1966
3936fcf4
VS		 1967 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1968 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 1969
453c5420 1970 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1971 /* We need to switch off panel power _and_ force vdd, for otherwise some
1972 * panels get very unhappy and cease to work. */
b3064154
PJ		 1973 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1974 EDP_BLC_ENABLE);
453c5420 1975
bf13e81b 1976 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1977
849e39f5
PZ		 1978 intel_dp->want_panel_vdd = false;
1979
453c5420
JB		 1980 I915_WRITE(pp_ctrl_reg, pp);
1981 POSTING_READ(pp_ctrl_reg);
9934c132 1982
dce56b3c 1983 intel_dp->last_power_cycle = jiffies;
4be73780 1984 wait_panel_off(intel_dp);
849e39f5
PZ		 1985
1986 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1987 power_domain = intel_display_port_power_domain(intel_encoder);
1988 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1989}
e39b999a 1990
9f0fb5be
VS		 1991void intel_edp_panel_off(struct intel_dp *intel_dp)
1992{
1993 if (!is_edp(intel_dp))
1994 return;
e39b999a 1995
9f0fb5be
VS		 1996 pps_lock(intel_dp);
1997 edp_panel_off(intel_dp);
773538e8 1998 pps_unlock(intel_dp);
9934c132
JB		 1999}
2000
1250d107
JN		 2001/* Enable backlight in the panel power control. */
2002static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2003{
da63a9f2
PZ		 2004 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2005 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 2006 struct drm_i915_private *dev_priv = dev->dev_private;
2007 u32 pp;
453c5420 2008 u32 pp_ctrl_reg;
32f9d658 2009
01cb9ea6
JB		 2010 /*
2011 * If we enable the backlight right away following a panel power
2012 * on, we may see slight flicker as the panel syncs with the eDP
2013 * link. So delay a bit to make sure the image is solid before
2014 * allowing it to appear.
2015 */
4be73780 2016 wait_backlight_on(intel_dp);
e39b999a 2017
773538e8 2018 pps_lock(intel_dp);
e39b999a 2019
453c5420 2020 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2021 pp |= EDP_BLC_ENABLE;
453c5420 2022
bf13e81b 2023 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2024
2025 I915_WRITE(pp_ctrl_reg, pp);
2026 POSTING_READ(pp_ctrl_reg);
e39b999a 2027
773538e8 2028 pps_unlock(intel_dp);
32f9d658
ZW		 2029}
2030
1250d107
JN		 2031/* Enable backlight PWM and backlight PP control. */
2032void intel_edp_backlight_on(struct intel_dp *intel_dp)
2033{
2034 if (!is_edp(intel_dp))
2035 return;
2036
2037 DRM_DEBUG_KMS("\n");
2038
2039 intel_panel_enable_backlight(intel_dp->attached_connector);
2040 _intel_edp_backlight_on(intel_dp);
2041}
2042
2043/* Disable backlight in the panel power control. */
2044static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2045{
30add22d 2046 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 2047 struct drm_i915_private *dev_priv = dev->dev_private;
2048 u32 pp;
453c5420 2049 u32 pp_ctrl_reg;
32f9d658 2050
f01eca2e
KP		 2051 if (!is_edp(intel_dp))
2052 return;
2053
773538e8 2054 pps_lock(intel_dp);
e39b999a 2055
453c5420 2056 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2057 pp &= ~EDP_BLC_ENABLE;
453c5420 2058
bf13e81b 2059 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2060
2061 I915_WRITE(pp_ctrl_reg, pp);
2062 POSTING_READ(pp_ctrl_reg);
f7d2323c 2063
773538e8 2064 pps_unlock(intel_dp);
e39b999a
VS		 2065
2066 intel_dp->last_backlight_off = jiffies;
f7d2323c 2067 edp_wait_backlight_off(intel_dp);
1250d107 2068}
f7d2323c 2069
1250d107
JN		 2070/* Disable backlight PP control and backlight PWM. */
2071void intel_edp_backlight_off(struct intel_dp *intel_dp)
2072{
2073 if (!is_edp(intel_dp))
2074 return;
2075
2076 DRM_DEBUG_KMS("\n");
f7d2323c 2077
1250d107 2078 _intel_edp_backlight_off(intel_dp);
f7d2323c 2079 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2080}
a4fc5ed6 2081
73580fb7
JN		 2082/*
2083 * Hook for controlling the panel power control backlight through the bl_power
2084 * sysfs attribute. Take care to handle multiple calls.
2085 */
2086static void intel_edp_backlight_power(struct intel_connector *connector,
2087 bool enable)
2088{
2089 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2090 bool is_enabled;
2091
773538e8 2092 pps_lock(intel_dp);
e39b999a 2093 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2094 pps_unlock(intel_dp);
73580fb7
JN		 2095
2096 if (is_enabled == enable)
2097 return;
2098
23ba9373
JN		 2099 DRM_DEBUG_KMS("panel power control backlight %s\n",
2100 enable ? "enable" : "disable");
73580fb7
JN		 2101
2102 if (enable)
2103 _intel_edp_backlight_on(intel_dp);
2104 else
2105 _intel_edp_backlight_off(intel_dp);
2106}
2107
2bd2ad64 2108static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2109{
da63a9f2
PZ		 2110 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2111 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2112 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2113 struct drm_i915_private *dev_priv = dev->dev_private;
2114 u32 dpa_ctl;
2115
2bd2ad64
DV		 2116 assert_pipe_disabled(dev_priv,
2117 to_intel_crtc(crtc)->pipe);
2118
d240f20f
JB		 2119 DRM_DEBUG_KMS("\n");
2120 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2121 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
2122 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2123
2124 /* We don't adjust intel_dp->DP while tearing down the link, to
2125 * facilitate link retraining (e.g. after hotplug). Hence clear all
2126 * enable bits here to ensure that we don't enable too much. */
2127 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
2128 intel_dp->DP |= DP_PLL_ENABLE;
2129 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2130 POSTING_READ(DP_A);
2131 udelay(200);
d240f20f
JB		 2132}
2133
2bd2ad64 2134static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2135{
da63a9f2
PZ		 2136 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2137 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2138 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2139 struct drm_i915_private *dev_priv = dev->dev_private;
2140 u32 dpa_ctl;
2141
2bd2ad64
DV		 2142 assert_pipe_disabled(dev_priv,
2143 to_intel_crtc(crtc)->pipe);
2144
d240f20f 2145 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2146 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
2147 "dp pll off, should be on\n");
2148 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2149
2150 /* We can't rely on the value tracked for the DP register in
2151 * intel_dp->DP because link_down must not change that (otherwise link
2152 * re-training will fail. */
298b0b39 2153 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 2154 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 2155 POSTING_READ(DP_A);
d240f20f
JB		 2156 udelay(200);
2157}
2158
c7ad3810 2159/* If the sink supports it, try to set the power state appropriately */
c19b0669 2160void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2161{
2162 int ret, i;
2163
2164 /* Should have a valid DPCD by this point */
2165 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2166 return;
2167
2168 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2169 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2170 DP_SET_POWER_D3);
c7ad3810
JB		 2171 } else {
2172 /*
2173 * When turning on, we need to retry for 1ms to give the sink
2174 * time to wake up.
2175 */
2176 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2177 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2178 DP_SET_POWER_D0);
c7ad3810
JB		 2179 if (ret == 1)
2180 break;
2181 msleep(1);
2182 }
2183 }
f9cac721
JN		 2184
2185 if (ret != 1)
2186 DRM_DEBUG_KMS("failed to %s sink power state\n",
2187 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2188}
2189
19d8fe15
DV		 2190static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2191 enum pipe *pipe)
d240f20f 2192{
19d8fe15 2193 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2194 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2195 struct drm_device *dev = encoder->base.dev;
2196 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2197 enum intel_display_power_domain power_domain;
2198 u32 tmp;
2199
2200 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 2201 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 2202 return false;
2203
2204 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2205
2206 if (!(tmp & DP_PORT_EN))
2207 return false;
2208
39e5fa88 2209 if (IS_GEN7(dev) && port == PORT_A) {
19d8fe15 2210 *pipe = PORT_TO_PIPE_CPT(tmp);
39e5fa88 2211 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
adc289d7 2212 enum pipe p;
19d8fe15 2213
adc289d7
VS		 2214 for_each_pipe(dev_priv, p) {
2215 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2216 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2217 *pipe = p;
19d8fe15
DV		 2218 return true;
2219 }
2220 }
19d8fe15 2221
4a0833ec
DV		 2222 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2223 intel_dp->output_reg);
39e5fa88
VS		 2224 } else if (IS_CHERRYVIEW(dev)) {
2225 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2226 } else {
2227 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2228 }
d240f20f 2229
19d8fe15
DV		 2230 return true;
2231}
d240f20f 2232
045ac3b5 2233static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2234 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2235{
2236 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2237 u32 tmp, flags = 0;
63000ef6
XZ		 2238 struct drm_device *dev = encoder->base.dev;
2239 struct drm_i915_private *dev_priv = dev->dev_private;
2240 enum port port = dp_to_dig_port(intel_dp)->port;
2241 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 2242 int dotclock;
045ac3b5 2243
9ed109a7 2244 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2245
2246 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2247
39e5fa88
VS		 2248 if (HAS_PCH_CPT(dev) && port != PORT_A) {
2249 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2250 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2251 flags |= DRM_MODE_FLAG_PHSYNC;
2252 else
2253 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2254
39e5fa88 2255 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2256 flags |= DRM_MODE_FLAG_PVSYNC;
2257 else
2258 flags |= DRM_MODE_FLAG_NVSYNC;
2259 } else {
39e5fa88 2260 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2261 flags |= DRM_MODE_FLAG_PHSYNC;
2262 else
2263 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2264
39e5fa88 2265 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2266 flags |= DRM_MODE_FLAG_PVSYNC;
2267 else
2268 flags |= DRM_MODE_FLAG_NVSYNC;
2269 }
045ac3b5 2270
2d112de7 2271 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2272
8c875fca
VS		 2273 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2274 tmp & DP_COLOR_RANGE_16_235)
2275 pipe_config->limited_color_range = true;
2276
eb14cb74
VS		 2277 pipe_config->has_dp_encoder = true;
2278
2279 intel_dp_get_m_n(crtc, pipe_config);
2280
18442d08 2281 if (port == PORT_A) {
f1f644dc
JB		 2282 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2283 pipe_config->port_clock = 162000;
2284 else
2285 pipe_config->port_clock = 270000;
2286 }
18442d08
VS		 2287
2288 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2289 &pipe_config->dp_m_n);
2290
2291 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2292 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2293
2d112de7 2294 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2295
c6cd2ee2
JN		 2296 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2297 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2298 /*
2299 * This is a big fat ugly hack.
2300 *
2301 * Some machines in UEFI boot mode provide us a VBT that has 18
2302 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2303 * unknown we fail to light up. Yet the same BIOS boots up with
2304 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2305 * max, not what it tells us to use.
2306 *
2307 * Note: This will still be broken if the eDP panel is not lit
2308 * up by the BIOS, and thus we can't get the mode at module
2309 * load.
2310 */
2311 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2312 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2313 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2314 }
045ac3b5
JB		 2315}
2316
e8cb4558 2317static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2318{
e8cb4558 2319 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2320 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2321 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2322
6e3c9717 2323 if (crtc->config->has_audio)
495a5bb8 2324 intel_audio_codec_disable(encoder);
6cb49835 2325
b32c6f48
RV		 2326 if (HAS_PSR(dev) && !HAS_DDI(dev))
2327 intel_psr_disable(intel_dp);
2328
6cb49835
DV		 2329 /* Make sure the panel is off before trying to change the mode. But also
2330 * ensure that we have vdd while we switch off the panel. */
24f3e092 2331 intel_edp_panel_vdd_on(intel_dp);
4be73780 2332 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2333 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2334 intel_edp_panel_off(intel_dp);
3739850b 2335
08aff3fe
VS		 2336 /* disable the port before the pipe on g4x */
2337 if (INTEL_INFO(dev)->gen < 5)
3739850b 2338 intel_dp_link_down(intel_dp);
d240f20f
JB		 2339}
2340
08aff3fe 2341static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2342{
2bd2ad64 2343 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2344 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2345
49277c31 2346 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2347 if (port == PORT_A)
2348 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2349}
2350
2351static void vlv_post_disable_dp(struct intel_encoder *encoder)
2352{
2353 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2354
2355 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2356}
2357
580d3811
VS		 2358static void chv_post_disable_dp(struct intel_encoder *encoder)
2359{
2360 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2361 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2362 struct drm_device *dev = encoder->base.dev;
2363 struct drm_i915_private *dev_priv = dev->dev_private;
2364 struct intel_crtc *intel_crtc =
2365 to_intel_crtc(encoder->base.crtc);
2366 enum dpio_channel ch = vlv_dport_to_channel(dport);
2367 enum pipe pipe = intel_crtc->pipe;
2368 u32 val;
2369
2370 intel_dp_link_down(intel_dp);
2371
a580516d 2372 mutex_lock(&dev_priv->sb_lock);
580d3811
VS		 2373
2374 /* Propagate soft reset to data lane reset */
97fd4d5c 2375 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2376 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2377 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2378
97fd4d5c
VS		 2379 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2380 val |= CHV_PCS_REQ_SOFTRESET_EN;
2381 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2382
2383 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2384 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2385 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2386
2387 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2388 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2389 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811 2390
a580516d 2391 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2392}
2393
7b13b58a
VS		 2394static void
2395_intel_dp_set_link_train(struct intel_dp *intel_dp,
2396 uint32_t *DP,
2397 uint8_t dp_train_pat)
2398{
2399 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2400 struct drm_device *dev = intel_dig_port->base.base.dev;
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 enum port port = intel_dig_port->port;
2403
2404 if (HAS_DDI(dev)) {
2405 uint32_t temp = I915_READ(DP_TP_CTL(port));
2406
2407 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2408 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2409 else
2410 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2411
2412 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2413 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2414 case DP_TRAINING_PATTERN_DISABLE:
2415 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2416
2417 break;
2418 case DP_TRAINING_PATTERN_1:
2419 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2420 break;
2421 case DP_TRAINING_PATTERN_2:
2422 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2423 break;
2424 case DP_TRAINING_PATTERN_3:
2425 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2426 break;
2427 }
2428 I915_WRITE(DP_TP_CTL(port), temp);
2429
39e5fa88
VS		 2430 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2431 (HAS_PCH_CPT(dev) && port != PORT_A)) {
7b13b58a
VS		 2432 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2433
2434 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2435 case DP_TRAINING_PATTERN_DISABLE:
2436 *DP |= DP_LINK_TRAIN_OFF_CPT;
2437 break;
2438 case DP_TRAINING_PATTERN_1:
2439 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2440 break;
2441 case DP_TRAINING_PATTERN_2:
2442 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2443 break;
2444 case DP_TRAINING_PATTERN_3:
2445 DRM_ERROR("DP training pattern 3 not supported\n");
2446 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2447 break;
2448 }
2449
2450 } else {
2451 if (IS_CHERRYVIEW(dev))
2452 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2453 else
2454 *DP &= ~DP_LINK_TRAIN_MASK;
2455
2456 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2457 case DP_TRAINING_PATTERN_DISABLE:
2458 *DP |= DP_LINK_TRAIN_OFF;
2459 break;
2460 case DP_TRAINING_PATTERN_1:
2461 *DP |= DP_LINK_TRAIN_PAT_1;
2462 break;
2463 case DP_TRAINING_PATTERN_2:
2464 *DP |= DP_LINK_TRAIN_PAT_2;
2465 break;
2466 case DP_TRAINING_PATTERN_3:
2467 if (IS_CHERRYVIEW(dev)) {
2468 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2469 } else {
2470 DRM_ERROR("DP training pattern 3 not supported\n");
2471 *DP |= DP_LINK_TRAIN_PAT_2;
2472 }
2473 break;
2474 }
2475 }
2476}
2477
2478static void intel_dp_enable_port(struct intel_dp *intel_dp)
2479{
2480 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2481 struct drm_i915_private *dev_priv = dev->dev_private;
2482
7b13b58a
VS		 2483 /* enable with pattern 1 (as per spec) */
2484 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2485 DP_TRAINING_PATTERN_1);
2486
2487 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2488 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2489
2490 /*
2491 * Magic for VLV/CHV. We _must_ first set up the register
2492 * without actually enabling the port, and then do another
2493 * write to enable the port. Otherwise link training will
2494 * fail when the power sequencer is freshly used for this port.
2495 */
2496 intel_dp->DP |= DP_PORT_EN;
2497
2498 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2499 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2500}
2501
e8cb4558 2502static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2503{
e8cb4558
DV		 2504 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2505 struct drm_device *dev = encoder->base.dev;
2506 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2507 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2508 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
9b6de0a1 2509 unsigned int lane_mask = 0x0;
5d613501 2510
0c33d8d7
DV		 2511 if (WARN_ON(dp_reg & DP_PORT_EN))
2512 return;
5d613501 2513
093e3f13
VS		 2514 pps_lock(intel_dp);
2515
2516 if (IS_VALLEYVIEW(dev))
2517 vlv_init_panel_power_sequencer(intel_dp);
2518
7b13b58a 2519 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2520
2521 edp_panel_vdd_on(intel_dp);
2522 edp_panel_on(intel_dp);
2523 edp_panel_vdd_off(intel_dp, true);
2524
2525 pps_unlock(intel_dp);
2526
61234fa5 2527 if (IS_VALLEYVIEW(dev))
9b6de0a1
VS		 2528 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2529 lane_mask);
61234fa5 2530
f01eca2e 2531 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2532 intel_dp_start_link_train(intel_dp);
33a34e4e 2533 intel_dp_complete_link_train(intel_dp);
3ab9c637 2534 intel_dp_stop_link_train(intel_dp);
c1dec79a 2535
6e3c9717 2536 if (crtc->config->has_audio) {
c1dec79a
JN		 2537 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2538 pipe_name(crtc->pipe));
2539 intel_audio_codec_enable(encoder);
2540 }
ab1f90f9 2541}
89b667f8 2542
ecff4f3b
JN		 2543static void g4x_enable_dp(struct intel_encoder *encoder)
2544{
828f5c6e
JN		 2545 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2546
ecff4f3b 2547 intel_enable_dp(encoder);
4be73780 2548 intel_edp_backlight_on(intel_dp);
ab1f90f9 2549}
89b667f8 2550
ab1f90f9
JN		 2551static void vlv_enable_dp(struct intel_encoder *encoder)
2552{
828f5c6e
JN		 2553 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2554
4be73780 2555 intel_edp_backlight_on(intel_dp);
b32c6f48 2556 intel_psr_enable(intel_dp);
d240f20f
JB		 2557}
2558
ecff4f3b 2559static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2560{
2561 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2562 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2563
8ac33ed3
DV		 2564 intel_dp_prepare(encoder);
2565
d41f1efb
DV		 2566 /* Only ilk+ has port A */
2567 if (dport->port == PORT_A) {
2568 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2569 ironlake_edp_pll_on(intel_dp);
d41f1efb 2570 }
ab1f90f9
JN		 2571}
2572
83b84597
VS		 2573static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2574{
2575 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2576 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2577 enum pipe pipe = intel_dp->pps_pipe;
2578 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2579
2580 edp_panel_vdd_off_sync(intel_dp);
2581
2582 /*
2583 * VLV seems to get confused when multiple power seqeuencers
2584 * have the same port selected (even if only one has power/vdd
2585 * enabled). The failure manifests as vlv_wait_port_ready() failing
2586 * CHV on the other hand doesn't seem to mind having the same port
2587 * selected in multiple power seqeuencers, but let's clear the
2588 * port select always when logically disconnecting a power sequencer
2589 * from a port.
2590 */
2591 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2592 pipe_name(pipe), port_name(intel_dig_port->port));
2593 I915_WRITE(pp_on_reg, 0);
2594 POSTING_READ(pp_on_reg);
2595
2596 intel_dp->pps_pipe = INVALID_PIPE;
2597}
2598
a4a5d2f8
VS		 2599static void vlv_steal_power_sequencer(struct drm_device *dev,
2600 enum pipe pipe)
2601{
2602 struct drm_i915_private *dev_priv = dev->dev_private;
2603 struct intel_encoder *encoder;
2604
2605 lockdep_assert_held(&dev_priv->pps_mutex);
2606
ac3c12e4
VS		 2607 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2608 return;
2609
a4a5d2f8
VS		 2610 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2611 base.head) {
2612 struct intel_dp *intel_dp;
773538e8 2613 enum port port;
a4a5d2f8
VS		 2614
2615 if (encoder->type != INTEL_OUTPUT_EDP)
2616 continue;
2617
2618 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2619 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2620
2621 if (intel_dp->pps_pipe != pipe)
2622 continue;
2623
2624 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2625 pipe_name(pipe), port_name(port));
a4a5d2f8 2626
034e43c6
VS		 2627 WARN(encoder->connectors_active,
2628 "stealing pipe %c power sequencer from active eDP port %c\n",
2629 pipe_name(pipe), port_name(port));
a4a5d2f8 2630
a4a5d2f8 2631 /* make sure vdd is off before we steal it */
83b84597 2632 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2633 }
2634}
2635
2636static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2637{
2638 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2639 struct intel_encoder *encoder = &intel_dig_port->base;
2640 struct drm_device *dev = encoder->base.dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2643
2644 lockdep_assert_held(&dev_priv->pps_mutex);
2645
093e3f13
VS		 2646 if (!is_edp(intel_dp))
2647 return;
2648
a4a5d2f8
VS		 2649 if (intel_dp->pps_pipe == crtc->pipe)
2650 return;
2651
2652 /*
2653 * If another power sequencer was being used on this
2654 * port previously make sure to turn off vdd there while
2655 * we still have control of it.
2656 */
2657 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2658 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2659
2660 /*
2661 * We may be stealing the power
2662 * sequencer from another port.
2663 */
2664 vlv_steal_power_sequencer(dev, crtc->pipe);
2665
2666 /* now it's all ours */
2667 intel_dp->pps_pipe = crtc->pipe;
2668
2669 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2670 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2671
2672 /* init power sequencer on this pipe and port */
36b5f425
VS		 2673 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2674 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2675}
2676
ab1f90f9 2677static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2678{
2bd2ad64 2679 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2680 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2681 struct drm_device *dev = encoder->base.dev;
89b667f8 2682 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2683 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2684 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2685 int pipe = intel_crtc->pipe;
2686 u32 val;
a4fc5ed6 2687
a580516d 2688 mutex_lock(&dev_priv->sb_lock);
89b667f8 2689
ab3c759a 2690 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2691 val = 0;
2692 if (pipe)
2693 val |= (1<<21);
2694 else
2695 val &= ~(1<<21);
2696 val |= 0x001000c4;
ab3c759a
CML		 2697 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2698 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2699 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2700
a580516d 2701 mutex_unlock(&dev_priv->sb_lock);
ab1f90f9
JN		 2702
2703 intel_enable_dp(encoder);
89b667f8
JB		 2704}
2705
ecff4f3b 2706static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2707{
2708 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2709 struct drm_device *dev = encoder->base.dev;
2710 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2711 struct intel_crtc *intel_crtc =
2712 to_intel_crtc(encoder->base.crtc);
e4607fcf 2713 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2714 int pipe = intel_crtc->pipe;
89b667f8 2715
8ac33ed3
DV		 2716 intel_dp_prepare(encoder);
2717
89b667f8 2718 /* Program Tx lane resets to default */
a580516d 2719 mutex_lock(&dev_priv->sb_lock);
ab3c759a 2720 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2721 DPIO_PCS_TX_LANE2_RESET |
2722 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2723 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2724 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2725 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2726 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2727 DPIO_PCS_CLK_SOFT_RESET);
2728
2729 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2730 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2731 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2732 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
a580516d 2733 mutex_unlock(&dev_priv->sb_lock);
a4fc5ed6
KP		 2734}
2735
e4a1d846
CML		 2736static void chv_pre_enable_dp(struct intel_encoder *encoder)
2737{
2738 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2739 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2740 struct drm_device *dev = encoder->base.dev;
2741 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2742 struct intel_crtc *intel_crtc =
2743 to_intel_crtc(encoder->base.crtc);
2744 enum dpio_channel ch = vlv_dport_to_channel(dport);
2745 int pipe = intel_crtc->pipe;
2e523e98 2746 int data, i, stagger;
949c1d43 2747 u32 val;
e4a1d846 2748
a580516d 2749 mutex_lock(&dev_priv->sb_lock);
949c1d43 2750
570e2a74
VS		 2751 /* allow hardware to manage TX FIFO reset source */
2752 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2753 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2754 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2755
2756 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2757 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2758 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2759
949c1d43 2760 /* Deassert soft data lane reset*/
97fd4d5c 2761 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2762 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2763 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2764
2765 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2766 val |= CHV_PCS_REQ_SOFTRESET_EN;
2767 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2768
2769 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2770 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2771 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2772
97fd4d5c 2773 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2774 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2775 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2776
2777 /* Program Tx lane latency optimal setting*/
e4a1d846 2778 for (i = 0; i < 4; i++) {
e4a1d846
CML		 2779 /* Set the upar bit */
2780 data = (i == 1) ? 0x0 : 0x1;
2781 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2782 data << DPIO_UPAR_SHIFT);
2783 }
2784
2785 /* Data lane stagger programming */
2e523e98
VS		 2786 if (intel_crtc->config->port_clock > 270000)
2787 stagger = 0x18;
2788 else if (intel_crtc->config->port_clock > 135000)
2789 stagger = 0xd;
2790 else if (intel_crtc->config->port_clock > 67500)
2791 stagger = 0x7;
2792 else if (intel_crtc->config->port_clock > 33750)
2793 stagger = 0x4;
2794 else
2795 stagger = 0x2;
2796
2797 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2798 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2799 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2800
2801 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2802 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2803 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2804
2805 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
2806 DPIO_LANESTAGGER_STRAP(stagger) |
2807 DPIO_LANESTAGGER_STRAP_OVRD |
2808 DPIO_TX1_STAGGER_MASK(0x1f) |
2809 DPIO_TX1_STAGGER_MULT(6) |
2810 DPIO_TX2_STAGGER_MULT(0));
2811
2812 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
2813 DPIO_LANESTAGGER_STRAP(stagger) |
2814 DPIO_LANESTAGGER_STRAP_OVRD |
2815 DPIO_TX1_STAGGER_MASK(0x1f) |
2816 DPIO_TX1_STAGGER_MULT(7) |
2817 DPIO_TX2_STAGGER_MULT(5));
e4a1d846 2818
a580516d 2819 mutex_unlock(&dev_priv->sb_lock);
e4a1d846 2820
e4a1d846 2821 intel_enable_dp(encoder);
e4a1d846
CML		 2822}
2823
9197c88b
VS		 2824static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2825{
2826 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2827 struct drm_device *dev = encoder->base.dev;
2828 struct drm_i915_private *dev_priv = dev->dev_private;
2829 struct intel_crtc *intel_crtc =
2830 to_intel_crtc(encoder->base.crtc);
2831 enum dpio_channel ch = vlv_dport_to_channel(dport);
2832 enum pipe pipe = intel_crtc->pipe;
2833 u32 val;
2834
625695f8
VS		 2835 intel_dp_prepare(encoder);
2836
a580516d 2837 mutex_lock(&dev_priv->sb_lock);
9197c88b 2838
b9e5ac3c
VS		 2839 /* program left/right clock distribution */
2840 if (pipe != PIPE_B) {
2841 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2842 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2843 if (ch == DPIO_CH0)
2844 val |= CHV_BUFLEFTENA1_FORCE;
2845 if (ch == DPIO_CH1)
2846 val |= CHV_BUFRIGHTENA1_FORCE;
2847 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2848 } else {
2849 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2850 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2851 if (ch == DPIO_CH0)
2852 val |= CHV_BUFLEFTENA2_FORCE;
2853 if (ch == DPIO_CH1)
2854 val |= CHV_BUFRIGHTENA2_FORCE;
2855 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2856 }
2857
9197c88b
VS		 2858 /* program clock channel usage */
2859 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2860 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2861 if (pipe != PIPE_B)
2862 val &= ~CHV_PCS_USEDCLKCHANNEL;
2863 else
2864 val |= CHV_PCS_USEDCLKCHANNEL;
2865 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2866
2867 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2868 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2869 if (pipe != PIPE_B)
2870 val &= ~CHV_PCS_USEDCLKCHANNEL;
2871 else
2872 val |= CHV_PCS_USEDCLKCHANNEL;
2873 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2874
2875 /*
2876 * This a a bit weird since generally CL
2877 * matches the pipe, but here we need to
2878 * pick the CL based on the port.
2879 */
2880 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2881 if (pipe != PIPE_B)
2882 val &= ~CHV_CMN_USEDCLKCHANNEL;
2883 else
2884 val |= CHV_CMN_USEDCLKCHANNEL;
2885 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2886
a580516d 2887 mutex_unlock(&dev_priv->sb_lock);
9197c88b
VS		 2888}
2889
a4fc5ed6 2890/*
df0c237d
JB		 2891 * Native read with retry for link status and receiver capability reads for
2892 * cases where the sink may still be asleep.
9d1a1031
JN		 2893 *
2894 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2895 * supposed to retry 3 times per the spec.
a4fc5ed6 2896 */
9d1a1031
JN		 2897static ssize_t
2898intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2899 void *buffer, size_t size)
a4fc5ed6 2900{
9d1a1031
JN		 2901 ssize_t ret;
2902 int i;
61da5fab 2903
f6a19066
VS		 2904 /*
2905 * Sometime we just get the same incorrect byte repeated
2906 * over the entire buffer. Doing just one throw away read
2907 * initially seems to "solve" it.
2908 */
2909 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2910
61da5fab 2911 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2912 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2913 if (ret == size)
2914 return ret;
61da5fab
JB		 2915 msleep(1);
2916 }
a4fc5ed6 2917
9d1a1031 2918 return ret;
a4fc5ed6
KP		 2919}
2920
2921/*
2922 * Fetch AUX CH registers 0x202 - 0x207 which contain
2923 * link status information
2924 */
2925static bool
93f62dad 2926intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2927{
9d1a1031
JN		 2928 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2929 DP_LANE0_1_STATUS,
2930 link_status,
2931 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2932}
2933
1100244e 2934/* These are source-specific values. */
a4fc5ed6 2935static uint8_t
1a2eb460 2936intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2937{
30add22d 2938 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 2939 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 2940 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2941
9314726b
VK		 2942 if (IS_BROXTON(dev))
2943 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2944 else if (INTEL_INFO(dev)->gen >= 9) {
9e458034 2945 if (dev_priv->edp_low_vswing && port == PORT_A)
7ad14a29 2946 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2947 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
7ad14a29 2948 } else if (IS_VALLEYVIEW(dev))
bd60018a 2949 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2950 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2951 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2952 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2953 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2954 else
bd60018a 2955 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2956}
2957
2958static uint8_t
2959intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2960{
30add22d 2961 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2962 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2963
5a9d1f1a
DL		 2964 if (INTEL_INFO(dev)->gen >= 9) {
2965 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2966 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2967 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2968 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2969 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2970 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2971 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 2972 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2973 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 2974 default:
2975 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2976 }
2977 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2978 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2979 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2980 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2981 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2982 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2983 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2984 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2985 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2986 default:
bd60018a 2987 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2988 }
e2fa6fba
P		 2989 } else if (IS_VALLEYVIEW(dev)) {
2990 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2991 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2992 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2993 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2994 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2995 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2996 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2997 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2998 default:
bd60018a 2999 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3000 }
bc7d38a4 3001 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 3002 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3004 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3005 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3006 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3007 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3008 default:
bd60018a 3009 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3010 }
3011 } else {
3012 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3014 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3015 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3016 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3017 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3018 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3019 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3020 default:
bd60018a 3021 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3022 }
a4fc5ed6
KP		 3023 }
3024}
3025
5829975c 3026static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba
P		 3027{
3028 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3029 struct drm_i915_private *dev_priv = dev->dev_private;
3030 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 3031 struct intel_crtc *intel_crtc =
3032 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 3033 unsigned long demph_reg_value, preemph_reg_value,
3034 uniqtranscale_reg_value;
3035 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 3036 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 3037 int pipe = intel_crtc->pipe;
e2fa6fba
P		 3038
3039 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3040 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3041 preemph_reg_value = 0x0004000;
3042 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3044 demph_reg_value = 0x2B405555;
3045 uniqtranscale_reg_value = 0x552AB83A;
3046 break;
bd60018a 3047 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3048 demph_reg_value = 0x2B404040;
3049 uniqtranscale_reg_value = 0x5548B83A;
3050 break;
bd60018a 3051 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3052 demph_reg_value = 0x2B245555;
3053 uniqtranscale_reg_value = 0x5560B83A;
3054 break;
bd60018a 3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3056 demph_reg_value = 0x2B405555;
3057 uniqtranscale_reg_value = 0x5598DA3A;
3058 break;
3059 default:
3060 return 0;
3061 }
3062 break;
bd60018a 3063 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3064 preemph_reg_value = 0x0002000;
3065 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3066 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3067 demph_reg_value = 0x2B404040;
3068 uniqtranscale_reg_value = 0x5552B83A;
3069 break;
bd60018a 3070 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3071 demph_reg_value = 0x2B404848;
3072 uniqtranscale_reg_value = 0x5580B83A;
3073 break;
bd60018a 3074 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3075 demph_reg_value = 0x2B404040;
3076 uniqtranscale_reg_value = 0x55ADDA3A;
3077 break;
3078 default:
3079 return 0;
3080 }
3081 break;
bd60018a 3082 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3083 preemph_reg_value = 0x0000000;
3084 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3085 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3086 demph_reg_value = 0x2B305555;
3087 uniqtranscale_reg_value = 0x5570B83A;
3088 break;
bd60018a 3089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3090 demph_reg_value = 0x2B2B4040;
3091 uniqtranscale_reg_value = 0x55ADDA3A;
3092 break;
3093 default:
3094 return 0;
3095 }
3096 break;
bd60018a 3097 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3098 preemph_reg_value = 0x0006000;
3099 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3100 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3101 demph_reg_value = 0x1B405555;
3102 uniqtranscale_reg_value = 0x55ADDA3A;
3103 break;
3104 default:
3105 return 0;
3106 }
3107 break;
3108 default:
3109 return 0;
3110 }
3111
a580516d 3112 mutex_lock(&dev_priv->sb_lock);
ab3c759a
CML		 3113 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3114 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3115 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3116 uniqtranscale_reg_value);
ab3c759a
CML		 3117 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3118 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3119 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3120 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
a580516d 3121 mutex_unlock(&dev_priv->sb_lock);
e2fa6fba
P		 3122
3123 return 0;
3124}
3125
5829975c 3126static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846
CML		 3127{
3128 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3129 struct drm_i915_private *dev_priv = dev->dev_private;
3130 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3131 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3132 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3133 uint8_t train_set = intel_dp->train_set[0];
3134 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3135 enum pipe pipe = intel_crtc->pipe;
3136 int i;
e4a1d846
CML		 3137
3138 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3139 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3140 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3141 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3142 deemph_reg_value = 128;
3143 margin_reg_value = 52;
3144 break;
bd60018a 3145 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3146 deemph_reg_value = 128;
3147 margin_reg_value = 77;
3148 break;
bd60018a 3149 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3150 deemph_reg_value = 128;
3151 margin_reg_value = 102;
3152 break;
bd60018a 3153 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3154 deemph_reg_value = 128;
3155 margin_reg_value = 154;
3156 /* FIXME extra to set for 1200 */
3157 break;
3158 default:
3159 return 0;
3160 }
3161 break;
bd60018a 3162 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3163 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3164 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3165 deemph_reg_value = 85;
3166 margin_reg_value = 78;
3167 break;
bd60018a 3168 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3169 deemph_reg_value = 85;
3170 margin_reg_value = 116;
3171 break;
bd60018a 3172 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3173 deemph_reg_value = 85;
3174 margin_reg_value = 154;
3175 break;
3176 default:
3177 return 0;
3178 }
3179 break;
bd60018a 3180 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3181 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3182 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3183 deemph_reg_value = 64;
3184 margin_reg_value = 104;
3185 break;
bd60018a 3186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3187 deemph_reg_value = 64;
3188 margin_reg_value = 154;
3189 break;
3190 default:
3191 return 0;
3192 }
3193 break;
bd60018a 3194 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3195 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3196 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3197 deemph_reg_value = 43;
3198 margin_reg_value = 154;
3199 break;
3200 default:
3201 return 0;
3202 }
3203 break;
3204 default:
3205 return 0;
3206 }
3207
a580516d 3208 mutex_lock(&dev_priv->sb_lock);
e4a1d846
CML		 3209
3210 /* Clear calc init */
1966e59e
VS		 3211 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3212 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3213 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3214 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3215 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3216
3217 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3218 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3219 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3220 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3221 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3222
a02ef3c7
VS		 3223 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3224 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3225 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3226 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3227
3228 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3229 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3230 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3231 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3232
e4a1d846 3233 /* Program swing deemph */
f72df8db
VS		 3234 for (i = 0; i < 4; i++) {
3235 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3236 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3237 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3238 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3239 }
e4a1d846
CML		 3240
3241 /* Program swing margin */
f72df8db
VS		 3242 for (i = 0; i < 4; i++) {
3243 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3244 val &= ~DPIO_SWING_MARGIN000_MASK;
3245 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3246 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3247 }
e4a1d846
CML		 3248
3249 /* Disable unique transition scale */
f72df8db
VS		 3250 for (i = 0; i < 4; i++) {
3251 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3252 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3253 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3254 }
e4a1d846
CML		 3255
3256 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3257 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3258 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3259 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3260
3261 /*
3262 * The document said it needs to set bit 27 for ch0 and bit 26
3263 * for ch1. Might be a typo in the doc.
3264 * For now, for this unique transition scale selection, set bit
3265 * 27 for ch0 and ch1.
3266 */
f72df8db
VS		 3267 for (i = 0; i < 4; i++) {
3268 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3269 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3270 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3271 }
e4a1d846 3272
f72df8db
VS		 3273 for (i = 0; i < 4; i++) {
3274 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3275 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3276 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3277 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3278 }
e4a1d846
CML		 3279 }
3280
3281 /* Start swing calculation */
1966e59e
VS		 3282 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3283 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3284 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3285
3286 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3287 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3288 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3289
3290 /* LRC Bypass */
3291 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3292 val |= DPIO_LRC_BYPASS;
3293 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3294
a580516d 3295 mutex_unlock(&dev_priv->sb_lock);
e4a1d846
CML		 3296
3297 return 0;
3298}
3299
a4fc5ed6 3300static void
0301b3ac
JN		 3301intel_get_adjust_train(struct intel_dp *intel_dp,
3302 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3303{
3304 uint8_t v = 0;
3305 uint8_t p = 0;
3306 int lane;
1a2eb460
KP		 3307 uint8_t voltage_max;
3308 uint8_t preemph_max;
a4fc5ed6 3309
33a34e4e 3310 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3311 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3312 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3313
3314 if (this_v > v)
3315 v = this_v;
3316 if (this_p > p)
3317 p = this_p;
3318 }
3319
1a2eb460 3320 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3321 if (v >= voltage_max)
3322 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3323
1a2eb460
KP		 3324 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3325 if (p >= preemph_max)
3326 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3327
3328 for (lane = 0; lane < 4; lane++)
33a34e4e 3329 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3330}
3331
3332static uint32_t
5829975c 3333gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3334{
3cf2efb1 3335 uint32_t signal_levels = 0;
a4fc5ed6 3336
3cf2efb1 3337 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3338 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3339 default:
3340 signal_levels |= DP_VOLTAGE_0_4;
3341 break;
bd60018a 3342 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3343 signal_levels |= DP_VOLTAGE_0_6;
3344 break;
bd60018a 3345 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3346 signal_levels |= DP_VOLTAGE_0_8;
3347 break;
bd60018a 3348 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3349 signal_levels |= DP_VOLTAGE_1_2;
3350 break;
3351 }
3cf2efb1 3352 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3353 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3354 default:
3355 signal_levels |= DP_PRE_EMPHASIS_0;
3356 break;
bd60018a 3357 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3358 signal_levels |= DP_PRE_EMPHASIS_3_5;
3359 break;
bd60018a 3360 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3361 signal_levels |= DP_PRE_EMPHASIS_6;
3362 break;
bd60018a 3363 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3364 signal_levels |= DP_PRE_EMPHASIS_9_5;
3365 break;
3366 }
3367 return signal_levels;
3368}
3369
e3421a18
ZW		 3370/* Gen6's DP voltage swing and pre-emphasis control */
3371static uint32_t
5829975c 3372gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3373{
3c5a62b5
YL		 3374 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3375 DP_TRAIN_PRE_EMPHASIS_MASK);
3376 switch (signal_levels) {
bd60018a
SJ		 3377 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3378 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3379 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3380 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3381 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3382 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3383 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3384 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3385 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3386 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3387 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3388 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3389 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3390 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3391 default:
3c5a62b5
YL		 3392 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3393 "0x%x\n", signal_levels);
3394 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3395 }
3396}
3397
1a2eb460
KP		 3398/* Gen7's DP voltage swing and pre-emphasis control */
3399static uint32_t
5829975c 3400gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3401{
3402 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3403 DP_TRAIN_PRE_EMPHASIS_MASK);
3404 switch (signal_levels) {
bd60018a 3405 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3406 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3407 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3408 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3409 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3410 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3411
bd60018a 3412 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3413 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3414 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3415 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3416
bd60018a 3417 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3418 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3419 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3420 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3421
3422 default:
3423 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3424 "0x%x\n", signal_levels);
3425 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3426 }
3427}
3428
f0a3424e
PZ		 3429/* Properly updates "DP" with the correct signal levels. */
3430static void
3431intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3432{
3433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3434 enum port port = intel_dig_port->port;
f0a3424e 3435 struct drm_device *dev = intel_dig_port->base.base.dev;
f8896f5d 3436 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3437 uint8_t train_set = intel_dp->train_set[0];
3438
f8896f5d
DW		 3439 if (HAS_DDI(dev)) {
3440 signal_levels = ddi_signal_levels(intel_dp);
3441
3442 if (IS_BROXTON(dev))
3443 signal_levels = 0;
3444 else
3445 mask = DDI_BUF_EMP_MASK;
e4a1d846 3446 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3447 signal_levels = chv_signal_levels(intel_dp);
e2fa6fba 3448 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3449 signal_levels = vlv_signal_levels(intel_dp);
bc7d38a4 3450 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3451 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3452 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3453 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3454 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3455 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3456 } else {
5829975c 3457 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3458 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3459 }
3460
96fb9f9b
VK		 3461 if (mask)
3462 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3463
3464 DRM_DEBUG_KMS("Using vswing level %d\n",
3465 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3466 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3467 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3468 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e
PZ		 3469
3470 *DP = (*DP & ~mask) | signal_levels;
3471}
3472
a4fc5ed6 3473static bool
ea5b213a 3474intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3475 uint32_t *DP,
58e10eb9 3476 uint8_t dp_train_pat)
a4fc5ed6 3477{
174edf1f
PZ		 3478 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3479 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3480 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3481 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3482 int ret, len;
a4fc5ed6 3483
7b13b58a 3484 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3485
70aff66c 3486 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3487 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3488
2cdfe6c8
JN		 3489 buf[0] = dp_train_pat;
3490 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3491 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3492 /* don't write DP_TRAINING_LANEx_SET on disable */
3493 len = 1;
3494 } else {
3495 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3496 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3497 len = intel_dp->lane_count + 1;
47ea7542 3498 }
a4fc5ed6 3499
9d1a1031
JN		 3500 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3501 buf, len);
2cdfe6c8
JN		 3502
3503 return ret == len;
a4fc5ed6
KP		 3504}
3505
70aff66c
JN		 3506static bool
3507intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3508 uint8_t dp_train_pat)
3509{
4e96c977
MK		 3510 if (!intel_dp->train_set_valid)
3511 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3512 intel_dp_set_signal_levels(intel_dp, DP);
3513 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3514}
3515
3516static bool
3517intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3518 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3519{
3520 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3521 struct drm_device *dev = intel_dig_port->base.base.dev;
3522 struct drm_i915_private *dev_priv = dev->dev_private;
3523 int ret;
3524
3525 intel_get_adjust_train(intel_dp, link_status);
3526 intel_dp_set_signal_levels(intel_dp, DP);
3527
3528 I915_WRITE(intel_dp->output_reg, *DP);
3529 POSTING_READ(intel_dp->output_reg);
3530
9d1a1031
JN		 3531 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3532 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3533
3534 return ret == intel_dp->lane_count;
3535}
3536
3ab9c637
ID		 3537static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3538{
3539 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3540 struct drm_device *dev = intel_dig_port->base.base.dev;
3541 struct drm_i915_private *dev_priv = dev->dev_private;
3542 enum port port = intel_dig_port->port;
3543 uint32_t val;
3544
3545 if (!HAS_DDI(dev))
3546 return;
3547
3548 val = I915_READ(DP_TP_CTL(port));
3549 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3550 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3551 I915_WRITE(DP_TP_CTL(port), val);
3552
3553 /*
3554 * On PORT_A we can have only eDP in SST mode. There the only reason
3555 * we need to set idle transmission mode is to work around a HW issue
3556 * where we enable the pipe while not in idle link-training mode.
3557 * In this case there is requirement to wait for a minimum number of
3558 * idle patterns to be sent.
3559 */
3560 if (port == PORT_A)
3561 return;
3562
3563 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3564 1))
3565 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3566}
3567
33a34e4e 3568/* Enable corresponding port and start training pattern 1 */
c19b0669 3569void
33a34e4e 3570intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3571{
da63a9f2 3572 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3573 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3574 int i;
3575 uint8_t voltage;
cdb0e95b 3576 int voltage_tries, loop_tries;
ea5b213a 3577 uint32_t DP = intel_dp->DP;
6aba5b6c 3578 uint8_t link_config[2];
a4fc5ed6 3579
affa9354 3580 if (HAS_DDI(dev))
c19b0669
PZ		 3581 intel_ddi_prepare_link_retrain(encoder);
3582
3cf2efb1 3583 /* Write the link configuration data */
6aba5b6c
JN		 3584 link_config[0] = intel_dp->link_bw;
3585 link_config[1] = intel_dp->lane_count;
3586 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3587 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3588 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
94ca719e 3589 if (intel_dp->num_sink_rates)
a8f3ef61
SJ		 3590 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
3591 &intel_dp->rate_select, 1);
6aba5b6c
JN		 3592
3593 link_config[0] = 0;
3594 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3595 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3596
3597 DP |= DP_PORT_EN;
1a2eb460 3598
70aff66c
JN		 3599 /* clock recovery */
3600 if (!intel_dp_reset_link_train(intel_dp, &DP,
3601 DP_TRAINING_PATTERN_1 |
3602 DP_LINK_SCRAMBLING_DISABLE)) {
3603 DRM_ERROR("failed to enable link training\n");
3604 return;
3605 }
3606
a4fc5ed6 3607 voltage = 0xff;
cdb0e95b
KP		 3608 voltage_tries = 0;
3609 loop_tries = 0;
a4fc5ed6 3610 for (;;) {
70aff66c 3611 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3612
a7c9655f 3613 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3614 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3615 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3616 break;
93f62dad 3617 }
a4fc5ed6 3618
01916270 3619 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3620 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3621 break;
3622 }
3623
4e96c977
MK		 3624 /*
3625 * if we used previously trained voltage and pre-emphasis values
3626 * and we don't get clock recovery, reset link training values
3627 */
3628 if (intel_dp->train_set_valid) {
3629 DRM_DEBUG_KMS("clock recovery not ok, reset");
3630 /* clear the flag as we are not reusing train set */
3631 intel_dp->train_set_valid = false;
3632 if (!intel_dp_reset_link_train(intel_dp, &DP,
3633 DP_TRAINING_PATTERN_1 |
3634 DP_LINK_SCRAMBLING_DISABLE)) {
3635 DRM_ERROR("failed to enable link training\n");
3636 return;
3637 }
3638 continue;
3639 }
3640
3cf2efb1
CW		 3641 /* Check to see if we've tried the max voltage */
3642 for (i = 0; i < intel_dp->lane_count; i++)
3643 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3644 break;
3b4f819d 3645 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3646 ++loop_tries;
3647 if (loop_tries == 5) {
3def84b3 3648 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3649 break;
3650 }
70aff66c
JN		 3651 intel_dp_reset_link_train(intel_dp, &DP,
3652 DP_TRAINING_PATTERN_1 |
3653 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3654 voltage_tries = 0;
3655 continue;
3656 }
a4fc5ed6 3657
3cf2efb1 3658 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3659 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3660 ++voltage_tries;
b06fbda3 3661 if (voltage_tries == 5) {
3def84b3 3662 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3663 break;
3664 }
3665 } else
3666 voltage_tries = 0;
3667 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3668
70aff66c
JN		 3669 /* Update training set as requested by target */
3670 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3671 DRM_ERROR("failed to update link training\n");
3672 break;
3673 }
a4fc5ed6
KP		 3674 }
3675
33a34e4e
JB		 3676 intel_dp->DP = DP;
3677}
3678
c19b0669 3679void
33a34e4e
JB		 3680intel_dp_complete_link_train(struct intel_dp *intel_dp)
3681{
33a34e4e 3682 bool channel_eq = false;
37f80975 3683 int tries, cr_tries;
33a34e4e 3684 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3685 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3686
3687 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3688 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3689 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3690
a4fc5ed6 3691 /* channel equalization */
70aff66c 3692 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3693 training_pattern |
70aff66c
JN		 3694 DP_LINK_SCRAMBLING_DISABLE)) {
3695 DRM_ERROR("failed to start channel equalization\n");
3696 return;
3697 }
3698
a4fc5ed6 3699 tries = 0;
37f80975 3700 cr_tries = 0;
a4fc5ed6
KP		 3701 channel_eq = false;
3702 for (;;) {
70aff66c 3703 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3704
37f80975
JB		 3705 if (cr_tries > 5) {
3706 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3707 break;
3708 }
3709
a7c9655f 3710 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3711 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3712 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3713 break;
70aff66c 3714 }
a4fc5ed6 3715
37f80975 3716 /* Make sure clock is still ok */
01916270 3717 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
4e96c977 3718 intel_dp->train_set_valid = false;
37f80975 3719 intel_dp_start_link_train(intel_dp);
70aff66c 3720 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3721 training_pattern |
70aff66c 3722 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3723 cr_tries++;
3724 continue;
3725 }
3726
1ffdff13 3727 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3728 channel_eq = true;
3729 break;
3730 }
a4fc5ed6 3731
37f80975
JB		 3732 /* Try 5 times, then try clock recovery if that fails */
3733 if (tries > 5) {
4e96c977 3734 intel_dp->train_set_valid = false;
37f80975 3735 intel_dp_start_link_train(intel_dp);
70aff66c 3736 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3737 training_pattern |
70aff66c 3738 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3739 tries = 0;
3740 cr_tries++;
3741 continue;
3742 }
a4fc5ed6 3743
70aff66c
JN		 3744 /* Update training set as requested by target */
3745 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3746 DRM_ERROR("failed to update link training\n");
3747 break;
3748 }
3cf2efb1 3749 ++tries;
869184a6 3750 }
3cf2efb1 3751
3ab9c637
ID		 3752 intel_dp_set_idle_link_train(intel_dp);
3753
3754 intel_dp->DP = DP;
3755
4e96c977 3756 if (channel_eq) {
5fa836a9 3757 intel_dp->train_set_valid = true;
07f42258 3758 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
4e96c977 3759 }
3ab9c637
ID		 3760}
3761
3762void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3763{
70aff66c 3764 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3765 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3766}
3767
3768static void
ea5b213a 3769intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3770{
da63a9f2 3771 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3772 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3773 enum port port = intel_dig_port->port;
da63a9f2 3774 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3775 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3776 uint32_t DP = intel_dp->DP;
a4fc5ed6 3777
bc76e320 3778 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3779 return;
3780
0c33d8d7 3781 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3782 return;
3783
28c97730 3784 DRM_DEBUG_KMS("\n");
32f9d658 3785
39e5fa88
VS		 3786 if ((IS_GEN7(dev) && port == PORT_A) ||
3787 (HAS_PCH_CPT(dev) && port != PORT_A)) {
e3421a18 3788 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3789 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3790 } else {
aad3d14d
VS		 3791 if (IS_CHERRYVIEW(dev))
3792 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3793 else
3794 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3795 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3796 }
1612c8bd 3797 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3798 POSTING_READ(intel_dp->output_reg);
5eb08b69 3799
1612c8bd
VS		 3800 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3801 I915_WRITE(intel_dp->output_reg, DP);
3802 POSTING_READ(intel_dp->output_reg);
3803
3804 /*
3805 * HW workaround for IBX, we need to move the port
3806 * to transcoder A after disabling it to allow the
3807 * matching HDMI port to be enabled on transcoder A.
3808 */
3809 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3810 /* always enable with pattern 1 (as per spec) */
3811 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3812 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3813 I915_WRITE(intel_dp->output_reg, DP);
3814 POSTING_READ(intel_dp->output_reg);
3815
3816 DP &= ~DP_PORT_EN;
5bddd17f 3817 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3818 POSTING_READ(intel_dp->output_reg);
5bddd17f
EA		 3819 }
3820
f01eca2e 3821 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3822}
3823
26d61aad
KP		 3824static bool
3825intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3826{
a031d709
RV		 3827 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3828 struct drm_device *dev = dig_port->base.base.dev;
3829 struct drm_i915_private *dev_priv = dev->dev_private;
fc0f8e25 3830 uint8_t rev;
a031d709 3831
9d1a1031
JN		 3832 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3833 sizeof(intel_dp->dpcd)) < 0)
edb39244 3834 return false; /* aux transfer failed */
92fd8fd1 3835
a8e98153 3836 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3837
edb39244
AJ		 3838 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3839 return false; /* DPCD not present */
3840
2293bb5c
SK		 3841 /* Check if the panel supports PSR */
3842 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3843 if (is_edp(intel_dp)) {
9d1a1031
JN		 3844 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3845 intel_dp->psr_dpcd,
3846 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3847 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3848 dev_priv->psr.sink_support = true;
50003939 3849 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3850 }
474d1ec4
SJ		 3851
3852 if (INTEL_INFO(dev)->gen >= 9 &&
3853 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3854 uint8_t frame_sync_cap;
3855
3856 dev_priv->psr.sink_support = true;
3857 intel_dp_dpcd_read_wake(&intel_dp->aux,
3858 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3859 &frame_sync_cap, 1);
3860 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3861 /* PSR2 needs frame sync as well */
3862 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3863 DRM_DEBUG_KMS("PSR2 %s on sink",
3864 dev_priv->psr.psr2_support ? "supported" : "not supported");
3865 }
50003939
JN		 3866 }
3867
7809a611 3868 /* Training Pattern 3 support, both source and sink */
06ea66b6 3869 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
7809a611
JN		 3870 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3871 (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
06ea66b6 3872 intel_dp->use_tps3 = true;
f8d8a672 3873 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3874 } else
3875 intel_dp->use_tps3 = false;
3876
fc0f8e25
SJ		 3877 /* Intermediate frequency support */
3878 if (is_edp(intel_dp) &&
3879 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3880 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3881 (rev >= 0x03)) { /* eDp v1.4 or higher */
94ca719e 3882 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3883 int i;
3884
fc0f8e25
SJ		 3885 intel_dp_dpcd_read_wake(&intel_dp->aux,
3886 DP_SUPPORTED_LINK_RATES,
94ca719e
VS		 3887 sink_rates,
3888 sizeof(sink_rates));
ea2d8a42 3889
94ca719e
VS		 3890 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3891 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3892
3893 if (val == 0)
3894 break;
3895
af77b974
SJ		 3896 /* Value read is in kHz while drm clock is saved in deca-kHz */
3897 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3898 }
94ca719e 3899 intel_dp->num_sink_rates = i;
fc0f8e25 3900 }
0336400e
VS		 3901
3902 intel_dp_print_rates(intel_dp);
3903
edb39244
AJ		 3904 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3905 DP_DWN_STRM_PORT_PRESENT))
3906 return true; /* native DP sink */
3907
3908 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3909 return true; /* no per-port downstream info */
3910
9d1a1031
JN		 3911 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3912 intel_dp->downstream_ports,
3913 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3914 return false; /* downstream port status fetch failed */
3915
3916 return true;
92fd8fd1
KP		 3917}
3918
0d198328
AJ		 3919static void
3920intel_dp_probe_oui(struct intel_dp *intel_dp)
3921{
3922 u8 buf[3];
3923
3924 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3925 return;
3926
9d1a1031 3927 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3928 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3929 buf[0], buf[1], buf[2]);
3930
9d1a1031 3931 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3932 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3933 buf[0], buf[1], buf[2]);
3934}
3935
0e32b39c
DA		 3936static bool
3937intel_dp_probe_mst(struct intel_dp *intel_dp)
3938{
3939 u8 buf[1];
3940
3941 if (!intel_dp->can_mst)
3942 return false;
3943
3944 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3945 return false;
3946
0e32b39c
DA		 3947 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3948 if (buf[0] & DP_MST_CAP) {
3949 DRM_DEBUG_KMS("Sink is MST capable\n");
3950 intel_dp->is_mst = true;
3951 } else {
3952 DRM_DEBUG_KMS("Sink is not MST capable\n");
3953 intel_dp->is_mst = false;
3954 }
3955 }
0e32b39c
DA		 3956
3957 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3958 return intel_dp->is_mst;
3959}
3960
d2e216d0
RV		 3961int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3962{
3963 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3964 struct drm_device *dev = intel_dig_port->base.base.dev;
3965 struct intel_crtc *intel_crtc =
3966 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3967 u8 buf;
3968 int test_crc_count;
3969 int attempts = 6;
4373f0f2 3970 int ret = 0;
d2e216d0 3971
4373f0f2 3972 hsw_disable_ips(intel_crtc);
d2e216d0 3973
4373f0f2
PZ		 3974 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) {
3975 ret = -EIO;
3976 goto out;
3977 }
3978
3979 if (!(buf & DP_TEST_CRC_SUPPORTED)) {
3980 ret = -ENOTTY;
3981 goto out;
3982 }
d2e216d0 3983
4373f0f2
PZ		 3984 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3985 ret = -EIO;
3986 goto out;
3987 }
1dda5f93 3988
9d1a1031 3989 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4373f0f2
PZ		 3990 buf | DP_TEST_SINK_START) < 0) {
3991 ret = -EIO;
3992 goto out;
3993 }
3994
3995 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) {
3996 ret = -EIO;
afe0d67e 3997 goto stop;
4373f0f2 3998 }
d2e216d0 3999
ad9dc91b 4000 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 4001
ad9dc91b 4002 do {
1dda5f93 4003 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 4004 DP_TEST_SINK_MISC, &buf) < 0) {
4005 ret = -EIO;
afe0d67e 4006 goto stop;
4373f0f2 4007 }
ad9dc91b
RV		 4008 intel_wait_for_vblank(dev, intel_crtc->pipe);
4009 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
4010
4011 if (attempts == 0) {
90bd1f46 4012 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
4373f0f2 4013 ret = -ETIMEDOUT;
afe0d67e 4014 goto stop;
ad9dc91b 4015 }
d2e216d0 4016
4373f0f2
PZ		 4017 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4018 ret = -EIO;
afe0d67e 4019 goto stop;
4373f0f2 4020 }
d2e216d0 4021
afe0d67e 4022stop:
4373f0f2 4023 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
dcc13bcb 4024 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
4373f0f2
PZ		 4025 goto out;
4026 }
1dda5f93 4027 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4373f0f2 4028 buf & ~DP_TEST_SINK_START) < 0) {
dcc13bcb 4029 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
4373f0f2
PZ		 4030 goto out;
4031 }
4032out:
4033 hsw_enable_ips(intel_crtc);
4034 return ret;
d2e216d0
RV		 4035}
4036
a60f0e38
JB		 4037static bool
4038intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4039{
9d1a1031
JN		 4040 return intel_dp_dpcd_read_wake(&intel_dp->aux,
4041 DP_DEVICE_SERVICE_IRQ_VECTOR,
4042 sink_irq_vector, 1) == 1;
a60f0e38
JB		 4043}
4044
0e32b39c
DA		 4045static bool
4046intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4047{
4048 int ret;
4049
4050 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4051 DP_SINK_COUNT_ESI,
4052 sink_irq_vector, 14);
4053 if (ret != 14)
4054 return false;
4055
4056 return true;
4057}
4058
c5d5ab7a
TP		 4059static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4060{
4061 uint8_t test_result = DP_TEST_ACK;
4062 return test_result;
4063}
4064
4065static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4066{
4067 uint8_t test_result = DP_TEST_NAK;
4068 return test_result;
4069}
4070
4071static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 4072{
c5d5ab7a 4073 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 4074 struct intel_connector *intel_connector = intel_dp->attached_connector;
4075 struct drm_connector *connector = &intel_connector->base;
4076
4077 if (intel_connector->detect_edid == NULL ||
ac6f2e29 4078 connector->edid_corrupt ||
559be30c
TP		 4079 intel_dp->aux.i2c_defer_count > 6) {
4080 /* Check EDID read for NACKs, DEFERs and corruption
4081 * (DP CTS 1.2 Core r1.1)
4082 * 4.2.2.4 : Failed EDID read, I2C_NAK
4083 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4084 * 4.2.2.6 : EDID corruption detected
4085 * Use failsafe mode for all cases
4086 */
4087 if (intel_dp->aux.i2c_nack_count > 0 ||
4088 intel_dp->aux.i2c_defer_count > 0)
4089 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4090 intel_dp->aux.i2c_nack_count,
4091 intel_dp->aux.i2c_defer_count);
4092 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4093 } else {
4094 if (!drm_dp_dpcd_write(&intel_dp->aux,
4095 DP_TEST_EDID_CHECKSUM,
4096 &intel_connector->detect_edid->checksum,
5a1cc655 4097 1))
559be30c
TP		 4098 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4099
4100 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4101 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4102 }
4103
4104 /* Set test active flag here so userspace doesn't interrupt things */
4105 intel_dp->compliance_test_active = 1;
4106
c5d5ab7a
TP		 4107 return test_result;
4108}
4109
4110static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 4111{
c5d5ab7a
TP		 4112 uint8_t test_result = DP_TEST_NAK;
4113 return test_result;
4114}
4115
4116static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4117{
4118 uint8_t response = DP_TEST_NAK;
4119 uint8_t rxdata = 0;
4120 int status = 0;
4121
559be30c 4122 intel_dp->compliance_test_active = 0;
c5d5ab7a 4123 intel_dp->compliance_test_type = 0;
559be30c
TP		 4124 intel_dp->compliance_test_data = 0;
4125
c5d5ab7a
TP		 4126 intel_dp->aux.i2c_nack_count = 0;
4127 intel_dp->aux.i2c_defer_count = 0;
4128
4129 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4130 if (status <= 0) {
4131 DRM_DEBUG_KMS("Could not read test request from sink\n");
4132 goto update_status;
4133 }
4134
4135 switch (rxdata) {
4136 case DP_TEST_LINK_TRAINING:
4137 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4138 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4139 response = intel_dp_autotest_link_training(intel_dp);
4140 break;
4141 case DP_TEST_LINK_VIDEO_PATTERN:
4142 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4143 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4144 response = intel_dp_autotest_video_pattern(intel_dp);
4145 break;
4146 case DP_TEST_LINK_EDID_READ:
4147 DRM_DEBUG_KMS("EDID test requested\n");
4148 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4149 response = intel_dp_autotest_edid(intel_dp);
4150 break;
4151 case DP_TEST_LINK_PHY_TEST_PATTERN:
4152 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4153 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4154 response = intel_dp_autotest_phy_pattern(intel_dp);
4155 break;
4156 default:
4157 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4158 break;
4159 }
4160
4161update_status:
4162 status = drm_dp_dpcd_write(&intel_dp->aux,
4163 DP_TEST_RESPONSE,
4164 &response, 1);
4165 if (status <= 0)
4166 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 4167}
4168
0e32b39c
DA		 4169static int
4170intel_dp_check_mst_status(struct intel_dp *intel_dp)
4171{
4172 bool bret;
4173
4174 if (intel_dp->is_mst) {
4175 u8 esi[16] = { 0 };
4176 int ret = 0;
4177 int retry;
4178 bool handled;
4179 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4180go_again:
4181 if (bret == true) {
4182
4183 /* check link status - esi[10] = 0x200c */
4184 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4185 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4186 intel_dp_start_link_train(intel_dp);
4187 intel_dp_complete_link_train(intel_dp);
4188 intel_dp_stop_link_train(intel_dp);
4189 }
4190
6f34cc39 4191 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 4192 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4193
4194 if (handled) {
4195 for (retry = 0; retry < 3; retry++) {
4196 int wret;
4197 wret = drm_dp_dpcd_write(&intel_dp->aux,
4198 DP_SINK_COUNT_ESI+1,
4199 &esi[1], 3);
4200 if (wret == 3) {
4201 break;
4202 }
4203 }
4204
4205 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4206 if (bret == true) {
6f34cc39 4207 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 4208 goto go_again;
4209 }
4210 } else
4211 ret = 0;
4212
4213 return ret;
4214 } else {
4215 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4216 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4217 intel_dp->is_mst = false;
4218 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4219 /* send a hotplug event */
4220 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4221 }
4222 }
4223 return -EINVAL;
4224}
4225
a4fc5ed6
KP		 4226/*
4227 * According to DP spec
4228 * 5.1.2:
4229 * 1. Read DPCD
4230 * 2. Configure link according to Receiver Capabilities
4231 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4232 * 4. Check link status on receipt of hot-plug interrupt
4233 */
a5146200 4234static void
ea5b213a 4235intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4236{
5b215bcf 4237 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4238 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4239 u8 sink_irq_vector;
93f62dad 4240 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4241
5b215bcf
DA		 4242 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4243
da63a9f2 4244 if (!intel_encoder->connectors_active)
d2b996ac 4245 return;
59cd09e1 4246
da63a9f2 4247 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4248 return;
4249
1a125d8a
ID		 4250 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4251 return;
4252
92fd8fd1 4253 /* Try to read receiver status if the link appears to be up */
93f62dad 4254 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4255 return;
4256 }
4257
92fd8fd1 4258 /* Now read the DPCD to see if it's actually running */
26d61aad 4259 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4260 return;
4261 }
4262
a60f0e38
JB		 4263 /* Try to read the source of the interrupt */
4264 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4265 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4266 /* Clear interrupt source */
9d1a1031
JN		 4267 drm_dp_dpcd_writeb(&intel_dp->aux,
4268 DP_DEVICE_SERVICE_IRQ_VECTOR,
4269 sink_irq_vector);
a60f0e38
JB		 4270
4271 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 4272 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 4273 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4274 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4275 }
4276
1ffdff13 4277 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4278 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4279 intel_encoder->base.name);
33a34e4e
JB		 4280 intel_dp_start_link_train(intel_dp);
4281 intel_dp_complete_link_train(intel_dp);
3ab9c637 4282 intel_dp_stop_link_train(intel_dp);
33a34e4e 4283 }
a4fc5ed6 4284}
a4fc5ed6 4285
caf9ab24 4286/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4287static enum drm_connector_status
26d61aad 4288intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4289{
caf9ab24 4290 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4291 uint8_t type;
4292
4293 if (!intel_dp_get_dpcd(intel_dp))
4294 return connector_status_disconnected;
4295
4296 /* if there's no downstream port, we're done */
4297 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4298 return connector_status_connected;
caf9ab24
AJ		 4299
4300 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4301 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4302 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4303 uint8_t reg;
9d1a1031
JN		 4304
4305 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4306 &reg, 1) < 0)
caf9ab24 4307 return connector_status_unknown;
9d1a1031 4308
23235177
AJ		 4309 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4310 : connector_status_disconnected;
caf9ab24
AJ		 4311 }
4312
4313 /* If no HPD, poke DDC gently */
0b99836f 4314 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4315 return connector_status_connected;
caf9ab24
AJ		 4316
4317 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4318 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4319 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4320 if (type == DP_DS_PORT_TYPE_VGA ||
4321 type == DP_DS_PORT_TYPE_NON_EDID)
4322 return connector_status_unknown;
4323 } else {
4324 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4325 DP_DWN_STRM_PORT_TYPE_MASK;
4326 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4327 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4328 return connector_status_unknown;
4329 }
caf9ab24
AJ		 4330
4331 /* Anything else is out of spec, warn and ignore */
4332 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4333 return connector_status_disconnected;
71ba9000
AJ		 4334}
4335
d410b56d
CW		 4336static enum drm_connector_status
4337edp_detect(struct intel_dp *intel_dp)
4338{
4339 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4340 enum drm_connector_status status;
4341
4342 status = intel_panel_detect(dev);
4343 if (status == connector_status_unknown)
4344 status = connector_status_connected;
4345
4346 return status;
4347}
4348
5eb08b69 4349static enum drm_connector_status
a9756bb5 4350ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4351{
30add22d 4352 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4353 struct drm_i915_private *dev_priv = dev->dev_private;
4354 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4355
1b469639
DL		 4356 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4357 return connector_status_disconnected;
4358
26d61aad 4359 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4360}
4361
2a592bec
DA		 4362static int g4x_digital_port_connected(struct drm_device *dev,
4363 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4364{
a4fc5ed6 4365 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4366 uint32_t bit;
5eb08b69 4367
232a6ee9
TP		 4368 if (IS_VALLEYVIEW(dev)) {
4369 switch (intel_dig_port->port) {
4370 case PORT_B:
4371 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4372 break;
4373 case PORT_C:
4374 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4375 break;
4376 case PORT_D:
4377 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4378 break;
4379 default:
2a592bec 4380 return -EINVAL;
232a6ee9
TP		 4381 }
4382 } else {
4383 switch (intel_dig_port->port) {
4384 case PORT_B:
4385 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4386 break;
4387 case PORT_C:
4388 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4389 break;
4390 case PORT_D:
4391 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4392 break;
4393 default:
2a592bec 4394 return -EINVAL;
232a6ee9 4395 }
a4fc5ed6
KP		 4396 }
4397
10f76a38 4398 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4399 return 0;
4400 return 1;
4401}
4402
4403static enum drm_connector_status
4404g4x_dp_detect(struct intel_dp *intel_dp)
4405{
4406 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4407 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4408 int ret;
4409
4410 /* Can't disconnect eDP, but you can close the lid... */
4411 if (is_edp(intel_dp)) {
4412 enum drm_connector_status status;
4413
4414 status = intel_panel_detect(dev);
4415 if (status == connector_status_unknown)
4416 status = connector_status_connected;
4417 return status;
4418 }
4419
4420 ret = g4x_digital_port_connected(dev, intel_dig_port);
4421 if (ret == -EINVAL)
4422 return connector_status_unknown;
4423 else if (ret == 0)
a4fc5ed6
KP		 4424 return connector_status_disconnected;
4425
26d61aad 4426 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4427}
4428
8c241fef 4429static struct edid *
beb60608 4430intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4431{
beb60608 4432 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4433
9cd300e0
JN		 4434 /* use cached edid if we have one */
4435 if (intel_connector->edid) {
9cd300e0
JN		 4436 /* invalid edid */
4437 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4438 return NULL;
4439
55e9edeb 4440 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4441 } else
4442 return drm_get_edid(&intel_connector->base,
4443 &intel_dp->aux.ddc);
4444}
8c241fef 4445
beb60608
CW		 4446static void
4447intel_dp_set_edid(struct intel_dp *intel_dp)
4448{
4449 struct intel_connector *intel_connector = intel_dp->attached_connector;
4450 struct edid *edid;
8c241fef 4451
beb60608
CW		 4452 edid = intel_dp_get_edid(intel_dp);
4453 intel_connector->detect_edid = edid;
4454
4455 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4456 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4457 else
4458 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4459}
4460
beb60608
CW		 4461static void
4462intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4463{
beb60608 4464 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4465
beb60608
CW		 4466 kfree(intel_connector->detect_edid);
4467 intel_connector->detect_edid = NULL;
9cd300e0 4468
beb60608
CW		 4469 intel_dp->has_audio = false;
4470}
d6f24d0f 4471
beb60608
CW		 4472static enum intel_display_power_domain
4473intel_dp_power_get(struct intel_dp *dp)
4474{
4475 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4476 enum intel_display_power_domain power_domain;
4477
4478 power_domain = intel_display_port_power_domain(encoder);
4479 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4480
4481 return power_domain;
4482}
d6f24d0f 4483
beb60608
CW		 4484static void
4485intel_dp_power_put(struct intel_dp *dp,
4486 enum intel_display_power_domain power_domain)
4487{
4488 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4489 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4490}
4491
a9756bb5
ZW		 4492static enum drm_connector_status
4493intel_dp_detect(struct drm_connector *connector, bool force)
4494{
4495 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4496 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4497 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4498 struct drm_device *dev = connector->dev;
a9756bb5 4499 enum drm_connector_status status;
671dedd2 4500 enum intel_display_power_domain power_domain;
0e32b39c 4501 bool ret;
09b1eb13 4502 u8 sink_irq_vector;
a9756bb5 4503
164c8598 4504 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4505 connector->base.id, connector->name);
beb60608 4506 intel_dp_unset_edid(intel_dp);
164c8598 4507
0e32b39c
DA		 4508 if (intel_dp->is_mst) {
4509 /* MST devices are disconnected from a monitor POV */
4510 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4511 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4512 return connector_status_disconnected;
0e32b39c
DA		 4513 }
4514
beb60608 4515 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4516
d410b56d
CW		 4517 /* Can't disconnect eDP, but you can close the lid... */
4518 if (is_edp(intel_dp))
4519 status = edp_detect(intel_dp);
4520 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4521 status = ironlake_dp_detect(intel_dp);
4522 else
4523 status = g4x_dp_detect(intel_dp);
4524 if (status != connector_status_connected)
c8c8fb33 4525 goto out;
a9756bb5 4526
0d198328
AJ		 4527 intel_dp_probe_oui(intel_dp);
4528
0e32b39c
DA		 4529 ret = intel_dp_probe_mst(intel_dp);
4530 if (ret) {
4531 /* if we are in MST mode then this connector
4532 won't appear connected or have anything with EDID on it */
4533 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4534 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4535 status = connector_status_disconnected;
4536 goto out;
4537 }
4538
beb60608 4539 intel_dp_set_edid(intel_dp);
a9756bb5 4540
d63885da
PZ		 4541 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4542 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4543 status = connector_status_connected;
4544
09b1eb13
TP		 4545 /* Try to read the source of the interrupt */
4546 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4547 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4548 /* Clear interrupt source */
4549 drm_dp_dpcd_writeb(&intel_dp->aux,
4550 DP_DEVICE_SERVICE_IRQ_VECTOR,
4551 sink_irq_vector);
4552
4553 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4554 intel_dp_handle_test_request(intel_dp);
4555 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4556 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4557 }
4558
c8c8fb33 4559out:
beb60608 4560 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4561 return status;
a4fc5ed6
KP		 4562}
4563
beb60608
CW		 4564static void
4565intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4566{
df0e9248 4567 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4568 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4569 enum intel_display_power_domain power_domain;
a4fc5ed6 4570
beb60608
CW		 4571 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4572 connector->base.id, connector->name);
4573 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4574
beb60608
CW		 4575 if (connector->status != connector_status_connected)
4576 return;
671dedd2 4577
beb60608
CW		 4578 power_domain = intel_dp_power_get(intel_dp);
4579
4580 intel_dp_set_edid(intel_dp);
4581
4582 intel_dp_power_put(intel_dp, power_domain);
4583
4584 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4585 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4586}
4587
4588static int intel_dp_get_modes(struct drm_connector *connector)
4589{
4590 struct intel_connector *intel_connector = to_intel_connector(connector);
4591 struct edid *edid;
4592
4593 edid = intel_connector->detect_edid;
4594 if (edid) {
4595 int ret = intel_connector_update_modes(connector, edid);
4596 if (ret)
4597 return ret;
4598 }
32f9d658 4599
f8779fda 4600 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4601 if (is_edp(intel_attached_dp(connector)) &&
4602 intel_connector->panel.fixed_mode) {
f8779fda 4603 struct drm_display_mode *mode;
beb60608
CW		 4604
4605 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4606 intel_connector->panel.fixed_mode);
f8779fda 4607 if (mode) {
32f9d658
ZW		 4608 drm_mode_probed_add(connector, mode);
4609 return 1;
4610 }
4611 }
beb60608 4612
32f9d658 4613 return 0;
a4fc5ed6
KP		 4614}
4615
1aad7ac0
CW		 4616static bool
4617intel_dp_detect_audio(struct drm_connector *connector)
4618{
1aad7ac0 4619 bool has_audio = false;
beb60608 4620 struct edid *edid;
1aad7ac0 4621
beb60608
CW		 4622 edid = to_intel_connector(connector)->detect_edid;
4623 if (edid)
1aad7ac0 4624 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4625
1aad7ac0
CW		 4626 return has_audio;
4627}
4628
f684960e
CW		 4629static int
4630intel_dp_set_property(struct drm_connector *connector,
4631 struct drm_property *property,
4632 uint64_t val)
4633{
e953fd7b 4634 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4635 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4636 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4637 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4638 int ret;
4639
662595df 4640 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4641 if (ret)
4642 return ret;
4643
3f43c48d 4644 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4645 int i = val;
4646 bool has_audio;
4647
4648 if (i == intel_dp->force_audio)
f684960e
CW		 4649 return 0;
4650
1aad7ac0 4651 intel_dp->force_audio = i;
f684960e 4652
c3e5f67b 4653 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4654 has_audio = intel_dp_detect_audio(connector);
4655 else
c3e5f67b 4656 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4657
4658 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4659 return 0;
4660
1aad7ac0 4661 intel_dp->has_audio = has_audio;
f684960e
CW		 4662 goto done;
4663 }
4664
e953fd7b 4665 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4666 bool old_auto = intel_dp->color_range_auto;
4667 uint32_t old_range = intel_dp->color_range;
4668
55bc60db
VS		 4669 switch (val) {
4670 case INTEL_BROADCAST_RGB_AUTO:
4671 intel_dp->color_range_auto = true;
4672 break;
4673 case INTEL_BROADCAST_RGB_FULL:
4674 intel_dp->color_range_auto = false;
4675 intel_dp->color_range = 0;
4676 break;
4677 case INTEL_BROADCAST_RGB_LIMITED:
4678 intel_dp->color_range_auto = false;
4679 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4680 break;
4681 default:
4682 return -EINVAL;
4683 }
ae4edb80
DV		 4684
4685 if (old_auto == intel_dp->color_range_auto &&
4686 old_range == intel_dp->color_range)
4687 return 0;
4688
e953fd7b
CW		 4689 goto done;
4690 }
4691
53b41837
YN		 4692 if (is_edp(intel_dp) &&
4693 property == connector->dev->mode_config.scaling_mode_property) {
4694 if (val == DRM_MODE_SCALE_NONE) {
4695 DRM_DEBUG_KMS("no scaling not supported\n");
4696 return -EINVAL;
4697 }
4698
4699 if (intel_connector->panel.fitting_mode == val) {
4700 /* the eDP scaling property is not changed */
4701 return 0;
4702 }
4703 intel_connector->panel.fitting_mode = val;
4704
4705 goto done;
4706 }
4707
f684960e
CW		 4708 return -EINVAL;
4709
4710done:
c0c36b94
CW		 4711 if (intel_encoder->base.crtc)
4712 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4713
4714 return 0;
4715}
4716
a4fc5ed6 4717static void
73845adf 4718intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4719{
1d508706 4720 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4721
10e972d3 4722 kfree(intel_connector->detect_edid);
beb60608 4723
9cd300e0
JN		 4724 if (!IS_ERR_OR_NULL(intel_connector->edid))
4725 kfree(intel_connector->edid);
4726
acd8db10
PZ		 4727 /* Can't call is_edp() since the encoder may have been destroyed
4728 * already. */
4729 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4730 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4731
a4fc5ed6 4732 drm_connector_cleanup(connector);
55f78c43 4733 kfree(connector);
a4fc5ed6
KP		 4734}
4735
00c09d70 4736void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4737{
da63a9f2
PZ		 4738 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4739 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4740
4f71d0cb 4741 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4742 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4743 if (is_edp(intel_dp)) {
4744 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4745 /*
4746 * vdd might still be enabled do to the delayed vdd off.
4747 * Make sure vdd is actually turned off here.
4748 */
773538e8 4749 pps_lock(intel_dp);
4be73780 4750 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4751 pps_unlock(intel_dp);
4752
01527b31
CT		 4753 if (intel_dp->edp_notifier.notifier_call) {
4754 unregister_reboot_notifier(&intel_dp->edp_notifier);
4755 intel_dp->edp_notifier.notifier_call = NULL;
4756 }
bd943159 4757 }
c8bd0e49 4758 drm_encoder_cleanup(encoder);
da63a9f2 4759 kfree(intel_dig_port);
24d05927
DV		 4760}
4761
07f9cd0b
ID		 4762static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4763{
4764 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4765
4766 if (!is_edp(intel_dp))
4767 return;
4768
951468f3
VS		 4769 /*
4770 * vdd might still be enabled do to the delayed vdd off.
4771 * Make sure vdd is actually turned off here.
4772 */
afa4e53a 4773 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4774 pps_lock(intel_dp);
07f9cd0b 4775 edp_panel_vdd_off_sync(intel_dp);
773538e8 4776 pps_unlock(intel_dp);
07f9cd0b
ID		 4777}
4778
49e6bc51
VS		 4779static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4780{
4781 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4782 struct drm_device *dev = intel_dig_port->base.base.dev;
4783 struct drm_i915_private *dev_priv = dev->dev_private;
4784 enum intel_display_power_domain power_domain;
4785
4786 lockdep_assert_held(&dev_priv->pps_mutex);
4787
4788 if (!edp_have_panel_vdd(intel_dp))
4789 return;
4790
4791 /*
4792 * The VDD bit needs a power domain reference, so if the bit is
4793 * already enabled when we boot or resume, grab this reference and
4794 * schedule a vdd off, so we don't hold on to the reference
4795 * indefinitely.
4796 */
4797 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4798 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4799 intel_display_power_get(dev_priv, power_domain);
4800
4801 edp_panel_vdd_schedule_off(intel_dp);
4802}
4803
6d93c0c4
ID		 4804static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4805{
49e6bc51
VS		 4806 struct intel_dp *intel_dp;
4807
4808 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4809 return;
4810
4811 intel_dp = enc_to_intel_dp(encoder);
4812
4813 pps_lock(intel_dp);
4814
4815 /*
4816 * Read out the current power sequencer assignment,
4817 * in case the BIOS did something with it.
4818 */
4819 if (IS_VALLEYVIEW(encoder->dev))
4820 vlv_initial_power_sequencer_setup(intel_dp);
4821
4822 intel_edp_panel_vdd_sanitize(intel_dp);
4823
4824 pps_unlock(intel_dp);
6d93c0c4
ID		 4825}
4826
a4fc5ed6 4827static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4828 .dpms = intel_connector_dpms,
a4fc5ed6 4829 .detect = intel_dp_detect,
beb60608 4830 .force = intel_dp_force,
a4fc5ed6 4831 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4832 .set_property = intel_dp_set_property,
2545e4a6 4833 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4834 .destroy = intel_dp_connector_destroy,
c6f95f27 4835 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4836 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4837};
4838
4839static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4840 .get_modes = intel_dp_get_modes,
4841 .mode_valid = intel_dp_mode_valid,
df0e9248 4842 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4843};
4844
a4fc5ed6 4845static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4846 .reset = intel_dp_encoder_reset,
24d05927 4847 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4848};
4849
b2c5c181 4850enum irqreturn
13cf5504
DA		 4851intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4852{
4853 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4854 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4855 struct drm_device *dev = intel_dig_port->base.base.dev;
4856 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4857 enum intel_display_power_domain power_domain;
b2c5c181 4858 enum irqreturn ret = IRQ_NONE;
1c767b33 4859
0e32b39c
DA		 4860 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4861 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4862
7a7f84cc
VS		 4863 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4864 /*
4865 * vdd off can generate a long pulse on eDP which
4866 * would require vdd on to handle it, and thus we
4867 * would end up in an endless cycle of
4868 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4869 */
4870 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4871 port_name(intel_dig_port->port));
a8b3d52f 4872 return IRQ_HANDLED;
7a7f84cc
VS		 4873 }
4874
26fbb774
VS		 4875 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4876 port_name(intel_dig_port->port),
0e32b39c 4877 long_hpd ? "long" : "short");
13cf5504 4878
1c767b33
ID		 4879 power_domain = intel_display_port_power_domain(intel_encoder);
4880 intel_display_power_get(dev_priv, power_domain);
4881
0e32b39c 4882 if (long_hpd) {
5fa836a9
MK		 4883 /* indicate that we need to restart link training */
4884 intel_dp->train_set_valid = false;
2a592bec
DA		 4885
4886 if (HAS_PCH_SPLIT(dev)) {
4887 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4888 goto mst_fail;
4889 } else {
4890 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4891 goto mst_fail;
4892 }
0e32b39c
DA		 4893
4894 if (!intel_dp_get_dpcd(intel_dp)) {
4895 goto mst_fail;
4896 }
4897
4898 intel_dp_probe_oui(intel_dp);
4899
4900 if (!intel_dp_probe_mst(intel_dp))
4901 goto mst_fail;
4902
4903 } else {
4904 if (intel_dp->is_mst) {
1c767b33 4905 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4906 goto mst_fail;
4907 }
4908
4909 if (!intel_dp->is_mst) {
4910 /*
4911 * we'll check the link status via the normal hot plug path later -
4912 * but for short hpds we should check it now
4913 */
5b215bcf 4914 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4915 intel_dp_check_link_status(intel_dp);
5b215bcf 4916 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4917 }
4918 }
b2c5c181
DV		 4919
4920 ret = IRQ_HANDLED;
4921
1c767b33 4922 goto put_power;
0e32b39c
DA		 4923mst_fail:
4924 /* if we were in MST mode, and device is not there get out of MST mode */
4925 if (intel_dp->is_mst) {
4926 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4927 intel_dp->is_mst = false;
4928 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4929 }
1c767b33
ID		 4930put_power:
4931 intel_display_power_put(dev_priv, power_domain);
4932
4933 return ret;
13cf5504
DA		 4934}
4935
e3421a18
ZW		 4936/* Return which DP Port should be selected for Transcoder DP control */
4937int
0206e353 4938intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4939{
4940 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4941 struct intel_encoder *intel_encoder;
4942 struct intel_dp *intel_dp;
e3421a18 4943
fa90ecef
PZ		 4944 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4945 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4946
fa90ecef
PZ		 4947 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4948 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4949 return intel_dp->output_reg;
e3421a18 4950 }
ea5b213a 4951
e3421a18
ZW		 4952 return -1;
4953}
4954
36e83a18 4955/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4956bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4957{
4958 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4959 union child_device_config *p_child;
36e83a18 4960 int i;
5d8a7752
VS		 4961 static const short port_mapping[] = {
4962 [PORT_B] = PORT_IDPB,
4963 [PORT_C] = PORT_IDPC,
4964 [PORT_D] = PORT_IDPD,
4965 };
36e83a18 4966
3b32a35b
VS		 4967 if (port == PORT_A)
4968 return true;
4969
41aa3448 4970 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4971 return false;
4972
41aa3448
RV		 4973 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4974 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4975
5d8a7752 4976 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4977 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4978 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4979 return true;
4980 }
4981 return false;
4982}
4983
0e32b39c 4984void
f684960e
CW		 4985intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4986{
53b41837
YN		 4987 struct intel_connector *intel_connector = to_intel_connector(connector);
4988
3f43c48d 4989 intel_attach_force_audio_property(connector);
e953fd7b 4990 intel_attach_broadcast_rgb_property(connector);
55bc60db 4991 intel_dp->color_range_auto = true;
53b41837
YN		 4992
4993 if (is_edp(intel_dp)) {
4994 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4995 drm_object_attach_property(
4996 &connector->base,
53b41837 4997 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4998 DRM_MODE_SCALE_ASPECT);
4999 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 5000 }
f684960e
CW		 5001}
5002
dada1a9f
ID		 5003static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5004{
5005 intel_dp->last_power_cycle = jiffies;
5006 intel_dp->last_power_on = jiffies;
5007 intel_dp->last_backlight_off = jiffies;
5008}
5009
67a54566
DV		 5010static void
5011intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 5012 struct intel_dp *intel_dp)
67a54566
DV		 5013{
5014 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 5015 struct edp_power_seq cur, vbt, spec,
5016 *final = &intel_dp->pps_delays;
b0a08bec
VK		 5017 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5018 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;
453c5420 5019
e39b999a
VS		 5020 lockdep_assert_held(&dev_priv->pps_mutex);
5021
81ddbc69
VS		 5022 /* already initialized? */
5023 if (final->t11_t12 != 0)
5024 return;
5025
b0a08bec
VK		 5026 if (IS_BROXTON(dev)) {
5027 /*
5028 * TODO: BXT has 2 sets of PPS registers.
5029 * Correct Register for Broxton need to be identified
5030 * using VBT. hardcoding for now
5031 */
5032 pp_ctrl_reg = BXT_PP_CONTROL(0);
5033 pp_on_reg = BXT_PP_ON_DELAYS(0);
5034 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5035 } else if (HAS_PCH_SPLIT(dev)) {
bf13e81b 5036 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 5037 pp_on_reg = PCH_PP_ON_DELAYS;
5038 pp_off_reg = PCH_PP_OFF_DELAYS;
5039 pp_div_reg = PCH_PP_DIVISOR;
5040 } else {
bf13e81b
JN		 5041 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5042
5043 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5044 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5045 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5046 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 5047 }
67a54566
DV		 5048
5049 /* Workaround: Need to write PP_CONTROL with the unlock key as
5050 * the very first thing. */
b0a08bec 5051 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 5052
453c5420
JB		 5053 pp_on = I915_READ(pp_on_reg);
5054 pp_off = I915_READ(pp_off_reg);
b0a08bec
VK		 5055 if (!IS_BROXTON(dev)) {
5056 I915_WRITE(pp_ctrl_reg, pp_ctl);
5057 pp_div = I915_READ(pp_div_reg);
5058 }
67a54566
DV		 5059
5060 /* Pull timing values out of registers */
5061 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5062 PANEL_POWER_UP_DELAY_SHIFT;
5063
5064 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5065 PANEL_LIGHT_ON_DELAY_SHIFT;
5066
5067 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5068 PANEL_LIGHT_OFF_DELAY_SHIFT;
5069
5070 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5071 PANEL_POWER_DOWN_DELAY_SHIFT;
5072
b0a08bec
VK		 5073 if (IS_BROXTON(dev)) {
5074 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5075 BXT_POWER_CYCLE_DELAY_SHIFT;
5076 if (tmp > 0)
5077 cur.t11_t12 = (tmp - 1) * 1000;
5078 else
5079 cur.t11_t12 = 0;
5080 } else {
5081 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 5082 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 5083 }
67a54566
DV		 5084
5085 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5086 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5087
41aa3448 5088 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 5089
5090 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5091 * our hw here, which are all in 100usec. */
5092 spec.t1_t3 = 210 * 10;
5093 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5094 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5095 spec.t10 = 500 * 10;
5096 /* This one is special and actually in units of 100ms, but zero
5097 * based in the hw (so we need to add 100 ms). But the sw vbt
5098 * table multiplies it with 1000 to make it in units of 100usec,
5099 * too. */
5100 spec.t11_t12 = (510 + 100) * 10;
5101
5102 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5103 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5104
5105 /* Use the max of the register settings and vbt. If both are
5106 * unset, fall back to the spec limits. */
36b5f425 5107#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 5108 spec.field : \
5109 max(cur.field, vbt.field))
5110 assign_final(t1_t3);
5111 assign_final(t8);
5112 assign_final(t9);
5113 assign_final(t10);
5114 assign_final(t11_t12);
5115#undef assign_final
5116
36b5f425 5117#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 5118 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5119 intel_dp->backlight_on_delay = get_delay(t8);
5120 intel_dp->backlight_off_delay = get_delay(t9);
5121 intel_dp->panel_power_down_delay = get_delay(t10);
5122 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5123#undef get_delay
5124
f30d26e4
JN		 5125 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5126 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5127 intel_dp->panel_power_cycle_delay);
5128
5129 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5130 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 5131}
5132
5133static void
5134intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 5135 struct intel_dp *intel_dp)
f30d26e4
JN		 5136{
5137 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 5138 u32 pp_on, pp_off, pp_div, port_sel = 0;
5139 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
b0a08bec 5140 int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;
ad933b56 5141 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 5142 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 5143
e39b999a 5144 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 5145
b0a08bec
VK		 5146 if (IS_BROXTON(dev)) {
5147 /*
5148 * TODO: BXT has 2 sets of PPS registers.
5149 * Correct Register for Broxton need to be identified
5150 * using VBT. hardcoding for now
5151 */
5152 pp_ctrl_reg = BXT_PP_CONTROL(0);
5153 pp_on_reg = BXT_PP_ON_DELAYS(0);
5154 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5155
5156 } else if (HAS_PCH_SPLIT(dev)) {
453c5420
JB		 5157 pp_on_reg = PCH_PP_ON_DELAYS;
5158 pp_off_reg = PCH_PP_OFF_DELAYS;
5159 pp_div_reg = PCH_PP_DIVISOR;
5160 } else {
bf13e81b
JN		 5161 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5162
5163 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5164 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5165 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 5166 }
5167
b2f19d1a
PZ		 5168 /*
5169 * And finally store the new values in the power sequencer. The
5170 * backlight delays are set to 1 because we do manual waits on them. For
5171 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5172 * we'll end up waiting for the backlight off delay twice: once when we
5173 * do the manual sleep, and once when we disable the panel and wait for
5174 * the PP_STATUS bit to become zero.
5175 */
f30d26e4 5176 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 5177 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5178 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5179 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5180 /* Compute the divisor for the pp clock, simply match the Bspec
5181 * formula. */
b0a08bec
VK		 5182 if (IS_BROXTON(dev)) {
5183 pp_div = I915_READ(pp_ctrl_reg);
5184 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5185 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5186 << BXT_POWER_CYCLE_DELAY_SHIFT);
5187 } else {
5188 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5189 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5190 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5191 }
67a54566
DV		 5192
5193 /* Haswell doesn't have any port selection bits for the panel
5194 * power sequencer any more. */
bc7d38a4 5195 if (IS_VALLEYVIEW(dev)) {
ad933b56 5196 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 5197 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 5198 if (port == PORT_A)
a24c144c 5199 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5200 else
a24c144c 5201 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5202 }
5203
453c5420
JB		 5204 pp_on |= port_sel;
5205
5206 I915_WRITE(pp_on_reg, pp_on);
5207 I915_WRITE(pp_off_reg, pp_off);
b0a08bec
VK		 5208 if (IS_BROXTON(dev))
5209 I915_WRITE(pp_ctrl_reg, pp_div);
5210 else
5211 I915_WRITE(pp_div_reg, pp_div);
67a54566 5212
67a54566 5213 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 5214 I915_READ(pp_on_reg),
5215 I915_READ(pp_off_reg),
b0a08bec
VK		 5216 IS_BROXTON(dev) ?
5217 (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
453c5420 5218 I915_READ(pp_div_reg));
f684960e
CW		 5219}
5220
b33a2815
VK		 5221/**
5222 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5223 * @dev: DRM device
5224 * @refresh_rate: RR to be programmed
5225 *
5226 * This function gets called when refresh rate (RR) has to be changed from
5227 * one frequency to another. Switches can be between high and low RR
5228 * supported by the panel or to any other RR based on media playback (in
5229 * this case, RR value needs to be passed from user space).
5230 *
5231 * The caller of this function needs to take a lock on dev_priv->drrs.
5232 */
96178eeb 5233static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 5234{
5235 struct drm_i915_private *dev_priv = dev->dev_private;
5236 struct intel_encoder *encoder;
96178eeb
VK		 5237 struct intel_digital_port *dig_port = NULL;
5238 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 5239 struct intel_crtc_state *config = NULL;
439d7ac0 5240 struct intel_crtc *intel_crtc = NULL;
439d7ac0 5241 u32 reg, val;
96178eeb 5242 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5243
5244 if (refresh_rate <= 0) {
5245 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5246 return;
5247 }
5248
96178eeb
VK		 5249 if (intel_dp == NULL) {
5250 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5251 return;
5252 }
5253
1fcc9d1c 5254 /*
e4d59f6b
RV		 5255 * FIXME: This needs proper synchronization with psr state for some
5256 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5257 */
439d7ac0 5258
96178eeb
VK		 5259 dig_port = dp_to_dig_port(intel_dp);
5260 encoder = &dig_port->base;
723f9aab 5261 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5262
5263 if (!intel_crtc) {
5264 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5265 return;
5266 }
5267
6e3c9717 5268 config = intel_crtc->config;
439d7ac0 5269
96178eeb 5270 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5271 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5272 return;
5273 }
5274
96178eeb
VK		 5275 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5276 refresh_rate)
439d7ac0
PB		 5277 index = DRRS_LOW_RR;
5278
96178eeb 5279 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5280 DRM_DEBUG_KMS(
5281 "DRRS requested for previously set RR...ignoring\n");
5282 return;
5283 }
5284
5285 if (!intel_crtc->active) {
5286 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5287 return;
5288 }
5289
44395bfe 5290 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5291 switch (index) {
5292 case DRRS_HIGH_RR:
5293 intel_dp_set_m_n(intel_crtc, M1_N1);
5294 break;
5295 case DRRS_LOW_RR:
5296 intel_dp_set_m_n(intel_crtc, M2_N2);
5297 break;
5298 case DRRS_MAX_RR:
5299 default:
5300 DRM_ERROR("Unsupported refreshrate type\n");
5301 }
5302 } else if (INTEL_INFO(dev)->gen > 6) {
6e3c9717 5303 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
439d7ac0 5304 val = I915_READ(reg);
a4c30b1d 5305
439d7ac0 5306 if (index > DRRS_HIGH_RR) {
6fa7aec1
VK		 5307 if (IS_VALLEYVIEW(dev))
5308 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5309 else
5310 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5311 } else {
6fa7aec1
VK		 5312 if (IS_VALLEYVIEW(dev))
5313 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5314 else
5315 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5316 }
5317 I915_WRITE(reg, val);
5318 }
5319
4e9ac947
VK		 5320 dev_priv->drrs.refresh_rate_type = index;
5321
5322 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5323}
5324
b33a2815
VK		 5325/**
5326 * intel_edp_drrs_enable - init drrs struct if supported
5327 * @intel_dp: DP struct
5328 *
5329 * Initializes frontbuffer_bits and drrs.dp
5330 */
c395578e
VK		 5331void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5332{
5333 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5334 struct drm_i915_private *dev_priv = dev->dev_private;
5335 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5336 struct drm_crtc *crtc = dig_port->base.base.crtc;
5337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5338
5339 if (!intel_crtc->config->has_drrs) {
5340 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5341 return;
5342 }
5343
5344 mutex_lock(&dev_priv->drrs.mutex);
5345 if (WARN_ON(dev_priv->drrs.dp)) {
5346 DRM_ERROR("DRRS already enabled\n");
5347 goto unlock;
5348 }
5349
5350 dev_priv->drrs.busy_frontbuffer_bits = 0;
5351
5352 dev_priv->drrs.dp = intel_dp;
5353
5354unlock:
5355 mutex_unlock(&dev_priv->drrs.mutex);
5356}
5357
b33a2815
VK		 5358/**
5359 * intel_edp_drrs_disable - Disable DRRS
5360 * @intel_dp: DP struct
5361 *
5362 */
c395578e
VK		 5363void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5364{
5365 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5366 struct drm_i915_private *dev_priv = dev->dev_private;
5367 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5368 struct drm_crtc *crtc = dig_port->base.base.crtc;
5369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5370
5371 if (!intel_crtc->config->has_drrs)
5372 return;
5373
5374 mutex_lock(&dev_priv->drrs.mutex);
5375 if (!dev_priv->drrs.dp) {
5376 mutex_unlock(&dev_priv->drrs.mutex);
5377 return;
5378 }
5379
5380 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5381 intel_dp_set_drrs_state(dev_priv->dev,
5382 intel_dp->attached_connector->panel.
5383 fixed_mode->vrefresh);
5384
5385 dev_priv->drrs.dp = NULL;
5386 mutex_unlock(&dev_priv->drrs.mutex);
5387
5388 cancel_delayed_work_sync(&dev_priv->drrs.work);
5389}
5390
4e9ac947
VK		 5391static void intel_edp_drrs_downclock_work(struct work_struct *work)
5392{
5393 struct drm_i915_private *dev_priv =
5394 container_of(work, typeof(*dev_priv), drrs.work.work);
5395 struct intel_dp *intel_dp;
5396
5397 mutex_lock(&dev_priv->drrs.mutex);
5398
5399 intel_dp = dev_priv->drrs.dp;
5400
5401 if (!intel_dp)
5402 goto unlock;
5403
439d7ac0 5404 /*
4e9ac947
VK		 5405 * The delayed work can race with an invalidate hence we need to
5406 * recheck.
439d7ac0
PB		 5407 */
5408
4e9ac947
VK		 5409 if (dev_priv->drrs.busy_frontbuffer_bits)
5410 goto unlock;
439d7ac0 5411
4e9ac947
VK		 5412 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5413 intel_dp_set_drrs_state(dev_priv->dev,
5414 intel_dp->attached_connector->panel.
5415 downclock_mode->vrefresh);
439d7ac0 5416
4e9ac947 5417unlock:
4e9ac947 5418 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5419}
5420
b33a2815 5421/**
0ddfd203 5422 * intel_edp_drrs_invalidate - Disable Idleness DRRS
b33a2815
VK		 5423 * @dev: DRM device
5424 * @frontbuffer_bits: frontbuffer plane tracking bits
5425 *
0ddfd203
R		 5426 * This function gets called everytime rendering on the given planes start.
5427 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5428 *
5429 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5430 */
a93fad0f
VK		 5431void intel_edp_drrs_invalidate(struct drm_device *dev,
5432 unsigned frontbuffer_bits)
5433{
5434 struct drm_i915_private *dev_priv = dev->dev_private;
5435 struct drm_crtc *crtc;
5436 enum pipe pipe;
5437
9da7d693 5438 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5439 return;
5440
88f933a8 5441 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5442
a93fad0f 5443 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5444 if (!dev_priv->drrs.dp) {
5445 mutex_unlock(&dev_priv->drrs.mutex);
5446 return;
5447 }
5448
a93fad0f
VK		 5449 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5450 pipe = to_intel_crtc(crtc)->pipe;
5451
c1d038c6
DV		 5452 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5453 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5454
0ddfd203 5455 /* invalidate means busy screen hence upclock */
c1d038c6 5456 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
a93fad0f
VK		 5457 intel_dp_set_drrs_state(dev_priv->dev,
5458 dev_priv->drrs.dp->attached_connector->panel.
5459 fixed_mode->vrefresh);
a93fad0f 5460
a93fad0f
VK		 5461 mutex_unlock(&dev_priv->drrs.mutex);
5462}
5463
b33a2815 5464/**
0ddfd203 5465 * intel_edp_drrs_flush - Restart Idleness DRRS
b33a2815
VK		 5466 * @dev: DRM device
5467 * @frontbuffer_bits: frontbuffer plane tracking bits
5468 *
0ddfd203
R		 5469 * This function gets called every time rendering on the given planes has
5470 * completed or flip on a crtc is completed. So DRRS should be upclocked
5471 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5472 * if no other planes are dirty.
b33a2815
VK		 5473 *
5474 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5475 */
a93fad0f
VK		 5476void intel_edp_drrs_flush(struct drm_device *dev,
5477 unsigned frontbuffer_bits)
5478{
5479 struct drm_i915_private *dev_priv = dev->dev_private;
5480 struct drm_crtc *crtc;
5481 enum pipe pipe;
5482
9da7d693 5483 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5484 return;
5485
88f933a8 5486 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5487
a93fad0f 5488 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5489 if (!dev_priv->drrs.dp) {
5490 mutex_unlock(&dev_priv->drrs.mutex);
5491 return;
5492 }
5493
a93fad0f
VK		 5494 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5495 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5496
5497 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5498 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5499
0ddfd203 5500 /* flush means busy screen hence upclock */
c1d038c6 5501 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
0ddfd203
R		 5502 intel_dp_set_drrs_state(dev_priv->dev,
5503 dev_priv->drrs.dp->attached_connector->panel.
5504 fixed_mode->vrefresh);
5505
5506 /*
5507 * flush also means no more activity hence schedule downclock, if all
5508 * other fbs are quiescent too
5509 */
5510 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5511 schedule_delayed_work(&dev_priv->drrs.work,
5512 msecs_to_jiffies(1000));
5513 mutex_unlock(&dev_priv->drrs.mutex);
5514}
5515
b33a2815
VK		 5516/**
5517 * DOC: Display Refresh Rate Switching (DRRS)
5518 *
5519 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5520 * which enables swtching between low and high refresh rates,
5521 * dynamically, based on the usage scenario. This feature is applicable
5522 * for internal panels.
5523 *
5524 * Indication that the panel supports DRRS is given by the panel EDID, which
5525 * would list multiple refresh rates for one resolution.
5526 *
5527 * DRRS is of 2 types - static and seamless.
5528 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5529 * (may appear as a blink on screen) and is used in dock-undock scenario.
5530 * Seamless DRRS involves changing RR without any visual effect to the user
5531 * and can be used during normal system usage. This is done by programming
5532 * certain registers.
5533 *
5534 * Support for static/seamless DRRS may be indicated in the VBT based on
5535 * inputs from the panel spec.
5536 *
5537 * DRRS saves power by switching to low RR based on usage scenarios.
5538 *
5539 * eDP DRRS:-
5540 * The implementation is based on frontbuffer tracking implementation.
5541 * When there is a disturbance on the screen triggered by user activity or a
5542 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5543 * When there is no movement on screen, after a timeout of 1 second, a switch
5544 * to low RR is made.
5545 * For integration with frontbuffer tracking code,
5546 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5547 *
5548 * DRRS can be further extended to support other internal panels and also
5549 * the scenario of video playback wherein RR is set based on the rate
5550 * requested by userspace.
5551 */
5552
5553/**
5554 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5555 * @intel_connector: eDP connector
5556 * @fixed_mode: preferred mode of panel
5557 *
5558 * This function is called only once at driver load to initialize basic
5559 * DRRS stuff.
5560 *
5561 * Returns:
5562 * Downclock mode if panel supports it, else return NULL.
5563 * DRRS support is determined by the presence of downclock mode (apart
5564 * from VBT setting).
5565 */
4f9db5b5 5566static struct drm_display_mode *
96178eeb
VK		 5567intel_dp_drrs_init(struct intel_connector *intel_connector,
5568 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5569{
5570 struct drm_connector *connector = &intel_connector->base;
96178eeb 5571 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5572 struct drm_i915_private *dev_priv = dev->dev_private;
5573 struct drm_display_mode *downclock_mode = NULL;
5574
9da7d693
DV		 5575 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5576 mutex_init(&dev_priv->drrs.mutex);
5577
4f9db5b5
PB		 5578 if (INTEL_INFO(dev)->gen <= 6) {
5579 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5580 return NULL;
5581 }
5582
5583 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5584 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5585 return NULL;
5586 }
5587
5588 downclock_mode = intel_find_panel_downclock
5589 (dev, fixed_mode, connector);
5590
5591 if (!downclock_mode) {
a1d26342 5592 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5593 return NULL;
5594 }
5595
96178eeb 5596 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5597
96178eeb 5598 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5599 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5600 return downclock_mode;
5601}
5602
ed92f0b2 5603static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5604 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5605{
5606 struct drm_connector *connector = &intel_connector->base;
5607 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5608 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5609 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5610 struct drm_i915_private *dev_priv = dev->dev_private;
5611 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5612 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5613 bool has_dpcd;
5614 struct drm_display_mode *scan;
5615 struct edid *edid;
6517d273 5616 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5617
5618 if (!is_edp(intel_dp))
5619 return true;
5620
49e6bc51
VS		 5621 pps_lock(intel_dp);
5622 intel_edp_panel_vdd_sanitize(intel_dp);
5623 pps_unlock(intel_dp);
63635217 5624
ed92f0b2 5625 /* Cache DPCD and EDID for edp. */
ed92f0b2 5626 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5627
5628 if (has_dpcd) {
5629 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5630 dev_priv->no_aux_handshake =
5631 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5632 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5633 } else {
5634 /* if this fails, presume the device is a ghost */
5635 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5636 return false;
5637 }
5638
5639 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5640 pps_lock(intel_dp);
36b5f425 5641 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5642 pps_unlock(intel_dp);
ed92f0b2 5643
060c8778 5644 mutex_lock(&dev->mode_config.mutex);
0b99836f 5645 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5646 if (edid) {
5647 if (drm_add_edid_modes(connector, edid)) {
5648 drm_mode_connector_update_edid_property(connector,
5649 edid);
5650 drm_edid_to_eld(connector, edid);
5651 } else {
5652 kfree(edid);
5653 edid = ERR_PTR(-EINVAL);
5654 }
5655 } else {
5656 edid = ERR_PTR(-ENOENT);
5657 }
5658 intel_connector->edid = edid;
5659
5660 /* prefer fixed mode from EDID if available */
5661 list_for_each_entry(scan, &connector->probed_modes, head) {
5662 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5663 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5664 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5665 intel_connector, fixed_mode);
ed92f0b2
PZ		 5666 break;
5667 }
5668 }
5669
5670 /* fallback to VBT if available for eDP */
5671 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5672 fixed_mode = drm_mode_duplicate(dev,
5673 dev_priv->vbt.lfp_lvds_vbt_mode);
5674 if (fixed_mode)
5675 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5676 }
060c8778 5677 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5678
01527b31
CT		 5679 if (IS_VALLEYVIEW(dev)) {
5680 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5681 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5682
5683 /*
5684 * Figure out the current pipe for the initial backlight setup.
5685 * If the current pipe isn't valid, try the PPS pipe, and if that
5686 * fails just assume pipe A.
5687 */
5688 if (IS_CHERRYVIEW(dev))
5689 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5690 else
5691 pipe = PORT_TO_PIPE(intel_dp->DP);
5692
5693 if (pipe != PIPE_A && pipe != PIPE_B)
5694 pipe = intel_dp->pps_pipe;
5695
5696 if (pipe != PIPE_A && pipe != PIPE_B)
5697 pipe = PIPE_A;
5698
5699 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5700 pipe_name(pipe));
01527b31
CT		 5701 }
5702
4f9db5b5 5703 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5704 intel_connector->panel.backlight_power = intel_edp_backlight_power;
6517d273 5705 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5706
5707 return true;
5708}
5709
16c25533 5710bool
f0fec3f2
PZ		 5711intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5712 struct intel_connector *intel_connector)
a4fc5ed6 5713{
f0fec3f2
PZ		 5714 struct drm_connector *connector = &intel_connector->base;
5715 struct intel_dp *intel_dp = &intel_dig_port->dp;
5716 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5717 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5718 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5719 enum port port = intel_dig_port->port;
0b99836f 5720 int type;
a4fc5ed6 5721
a4a5d2f8
VS		 5722 intel_dp->pps_pipe = INVALID_PIPE;
5723
ec5b01dd 5724 /* intel_dp vfuncs */
b6b5e383
DL		 5725 if (INTEL_INFO(dev)->gen >= 9)
5726 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5727 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5728 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5729 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5730 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5731 else if (HAS_PCH_SPLIT(dev))
5732 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5733 else
5734 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5735
b9ca5fad
DL		 5736 if (INTEL_INFO(dev)->gen >= 9)
5737 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5738 else
5739 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5740
0767935e
DV		 5741 /* Preserve the current hw state. */
5742 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5743 intel_dp->attached_connector = intel_connector;
3d3dc149 5744
3b32a35b 5745 if (intel_dp_is_edp(dev, port))
b329530c 5746 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5747 else
5748 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5749
f7d24902
ID		 5750 /*
5751 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5752 * for DP the encoder type can be set by the caller to
5753 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5754 */
5755 if (type == DRM_MODE_CONNECTOR_eDP)
5756 intel_encoder->type = INTEL_OUTPUT_EDP;
5757
c17ed5b5
VS		 5758 /* eDP only on port B and/or C on vlv/chv */
5759 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5760 port != PORT_B && port != PORT_C))
5761 return false;
5762
e7281eab
ID		 5763 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5764 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5765 port_name(port));
5766
b329530c 5767 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5768 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5769
a4fc5ed6
KP		 5770 connector->interlace_allowed = true;
5771 connector->doublescan_allowed = 0;
5772
f0fec3f2 5773 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5774 edp_panel_vdd_work);
a4fc5ed6 5775
df0e9248 5776 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5777 drm_connector_register(connector);
a4fc5ed6 5778
affa9354 5779 if (HAS_DDI(dev))
bcbc889b
PZ		 5780 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5781 else
5782 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5783 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5784
0b99836f 5785 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5786 switch (port) {
5787 case PORT_A:
1d843f9d 5788 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5789 break;
5790 case PORT_B:
1d843f9d 5791 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5792 break;
5793 case PORT_C:
1d843f9d 5794 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5795 break;
5796 case PORT_D:
1d843f9d 5797 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5798 break;
5799 default:
ad1c0b19 5800 BUG();
5eb08b69
ZW		 5801 }
5802
dada1a9f 5803 if (is_edp(intel_dp)) {
773538e8 5804 pps_lock(intel_dp);
1e74a324
VS		 5805 intel_dp_init_panel_power_timestamps(intel_dp);
5806 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5807 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5808 else
36b5f425 5809 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5810 pps_unlock(intel_dp);
dada1a9f 5811 }
0095e6dc 5812
9d1a1031 5813 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5814
0e32b39c 5815 /* init MST on ports that can support it */
0c9b3715
JN		 5816 if (HAS_DP_MST(dev) &&
5817 (port == PORT_B || port == PORT_C || port == PORT_D))
5818 intel_dp_mst_encoder_init(intel_dig_port,
5819 intel_connector->base.base.id);
0e32b39c 5820
36b5f425 5821 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5822 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5823 if (is_edp(intel_dp)) {
5824 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5825 /*
5826 * vdd might still be enabled do to the delayed vdd off.
5827 * Make sure vdd is actually turned off here.
5828 */
773538e8 5829 pps_lock(intel_dp);
4be73780 5830 edp_panel_vdd_off_sync(intel_dp);
773538e8 5831 pps_unlock(intel_dp);
15b1d171 5832 }
34ea3d38 5833 drm_connector_unregister(connector);
b2f246a8 5834 drm_connector_cleanup(connector);
16c25533 5835 return false;
b2f246a8 5836 }
32f9d658 5837
f684960e
CW		 5838 intel_dp_add_properties(intel_dp, connector);
5839
a4fc5ed6
KP		 5840 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5841 * 0xd. Failure to do so will result in spurious interrupts being
5842 * generated on the port when a cable is not attached.
5843 */
5844 if (IS_G4X(dev) && !IS_GM45(dev)) {
5845 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5846 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5847 }
16c25533 5848
aa7471d2
JN		 5849 i915_debugfs_connector_add(connector);
5850
16c25533 5851 return true;
a4fc5ed6 5852}
f0fec3f2
PZ		 5853
5854void
5855intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5856{
13cf5504 5857 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5858 struct intel_digital_port *intel_dig_port;
5859 struct intel_encoder *intel_encoder;
5860 struct drm_encoder *encoder;
5861 struct intel_connector *intel_connector;
5862
b14c5679 5863 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5864 if (!intel_dig_port)
5865 return;
5866
08d9bc92 5867 intel_connector = intel_connector_alloc();
f0fec3f2
PZ		 5868 if (!intel_connector) {
5869 kfree(intel_dig_port);
5870 return;
5871 }
5872
5873 intel_encoder = &intel_dig_port->base;
5874 encoder = &intel_encoder->base;
5875
5876 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5877 DRM_MODE_ENCODER_TMDS);
5878
5bfe2ac0 5879 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5880 intel_encoder->disable = intel_disable_dp;
00c09d70 5881 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5882 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5883 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5884 if (IS_CHERRYVIEW(dev)) {
9197c88b 5885 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5886 intel_encoder->pre_enable = chv_pre_enable_dp;
5887 intel_encoder->enable = vlv_enable_dp;
580d3811 5888 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5889 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5890 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5891 intel_encoder->pre_enable = vlv_pre_enable_dp;
5892 intel_encoder->enable = vlv_enable_dp;
49277c31 5893 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5894 } else {
ecff4f3b
JN		 5895 intel_encoder->pre_enable = g4x_pre_enable_dp;
5896 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5897 if (INTEL_INFO(dev)->gen >= 5)
5898 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5899 }
f0fec3f2 5900
174edf1f 5901 intel_dig_port->port = port;
f0fec3f2
PZ		 5902 intel_dig_port->dp.output_reg = output_reg;
5903
00c09d70 5904 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5905 if (IS_CHERRYVIEW(dev)) {
5906 if (port == PORT_D)
5907 intel_encoder->crtc_mask = 1 << 2;
5908 else
5909 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5910 } else {
5911 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5912 }
bc079e8b 5913 intel_encoder->cloneable = 0;
f0fec3f2 5914
13cf5504 5915 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 5916 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 5917
15b1d171
PZ		 5918 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5919 drm_encoder_cleanup(encoder);
5920 kfree(intel_dig_port);
b2f246a8 5921 kfree(intel_connector);
15b1d171 5922 }
f0fec3f2 5923}
0e32b39c
DA		 5924
5925void intel_dp_mst_suspend(struct drm_device *dev)
5926{
5927 struct drm_i915_private *dev_priv = dev->dev_private;
5928 int i;
5929
5930 /* disable MST */
5931 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5932 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 5933 if (!intel_dig_port)
5934 continue;
5935
5936 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5937 if (!intel_dig_port->dp.can_mst)
5938 continue;
5939 if (intel_dig_port->dp.is_mst)
5940 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5941 }
5942 }
5943}
5944
5945void intel_dp_mst_resume(struct drm_device *dev)
5946{
5947 struct drm_i915_private *dev_priv = dev->dev_private;
5948 int i;
5949
5950 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5951 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 5952 if (!intel_dig_port)
5953 continue;
5954 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5955 int ret;
5956
5957 if (!intel_dig_port->dp.can_mst)
5958 continue;
5959
5960 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5961 if (ret != 0) {
5962 intel_dp_check_mst_status(&intel_dig_port->dp);
5963 }
5964 }
5965 }
5966}
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