]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/gpu/drm/i915/intel_dp.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: refactor cpu eDP PLL handling a bit
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
68b4d824
ID		 55static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
56{
57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
58
59 return intel_dig_port->base.base.dev;
60}
61
df0e9248
CW		 62static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
63{
fa90ecef 64 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 65}
66
ea5b213a 67static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 68
a4fc5ed6 69static int
ea5b213a 70intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 71{
7183dc29 72 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 73
74 switch (max_link_bw) {
75 case DP_LINK_BW_1_62:
76 case DP_LINK_BW_2_7:
77 break;
78 default:
79 max_link_bw = DP_LINK_BW_1_62;
80 break;
81 }
82 return max_link_bw;
83}
84
cd9dde44
AJ		 85/*
86 * The units on the numbers in the next two are... bizarre. Examples will
87 * make it clearer; this one parallels an example in the eDP spec.
88 *
89 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
90 *
91 * 270000 * 1 * 8 / 10 == 216000
92 *
93 * The actual data capacity of that configuration is 2.16Gbit/s, so the
94 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
95 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
96 * 119000. At 18bpp that's 2142000 kilobits per second.
97 *
98 * Thus the strange-looking division by 10 in intel_dp_link_required, to
99 * get the result in decakilobits instead of kilobits.
100 */
101
a4fc5ed6 102static int
c898261c 103intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 104{
cd9dde44 105 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 106}
107
fe27d53e
DA		 108static int
109intel_dp_max_data_rate(int max_link_clock, int max_lanes)
110{
111 return (max_link_clock * max_lanes * 8) / 10;
112}
113
a4fc5ed6
KP		 114static int
115intel_dp_mode_valid(struct drm_connector *connector,
116 struct drm_display_mode *mode)
117{
df0e9248 118 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 119 struct intel_connector *intel_connector = to_intel_connector(connector);
120 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 121 int target_clock = mode->clock;
122 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 123
dd06f90e
JN		 124 if (is_edp(intel_dp) && fixed_mode) {
125 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 126 return MODE_PANEL;
127
dd06f90e 128 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 129 return MODE_PANEL;
03afc4a2
DV		 130
131 target_clock = fixed_mode->clock;
7de56f43
ZY		 132 }
133
36008365
DV		 134 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
135 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
136
137 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
138 mode_rate = intel_dp_link_required(target_clock, 18);
139
140 if (mode_rate > max_rate)
c4867936 141 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 142
143 if (mode->clock < 10000)
144 return MODE_CLOCK_LOW;
145
0af78a2b
DV		 146 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
147 return MODE_H_ILLEGAL;
148
a4fc5ed6
KP		 149 return MODE_OK;
150}
151
152static uint32_t
153pack_aux(uint8_t *src, int src_bytes)
154{
155 int i;
156 uint32_t v = 0;
157
158 if (src_bytes > 4)
159 src_bytes = 4;
160 for (i = 0; i < src_bytes; i++)
161 v |= ((uint32_t) src[i]) << ((3-i) * 8);
162 return v;
163}
164
165static void
166unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
167{
168 int i;
169 if (dst_bytes > 4)
170 dst_bytes = 4;
171 for (i = 0; i < dst_bytes; i++)
172 dst[i] = src >> ((3-i) * 8);
173}
174
fb0f8fbf
KP		 175/* hrawclock is 1/4 the FSB frequency */
176static int
177intel_hrawclk(struct drm_device *dev)
178{
179 struct drm_i915_private *dev_priv = dev->dev_private;
180 uint32_t clkcfg;
181
9473c8f4
VP		 182 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
183 if (IS_VALLEYVIEW(dev))
184 return 200;
185
fb0f8fbf
KP		 186 clkcfg = I915_READ(CLKCFG);
187 switch (clkcfg & CLKCFG_FSB_MASK) {
188 case CLKCFG_FSB_400:
189 return 100;
190 case CLKCFG_FSB_533:
191 return 133;
192 case CLKCFG_FSB_667:
193 return 166;
194 case CLKCFG_FSB_800:
195 return 200;
196 case CLKCFG_FSB_1067:
197 return 266;
198 case CLKCFG_FSB_1333:
199 return 333;
200 /* these two are just a guess; one of them might be right */
201 case CLKCFG_FSB_1600:
202 case CLKCFG_FSB_1600_ALT:
203 return 400;
204 default:
205 return 133;
206 }
207}
208
ebf33b18
KP		 209static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
210{
30add22d 211 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 212 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 213 u32 pp_stat_reg;
ebf33b18 214
453c5420
JB		 215 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
216 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
ebf33b18
KP		 217}
218
219static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
220{
30add22d 221 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 222 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 223 u32 pp_ctrl_reg;
ebf33b18 224
453c5420
JB		 225 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
226 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 227}
228
9b984dae
KP		 229static void
230intel_dp_check_edp(struct intel_dp *intel_dp)
231{
30add22d 232 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 233 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 234 u32 pp_stat_reg, pp_ctrl_reg;
ebf33b18 235
9b984dae
KP		 236 if (!is_edp(intel_dp))
237 return;
453c5420
JB		 238
239 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
240 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
241
ebf33b18 242 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 243 WARN(1, "eDP powered off while attempting aux channel communication.\n");
244 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
453c5420
JB		 245 I915_READ(pp_stat_reg),
246 I915_READ(pp_ctrl_reg));
9b984dae
KP		 247 }
248}
249
9ee32fea
DV		 250static uint32_t
251intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
252{
253 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 256 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 257 uint32_t status;
258 bool done;
259
ef04f00d 260#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 261 if (has_aux_irq)
b90f5176
PZ		 262 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
263 msecs_to_jiffies(10));
9ee32fea
DV		 264 else
265 done = wait_for_atomic(C, 10) == 0;
266 if (!done)
267 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
268 has_aux_irq);
269#undef C
270
271 return status;
272}
273
a4fc5ed6 274static int
ea5b213a 275intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 276 uint8_t *send, int send_bytes,
277 uint8_t *recv, int recv_size)
278{
174edf1f
PZ		 279 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
280 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 281 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 282 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
a4fc5ed6 283 uint32_t ch_data = ch_ctl + 4;
9ee32fea 284 int i, ret, recv_bytes;
a4fc5ed6 285 uint32_t status;
fb0f8fbf 286 uint32_t aux_clock_divider;
6b4e0a93 287 int try, precharge;
9ee32fea
DV		 288 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
289
290 /* dp aux is extremely sensitive to irq latency, hence request the
291 * lowest possible wakeup latency and so prevent the cpu from going into
292 * deep sleep states.
293 */
294 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 295
9b984dae 296 intel_dp_check_edp(intel_dp);
a4fc5ed6 297 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 298 * and would like to run at 2MHz. So, take the
299 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 300 *
301 * Note that PCH attached eDP panels should use a 125MHz input
302 * clock divider.
a4fc5ed6 303 */
a62d0834
ID		 304 if (IS_VALLEYVIEW(dev)) {
305 aux_clock_divider = 100;
306 } else if (intel_dig_port->port == PORT_A) {
affa9354 307 if (HAS_DDI(dev))
b2b877ff
PZ		 308 aux_clock_divider = DIV_ROUND_CLOSEST(
309 intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 310 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 311 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 312 else
313 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 314 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
315 /* Workaround for non-ULT HSW */
316 aux_clock_divider = 74;
317 } else if (HAS_PCH_SPLIT(dev)) {
6b3ec1c9 318 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 319 } else {
5eb08b69 320 aux_clock_divider = intel_hrawclk(dev) / 2;
2c55c336 321 }
5eb08b69 322
6b4e0a93
DV		 323 if (IS_GEN6(dev))
324 precharge = 3;
325 else
326 precharge = 5;
327
11bee43e
JB		 328 /* Try to wait for any previous AUX channel activity */
329 for (try = 0; try < 3; try++) {
ef04f00d 330 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 331 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
332 break;
333 msleep(1);
334 }
335
336 if (try == 3) {
337 WARN(1, "dp_aux_ch not started status 0x%08x\n",
338 I915_READ(ch_ctl));
9ee32fea
DV		 339 ret = -EBUSY;
340 goto out;
4f7f7b7e
CW		 341 }
342
fb0f8fbf
KP		 343 /* Must try at least 3 times according to DP spec */
344 for (try = 0; try < 5; try++) {
345 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 346 for (i = 0; i < send_bytes; i += 4)
347 I915_WRITE(ch_data + i,
348 pack_aux(send + i, send_bytes - i));
0206e353 349
fb0f8fbf 350 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 351 I915_WRITE(ch_ctl,
352 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 353 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 354 DP_AUX_CH_CTL_TIME_OUT_400us |
355 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
356 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
357 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
358 DP_AUX_CH_CTL_DONE |
359 DP_AUX_CH_CTL_TIME_OUT_ERROR |
360 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 361
362 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 363
fb0f8fbf 364 /* Clear done status and any errors */
4f7f7b7e
CW		 365 I915_WRITE(ch_ctl,
366 status |
367 DP_AUX_CH_CTL_DONE |
368 DP_AUX_CH_CTL_TIME_OUT_ERROR |
369 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 370
371 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
372 DP_AUX_CH_CTL_RECEIVE_ERROR))
373 continue;
4f7f7b7e 374 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 375 break;
376 }
377
a4fc5ed6 378 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 379 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 380 ret = -EBUSY;
381 goto out;
a4fc5ed6
KP		 382 }
383
384 /* Check for timeout or receive error.
385 * Timeouts occur when the sink is not connected
386 */
a5b3da54 387 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 388 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 389 ret = -EIO;
390 goto out;
a5b3da54 391 }
1ae8c0a5
KP		 392
393 /* Timeouts occur when the device isn't connected, so they're
394 * "normal" -- don't fill the kernel log with these */
a5b3da54 395 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 396 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 397 ret = -ETIMEDOUT;
398 goto out;
a4fc5ed6
KP		 399 }
400
401 /* Unload any bytes sent back from the other side */
402 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
403 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 404 if (recv_bytes > recv_size)
405 recv_bytes = recv_size;
0206e353 406
4f7f7b7e
CW		 407 for (i = 0; i < recv_bytes; i += 4)
408 unpack_aux(I915_READ(ch_data + i),
409 recv + i, recv_bytes - i);
a4fc5ed6 410
9ee32fea
DV		 411 ret = recv_bytes;
412out:
413 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
414
415 return ret;
a4fc5ed6
KP		 416}
417
418/* Write data to the aux channel in native mode */
419static int
ea5b213a 420intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 421 uint16_t address, uint8_t *send, int send_bytes)
422{
423 int ret;
424 uint8_t msg[20];
425 int msg_bytes;
426 uint8_t ack;
427
9b984dae 428 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 429 if (send_bytes > 16)
430 return -1;
431 msg[0] = AUX_NATIVE_WRITE << 4;
432 msg[1] = address >> 8;
eebc863e 433 msg[2] = address & 0xff;
a4fc5ed6
KP		 434 msg[3] = send_bytes - 1;
435 memcpy(&msg[4], send, send_bytes);
436 msg_bytes = send_bytes + 4;
437 for (;;) {
ea5b213a 438 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 439 if (ret < 0)
440 return ret;
441 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
442 break;
443 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
444 udelay(100);
445 else
a5b3da54 446 return -EIO;
a4fc5ed6
KP		 447 }
448 return send_bytes;
449}
450
451/* Write a single byte to the aux channel in native mode */
452static int
ea5b213a 453intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 454 uint16_t address, uint8_t byte)
455{
ea5b213a 456 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 457}
458
459/* read bytes from a native aux channel */
460static int
ea5b213a 461intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 462 uint16_t address, uint8_t *recv, int recv_bytes)
463{
464 uint8_t msg[4];
465 int msg_bytes;
466 uint8_t reply[20];
467 int reply_bytes;
468 uint8_t ack;
469 int ret;
470
9b984dae 471 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 472 msg[0] = AUX_NATIVE_READ << 4;
473 msg[1] = address >> 8;
474 msg[2] = address & 0xff;
475 msg[3] = recv_bytes - 1;
476
477 msg_bytes = 4;
478 reply_bytes = recv_bytes + 1;
479
480 for (;;) {
ea5b213a 481 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 482 reply, reply_bytes);
a5b3da54
KP		 483 if (ret == 0)
484 return -EPROTO;
485 if (ret < 0)
a4fc5ed6
KP		 486 return ret;
487 ack = reply[0];
488 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
489 memcpy(recv, reply + 1, ret - 1);
490 return ret - 1;
491 }
492 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
493 udelay(100);
494 else
a5b3da54 495 return -EIO;
a4fc5ed6
KP		 496 }
497}
498
499static int
ab2c0672
DA		 500intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
501 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 502{
ab2c0672 503 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 504 struct intel_dp *intel_dp = container_of(adapter,
505 struct intel_dp,
506 adapter);
ab2c0672
DA		 507 uint16_t address = algo_data->address;
508 uint8_t msg[5];
509 uint8_t reply[2];
8316f337 510 unsigned retry;
ab2c0672
DA		 511 int msg_bytes;
512 int reply_bytes;
513 int ret;
514
9b984dae 515 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 516 /* Set up the command byte */
517 if (mode & MODE_I2C_READ)
518 msg[0] = AUX_I2C_READ << 4;
519 else
520 msg[0] = AUX_I2C_WRITE << 4;
521
522 if (!(mode & MODE_I2C_STOP))
523 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 524
ab2c0672
DA		 525 msg[1] = address >> 8;
526 msg[2] = address;
527
528 switch (mode) {
529 case MODE_I2C_WRITE:
530 msg[3] = 0;
531 msg[4] = write_byte;
532 msg_bytes = 5;
533 reply_bytes = 1;
534 break;
535 case MODE_I2C_READ:
536 msg[3] = 0;
537 msg_bytes = 4;
538 reply_bytes = 2;
539 break;
540 default:
541 msg_bytes = 3;
542 reply_bytes = 1;
543 break;
544 }
545
8316f337
DF		 546 for (retry = 0; retry < 5; retry++) {
547 ret = intel_dp_aux_ch(intel_dp,
548 msg, msg_bytes,
549 reply, reply_bytes);
ab2c0672 550 if (ret < 0) {
3ff99164 551 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 552 return ret;
553 }
8316f337
DF		 554
555 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
556 case AUX_NATIVE_REPLY_ACK:
557 /* I2C-over-AUX Reply field is only valid
558 * when paired with AUX ACK.
559 */
560 break;
561 case AUX_NATIVE_REPLY_NACK:
562 DRM_DEBUG_KMS("aux_ch native nack\n");
563 return -EREMOTEIO;
564 case AUX_NATIVE_REPLY_DEFER:
565 udelay(100);
566 continue;
567 default:
568 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
569 reply[0]);
570 return -EREMOTEIO;
571 }
572
ab2c0672
DA		 573 switch (reply[0] & AUX_I2C_REPLY_MASK) {
574 case AUX_I2C_REPLY_ACK:
575 if (mode == MODE_I2C_READ) {
576 *read_byte = reply[1];
577 }
578 return reply_bytes - 1;
579 case AUX_I2C_REPLY_NACK:
8316f337 580 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 581 return -EREMOTEIO;
582 case AUX_I2C_REPLY_DEFER:
8316f337 583 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 584 udelay(100);
585 break;
586 default:
8316f337 587 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 588 return -EREMOTEIO;
589 }
590 }
8316f337
DF		 591
592 DRM_ERROR("too many retries, giving up\n");
593 return -EREMOTEIO;
a4fc5ed6
KP		 594}
595
596static int
ea5b213a 597intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 598 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 599{
0b5c541b
KP		 600 int ret;
601
d54e9d28 602 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 603 intel_dp->algo.running = false;
604 intel_dp->algo.address = 0;
605 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
606
0206e353 607 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 608 intel_dp->adapter.owner = THIS_MODULE;
609 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 610 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 611 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
612 intel_dp->adapter.algo_data = &intel_dp->algo;
613 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
614
0b5c541b
KP		 615 ironlake_edp_panel_vdd_on(intel_dp);
616 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 617 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 618 return ret;
a4fc5ed6
KP		 619}
620
c6bb3538
DV		 621static void
622intel_dp_set_clock(struct intel_encoder *encoder,
623 struct intel_crtc_config *pipe_config, int link_bw)
624{
625 struct drm_device *dev = encoder->base.dev;
626
627 if (IS_G4X(dev)) {
628 if (link_bw == DP_LINK_BW_1_62) {
629 pipe_config->dpll.p1 = 2;
630 pipe_config->dpll.p2 = 10;
631 pipe_config->dpll.n = 2;
632 pipe_config->dpll.m1 = 23;
633 pipe_config->dpll.m2 = 8;
634 } else {
635 pipe_config->dpll.p1 = 1;
636 pipe_config->dpll.p2 = 10;
637 pipe_config->dpll.n = 1;
638 pipe_config->dpll.m1 = 14;
639 pipe_config->dpll.m2 = 2;
640 }
641 pipe_config->clock_set = true;
642 } else if (IS_HASWELL(dev)) {
643 /* Haswell has special-purpose DP DDI clocks. */
644 } else if (HAS_PCH_SPLIT(dev)) {
645 if (link_bw == DP_LINK_BW_1_62) {
646 pipe_config->dpll.n = 1;
647 pipe_config->dpll.p1 = 2;
648 pipe_config->dpll.p2 = 10;
649 pipe_config->dpll.m1 = 12;
650 pipe_config->dpll.m2 = 9;
651 } else {
652 pipe_config->dpll.n = 2;
653 pipe_config->dpll.p1 = 1;
654 pipe_config->dpll.p2 = 10;
655 pipe_config->dpll.m1 = 14;
656 pipe_config->dpll.m2 = 8;
657 }
658 pipe_config->clock_set = true;
659 } else if (IS_VALLEYVIEW(dev)) {
660 /* FIXME: Need to figure out optimized DP clocks for vlv. */
661 }
662}
663
00c09d70 664bool
5bfe2ac0
DV		 665intel_dp_compute_config(struct intel_encoder *encoder,
666 struct intel_crtc_config *pipe_config)
a4fc5ed6 667{
5bfe2ac0 668 struct drm_device *dev = encoder->base.dev;
36008365 669 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 670 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 671 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 672 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 673 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 674 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 675 int lane_count, clock;
397fe157 676 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 677 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 678 int bpp, mode_rate;
a4fc5ed6 679 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
36008365 680 int target_clock, link_avail, link_clock;
a4fc5ed6 681
bc7d38a4 682 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 683 pipe_config->has_pch_encoder = true;
684
03afc4a2
DV		 685 pipe_config->has_dp_encoder = true;
686
dd06f90e
JN		 687 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
688 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
689 adjusted_mode);
2dd24552
JB		 690 if (!HAS_PCH_SPLIT(dev))
691 intel_gmch_panel_fitting(intel_crtc, pipe_config,
692 intel_connector->panel.fitting_mode);
693 else
b074cec8
JB		 694 intel_pch_panel_fitting(intel_crtc, pipe_config,
695 intel_connector->panel.fitting_mode);
0d3a1bee 696 }
36008365
DV		 697 /* We need to take the panel's fixed mode into account. */
698 target_clock = adjusted_mode->clock;
0d3a1bee 699
cb1793ce 700 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 701 return false;
702
083f9560
DV		 703 DRM_DEBUG_KMS("DP link computation with max lane count %i "
704 "max bw %02x pixel clock %iKHz\n",
71244653 705 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 706
36008365
DV		 707 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
708 * bpc in between. */
03afc4a2 709 bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
e1b73cba
DV		 710 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp)
711 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
af13188a 712
36008365
DV		 713 for (; bpp >= 6*3; bpp -= 2*3) {
714 mode_rate = intel_dp_link_required(target_clock, bpp);
715
716 for (clock = 0; clock <= max_clock; clock++) {
717 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
718 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
719 link_avail = intel_dp_max_data_rate(link_clock,
720 lane_count);
721
722 if (mode_rate <= link_avail) {
723 goto found;
724 }
725 }
726 }
727 }
c4867936 728
36008365 729 return false;
3685a8f3 730
36008365 731found:
55bc60db
VS		 732 if (intel_dp->color_range_auto) {
733 /*
734 * See:
735 * CEA-861-E - 5.1 Default Encoding Parameters
736 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
737 */
18316c8c 738 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 739 intel_dp->color_range = DP_COLOR_RANGE_16_235;
740 else
741 intel_dp->color_range = 0;
742 }
743
3685a8f3 744 if (intel_dp->color_range)
50f3b016 745 pipe_config->limited_color_range = true;
3685a8f3 746
36008365
DV		 747 intel_dp->link_bw = bws[clock];
748 intel_dp->lane_count = lane_count;
749 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
657445fe 750 pipe_config->pipe_bpp = bpp;
df92b1e6 751 pipe_config->pixel_target_clock = target_clock;
fe27d53e 752
36008365
DV		 753 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
754 intel_dp->link_bw, intel_dp->lane_count,
755 adjusted_mode->clock, bpp);
756 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
757 mode_rate, link_avail);
758
03afc4a2
DV		 759 intel_link_compute_m_n(bpp, lane_count,
760 target_clock, adjusted_mode->clock,
761 &pipe_config->dp_m_n);
a4fc5ed6 762
c6bb3538
DV		 763 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
764
03afc4a2 765 return true;
a4fc5ed6
KP		 766}
767
247d89f6
PZ		 768void intel_dp_init_link_config(struct intel_dp *intel_dp)
769{
770 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
771 intel_dp->link_configuration[0] = intel_dp->link_bw;
772 intel_dp->link_configuration[1] = intel_dp->lane_count;
773 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
774 /*
775 * Check for DPCD version > 1.1 and enhanced framing support
776 */
777 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
778 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
779 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
780 }
781}
782
7c62a164 783static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 784{
7c62a164
DV		 785 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
786 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
787 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 788 struct drm_i915_private *dev_priv = dev->dev_private;
789 u32 dpa_ctl;
790
7c62a164
DV		 791 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
792 crtc->config.adjusted_mode.clock);
ea9b6006
DV		 793 dpa_ctl = I915_READ(DP_A);
794 dpa_ctl &= ~DP_PLL_FREQ_MASK;
795
7c62a164 796 if (crtc->config.adjusted_mode.clock == 162000) {
1ce17038
DV		 797 /* For a long time we've carried around a ILK-DevA w/a for the
798 * 160MHz clock. If we're really unlucky, it's still required.
799 */
800 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 801 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 802 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 803 } else {
804 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 805 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 806 }
1ce17038 807
ea9b6006
DV		 808 I915_WRITE(DP_A, dpa_ctl);
809
810 POSTING_READ(DP_A);
811 udelay(500);
812}
813
a4fc5ed6
KP		 814static void
815intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
816 struct drm_display_mode *adjusted_mode)
817{
e3421a18 818 struct drm_device *dev = encoder->dev;
417e822d 819 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 820 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
bc7d38a4 821 enum port port = dp_to_dig_port(intel_dp)->port;
7c62a164 822 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
a4fc5ed6 823
417e822d 824 /*
1a2eb460 825 * There are four kinds of DP registers:
417e822d
KP		 826 *
827 * IBX PCH
1a2eb460
KP		 828 * SNB CPU
829 * IVB CPU
417e822d
KP		 830 * CPT PCH
831 *
832 * IBX PCH and CPU are the same for almost everything,
833 * except that the CPU DP PLL is configured in this
834 * register
835 *
836 * CPT PCH is quite different, having many bits moved
837 * to the TRANS_DP_CTL register instead. That
838 * configuration happens (oddly) in ironlake_pch_enable
839 */
9c9e7927 840
417e822d
KP		 841 /* Preserve the BIOS-computed detected bit. This is
842 * supposed to be read-only.
843 */
844 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 845
417e822d 846 /* Handle DP bits in common between all three register formats */
417e822d 847 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 848 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 849
e0dac65e
WF		 850 if (intel_dp->has_audio) {
851 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 852 pipe_name(crtc->pipe));
ea5b213a 853 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 854 intel_write_eld(encoder, adjusted_mode);
855 }
247d89f6
PZ		 856
857 intel_dp_init_link_config(intel_dp);
a4fc5ed6 858
417e822d 859 /* Split out the IBX/CPU vs CPT settings */
32f9d658 860
bc7d38a4 861 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 862 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
863 intel_dp->DP |= DP_SYNC_HS_HIGH;
864 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
865 intel_dp->DP |= DP_SYNC_VS_HIGH;
866 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
867
868 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
869 intel_dp->DP |= DP_ENHANCED_FRAMING;
870
7c62a164 871 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 872 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 873 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 874 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 875
876 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
877 intel_dp->DP |= DP_SYNC_HS_HIGH;
878 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
879 intel_dp->DP |= DP_SYNC_VS_HIGH;
880 intel_dp->DP |= DP_LINK_TRAIN_OFF;
881
882 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
883 intel_dp->DP |= DP_ENHANCED_FRAMING;
884
7c62a164 885 if (crtc->pipe == 1)
417e822d 886 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 887 } else {
888 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 889 }
ea9b6006 890
bc7d38a4 891 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 892 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 893}
894
99ea7127
KP		 895#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
896#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
897
898#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
899#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
900
901#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
902#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
903
904static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
905 u32 mask,
906 u32 value)
bd943159 907{
30add22d 908 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 909 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 910 u32 pp_stat_reg, pp_ctrl_reg;
911
912 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
913 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
32ce697c 914
99ea7127 915 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 916 mask, value,
917 I915_READ(pp_stat_reg),
918 I915_READ(pp_ctrl_reg));
32ce697c 919
453c5420 920 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 921 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 922 I915_READ(pp_stat_reg),
923 I915_READ(pp_ctrl_reg));
32ce697c 924 }
99ea7127 925}
32ce697c 926
99ea7127
KP		 927static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
928{
929 DRM_DEBUG_KMS("Wait for panel power on\n");
930 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 931}
932
99ea7127
KP		 933static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
934{
935 DRM_DEBUG_KMS("Wait for panel power off time\n");
936 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
937}
938
939static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
940{
941 DRM_DEBUG_KMS("Wait for panel power cycle\n");
942 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
943}
944
945
832dd3c1
KP		 946/* Read the current pp_control value, unlocking the register if it
947 * is locked
948 */
949
453c5420 950static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 951{
453c5420
JB		 952 struct drm_device *dev = intel_dp_to_dev(intel_dp);
953 struct drm_i915_private *dev_priv = dev->dev_private;
954 u32 control;
955 u32 pp_ctrl_reg;
956
957 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
958 control = I915_READ(pp_ctrl_reg);
832dd3c1
KP		 959
960 control &= ~PANEL_UNLOCK_MASK;
961 control |= PANEL_UNLOCK_REGS;
962 return control;
bd943159
KP		 963}
964
82a4d9c0 965void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 966{
30add22d 967 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 968 struct drm_i915_private *dev_priv = dev->dev_private;
969 u32 pp;
453c5420 970 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 971
97af61f5
KP		 972 if (!is_edp(intel_dp))
973 return;
f01eca2e 974 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 975
bd943159
KP		 976 WARN(intel_dp->want_panel_vdd,
977 "eDP VDD already requested on\n");
978
979 intel_dp->want_panel_vdd = true;
99ea7127 980
bd943159
KP		 981 if (ironlake_edp_have_panel_vdd(intel_dp)) {
982 DRM_DEBUG_KMS("eDP VDD already on\n");
983 return;
984 }
985
99ea7127
KP		 986 if (!ironlake_edp_have_panel_power(intel_dp))
987 ironlake_wait_panel_power_cycle(intel_dp);
988
453c5420 989 pp = ironlake_get_pp_control(intel_dp);
5d613501 990 pp |= EDP_FORCE_VDD;
ebf33b18 991
453c5420
JB		 992 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
993 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
994
995 I915_WRITE(pp_ctrl_reg, pp);
996 POSTING_READ(pp_ctrl_reg);
997 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
998 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 999 /*
1000 * If the panel wasn't on, delay before accessing aux channel
1001 */
1002 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1003 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1004 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1005 }
5d613501
JB		 1006}
1007
bd943159 1008static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1009{
30add22d 1010 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1011 struct drm_i915_private *dev_priv = dev->dev_private;
1012 u32 pp;
453c5420 1013 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1014
a0e99e68
DV		 1015 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1016
bd943159 1017 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1018 pp = ironlake_get_pp_control(intel_dp);
bd943159 1019 pp &= ~EDP_FORCE_VDD;
bd943159 1020
453c5420
JB		 1021 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1022 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1023
1024 I915_WRITE(pp_ctrl_reg, pp);
1025 POSTING_READ(pp_ctrl_reg);
99ea7127 1026
453c5420
JB		 1027 /* Make sure sequencer is idle before allowing subsequent activity */
1028 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1029 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1030 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1031 }
1032}
5d613501 1033
bd943159
KP		 1034static void ironlake_panel_vdd_work(struct work_struct *__work)
1035{
1036 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1037 struct intel_dp, panel_vdd_work);
30add22d 1038 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1039
627f7675 1040 mutex_lock(&dev->mode_config.mutex);
bd943159 1041 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1042 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1043}
1044
82a4d9c0 1045void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1046{
97af61f5
KP		 1047 if (!is_edp(intel_dp))
1048 return;
5d613501 1049
bd943159
KP		 1050 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1051 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1052
bd943159
KP		 1053 intel_dp->want_panel_vdd = false;
1054
1055 if (sync) {
1056 ironlake_panel_vdd_off_sync(intel_dp);
1057 } else {
1058 /*
1059 * Queue the timer to fire a long
1060 * time from now (relative to the power down delay)
1061 * to keep the panel power up across a sequence of operations
1062 */
1063 schedule_delayed_work(&intel_dp->panel_vdd_work,
1064 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1065 }
5d613501
JB		 1066}
1067
82a4d9c0 1068void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1069{
30add22d 1070 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1071 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1072 u32 pp;
453c5420 1073 u32 pp_ctrl_reg;
9934c132 1074
97af61f5 1075 if (!is_edp(intel_dp))
bd943159 1076 return;
99ea7127
KP		 1077
1078 DRM_DEBUG_KMS("Turn eDP power on\n");
1079
1080 if (ironlake_edp_have_panel_power(intel_dp)) {
1081 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1082 return;
99ea7127 1083 }
9934c132 1084
99ea7127 1085 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1086
453c5420 1087 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1088 if (IS_GEN5(dev)) {
1089 /* ILK workaround: disable reset around power sequence */
1090 pp &= ~PANEL_POWER_RESET;
1091 I915_WRITE(PCH_PP_CONTROL, pp);
1092 POSTING_READ(PCH_PP_CONTROL);
1093 }
37c6c9b0 1094
1c0ae80a 1095 pp |= POWER_TARGET_ON;
99ea7127
KP		 1096 if (!IS_GEN5(dev))
1097 pp |= PANEL_POWER_RESET;
1098
453c5420
JB		 1099 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1100
1101 I915_WRITE(pp_ctrl_reg, pp);
1102 POSTING_READ(pp_ctrl_reg);
9934c132 1103
99ea7127 1104 ironlake_wait_panel_on(intel_dp);
9934c132 1105
05ce1a49
KP		 1106 if (IS_GEN5(dev)) {
1107 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1108 I915_WRITE(PCH_PP_CONTROL, pp);
1109 POSTING_READ(PCH_PP_CONTROL);
1110 }
9934c132
JB		 1111}
1112
82a4d9c0 1113void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1114{
30add22d 1115 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1116 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1117 u32 pp;
453c5420 1118 u32 pp_ctrl_reg;
9934c132 1119
97af61f5
KP		 1120 if (!is_edp(intel_dp))
1121 return;
37c6c9b0 1122
99ea7127 1123 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1124
6cb49835 1125 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1126
453c5420 1127 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1128 /* We need to switch off panel power _and_ force vdd, for otherwise some
1129 * panels get very unhappy and cease to work. */
1130 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420
JB		 1131
1132 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1133
1134 I915_WRITE(pp_ctrl_reg, pp);
1135 POSTING_READ(pp_ctrl_reg);
9934c132 1136
35a38556
DV		 1137 intel_dp->want_panel_vdd = false;
1138
99ea7127 1139 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1140}
1141
d6c50ff8 1142void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1143{
da63a9f2
PZ		 1144 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1145 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1146 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1147 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1148 u32 pp;
453c5420 1149 u32 pp_ctrl_reg;
32f9d658 1150
f01eca2e
KP		 1151 if (!is_edp(intel_dp))
1152 return;
1153
28c97730 1154 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1155 /*
1156 * If we enable the backlight right away following a panel power
1157 * on, we may see slight flicker as the panel syncs with the eDP
1158 * link. So delay a bit to make sure the image is solid before
1159 * allowing it to appear.
1160 */
f01eca2e 1161 msleep(intel_dp->backlight_on_delay);
453c5420 1162 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1163 pp |= EDP_BLC_ENABLE;
453c5420
JB		 1164
1165 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1166
1167 I915_WRITE(pp_ctrl_reg, pp);
1168 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1169
1170 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1171}
1172
d6c50ff8 1173void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1174{
30add22d 1175 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1176 struct drm_i915_private *dev_priv = dev->dev_private;
1177 u32 pp;
453c5420 1178 u32 pp_ctrl_reg;
32f9d658 1179
f01eca2e
KP		 1180 if (!is_edp(intel_dp))
1181 return;
1182
035aa3de
DV		 1183 intel_panel_disable_backlight(dev);
1184
28c97730 1185 DRM_DEBUG_KMS("\n");
453c5420 1186 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1187 pp &= ~EDP_BLC_ENABLE;
453c5420
JB		 1188
1189 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1190
1191 I915_WRITE(pp_ctrl_reg, pp);
1192 POSTING_READ(pp_ctrl_reg);
f01eca2e 1193 msleep(intel_dp->backlight_off_delay);
32f9d658 1194}
a4fc5ed6 1195
2bd2ad64 1196static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1197{
da63a9f2
PZ		 1198 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1199 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1200 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1201 struct drm_i915_private *dev_priv = dev->dev_private;
1202 u32 dpa_ctl;
1203
2bd2ad64
DV		 1204 assert_pipe_disabled(dev_priv,
1205 to_intel_crtc(crtc)->pipe);
1206
d240f20f
JB		 1207 DRM_DEBUG_KMS("\n");
1208 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1209 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1210 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1211
1212 /* We don't adjust intel_dp->DP while tearing down the link, to
1213 * facilitate link retraining (e.g. after hotplug). Hence clear all
1214 * enable bits here to ensure that we don't enable too much. */
1215 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1216 intel_dp->DP |= DP_PLL_ENABLE;
1217 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1218 POSTING_READ(DP_A);
1219 udelay(200);
d240f20f
JB		 1220}
1221
2bd2ad64 1222static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1223{
da63a9f2
PZ		 1224 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1225 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1226 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1227 struct drm_i915_private *dev_priv = dev->dev_private;
1228 u32 dpa_ctl;
1229
2bd2ad64
DV		 1230 assert_pipe_disabled(dev_priv,
1231 to_intel_crtc(crtc)->pipe);
1232
d240f20f 1233 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1234 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1235 "dp pll off, should be on\n");
1236 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1237
1238 /* We can't rely on the value tracked for the DP register in
1239 * intel_dp->DP because link_down must not change that (otherwise link
1240 * re-training will fail. */
298b0b39 1241 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1242 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1243 POSTING_READ(DP_A);
d240f20f
JB		 1244 udelay(200);
1245}
1246
c7ad3810 1247/* If the sink supports it, try to set the power state appropriately */
c19b0669 1248void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1249{
1250 int ret, i;
1251
1252 /* Should have a valid DPCD by this point */
1253 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1254 return;
1255
1256 if (mode != DRM_MODE_DPMS_ON) {
1257 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1258 DP_SET_POWER_D3);
1259 if (ret != 1)
1260 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1261 } else {
1262 /*
1263 * When turning on, we need to retry for 1ms to give the sink
1264 * time to wake up.
1265 */
1266 for (i = 0; i < 3; i++) {
1267 ret = intel_dp_aux_native_write_1(intel_dp,
1268 DP_SET_POWER,
1269 DP_SET_POWER_D0);
1270 if (ret == 1)
1271 break;
1272 msleep(1);
1273 }
1274 }
1275}
1276
19d8fe15
DV		 1277static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1278 enum pipe *pipe)
d240f20f 1279{
19d8fe15 1280 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1281 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1282 struct drm_device *dev = encoder->base.dev;
1283 struct drm_i915_private *dev_priv = dev->dev_private;
1284 u32 tmp = I915_READ(intel_dp->output_reg);
1285
1286 if (!(tmp & DP_PORT_EN))
1287 return false;
1288
bc7d38a4 1289 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1290 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1291 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1292 *pipe = PORT_TO_PIPE(tmp);
1293 } else {
1294 u32 trans_sel;
1295 u32 trans_dp;
1296 int i;
1297
1298 switch (intel_dp->output_reg) {
1299 case PCH_DP_B:
1300 trans_sel = TRANS_DP_PORT_SEL_B;
1301 break;
1302 case PCH_DP_C:
1303 trans_sel = TRANS_DP_PORT_SEL_C;
1304 break;
1305 case PCH_DP_D:
1306 trans_sel = TRANS_DP_PORT_SEL_D;
1307 break;
1308 default:
1309 return true;
1310 }
1311
1312 for_each_pipe(i) {
1313 trans_dp = I915_READ(TRANS_DP_CTL(i));
1314 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1315 *pipe = i;
1316 return true;
1317 }
1318 }
19d8fe15 1319
4a0833ec
DV		 1320 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1321 intel_dp->output_reg);
1322 }
d240f20f 1323
2af8898b 1324 return true;
19d8fe15 1325}
d240f20f 1326
045ac3b5
JB		 1327static void intel_dp_get_config(struct intel_encoder *encoder,
1328 struct intel_crtc_config *pipe_config)
1329{
1330 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1331 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1332 u32 tmp, flags = 0;
1333
1334 tmp = I915_READ(intel_dp->output_reg);
1335
1336 if (tmp & DP_SYNC_HS_HIGH)
1337 flags |= DRM_MODE_FLAG_PHSYNC;
1338 else
1339 flags |= DRM_MODE_FLAG_NHSYNC;
1340
1341 if (tmp & DP_SYNC_VS_HIGH)
1342 flags |= DRM_MODE_FLAG_PVSYNC;
1343 else
1344 flags |= DRM_MODE_FLAG_NVSYNC;
1345
1346 pipe_config->adjusted_mode.flags |= flags;
1347}
1348
e8cb4558 1349static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1350{
e8cb4558 1351 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1352 enum port port = dp_to_dig_port(intel_dp)->port;
1353 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1354
1355 /* Make sure the panel is off before trying to change the mode. But also
1356 * ensure that we have vdd while we switch off the panel. */
1357 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1358 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1359 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1360 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1361
1362 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1363 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1364 intel_dp_link_down(intel_dp);
d240f20f
JB		 1365}
1366
2bd2ad64 1367static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1368{
2bd2ad64 1369 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1370 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1371 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1372
982a3866 1373 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1374 intel_dp_link_down(intel_dp);
b2634017
JB		 1375 if (!IS_VALLEYVIEW(dev))
1376 ironlake_edp_pll_off(intel_dp);
3739850b 1377 }
2bd2ad64
DV		 1378}
1379
e8cb4558 1380static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1381{
e8cb4558
DV		 1382 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1383 struct drm_device *dev = encoder->base.dev;
1384 struct drm_i915_private *dev_priv = dev->dev_private;
1385 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1386
0c33d8d7
DV		 1387 if (WARN_ON(dp_reg & DP_PORT_EN))
1388 return;
5d613501 1389
97af61f5 1390 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1391 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1392 intel_dp_start_link_train(intel_dp);
97af61f5 1393 ironlake_edp_panel_on(intel_dp);
bd943159 1394 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1395 intel_dp_complete_link_train(intel_dp);
3ab9c637 1396 intel_dp_stop_link_train(intel_dp);
f01eca2e 1397 ironlake_edp_backlight_on(intel_dp);
89b667f8
JB		 1398
1399 if (IS_VALLEYVIEW(dev)) {
1400 struct intel_digital_port *dport =
1401 enc_to_dig_port(&encoder->base);
1402 int channel = vlv_dport_to_channel(dport);
1403
1404 vlv_wait_port_ready(dev_priv, channel);
1405 }
d240f20f
JB		 1406}
1407
2bd2ad64 1408static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1409{
2bd2ad64 1410 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1411 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1412 struct drm_device *dev = encoder->base.dev;
89b667f8 1413 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1414
bc7d38a4 1415 if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))
2bd2ad64 1416 ironlake_edp_pll_on(intel_dp);
89b667f8
JB		 1417
1418 if (IS_VALLEYVIEW(dev)) {
89b667f8
JB		 1419 struct intel_crtc *intel_crtc =
1420 to_intel_crtc(encoder->base.crtc);
1421 int port = vlv_dport_to_channel(dport);
1422 int pipe = intel_crtc->pipe;
1423 u32 val;
1424
ae99258f 1425 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
89b667f8
JB		 1426 val = 0;
1427 if (pipe)
1428 val |= (1<<21);
1429 else
1430 val &= ~(1<<21);
1431 val |= 0x001000c4;
ae99258f 1432 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
89b667f8 1433
ae99258f 1434 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
89b667f8 1435 0x00760018);
ae99258f 1436 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
89b667f8
JB		 1437 0x00400888);
1438 }
1439}
1440
1441static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1442{
1443 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1444 struct drm_device *dev = encoder->base.dev;
1445 struct drm_i915_private *dev_priv = dev->dev_private;
1446 int port = vlv_dport_to_channel(dport);
1447
1448 if (!IS_VALLEYVIEW(dev))
1449 return;
1450
89b667f8 1451 /* Program Tx lane resets to default */
ae99258f 1452 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
89b667f8
JB		 1453 DPIO_PCS_TX_LANE2_RESET |
1454 DPIO_PCS_TX_LANE1_RESET);
ae99258f 1455 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
89b667f8
JB		 1456 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1457 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1458 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1459 DPIO_PCS_CLK_SOFT_RESET);
1460
1461 /* Fix up inter-pair skew failure */
ae99258f
JN		 1462 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1463 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1464 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
a4fc5ed6
KP		 1465}
1466
1467/*
df0c237d
JB		 1468 * Native read with retry for link status and receiver capability reads for
1469 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1470 */
1471static bool
df0c237d
JB		 1472intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1473 uint8_t *recv, int recv_bytes)
a4fc5ed6 1474{
61da5fab
JB		 1475 int ret, i;
1476
df0c237d
JB		 1477 /*
1478 * Sinks are *supposed* to come up within 1ms from an off state,
1479 * but we're also supposed to retry 3 times per the spec.
1480 */
61da5fab 1481 for (i = 0; i < 3; i++) {
df0c237d
JB		 1482 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1483 recv_bytes);
1484 if (ret == recv_bytes)
61da5fab
JB		 1485 return true;
1486 msleep(1);
1487 }
a4fc5ed6 1488
61da5fab 1489 return false;
a4fc5ed6
KP		 1490}
1491
1492/*
1493 * Fetch AUX CH registers 0x202 - 0x207 which contain
1494 * link status information
1495 */
1496static bool
93f62dad 1497intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1498{
df0c237d
JB		 1499 return intel_dp_aux_native_read_retry(intel_dp,
1500 DP_LANE0_1_STATUS,
93f62dad 1501 link_status,
df0c237d 1502 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1503}
1504
a4fc5ed6
KP		 1505#if 0
1506static char *voltage_names[] = {
1507 "0.4V", "0.6V", "0.8V", "1.2V"
1508};
1509static char *pre_emph_names[] = {
1510 "0dB", "3.5dB", "6dB", "9.5dB"
1511};
1512static char *link_train_names[] = {
1513 "pattern 1", "pattern 2", "idle", "off"
1514};
1515#endif
1516
1517/*
1518 * These are source-specific values; current Intel hardware supports
1519 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1520 */
a4fc5ed6
KP		 1521
1522static uint8_t
1a2eb460 1523intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1524{
30add22d 1525 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1526 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1527
e2fa6fba
P		 1528 if (IS_VALLEYVIEW(dev))
1529 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1530 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1531 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1532 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1533 return DP_TRAIN_VOLTAGE_SWING_1200;
1534 else
1535 return DP_TRAIN_VOLTAGE_SWING_800;
1536}
1537
1538static uint8_t
1539intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1540{
30add22d 1541 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1542 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1543
22b8bf17 1544 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1545 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1546 case DP_TRAIN_VOLTAGE_SWING_400:
1547 return DP_TRAIN_PRE_EMPHASIS_9_5;
1548 case DP_TRAIN_VOLTAGE_SWING_600:
1549 return DP_TRAIN_PRE_EMPHASIS_6;
1550 case DP_TRAIN_VOLTAGE_SWING_800:
1551 return DP_TRAIN_PRE_EMPHASIS_3_5;
1552 case DP_TRAIN_VOLTAGE_SWING_1200:
1553 default:
1554 return DP_TRAIN_PRE_EMPHASIS_0;
1555 }
e2fa6fba
P		 1556 } else if (IS_VALLEYVIEW(dev)) {
1557 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1558 case DP_TRAIN_VOLTAGE_SWING_400:
1559 return DP_TRAIN_PRE_EMPHASIS_9_5;
1560 case DP_TRAIN_VOLTAGE_SWING_600:
1561 return DP_TRAIN_PRE_EMPHASIS_6;
1562 case DP_TRAIN_VOLTAGE_SWING_800:
1563 return DP_TRAIN_PRE_EMPHASIS_3_5;
1564 case DP_TRAIN_VOLTAGE_SWING_1200:
1565 default:
1566 return DP_TRAIN_PRE_EMPHASIS_0;
1567 }
bc7d38a4 1568 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1569 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1570 case DP_TRAIN_VOLTAGE_SWING_400:
1571 return DP_TRAIN_PRE_EMPHASIS_6;
1572 case DP_TRAIN_VOLTAGE_SWING_600:
1573 case DP_TRAIN_VOLTAGE_SWING_800:
1574 return DP_TRAIN_PRE_EMPHASIS_3_5;
1575 default:
1576 return DP_TRAIN_PRE_EMPHASIS_0;
1577 }
1578 } else {
1579 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1580 case DP_TRAIN_VOLTAGE_SWING_400:
1581 return DP_TRAIN_PRE_EMPHASIS_6;
1582 case DP_TRAIN_VOLTAGE_SWING_600:
1583 return DP_TRAIN_PRE_EMPHASIS_6;
1584 case DP_TRAIN_VOLTAGE_SWING_800:
1585 return DP_TRAIN_PRE_EMPHASIS_3_5;
1586 case DP_TRAIN_VOLTAGE_SWING_1200:
1587 default:
1588 return DP_TRAIN_PRE_EMPHASIS_0;
1589 }
a4fc5ed6
KP		 1590 }
1591}
1592
e2fa6fba
P		 1593static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1594{
1595 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1596 struct drm_i915_private *dev_priv = dev->dev_private;
1597 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1598 unsigned long demph_reg_value, preemph_reg_value,
1599 uniqtranscale_reg_value;
1600 uint8_t train_set = intel_dp->train_set[0];
cece5d58 1601 int port = vlv_dport_to_channel(dport);
e2fa6fba
P		 1602
1603 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1604 case DP_TRAIN_PRE_EMPHASIS_0:
1605 preemph_reg_value = 0x0004000;
1606 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1607 case DP_TRAIN_VOLTAGE_SWING_400:
1608 demph_reg_value = 0x2B405555;
1609 uniqtranscale_reg_value = 0x552AB83A;
1610 break;
1611 case DP_TRAIN_VOLTAGE_SWING_600:
1612 demph_reg_value = 0x2B404040;
1613 uniqtranscale_reg_value = 0x5548B83A;
1614 break;
1615 case DP_TRAIN_VOLTAGE_SWING_800:
1616 demph_reg_value = 0x2B245555;
1617 uniqtranscale_reg_value = 0x5560B83A;
1618 break;
1619 case DP_TRAIN_VOLTAGE_SWING_1200:
1620 demph_reg_value = 0x2B405555;
1621 uniqtranscale_reg_value = 0x5598DA3A;
1622 break;
1623 default:
1624 return 0;
1625 }
1626 break;
1627 case DP_TRAIN_PRE_EMPHASIS_3_5:
1628 preemph_reg_value = 0x0002000;
1629 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1630 case DP_TRAIN_VOLTAGE_SWING_400:
1631 demph_reg_value = 0x2B404040;
1632 uniqtranscale_reg_value = 0x5552B83A;
1633 break;
1634 case DP_TRAIN_VOLTAGE_SWING_600:
1635 demph_reg_value = 0x2B404848;
1636 uniqtranscale_reg_value = 0x5580B83A;
1637 break;
1638 case DP_TRAIN_VOLTAGE_SWING_800:
1639 demph_reg_value = 0x2B404040;
1640 uniqtranscale_reg_value = 0x55ADDA3A;
1641 break;
1642 default:
1643 return 0;
1644 }
1645 break;
1646 case DP_TRAIN_PRE_EMPHASIS_6:
1647 preemph_reg_value = 0x0000000;
1648 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1649 case DP_TRAIN_VOLTAGE_SWING_400:
1650 demph_reg_value = 0x2B305555;
1651 uniqtranscale_reg_value = 0x5570B83A;
1652 break;
1653 case DP_TRAIN_VOLTAGE_SWING_600:
1654 demph_reg_value = 0x2B2B4040;
1655 uniqtranscale_reg_value = 0x55ADDA3A;
1656 break;
1657 default:
1658 return 0;
1659 }
1660 break;
1661 case DP_TRAIN_PRE_EMPHASIS_9_5:
1662 preemph_reg_value = 0x0006000;
1663 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1664 case DP_TRAIN_VOLTAGE_SWING_400:
1665 demph_reg_value = 0x1B405555;
1666 uniqtranscale_reg_value = 0x55ADDA3A;
1667 break;
1668 default:
1669 return 0;
1670 }
1671 break;
1672 default:
1673 return 0;
1674 }
1675
ae99258f
JN		 1676 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1677 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1678 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
e2fa6fba 1679 uniqtranscale_reg_value);
ae99258f
JN		 1680 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1681 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1682 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1683 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
e2fa6fba
P		 1684
1685 return 0;
1686}
1687
a4fc5ed6 1688static void
93f62dad 1689intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1690{
1691 uint8_t v = 0;
1692 uint8_t p = 0;
1693 int lane;
1a2eb460
KP		 1694 uint8_t voltage_max;
1695 uint8_t preemph_max;
a4fc5ed6 1696
33a34e4e 1697 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1698 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1699 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1700
1701 if (this_v > v)
1702 v = this_v;
1703 if (this_p > p)
1704 p = this_p;
1705 }
1706
1a2eb460 1707 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1708 if (v >= voltage_max)
1709 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1710
1a2eb460
KP		 1711 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1712 if (p >= preemph_max)
1713 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1714
1715 for (lane = 0; lane < 4; lane++)
33a34e4e 1716 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1717}
1718
1719static uint32_t
f0a3424e 1720intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 1721{
3cf2efb1 1722 uint32_t signal_levels = 0;
a4fc5ed6 1723
3cf2efb1 1724 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1725 case DP_TRAIN_VOLTAGE_SWING_400:
1726 default:
1727 signal_levels |= DP_VOLTAGE_0_4;
1728 break;
1729 case DP_TRAIN_VOLTAGE_SWING_600:
1730 signal_levels |= DP_VOLTAGE_0_6;
1731 break;
1732 case DP_TRAIN_VOLTAGE_SWING_800:
1733 signal_levels |= DP_VOLTAGE_0_8;
1734 break;
1735 case DP_TRAIN_VOLTAGE_SWING_1200:
1736 signal_levels |= DP_VOLTAGE_1_2;
1737 break;
1738 }
3cf2efb1 1739 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1740 case DP_TRAIN_PRE_EMPHASIS_0:
1741 default:
1742 signal_levels |= DP_PRE_EMPHASIS_0;
1743 break;
1744 case DP_TRAIN_PRE_EMPHASIS_3_5:
1745 signal_levels |= DP_PRE_EMPHASIS_3_5;
1746 break;
1747 case DP_TRAIN_PRE_EMPHASIS_6:
1748 signal_levels |= DP_PRE_EMPHASIS_6;
1749 break;
1750 case DP_TRAIN_PRE_EMPHASIS_9_5:
1751 signal_levels |= DP_PRE_EMPHASIS_9_5;
1752 break;
1753 }
1754 return signal_levels;
1755}
1756
e3421a18
ZW		 1757/* Gen6's DP voltage swing and pre-emphasis control */
1758static uint32_t
1759intel_gen6_edp_signal_levels(uint8_t train_set)
1760{
3c5a62b5
YL		 1761 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1762 DP_TRAIN_PRE_EMPHASIS_MASK);
1763 switch (signal_levels) {
e3421a18 1764 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1765 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1766 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1767 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1768 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1769 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1770 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1771 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1772 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1773 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1774 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1775 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1776 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1777 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1778 default:
3c5a62b5
YL		 1779 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1780 "0x%x\n", signal_levels);
1781 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1782 }
1783}
1784
1a2eb460
KP		 1785/* Gen7's DP voltage swing and pre-emphasis control */
1786static uint32_t
1787intel_gen7_edp_signal_levels(uint8_t train_set)
1788{
1789 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1790 DP_TRAIN_PRE_EMPHASIS_MASK);
1791 switch (signal_levels) {
1792 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1793 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1794 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1795 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1796 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1797 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1798
1799 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1800 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1801 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1802 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1803
1804 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1805 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1806 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1807 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1808
1809 default:
1810 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1811 "0x%x\n", signal_levels);
1812 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1813 }
1814}
1815
d6c0d722
PZ		 1816/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1817static uint32_t
f0a3424e 1818intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 1819{
d6c0d722
PZ		 1820 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1821 DP_TRAIN_PRE_EMPHASIS_MASK);
1822 switch (signal_levels) {
1823 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1824 return DDI_BUF_EMP_400MV_0DB_HSW;
1825 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1826 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1827 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1828 return DDI_BUF_EMP_400MV_6DB_HSW;
1829 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1830 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1831
d6c0d722
PZ		 1832 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1833 return DDI_BUF_EMP_600MV_0DB_HSW;
1834 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1835 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1836 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1837 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1838
d6c0d722
PZ		 1839 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1840 return DDI_BUF_EMP_800MV_0DB_HSW;
1841 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1842 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1843 default:
1844 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1845 "0x%x\n", signal_levels);
1846 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1847 }
a4fc5ed6
KP		 1848}
1849
f0a3424e
PZ		 1850/* Properly updates "DP" with the correct signal levels. */
1851static void
1852intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1853{
1854 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 1855 enum port port = intel_dig_port->port;
f0a3424e
PZ		 1856 struct drm_device *dev = intel_dig_port->base.base.dev;
1857 uint32_t signal_levels, mask;
1858 uint8_t train_set = intel_dp->train_set[0];
1859
22b8bf17 1860 if (HAS_DDI(dev)) {
f0a3424e
PZ		 1861 signal_levels = intel_hsw_signal_levels(train_set);
1862 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 1863 } else if (IS_VALLEYVIEW(dev)) {
1864 signal_levels = intel_vlv_signal_levels(intel_dp);
1865 mask = 0;
bc7d38a4 1866 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 1867 signal_levels = intel_gen7_edp_signal_levels(train_set);
1868 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 1869 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 1870 signal_levels = intel_gen6_edp_signal_levels(train_set);
1871 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1872 } else {
1873 signal_levels = intel_gen4_signal_levels(train_set);
1874 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1875 }
1876
1877 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1878
1879 *DP = (*DP & ~mask) | signal_levels;
1880}
1881
a4fc5ed6 1882static bool
ea5b213a 1883intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1884 uint32_t dp_reg_value,
58e10eb9 1885 uint8_t dp_train_pat)
a4fc5ed6 1886{
174edf1f
PZ		 1887 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1888 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1889 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1890 enum port port = intel_dig_port->port;
a4fc5ed6
KP		 1891 int ret;
1892
22b8bf17 1893 if (HAS_DDI(dev)) {
3ab9c637 1894 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1895
1896 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1897 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1898 else
1899 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1900
1901 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1902 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1903 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 1904 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1905
1906 break;
1907 case DP_TRAINING_PATTERN_1:
1908 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1909 break;
1910 case DP_TRAINING_PATTERN_2:
1911 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1912 break;
1913 case DP_TRAINING_PATTERN_3:
1914 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1915 break;
1916 }
174edf1f 1917 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 1918
bc7d38a4 1919 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
47ea7542
PZ		 1920 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1921
1922 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1923 case DP_TRAINING_PATTERN_DISABLE:
1924 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1925 break;
1926 case DP_TRAINING_PATTERN_1:
1927 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1928 break;
1929 case DP_TRAINING_PATTERN_2:
1930 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1931 break;
1932 case DP_TRAINING_PATTERN_3:
1933 DRM_ERROR("DP training pattern 3 not supported\n");
1934 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1935 break;
1936 }
1937
1938 } else {
1939 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1940
1941 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1942 case DP_TRAINING_PATTERN_DISABLE:
1943 dp_reg_value |= DP_LINK_TRAIN_OFF;
1944 break;
1945 case DP_TRAINING_PATTERN_1:
1946 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1947 break;
1948 case DP_TRAINING_PATTERN_2:
1949 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1950 break;
1951 case DP_TRAINING_PATTERN_3:
1952 DRM_ERROR("DP training pattern 3 not supported\n");
1953 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1954 break;
1955 }
1956 }
1957
ea5b213a
CW		 1958 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1959 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1960
ea5b213a 1961 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1962 DP_TRAINING_PATTERN_SET,
1963 dp_train_pat);
1964
47ea7542
PZ		 1965 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1966 DP_TRAINING_PATTERN_DISABLE) {
1967 ret = intel_dp_aux_native_write(intel_dp,
1968 DP_TRAINING_LANE0_SET,
1969 intel_dp->train_set,
1970 intel_dp->lane_count);
1971 if (ret != intel_dp->lane_count)
1972 return false;
1973 }
a4fc5ed6
KP		 1974
1975 return true;
1976}
1977
3ab9c637
ID		 1978static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
1979{
1980 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1981 struct drm_device *dev = intel_dig_port->base.base.dev;
1982 struct drm_i915_private *dev_priv = dev->dev_private;
1983 enum port port = intel_dig_port->port;
1984 uint32_t val;
1985
1986 if (!HAS_DDI(dev))
1987 return;
1988
1989 val = I915_READ(DP_TP_CTL(port));
1990 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1991 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
1992 I915_WRITE(DP_TP_CTL(port), val);
1993
1994 /*
1995 * On PORT_A we can have only eDP in SST mode. There the only reason
1996 * we need to set idle transmission mode is to work around a HW issue
1997 * where we enable the pipe while not in idle link-training mode.
1998 * In this case there is requirement to wait for a minimum number of
1999 * idle patterns to be sent.
2000 */
2001 if (port == PORT_A)
2002 return;
2003
2004 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2005 1))
2006 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2007}
2008
33a34e4e 2009/* Enable corresponding port and start training pattern 1 */
c19b0669 2010void
33a34e4e 2011intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2012{
da63a9f2 2013 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2014 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2015 int i;
2016 uint8_t voltage;
2017 bool clock_recovery = false;
cdb0e95b 2018 int voltage_tries, loop_tries;
ea5b213a 2019 uint32_t DP = intel_dp->DP;
a4fc5ed6 2020
affa9354 2021 if (HAS_DDI(dev))
c19b0669
PZ		 2022 intel_ddi_prepare_link_retrain(encoder);
2023
3cf2efb1
CW		 2024 /* Write the link configuration data */
2025 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2026 intel_dp->link_configuration,
2027 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 2028
2029 DP |= DP_PORT_EN;
1a2eb460 2030
33a34e4e 2031 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 2032 voltage = 0xff;
cdb0e95b
KP		 2033 voltage_tries = 0;
2034 loop_tries = 0;
a4fc5ed6
KP		 2035 clock_recovery = false;
2036 for (;;) {
33a34e4e 2037 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 2038 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 2039
2040 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 2041
a7c9655f 2042 /* Set training pattern 1 */
47ea7542 2043 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2044 DP_TRAINING_PATTERN_1 |
2045 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 2046 break;
a4fc5ed6 2047
a7c9655f 2048 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2049 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2050 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2051 break;
93f62dad 2052 }
a4fc5ed6 2053
01916270 2054 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2055 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2056 clock_recovery = true;
2057 break;
2058 }
2059
2060 /* Check to see if we've tried the max voltage */
2061 for (i = 0; i < intel_dp->lane_count; i++)
2062 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2063 break;
3b4f819d 2064 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2065 ++loop_tries;
2066 if (loop_tries == 5) {
cdb0e95b
KP		 2067 DRM_DEBUG_KMS("too many full retries, give up\n");
2068 break;
2069 }
2070 memset(intel_dp->train_set, 0, 4);
2071 voltage_tries = 0;
2072 continue;
2073 }
a4fc5ed6 2074
3cf2efb1 2075 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2076 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2077 ++voltage_tries;
b06fbda3
DV		 2078 if (voltage_tries == 5) {
2079 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2080 break;
2081 }
2082 } else
2083 voltage_tries = 0;
2084 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2085
3cf2efb1 2086 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2087 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 2088 }
2089
33a34e4e
JB		 2090 intel_dp->DP = DP;
2091}
2092
c19b0669 2093void
33a34e4e
JB		 2094intel_dp_complete_link_train(struct intel_dp *intel_dp)
2095{
33a34e4e 2096 bool channel_eq = false;
37f80975 2097 int tries, cr_tries;
33a34e4e
JB		 2098 uint32_t DP = intel_dp->DP;
2099
a4fc5ed6
KP		 2100 /* channel equalization */
2101 tries = 0;
37f80975 2102 cr_tries = 0;
a4fc5ed6
KP		 2103 channel_eq = false;
2104 for (;;) {
93f62dad 2105 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2106
37f80975
JB		 2107 if (cr_tries > 5) {
2108 DRM_ERROR("failed to train DP, aborting\n");
2109 intel_dp_link_down(intel_dp);
2110 break;
2111 }
2112
f0a3424e 2113 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 2114
a4fc5ed6 2115 /* channel eq pattern */
47ea7542 2116 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2117 DP_TRAINING_PATTERN_2 |
2118 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 2119 break;
2120
a7c9655f 2121 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2122 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2123 break;
a4fc5ed6 2124
37f80975 2125 /* Make sure clock is still ok */
01916270 2126 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2127 intel_dp_start_link_train(intel_dp);
2128 cr_tries++;
2129 continue;
2130 }
2131
1ffdff13 2132 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2133 channel_eq = true;
2134 break;
2135 }
a4fc5ed6 2136
37f80975
JB		 2137 /* Try 5 times, then try clock recovery if that fails */
2138 if (tries > 5) {
2139 intel_dp_link_down(intel_dp);
2140 intel_dp_start_link_train(intel_dp);
2141 tries = 0;
2142 cr_tries++;
2143 continue;
2144 }
a4fc5ed6 2145
3cf2efb1 2146 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2147 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2148 ++tries;
869184a6 2149 }
3cf2efb1 2150
3ab9c637
ID		 2151 intel_dp_set_idle_link_train(intel_dp);
2152
2153 intel_dp->DP = DP;
2154
d6c0d722 2155 if (channel_eq)
07f42258 2156 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2157
3ab9c637
ID		 2158}
2159
2160void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2161{
2162 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2163 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2164}
2165
2166static void
ea5b213a 2167intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2168{
da63a9f2 2169 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2170 enum port port = intel_dig_port->port;
da63a9f2 2171 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2172 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2173 struct intel_crtc *intel_crtc =
2174 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2175 uint32_t DP = intel_dp->DP;
a4fc5ed6 2176
c19b0669
PZ		 2177 /*
2178 * DDI code has a strict mode set sequence and we should try to respect
2179 * it, otherwise we might hang the machine in many different ways. So we
2180 * really should be disabling the port only on a complete crtc_disable
2181 * sequence. This function is just called under two conditions on DDI
2182 * code:
2183 * - Link train failed while doing crtc_enable, and on this case we
2184 * really should respect the mode set sequence and wait for a
2185 * crtc_disable.
2186 * - Someone turned the monitor off and intel_dp_check_link_status
2187 * called us. We don't need to disable the whole port on this case, so
2188 * when someone turns the monitor on again,
2189 * intel_ddi_prepare_link_retrain will take care of redoing the link
2190 * train.
2191 */
affa9354 2192 if (HAS_DDI(dev))
c19b0669
PZ		 2193 return;
2194
0c33d8d7 2195 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2196 return;
2197
28c97730 2198 DRM_DEBUG_KMS("\n");
32f9d658 2199
bc7d38a4 2200 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2201 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2202 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2203 } else {
2204 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2205 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2206 }
fe255d00 2207 POSTING_READ(intel_dp->output_reg);
5eb08b69 2208
ab527efc
DV		 2209 /* We don't really know why we're doing this */
2210 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2211
493a7081 2212 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2213 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2214 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2215
5bddd17f
EA		 2216 /* Hardware workaround: leaving our transcoder select
2217 * set to transcoder B while it's off will prevent the
2218 * corresponding HDMI output on transcoder A.
2219 *
2220 * Combine this with another hardware workaround:
2221 * transcoder select bit can only be cleared while the
2222 * port is enabled.
2223 */
2224 DP &= ~DP_PIPEB_SELECT;
2225 I915_WRITE(intel_dp->output_reg, DP);
2226
2227 /* Changes to enable or select take place the vblank
2228 * after being written.
2229 */
ff50afe9
DV		 2230 if (WARN_ON(crtc == NULL)) {
2231 /* We should never try to disable a port without a crtc
2232 * attached. For paranoia keep the code around for a
2233 * bit. */
31acbcc4
CW		 2234 POSTING_READ(intel_dp->output_reg);
2235 msleep(50);
2236 } else
ab527efc 2237 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2238 }
2239
832afda6 2240 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2241 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2242 POSTING_READ(intel_dp->output_reg);
f01eca2e 2243 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2244}
2245
26d61aad
KP		 2246static bool
2247intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2248{
577c7a50
DL		 2249 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2250
92fd8fd1 2251 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2252 sizeof(intel_dp->dpcd)) == 0)
2253 return false; /* aux transfer failed */
92fd8fd1 2254
577c7a50
DL		 2255 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2256 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2257 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2258
edb39244
AJ		 2259 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2260 return false; /* DPCD not present */
2261
2262 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2263 DP_DWN_STRM_PORT_PRESENT))
2264 return true; /* native DP sink */
2265
2266 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2267 return true; /* no per-port downstream info */
2268
2269 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2270 intel_dp->downstream_ports,
2271 DP_MAX_DOWNSTREAM_PORTS) == 0)
2272 return false; /* downstream port status fetch failed */
2273
2274 return true;
92fd8fd1
KP		 2275}
2276
0d198328
AJ		 2277static void
2278intel_dp_probe_oui(struct intel_dp *intel_dp)
2279{
2280 u8 buf[3];
2281
2282 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2283 return;
2284
351cfc34
DV		 2285 ironlake_edp_panel_vdd_on(intel_dp);
2286
0d198328
AJ		 2287 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2288 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2289 buf[0], buf[1], buf[2]);
2290
2291 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2292 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2293 buf[0], buf[1], buf[2]);
351cfc34
DV		 2294
2295 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2296}
2297
a60f0e38
JB		 2298static bool
2299intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2300{
2301 int ret;
2302
2303 ret = intel_dp_aux_native_read_retry(intel_dp,
2304 DP_DEVICE_SERVICE_IRQ_VECTOR,
2305 sink_irq_vector, 1);
2306 if (!ret)
2307 return false;
2308
2309 return true;
2310}
2311
2312static void
2313intel_dp_handle_test_request(struct intel_dp *intel_dp)
2314{
2315 /* NAK by default */
9324cf7f 2316 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2317}
2318
a4fc5ed6
KP		 2319/*
2320 * According to DP spec
2321 * 5.1.2:
2322 * 1. Read DPCD
2323 * 2. Configure link according to Receiver Capabilities
2324 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2325 * 4. Check link status on receipt of hot-plug interrupt
2326 */
2327
00c09d70 2328void
ea5b213a 2329intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2330{
da63a9f2 2331 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2332 u8 sink_irq_vector;
93f62dad 2333 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2334
da63a9f2 2335 if (!intel_encoder->connectors_active)
d2b996ac 2336 return;
59cd09e1 2337
da63a9f2 2338 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2339 return;
2340
92fd8fd1 2341 /* Try to read receiver status if the link appears to be up */
93f62dad 2342 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2343 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2344 return;
2345 }
2346
92fd8fd1 2347 /* Now read the DPCD to see if it's actually running */
26d61aad 2348 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2349 intel_dp_link_down(intel_dp);
2350 return;
2351 }
2352
a60f0e38
JB		 2353 /* Try to read the source of the interrupt */
2354 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2355 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2356 /* Clear interrupt source */
2357 intel_dp_aux_native_write_1(intel_dp,
2358 DP_DEVICE_SERVICE_IRQ_VECTOR,
2359 sink_irq_vector);
2360
2361 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2362 intel_dp_handle_test_request(intel_dp);
2363 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2364 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2365 }
2366
1ffdff13 2367 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2368 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2369 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2370 intel_dp_start_link_train(intel_dp);
2371 intel_dp_complete_link_train(intel_dp);
3ab9c637 2372 intel_dp_stop_link_train(intel_dp);
33a34e4e 2373 }
a4fc5ed6 2374}
a4fc5ed6 2375
caf9ab24 2376/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2377static enum drm_connector_status
26d61aad 2378intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2379{
caf9ab24
AJ		 2380 uint8_t *dpcd = intel_dp->dpcd;
2381 bool hpd;
2382 uint8_t type;
2383
2384 if (!intel_dp_get_dpcd(intel_dp))
2385 return connector_status_disconnected;
2386
2387 /* if there's no downstream port, we're done */
2388 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2389 return connector_status_connected;
caf9ab24
AJ		 2390
2391 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2392 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2393 if (hpd) {
23235177 2394 uint8_t reg;
caf9ab24 2395 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2396 &reg, 1))
caf9ab24 2397 return connector_status_unknown;
23235177
AJ		 2398 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2399 : connector_status_disconnected;
caf9ab24
AJ		 2400 }
2401
2402 /* If no HPD, poke DDC gently */
2403 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2404 return connector_status_connected;
caf9ab24
AJ		 2405
2406 /* Well we tried, say unknown for unreliable port types */
2407 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2408 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2409 return connector_status_unknown;
2410
2411 /* Anything else is out of spec, warn and ignore */
2412 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2413 return connector_status_disconnected;
71ba9000
AJ		 2414}
2415
5eb08b69 2416static enum drm_connector_status
a9756bb5 2417ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2418{
30add22d 2419 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2420 struct drm_i915_private *dev_priv = dev->dev_private;
2421 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2422 enum drm_connector_status status;
2423
fe16d949
CW		 2424 /* Can't disconnect eDP, but you can close the lid... */
2425 if (is_edp(intel_dp)) {
30add22d 2426 status = intel_panel_detect(dev);
fe16d949
CW		 2427 if (status == connector_status_unknown)
2428 status = connector_status_connected;
2429 return status;
2430 }
01cb9ea6 2431
1b469639
DL		 2432 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2433 return connector_status_disconnected;
2434
26d61aad 2435 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2436}
2437
a4fc5ed6 2438static enum drm_connector_status
a9756bb5 2439g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2440{
30add22d 2441 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2442 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2443 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2444 uint32_t bit;
5eb08b69 2445
35aad75f
JB		 2446 /* Can't disconnect eDP, but you can close the lid... */
2447 if (is_edp(intel_dp)) {
2448 enum drm_connector_status status;
2449
2450 status = intel_panel_detect(dev);
2451 if (status == connector_status_unknown)
2452 status = connector_status_connected;
2453 return status;
2454 }
2455
34f2be46
VS		 2456 switch (intel_dig_port->port) {
2457 case PORT_B:
26739f12 2458 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2459 break;
34f2be46 2460 case PORT_C:
26739f12 2461 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2462 break;
34f2be46 2463 case PORT_D:
26739f12 2464 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2465 break;
2466 default:
2467 return connector_status_unknown;
2468 }
2469
10f76a38 2470 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2471 return connector_status_disconnected;
2472
26d61aad 2473 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2474}
2475
8c241fef
KP		 2476static struct edid *
2477intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2478{
9cd300e0 2479 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2480
9cd300e0
JN		 2481 /* use cached edid if we have one */
2482 if (intel_connector->edid) {
2483 struct edid *edid;
2484 int size;
2485
2486 /* invalid edid */
2487 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2488 return NULL;
2489
9cd300e0 2490 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
edbe1581 2491 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
d6f24d0f
JB		 2492 if (!edid)
2493 return NULL;
2494
d6f24d0f
JB		 2495 return edid;
2496 }
8c241fef 2497
9cd300e0 2498 return drm_get_edid(connector, adapter);
8c241fef
KP		 2499}
2500
2501static int
2502intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2503{
9cd300e0 2504 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2505
9cd300e0
JN		 2506 /* use cached edid if we have one */
2507 if (intel_connector->edid) {
2508 /* invalid edid */
2509 if (IS_ERR(intel_connector->edid))
2510 return 0;
2511
2512 return intel_connector_update_modes(connector,
2513 intel_connector->edid);
d6f24d0f
JB		 2514 }
2515
9cd300e0 2516 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2517}
2518
a9756bb5
ZW		 2519static enum drm_connector_status
2520intel_dp_detect(struct drm_connector *connector, bool force)
2521{
2522 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2523 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2524 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2525 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2526 enum drm_connector_status status;
2527 struct edid *edid = NULL;
2528
2529 intel_dp->has_audio = false;
2530
2531 if (HAS_PCH_SPLIT(dev))
2532 status = ironlake_dp_detect(intel_dp);
2533 else
2534 status = g4x_dp_detect(intel_dp);
1b9be9d0 2535
a9756bb5
ZW		 2536 if (status != connector_status_connected)
2537 return status;
2538
0d198328
AJ		 2539 intel_dp_probe_oui(intel_dp);
2540
c3e5f67b
DV		 2541 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2542 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2543 } else {
8c241fef 2544 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2545 if (edid) {
2546 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2547 kfree(edid);
2548 }
a9756bb5
ZW		 2549 }
2550
d63885da
PZ		 2551 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2552 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2553 return connector_status_connected;
a4fc5ed6
KP		 2554}
2555
2556static int intel_dp_get_modes(struct drm_connector *connector)
2557{
df0e9248 2558 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2559 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2560 struct drm_device *dev = connector->dev;
32f9d658 2561 int ret;
a4fc5ed6
KP		 2562
2563 /* We should parse the EDID data and find out if it has an audio sink
2564 */
2565
8c241fef 2566 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2567 if (ret)
32f9d658
ZW		 2568 return ret;
2569
f8779fda 2570 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2571 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2572 struct drm_display_mode *mode;
dd06f90e
JN		 2573 mode = drm_mode_duplicate(dev,
2574 intel_connector->panel.fixed_mode);
f8779fda 2575 if (mode) {
32f9d658
ZW		 2576 drm_mode_probed_add(connector, mode);
2577 return 1;
2578 }
2579 }
2580 return 0;
a4fc5ed6
KP		 2581}
2582
1aad7ac0
CW		 2583static bool
2584intel_dp_detect_audio(struct drm_connector *connector)
2585{
2586 struct intel_dp *intel_dp = intel_attached_dp(connector);
2587 struct edid *edid;
2588 bool has_audio = false;
2589
8c241fef 2590 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2591 if (edid) {
2592 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2593 kfree(edid);
2594 }
2595
2596 return has_audio;
2597}
2598
f684960e
CW		 2599static int
2600intel_dp_set_property(struct drm_connector *connector,
2601 struct drm_property *property,
2602 uint64_t val)
2603{
e953fd7b 2604 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2605 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2606 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2607 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2608 int ret;
2609
662595df 2610 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2611 if (ret)
2612 return ret;
2613
3f43c48d 2614 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2615 int i = val;
2616 bool has_audio;
2617
2618 if (i == intel_dp->force_audio)
f684960e
CW		 2619 return 0;
2620
1aad7ac0 2621 intel_dp->force_audio = i;
f684960e 2622
c3e5f67b 2623 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2624 has_audio = intel_dp_detect_audio(connector);
2625 else
c3e5f67b 2626 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2627
2628 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2629 return 0;
2630
1aad7ac0 2631 intel_dp->has_audio = has_audio;
f684960e
CW		 2632 goto done;
2633 }
2634
e953fd7b 2635 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2636 bool old_auto = intel_dp->color_range_auto;
2637 uint32_t old_range = intel_dp->color_range;
2638
55bc60db
VS		 2639 switch (val) {
2640 case INTEL_BROADCAST_RGB_AUTO:
2641 intel_dp->color_range_auto = true;
2642 break;
2643 case INTEL_BROADCAST_RGB_FULL:
2644 intel_dp->color_range_auto = false;
2645 intel_dp->color_range = 0;
2646 break;
2647 case INTEL_BROADCAST_RGB_LIMITED:
2648 intel_dp->color_range_auto = false;
2649 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2650 break;
2651 default:
2652 return -EINVAL;
2653 }
ae4edb80
DV		 2654
2655 if (old_auto == intel_dp->color_range_auto &&
2656 old_range == intel_dp->color_range)
2657 return 0;
2658
e953fd7b
CW		 2659 goto done;
2660 }
2661
53b41837
YN		 2662 if (is_edp(intel_dp) &&
2663 property == connector->dev->mode_config.scaling_mode_property) {
2664 if (val == DRM_MODE_SCALE_NONE) {
2665 DRM_DEBUG_KMS("no scaling not supported\n");
2666 return -EINVAL;
2667 }
2668
2669 if (intel_connector->panel.fitting_mode == val) {
2670 /* the eDP scaling property is not changed */
2671 return 0;
2672 }
2673 intel_connector->panel.fitting_mode = val;
2674
2675 goto done;
2676 }
2677
f684960e
CW		 2678 return -EINVAL;
2679
2680done:
c0c36b94
CW		 2681 if (intel_encoder->base.crtc)
2682 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 2683
2684 return 0;
2685}
2686
a4fc5ed6 2687static void
0206e353 2688intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2689{
be3cd5e3 2690 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2691 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2692
9cd300e0
JN		 2693 if (!IS_ERR_OR_NULL(intel_connector->edid))
2694 kfree(intel_connector->edid);
2695
dc652f90 2696 if (is_edp(intel_dp))
1d508706 2697 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 2698
a4fc5ed6
KP		 2699 drm_sysfs_connector_remove(connector);
2700 drm_connector_cleanup(connector);
55f78c43 2701 kfree(connector);
a4fc5ed6
KP		 2702}
2703
00c09d70 2704void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2705{
da63a9f2
PZ		 2706 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2707 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 2708 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 2709
2710 i2c_del_adapter(&intel_dp->adapter);
2711 drm_encoder_cleanup(encoder);
bd943159
KP		 2712 if (is_edp(intel_dp)) {
2713 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 2714 mutex_lock(&dev->mode_config.mutex);
bd943159 2715 ironlake_panel_vdd_off_sync(intel_dp);
bd173813 2716 mutex_unlock(&dev->mode_config.mutex);
bd943159 2717 }
da63a9f2 2718 kfree(intel_dig_port);
24d05927
DV		 2719}
2720
a4fc5ed6 2721static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2722 .mode_set = intel_dp_mode_set,
a4fc5ed6
KP		 2723};
2724
2725static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2726 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2727 .detect = intel_dp_detect,
2728 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2729 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2730 .destroy = intel_dp_destroy,
2731};
2732
2733static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2734 .get_modes = intel_dp_get_modes,
2735 .mode_valid = intel_dp_mode_valid,
df0e9248 2736 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2737};
2738
a4fc5ed6 2739static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2740 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2741};
2742
995b6762 2743static void
21d40d37 2744intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2745{
fa90ecef 2746 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2747
885a5014 2748 intel_dp_check_link_status(intel_dp);
c8110e52 2749}
6207937d 2750
e3421a18
ZW		 2751/* Return which DP Port should be selected for Transcoder DP control */
2752int
0206e353 2753intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2754{
2755 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2756 struct intel_encoder *intel_encoder;
2757 struct intel_dp *intel_dp;
e3421a18 2758
fa90ecef
PZ		 2759 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2760 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2761
fa90ecef
PZ		 2762 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2763 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2764 return intel_dp->output_reg;
e3421a18 2765 }
ea5b213a 2766
e3421a18
ZW		 2767 return -1;
2768}
2769
36e83a18 2770/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2771bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2772{
2773 struct drm_i915_private *dev_priv = dev->dev_private;
2774 struct child_device_config *p_child;
2775 int i;
2776
41aa3448 2777 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 2778 return false;
2779
41aa3448
RV		 2780 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
2781 p_child = dev_priv->vbt.child_dev + i;
36e83a18
ZY		 2782
2783 if (p_child->dvo_port == PORT_IDPD &&
2784 p_child->device_type == DEVICE_TYPE_eDP)
2785 return true;
2786 }
2787 return false;
2788}
2789
f684960e
CW		 2790static void
2791intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2792{
53b41837
YN		 2793 struct intel_connector *intel_connector = to_intel_connector(connector);
2794
3f43c48d 2795 intel_attach_force_audio_property(connector);
e953fd7b 2796 intel_attach_broadcast_rgb_property(connector);
55bc60db 2797 intel_dp->color_range_auto = true;
53b41837
YN		 2798
2799 if (is_edp(intel_dp)) {
2800 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 2801 drm_object_attach_property(
2802 &connector->base,
53b41837 2803 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2804 DRM_MODE_SCALE_ASPECT);
2805 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2806 }
f684960e
CW		 2807}
2808
67a54566
DV		 2809static void
2810intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 2811 struct intel_dp *intel_dp,
2812 struct edp_power_seq *out)
67a54566
DV		 2813{
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815 struct edp_power_seq cur, vbt, spec, final;
2816 u32 pp_on, pp_off, pp_div, pp;
453c5420
JB		 2817 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2818
2819 if (HAS_PCH_SPLIT(dev)) {
2820 pp_control_reg = PCH_PP_CONTROL;
2821 pp_on_reg = PCH_PP_ON_DELAYS;
2822 pp_off_reg = PCH_PP_OFF_DELAYS;
2823 pp_div_reg = PCH_PP_DIVISOR;
2824 } else {
2825 pp_control_reg = PIPEA_PP_CONTROL;
2826 pp_on_reg = PIPEA_PP_ON_DELAYS;
2827 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2828 pp_div_reg = PIPEA_PP_DIVISOR;
2829 }
67a54566
DV		 2830
2831 /* Workaround: Need to write PP_CONTROL with the unlock key as
2832 * the very first thing. */
453c5420
JB		 2833 pp = ironlake_get_pp_control(intel_dp);
2834 I915_WRITE(pp_control_reg, pp);
67a54566 2835
453c5420
JB		 2836 pp_on = I915_READ(pp_on_reg);
2837 pp_off = I915_READ(pp_off_reg);
2838 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 2839
2840 /* Pull timing values out of registers */
2841 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2842 PANEL_POWER_UP_DELAY_SHIFT;
2843
2844 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2845 PANEL_LIGHT_ON_DELAY_SHIFT;
2846
2847 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2848 PANEL_LIGHT_OFF_DELAY_SHIFT;
2849
2850 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2851 PANEL_POWER_DOWN_DELAY_SHIFT;
2852
2853 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2854 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2855
2856 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2857 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2858
41aa3448 2859 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 2860
2861 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2862 * our hw here, which are all in 100usec. */
2863 spec.t1_t3 = 210 * 10;
2864 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2865 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2866 spec.t10 = 500 * 10;
2867 /* This one is special and actually in units of 100ms, but zero
2868 * based in the hw (so we need to add 100 ms). But the sw vbt
2869 * table multiplies it with 1000 to make it in units of 100usec,
2870 * too. */
2871 spec.t11_t12 = (510 + 100) * 10;
2872
2873 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2874 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2875
2876 /* Use the max of the register settings and vbt. If both are
2877 * unset, fall back to the spec limits. */
2878#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2879 spec.field : \
2880 max(cur.field, vbt.field))
2881 assign_final(t1_t3);
2882 assign_final(t8);
2883 assign_final(t9);
2884 assign_final(t10);
2885 assign_final(t11_t12);
2886#undef assign_final
2887
2888#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2889 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2890 intel_dp->backlight_on_delay = get_delay(t8);
2891 intel_dp->backlight_off_delay = get_delay(t9);
2892 intel_dp->panel_power_down_delay = get_delay(t10);
2893 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2894#undef get_delay
2895
f30d26e4
JN		 2896 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2897 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2898 intel_dp->panel_power_cycle_delay);
2899
2900 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2901 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2902
2903 if (out)
2904 *out = final;
2905}
2906
2907static void
2908intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2909 struct intel_dp *intel_dp,
2910 struct edp_power_seq *seq)
2911{
2912 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 2913 u32 pp_on, pp_off, pp_div, port_sel = 0;
2914 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2915 int pp_on_reg, pp_off_reg, pp_div_reg;
2916
2917 if (HAS_PCH_SPLIT(dev)) {
2918 pp_on_reg = PCH_PP_ON_DELAYS;
2919 pp_off_reg = PCH_PP_OFF_DELAYS;
2920 pp_div_reg = PCH_PP_DIVISOR;
2921 } else {
2922 pp_on_reg = PIPEA_PP_ON_DELAYS;
2923 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2924 pp_div_reg = PIPEA_PP_DIVISOR;
2925 }
2926
67a54566 2927 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 2928 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2929 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2930 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2931 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 2932 /* Compute the divisor for the pp clock, simply match the Bspec
2933 * formula. */
453c5420 2934 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 2935 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 2936 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2937
2938 /* Haswell doesn't have any port selection bits for the panel
2939 * power sequencer any more. */
bc7d38a4
ID		 2940 if (IS_VALLEYVIEW(dev)) {
2941 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2942 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2943 if (dp_to_dig_port(intel_dp)->port == PORT_A)
453c5420 2944 port_sel = PANEL_POWER_PORT_DP_A;
67a54566 2945 else
453c5420 2946 port_sel = PANEL_POWER_PORT_DP_D;
67a54566
DV		 2947 }
2948
453c5420
JB		 2949 pp_on |= port_sel;
2950
2951 I915_WRITE(pp_on_reg, pp_on);
2952 I915_WRITE(pp_off_reg, pp_off);
2953 I915_WRITE(pp_div_reg, pp_div);
67a54566 2954
67a54566 2955 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 2956 I915_READ(pp_on_reg),
2957 I915_READ(pp_off_reg),
2958 I915_READ(pp_div_reg));
f684960e
CW		 2959}
2960
a4fc5ed6 2961void
f0fec3f2
PZ		 2962intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2963 struct intel_connector *intel_connector)
a4fc5ed6 2964{
f0fec3f2
PZ		 2965 struct drm_connector *connector = &intel_connector->base;
2966 struct intel_dp *intel_dp = &intel_dig_port->dp;
2967 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2968 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2969 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2970 struct drm_display_mode *fixed_mode = NULL;
f30d26e4 2971 struct edp_power_seq power_seq = { 0 };
174edf1f 2972 enum port port = intel_dig_port->port;
5eb08b69 2973 const char *name = NULL;
b329530c 2974 int type;
a4fc5ed6 2975
0767935e
DV		 2976 /* Preserve the current hw state. */
2977 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2978 intel_dp->attached_connector = intel_connector;
3d3dc149 2979
f7d24902 2980 type = DRM_MODE_CONNECTOR_DisplayPort;
19c03924
GB		 2981 /*
2982 * FIXME : We need to initialize built-in panels before external panels.
2983 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2984 */
f7d24902
ID		 2985 switch (port) {
2986 case PORT_A:
19c03924 2987 type = DRM_MODE_CONNECTOR_eDP;
f7d24902
ID		 2988 break;
2989 case PORT_C:
2990 if (IS_VALLEYVIEW(dev))
2991 type = DRM_MODE_CONNECTOR_eDP;
2992 break;
2993 case PORT_D:
2994 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
2995 type = DRM_MODE_CONNECTOR_eDP;
2996 break;
2997 default: /* silence GCC warning */
2998 break;
b329530c
AJ		 2999 }
3000
f7d24902
ID		 3001 /*
3002 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3003 * for DP the encoder type can be set by the caller to
3004 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3005 */
3006 if (type == DRM_MODE_CONNECTOR_eDP)
3007 intel_encoder->type = INTEL_OUTPUT_EDP;
3008
e7281eab
ID		 3009 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3010 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3011 port_name(port));
3012
b329530c 3013 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3014 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3015
a4fc5ed6
KP		 3016 connector->interlace_allowed = true;
3017 connector->doublescan_allowed = 0;
3018
f0fec3f2
PZ		 3019 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3020 ironlake_panel_vdd_work);
a4fc5ed6 3021
df0e9248 3022 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3023 drm_sysfs_connector_add(connector);
3024
affa9354 3025 if (HAS_DDI(dev))
bcbc889b
PZ		 3026 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3027 else
3028 intel_connector->get_hw_state = intel_connector_get_hw_state;
3029
9ed35ab1
PZ		 3030 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3031 if (HAS_DDI(dev)) {
3032 switch (intel_dig_port->port) {
3033 case PORT_A:
3034 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3035 break;
3036 case PORT_B:
3037 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3038 break;
3039 case PORT_C:
3040 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3041 break;
3042 case PORT_D:
3043 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3044 break;
3045 default:
3046 BUG();
3047 }
3048 }
e8cb4558 3049
a4fc5ed6 3050 /* Set up the DDC bus. */
ab9d7c30
PZ		 3051 switch (port) {
3052 case PORT_A:
1d843f9d 3053 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3054 name = "DPDDC-A";
3055 break;
3056 case PORT_B:
1d843f9d 3057 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3058 name = "DPDDC-B";
3059 break;
3060 case PORT_C:
1d843f9d 3061 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3062 name = "DPDDC-C";
3063 break;
3064 case PORT_D:
1d843f9d 3065 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3066 name = "DPDDC-D";
3067 break;
3068 default:
ad1c0b19 3069 BUG();
5eb08b69
ZW		 3070 }
3071
67a54566 3072 if (is_edp(intel_dp))
f30d26e4 3073 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
c1f05264
DA		 3074
3075 intel_dp_i2c_init(intel_dp, intel_connector, name);
3076
67a54566 3077 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 3078 if (is_edp(intel_dp)) {
3079 bool ret;
f8779fda 3080 struct drm_display_mode *scan;
c1f05264 3081 struct edid *edid;
5d613501
JB		 3082
3083 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 3084 ret = intel_dp_get_dpcd(intel_dp);
bd943159 3085 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 3086
59f3e272 3087 if (ret) {
7183dc29
JB		 3088 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3089 dev_priv->no_aux_handshake =
3090 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 3091 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3092 } else {
3d3dc149 3093 /* if this fails, presume the device is a ghost */
48898b03 3094 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ		 3095 intel_dp_encoder_destroy(&intel_encoder->base);
3096 intel_dp_destroy(connector);
3d3dc149 3097 return;
89667383 3098 }
89667383 3099
f30d26e4
JN		 3100 /* We now know it's not a ghost, init power sequence regs. */
3101 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3102 &power_seq);
3103
d6f24d0f
JB		 3104 ironlake_edp_panel_vdd_on(intel_dp);
3105 edid = drm_get_edid(connector, &intel_dp->adapter);
3106 if (edid) {
9cd300e0
JN		 3107 if (drm_add_edid_modes(connector, edid)) {
3108 drm_mode_connector_update_edid_property(connector, edid);
3109 drm_edid_to_eld(connector, edid);
3110 } else {
3111 kfree(edid);
3112 edid = ERR_PTR(-EINVAL);
3113 }
3114 } else {
3115 edid = ERR_PTR(-ENOENT);
d6f24d0f 3116 }
9cd300e0 3117 intel_connector->edid = edid;
f8779fda
JN		 3118
3119 /* prefer fixed mode from EDID if available */
3120 list_for_each_entry(scan, &connector->probed_modes, head) {
3121 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3122 fixed_mode = drm_mode_duplicate(dev, scan);
3123 break;
3124 }
d6f24d0f 3125 }
f8779fda
JN		 3126
3127 /* fallback to VBT if available for eDP */
41aa3448
RV		 3128 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3129 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
f8779fda
JN		 3130 if (fixed_mode)
3131 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3132 }
f8779fda 3133
d6f24d0f
JB		 3134 ironlake_edp_panel_vdd_off(intel_dp, false);
3135 }
552fb0b7 3136
4d926461 3137 if (is_edp(intel_dp)) {
dd06f90e 3138 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 3139 intel_panel_setup_backlight(connector);
32f9d658
ZW		 3140 }
3141
f684960e
CW		 3142 intel_dp_add_properties(intel_dp, connector);
3143
a4fc5ed6
KP		 3144 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3145 * 0xd. Failure to do so will result in spurious interrupts being
3146 * generated on the port when a cable is not attached.
3147 */
3148 if (IS_G4X(dev) && !IS_GM45(dev)) {
3149 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3150 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3151 }
3152}
f0fec3f2
PZ		 3153
3154void
3155intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3156{
3157 struct intel_digital_port *intel_dig_port;
3158 struct intel_encoder *intel_encoder;
3159 struct drm_encoder *encoder;
3160 struct intel_connector *intel_connector;
3161
3162 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3163 if (!intel_dig_port)
3164 return;
3165
3166 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3167 if (!intel_connector) {
3168 kfree(intel_dig_port);
3169 return;
3170 }
3171
3172 intel_encoder = &intel_dig_port->base;
3173 encoder = &intel_encoder->base;
3174
3175 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3176 DRM_MODE_ENCODER_TMDS);
00c09d70 3177 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 3178
5bfe2ac0 3179 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70
PZ		 3180 intel_encoder->enable = intel_enable_dp;
3181 intel_encoder->pre_enable = intel_pre_enable_dp;
3182 intel_encoder->disable = intel_disable_dp;
3183 intel_encoder->post_disable = intel_post_disable_dp;
3184 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3185 intel_encoder->get_config = intel_dp_get_config;
89b667f8
JB		 3186 if (IS_VALLEYVIEW(dev))
3187 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
f0fec3f2 3188
174edf1f 3189 intel_dig_port->port = port;
f0fec3f2
PZ		 3190 intel_dig_port->dp.output_reg = output_reg;
3191
00c09d70 3192 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3193 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3194 intel_encoder->cloneable = false;
3195 intel_encoder->hot_plug = intel_dp_hot_plug;
3196
3197 intel_dp_init_connector(intel_dig_port, intel_connector);
3198}
Ubuntu Artful kernel mirror