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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
611032bf | 31 | #include <linux/types.h> |
01527b31 CT |
32 | #include <linux/notifier.h> |
33 | #include <linux/reboot.h> | |
611032bf | 34 | #include <asm/byteorder.h> |
760285e7 | 35 | #include <drm/drmP.h> |
c6f95f27 | 36 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
37 | #include <drm/drm_crtc.h> |
38 | #include <drm/drm_crtc_helper.h> | |
39 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 40 | #include "intel_drv.h" |
760285e7 | 41 | #include <drm/i915_drm.h> |
a4fc5ed6 | 42 | #include "i915_drv.h" |
a4fc5ed6 | 43 | |
a4fc5ed6 KP |
44 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
45 | ||
559be30c TP |
46 | /* Compliance test status bits */ |
47 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 | |
48 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
49 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
50 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
51 | ||
9dd4ffdf | 52 | struct dp_link_dpll { |
840b32b7 | 53 | int clock; |
9dd4ffdf CML |
54 | struct dpll dpll; |
55 | }; | |
56 | ||
57 | static const struct dp_link_dpll gen4_dpll[] = { | |
840b32b7 | 58 | { 162000, |
9dd4ffdf | 59 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
840b32b7 | 60 | { 270000, |
9dd4ffdf CML |
61 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
62 | }; | |
63 | ||
64 | static const struct dp_link_dpll pch_dpll[] = { | |
840b32b7 | 65 | { 162000, |
9dd4ffdf | 66 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
840b32b7 | 67 | { 270000, |
9dd4ffdf CML |
68 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
69 | }; | |
70 | ||
65ce4bf5 | 71 | static const struct dp_link_dpll vlv_dpll[] = { |
840b32b7 | 72 | { 162000, |
58f6e632 | 73 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
840b32b7 | 74 | { 270000, |
65ce4bf5 CML |
75 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
76 | }; | |
77 | ||
ef9348c8 CML |
78 | /* |
79 | * CHV supports eDP 1.4 that have more link rates. | |
80 | * Below only provides the fixed rate but exclude variable rate. | |
81 | */ | |
82 | static const struct dp_link_dpll chv_dpll[] = { | |
83 | /* | |
84 | * CHV requires to program fractional division for m2. | |
85 | * m2 is stored in fixed point format using formula below | |
86 | * (m2_int << 22) | m2_fraction | |
87 | */ | |
840b32b7 | 88 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
ef9348c8 | 89 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
840b32b7 | 90 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 | 91 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
840b32b7 | 92 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 CML |
93 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
94 | }; | |
637a9c63 | 95 | |
64987fc5 SJ |
96 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
97 | 324000, 432000, 540000 }; | |
637a9c63 | 98 | static const int skl_rates[] = { 162000, 216000, 270000, |
f4896f15 VS |
99 | 324000, 432000, 540000 }; |
100 | static const int default_rates[] = { 162000, 270000, 540000 }; | |
ef9348c8 | 101 | |
cfcb0fc9 JB |
102 | /** |
103 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
104 | * @intel_dp: DP struct | |
105 | * | |
106 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
107 | * will return true, and false otherwise. | |
108 | */ | |
109 | static bool is_edp(struct intel_dp *intel_dp) | |
110 | { | |
da63a9f2 PZ |
111 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
112 | ||
113 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
114 | } |
115 | ||
68b4d824 | 116 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 117 | { |
68b4d824 ID |
118 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
119 | ||
120 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
121 | } |
122 | ||
df0e9248 CW |
123 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
124 | { | |
fa90ecef | 125 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
126 | } |
127 | ||
ea5b213a | 128 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
1e0560e0 | 129 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 130 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
093e3f13 | 131 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
a8c3344e VS |
132 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
133 | enum pipe pipe); | |
f21a2198 | 134 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
a4fc5ed6 | 135 | |
ed4e9c1d VS |
136 | static int |
137 | intel_dp_max_link_bw(struct intel_dp *intel_dp) | |
a4fc5ed6 | 138 | { |
7183dc29 | 139 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
140 | |
141 | switch (max_link_bw) { | |
142 | case DP_LINK_BW_1_62: | |
143 | case DP_LINK_BW_2_7: | |
1db10e28 | 144 | case DP_LINK_BW_5_4: |
d4eead50 | 145 | break; |
a4fc5ed6 | 146 | default: |
d4eead50 ID |
147 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
148 | max_link_bw); | |
a4fc5ed6 KP |
149 | max_link_bw = DP_LINK_BW_1_62; |
150 | break; | |
151 | } | |
152 | return max_link_bw; | |
153 | } | |
154 | ||
eeb6324d PZ |
155 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
156 | { | |
157 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
eeb6324d PZ |
158 | u8 source_max, sink_max; |
159 | ||
ccb1a831 | 160 | source_max = intel_dig_port->max_lanes; |
f482984a | 161 | sink_max = intel_dp->max_sink_lane_count; |
eeb6324d PZ |
162 | |
163 | return min(source_max, sink_max); | |
164 | } | |
165 | ||
22a2c8e0 | 166 | int |
c898261c | 167 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 168 | { |
fd81c44e DP |
169 | /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ |
170 | return DIV_ROUND_UP(pixel_clock * bpp, 8); | |
a4fc5ed6 KP |
171 | } |
172 | ||
22a2c8e0 | 173 | int |
fe27d53e DA |
174 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
175 | { | |
fd81c44e DP |
176 | /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the |
177 | * link rate that is generally expressed in Gbps. Since, 8 bits of data | |
178 | * is transmitted every LS_Clk per lane, there is no need to account for | |
179 | * the channel encoding that is done in the PHY layer here. | |
180 | */ | |
181 | ||
182 | return max_link_clock * max_lanes; | |
fe27d53e DA |
183 | } |
184 | ||
70ec0645 MK |
185 | static int |
186 | intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) | |
187 | { | |
188 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
189 | struct intel_encoder *encoder = &intel_dig_port->base; | |
190 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
191 | int max_dotclk = dev_priv->max_dotclk_freq; | |
192 | int ds_max_dotclk; | |
193 | ||
194 | int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
195 | ||
196 | if (type != DP_DS_PORT_TYPE_VGA) | |
197 | return max_dotclk; | |
198 | ||
199 | ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, | |
200 | intel_dp->downstream_ports); | |
201 | ||
202 | if (ds_max_dotclk != 0) | |
203 | max_dotclk = min(max_dotclk, ds_max_dotclk); | |
204 | ||
205 | return max_dotclk; | |
206 | } | |
207 | ||
40dba341 NM |
208 | static int |
209 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) | |
210 | { | |
211 | if (intel_dp->num_sink_rates) { | |
212 | *sink_rates = intel_dp->sink_rates; | |
213 | return intel_dp->num_sink_rates; | |
214 | } | |
215 | ||
216 | *sink_rates = default_rates; | |
217 | ||
f482984a | 218 | return (intel_dp->max_sink_link_bw >> 3) + 1; |
40dba341 NM |
219 | } |
220 | ||
221 | static int | |
222 | intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) | |
223 | { | |
224 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
225 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
226 | int size; | |
227 | ||
cc3f90f0 | 228 | if (IS_GEN9_LP(dev_priv)) { |
40dba341 NM |
229 | *source_rates = bxt_rates; |
230 | size = ARRAY_SIZE(bxt_rates); | |
b976dc53 | 231 | } else if (IS_GEN9_BC(dev_priv)) { |
40dba341 NM |
232 | *source_rates = skl_rates; |
233 | size = ARRAY_SIZE(skl_rates); | |
234 | } else { | |
235 | *source_rates = default_rates; | |
236 | size = ARRAY_SIZE(default_rates); | |
237 | } | |
238 | ||
239 | /* This depends on the fact that 5.4 is last value in the array */ | |
240 | if (!intel_dp_source_supports_hbr2(intel_dp)) | |
241 | size--; | |
242 | ||
243 | return size; | |
244 | } | |
245 | ||
246 | static int intersect_rates(const int *source_rates, int source_len, | |
247 | const int *sink_rates, int sink_len, | |
248 | int *common_rates) | |
249 | { | |
250 | int i = 0, j = 0, k = 0; | |
251 | ||
252 | while (i < source_len && j < sink_len) { | |
253 | if (source_rates[i] == sink_rates[j]) { | |
254 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) | |
255 | return k; | |
256 | common_rates[k] = source_rates[i]; | |
257 | ++k; | |
258 | ++i; | |
259 | ++j; | |
260 | } else if (source_rates[i] < sink_rates[j]) { | |
261 | ++i; | |
262 | } else { | |
263 | ++j; | |
264 | } | |
265 | } | |
266 | return k; | |
267 | } | |
268 | ||
269 | static int intel_dp_common_rates(struct intel_dp *intel_dp, | |
270 | int *common_rates) | |
271 | { | |
272 | const int *source_rates, *sink_rates; | |
273 | int source_len, sink_len; | |
274 | ||
275 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); | |
276 | source_len = intel_dp_source_rates(intel_dp, &source_rates); | |
277 | ||
278 | return intersect_rates(source_rates, source_len, | |
279 | sink_rates, sink_len, | |
280 | common_rates); | |
281 | } | |
282 | ||
fdb14d33 MN |
283 | static int intel_dp_link_rate_index(struct intel_dp *intel_dp, |
284 | int *common_rates, int link_rate) | |
285 | { | |
286 | int common_len; | |
287 | int index; | |
288 | ||
289 | common_len = intel_dp_common_rates(intel_dp, common_rates); | |
290 | for (index = 0; index < common_len; index++) { | |
291 | if (link_rate == common_rates[common_len - index - 1]) | |
292 | return common_len - index - 1; | |
293 | } | |
294 | ||
295 | return -1; | |
296 | } | |
297 | ||
298 | int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, | |
299 | int link_rate, uint8_t lane_count) | |
300 | { | |
301 | int common_rates[DP_MAX_SUPPORTED_RATES]; | |
302 | int link_rate_index; | |
303 | ||
304 | link_rate_index = intel_dp_link_rate_index(intel_dp, | |
305 | common_rates, | |
306 | link_rate); | |
307 | if (link_rate_index > 0) { | |
308 | intel_dp->max_sink_link_bw = drm_dp_link_rate_to_bw_code(common_rates[link_rate_index - 1]); | |
309 | intel_dp->max_sink_lane_count = lane_count; | |
310 | } else if (lane_count > 1) { | |
311 | intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp); | |
312 | intel_dp->max_sink_lane_count = lane_count >> 1; | |
313 | } else { | |
314 | DRM_ERROR("Link Training Unsuccessful\n"); | |
315 | return -1; | |
316 | } | |
317 | ||
318 | return 0; | |
319 | } | |
320 | ||
c19de8eb | 321 | static enum drm_mode_status |
a4fc5ed6 KP |
322 | intel_dp_mode_valid(struct drm_connector *connector, |
323 | struct drm_display_mode *mode) | |
324 | { | |
df0e9248 | 325 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
326 | struct intel_connector *intel_connector = to_intel_connector(connector); |
327 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
328 | int target_clock = mode->clock; |
329 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
70ec0645 MK |
330 | int max_dotclk; |
331 | ||
332 | max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); | |
a4fc5ed6 | 333 | |
dd06f90e JN |
334 | if (is_edp(intel_dp) && fixed_mode) { |
335 | if (mode->hdisplay > fixed_mode->hdisplay) | |
7de56f43 ZY |
336 | return MODE_PANEL; |
337 | ||
dd06f90e | 338 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 339 | return MODE_PANEL; |
03afc4a2 DV |
340 | |
341 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
342 | } |
343 | ||
50fec21a | 344 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
eeb6324d | 345 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 DV |
346 | |
347 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
348 | mode_rate = intel_dp_link_required(target_clock, 18); | |
349 | ||
799487f5 | 350 | if (mode_rate > max_rate || target_clock > max_dotclk) |
c4867936 | 351 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
352 | |
353 | if (mode->clock < 10000) | |
354 | return MODE_CLOCK_LOW; | |
355 | ||
0af78a2b DV |
356 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
357 | return MODE_H_ILLEGAL; | |
358 | ||
a4fc5ed6 KP |
359 | return MODE_OK; |
360 | } | |
361 | ||
a4f1289e | 362 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
a4fc5ed6 KP |
363 | { |
364 | int i; | |
365 | uint32_t v = 0; | |
366 | ||
367 | if (src_bytes > 4) | |
368 | src_bytes = 4; | |
369 | for (i = 0; i < src_bytes; i++) | |
370 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
371 | return v; | |
372 | } | |
373 | ||
c2af70e2 | 374 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
a4fc5ed6 KP |
375 | { |
376 | int i; | |
377 | if (dst_bytes > 4) | |
378 | dst_bytes = 4; | |
379 | for (i = 0; i < dst_bytes; i++) | |
380 | dst[i] = src >> ((3-i) * 8); | |
381 | } | |
382 | ||
bf13e81b JN |
383 | static void |
384 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
36b5f425 | 385 | struct intel_dp *intel_dp); |
bf13e81b JN |
386 | static void |
387 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
5d5ab2d2 VS |
388 | struct intel_dp *intel_dp, |
389 | bool force_disable_vdd); | |
335f752b ID |
390 | static void |
391 | intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp); | |
bf13e81b | 392 | |
773538e8 VS |
393 | static void pps_lock(struct intel_dp *intel_dp) |
394 | { | |
395 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
396 | struct intel_encoder *encoder = &intel_dig_port->base; | |
397 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 398 | struct drm_i915_private *dev_priv = to_i915(dev); |
773538e8 VS |
399 | enum intel_display_power_domain power_domain; |
400 | ||
401 | /* | |
402 | * See vlv_power_sequencer_reset() why we need | |
403 | * a power domain reference here. | |
404 | */ | |
25f78f58 | 405 | power_domain = intel_display_port_aux_power_domain(encoder); |
773538e8 VS |
406 | intel_display_power_get(dev_priv, power_domain); |
407 | ||
408 | mutex_lock(&dev_priv->pps_mutex); | |
409 | } | |
410 | ||
411 | static void pps_unlock(struct intel_dp *intel_dp) | |
412 | { | |
413 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
414 | struct intel_encoder *encoder = &intel_dig_port->base; | |
415 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 416 | struct drm_i915_private *dev_priv = to_i915(dev); |
773538e8 VS |
417 | enum intel_display_power_domain power_domain; |
418 | ||
419 | mutex_unlock(&dev_priv->pps_mutex); | |
420 | ||
25f78f58 | 421 | power_domain = intel_display_port_aux_power_domain(encoder); |
773538e8 VS |
422 | intel_display_power_put(dev_priv, power_domain); |
423 | } | |
424 | ||
961a0db0 VS |
425 | static void |
426 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) | |
427 | { | |
428 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
30ad9814 | 429 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
961a0db0 | 430 | enum pipe pipe = intel_dp->pps_pipe; |
0047eedc VS |
431 | bool pll_enabled, release_cl_override = false; |
432 | enum dpio_phy phy = DPIO_PHY(pipe); | |
433 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); | |
961a0db0 VS |
434 | uint32_t DP; |
435 | ||
436 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, | |
437 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", | |
438 | pipe_name(pipe), port_name(intel_dig_port->port))) | |
439 | return; | |
440 | ||
441 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", | |
442 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
443 | ||
444 | /* Preserve the BIOS-computed detected bit. This is | |
445 | * supposed to be read-only. | |
446 | */ | |
447 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
448 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
449 | DP |= DP_PORT_WIDTH(1); | |
450 | DP |= DP_LINK_TRAIN_PAT_1; | |
451 | ||
920a14b2 | 452 | if (IS_CHERRYVIEW(dev_priv)) |
961a0db0 VS |
453 | DP |= DP_PIPE_SELECT_CHV(pipe); |
454 | else if (pipe == PIPE_B) | |
455 | DP |= DP_PIPEB_SELECT; | |
456 | ||
d288f65f VS |
457 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
458 | ||
459 | /* | |
460 | * The DPLL for the pipe must be enabled for this to work. | |
461 | * So enable temporarily it if it's not already enabled. | |
462 | */ | |
0047eedc | 463 | if (!pll_enabled) { |
920a14b2 | 464 | release_cl_override = IS_CHERRYVIEW(dev_priv) && |
0047eedc VS |
465 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
466 | ||
30ad9814 | 467 | if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ? |
3f36b937 TU |
468 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
469 | DRM_ERROR("Failed to force on pll for pipe %c!\n", | |
470 | pipe_name(pipe)); | |
471 | return; | |
472 | } | |
0047eedc | 473 | } |
d288f65f | 474 | |
961a0db0 VS |
475 | /* |
476 | * Similar magic as in intel_dp_enable_port(). | |
477 | * We _must_ do this port enable + disable trick | |
478 | * to make this power seqeuencer lock onto the port. | |
479 | * Otherwise even VDD force bit won't work. | |
480 | */ | |
481 | I915_WRITE(intel_dp->output_reg, DP); | |
482 | POSTING_READ(intel_dp->output_reg); | |
483 | ||
484 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); | |
485 | POSTING_READ(intel_dp->output_reg); | |
486 | ||
487 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); | |
488 | POSTING_READ(intel_dp->output_reg); | |
d288f65f | 489 | |
0047eedc | 490 | if (!pll_enabled) { |
30ad9814 | 491 | vlv_force_pll_off(dev_priv, pipe); |
0047eedc VS |
492 | |
493 | if (release_cl_override) | |
494 | chv_phy_powergate_ch(dev_priv, phy, ch, false); | |
495 | } | |
961a0db0 VS |
496 | } |
497 | ||
9f2bdb00 VS |
498 | static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv) |
499 | { | |
500 | struct intel_encoder *encoder; | |
501 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); | |
502 | ||
503 | /* | |
504 | * We don't have power sequencer currently. | |
505 | * Pick one that's not used by other ports. | |
506 | */ | |
507 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
508 | struct intel_dp *intel_dp; | |
509 | ||
510 | if (encoder->type != INTEL_OUTPUT_DP && | |
511 | encoder->type != INTEL_OUTPUT_EDP) | |
512 | continue; | |
513 | ||
514 | intel_dp = enc_to_intel_dp(&encoder->base); | |
515 | ||
516 | if (encoder->type == INTEL_OUTPUT_EDP) { | |
517 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE && | |
518 | intel_dp->active_pipe != intel_dp->pps_pipe); | |
519 | ||
520 | if (intel_dp->pps_pipe != INVALID_PIPE) | |
521 | pipes &= ~(1 << intel_dp->pps_pipe); | |
522 | } else { | |
523 | WARN_ON(intel_dp->pps_pipe != INVALID_PIPE); | |
524 | ||
525 | if (intel_dp->active_pipe != INVALID_PIPE) | |
526 | pipes &= ~(1 << intel_dp->active_pipe); | |
527 | } | |
528 | } | |
529 | ||
530 | if (pipes == 0) | |
531 | return INVALID_PIPE; | |
532 | ||
533 | return ffs(pipes) - 1; | |
534 | } | |
535 | ||
bf13e81b JN |
536 | static enum pipe |
537 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
538 | { | |
539 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bf13e81b | 540 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 541 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8c3344e | 542 | enum pipe pipe; |
bf13e81b | 543 | |
e39b999a | 544 | lockdep_assert_held(&dev_priv->pps_mutex); |
bf13e81b | 545 | |
a8c3344e VS |
546 | /* We should never land here with regular DP ports */ |
547 | WARN_ON(!is_edp(intel_dp)); | |
548 | ||
9f2bdb00 VS |
549 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE && |
550 | intel_dp->active_pipe != intel_dp->pps_pipe); | |
551 | ||
a4a5d2f8 VS |
552 | if (intel_dp->pps_pipe != INVALID_PIPE) |
553 | return intel_dp->pps_pipe; | |
554 | ||
9f2bdb00 | 555 | pipe = vlv_find_free_pps(dev_priv); |
a4a5d2f8 VS |
556 | |
557 | /* | |
558 | * Didn't find one. This should not happen since there | |
559 | * are two power sequencers and up to two eDP ports. | |
560 | */ | |
9f2bdb00 | 561 | if (WARN_ON(pipe == INVALID_PIPE)) |
a8c3344e | 562 | pipe = PIPE_A; |
a4a5d2f8 | 563 | |
a8c3344e VS |
564 | vlv_steal_power_sequencer(dev, pipe); |
565 | intel_dp->pps_pipe = pipe; | |
a4a5d2f8 VS |
566 | |
567 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", | |
568 | pipe_name(intel_dp->pps_pipe), | |
569 | port_name(intel_dig_port->port)); | |
570 | ||
571 | /* init power sequencer on this pipe and port */ | |
36b5f425 | 572 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
5d5ab2d2 | 573 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true); |
a4a5d2f8 | 574 | |
961a0db0 VS |
575 | /* |
576 | * Even vdd force doesn't work until we've made | |
577 | * the power sequencer lock in on the port. | |
578 | */ | |
579 | vlv_power_sequencer_kick(intel_dp); | |
a4a5d2f8 VS |
580 | |
581 | return intel_dp->pps_pipe; | |
582 | } | |
583 | ||
78597996 ID |
584 | static int |
585 | bxt_power_sequencer_idx(struct intel_dp *intel_dp) | |
586 | { | |
587 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
588 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 589 | struct drm_i915_private *dev_priv = to_i915(dev); |
78597996 ID |
590 | |
591 | lockdep_assert_held(&dev_priv->pps_mutex); | |
592 | ||
593 | /* We should never land here with regular DP ports */ | |
594 | WARN_ON(!is_edp(intel_dp)); | |
595 | ||
596 | /* | |
597 | * TODO: BXT has 2 PPS instances. The correct port->PPS instance | |
598 | * mapping needs to be retrieved from VBT, for now just hard-code to | |
599 | * use instance #0 always. | |
600 | */ | |
601 | if (!intel_dp->pps_reset) | |
602 | return 0; | |
603 | ||
604 | intel_dp->pps_reset = false; | |
605 | ||
606 | /* | |
607 | * Only the HW needs to be reprogrammed, the SW state is fixed and | |
608 | * has been setup during connector init. | |
609 | */ | |
5d5ab2d2 | 610 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false); |
78597996 ID |
611 | |
612 | return 0; | |
613 | } | |
614 | ||
6491ab27 VS |
615 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
616 | enum pipe pipe); | |
617 | ||
618 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, | |
619 | enum pipe pipe) | |
620 | { | |
44cb734c | 621 | return I915_READ(PP_STATUS(pipe)) & PP_ON; |
6491ab27 VS |
622 | } |
623 | ||
624 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, | |
625 | enum pipe pipe) | |
626 | { | |
44cb734c | 627 | return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
6491ab27 VS |
628 | } |
629 | ||
630 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, | |
631 | enum pipe pipe) | |
632 | { | |
633 | return true; | |
634 | } | |
bf13e81b | 635 | |
a4a5d2f8 | 636 | static enum pipe |
6491ab27 VS |
637 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
638 | enum port port, | |
639 | vlv_pipe_check pipe_check) | |
a4a5d2f8 VS |
640 | { |
641 | enum pipe pipe; | |
bf13e81b | 642 | |
bf13e81b | 643 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
44cb734c | 644 | u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & |
bf13e81b | 645 | PANEL_PORT_SELECT_MASK; |
a4a5d2f8 VS |
646 | |
647 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) | |
648 | continue; | |
649 | ||
6491ab27 VS |
650 | if (!pipe_check(dev_priv, pipe)) |
651 | continue; | |
652 | ||
a4a5d2f8 | 653 | return pipe; |
bf13e81b JN |
654 | } |
655 | ||
a4a5d2f8 VS |
656 | return INVALID_PIPE; |
657 | } | |
658 | ||
659 | static void | |
660 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) | |
661 | { | |
662 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
663 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 664 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
665 | enum port port = intel_dig_port->port; |
666 | ||
667 | lockdep_assert_held(&dev_priv->pps_mutex); | |
668 | ||
669 | /* try to find a pipe with this port selected */ | |
6491ab27 VS |
670 | /* first pick one where the panel is on */ |
671 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
672 | vlv_pipe_has_pp_on); | |
673 | /* didn't find one? pick one where vdd is on */ | |
674 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
675 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
676 | vlv_pipe_has_vdd_on); | |
677 | /* didn't find one? pick one with just the correct port */ | |
678 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
679 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
680 | vlv_pipe_any); | |
a4a5d2f8 VS |
681 | |
682 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ | |
683 | if (intel_dp->pps_pipe == INVALID_PIPE) { | |
684 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", | |
685 | port_name(port)); | |
686 | return; | |
bf13e81b JN |
687 | } |
688 | ||
a4a5d2f8 VS |
689 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
690 | port_name(port), pipe_name(intel_dp->pps_pipe)); | |
691 | ||
36b5f425 | 692 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
5d5ab2d2 | 693 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false); |
bf13e81b JN |
694 | } |
695 | ||
78597996 | 696 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) |
773538e8 | 697 | { |
91c8a326 | 698 | struct drm_device *dev = &dev_priv->drm; |
773538e8 VS |
699 | struct intel_encoder *encoder; |
700 | ||
920a14b2 | 701 | if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 702 | !IS_GEN9_LP(dev_priv))) |
773538e8 VS |
703 | return; |
704 | ||
705 | /* | |
706 | * We can't grab pps_mutex here due to deadlock with power_domain | |
707 | * mutex when power_domain functions are called while holding pps_mutex. | |
708 | * That also means that in order to use pps_pipe the code needs to | |
709 | * hold both a power domain reference and pps_mutex, and the power domain | |
710 | * reference get/put must be done while _not_ holding pps_mutex. | |
711 | * pps_{lock,unlock}() do these steps in the correct order, so one | |
712 | * should use them always. | |
713 | */ | |
714 | ||
19c8054c | 715 | for_each_intel_encoder(dev, encoder) { |
773538e8 VS |
716 | struct intel_dp *intel_dp; |
717 | ||
9f2bdb00 VS |
718 | if (encoder->type != INTEL_OUTPUT_DP && |
719 | encoder->type != INTEL_OUTPUT_EDP) | |
773538e8 VS |
720 | continue; |
721 | ||
722 | intel_dp = enc_to_intel_dp(&encoder->base); | |
9f2bdb00 VS |
723 | |
724 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); | |
725 | ||
726 | if (encoder->type != INTEL_OUTPUT_EDP) | |
727 | continue; | |
728 | ||
cc3f90f0 | 729 | if (IS_GEN9_LP(dev_priv)) |
78597996 ID |
730 | intel_dp->pps_reset = true; |
731 | else | |
732 | intel_dp->pps_pipe = INVALID_PIPE; | |
773538e8 | 733 | } |
bf13e81b JN |
734 | } |
735 | ||
8e8232d5 ID |
736 | struct pps_registers { |
737 | i915_reg_t pp_ctrl; | |
738 | i915_reg_t pp_stat; | |
739 | i915_reg_t pp_on; | |
740 | i915_reg_t pp_off; | |
741 | i915_reg_t pp_div; | |
742 | }; | |
743 | ||
744 | static void intel_pps_get_registers(struct drm_i915_private *dev_priv, | |
745 | struct intel_dp *intel_dp, | |
746 | struct pps_registers *regs) | |
747 | { | |
44cb734c ID |
748 | int pps_idx = 0; |
749 | ||
8e8232d5 ID |
750 | memset(regs, 0, sizeof(*regs)); |
751 | ||
cc3f90f0 | 752 | if (IS_GEN9_LP(dev_priv)) |
44cb734c ID |
753 | pps_idx = bxt_power_sequencer_idx(intel_dp); |
754 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
755 | pps_idx = vlv_power_sequencer_pipe(intel_dp); | |
8e8232d5 | 756 | |
44cb734c ID |
757 | regs->pp_ctrl = PP_CONTROL(pps_idx); |
758 | regs->pp_stat = PP_STATUS(pps_idx); | |
759 | regs->pp_on = PP_ON_DELAYS(pps_idx); | |
760 | regs->pp_off = PP_OFF_DELAYS(pps_idx); | |
cc3f90f0 | 761 | if (!IS_GEN9_LP(dev_priv)) |
44cb734c | 762 | regs->pp_div = PP_DIVISOR(pps_idx); |
8e8232d5 ID |
763 | } |
764 | ||
f0f59a00 VS |
765 | static i915_reg_t |
766 | _pp_ctrl_reg(struct intel_dp *intel_dp) | |
bf13e81b | 767 | { |
8e8232d5 | 768 | struct pps_registers regs; |
bf13e81b | 769 | |
8e8232d5 ID |
770 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
771 | ®s); | |
772 | ||
773 | return regs.pp_ctrl; | |
bf13e81b JN |
774 | } |
775 | ||
f0f59a00 VS |
776 | static i915_reg_t |
777 | _pp_stat_reg(struct intel_dp *intel_dp) | |
bf13e81b | 778 | { |
8e8232d5 | 779 | struct pps_registers regs; |
bf13e81b | 780 | |
8e8232d5 ID |
781 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
782 | ®s); | |
783 | ||
784 | return regs.pp_stat; | |
bf13e81b JN |
785 | } |
786 | ||
01527b31 CT |
787 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
788 | This function only applicable when panel PM state is not to be tracked */ | |
789 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, | |
790 | void *unused) | |
791 | { | |
792 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), | |
793 | edp_notifier); | |
794 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 795 | struct drm_i915_private *dev_priv = to_i915(dev); |
01527b31 CT |
796 | |
797 | if (!is_edp(intel_dp) || code != SYS_RESTART) | |
798 | return 0; | |
799 | ||
773538e8 | 800 | pps_lock(intel_dp); |
e39b999a | 801 | |
920a14b2 | 802 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e39b999a | 803 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
f0f59a00 | 804 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
649636ef | 805 | u32 pp_div; |
e39b999a | 806 | |
44cb734c ID |
807 | pp_ctrl_reg = PP_CONTROL(pipe); |
808 | pp_div_reg = PP_DIVISOR(pipe); | |
01527b31 CT |
809 | pp_div = I915_READ(pp_div_reg); |
810 | pp_div &= PP_REFERENCE_DIVIDER_MASK; | |
811 | ||
812 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ | |
813 | I915_WRITE(pp_div_reg, pp_div | 0x1F); | |
814 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); | |
815 | msleep(intel_dp->panel_power_cycle_delay); | |
816 | } | |
817 | ||
773538e8 | 818 | pps_unlock(intel_dp); |
e39b999a | 819 | |
01527b31 CT |
820 | return 0; |
821 | } | |
822 | ||
4be73780 | 823 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 824 | { |
30add22d | 825 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 826 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 827 | |
e39b999a VS |
828 | lockdep_assert_held(&dev_priv->pps_mutex); |
829 | ||
920a14b2 | 830 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
831 | intel_dp->pps_pipe == INVALID_PIPE) |
832 | return false; | |
833 | ||
bf13e81b | 834 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
835 | } |
836 | ||
4be73780 | 837 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 838 | { |
30add22d | 839 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 840 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 841 | |
e39b999a VS |
842 | lockdep_assert_held(&dev_priv->pps_mutex); |
843 | ||
920a14b2 | 844 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
845 | intel_dp->pps_pipe == INVALID_PIPE) |
846 | return false; | |
847 | ||
773538e8 | 848 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
ebf33b18 KP |
849 | } |
850 | ||
9b984dae KP |
851 | static void |
852 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
853 | { | |
30add22d | 854 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 855 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 856 | |
9b984dae KP |
857 | if (!is_edp(intel_dp)) |
858 | return; | |
453c5420 | 859 | |
4be73780 | 860 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
861 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
862 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
863 | I915_READ(_pp_stat_reg(intel_dp)), |
864 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
865 | } |
866 | } | |
867 | ||
9ee32fea DV |
868 | static uint32_t |
869 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
870 | { | |
871 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
872 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 873 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 874 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
875 | uint32_t status; |
876 | bool done; | |
877 | ||
ef04f00d | 878 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 879 | if (has_aux_irq) |
b18ac466 | 880 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 881 | msecs_to_jiffies_timeout(10)); |
9ee32fea | 882 | else |
713a6b66 | 883 | done = wait_for(C, 10) == 0; |
9ee32fea DV |
884 | if (!done) |
885 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
886 | has_aux_irq); | |
887 | #undef C | |
888 | ||
889 | return status; | |
890 | } | |
891 | ||
6ffb1be7 | 892 | static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 893 | { |
174edf1f | 894 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
e7dc33f3 | 895 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
9ee32fea | 896 | |
a457f54b VS |
897 | if (index) |
898 | return 0; | |
899 | ||
ec5b01dd DL |
900 | /* |
901 | * The clock divider is based off the hrawclk, and would like to run at | |
a457f54b | 902 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
a4fc5ed6 | 903 | */ |
a457f54b | 904 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
ec5b01dd DL |
905 | } |
906 | ||
907 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
908 | { | |
909 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 910 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd DL |
911 | |
912 | if (index) | |
913 | return 0; | |
914 | ||
a457f54b VS |
915 | /* |
916 | * The clock divider is based off the cdclk or PCH rawclk, and would | |
917 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and | |
918 | * divide by 2000 and use that | |
919 | */ | |
e7dc33f3 | 920 | if (intel_dig_port->port == PORT_A) |
fce18c4c | 921 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
e7dc33f3 VS |
922 | else |
923 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); | |
ec5b01dd DL |
924 | } |
925 | ||
926 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
927 | { | |
928 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 929 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd | 930 | |
a457f54b | 931 | if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { |
2c55c336 | 932 | /* Workaround for non-ULT HSW */ |
bc86625a CW |
933 | switch (index) { |
934 | case 0: return 63; | |
935 | case 1: return 72; | |
936 | default: return 0; | |
937 | } | |
2c55c336 | 938 | } |
a457f54b VS |
939 | |
940 | return ilk_get_aux_clock_divider(intel_dp, index); | |
b84a1cf8 RV |
941 | } |
942 | ||
b6b5e383 DL |
943 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
944 | { | |
945 | /* | |
946 | * SKL doesn't need us to program the AUX clock divider (Hardware will | |
947 | * derive the clock from CDCLK automatically). We still implement the | |
948 | * get_aux_clock_divider vfunc to plug-in into the existing code. | |
949 | */ | |
950 | return index ? 0 : 1; | |
951 | } | |
952 | ||
6ffb1be7 VS |
953 | static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
954 | bool has_aux_irq, | |
955 | int send_bytes, | |
956 | uint32_t aux_clock_divider) | |
5ed12a19 DL |
957 | { |
958 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
8652744b TU |
959 | struct drm_i915_private *dev_priv = |
960 | to_i915(intel_dig_port->base.base.dev); | |
5ed12a19 DL |
961 | uint32_t precharge, timeout; |
962 | ||
8652744b | 963 | if (IS_GEN6(dev_priv)) |
5ed12a19 DL |
964 | precharge = 3; |
965 | else | |
966 | precharge = 5; | |
967 | ||
8652744b | 968 | if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A) |
5ed12a19 DL |
969 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
970 | else | |
971 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
972 | ||
973 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 974 | DP_AUX_CH_CTL_DONE | |
5ed12a19 | 975 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
788d4433 | 976 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 977 | timeout | |
788d4433 | 978 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
979 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
980 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 981 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
982 | } |
983 | ||
b9ca5fad DL |
984 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
985 | bool has_aux_irq, | |
986 | int send_bytes, | |
987 | uint32_t unused) | |
988 | { | |
989 | return DP_AUX_CH_CTL_SEND_BUSY | | |
990 | DP_AUX_CH_CTL_DONE | | |
991 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | | |
992 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
993 | DP_AUX_CH_CTL_TIME_OUT_1600us | | |
994 | DP_AUX_CH_CTL_RECEIVE_ERROR | | |
995 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
d4dcbdce | 996 | DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | |
b9ca5fad DL |
997 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
998 | } | |
999 | ||
b84a1cf8 RV |
1000 | static int |
1001 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
bd9f74a5 | 1002 | const uint8_t *send, int send_bytes, |
b84a1cf8 RV |
1003 | uint8_t *recv, int recv_size) |
1004 | { | |
1005 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
0031fb96 TU |
1006 | struct drm_i915_private *dev_priv = |
1007 | to_i915(intel_dig_port->base.base.dev); | |
f0f59a00 | 1008 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
bc86625a | 1009 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
1010 | int i, ret, recv_bytes; |
1011 | uint32_t status; | |
5ed12a19 | 1012 | int try, clock = 0; |
0031fb96 | 1013 | bool has_aux_irq = HAS_AUX_IRQ(dev_priv); |
884f19e9 JN |
1014 | bool vdd; |
1015 | ||
773538e8 | 1016 | pps_lock(intel_dp); |
e39b999a | 1017 | |
72c3500a VS |
1018 | /* |
1019 | * We will be called with VDD already enabled for dpcd/edid/oui reads. | |
1020 | * In such cases we want to leave VDD enabled and it's up to upper layers | |
1021 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off | |
1022 | * ourselves. | |
1023 | */ | |
1e0560e0 | 1024 | vdd = edp_panel_vdd_on(intel_dp); |
b84a1cf8 RV |
1025 | |
1026 | /* dp aux is extremely sensitive to irq latency, hence request the | |
1027 | * lowest possible wakeup latency and so prevent the cpu from going into | |
1028 | * deep sleep states. | |
1029 | */ | |
1030 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
1031 | ||
1032 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 1033 | |
11bee43e JB |
1034 | /* Try to wait for any previous AUX channel activity */ |
1035 | for (try = 0; try < 3; try++) { | |
ef04f00d | 1036 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
1037 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
1038 | break; | |
1039 | msleep(1); | |
1040 | } | |
1041 | ||
1042 | if (try == 3) { | |
02196c77 MK |
1043 | static u32 last_status = -1; |
1044 | const u32 status = I915_READ(ch_ctl); | |
1045 | ||
1046 | if (status != last_status) { | |
1047 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
1048 | status); | |
1049 | last_status = status; | |
1050 | } | |
1051 | ||
9ee32fea DV |
1052 | ret = -EBUSY; |
1053 | goto out; | |
4f7f7b7e CW |
1054 | } |
1055 | ||
46a5ae9f PZ |
1056 | /* Only 5 data registers! */ |
1057 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
1058 | ret = -E2BIG; | |
1059 | goto out; | |
1060 | } | |
1061 | ||
ec5b01dd | 1062 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
153b1100 DL |
1063 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
1064 | has_aux_irq, | |
1065 | send_bytes, | |
1066 | aux_clock_divider); | |
5ed12a19 | 1067 | |
bc86625a CW |
1068 | /* Must try at least 3 times according to DP spec */ |
1069 | for (try = 0; try < 5; try++) { | |
1070 | /* Load the send data into the aux channel data registers */ | |
1071 | for (i = 0; i < send_bytes; i += 4) | |
330e20ec | 1072 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
a4f1289e RV |
1073 | intel_dp_pack_aux(send + i, |
1074 | send_bytes - i)); | |
bc86625a CW |
1075 | |
1076 | /* Send the command and wait for it to complete */ | |
5ed12a19 | 1077 | I915_WRITE(ch_ctl, send_ctl); |
bc86625a CW |
1078 | |
1079 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
1080 | ||
1081 | /* Clear done status and any errors */ | |
1082 | I915_WRITE(ch_ctl, | |
1083 | status | | |
1084 | DP_AUX_CH_CTL_DONE | | |
1085 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
1086 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
1087 | ||
74ebf294 | 1088 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
bc86625a | 1089 | continue; |
74ebf294 TP |
1090 | |
1091 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 | |
1092 | * 400us delay required for errors and timeouts | |
1093 | * Timeout errors from the HW already meet this | |
1094 | * requirement so skip to next iteration | |
1095 | */ | |
1096 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { | |
1097 | usleep_range(400, 500); | |
bc86625a | 1098 | continue; |
74ebf294 | 1099 | } |
bc86625a | 1100 | if (status & DP_AUX_CH_CTL_DONE) |
e058c945 | 1101 | goto done; |
bc86625a | 1102 | } |
a4fc5ed6 KP |
1103 | } |
1104 | ||
a4fc5ed6 | 1105 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 1106 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
1107 | ret = -EBUSY; |
1108 | goto out; | |
a4fc5ed6 KP |
1109 | } |
1110 | ||
e058c945 | 1111 | done: |
a4fc5ed6 KP |
1112 | /* Check for timeout or receive error. |
1113 | * Timeouts occur when the sink is not connected | |
1114 | */ | |
a5b3da54 | 1115 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 1116 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
1117 | ret = -EIO; |
1118 | goto out; | |
a5b3da54 | 1119 | } |
1ae8c0a5 KP |
1120 | |
1121 | /* Timeouts occur when the device isn't connected, so they're | |
1122 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 1123 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 1124 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
1125 | ret = -ETIMEDOUT; |
1126 | goto out; | |
a4fc5ed6 KP |
1127 | } |
1128 | ||
1129 | /* Unload any bytes sent back from the other side */ | |
1130 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
1131 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
14e01889 RV |
1132 | |
1133 | /* | |
1134 | * By BSpec: "Message sizes of 0 or >20 are not allowed." | |
1135 | * We have no idea of what happened so we return -EBUSY so | |
1136 | * drm layer takes care for the necessary retries. | |
1137 | */ | |
1138 | if (recv_bytes == 0 || recv_bytes > 20) { | |
1139 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", | |
1140 | recv_bytes); | |
1141 | /* | |
1142 | * FIXME: This patch was created on top of a series that | |
1143 | * organize the retries at drm level. There EBUSY should | |
1144 | * also take care for 1ms wait before retrying. | |
1145 | * That aux retries re-org is still needed and after that is | |
1146 | * merged we remove this sleep from here. | |
1147 | */ | |
1148 | usleep_range(1000, 1500); | |
1149 | ret = -EBUSY; | |
1150 | goto out; | |
1151 | } | |
1152 | ||
a4fc5ed6 KP |
1153 | if (recv_bytes > recv_size) |
1154 | recv_bytes = recv_size; | |
0206e353 | 1155 | |
4f7f7b7e | 1156 | for (i = 0; i < recv_bytes; i += 4) |
330e20ec | 1157 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
a4f1289e | 1158 | recv + i, recv_bytes - i); |
a4fc5ed6 | 1159 | |
9ee32fea DV |
1160 | ret = recv_bytes; |
1161 | out: | |
1162 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
1163 | ||
884f19e9 JN |
1164 | if (vdd) |
1165 | edp_panel_vdd_off(intel_dp, false); | |
1166 | ||
773538e8 | 1167 | pps_unlock(intel_dp); |
e39b999a | 1168 | |
9ee32fea | 1169 | return ret; |
a4fc5ed6 KP |
1170 | } |
1171 | ||
a6c8aff0 JN |
1172 | #define BARE_ADDRESS_SIZE 3 |
1173 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
9d1a1031 JN |
1174 | static ssize_t |
1175 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 1176 | { |
9d1a1031 JN |
1177 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
1178 | uint8_t txbuf[20], rxbuf[20]; | |
1179 | size_t txsize, rxsize; | |
a4fc5ed6 | 1180 | int ret; |
a4fc5ed6 | 1181 | |
d2d9cbbd VS |
1182 | txbuf[0] = (msg->request << 4) | |
1183 | ((msg->address >> 16) & 0xf); | |
1184 | txbuf[1] = (msg->address >> 8) & 0xff; | |
9d1a1031 JN |
1185 | txbuf[2] = msg->address & 0xff; |
1186 | txbuf[3] = msg->size - 1; | |
46a5ae9f | 1187 | |
9d1a1031 JN |
1188 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
1189 | case DP_AUX_NATIVE_WRITE: | |
1190 | case DP_AUX_I2C_WRITE: | |
c1e74122 | 1191 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
a6c8aff0 | 1192 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
a1ddefd8 | 1193 | rxsize = 2; /* 0 or 1 data bytes */ |
f51a44b9 | 1194 | |
9d1a1031 JN |
1195 | if (WARN_ON(txsize > 20)) |
1196 | return -E2BIG; | |
a4fc5ed6 | 1197 | |
dd788090 VS |
1198 | WARN_ON(!msg->buffer != !msg->size); |
1199 | ||
d81a67cc ID |
1200 | if (msg->buffer) |
1201 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); | |
a4fc5ed6 | 1202 | |
9d1a1031 JN |
1203 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1204 | if (ret > 0) { | |
1205 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 1206 | |
a1ddefd8 JN |
1207 | if (ret > 1) { |
1208 | /* Number of bytes written in a short write. */ | |
1209 | ret = clamp_t(int, rxbuf[1], 0, msg->size); | |
1210 | } else { | |
1211 | /* Return payload size. */ | |
1212 | ret = msg->size; | |
1213 | } | |
9d1a1031 JN |
1214 | } |
1215 | break; | |
46a5ae9f | 1216 | |
9d1a1031 JN |
1217 | case DP_AUX_NATIVE_READ: |
1218 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 1219 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 1220 | rxsize = msg->size + 1; |
a4fc5ed6 | 1221 | |
9d1a1031 JN |
1222 | if (WARN_ON(rxsize > 20)) |
1223 | return -E2BIG; | |
a4fc5ed6 | 1224 | |
9d1a1031 JN |
1225 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1226 | if (ret > 0) { | |
1227 | msg->reply = rxbuf[0] >> 4; | |
1228 | /* | |
1229 | * Assume happy day, and copy the data. The caller is | |
1230 | * expected to check msg->reply before touching it. | |
1231 | * | |
1232 | * Return payload size. | |
1233 | */ | |
1234 | ret--; | |
1235 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 1236 | } |
9d1a1031 JN |
1237 | break; |
1238 | ||
1239 | default: | |
1240 | ret = -EINVAL; | |
1241 | break; | |
a4fc5ed6 | 1242 | } |
f51a44b9 | 1243 | |
9d1a1031 | 1244 | return ret; |
a4fc5ed6 KP |
1245 | } |
1246 | ||
8f7ce038 VS |
1247 | static enum port intel_aux_port(struct drm_i915_private *dev_priv, |
1248 | enum port port) | |
1249 | { | |
1250 | const struct ddi_vbt_port_info *info = | |
1251 | &dev_priv->vbt.ddi_port_info[port]; | |
1252 | enum port aux_port; | |
1253 | ||
1254 | if (!info->alternate_aux_channel) { | |
1255 | DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n", | |
1256 | port_name(port), port_name(port)); | |
1257 | return port; | |
1258 | } | |
1259 | ||
1260 | switch (info->alternate_aux_channel) { | |
1261 | case DP_AUX_A: | |
1262 | aux_port = PORT_A; | |
1263 | break; | |
1264 | case DP_AUX_B: | |
1265 | aux_port = PORT_B; | |
1266 | break; | |
1267 | case DP_AUX_C: | |
1268 | aux_port = PORT_C; | |
1269 | break; | |
1270 | case DP_AUX_D: | |
1271 | aux_port = PORT_D; | |
1272 | break; | |
1273 | default: | |
1274 | MISSING_CASE(info->alternate_aux_channel); | |
1275 | aux_port = PORT_A; | |
1276 | break; | |
1277 | } | |
1278 | ||
1279 | DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n", | |
1280 | port_name(aux_port), port_name(port)); | |
1281 | ||
1282 | return aux_port; | |
1283 | } | |
1284 | ||
f0f59a00 | 1285 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1286 | enum port port) |
da00bdcf VS |
1287 | { |
1288 | switch (port) { | |
1289 | case PORT_B: | |
1290 | case PORT_C: | |
1291 | case PORT_D: | |
1292 | return DP_AUX_CH_CTL(port); | |
1293 | default: | |
1294 | MISSING_CASE(port); | |
1295 | return DP_AUX_CH_CTL(PORT_B); | |
1296 | } | |
1297 | } | |
1298 | ||
f0f59a00 | 1299 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1300 | enum port port, int index) |
330e20ec VS |
1301 | { |
1302 | switch (port) { | |
1303 | case PORT_B: | |
1304 | case PORT_C: | |
1305 | case PORT_D: | |
1306 | return DP_AUX_CH_DATA(port, index); | |
1307 | default: | |
1308 | MISSING_CASE(port); | |
1309 | return DP_AUX_CH_DATA(PORT_B, index); | |
1310 | } | |
1311 | } | |
1312 | ||
f0f59a00 | 1313 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1314 | enum port port) |
da00bdcf VS |
1315 | { |
1316 | switch (port) { | |
1317 | case PORT_A: | |
1318 | return DP_AUX_CH_CTL(port); | |
1319 | case PORT_B: | |
1320 | case PORT_C: | |
1321 | case PORT_D: | |
1322 | return PCH_DP_AUX_CH_CTL(port); | |
1323 | default: | |
1324 | MISSING_CASE(port); | |
1325 | return DP_AUX_CH_CTL(PORT_A); | |
1326 | } | |
1327 | } | |
1328 | ||
f0f59a00 | 1329 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1330 | enum port port, int index) |
330e20ec VS |
1331 | { |
1332 | switch (port) { | |
1333 | case PORT_A: | |
1334 | return DP_AUX_CH_DATA(port, index); | |
1335 | case PORT_B: | |
1336 | case PORT_C: | |
1337 | case PORT_D: | |
1338 | return PCH_DP_AUX_CH_DATA(port, index); | |
1339 | default: | |
1340 | MISSING_CASE(port); | |
1341 | return DP_AUX_CH_DATA(PORT_A, index); | |
1342 | } | |
1343 | } | |
1344 | ||
f0f59a00 | 1345 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1346 | enum port port) |
da00bdcf | 1347 | { |
da00bdcf VS |
1348 | switch (port) { |
1349 | case PORT_A: | |
1350 | case PORT_B: | |
1351 | case PORT_C: | |
1352 | case PORT_D: | |
1353 | return DP_AUX_CH_CTL(port); | |
1354 | default: | |
1355 | MISSING_CASE(port); | |
1356 | return DP_AUX_CH_CTL(PORT_A); | |
1357 | } | |
1358 | } | |
1359 | ||
f0f59a00 | 1360 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1361 | enum port port, int index) |
330e20ec | 1362 | { |
330e20ec VS |
1363 | switch (port) { |
1364 | case PORT_A: | |
1365 | case PORT_B: | |
1366 | case PORT_C: | |
1367 | case PORT_D: | |
1368 | return DP_AUX_CH_DATA(port, index); | |
1369 | default: | |
1370 | MISSING_CASE(port); | |
1371 | return DP_AUX_CH_DATA(PORT_A, index); | |
1372 | } | |
1373 | } | |
1374 | ||
f0f59a00 | 1375 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1376 | enum port port) |
330e20ec VS |
1377 | { |
1378 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1379 | return skl_aux_ctl_reg(dev_priv, port); | |
1380 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1381 | return ilk_aux_ctl_reg(dev_priv, port); | |
1382 | else | |
1383 | return g4x_aux_ctl_reg(dev_priv, port); | |
1384 | } | |
1385 | ||
f0f59a00 | 1386 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1387 | enum port port, int index) |
330e20ec VS |
1388 | { |
1389 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1390 | return skl_aux_data_reg(dev_priv, port, index); | |
1391 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1392 | return ilk_aux_data_reg(dev_priv, port, index); | |
1393 | else | |
1394 | return g4x_aux_data_reg(dev_priv, port, index); | |
1395 | } | |
1396 | ||
1397 | static void intel_aux_reg_init(struct intel_dp *intel_dp) | |
1398 | { | |
1399 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); | |
8f7ce038 VS |
1400 | enum port port = intel_aux_port(dev_priv, |
1401 | dp_to_dig_port(intel_dp)->port); | |
330e20ec VS |
1402 | int i; |
1403 | ||
1404 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); | |
1405 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) | |
1406 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); | |
1407 | } | |
1408 | ||
9d1a1031 | 1409 | static void |
a121f4e5 VS |
1410 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
1411 | { | |
a121f4e5 VS |
1412 | kfree(intel_dp->aux.name); |
1413 | } | |
1414 | ||
7a418e34 | 1415 | static void |
b6339585 | 1416 | intel_dp_aux_init(struct intel_dp *intel_dp) |
9d1a1031 | 1417 | { |
33ad6626 JN |
1418 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1419 | enum port port = intel_dig_port->port; | |
ab2c0672 | 1420 | |
330e20ec | 1421 | intel_aux_reg_init(intel_dp); |
7a418e34 | 1422 | drm_dp_aux_init(&intel_dp->aux); |
8316f337 | 1423 | |
7a418e34 | 1424 | /* Failure to allocate our preferred name is not critical */ |
a121f4e5 | 1425 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
9d1a1031 | 1426 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
a4fc5ed6 KP |
1427 | } |
1428 | ||
e588fa18 | 1429 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
ed63baaf | 1430 | { |
e588fa18 | 1431 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
577c5430 | 1432 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
e588fa18 | 1433 | |
577c5430 NM |
1434 | if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || |
1435 | IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9)) | |
ed63baaf TS |
1436 | return true; |
1437 | else | |
1438 | return false; | |
1439 | } | |
1440 | ||
c6bb3538 DV |
1441 | static void |
1442 | intel_dp_set_clock(struct intel_encoder *encoder, | |
840b32b7 | 1443 | struct intel_crtc_state *pipe_config) |
c6bb3538 DV |
1444 | { |
1445 | struct drm_device *dev = encoder->base.dev; | |
6e266956 | 1446 | struct drm_i915_private *dev_priv = to_i915(dev); |
9dd4ffdf CML |
1447 | const struct dp_link_dpll *divisor = NULL; |
1448 | int i, count = 0; | |
c6bb3538 | 1449 | |
9beb5fea | 1450 | if (IS_G4X(dev_priv)) { |
9dd4ffdf CML |
1451 | divisor = gen4_dpll; |
1452 | count = ARRAY_SIZE(gen4_dpll); | |
6e266956 | 1453 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
9dd4ffdf CML |
1454 | divisor = pch_dpll; |
1455 | count = ARRAY_SIZE(pch_dpll); | |
920a14b2 | 1456 | } else if (IS_CHERRYVIEW(dev_priv)) { |
ef9348c8 CML |
1457 | divisor = chv_dpll; |
1458 | count = ARRAY_SIZE(chv_dpll); | |
11a914c2 | 1459 | } else if (IS_VALLEYVIEW(dev_priv)) { |
65ce4bf5 CML |
1460 | divisor = vlv_dpll; |
1461 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 1462 | } |
9dd4ffdf CML |
1463 | |
1464 | if (divisor && count) { | |
1465 | for (i = 0; i < count; i++) { | |
840b32b7 | 1466 | if (pipe_config->port_clock == divisor[i].clock) { |
9dd4ffdf CML |
1467 | pipe_config->dpll = divisor[i].dpll; |
1468 | pipe_config->clock_set = true; | |
1469 | break; | |
1470 | } | |
1471 | } | |
c6bb3538 DV |
1472 | } |
1473 | } | |
1474 | ||
0336400e VS |
1475 | static void snprintf_int_array(char *str, size_t len, |
1476 | const int *array, int nelem) | |
1477 | { | |
1478 | int i; | |
1479 | ||
1480 | str[0] = '\0'; | |
1481 | ||
1482 | for (i = 0; i < nelem; i++) { | |
b2f505be | 1483 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
0336400e VS |
1484 | if (r >= len) |
1485 | return; | |
1486 | str += r; | |
1487 | len -= r; | |
1488 | } | |
1489 | } | |
1490 | ||
1491 | static void intel_dp_print_rates(struct intel_dp *intel_dp) | |
1492 | { | |
0336400e | 1493 | const int *source_rates, *sink_rates; |
94ca719e VS |
1494 | int source_len, sink_len, common_len; |
1495 | int common_rates[DP_MAX_SUPPORTED_RATES]; | |
0336400e VS |
1496 | char str[128]; /* FIXME: too big for stack? */ |
1497 | ||
1498 | if ((drm_debug & DRM_UT_KMS) == 0) | |
1499 | return; | |
1500 | ||
e588fa18 | 1501 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
0336400e VS |
1502 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
1503 | DRM_DEBUG_KMS("source rates: %s\n", str); | |
1504 | ||
1505 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); | |
1506 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); | |
1507 | DRM_DEBUG_KMS("sink rates: %s\n", str); | |
1508 | ||
94ca719e VS |
1509 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1510 | snprintf_int_array(str, sizeof(str), common_rates, common_len); | |
1511 | DRM_DEBUG_KMS("common rates: %s\n", str); | |
0336400e VS |
1512 | } |
1513 | ||
489375c8 | 1514 | bool |
7b3fc170 | 1515 | __intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc) |
0e390a33 | 1516 | { |
7b3fc170 ID |
1517 | u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI : |
1518 | DP_SINK_OUI; | |
0e390a33 | 1519 | |
7b3fc170 ID |
1520 | return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) == |
1521 | sizeof(*desc); | |
0e390a33 MK |
1522 | } |
1523 | ||
12a47a42 | 1524 | bool intel_dp_read_desc(struct intel_dp *intel_dp) |
1a2724fa | 1525 | { |
7b3fc170 ID |
1526 | struct intel_dp_desc *desc = &intel_dp->desc; |
1527 | bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & | |
1528 | DP_OUI_SUPPORT; | |
1529 | int dev_id_len; | |
1a2724fa | 1530 | |
7b3fc170 ID |
1531 | if (!__intel_dp_read_desc(intel_dp, desc)) |
1532 | return false; | |
1a2724fa | 1533 | |
7b3fc170 ID |
1534 | dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id)); |
1535 | DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n", | |
1536 | drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink", | |
1537 | (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)", | |
1538 | dev_id_len, desc->device_id, | |
1539 | desc->hw_rev >> 4, desc->hw_rev & 0xf, | |
1540 | desc->sw_major_rev, desc->sw_minor_rev); | |
1a2724fa | 1541 | |
7b3fc170 | 1542 | return true; |
1a2724fa MK |
1543 | } |
1544 | ||
f4896f15 | 1545 | static int rate_to_index(int find, const int *rates) |
a8f3ef61 SJ |
1546 | { |
1547 | int i = 0; | |
1548 | ||
1549 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) | |
1550 | if (find == rates[i]) | |
1551 | break; | |
1552 | ||
1553 | return i; | |
1554 | } | |
1555 | ||
50fec21a VS |
1556 | int |
1557 | intel_dp_max_link_rate(struct intel_dp *intel_dp) | |
1558 | { | |
1559 | int rates[DP_MAX_SUPPORTED_RATES] = {}; | |
1560 | int len; | |
1561 | ||
94ca719e | 1562 | len = intel_dp_common_rates(intel_dp, rates); |
50fec21a VS |
1563 | if (WARN_ON(len <= 0)) |
1564 | return 162000; | |
1565 | ||
1354f734 | 1566 | return rates[len - 1]; |
50fec21a VS |
1567 | } |
1568 | ||
ed4e9c1d VS |
1569 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1570 | { | |
94ca719e | 1571 | return rate_to_index(rate, intel_dp->sink_rates); |
ed4e9c1d VS |
1572 | } |
1573 | ||
94223d04 ACO |
1574 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1575 | uint8_t *link_bw, uint8_t *rate_select) | |
04a60f9f VS |
1576 | { |
1577 | if (intel_dp->num_sink_rates) { | |
1578 | *link_bw = 0; | |
1579 | *rate_select = | |
1580 | intel_dp_rate_select(intel_dp, port_clock); | |
1581 | } else { | |
1582 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); | |
1583 | *rate_select = 0; | |
1584 | } | |
1585 | } | |
1586 | ||
f580bea9 JN |
1587 | static int intel_dp_compute_bpp(struct intel_dp *intel_dp, |
1588 | struct intel_crtc_state *pipe_config) | |
f9bb705e MK |
1589 | { |
1590 | int bpp, bpc; | |
1591 | ||
1592 | bpp = pipe_config->pipe_bpp; | |
1593 | bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports); | |
1594 | ||
1595 | if (bpc > 0) | |
1596 | bpp = min(bpp, 3*bpc); | |
1597 | ||
611032bf MN |
1598 | /* For DP Compliance we override the computed bpp for the pipe */ |
1599 | if (intel_dp->compliance.test_data.bpc != 0) { | |
1600 | pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc; | |
1601 | pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3; | |
1602 | DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", | |
1603 | pipe_config->pipe_bpp); | |
1604 | } | |
f9bb705e MK |
1605 | return bpp; |
1606 | } | |
1607 | ||
00c09d70 | 1608 | bool |
5bfe2ac0 | 1609 | intel_dp_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
1610 | struct intel_crtc_state *pipe_config, |
1611 | struct drm_connector_state *conn_state) | |
a4fc5ed6 | 1612 | { |
dd11bc10 | 1613 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2d112de7 | 1614 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
5bfe2ac0 | 1615 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1616 | enum port port = dp_to_dig_port(intel_dp)->port; |
84556d58 | 1617 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
dd06f90e | 1618 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
a4fc5ed6 | 1619 | int lane_count, clock; |
56071a20 | 1620 | int min_lane_count = 1; |
eeb6324d | 1621 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
06ea66b6 | 1622 | /* Conveniently, the link BW constants become indices with a shift...*/ |
56071a20 | 1623 | int min_clock = 0; |
a8f3ef61 | 1624 | int max_clock; |
da15f7cb | 1625 | int link_rate_index; |
083f9560 | 1626 | int bpp, mode_rate; |
ff9a6750 | 1627 | int link_avail, link_clock; |
94ca719e VS |
1628 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
1629 | int common_len; | |
04a60f9f | 1630 | uint8_t link_bw, rate_select; |
a8f3ef61 | 1631 | |
94ca719e | 1632 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
a8f3ef61 SJ |
1633 | |
1634 | /* No common link rates between source and sink */ | |
94ca719e | 1635 | WARN_ON(common_len <= 0); |
a8f3ef61 | 1636 | |
94ca719e | 1637 | max_clock = common_len - 1; |
a4fc5ed6 | 1638 | |
4f8036a2 | 1639 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) |
5bfe2ac0 DV |
1640 | pipe_config->has_pch_encoder = true; |
1641 | ||
f769cd24 | 1642 | pipe_config->has_drrs = false; |
9fcb1704 | 1643 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
a4fc5ed6 | 1644 | |
dd06f90e JN |
1645 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
1646 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
1647 | adjusted_mode); | |
a1b2278e | 1648 | |
dd11bc10 | 1649 | if (INTEL_GEN(dev_priv) >= 9) { |
a1b2278e | 1650 | int ret; |
e435d6e5 | 1651 | ret = skl_update_scaler_crtc(pipe_config); |
a1b2278e CK |
1652 | if (ret) |
1653 | return ret; | |
1654 | } | |
1655 | ||
49cff963 | 1656 | if (HAS_GMCH_DISPLAY(dev_priv)) |
2dd24552 JB |
1657 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
1658 | intel_connector->panel.fitting_mode); | |
1659 | else | |
b074cec8 JB |
1660 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
1661 | intel_connector->panel.fitting_mode); | |
0d3a1bee ZY |
1662 | } |
1663 | ||
cb1793ce | 1664 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
1665 | return false; |
1666 | ||
da15f7cb MN |
1667 | /* Use values requested by Compliance Test Request */ |
1668 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { | |
1669 | link_rate_index = intel_dp_link_rate_index(intel_dp, | |
1670 | common_rates, | |
1671 | intel_dp->compliance.test_link_rate); | |
1672 | if (link_rate_index >= 0) | |
1673 | min_clock = max_clock = link_rate_index; | |
1674 | min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count; | |
1675 | } | |
083f9560 | 1676 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
a8f3ef61 | 1677 | "max bw %d pixel clock %iKHz\n", |
94ca719e | 1678 | max_lane_count, common_rates[max_clock], |
241bfc38 | 1679 | adjusted_mode->crtc_clock); |
083f9560 | 1680 | |
36008365 DV |
1681 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1682 | * bpc in between. */ | |
f9bb705e | 1683 | bpp = intel_dp_compute_bpp(intel_dp, pipe_config); |
56071a20 | 1684 | if (is_edp(intel_dp)) { |
22ce5628 TS |
1685 | |
1686 | /* Get bpp from vbt only for panels that dont have bpp in edid */ | |
1687 | if (intel_connector->base.display_info.bpc == 0 && | |
6aa23e65 | 1688 | (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { |
56071a20 | 1689 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
6aa23e65 JN |
1690 | dev_priv->vbt.edp.bpp); |
1691 | bpp = dev_priv->vbt.edp.bpp; | |
56071a20 JN |
1692 | } |
1693 | ||
344c5bbc JN |
1694 | /* |
1695 | * Use the maximum clock and number of lanes the eDP panel | |
1696 | * advertizes being capable of. The panels are generally | |
1697 | * designed to support only a single clock and lane | |
1698 | * configuration, and typically these values correspond to the | |
1699 | * native resolution of the panel. | |
1700 | */ | |
1701 | min_lane_count = max_lane_count; | |
1702 | min_clock = max_clock; | |
7984211e | 1703 | } |
657445fe | 1704 | |
36008365 | 1705 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
1706 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1707 | bpp); | |
36008365 | 1708 | |
c6930992 | 1709 | for (clock = min_clock; clock <= max_clock; clock++) { |
a8f3ef61 SJ |
1710 | for (lane_count = min_lane_count; |
1711 | lane_count <= max_lane_count; | |
1712 | lane_count <<= 1) { | |
1713 | ||
94ca719e | 1714 | link_clock = common_rates[clock]; |
36008365 DV |
1715 | link_avail = intel_dp_max_data_rate(link_clock, |
1716 | lane_count); | |
1717 | ||
1718 | if (mode_rate <= link_avail) { | |
1719 | goto found; | |
1720 | } | |
1721 | } | |
1722 | } | |
1723 | } | |
c4867936 | 1724 | |
36008365 | 1725 | return false; |
3685a8f3 | 1726 | |
36008365 | 1727 | found: |
55bc60db VS |
1728 | if (intel_dp->color_range_auto) { |
1729 | /* | |
1730 | * See: | |
1731 | * CEA-861-E - 5.1 Default Encoding Parameters | |
1732 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
1733 | */ | |
0f2a2a75 | 1734 | pipe_config->limited_color_range = |
c8127cf0 VS |
1735 | bpp != 18 && |
1736 | drm_default_rgb_quant_range(adjusted_mode) == | |
1737 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
0f2a2a75 VS |
1738 | } else { |
1739 | pipe_config->limited_color_range = | |
1740 | intel_dp->limited_color_range; | |
55bc60db VS |
1741 | } |
1742 | ||
90a6b7b0 | 1743 | pipe_config->lane_count = lane_count; |
a8f3ef61 | 1744 | |
657445fe | 1745 | pipe_config->pipe_bpp = bpp; |
94ca719e | 1746 | pipe_config->port_clock = common_rates[clock]; |
a4fc5ed6 | 1747 | |
04a60f9f VS |
1748 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
1749 | &link_bw, &rate_select); | |
1750 | ||
1751 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", | |
1752 | link_bw, rate_select, pipe_config->lane_count, | |
ff9a6750 | 1753 | pipe_config->port_clock, bpp); |
36008365 DV |
1754 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1755 | mode_rate, link_avail); | |
a4fc5ed6 | 1756 | |
03afc4a2 | 1757 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
1758 | adjusted_mode->crtc_clock, |
1759 | pipe_config->port_clock, | |
03afc4a2 | 1760 | &pipe_config->dp_m_n); |
9d1a455b | 1761 | |
439d7ac0 | 1762 | if (intel_connector->panel.downclock_mode != NULL && |
96178eeb | 1763 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
f769cd24 | 1764 | pipe_config->has_drrs = true; |
439d7ac0 PB |
1765 | intel_link_compute_m_n(bpp, lane_count, |
1766 | intel_connector->panel.downclock_mode->clock, | |
1767 | pipe_config->port_clock, | |
1768 | &pipe_config->dp_m2_n2); | |
1769 | } | |
1770 | ||
14d41b3b VS |
1771 | /* |
1772 | * DPLL0 VCO may need to be adjusted to get the correct | |
1773 | * clock for eDP. This will affect cdclk as well. | |
1774 | */ | |
b976dc53 | 1775 | if (is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) { |
14d41b3b VS |
1776 | int vco; |
1777 | ||
1778 | switch (pipe_config->port_clock / 2) { | |
1779 | case 108000: | |
1780 | case 216000: | |
63911d72 | 1781 | vco = 8640000; |
14d41b3b VS |
1782 | break; |
1783 | default: | |
63911d72 | 1784 | vco = 8100000; |
14d41b3b VS |
1785 | break; |
1786 | } | |
1787 | ||
1788 | to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco; | |
1789 | } | |
1790 | ||
4f8036a2 | 1791 | if (!HAS_DDI(dev_priv)) |
840b32b7 | 1792 | intel_dp_set_clock(encoder, pipe_config); |
c6bb3538 | 1793 | |
03afc4a2 | 1794 | return true; |
a4fc5ed6 KP |
1795 | } |
1796 | ||
901c2daf | 1797 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
dfa10480 ACO |
1798 | int link_rate, uint8_t lane_count, |
1799 | bool link_mst) | |
901c2daf | 1800 | { |
dfa10480 ACO |
1801 | intel_dp->link_rate = link_rate; |
1802 | intel_dp->lane_count = lane_count; | |
1803 | intel_dp->link_mst = link_mst; | |
901c2daf VS |
1804 | } |
1805 | ||
85cb48a1 ML |
1806 | static void intel_dp_prepare(struct intel_encoder *encoder, |
1807 | struct intel_crtc_state *pipe_config) | |
a4fc5ed6 | 1808 | { |
b934223d | 1809 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1810 | struct drm_i915_private *dev_priv = to_i915(dev); |
b934223d | 1811 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1812 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d | 1813 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
85cb48a1 | 1814 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
a4fc5ed6 | 1815 | |
dfa10480 ACO |
1816 | intel_dp_set_link_params(intel_dp, pipe_config->port_clock, |
1817 | pipe_config->lane_count, | |
1818 | intel_crtc_has_type(pipe_config, | |
1819 | INTEL_OUTPUT_DP_MST)); | |
901c2daf | 1820 | |
417e822d | 1821 | /* |
1a2eb460 | 1822 | * There are four kinds of DP registers: |
417e822d KP |
1823 | * |
1824 | * IBX PCH | |
1a2eb460 KP |
1825 | * SNB CPU |
1826 | * IVB CPU | |
417e822d KP |
1827 | * CPT PCH |
1828 | * | |
1829 | * IBX PCH and CPU are the same for almost everything, | |
1830 | * except that the CPU DP PLL is configured in this | |
1831 | * register | |
1832 | * | |
1833 | * CPT PCH is quite different, having many bits moved | |
1834 | * to the TRANS_DP_CTL register instead. That | |
1835 | * configuration happens (oddly) in ironlake_pch_enable | |
1836 | */ | |
9c9e7927 | 1837 | |
417e822d KP |
1838 | /* Preserve the BIOS-computed detected bit. This is |
1839 | * supposed to be read-only. | |
1840 | */ | |
1841 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 1842 | |
417e822d | 1843 | /* Handle DP bits in common between all three register formats */ |
417e822d | 1844 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
85cb48a1 | 1845 | intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); |
a4fc5ed6 | 1846 | |
417e822d | 1847 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 1848 | |
5db94019 | 1849 | if (IS_GEN7(dev_priv) && port == PORT_A) { |
1a2eb460 KP |
1850 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1851 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1852 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1853 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1854 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
1855 | ||
6aba5b6c | 1856 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
1857 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1858 | ||
7c62a164 | 1859 | intel_dp->DP |= crtc->pipe << 29; |
6e266956 | 1860 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
e3ef4479 VS |
1861 | u32 trans_dp; |
1862 | ||
39e5fa88 | 1863 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3ef4479 VS |
1864 | |
1865 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
1866 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
1867 | trans_dp |= TRANS_DP_ENH_FRAMING; | |
1868 | else | |
1869 | trans_dp &= ~TRANS_DP_ENH_FRAMING; | |
1870 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); | |
39e5fa88 | 1871 | } else { |
c99f53f7 | 1872 | if (IS_G4X(dev_priv) && pipe_config->limited_color_range) |
0f2a2a75 | 1873 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
417e822d KP |
1874 | |
1875 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
1876 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1877 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1878 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1879 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
1880 | ||
6aba5b6c | 1881 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
1882 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1883 | ||
920a14b2 | 1884 | if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 1885 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
39e5fa88 VS |
1886 | else if (crtc->pipe == PIPE_B) |
1887 | intel_dp->DP |= DP_PIPEB_SELECT; | |
32f9d658 | 1888 | } |
a4fc5ed6 KP |
1889 | } |
1890 | ||
ffd6749d PZ |
1891 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1892 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 1893 | |
1a5ef5b7 PZ |
1894 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1895 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 1896 | |
ffd6749d PZ |
1897 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1898 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 1899 | |
de9c1b6b ID |
1900 | static void intel_pps_verify_state(struct drm_i915_private *dev_priv, |
1901 | struct intel_dp *intel_dp); | |
1902 | ||
4be73780 | 1903 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
1904 | u32 mask, |
1905 | u32 value) | |
bd943159 | 1906 | { |
30add22d | 1907 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 1908 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1909 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
453c5420 | 1910 | |
e39b999a VS |
1911 | lockdep_assert_held(&dev_priv->pps_mutex); |
1912 | ||
de9c1b6b ID |
1913 | intel_pps_verify_state(dev_priv, intel_dp); |
1914 | ||
bf13e81b JN |
1915 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1916 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 1917 | |
99ea7127 | 1918 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
1919 | mask, value, |
1920 | I915_READ(pp_stat_reg), | |
1921 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1922 | |
9036ff06 CW |
1923 | if (intel_wait_for_register(dev_priv, |
1924 | pp_stat_reg, mask, value, | |
1925 | 5000)) | |
99ea7127 | 1926 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
1927 | I915_READ(pp_stat_reg), |
1928 | I915_READ(pp_ctrl_reg)); | |
54c136d4 CW |
1929 | |
1930 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 1931 | } |
32ce697c | 1932 | |
4be73780 | 1933 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
1934 | { |
1935 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 1936 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
1937 | } |
1938 | ||
4be73780 | 1939 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
1940 | { |
1941 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 1942 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
1943 | } |
1944 | ||
4be73780 | 1945 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 | 1946 | { |
d28d4731 AK |
1947 | ktime_t panel_power_on_time; |
1948 | s64 panel_power_off_duration; | |
1949 | ||
99ea7127 | 1950 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
dce56b3c | 1951 | |
d28d4731 AK |
1952 | /* take the difference of currrent time and panel power off time |
1953 | * and then make panel wait for t11_t12 if needed. */ | |
1954 | panel_power_on_time = ktime_get_boottime(); | |
1955 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); | |
1956 | ||
dce56b3c PZ |
1957 | /* When we disable the VDD override bit last we have to do the manual |
1958 | * wait. */ | |
d28d4731 AK |
1959 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
1960 | wait_remaining_ms_from_jiffies(jiffies, | |
1961 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); | |
dce56b3c | 1962 | |
4be73780 | 1963 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
1964 | } |
1965 | ||
4be73780 | 1966 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
1967 | { |
1968 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
1969 | intel_dp->backlight_on_delay); | |
1970 | } | |
1971 | ||
4be73780 | 1972 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
1973 | { |
1974 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
1975 | intel_dp->backlight_off_delay); | |
1976 | } | |
99ea7127 | 1977 | |
832dd3c1 KP |
1978 | /* Read the current pp_control value, unlocking the register if it |
1979 | * is locked | |
1980 | */ | |
1981 | ||
453c5420 | 1982 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 1983 | { |
453c5420 | 1984 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 1985 | struct drm_i915_private *dev_priv = to_i915(dev); |
453c5420 | 1986 | u32 control; |
832dd3c1 | 1987 | |
e39b999a VS |
1988 | lockdep_assert_held(&dev_priv->pps_mutex); |
1989 | ||
bf13e81b | 1990 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
8090ba8c ID |
1991 | if (WARN_ON(!HAS_DDI(dev_priv) && |
1992 | (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { | |
b0a08bec VK |
1993 | control &= ~PANEL_UNLOCK_MASK; |
1994 | control |= PANEL_UNLOCK_REGS; | |
1995 | } | |
832dd3c1 | 1996 | return control; |
bd943159 KP |
1997 | } |
1998 | ||
951468f3 VS |
1999 | /* |
2000 | * Must be paired with edp_panel_vdd_off(). | |
2001 | * Must hold pps_mutex around the whole on/off sequence. | |
2002 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2003 | */ | |
1e0560e0 | 2004 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 2005 | { |
30add22d | 2006 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4e6e1a54 ID |
2007 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2008 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fac5e23e | 2009 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e6e1a54 | 2010 | enum intel_display_power_domain power_domain; |
5d613501 | 2011 | u32 pp; |
f0f59a00 | 2012 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 2013 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 2014 | |
e39b999a VS |
2015 | lockdep_assert_held(&dev_priv->pps_mutex); |
2016 | ||
97af61f5 | 2017 | if (!is_edp(intel_dp)) |
adddaaf4 | 2018 | return false; |
bd943159 | 2019 | |
2c623c11 | 2020 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
bd943159 | 2021 | intel_dp->want_panel_vdd = true; |
99ea7127 | 2022 | |
4be73780 | 2023 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 2024 | return need_to_disable; |
b0665d57 | 2025 | |
25f78f58 | 2026 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4e6e1a54 | 2027 | intel_display_power_get(dev_priv, power_domain); |
e9cb81a2 | 2028 | |
3936fcf4 VS |
2029 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
2030 | port_name(intel_dig_port->port)); | |
bd943159 | 2031 | |
4be73780 DV |
2032 | if (!edp_have_panel_power(intel_dp)) |
2033 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 2034 | |
453c5420 | 2035 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 2036 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 2037 | |
bf13e81b JN |
2038 | pp_stat_reg = _pp_stat_reg(intel_dp); |
2039 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
2040 | |
2041 | I915_WRITE(pp_ctrl_reg, pp); | |
2042 | POSTING_READ(pp_ctrl_reg); | |
2043 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
2044 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
2045 | /* |
2046 | * If the panel wasn't on, delay before accessing aux channel | |
2047 | */ | |
4be73780 | 2048 | if (!edp_have_panel_power(intel_dp)) { |
3936fcf4 VS |
2049 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
2050 | port_name(intel_dig_port->port)); | |
f01eca2e | 2051 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 2052 | } |
adddaaf4 JN |
2053 | |
2054 | return need_to_disable; | |
2055 | } | |
2056 | ||
951468f3 VS |
2057 | /* |
2058 | * Must be paired with intel_edp_panel_vdd_off() or | |
2059 | * intel_edp_panel_off(). | |
2060 | * Nested calls to these functions are not allowed since | |
2061 | * we drop the lock. Caller must use some higher level | |
2062 | * locking to prevent nested calls from other threads. | |
2063 | */ | |
b80d6c78 | 2064 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 | 2065 | { |
c695b6b6 | 2066 | bool vdd; |
adddaaf4 | 2067 | |
c695b6b6 VS |
2068 | if (!is_edp(intel_dp)) |
2069 | return; | |
2070 | ||
773538e8 | 2071 | pps_lock(intel_dp); |
c695b6b6 | 2072 | vdd = edp_panel_vdd_on(intel_dp); |
773538e8 | 2073 | pps_unlock(intel_dp); |
c695b6b6 | 2074 | |
e2c719b7 | 2075 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
3936fcf4 | 2076 | port_name(dp_to_dig_port(intel_dp)->port)); |
5d613501 JB |
2077 | } |
2078 | ||
4be73780 | 2079 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 2080 | { |
30add22d | 2081 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2082 | struct drm_i915_private *dev_priv = to_i915(dev); |
be2c9196 VS |
2083 | struct intel_digital_port *intel_dig_port = |
2084 | dp_to_dig_port(intel_dp); | |
2085 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
2086 | enum intel_display_power_domain power_domain; | |
5d613501 | 2087 | u32 pp; |
f0f59a00 | 2088 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
5d613501 | 2089 | |
e39b999a | 2090 | lockdep_assert_held(&dev_priv->pps_mutex); |
a0e99e68 | 2091 | |
15e899a0 | 2092 | WARN_ON(intel_dp->want_panel_vdd); |
4e6e1a54 | 2093 | |
15e899a0 | 2094 | if (!edp_have_panel_vdd(intel_dp)) |
be2c9196 | 2095 | return; |
b0665d57 | 2096 | |
3936fcf4 VS |
2097 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
2098 | port_name(intel_dig_port->port)); | |
bd943159 | 2099 | |
be2c9196 VS |
2100 | pp = ironlake_get_pp_control(intel_dp); |
2101 | pp &= ~EDP_FORCE_VDD; | |
453c5420 | 2102 | |
be2c9196 VS |
2103 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2104 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
99ea7127 | 2105 | |
be2c9196 VS |
2106 | I915_WRITE(pp_ctrl_reg, pp); |
2107 | POSTING_READ(pp_ctrl_reg); | |
90791a5c | 2108 | |
be2c9196 VS |
2109 | /* Make sure sequencer is idle before allowing subsequent activity */ |
2110 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
2111 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
e9cb81a2 | 2112 | |
5a162e22 | 2113 | if ((pp & PANEL_POWER_ON) == 0) |
d28d4731 | 2114 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
e9cb81a2 | 2115 | |
25f78f58 | 2116 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
be2c9196 | 2117 | intel_display_power_put(dev_priv, power_domain); |
bd943159 | 2118 | } |
5d613501 | 2119 | |
4be73780 | 2120 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
2121 | { |
2122 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
2123 | struct intel_dp, panel_vdd_work); | |
bd943159 | 2124 | |
773538e8 | 2125 | pps_lock(intel_dp); |
15e899a0 VS |
2126 | if (!intel_dp->want_panel_vdd) |
2127 | edp_panel_vdd_off_sync(intel_dp); | |
773538e8 | 2128 | pps_unlock(intel_dp); |
bd943159 KP |
2129 | } |
2130 | ||
aba86890 ID |
2131 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
2132 | { | |
2133 | unsigned long delay; | |
2134 | ||
2135 | /* | |
2136 | * Queue the timer to fire a long time from now (relative to the power | |
2137 | * down delay) to keep the panel power up across a sequence of | |
2138 | * operations. | |
2139 | */ | |
2140 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); | |
2141 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); | |
2142 | } | |
2143 | ||
951468f3 VS |
2144 | /* |
2145 | * Must be paired with edp_panel_vdd_on(). | |
2146 | * Must hold pps_mutex around the whole on/off sequence. | |
2147 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2148 | */ | |
4be73780 | 2149 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 2150 | { |
fac5e23e | 2151 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
e39b999a VS |
2152 | |
2153 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2154 | ||
97af61f5 KP |
2155 | if (!is_edp(intel_dp)) |
2156 | return; | |
5d613501 | 2157 | |
e2c719b7 | 2158 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
3936fcf4 | 2159 | port_name(dp_to_dig_port(intel_dp)->port)); |
f2e8b18a | 2160 | |
bd943159 KP |
2161 | intel_dp->want_panel_vdd = false; |
2162 | ||
aba86890 | 2163 | if (sync) |
4be73780 | 2164 | edp_panel_vdd_off_sync(intel_dp); |
aba86890 ID |
2165 | else |
2166 | edp_panel_vdd_schedule_off(intel_dp); | |
5d613501 JB |
2167 | } |
2168 | ||
9f0fb5be | 2169 | static void edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 2170 | { |
30add22d | 2171 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2172 | struct drm_i915_private *dev_priv = to_i915(dev); |
99ea7127 | 2173 | u32 pp; |
f0f59a00 | 2174 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2175 | |
9f0fb5be VS |
2176 | lockdep_assert_held(&dev_priv->pps_mutex); |
2177 | ||
97af61f5 | 2178 | if (!is_edp(intel_dp)) |
bd943159 | 2179 | return; |
99ea7127 | 2180 | |
3936fcf4 VS |
2181 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
2182 | port_name(dp_to_dig_port(intel_dp)->port)); | |
e39b999a | 2183 | |
e7a89ace VS |
2184 | if (WARN(edp_have_panel_power(intel_dp), |
2185 | "eDP port %c panel power already on\n", | |
2186 | port_name(dp_to_dig_port(intel_dp)->port))) | |
9f0fb5be | 2187 | return; |
9934c132 | 2188 | |
4be73780 | 2189 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 2190 | |
bf13e81b | 2191 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2192 | pp = ironlake_get_pp_control(intel_dp); |
5db94019 | 2193 | if (IS_GEN5(dev_priv)) { |
05ce1a49 KP |
2194 | /* ILK workaround: disable reset around power sequence */ |
2195 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
2196 | I915_WRITE(pp_ctrl_reg, pp); |
2197 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2198 | } |
37c6c9b0 | 2199 | |
5a162e22 | 2200 | pp |= PANEL_POWER_ON; |
5db94019 | 2201 | if (!IS_GEN5(dev_priv)) |
99ea7127 KP |
2202 | pp |= PANEL_POWER_RESET; |
2203 | ||
453c5420 JB |
2204 | I915_WRITE(pp_ctrl_reg, pp); |
2205 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2206 | |
4be73780 | 2207 | wait_panel_on(intel_dp); |
dce56b3c | 2208 | intel_dp->last_power_on = jiffies; |
9934c132 | 2209 | |
5db94019 | 2210 | if (IS_GEN5(dev_priv)) { |
05ce1a49 | 2211 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
bf13e81b JN |
2212 | I915_WRITE(pp_ctrl_reg, pp); |
2213 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2214 | } |
9f0fb5be | 2215 | } |
e39b999a | 2216 | |
9f0fb5be VS |
2217 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
2218 | { | |
2219 | if (!is_edp(intel_dp)) | |
2220 | return; | |
2221 | ||
2222 | pps_lock(intel_dp); | |
2223 | edp_panel_on(intel_dp); | |
773538e8 | 2224 | pps_unlock(intel_dp); |
9934c132 JB |
2225 | } |
2226 | ||
9f0fb5be VS |
2227 | |
2228 | static void edp_panel_off(struct intel_dp *intel_dp) | |
9934c132 | 2229 | { |
4e6e1a54 ID |
2230 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2231 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
30add22d | 2232 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2233 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e6e1a54 | 2234 | enum intel_display_power_domain power_domain; |
99ea7127 | 2235 | u32 pp; |
f0f59a00 | 2236 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2237 | |
9f0fb5be VS |
2238 | lockdep_assert_held(&dev_priv->pps_mutex); |
2239 | ||
97af61f5 KP |
2240 | if (!is_edp(intel_dp)) |
2241 | return; | |
37c6c9b0 | 2242 | |
3936fcf4 VS |
2243 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2244 | port_name(dp_to_dig_port(intel_dp)->port)); | |
37c6c9b0 | 2245 | |
3936fcf4 VS |
2246 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2247 | port_name(dp_to_dig_port(intel_dp)->port)); | |
24f3e092 | 2248 | |
453c5420 | 2249 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
2250 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2251 | * panels get very unhappy and cease to work. */ | |
5a162e22 | 2252 | pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
b3064154 | 2253 | EDP_BLC_ENABLE); |
453c5420 | 2254 | |
bf13e81b | 2255 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2256 | |
849e39f5 PZ |
2257 | intel_dp->want_panel_vdd = false; |
2258 | ||
453c5420 JB |
2259 | I915_WRITE(pp_ctrl_reg, pp); |
2260 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2261 | |
d28d4731 | 2262 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
4be73780 | 2263 | wait_panel_off(intel_dp); |
849e39f5 PZ |
2264 | |
2265 | /* We got a reference when we enabled the VDD. */ | |
25f78f58 | 2266 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4e6e1a54 | 2267 | intel_display_power_put(dev_priv, power_domain); |
9f0fb5be | 2268 | } |
e39b999a | 2269 | |
9f0fb5be VS |
2270 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2271 | { | |
2272 | if (!is_edp(intel_dp)) | |
2273 | return; | |
e39b999a | 2274 | |
9f0fb5be VS |
2275 | pps_lock(intel_dp); |
2276 | edp_panel_off(intel_dp); | |
773538e8 | 2277 | pps_unlock(intel_dp); |
9934c132 JB |
2278 | } |
2279 | ||
1250d107 JN |
2280 | /* Enable backlight in the panel power control. */ |
2281 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) | |
32f9d658 | 2282 | { |
da63a9f2 PZ |
2283 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2284 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 2285 | struct drm_i915_private *dev_priv = to_i915(dev); |
32f9d658 | 2286 | u32 pp; |
f0f59a00 | 2287 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2288 | |
01cb9ea6 JB |
2289 | /* |
2290 | * If we enable the backlight right away following a panel power | |
2291 | * on, we may see slight flicker as the panel syncs with the eDP | |
2292 | * link. So delay a bit to make sure the image is solid before | |
2293 | * allowing it to appear. | |
2294 | */ | |
4be73780 | 2295 | wait_backlight_on(intel_dp); |
e39b999a | 2296 | |
773538e8 | 2297 | pps_lock(intel_dp); |
e39b999a | 2298 | |
453c5420 | 2299 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2300 | pp |= EDP_BLC_ENABLE; |
453c5420 | 2301 | |
bf13e81b | 2302 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2303 | |
2304 | I915_WRITE(pp_ctrl_reg, pp); | |
2305 | POSTING_READ(pp_ctrl_reg); | |
e39b999a | 2306 | |
773538e8 | 2307 | pps_unlock(intel_dp); |
32f9d658 ZW |
2308 | } |
2309 | ||
1250d107 JN |
2310 | /* Enable backlight PWM and backlight PP control. */ |
2311 | void intel_edp_backlight_on(struct intel_dp *intel_dp) | |
2312 | { | |
2313 | if (!is_edp(intel_dp)) | |
2314 | return; | |
2315 | ||
2316 | DRM_DEBUG_KMS("\n"); | |
2317 | ||
2318 | intel_panel_enable_backlight(intel_dp->attached_connector); | |
2319 | _intel_edp_backlight_on(intel_dp); | |
2320 | } | |
2321 | ||
2322 | /* Disable backlight in the panel power control. */ | |
2323 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) | |
32f9d658 | 2324 | { |
30add22d | 2325 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2326 | struct drm_i915_private *dev_priv = to_i915(dev); |
32f9d658 | 2327 | u32 pp; |
f0f59a00 | 2328 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2329 | |
f01eca2e KP |
2330 | if (!is_edp(intel_dp)) |
2331 | return; | |
2332 | ||
773538e8 | 2333 | pps_lock(intel_dp); |
e39b999a | 2334 | |
453c5420 | 2335 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2336 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 2337 | |
bf13e81b | 2338 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2339 | |
2340 | I915_WRITE(pp_ctrl_reg, pp); | |
2341 | POSTING_READ(pp_ctrl_reg); | |
f7d2323c | 2342 | |
773538e8 | 2343 | pps_unlock(intel_dp); |
e39b999a VS |
2344 | |
2345 | intel_dp->last_backlight_off = jiffies; | |
f7d2323c | 2346 | edp_wait_backlight_off(intel_dp); |
1250d107 | 2347 | } |
f7d2323c | 2348 | |
1250d107 JN |
2349 | /* Disable backlight PP control and backlight PWM. */ |
2350 | void intel_edp_backlight_off(struct intel_dp *intel_dp) | |
2351 | { | |
2352 | if (!is_edp(intel_dp)) | |
2353 | return; | |
2354 | ||
2355 | DRM_DEBUG_KMS("\n"); | |
f7d2323c | 2356 | |
1250d107 | 2357 | _intel_edp_backlight_off(intel_dp); |
f7d2323c | 2358 | intel_panel_disable_backlight(intel_dp->attached_connector); |
32f9d658 | 2359 | } |
a4fc5ed6 | 2360 | |
73580fb7 JN |
2361 | /* |
2362 | * Hook for controlling the panel power control backlight through the bl_power | |
2363 | * sysfs attribute. Take care to handle multiple calls. | |
2364 | */ | |
2365 | static void intel_edp_backlight_power(struct intel_connector *connector, | |
2366 | bool enable) | |
2367 | { | |
2368 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); | |
e39b999a VS |
2369 | bool is_enabled; |
2370 | ||
773538e8 | 2371 | pps_lock(intel_dp); |
e39b999a | 2372 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
773538e8 | 2373 | pps_unlock(intel_dp); |
73580fb7 JN |
2374 | |
2375 | if (is_enabled == enable) | |
2376 | return; | |
2377 | ||
23ba9373 JN |
2378 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2379 | enable ? "enable" : "disable"); | |
73580fb7 JN |
2380 | |
2381 | if (enable) | |
2382 | _intel_edp_backlight_on(intel_dp); | |
2383 | else | |
2384 | _intel_edp_backlight_off(intel_dp); | |
2385 | } | |
2386 | ||
64e1077a VS |
2387 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
2388 | { | |
2389 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2390 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
2391 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; | |
2392 | ||
2393 | I915_STATE_WARN(cur_state != state, | |
2394 | "DP port %c state assertion failure (expected %s, current %s)\n", | |
2395 | port_name(dig_port->port), | |
87ad3212 | 2396 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2397 | } |
2398 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) | |
2399 | ||
2400 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) | |
2401 | { | |
2402 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; | |
2403 | ||
2404 | I915_STATE_WARN(cur_state != state, | |
2405 | "eDP PLL state assertion failure (expected %s, current %s)\n", | |
87ad3212 | 2406 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2407 | } |
2408 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) | |
2409 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) | |
2410 | ||
85cb48a1 ML |
2411 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp, |
2412 | struct intel_crtc_state *pipe_config) | |
d240f20f | 2413 | { |
85cb48a1 | 2414 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
64e1077a | 2415 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d240f20f | 2416 | |
64e1077a VS |
2417 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2418 | assert_dp_port_disabled(intel_dp); | |
2419 | assert_edp_pll_disabled(dev_priv); | |
2bd2ad64 | 2420 | |
abfce949 | 2421 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
85cb48a1 | 2422 | pipe_config->port_clock); |
abfce949 VS |
2423 | |
2424 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; | |
2425 | ||
85cb48a1 | 2426 | if (pipe_config->port_clock == 162000) |
abfce949 VS |
2427 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
2428 | else | |
2429 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
2430 | ||
2431 | I915_WRITE(DP_A, intel_dp->DP); | |
2432 | POSTING_READ(DP_A); | |
2433 | udelay(500); | |
2434 | ||
6b23f3e8 VS |
2435 | /* |
2436 | * [DevILK] Work around required when enabling DP PLL | |
2437 | * while a pipe is enabled going to FDI: | |
2438 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI | |
2439 | * 2. Program DP PLL enable | |
2440 | */ | |
2441 | if (IS_GEN5(dev_priv)) | |
0f0f74bc | 2442 | intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); |
6b23f3e8 | 2443 | |
0767935e | 2444 | intel_dp->DP |= DP_PLL_ENABLE; |
6fec7662 | 2445 | |
0767935e | 2446 | I915_WRITE(DP_A, intel_dp->DP); |
298b0b39 JB |
2447 | POSTING_READ(DP_A); |
2448 | udelay(200); | |
d240f20f JB |
2449 | } |
2450 | ||
2bd2ad64 | 2451 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 2452 | { |
da63a9f2 | 2453 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
64e1077a VS |
2454 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2455 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
d240f20f | 2456 | |
64e1077a VS |
2457 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2458 | assert_dp_port_disabled(intel_dp); | |
2459 | assert_edp_pll_enabled(dev_priv); | |
2bd2ad64 | 2460 | |
abfce949 VS |
2461 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
2462 | ||
6fec7662 | 2463 | intel_dp->DP &= ~DP_PLL_ENABLE; |
0767935e | 2464 | |
6fec7662 | 2465 | I915_WRITE(DP_A, intel_dp->DP); |
1af5fa1b | 2466 | POSTING_READ(DP_A); |
d240f20f JB |
2467 | udelay(200); |
2468 | } | |
2469 | ||
c7ad3810 | 2470 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 2471 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
2472 | { |
2473 | int ret, i; | |
2474 | ||
2475 | /* Should have a valid DPCD by this point */ | |
2476 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
2477 | return; | |
2478 | ||
2479 | if (mode != DRM_MODE_DPMS_ON) { | |
9d1a1031 JN |
2480 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2481 | DP_SET_POWER_D3); | |
c7ad3810 | 2482 | } else { |
357c0ae9 ID |
2483 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
2484 | ||
c7ad3810 JB |
2485 | /* |
2486 | * When turning on, we need to retry for 1ms to give the sink | |
2487 | * time to wake up. | |
2488 | */ | |
2489 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
2490 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2491 | DP_SET_POWER_D0); | |
c7ad3810 JB |
2492 | if (ret == 1) |
2493 | break; | |
2494 | msleep(1); | |
2495 | } | |
357c0ae9 ID |
2496 | |
2497 | if (ret == 1 && lspcon->active) | |
2498 | lspcon_wait_pcon_mode(lspcon); | |
c7ad3810 | 2499 | } |
f9cac721 JN |
2500 | |
2501 | if (ret != 1) | |
2502 | DRM_DEBUG_KMS("failed to %s sink power state\n", | |
2503 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); | |
c7ad3810 JB |
2504 | } |
2505 | ||
19d8fe15 DV |
2506 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2507 | enum pipe *pipe) | |
d240f20f | 2508 | { |
19d8fe15 | 2509 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 2510 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 | 2511 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2512 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d129bea ID |
2513 | enum intel_display_power_domain power_domain; |
2514 | u32 tmp; | |
6fa9a5ec | 2515 | bool ret; |
6d129bea ID |
2516 | |
2517 | power_domain = intel_display_port_power_domain(encoder); | |
6fa9a5ec | 2518 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
2519 | return false; |
2520 | ||
6fa9a5ec ID |
2521 | ret = false; |
2522 | ||
6d129bea | 2523 | tmp = I915_READ(intel_dp->output_reg); |
19d8fe15 DV |
2524 | |
2525 | if (!(tmp & DP_PORT_EN)) | |
6fa9a5ec | 2526 | goto out; |
19d8fe15 | 2527 | |
5db94019 | 2528 | if (IS_GEN7(dev_priv) && port == PORT_A) { |
19d8fe15 | 2529 | *pipe = PORT_TO_PIPE_CPT(tmp); |
6e266956 | 2530 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
adc289d7 | 2531 | enum pipe p; |
19d8fe15 | 2532 | |
adc289d7 VS |
2533 | for_each_pipe(dev_priv, p) { |
2534 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); | |
2535 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { | |
2536 | *pipe = p; | |
6fa9a5ec ID |
2537 | ret = true; |
2538 | ||
2539 | goto out; | |
19d8fe15 DV |
2540 | } |
2541 | } | |
19d8fe15 | 2542 | |
4a0833ec | 2543 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
f0f59a00 | 2544 | i915_mmio_reg_offset(intel_dp->output_reg)); |
920a14b2 | 2545 | } else if (IS_CHERRYVIEW(dev_priv)) { |
39e5fa88 VS |
2546 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
2547 | } else { | |
2548 | *pipe = PORT_TO_PIPE(tmp); | |
4a0833ec | 2549 | } |
d240f20f | 2550 | |
6fa9a5ec ID |
2551 | ret = true; |
2552 | ||
2553 | out: | |
2554 | intel_display_power_put(dev_priv, power_domain); | |
2555 | ||
2556 | return ret; | |
19d8fe15 | 2557 | } |
d240f20f | 2558 | |
045ac3b5 | 2559 | static void intel_dp_get_config(struct intel_encoder *encoder, |
5cec258b | 2560 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
2561 | { |
2562 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 2563 | u32 tmp, flags = 0; |
63000ef6 | 2564 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2565 | struct drm_i915_private *dev_priv = to_i915(dev); |
63000ef6 XZ |
2566 | enum port port = dp_to_dig_port(intel_dp)->port; |
2567 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
045ac3b5 | 2568 | |
9ed109a7 | 2569 | tmp = I915_READ(intel_dp->output_reg); |
9fcb1704 JN |
2570 | |
2571 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; | |
9ed109a7 | 2572 | |
6e266956 | 2573 | if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
b81e34c2 VS |
2574 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2575 | ||
2576 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
63000ef6 XZ |
2577 | flags |= DRM_MODE_FLAG_PHSYNC; |
2578 | else | |
2579 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2580 | |
b81e34c2 | 2581 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
63000ef6 XZ |
2582 | flags |= DRM_MODE_FLAG_PVSYNC; |
2583 | else | |
2584 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2585 | } else { | |
39e5fa88 | 2586 | if (tmp & DP_SYNC_HS_HIGH) |
63000ef6 XZ |
2587 | flags |= DRM_MODE_FLAG_PHSYNC; |
2588 | else | |
2589 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2590 | |
39e5fa88 | 2591 | if (tmp & DP_SYNC_VS_HIGH) |
63000ef6 XZ |
2592 | flags |= DRM_MODE_FLAG_PVSYNC; |
2593 | else | |
2594 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2595 | } | |
045ac3b5 | 2596 | |
2d112de7 | 2597 | pipe_config->base.adjusted_mode.flags |= flags; |
f1f644dc | 2598 | |
c99f53f7 | 2599 | if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) |
8c875fca VS |
2600 | pipe_config->limited_color_range = true; |
2601 | ||
90a6b7b0 VS |
2602 | pipe_config->lane_count = |
2603 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; | |
2604 | ||
eb14cb74 VS |
2605 | intel_dp_get_m_n(crtc, pipe_config); |
2606 | ||
18442d08 | 2607 | if (port == PORT_A) { |
b377e0df | 2608 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
f1f644dc JB |
2609 | pipe_config->port_clock = 162000; |
2610 | else | |
2611 | pipe_config->port_clock = 270000; | |
2612 | } | |
18442d08 | 2613 | |
e3b247da VS |
2614 | pipe_config->base.adjusted_mode.crtc_clock = |
2615 | intel_dotclock_calculate(pipe_config->port_clock, | |
2616 | &pipe_config->dp_m_n); | |
7f16e5c1 | 2617 | |
6aa23e65 JN |
2618 | if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
2619 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { | |
c6cd2ee2 JN |
2620 | /* |
2621 | * This is a big fat ugly hack. | |
2622 | * | |
2623 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2624 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2625 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2626 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2627 | * max, not what it tells us to use. | |
2628 | * | |
2629 | * Note: This will still be broken if the eDP panel is not lit | |
2630 | * up by the BIOS, and thus we can't get the mode at module | |
2631 | * load. | |
2632 | */ | |
2633 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
2634 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
2635 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
c6cd2ee2 | 2636 | } |
045ac3b5 JB |
2637 | } |
2638 | ||
fd6bbda9 ML |
2639 | static void intel_disable_dp(struct intel_encoder *encoder, |
2640 | struct intel_crtc_state *old_crtc_state, | |
2641 | struct drm_connector_state *old_conn_state) | |
d240f20f | 2642 | { |
e8cb4558 | 2643 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
85cb48a1 | 2644 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
495a5bb8 | 2645 | |
85cb48a1 | 2646 | if (old_crtc_state->has_audio) |
495a5bb8 | 2647 | intel_audio_codec_disable(encoder); |
6cb49835 | 2648 | |
85cb48a1 | 2649 | if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv)) |
b32c6f48 RV |
2650 | intel_psr_disable(intel_dp); |
2651 | ||
6cb49835 DV |
2652 | /* Make sure the panel is off before trying to change the mode. But also |
2653 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 2654 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 2655 | intel_edp_backlight_off(intel_dp); |
fdbc3b1f | 2656 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 2657 | intel_edp_panel_off(intel_dp); |
3739850b | 2658 | |
08aff3fe | 2659 | /* disable the port before the pipe on g4x */ |
85cb48a1 | 2660 | if (INTEL_GEN(dev_priv) < 5) |
3739850b | 2661 | intel_dp_link_down(intel_dp); |
d240f20f JB |
2662 | } |
2663 | ||
fd6bbda9 ML |
2664 | static void ilk_post_disable_dp(struct intel_encoder *encoder, |
2665 | struct intel_crtc_state *old_crtc_state, | |
2666 | struct drm_connector_state *old_conn_state) | |
d240f20f | 2667 | { |
2bd2ad64 | 2668 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2669 | enum port port = dp_to_dig_port(intel_dp)->port; |
2bd2ad64 | 2670 | |
49277c31 | 2671 | intel_dp_link_down(intel_dp); |
abfce949 VS |
2672 | |
2673 | /* Only ilk+ has port A */ | |
08aff3fe VS |
2674 | if (port == PORT_A) |
2675 | ironlake_edp_pll_off(intel_dp); | |
49277c31 VS |
2676 | } |
2677 | ||
fd6bbda9 ML |
2678 | static void vlv_post_disable_dp(struct intel_encoder *encoder, |
2679 | struct intel_crtc_state *old_crtc_state, | |
2680 | struct drm_connector_state *old_conn_state) | |
49277c31 VS |
2681 | { |
2682 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2683 | ||
2684 | intel_dp_link_down(intel_dp); | |
2bd2ad64 DV |
2685 | } |
2686 | ||
fd6bbda9 ML |
2687 | static void chv_post_disable_dp(struct intel_encoder *encoder, |
2688 | struct intel_crtc_state *old_crtc_state, | |
2689 | struct drm_connector_state *old_conn_state) | |
a8f327fb VS |
2690 | { |
2691 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2692 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2693 | struct drm_i915_private *dev_priv = to_i915(dev); |
97fd4d5c | 2694 | |
a8f327fb VS |
2695 | intel_dp_link_down(intel_dp); |
2696 | ||
2697 | mutex_lock(&dev_priv->sb_lock); | |
2698 | ||
2699 | /* Assert data lane reset */ | |
2700 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 2701 | |
a580516d | 2702 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
2703 | } |
2704 | ||
7b13b58a VS |
2705 | static void |
2706 | _intel_dp_set_link_train(struct intel_dp *intel_dp, | |
2707 | uint32_t *DP, | |
2708 | uint8_t dp_train_pat) | |
2709 | { | |
2710 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2711 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 2712 | struct drm_i915_private *dev_priv = to_i915(dev); |
7b13b58a VS |
2713 | enum port port = intel_dig_port->port; |
2714 | ||
8b0878a0 PD |
2715 | if (dp_train_pat & DP_TRAINING_PATTERN_MASK) |
2716 | DRM_DEBUG_KMS("Using DP training pattern TPS%d\n", | |
2717 | dp_train_pat & DP_TRAINING_PATTERN_MASK); | |
2718 | ||
4f8036a2 | 2719 | if (HAS_DDI(dev_priv)) { |
7b13b58a VS |
2720 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
2721 | ||
2722 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2723 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2724 | else | |
2725 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2726 | ||
2727 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2728 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2729 | case DP_TRAINING_PATTERN_DISABLE: | |
2730 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; | |
2731 | ||
2732 | break; | |
2733 | case DP_TRAINING_PATTERN_1: | |
2734 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2735 | break; | |
2736 | case DP_TRAINING_PATTERN_2: | |
2737 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2738 | break; | |
2739 | case DP_TRAINING_PATTERN_3: | |
2740 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2741 | break; | |
2742 | } | |
2743 | I915_WRITE(DP_TP_CTL(port), temp); | |
2744 | ||
5db94019 | 2745 | } else if ((IS_GEN7(dev_priv) && port == PORT_A) || |
6e266956 | 2746 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
7b13b58a VS |
2747 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2748 | ||
2749 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2750 | case DP_TRAINING_PATTERN_DISABLE: | |
2751 | *DP |= DP_LINK_TRAIN_OFF_CPT; | |
2752 | break; | |
2753 | case DP_TRAINING_PATTERN_1: | |
2754 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; | |
2755 | break; | |
2756 | case DP_TRAINING_PATTERN_2: | |
2757 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2758 | break; | |
2759 | case DP_TRAINING_PATTERN_3: | |
8b0878a0 | 2760 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
7b13b58a VS |
2761 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2762 | break; | |
2763 | } | |
2764 | ||
2765 | } else { | |
920a14b2 | 2766 | if (IS_CHERRYVIEW(dev_priv)) |
7b13b58a VS |
2767 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
2768 | else | |
2769 | *DP &= ~DP_LINK_TRAIN_MASK; | |
2770 | ||
2771 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2772 | case DP_TRAINING_PATTERN_DISABLE: | |
2773 | *DP |= DP_LINK_TRAIN_OFF; | |
2774 | break; | |
2775 | case DP_TRAINING_PATTERN_1: | |
2776 | *DP |= DP_LINK_TRAIN_PAT_1; | |
2777 | break; | |
2778 | case DP_TRAINING_PATTERN_2: | |
2779 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2780 | break; | |
2781 | case DP_TRAINING_PATTERN_3: | |
920a14b2 | 2782 | if (IS_CHERRYVIEW(dev_priv)) { |
7b13b58a VS |
2783 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
2784 | } else { | |
8b0878a0 | 2785 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
7b13b58a VS |
2786 | *DP |= DP_LINK_TRAIN_PAT_2; |
2787 | } | |
2788 | break; | |
2789 | } | |
2790 | } | |
2791 | } | |
2792 | ||
85cb48a1 ML |
2793 | static void intel_dp_enable_port(struct intel_dp *intel_dp, |
2794 | struct intel_crtc_state *old_crtc_state) | |
7b13b58a VS |
2795 | { |
2796 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 2797 | struct drm_i915_private *dev_priv = to_i915(dev); |
7b13b58a | 2798 | |
7b13b58a | 2799 | /* enable with pattern 1 (as per spec) */ |
7b13b58a | 2800 | |
8b0878a0 | 2801 | intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1); |
7b713f50 VS |
2802 | |
2803 | /* | |
2804 | * Magic for VLV/CHV. We _must_ first set up the register | |
2805 | * without actually enabling the port, and then do another | |
2806 | * write to enable the port. Otherwise link training will | |
2807 | * fail when the power sequencer is freshly used for this port. | |
2808 | */ | |
2809 | intel_dp->DP |= DP_PORT_EN; | |
85cb48a1 | 2810 | if (old_crtc_state->has_audio) |
6fec7662 | 2811 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
7b713f50 VS |
2812 | |
2813 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2814 | POSTING_READ(intel_dp->output_reg); | |
580d3811 VS |
2815 | } |
2816 | ||
85cb48a1 | 2817 | static void intel_enable_dp(struct intel_encoder *encoder, |
bbf35e9d ML |
2818 | struct intel_crtc_state *pipe_config, |
2819 | struct drm_connector_state *conn_state) | |
d240f20f | 2820 | { |
e8cb4558 DV |
2821 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2822 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2823 | struct drm_i915_private *dev_priv = to_i915(dev); |
c1dec79a | 2824 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
e8cb4558 | 2825 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
d6fbdd15 | 2826 | enum pipe pipe = crtc->pipe; |
5d613501 | 2827 | |
0c33d8d7 DV |
2828 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2829 | return; | |
5d613501 | 2830 | |
093e3f13 VS |
2831 | pps_lock(intel_dp); |
2832 | ||
920a14b2 | 2833 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
093e3f13 VS |
2834 | vlv_init_panel_power_sequencer(intel_dp); |
2835 | ||
85cb48a1 | 2836 | intel_dp_enable_port(intel_dp, pipe_config); |
093e3f13 VS |
2837 | |
2838 | edp_panel_vdd_on(intel_dp); | |
2839 | edp_panel_on(intel_dp); | |
2840 | edp_panel_vdd_off(intel_dp, true); | |
2841 | ||
2842 | pps_unlock(intel_dp); | |
2843 | ||
920a14b2 | 2844 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e0fce78f VS |
2845 | unsigned int lane_mask = 0x0; |
2846 | ||
920a14b2 | 2847 | if (IS_CHERRYVIEW(dev_priv)) |
85cb48a1 | 2848 | lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); |
e0fce78f | 2849 | |
9b6de0a1 VS |
2850 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2851 | lane_mask); | |
e0fce78f | 2852 | } |
61234fa5 | 2853 | |
f01eca2e | 2854 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 2855 | intel_dp_start_link_train(intel_dp); |
3ab9c637 | 2856 | intel_dp_stop_link_train(intel_dp); |
c1dec79a | 2857 | |
85cb48a1 | 2858 | if (pipe_config->has_audio) { |
c1dec79a | 2859 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
d6fbdd15 | 2860 | pipe_name(pipe)); |
bbf35e9d | 2861 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
c1dec79a | 2862 | } |
ab1f90f9 | 2863 | } |
89b667f8 | 2864 | |
fd6bbda9 ML |
2865 | static void g4x_enable_dp(struct intel_encoder *encoder, |
2866 | struct intel_crtc_state *pipe_config, | |
2867 | struct drm_connector_state *conn_state) | |
ecff4f3b | 2868 | { |
828f5c6e JN |
2869 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2870 | ||
bbf35e9d | 2871 | intel_enable_dp(encoder, pipe_config, conn_state); |
4be73780 | 2872 | intel_edp_backlight_on(intel_dp); |
ab1f90f9 | 2873 | } |
89b667f8 | 2874 | |
fd6bbda9 ML |
2875 | static void vlv_enable_dp(struct intel_encoder *encoder, |
2876 | struct intel_crtc_state *pipe_config, | |
2877 | struct drm_connector_state *conn_state) | |
ab1f90f9 | 2878 | { |
828f5c6e JN |
2879 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2880 | ||
4be73780 | 2881 | intel_edp_backlight_on(intel_dp); |
b32c6f48 | 2882 | intel_psr_enable(intel_dp); |
d240f20f JB |
2883 | } |
2884 | ||
fd6bbda9 ML |
2885 | static void g4x_pre_enable_dp(struct intel_encoder *encoder, |
2886 | struct intel_crtc_state *pipe_config, | |
2887 | struct drm_connector_state *conn_state) | |
ab1f90f9 JN |
2888 | { |
2889 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
d6fbdd15 | 2890 | enum port port = dp_to_dig_port(intel_dp)->port; |
ab1f90f9 | 2891 | |
85cb48a1 | 2892 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 2893 | |
d41f1efb | 2894 | /* Only ilk+ has port A */ |
abfce949 | 2895 | if (port == PORT_A) |
85cb48a1 | 2896 | ironlake_edp_pll_on(intel_dp, pipe_config); |
ab1f90f9 JN |
2897 | } |
2898 | ||
83b84597 VS |
2899 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2900 | { | |
2901 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
fac5e23e | 2902 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
83b84597 | 2903 | enum pipe pipe = intel_dp->pps_pipe; |
44cb734c | 2904 | i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); |
83b84597 | 2905 | |
9f2bdb00 VS |
2906 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); |
2907 | ||
83b84597 VS |
2908 | edp_panel_vdd_off_sync(intel_dp); |
2909 | ||
2910 | /* | |
2911 | * VLV seems to get confused when multiple power seqeuencers | |
2912 | * have the same port selected (even if only one has power/vdd | |
2913 | * enabled). The failure manifests as vlv_wait_port_ready() failing | |
2914 | * CHV on the other hand doesn't seem to mind having the same port | |
2915 | * selected in multiple power seqeuencers, but let's clear the | |
2916 | * port select always when logically disconnecting a power sequencer | |
2917 | * from a port. | |
2918 | */ | |
2919 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", | |
2920 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
2921 | I915_WRITE(pp_on_reg, 0); | |
2922 | POSTING_READ(pp_on_reg); | |
2923 | ||
2924 | intel_dp->pps_pipe = INVALID_PIPE; | |
2925 | } | |
2926 | ||
a4a5d2f8 VS |
2927 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2928 | enum pipe pipe) | |
2929 | { | |
fac5e23e | 2930 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
2931 | struct intel_encoder *encoder; |
2932 | ||
2933 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2934 | ||
ac3c12e4 VS |
2935 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2936 | return; | |
2937 | ||
19c8054c | 2938 | for_each_intel_encoder(dev, encoder) { |
a4a5d2f8 | 2939 | struct intel_dp *intel_dp; |
773538e8 | 2940 | enum port port; |
a4a5d2f8 | 2941 | |
9f2bdb00 VS |
2942 | if (encoder->type != INTEL_OUTPUT_DP && |
2943 | encoder->type != INTEL_OUTPUT_EDP) | |
a4a5d2f8 VS |
2944 | continue; |
2945 | ||
2946 | intel_dp = enc_to_intel_dp(&encoder->base); | |
773538e8 | 2947 | port = dp_to_dig_port(intel_dp)->port; |
a4a5d2f8 | 2948 | |
9f2bdb00 VS |
2949 | WARN(intel_dp->active_pipe == pipe, |
2950 | "stealing pipe %c power sequencer from active (e)DP port %c\n", | |
2951 | pipe_name(pipe), port_name(port)); | |
2952 | ||
a4a5d2f8 VS |
2953 | if (intel_dp->pps_pipe != pipe) |
2954 | continue; | |
2955 | ||
2956 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", | |
773538e8 | 2957 | pipe_name(pipe), port_name(port)); |
a4a5d2f8 VS |
2958 | |
2959 | /* make sure vdd is off before we steal it */ | |
83b84597 | 2960 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2961 | } |
2962 | } | |
2963 | ||
2964 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) | |
2965 | { | |
2966 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2967 | struct intel_encoder *encoder = &intel_dig_port->base; | |
2968 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2969 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 | 2970 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
a4a5d2f8 VS |
2971 | |
2972 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2973 | ||
9f2bdb00 | 2974 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); |
093e3f13 | 2975 | |
9f2bdb00 VS |
2976 | if (intel_dp->pps_pipe != INVALID_PIPE && |
2977 | intel_dp->pps_pipe != crtc->pipe) { | |
2978 | /* | |
2979 | * If another power sequencer was being used on this | |
2980 | * port previously make sure to turn off vdd there while | |
2981 | * we still have control of it. | |
2982 | */ | |
83b84597 | 2983 | vlv_detach_power_sequencer(intel_dp); |
9f2bdb00 | 2984 | } |
a4a5d2f8 VS |
2985 | |
2986 | /* | |
2987 | * We may be stealing the power | |
2988 | * sequencer from another port. | |
2989 | */ | |
2990 | vlv_steal_power_sequencer(dev, crtc->pipe); | |
2991 | ||
9f2bdb00 VS |
2992 | intel_dp->active_pipe = crtc->pipe; |
2993 | ||
2994 | if (!is_edp(intel_dp)) | |
2995 | return; | |
2996 | ||
a4a5d2f8 VS |
2997 | /* now it's all ours */ |
2998 | intel_dp->pps_pipe = crtc->pipe; | |
2999 | ||
3000 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", | |
3001 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); | |
3002 | ||
3003 | /* init power sequencer on this pipe and port */ | |
36b5f425 | 3004 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
5d5ab2d2 | 3005 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true); |
a4a5d2f8 VS |
3006 | } |
3007 | ||
fd6bbda9 ML |
3008 | static void vlv_pre_enable_dp(struct intel_encoder *encoder, |
3009 | struct intel_crtc_state *pipe_config, | |
3010 | struct drm_connector_state *conn_state) | |
a4fc5ed6 | 3011 | { |
5f68c275 | 3012 | vlv_phy_pre_encoder_enable(encoder); |
ab1f90f9 | 3013 | |
bbf35e9d | 3014 | intel_enable_dp(encoder, pipe_config, conn_state); |
89b667f8 JB |
3015 | } |
3016 | ||
fd6bbda9 ML |
3017 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder, |
3018 | struct intel_crtc_state *pipe_config, | |
3019 | struct drm_connector_state *conn_state) | |
89b667f8 | 3020 | { |
85cb48a1 | 3021 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 3022 | |
6da2e616 | 3023 | vlv_phy_pre_pll_enable(encoder); |
a4fc5ed6 KP |
3024 | } |
3025 | ||
fd6bbda9 ML |
3026 | static void chv_pre_enable_dp(struct intel_encoder *encoder, |
3027 | struct intel_crtc_state *pipe_config, | |
3028 | struct drm_connector_state *conn_state) | |
e4a1d846 | 3029 | { |
e7d2a717 | 3030 | chv_phy_pre_encoder_enable(encoder); |
e4a1d846 | 3031 | |
bbf35e9d | 3032 | intel_enable_dp(encoder, pipe_config, conn_state); |
b0b33846 VS |
3033 | |
3034 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 3035 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
3036 | } |
3037 | ||
fd6bbda9 ML |
3038 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder, |
3039 | struct intel_crtc_state *pipe_config, | |
3040 | struct drm_connector_state *conn_state) | |
9197c88b | 3041 | { |
85cb48a1 | 3042 | intel_dp_prepare(encoder, pipe_config); |
625695f8 | 3043 | |
419b1b7a | 3044 | chv_phy_pre_pll_enable(encoder); |
9197c88b VS |
3045 | } |
3046 | ||
fd6bbda9 ML |
3047 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder, |
3048 | struct intel_crtc_state *pipe_config, | |
3049 | struct drm_connector_state *conn_state) | |
d6db995f | 3050 | { |
204970b5 | 3051 | chv_phy_post_pll_disable(encoder); |
d6db995f VS |
3052 | } |
3053 | ||
a4fc5ed6 KP |
3054 | /* |
3055 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
3056 | * link status information | |
3057 | */ | |
94223d04 | 3058 | bool |
93f62dad | 3059 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 3060 | { |
9f085ebb L |
3061 | return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, |
3062 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
3063 | } |
3064 | ||
97da2ef4 NV |
3065 | static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp) |
3066 | { | |
3067 | uint8_t psr_caps = 0; | |
3068 | ||
3069 | drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps); | |
3070 | return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED; | |
3071 | } | |
3072 | ||
3073 | static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) | |
3074 | { | |
3075 | uint8_t dprx = 0; | |
3076 | ||
3077 | drm_dp_dpcd_readb(&intel_dp->aux, | |
3078 | DP_DPRX_FEATURE_ENUMERATION_LIST, | |
3079 | &dprx); | |
3080 | return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; | |
3081 | } | |
3082 | ||
a76f73dc | 3083 | static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) |
340c93c0 NV |
3084 | { |
3085 | uint8_t alpm_caps = 0; | |
3086 | ||
3087 | drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &alpm_caps); | |
3088 | return alpm_caps & DP_ALPM_CAP; | |
3089 | } | |
3090 | ||
1100244e | 3091 | /* These are source-specific values. */ |
94223d04 | 3092 | uint8_t |
1a2eb460 | 3093 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 3094 | { |
dd11bc10 | 3095 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
bc7d38a4 | 3096 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 3097 | |
cc3f90f0 | 3098 | if (IS_GEN9_LP(dev_priv)) |
9314726b | 3099 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
dd11bc10 | 3100 | else if (INTEL_GEN(dev_priv) >= 9) { |
06411f08 | 3101 | if (dev_priv->vbt.edp.low_vswing && port == PORT_A) |
7ad14a29 | 3102 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
5a9d1f1a | 3103 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
920a14b2 | 3104 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
bd60018a | 3105 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
5db94019 | 3106 | else if (IS_GEN7(dev_priv) && port == PORT_A) |
bd60018a | 3107 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
6e266956 | 3108 | else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) |
bd60018a | 3109 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
1a2eb460 | 3110 | else |
bd60018a | 3111 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
1a2eb460 KP |
3112 | } |
3113 | ||
94223d04 | 3114 | uint8_t |
1a2eb460 KP |
3115 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
3116 | { | |
8652744b | 3117 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
bc7d38a4 | 3118 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 3119 | |
8652744b | 3120 | if (INTEL_GEN(dev_priv) >= 9) { |
5a9d1f1a DL |
3121 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3122 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: | |
3123 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3124 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3125 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3126 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3127 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
7ad14a29 SJ |
3128 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3129 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
5a9d1f1a DL |
3130 | default: |
3131 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
3132 | } | |
8652744b | 3133 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
d6c0d722 | 3134 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3135 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3136 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3137 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3138 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3139 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3140 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3141 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
d6c0d722 | 3142 | default: |
bd60018a | 3143 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
d6c0d722 | 3144 | } |
8652744b | 3145 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e2fa6fba | 3146 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3147 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3148 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3149 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3150 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3151 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3152 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3153 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
e2fa6fba | 3154 | default: |
bd60018a | 3155 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
e2fa6fba | 3156 | } |
8652744b | 3157 | } else if (IS_GEN7(dev_priv) && port == PORT_A) { |
1a2eb460 | 3158 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3159 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3160 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3161 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3162 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3163 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
1a2eb460 | 3164 | default: |
bd60018a | 3165 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 KP |
3166 | } |
3167 | } else { | |
3168 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
3169 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3170 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3171 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3172 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3173 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3174 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3175 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
1a2eb460 | 3176 | default: |
bd60018a | 3177 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 | 3178 | } |
a4fc5ed6 KP |
3179 | } |
3180 | } | |
3181 | ||
5829975c | 3182 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
e2fa6fba | 3183 | { |
53d98725 | 3184 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
e2fa6fba P |
3185 | unsigned long demph_reg_value, preemph_reg_value, |
3186 | uniqtranscale_reg_value; | |
3187 | uint8_t train_set = intel_dp->train_set[0]; | |
e2fa6fba P |
3188 | |
3189 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3190 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e2fa6fba P |
3191 | preemph_reg_value = 0x0004000; |
3192 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3193 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3194 | demph_reg_value = 0x2B405555; |
3195 | uniqtranscale_reg_value = 0x552AB83A; | |
3196 | break; | |
bd60018a | 3197 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3198 | demph_reg_value = 0x2B404040; |
3199 | uniqtranscale_reg_value = 0x5548B83A; | |
3200 | break; | |
bd60018a | 3201 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3202 | demph_reg_value = 0x2B245555; |
3203 | uniqtranscale_reg_value = 0x5560B83A; | |
3204 | break; | |
bd60018a | 3205 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e2fa6fba P |
3206 | demph_reg_value = 0x2B405555; |
3207 | uniqtranscale_reg_value = 0x5598DA3A; | |
3208 | break; | |
3209 | default: | |
3210 | return 0; | |
3211 | } | |
3212 | break; | |
bd60018a | 3213 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e2fa6fba P |
3214 | preemph_reg_value = 0x0002000; |
3215 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3216 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3217 | demph_reg_value = 0x2B404040; |
3218 | uniqtranscale_reg_value = 0x5552B83A; | |
3219 | break; | |
bd60018a | 3220 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3221 | demph_reg_value = 0x2B404848; |
3222 | uniqtranscale_reg_value = 0x5580B83A; | |
3223 | break; | |
bd60018a | 3224 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3225 | demph_reg_value = 0x2B404040; |
3226 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3227 | break; | |
3228 | default: | |
3229 | return 0; | |
3230 | } | |
3231 | break; | |
bd60018a | 3232 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e2fa6fba P |
3233 | preemph_reg_value = 0x0000000; |
3234 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3235 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3236 | demph_reg_value = 0x2B305555; |
3237 | uniqtranscale_reg_value = 0x5570B83A; | |
3238 | break; | |
bd60018a | 3239 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3240 | demph_reg_value = 0x2B2B4040; |
3241 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3242 | break; | |
3243 | default: | |
3244 | return 0; | |
3245 | } | |
3246 | break; | |
bd60018a | 3247 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e2fa6fba P |
3248 | preemph_reg_value = 0x0006000; |
3249 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3250 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3251 | demph_reg_value = 0x1B405555; |
3252 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3253 | break; | |
3254 | default: | |
3255 | return 0; | |
3256 | } | |
3257 | break; | |
3258 | default: | |
3259 | return 0; | |
3260 | } | |
3261 | ||
53d98725 ACO |
3262 | vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, |
3263 | uniqtranscale_reg_value, 0); | |
e2fa6fba P |
3264 | |
3265 | return 0; | |
3266 | } | |
3267 | ||
5829975c | 3268 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
e4a1d846 | 3269 | { |
b7fa22d8 ACO |
3270 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3271 | u32 deemph_reg_value, margin_reg_value; | |
3272 | bool uniq_trans_scale = false; | |
e4a1d846 | 3273 | uint8_t train_set = intel_dp->train_set[0]; |
e4a1d846 CML |
3274 | |
3275 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3276 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e4a1d846 | 3277 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3278 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3279 | deemph_reg_value = 128; |
3280 | margin_reg_value = 52; | |
3281 | break; | |
bd60018a | 3282 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3283 | deemph_reg_value = 128; |
3284 | margin_reg_value = 77; | |
3285 | break; | |
bd60018a | 3286 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3287 | deemph_reg_value = 128; |
3288 | margin_reg_value = 102; | |
3289 | break; | |
bd60018a | 3290 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e4a1d846 CML |
3291 | deemph_reg_value = 128; |
3292 | margin_reg_value = 154; | |
b7fa22d8 | 3293 | uniq_trans_scale = true; |
e4a1d846 CML |
3294 | break; |
3295 | default: | |
3296 | return 0; | |
3297 | } | |
3298 | break; | |
bd60018a | 3299 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e4a1d846 | 3300 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3301 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3302 | deemph_reg_value = 85; |
3303 | margin_reg_value = 78; | |
3304 | break; | |
bd60018a | 3305 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3306 | deemph_reg_value = 85; |
3307 | margin_reg_value = 116; | |
3308 | break; | |
bd60018a | 3309 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3310 | deemph_reg_value = 85; |
3311 | margin_reg_value = 154; | |
3312 | break; | |
3313 | default: | |
3314 | return 0; | |
3315 | } | |
3316 | break; | |
bd60018a | 3317 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e4a1d846 | 3318 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3319 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3320 | deemph_reg_value = 64; |
3321 | margin_reg_value = 104; | |
3322 | break; | |
bd60018a | 3323 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3324 | deemph_reg_value = 64; |
3325 | margin_reg_value = 154; | |
3326 | break; | |
3327 | default: | |
3328 | return 0; | |
3329 | } | |
3330 | break; | |
bd60018a | 3331 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e4a1d846 | 3332 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3333 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3334 | deemph_reg_value = 43; |
3335 | margin_reg_value = 154; | |
3336 | break; | |
3337 | default: | |
3338 | return 0; | |
3339 | } | |
3340 | break; | |
3341 | default: | |
3342 | return 0; | |
3343 | } | |
3344 | ||
b7fa22d8 ACO |
3345 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
3346 | margin_reg_value, uniq_trans_scale); | |
e4a1d846 CML |
3347 | |
3348 | return 0; | |
3349 | } | |
3350 | ||
a4fc5ed6 | 3351 | static uint32_t |
5829975c | 3352 | gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 3353 | { |
3cf2efb1 | 3354 | uint32_t signal_levels = 0; |
a4fc5ed6 | 3355 | |
3cf2efb1 | 3356 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3357 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
a4fc5ed6 KP |
3358 | default: |
3359 | signal_levels |= DP_VOLTAGE_0_4; | |
3360 | break; | |
bd60018a | 3361 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
a4fc5ed6 KP |
3362 | signal_levels |= DP_VOLTAGE_0_6; |
3363 | break; | |
bd60018a | 3364 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
a4fc5ed6 KP |
3365 | signal_levels |= DP_VOLTAGE_0_8; |
3366 | break; | |
bd60018a | 3367 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
a4fc5ed6 KP |
3368 | signal_levels |= DP_VOLTAGE_1_2; |
3369 | break; | |
3370 | } | |
3cf2efb1 | 3371 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
bd60018a | 3372 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
a4fc5ed6 KP |
3373 | default: |
3374 | signal_levels |= DP_PRE_EMPHASIS_0; | |
3375 | break; | |
bd60018a | 3376 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
a4fc5ed6 KP |
3377 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3378 | break; | |
bd60018a | 3379 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
a4fc5ed6 KP |
3380 | signal_levels |= DP_PRE_EMPHASIS_6; |
3381 | break; | |
bd60018a | 3382 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
a4fc5ed6 KP |
3383 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3384 | break; | |
3385 | } | |
3386 | return signal_levels; | |
3387 | } | |
3388 | ||
e3421a18 ZW |
3389 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3390 | static uint32_t | |
5829975c | 3391 | gen6_edp_signal_levels(uint8_t train_set) |
e3421a18 | 3392 | { |
3c5a62b5 YL |
3393 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3394 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3395 | switch (signal_levels) { | |
bd60018a SJ |
3396 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3397 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3398 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
bd60018a | 3399 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3c5a62b5 | 3400 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
bd60018a SJ |
3401 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3402 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
3c5a62b5 | 3403 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
bd60018a SJ |
3404 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3405 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
3c5a62b5 | 3406 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
bd60018a SJ |
3407 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3408 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3409 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
e3421a18 | 3410 | default: |
3c5a62b5 YL |
3411 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3412 | "0x%x\n", signal_levels); | |
3413 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
3414 | } |
3415 | } | |
3416 | ||
1a2eb460 KP |
3417 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3418 | static uint32_t | |
5829975c | 3419 | gen7_edp_signal_levels(uint8_t train_set) |
1a2eb460 KP |
3420 | { |
3421 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
3422 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3423 | switch (signal_levels) { | |
bd60018a | 3424 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3425 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
bd60018a | 3426 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 | 3427 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
bd60018a | 3428 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
1a2eb460 KP |
3429 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3430 | ||
bd60018a | 3431 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3432 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
bd60018a | 3433 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3434 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3435 | ||
bd60018a | 3436 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3437 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
bd60018a | 3438 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3439 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3440 | ||
3441 | default: | |
3442 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
3443 | "0x%x\n", signal_levels); | |
3444 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
3445 | } | |
3446 | } | |
3447 | ||
94223d04 | 3448 | void |
f4eb692e | 3449 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
f0a3424e PZ |
3450 | { |
3451 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 3452 | enum port port = intel_dig_port->port; |
f0a3424e | 3453 | struct drm_device *dev = intel_dig_port->base.base.dev; |
b905a915 | 3454 | struct drm_i915_private *dev_priv = to_i915(dev); |
f8896f5d | 3455 | uint32_t signal_levels, mask = 0; |
f0a3424e PZ |
3456 | uint8_t train_set = intel_dp->train_set[0]; |
3457 | ||
4f8036a2 | 3458 | if (HAS_DDI(dev_priv)) { |
f8896f5d DW |
3459 | signal_levels = ddi_signal_levels(intel_dp); |
3460 | ||
254e0931 | 3461 | if (IS_GEN9_LP(dev_priv)) |
f8896f5d DW |
3462 | signal_levels = 0; |
3463 | else | |
3464 | mask = DDI_BUF_EMP_MASK; | |
920a14b2 | 3465 | } else if (IS_CHERRYVIEW(dev_priv)) { |
5829975c | 3466 | signal_levels = chv_signal_levels(intel_dp); |
11a914c2 | 3467 | } else if (IS_VALLEYVIEW(dev_priv)) { |
5829975c | 3468 | signal_levels = vlv_signal_levels(intel_dp); |
5db94019 | 3469 | } else if (IS_GEN7(dev_priv) && port == PORT_A) { |
5829975c | 3470 | signal_levels = gen7_edp_signal_levels(train_set); |
f0a3424e | 3471 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
5db94019 | 3472 | } else if (IS_GEN6(dev_priv) && port == PORT_A) { |
5829975c | 3473 | signal_levels = gen6_edp_signal_levels(train_set); |
f0a3424e PZ |
3474 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3475 | } else { | |
5829975c | 3476 | signal_levels = gen4_signal_levels(train_set); |
f0a3424e PZ |
3477 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3478 | } | |
3479 | ||
96fb9f9b VK |
3480 | if (mask) |
3481 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
3482 | ||
3483 | DRM_DEBUG_KMS("Using vswing level %d\n", | |
3484 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); | |
3485 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", | |
3486 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
3487 | DP_TRAIN_PRE_EMPHASIS_SHIFT); | |
f0a3424e | 3488 | |
f4eb692e | 3489 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
b905a915 ACO |
3490 | |
3491 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
3492 | POSTING_READ(intel_dp->output_reg); | |
f0a3424e PZ |
3493 | } |
3494 | ||
94223d04 | 3495 | void |
e9c176d5 ACO |
3496 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
3497 | uint8_t dp_train_pat) | |
a4fc5ed6 | 3498 | { |
174edf1f | 3499 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
90a6b7b0 VS |
3500 | struct drm_i915_private *dev_priv = |
3501 | to_i915(intel_dig_port->base.base.dev); | |
a4fc5ed6 | 3502 | |
f4eb692e | 3503 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
47ea7542 | 3504 | |
f4eb692e | 3505 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
ea5b213a | 3506 | POSTING_READ(intel_dp->output_reg); |
e9c176d5 ACO |
3507 | } |
3508 | ||
94223d04 | 3509 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3ab9c637 ID |
3510 | { |
3511 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3512 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 3513 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ab9c637 ID |
3514 | enum port port = intel_dig_port->port; |
3515 | uint32_t val; | |
3516 | ||
4f8036a2 | 3517 | if (!HAS_DDI(dev_priv)) |
3ab9c637 ID |
3518 | return; |
3519 | ||
3520 | val = I915_READ(DP_TP_CTL(port)); | |
3521 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
3522 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
3523 | I915_WRITE(DP_TP_CTL(port), val); | |
3524 | ||
3525 | /* | |
3526 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
3527 | * we need to set idle transmission mode is to work around a HW issue | |
3528 | * where we enable the pipe while not in idle link-training mode. | |
3529 | * In this case there is requirement to wait for a minimum number of | |
3530 | * idle patterns to be sent. | |
3531 | */ | |
3532 | if (port == PORT_A) | |
3533 | return; | |
3534 | ||
a767017f CW |
3535 | if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port), |
3536 | DP_TP_STATUS_IDLE_DONE, | |
3537 | DP_TP_STATUS_IDLE_DONE, | |
3538 | 1)) | |
3ab9c637 ID |
3539 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
3540 | } | |
3541 | ||
a4fc5ed6 | 3542 | static void |
ea5b213a | 3543 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 3544 | { |
da63a9f2 | 3545 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1612c8bd | 3546 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
bc7d38a4 | 3547 | enum port port = intel_dig_port->port; |
da63a9f2 | 3548 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 3549 | struct drm_i915_private *dev_priv = to_i915(dev); |
ea5b213a | 3550 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 3551 | |
4f8036a2 | 3552 | if (WARN_ON(HAS_DDI(dev_priv))) |
c19b0669 PZ |
3553 | return; |
3554 | ||
0c33d8d7 | 3555 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
3556 | return; |
3557 | ||
28c97730 | 3558 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 3559 | |
5db94019 | 3560 | if ((IS_GEN7(dev_priv) && port == PORT_A) || |
6e266956 | 3561 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
e3421a18 | 3562 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1612c8bd | 3563 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
e3421a18 | 3564 | } else { |
920a14b2 | 3565 | if (IS_CHERRYVIEW(dev_priv)) |
aad3d14d VS |
3566 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
3567 | else | |
3568 | DP &= ~DP_LINK_TRAIN_MASK; | |
1612c8bd | 3569 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
e3421a18 | 3570 | } |
1612c8bd | 3571 | I915_WRITE(intel_dp->output_reg, DP); |
fe255d00 | 3572 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 3573 | |
1612c8bd VS |
3574 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3575 | I915_WRITE(intel_dp->output_reg, DP); | |
3576 | POSTING_READ(intel_dp->output_reg); | |
3577 | ||
3578 | /* | |
3579 | * HW workaround for IBX, we need to move the port | |
3580 | * to transcoder A after disabling it to allow the | |
3581 | * matching HDMI port to be enabled on transcoder A. | |
3582 | */ | |
6e266956 | 3583 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { |
0c241d5b VS |
3584 | /* |
3585 | * We get CPU/PCH FIFO underruns on the other pipe when | |
3586 | * doing the workaround. Sweep them under the rug. | |
3587 | */ | |
3588 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3589 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3590 | ||
1612c8bd VS |
3591 | /* always enable with pattern 1 (as per spec) */ |
3592 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); | |
3593 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; | |
3594 | I915_WRITE(intel_dp->output_reg, DP); | |
3595 | POSTING_READ(intel_dp->output_reg); | |
3596 | ||
3597 | DP &= ~DP_PORT_EN; | |
5bddd17f | 3598 | I915_WRITE(intel_dp->output_reg, DP); |
0ca09685 | 3599 | POSTING_READ(intel_dp->output_reg); |
0c241d5b | 3600 | |
0f0f74bc | 3601 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
3602 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
3603 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
5bddd17f EA |
3604 | } |
3605 | ||
f01eca2e | 3606 | msleep(intel_dp->panel_power_down_delay); |
6fec7662 VS |
3607 | |
3608 | intel_dp->DP = DP; | |
9f2bdb00 VS |
3609 | |
3610 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
3611 | pps_lock(intel_dp); | |
3612 | intel_dp->active_pipe = INVALID_PIPE; | |
3613 | pps_unlock(intel_dp); | |
3614 | } | |
a4fc5ed6 KP |
3615 | } |
3616 | ||
24e807e7 | 3617 | bool |
fe5a66f9 | 3618 | intel_dp_read_dpcd(struct intel_dp *intel_dp) |
92fd8fd1 | 3619 | { |
9f085ebb L |
3620 | if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3621 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 3622 | return false; /* aux transfer failed */ |
92fd8fd1 | 3623 | |
a8e98153 | 3624 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
577c7a50 | 3625 | |
fe5a66f9 VS |
3626 | return intel_dp->dpcd[DP_DPCD_REV] != 0; |
3627 | } | |
edb39244 | 3628 | |
fe5a66f9 VS |
3629 | static bool |
3630 | intel_edp_init_dpcd(struct intel_dp *intel_dp) | |
3631 | { | |
3632 | struct drm_i915_private *dev_priv = | |
3633 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
30d9aa42 | 3634 | |
fe5a66f9 VS |
3635 | /* this function is meant to be called only once */ |
3636 | WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); | |
30d9aa42 | 3637 | |
fe5a66f9 | 3638 | if (!intel_dp_read_dpcd(intel_dp)) |
30d9aa42 SS |
3639 | return false; |
3640 | ||
12a47a42 ID |
3641 | intel_dp_read_desc(intel_dp); |
3642 | ||
fe5a66f9 VS |
3643 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
3644 | dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
3645 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
474d1ec4 | 3646 | |
fe5a66f9 VS |
3647 | /* Check if the panel supports PSR */ |
3648 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, | |
3649 | intel_dp->psr_dpcd, | |
3650 | sizeof(intel_dp->psr_dpcd)); | |
3651 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { | |
3652 | dev_priv->psr.sink_support = true; | |
3653 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); | |
3654 | } | |
86ee27b5 | 3655 | |
fe5a66f9 VS |
3656 | if (INTEL_GEN(dev_priv) >= 9 && |
3657 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { | |
3658 | uint8_t frame_sync_cap; | |
3659 | ||
3660 | dev_priv->psr.sink_support = true; | |
3661 | drm_dp_dpcd_read(&intel_dp->aux, | |
3662 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, | |
3663 | &frame_sync_cap, 1); | |
3664 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; | |
3665 | /* PSR2 needs frame sync as well */ | |
3666 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; | |
3667 | DRM_DEBUG_KMS("PSR2 %s on sink", | |
3668 | dev_priv->psr.psr2_support ? "supported" : "not supported"); | |
97da2ef4 NV |
3669 | |
3670 | if (dev_priv->psr.psr2_support) { | |
3671 | dev_priv->psr.y_cord_support = | |
3672 | intel_dp_get_y_cord_status(intel_dp); | |
3673 | dev_priv->psr.colorimetry_support = | |
3674 | intel_dp_get_colorimetry_status(intel_dp); | |
340c93c0 NV |
3675 | dev_priv->psr.alpm = |
3676 | intel_dp_get_alpm_status(intel_dp); | |
97da2ef4 NV |
3677 | } |
3678 | ||
50003939 JN |
3679 | } |
3680 | ||
fe5a66f9 VS |
3681 | /* Read the eDP Display control capabilities registers */ |
3682 | if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && | |
3683 | drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, | |
f7170e2e DC |
3684 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == |
3685 | sizeof(intel_dp->edp_dpcd)) | |
fe5a66f9 VS |
3686 | DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), |
3687 | intel_dp->edp_dpcd); | |
06ea66b6 | 3688 | |
fc0f8e25 | 3689 | /* Intermediate frequency support */ |
fe5a66f9 | 3690 | if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */ |
94ca719e | 3691 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
ea2d8a42 VS |
3692 | int i; |
3693 | ||
9f085ebb L |
3694 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, |
3695 | sink_rates, sizeof(sink_rates)); | |
ea2d8a42 | 3696 | |
94ca719e VS |
3697 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
3698 | int val = le16_to_cpu(sink_rates[i]); | |
ea2d8a42 VS |
3699 | |
3700 | if (val == 0) | |
3701 | break; | |
3702 | ||
fd81c44e DP |
3703 | /* Value read multiplied by 200kHz gives the per-lane |
3704 | * link rate in kHz. The source rates are, however, | |
3705 | * stored in terms of LS_Clk kHz. The full conversion | |
3706 | * back to symbols is | |
3707 | * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) | |
3708 | */ | |
af77b974 | 3709 | intel_dp->sink_rates[i] = (val * 200) / 10; |
ea2d8a42 | 3710 | } |
94ca719e | 3711 | intel_dp->num_sink_rates = i; |
fc0f8e25 | 3712 | } |
0336400e | 3713 | |
fe5a66f9 VS |
3714 | return true; |
3715 | } | |
3716 | ||
3717 | ||
3718 | static bool | |
3719 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
3720 | { | |
3721 | if (!intel_dp_read_dpcd(intel_dp)) | |
3722 | return false; | |
3723 | ||
3724 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT, | |
3725 | &intel_dp->sink_count, 1) < 0) | |
3726 | return false; | |
3727 | ||
3728 | /* | |
3729 | * Sink count can change between short pulse hpd hence | |
3730 | * a member variable in intel_dp will track any changes | |
3731 | * between short pulse interrupts. | |
3732 | */ | |
3733 | intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count); | |
3734 | ||
3735 | /* | |
3736 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that | |
3737 | * a dongle is present but no display. Unless we require to know | |
3738 | * if a dongle is present or not, we don't need to update | |
3739 | * downstream port information. So, an early return here saves | |
3740 | * time from performing other operations which are not required. | |
3741 | */ | |
3742 | if (!is_edp(intel_dp) && !intel_dp->sink_count) | |
3743 | return false; | |
0336400e | 3744 | |
c726ad01 | 3745 | if (!drm_dp_is_branch(intel_dp->dpcd)) |
edb39244 AJ |
3746 | return true; /* native DP sink */ |
3747 | ||
3748 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
3749 | return true; /* no per-port downstream info */ | |
3750 | ||
9f085ebb L |
3751 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3752 | intel_dp->downstream_ports, | |
3753 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
3754 | return false; /* downstream port status fetch failed */ |
3755 | ||
3756 | return true; | |
92fd8fd1 KP |
3757 | } |
3758 | ||
0e32b39c | 3759 | static bool |
c4e3170a | 3760 | intel_dp_can_mst(struct intel_dp *intel_dp) |
0e32b39c DA |
3761 | { |
3762 | u8 buf[1]; | |
3763 | ||
7cc96139 NS |
3764 | if (!i915.enable_dp_mst) |
3765 | return false; | |
3766 | ||
0e32b39c DA |
3767 | if (!intel_dp->can_mst) |
3768 | return false; | |
3769 | ||
3770 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) | |
3771 | return false; | |
3772 | ||
c4e3170a VS |
3773 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1) |
3774 | return false; | |
0e32b39c | 3775 | |
c4e3170a VS |
3776 | return buf[0] & DP_MST_CAP; |
3777 | } | |
3778 | ||
3779 | static void | |
3780 | intel_dp_configure_mst(struct intel_dp *intel_dp) | |
3781 | { | |
3782 | if (!i915.enable_dp_mst) | |
3783 | return; | |
3784 | ||
3785 | if (!intel_dp->can_mst) | |
3786 | return; | |
3787 | ||
3788 | intel_dp->is_mst = intel_dp_can_mst(intel_dp); | |
3789 | ||
3790 | if (intel_dp->is_mst) | |
3791 | DRM_DEBUG_KMS("Sink is MST capable\n"); | |
3792 | else | |
3793 | DRM_DEBUG_KMS("Sink is not MST capable\n"); | |
3794 | ||
3795 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
3796 | intel_dp->is_mst); | |
0e32b39c DA |
3797 | } |
3798 | ||
e5a1cab5 | 3799 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
d2e216d0 | 3800 | { |
082dcc7c | 3801 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
0f0f74bc | 3802 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c | 3803 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
ad9dc91b | 3804 | u8 buf; |
e5a1cab5 | 3805 | int ret = 0; |
c6297843 RV |
3806 | int count = 0; |
3807 | int attempts = 10; | |
d2e216d0 | 3808 | |
082dcc7c RV |
3809 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
3810 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); | |
e5a1cab5 RV |
3811 | ret = -EIO; |
3812 | goto out; | |
4373f0f2 PZ |
3813 | } |
3814 | ||
082dcc7c | 3815 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
e5a1cab5 | 3816 | buf & ~DP_TEST_SINK_START) < 0) { |
082dcc7c | 3817 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
e5a1cab5 RV |
3818 | ret = -EIO; |
3819 | goto out; | |
3820 | } | |
d2e216d0 | 3821 | |
c6297843 | 3822 | do { |
0f0f74bc | 3823 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
c6297843 RV |
3824 | |
3825 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
3826 | DP_TEST_SINK_MISC, &buf) < 0) { | |
3827 | ret = -EIO; | |
3828 | goto out; | |
3829 | } | |
3830 | count = buf & DP_TEST_COUNT_MASK; | |
3831 | } while (--attempts && count); | |
3832 | ||
3833 | if (attempts == 0) { | |
dc5a9037 | 3834 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
c6297843 RV |
3835 | ret = -ETIMEDOUT; |
3836 | } | |
3837 | ||
e5a1cab5 | 3838 | out: |
082dcc7c | 3839 | hsw_enable_ips(intel_crtc); |
e5a1cab5 | 3840 | return ret; |
082dcc7c RV |
3841 | } |
3842 | ||
3843 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) | |
3844 | { | |
3845 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
0f0f74bc | 3846 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c RV |
3847 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3848 | u8 buf; | |
e5a1cab5 RV |
3849 | int ret; |
3850 | ||
082dcc7c RV |
3851 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
3852 | return -EIO; | |
3853 | ||
3854 | if (!(buf & DP_TEST_CRC_SUPPORTED)) | |
3855 | return -ENOTTY; | |
3856 | ||
3857 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) | |
3858 | return -EIO; | |
3859 | ||
6d8175da RV |
3860 | if (buf & DP_TEST_SINK_START) { |
3861 | ret = intel_dp_sink_crc_stop(intel_dp); | |
3862 | if (ret) | |
3863 | return ret; | |
3864 | } | |
3865 | ||
082dcc7c | 3866 | hsw_disable_ips(intel_crtc); |
1dda5f93 | 3867 | |
9d1a1031 | 3868 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
082dcc7c RV |
3869 | buf | DP_TEST_SINK_START) < 0) { |
3870 | hsw_enable_ips(intel_crtc); | |
3871 | return -EIO; | |
4373f0f2 PZ |
3872 | } |
3873 | ||
0f0f74bc | 3874 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
082dcc7c RV |
3875 | return 0; |
3876 | } | |
3877 | ||
3878 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) | |
3879 | { | |
3880 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
0f0f74bc | 3881 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c RV |
3882 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3883 | u8 buf; | |
621d4c76 | 3884 | int count, ret; |
082dcc7c | 3885 | int attempts = 6; |
082dcc7c RV |
3886 | |
3887 | ret = intel_dp_sink_crc_start(intel_dp); | |
3888 | if (ret) | |
3889 | return ret; | |
3890 | ||
ad9dc91b | 3891 | do { |
0f0f74bc | 3892 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
621d4c76 | 3893 | |
1dda5f93 | 3894 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4373f0f2 PZ |
3895 | DP_TEST_SINK_MISC, &buf) < 0) { |
3896 | ret = -EIO; | |
afe0d67e | 3897 | goto stop; |
4373f0f2 | 3898 | } |
621d4c76 | 3899 | count = buf & DP_TEST_COUNT_MASK; |
aabc95dc | 3900 | |
7e38eeff | 3901 | } while (--attempts && count == 0); |
ad9dc91b RV |
3902 | |
3903 | if (attempts == 0) { | |
7e38eeff RV |
3904 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
3905 | ret = -ETIMEDOUT; | |
3906 | goto stop; | |
3907 | } | |
3908 | ||
3909 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { | |
3910 | ret = -EIO; | |
3911 | goto stop; | |
ad9dc91b | 3912 | } |
d2e216d0 | 3913 | |
afe0d67e | 3914 | stop: |
082dcc7c | 3915 | intel_dp_sink_crc_stop(intel_dp); |
4373f0f2 | 3916 | return ret; |
d2e216d0 RV |
3917 | } |
3918 | ||
a60f0e38 JB |
3919 | static bool |
3920 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3921 | { | |
9f085ebb | 3922 | return drm_dp_dpcd_read(&intel_dp->aux, |
9d1a1031 JN |
3923 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
3924 | sink_irq_vector, 1) == 1; | |
a60f0e38 JB |
3925 | } |
3926 | ||
0e32b39c DA |
3927 | static bool |
3928 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3929 | { | |
3930 | int ret; | |
3931 | ||
9f085ebb | 3932 | ret = drm_dp_dpcd_read(&intel_dp->aux, |
0e32b39c DA |
3933 | DP_SINK_COUNT_ESI, |
3934 | sink_irq_vector, 14); | |
3935 | if (ret != 14) | |
3936 | return false; | |
3937 | ||
3938 | return true; | |
3939 | } | |
3940 | ||
c5d5ab7a TP |
3941 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
3942 | { | |
da15f7cb MN |
3943 | int status = 0; |
3944 | int min_lane_count = 1; | |
3945 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; | |
3946 | int link_rate_index, test_link_rate; | |
3947 | uint8_t test_lane_count, test_link_bw; | |
3948 | /* (DP CTS 1.2) | |
3949 | * 4.3.1.11 | |
3950 | */ | |
3951 | /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ | |
3952 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, | |
3953 | &test_lane_count); | |
3954 | ||
3955 | if (status <= 0) { | |
3956 | DRM_DEBUG_KMS("Lane count read failed\n"); | |
3957 | return DP_TEST_NAK; | |
3958 | } | |
3959 | test_lane_count &= DP_MAX_LANE_COUNT_MASK; | |
3960 | /* Validate the requested lane count */ | |
3961 | if (test_lane_count < min_lane_count || | |
3962 | test_lane_count > intel_dp->max_sink_lane_count) | |
3963 | return DP_TEST_NAK; | |
3964 | ||
3965 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, | |
3966 | &test_link_bw); | |
3967 | if (status <= 0) { | |
3968 | DRM_DEBUG_KMS("Link Rate read failed\n"); | |
3969 | return DP_TEST_NAK; | |
3970 | } | |
3971 | /* Validate the requested link rate */ | |
3972 | test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); | |
3973 | link_rate_index = intel_dp_link_rate_index(intel_dp, | |
3974 | common_rates, | |
3975 | test_link_rate); | |
3976 | if (link_rate_index < 0) | |
3977 | return DP_TEST_NAK; | |
3978 | ||
3979 | intel_dp->compliance.test_lane_count = test_lane_count; | |
3980 | intel_dp->compliance.test_link_rate = test_link_rate; | |
3981 | ||
3982 | return DP_TEST_ACK; | |
c5d5ab7a TP |
3983 | } |
3984 | ||
3985 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) | |
3986 | { | |
611032bf MN |
3987 | uint8_t test_pattern; |
3988 | uint16_t test_misc; | |
3989 | __be16 h_width, v_height; | |
3990 | int status = 0; | |
3991 | ||
3992 | /* Read the TEST_PATTERN (DP CTS 3.1.5) */ | |
3993 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_PATTERN, | |
3994 | &test_pattern, 1); | |
3995 | if (status <= 0) { | |
3996 | DRM_DEBUG_KMS("Test pattern read failed\n"); | |
3997 | return DP_TEST_NAK; | |
3998 | } | |
3999 | if (test_pattern != DP_COLOR_RAMP) | |
4000 | return DP_TEST_NAK; | |
4001 | ||
4002 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, | |
4003 | &h_width, 2); | |
4004 | if (status <= 0) { | |
4005 | DRM_DEBUG_KMS("H Width read failed\n"); | |
4006 | return DP_TEST_NAK; | |
4007 | } | |
4008 | ||
4009 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, | |
4010 | &v_height, 2); | |
4011 | if (status <= 0) { | |
4012 | DRM_DEBUG_KMS("V Height read failed\n"); | |
4013 | return DP_TEST_NAK; | |
4014 | } | |
4015 | ||
4016 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_MISC0, | |
4017 | &test_misc, 1); | |
4018 | if (status <= 0) { | |
4019 | DRM_DEBUG_KMS("TEST MISC read failed\n"); | |
4020 | return DP_TEST_NAK; | |
4021 | } | |
4022 | if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB) | |
4023 | return DP_TEST_NAK; | |
4024 | if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA) | |
4025 | return DP_TEST_NAK; | |
4026 | switch (test_misc & DP_TEST_BIT_DEPTH_MASK) { | |
4027 | case DP_TEST_BIT_DEPTH_6: | |
4028 | intel_dp->compliance.test_data.bpc = 6; | |
4029 | break; | |
4030 | case DP_TEST_BIT_DEPTH_8: | |
4031 | intel_dp->compliance.test_data.bpc = 8; | |
4032 | break; | |
4033 | default: | |
4034 | return DP_TEST_NAK; | |
4035 | } | |
4036 | ||
4037 | intel_dp->compliance.test_data.video_pattern = test_pattern; | |
4038 | intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); | |
4039 | intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); | |
4040 | /* Set test active flag here so userspace doesn't interrupt things */ | |
4041 | intel_dp->compliance.test_active = 1; | |
4042 | ||
4043 | return DP_TEST_ACK; | |
c5d5ab7a TP |
4044 | } |
4045 | ||
4046 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) | |
a60f0e38 | 4047 | { |
b48a5ba9 | 4048 | uint8_t test_result = DP_TEST_ACK; |
559be30c TP |
4049 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4050 | struct drm_connector *connector = &intel_connector->base; | |
4051 | ||
4052 | if (intel_connector->detect_edid == NULL || | |
ac6f2e29 | 4053 | connector->edid_corrupt || |
559be30c TP |
4054 | intel_dp->aux.i2c_defer_count > 6) { |
4055 | /* Check EDID read for NACKs, DEFERs and corruption | |
4056 | * (DP CTS 1.2 Core r1.1) | |
4057 | * 4.2.2.4 : Failed EDID read, I2C_NAK | |
4058 | * 4.2.2.5 : Failed EDID read, I2C_DEFER | |
4059 | * 4.2.2.6 : EDID corruption detected | |
4060 | * Use failsafe mode for all cases | |
4061 | */ | |
4062 | if (intel_dp->aux.i2c_nack_count > 0 || | |
4063 | intel_dp->aux.i2c_defer_count > 0) | |
4064 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", | |
4065 | intel_dp->aux.i2c_nack_count, | |
4066 | intel_dp->aux.i2c_defer_count); | |
c1617abc | 4067 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; |
559be30c | 4068 | } else { |
f79b468e TS |
4069 | struct edid *block = intel_connector->detect_edid; |
4070 | ||
4071 | /* We have to write the checksum | |
4072 | * of the last block read | |
4073 | */ | |
4074 | block += intel_connector->detect_edid->extensions; | |
4075 | ||
559be30c TP |
4076 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
4077 | DP_TEST_EDID_CHECKSUM, | |
f79b468e | 4078 | &block->checksum, |
5a1cc655 | 4079 | 1)) |
559be30c TP |
4080 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
4081 | ||
4082 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; | |
b48a5ba9 | 4083 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; |
559be30c TP |
4084 | } |
4085 | ||
4086 | /* Set test active flag here so userspace doesn't interrupt things */ | |
c1617abc | 4087 | intel_dp->compliance.test_active = 1; |
559be30c | 4088 | |
c5d5ab7a TP |
4089 | return test_result; |
4090 | } | |
4091 | ||
4092 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) | |
a60f0e38 | 4093 | { |
c5d5ab7a TP |
4094 | uint8_t test_result = DP_TEST_NAK; |
4095 | return test_result; | |
4096 | } | |
4097 | ||
4098 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
4099 | { | |
4100 | uint8_t response = DP_TEST_NAK; | |
5ec63bbd JN |
4101 | uint8_t request = 0; |
4102 | int status; | |
c5d5ab7a | 4103 | |
5ec63bbd | 4104 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); |
c5d5ab7a TP |
4105 | if (status <= 0) { |
4106 | DRM_DEBUG_KMS("Could not read test request from sink\n"); | |
4107 | goto update_status; | |
4108 | } | |
4109 | ||
5ec63bbd | 4110 | switch (request) { |
c5d5ab7a TP |
4111 | case DP_TEST_LINK_TRAINING: |
4112 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); | |
c5d5ab7a TP |
4113 | response = intel_dp_autotest_link_training(intel_dp); |
4114 | break; | |
4115 | case DP_TEST_LINK_VIDEO_PATTERN: | |
4116 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); | |
c5d5ab7a TP |
4117 | response = intel_dp_autotest_video_pattern(intel_dp); |
4118 | break; | |
4119 | case DP_TEST_LINK_EDID_READ: | |
4120 | DRM_DEBUG_KMS("EDID test requested\n"); | |
c5d5ab7a TP |
4121 | response = intel_dp_autotest_edid(intel_dp); |
4122 | break; | |
4123 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
4124 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); | |
c5d5ab7a TP |
4125 | response = intel_dp_autotest_phy_pattern(intel_dp); |
4126 | break; | |
4127 | default: | |
5ec63bbd | 4128 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", request); |
c5d5ab7a TP |
4129 | break; |
4130 | } | |
4131 | ||
5ec63bbd JN |
4132 | if (response & DP_TEST_ACK) |
4133 | intel_dp->compliance.test_type = request; | |
4134 | ||
c5d5ab7a | 4135 | update_status: |
5ec63bbd | 4136 | status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); |
c5d5ab7a TP |
4137 | if (status <= 0) |
4138 | DRM_DEBUG_KMS("Could not write test response to sink\n"); | |
a60f0e38 JB |
4139 | } |
4140 | ||
0e32b39c DA |
4141 | static int |
4142 | intel_dp_check_mst_status(struct intel_dp *intel_dp) | |
4143 | { | |
4144 | bool bret; | |
4145 | ||
4146 | if (intel_dp->is_mst) { | |
4147 | u8 esi[16] = { 0 }; | |
4148 | int ret = 0; | |
4149 | int retry; | |
4150 | bool handled; | |
4151 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
4152 | go_again: | |
4153 | if (bret == true) { | |
4154 | ||
4155 | /* check link status - esi[10] = 0x200c */ | |
19e0b4ca | 4156 | if (intel_dp->active_mst_links && |
901c2daf | 4157 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
0e32b39c DA |
4158 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
4159 | intel_dp_start_link_train(intel_dp); | |
0e32b39c DA |
4160 | intel_dp_stop_link_train(intel_dp); |
4161 | } | |
4162 | ||
6f34cc39 | 4163 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
0e32b39c DA |
4164 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
4165 | ||
4166 | if (handled) { | |
4167 | for (retry = 0; retry < 3; retry++) { | |
4168 | int wret; | |
4169 | wret = drm_dp_dpcd_write(&intel_dp->aux, | |
4170 | DP_SINK_COUNT_ESI+1, | |
4171 | &esi[1], 3); | |
4172 | if (wret == 3) { | |
4173 | break; | |
4174 | } | |
4175 | } | |
4176 | ||
4177 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
4178 | if (bret == true) { | |
6f34cc39 | 4179 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
0e32b39c DA |
4180 | goto go_again; |
4181 | } | |
4182 | } else | |
4183 | ret = 0; | |
4184 | ||
4185 | return ret; | |
4186 | } else { | |
4187 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4188 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); | |
4189 | intel_dp->is_mst = false; | |
4190 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
4191 | /* send a hotplug event */ | |
4192 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); | |
4193 | } | |
4194 | } | |
4195 | return -EINVAL; | |
4196 | } | |
4197 | ||
bfd02b3c VS |
4198 | static void |
4199 | intel_dp_retrain_link(struct intel_dp *intel_dp) | |
4200 | { | |
4201 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; | |
4202 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
4203 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
4204 | ||
4205 | /* Suppress underruns caused by re-training */ | |
4206 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); | |
4207 | if (crtc->config->has_pch_encoder) | |
4208 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
4209 | intel_crtc_pch_transcoder(crtc), false); | |
4210 | ||
4211 | intel_dp_start_link_train(intel_dp); | |
4212 | intel_dp_stop_link_train(intel_dp); | |
4213 | ||
4214 | /* Keep underrun reporting disabled until things are stable */ | |
0f0f74bc | 4215 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
bfd02b3c VS |
4216 | |
4217 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); | |
4218 | if (crtc->config->has_pch_encoder) | |
4219 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
4220 | intel_crtc_pch_transcoder(crtc), true); | |
4221 | } | |
4222 | ||
5c9114d0 SS |
4223 | static void |
4224 | intel_dp_check_link_status(struct intel_dp *intel_dp) | |
4225 | { | |
4226 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; | |
4227 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
4228 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
4229 | ||
4230 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
4231 | ||
4232 | if (!intel_dp_get_link_status(intel_dp, link_status)) { | |
4233 | DRM_ERROR("Failed to get link status\n"); | |
4234 | return; | |
4235 | } | |
4236 | ||
4237 | if (!intel_encoder->base.crtc) | |
4238 | return; | |
4239 | ||
4240 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) | |
4241 | return; | |
4242 | ||
d4cb3fd9 | 4243 | /* FIXME: we need to synchronize this sort of stuff with hardware |
2dd85aeb DV |
4244 | * readout. Currently fast link training doesn't work on boot-up. */ |
4245 | if (!intel_dp->lane_count) | |
d4cb3fd9 MA |
4246 | return; |
4247 | ||
da15f7cb MN |
4248 | /* Retrain if Channel EQ or CR not ok */ |
4249 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { | |
5c9114d0 SS |
4250 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
4251 | intel_encoder->base.name); | |
bfd02b3c VS |
4252 | |
4253 | intel_dp_retrain_link(intel_dp); | |
5c9114d0 SS |
4254 | } |
4255 | } | |
4256 | ||
a4fc5ed6 KP |
4257 | /* |
4258 | * According to DP spec | |
4259 | * 5.1.2: | |
4260 | * 1. Read DPCD | |
4261 | * 2. Configure link according to Receiver Capabilities | |
4262 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
4263 | * 4. Check link status on receipt of hot-plug interrupt | |
39ff747b SS |
4264 | * |
4265 | * intel_dp_short_pulse - handles short pulse interrupts | |
4266 | * when full detection is not required. | |
4267 | * Returns %true if short pulse is handled and full detection | |
4268 | * is NOT required and %false otherwise. | |
a4fc5ed6 | 4269 | */ |
39ff747b | 4270 | static bool |
5c9114d0 | 4271 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
a4fc5ed6 | 4272 | { |
5b215bcf | 4273 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
da15f7cb | 4274 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
65fbb4e7 | 4275 | u8 sink_irq_vector = 0; |
39ff747b SS |
4276 | u8 old_sink_count = intel_dp->sink_count; |
4277 | bool ret; | |
5b215bcf | 4278 | |
4df6960e SS |
4279 | /* |
4280 | * Clearing compliance test variables to allow capturing | |
4281 | * of values for next automated test request. | |
4282 | */ | |
c1617abc | 4283 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
4df6960e | 4284 | |
39ff747b SS |
4285 | /* |
4286 | * Now read the DPCD to see if it's actually running | |
4287 | * If the current value of sink count doesn't match with | |
4288 | * the value that was stored earlier or dpcd read failed | |
4289 | * we need to do full detection | |
4290 | */ | |
4291 | ret = intel_dp_get_dpcd(intel_dp); | |
4292 | ||
4293 | if ((old_sink_count != intel_dp->sink_count) || !ret) { | |
4294 | /* No need to proceed if we are going to do full detect */ | |
4295 | return false; | |
59cd09e1 JB |
4296 | } |
4297 | ||
a60f0e38 JB |
4298 | /* Try to read the source of the interrupt */ |
4299 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
4300 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
4301 | sink_irq_vector != 0) { | |
a60f0e38 | 4302 | /* Clear interrupt source */ |
9d1a1031 JN |
4303 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4304 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4305 | sink_irq_vector); | |
a60f0e38 JB |
4306 | |
4307 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
da15f7cb | 4308 | intel_dp_handle_test_request(intel_dp); |
a60f0e38 JB |
4309 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4310 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4311 | } | |
4312 | ||
5c9114d0 SS |
4313 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
4314 | intel_dp_check_link_status(intel_dp); | |
4315 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
da15f7cb MN |
4316 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { |
4317 | DRM_DEBUG_KMS("Link Training Compliance Test requested\n"); | |
4318 | /* Send a Hotplug Uevent to userspace to start modeset */ | |
4319 | drm_kms_helper_hotplug_event(intel_encoder->base.dev); | |
4320 | } | |
39ff747b SS |
4321 | |
4322 | return true; | |
a4fc5ed6 | 4323 | } |
a4fc5ed6 | 4324 | |
caf9ab24 | 4325 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 4326 | static enum drm_connector_status |
26d61aad | 4327 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 4328 | { |
caf9ab24 | 4329 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
4330 | uint8_t type; |
4331 | ||
4332 | if (!intel_dp_get_dpcd(intel_dp)) | |
4333 | return connector_status_disconnected; | |
4334 | ||
1034ce70 SS |
4335 | if (is_edp(intel_dp)) |
4336 | return connector_status_connected; | |
4337 | ||
caf9ab24 | 4338 | /* if there's no downstream port, we're done */ |
c726ad01 | 4339 | if (!drm_dp_is_branch(dpcd)) |
26d61aad | 4340 | return connector_status_connected; |
caf9ab24 AJ |
4341 | |
4342 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
4343 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4344 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
9d1a1031 | 4345 | |
30d9aa42 SS |
4346 | return intel_dp->sink_count ? |
4347 | connector_status_connected : connector_status_disconnected; | |
caf9ab24 AJ |
4348 | } |
4349 | ||
c4e3170a VS |
4350 | if (intel_dp_can_mst(intel_dp)) |
4351 | return connector_status_connected; | |
4352 | ||
caf9ab24 | 4353 | /* If no HPD, poke DDC gently */ |
0b99836f | 4354 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 4355 | return connector_status_connected; |
caf9ab24 AJ |
4356 | |
4357 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
4358 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4359 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
4360 | if (type == DP_DS_PORT_TYPE_VGA || | |
4361 | type == DP_DS_PORT_TYPE_NON_EDID) | |
4362 | return connector_status_unknown; | |
4363 | } else { | |
4364 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
4365 | DP_DWN_STRM_PORT_TYPE_MASK; | |
4366 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
4367 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
4368 | return connector_status_unknown; | |
4369 | } | |
caf9ab24 AJ |
4370 | |
4371 | /* Anything else is out of spec, warn and ignore */ | |
4372 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 4373 | return connector_status_disconnected; |
71ba9000 AJ |
4374 | } |
4375 | ||
d410b56d CW |
4376 | static enum drm_connector_status |
4377 | edp_detect(struct intel_dp *intel_dp) | |
4378 | { | |
4379 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1650be74 | 4380 | struct drm_i915_private *dev_priv = to_i915(dev); |
d410b56d CW |
4381 | enum drm_connector_status status; |
4382 | ||
1650be74 | 4383 | status = intel_panel_detect(dev_priv); |
d410b56d CW |
4384 | if (status == connector_status_unknown) |
4385 | status = connector_status_connected; | |
4386 | ||
4387 | return status; | |
4388 | } | |
4389 | ||
b93433cc JN |
4390 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
4391 | struct intel_digital_port *port) | |
5eb08b69 | 4392 | { |
b93433cc | 4393 | u32 bit; |
01cb9ea6 | 4394 | |
0df53b77 JN |
4395 | switch (port->port) { |
4396 | case PORT_A: | |
4397 | return true; | |
4398 | case PORT_B: | |
4399 | bit = SDE_PORTB_HOTPLUG; | |
4400 | break; | |
4401 | case PORT_C: | |
4402 | bit = SDE_PORTC_HOTPLUG; | |
4403 | break; | |
4404 | case PORT_D: | |
4405 | bit = SDE_PORTD_HOTPLUG; | |
4406 | break; | |
4407 | default: | |
4408 | MISSING_CASE(port->port); | |
4409 | return false; | |
4410 | } | |
4411 | ||
4412 | return I915_READ(SDEISR) & bit; | |
4413 | } | |
4414 | ||
4415 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, | |
4416 | struct intel_digital_port *port) | |
4417 | { | |
4418 | u32 bit; | |
4419 | ||
4420 | switch (port->port) { | |
4421 | case PORT_A: | |
4422 | return true; | |
4423 | case PORT_B: | |
4424 | bit = SDE_PORTB_HOTPLUG_CPT; | |
4425 | break; | |
4426 | case PORT_C: | |
4427 | bit = SDE_PORTC_HOTPLUG_CPT; | |
4428 | break; | |
4429 | case PORT_D: | |
4430 | bit = SDE_PORTD_HOTPLUG_CPT; | |
4431 | break; | |
a78695d3 JN |
4432 | case PORT_E: |
4433 | bit = SDE_PORTE_HOTPLUG_SPT; | |
4434 | break; | |
0df53b77 JN |
4435 | default: |
4436 | MISSING_CASE(port->port); | |
4437 | return false; | |
b93433cc | 4438 | } |
1b469639 | 4439 | |
b93433cc | 4440 | return I915_READ(SDEISR) & bit; |
5eb08b69 ZW |
4441 | } |
4442 | ||
7e66bcf2 | 4443 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
1d245987 | 4444 | struct intel_digital_port *port) |
a4fc5ed6 | 4445 | { |
9642c81c | 4446 | u32 bit; |
5eb08b69 | 4447 | |
9642c81c JN |
4448 | switch (port->port) { |
4449 | case PORT_B: | |
4450 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; | |
4451 | break; | |
4452 | case PORT_C: | |
4453 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; | |
4454 | break; | |
4455 | case PORT_D: | |
4456 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | |
4457 | break; | |
4458 | default: | |
4459 | MISSING_CASE(port->port); | |
4460 | return false; | |
4461 | } | |
4462 | ||
4463 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
4464 | } | |
4465 | ||
0780cd36 VS |
4466 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
4467 | struct intel_digital_port *port) | |
9642c81c JN |
4468 | { |
4469 | u32 bit; | |
4470 | ||
4471 | switch (port->port) { | |
4472 | case PORT_B: | |
0780cd36 | 4473 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4474 | break; |
4475 | case PORT_C: | |
0780cd36 | 4476 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4477 | break; |
4478 | case PORT_D: | |
0780cd36 | 4479 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4480 | break; |
4481 | default: | |
4482 | MISSING_CASE(port->port); | |
4483 | return false; | |
a4fc5ed6 KP |
4484 | } |
4485 | ||
1d245987 | 4486 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
2a592bec DA |
4487 | } |
4488 | ||
e464bfde | 4489 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
e2ec35a5 | 4490 | struct intel_digital_port *intel_dig_port) |
e464bfde | 4491 | { |
e2ec35a5 SJ |
4492 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4493 | enum port port; | |
e464bfde JN |
4494 | u32 bit; |
4495 | ||
e2ec35a5 SJ |
4496 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
4497 | switch (port) { | |
e464bfde JN |
4498 | case PORT_A: |
4499 | bit = BXT_DE_PORT_HP_DDIA; | |
4500 | break; | |
4501 | case PORT_B: | |
4502 | bit = BXT_DE_PORT_HP_DDIB; | |
4503 | break; | |
4504 | case PORT_C: | |
4505 | bit = BXT_DE_PORT_HP_DDIC; | |
4506 | break; | |
4507 | default: | |
e2ec35a5 | 4508 | MISSING_CASE(port); |
e464bfde JN |
4509 | return false; |
4510 | } | |
4511 | ||
4512 | return I915_READ(GEN8_DE_PORT_ISR) & bit; | |
4513 | } | |
4514 | ||
7e66bcf2 JN |
4515 | /* |
4516 | * intel_digital_port_connected - is the specified port connected? | |
4517 | * @dev_priv: i915 private structure | |
4518 | * @port: the port to test | |
4519 | * | |
4520 | * Return %true if @port is connected, %false otherwise. | |
4521 | */ | |
23f889bd | 4522 | static bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
7e66bcf2 JN |
4523 | struct intel_digital_port *port) |
4524 | { | |
0df53b77 | 4525 | if (HAS_PCH_IBX(dev_priv)) |
7e66bcf2 | 4526 | return ibx_digital_port_connected(dev_priv, port); |
22824fac | 4527 | else if (HAS_PCH_SPLIT(dev_priv)) |
0df53b77 | 4528 | return cpt_digital_port_connected(dev_priv, port); |
cc3f90f0 | 4529 | else if (IS_GEN9_LP(dev_priv)) |
e464bfde | 4530 | return bxt_digital_port_connected(dev_priv, port); |
0780cd36 VS |
4531 | else if (IS_GM45(dev_priv)) |
4532 | return gm45_digital_port_connected(dev_priv, port); | |
7e66bcf2 JN |
4533 | else |
4534 | return g4x_digital_port_connected(dev_priv, port); | |
4535 | } | |
4536 | ||
8c241fef | 4537 | static struct edid * |
beb60608 | 4538 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 4539 | { |
beb60608 | 4540 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
d6f24d0f | 4541 | |
9cd300e0 JN |
4542 | /* use cached edid if we have one */ |
4543 | if (intel_connector->edid) { | |
9cd300e0 JN |
4544 | /* invalid edid */ |
4545 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
4546 | return NULL; |
4547 | ||
55e9edeb | 4548 | return drm_edid_duplicate(intel_connector->edid); |
beb60608 CW |
4549 | } else |
4550 | return drm_get_edid(&intel_connector->base, | |
4551 | &intel_dp->aux.ddc); | |
4552 | } | |
8c241fef | 4553 | |
beb60608 CW |
4554 | static void |
4555 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
4556 | { | |
4557 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
4558 | struct edid *edid; | |
8c241fef | 4559 | |
f21a2198 | 4560 | intel_dp_unset_edid(intel_dp); |
beb60608 CW |
4561 | edid = intel_dp_get_edid(intel_dp); |
4562 | intel_connector->detect_edid = edid; | |
4563 | ||
4564 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) | |
4565 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; | |
4566 | else | |
4567 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
8c241fef KP |
4568 | } |
4569 | ||
beb60608 CW |
4570 | static void |
4571 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 4572 | { |
beb60608 | 4573 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8c241fef | 4574 | |
beb60608 CW |
4575 | kfree(intel_connector->detect_edid); |
4576 | intel_connector->detect_edid = NULL; | |
9cd300e0 | 4577 | |
beb60608 CW |
4578 | intel_dp->has_audio = false; |
4579 | } | |
d6f24d0f | 4580 | |
5cb651a7 | 4581 | static enum drm_connector_status |
f21a2198 | 4582 | intel_dp_long_pulse(struct intel_connector *intel_connector) |
a9756bb5 | 4583 | { |
f21a2198 | 4584 | struct drm_connector *connector = &intel_connector->base; |
a9756bb5 | 4585 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
d63885da PZ |
4586 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4587 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 4588 | struct drm_device *dev = connector->dev; |
a9756bb5 | 4589 | enum drm_connector_status status; |
671dedd2 | 4590 | enum intel_display_power_domain power_domain; |
65fbb4e7 | 4591 | u8 sink_irq_vector = 0; |
a9756bb5 | 4592 | |
25f78f58 VS |
4593 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4594 | intel_display_power_get(to_i915(dev), power_domain); | |
a9756bb5 | 4595 | |
d410b56d CW |
4596 | /* Can't disconnect eDP, but you can close the lid... */ |
4597 | if (is_edp(intel_dp)) | |
4598 | status = edp_detect(intel_dp); | |
c555a81d ACO |
4599 | else if (intel_digital_port_connected(to_i915(dev), |
4600 | dp_to_dig_port(intel_dp))) | |
4601 | status = intel_dp_detect_dpcd(intel_dp); | |
a9756bb5 | 4602 | else |
c555a81d ACO |
4603 | status = connector_status_disconnected; |
4604 | ||
5cb651a7 | 4605 | if (status == connector_status_disconnected) { |
c1617abc | 4606 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
4df6960e | 4607 | |
0e505a08 | 4608 | if (intel_dp->is_mst) { |
4609 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4610 | intel_dp->is_mst, | |
4611 | intel_dp->mst_mgr.mst_state); | |
4612 | intel_dp->is_mst = false; | |
4613 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4614 | intel_dp->is_mst); | |
4615 | } | |
4616 | ||
c8c8fb33 | 4617 | goto out; |
4df6960e | 4618 | } |
a9756bb5 | 4619 | |
f21a2198 | 4620 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
cca0502b | 4621 | intel_encoder->type = INTEL_OUTPUT_DP; |
f21a2198 | 4622 | |
fe5a66f9 VS |
4623 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
4624 | yesno(intel_dp_source_supports_hbr2(intel_dp)), | |
4625 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); | |
4626 | ||
f482984a MN |
4627 | /* Set the max lane count for sink */ |
4628 | intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); | |
4629 | ||
4630 | /* Set the max link BW for sink */ | |
4631 | intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp); | |
4632 | ||
fe5a66f9 VS |
4633 | intel_dp_print_rates(intel_dp); |
4634 | ||
7b3fc170 | 4635 | intel_dp_read_desc(intel_dp); |
0e390a33 | 4636 | |
c4e3170a VS |
4637 | intel_dp_configure_mst(intel_dp); |
4638 | ||
4639 | if (intel_dp->is_mst) { | |
f21a2198 SS |
4640 | /* |
4641 | * If we are in MST mode then this connector | |
4642 | * won't appear connected or have anything | |
4643 | * with EDID on it | |
4644 | */ | |
0e32b39c DA |
4645 | status = connector_status_disconnected; |
4646 | goto out; | |
7d23e3c3 SS |
4647 | } else if (connector->status == connector_status_connected) { |
4648 | /* | |
4649 | * If display was connected already and is still connected | |
4650 | * check links status, there has been known issues of | |
4651 | * link loss triggerring long pulse!!!! | |
4652 | */ | |
4653 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); | |
4654 | intel_dp_check_link_status(intel_dp); | |
4655 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
4656 | goto out; | |
0e32b39c DA |
4657 | } |
4658 | ||
4df6960e SS |
4659 | /* |
4660 | * Clearing NACK and defer counts to get their exact values | |
4661 | * while reading EDID which are required by Compliance tests | |
4662 | * 4.2.2.4 and 4.2.2.5 | |
4663 | */ | |
4664 | intel_dp->aux.i2c_nack_count = 0; | |
4665 | intel_dp->aux.i2c_defer_count = 0; | |
4666 | ||
beb60608 | 4667 | intel_dp_set_edid(intel_dp); |
5cb651a7 VS |
4668 | if (is_edp(intel_dp) || intel_connector->detect_edid) |
4669 | status = connector_status_connected; | |
7d23e3c3 | 4670 | intel_dp->detect_done = true; |
c8c8fb33 | 4671 | |
09b1eb13 TP |
4672 | /* Try to read the source of the interrupt */ |
4673 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
4674 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
4675 | sink_irq_vector != 0) { | |
09b1eb13 TP |
4676 | /* Clear interrupt source */ |
4677 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
4678 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4679 | sink_irq_vector); | |
4680 | ||
4681 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
4682 | intel_dp_handle_test_request(intel_dp); | |
4683 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
4684 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4685 | } | |
4686 | ||
c8c8fb33 | 4687 | out: |
5cb651a7 | 4688 | if (status != connector_status_connected && !intel_dp->is_mst) |
f21a2198 | 4689 | intel_dp_unset_edid(intel_dp); |
7d23e3c3 | 4690 | |
25f78f58 | 4691 | intel_display_power_put(to_i915(dev), power_domain); |
5cb651a7 | 4692 | return status; |
f21a2198 SS |
4693 | } |
4694 | ||
4695 | static enum drm_connector_status | |
4696 | intel_dp_detect(struct drm_connector *connector, bool force) | |
4697 | { | |
4698 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
5cb651a7 | 4699 | enum drm_connector_status status = connector->status; |
f21a2198 SS |
4700 | |
4701 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4702 | connector->base.id, connector->name); | |
4703 | ||
7d23e3c3 SS |
4704 | /* If full detect is not performed yet, do a full detect */ |
4705 | if (!intel_dp->detect_done) | |
5cb651a7 | 4706 | status = intel_dp_long_pulse(intel_dp->attached_connector); |
7d23e3c3 SS |
4707 | |
4708 | intel_dp->detect_done = false; | |
f21a2198 | 4709 | |
5cb651a7 | 4710 | return status; |
a4fc5ed6 KP |
4711 | } |
4712 | ||
beb60608 CW |
4713 | static void |
4714 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 4715 | { |
df0e9248 | 4716 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
beb60608 | 4717 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
25f78f58 | 4718 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
671dedd2 | 4719 | enum intel_display_power_domain power_domain; |
a4fc5ed6 | 4720 | |
beb60608 CW |
4721 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4722 | connector->base.id, connector->name); | |
4723 | intel_dp_unset_edid(intel_dp); | |
a4fc5ed6 | 4724 | |
beb60608 CW |
4725 | if (connector->status != connector_status_connected) |
4726 | return; | |
671dedd2 | 4727 | |
25f78f58 VS |
4728 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4729 | intel_display_power_get(dev_priv, power_domain); | |
beb60608 CW |
4730 | |
4731 | intel_dp_set_edid(intel_dp); | |
4732 | ||
25f78f58 | 4733 | intel_display_power_put(dev_priv, power_domain); |
beb60608 CW |
4734 | |
4735 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
cca0502b | 4736 | intel_encoder->type = INTEL_OUTPUT_DP; |
beb60608 CW |
4737 | } |
4738 | ||
4739 | static int intel_dp_get_modes(struct drm_connector *connector) | |
4740 | { | |
4741 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4742 | struct edid *edid; | |
4743 | ||
4744 | edid = intel_connector->detect_edid; | |
4745 | if (edid) { | |
4746 | int ret = intel_connector_update_modes(connector, edid); | |
4747 | if (ret) | |
4748 | return ret; | |
4749 | } | |
32f9d658 | 4750 | |
f8779fda | 4751 | /* if eDP has no EDID, fall back to fixed mode */ |
beb60608 CW |
4752 | if (is_edp(intel_attached_dp(connector)) && |
4753 | intel_connector->panel.fixed_mode) { | |
f8779fda | 4754 | struct drm_display_mode *mode; |
beb60608 CW |
4755 | |
4756 | mode = drm_mode_duplicate(connector->dev, | |
dd06f90e | 4757 | intel_connector->panel.fixed_mode); |
f8779fda | 4758 | if (mode) { |
32f9d658 ZW |
4759 | drm_mode_probed_add(connector, mode); |
4760 | return 1; | |
4761 | } | |
4762 | } | |
beb60608 | 4763 | |
32f9d658 | 4764 | return 0; |
a4fc5ed6 KP |
4765 | } |
4766 | ||
1aad7ac0 CW |
4767 | static bool |
4768 | intel_dp_detect_audio(struct drm_connector *connector) | |
4769 | { | |
1aad7ac0 | 4770 | bool has_audio = false; |
beb60608 | 4771 | struct edid *edid; |
1aad7ac0 | 4772 | |
beb60608 CW |
4773 | edid = to_intel_connector(connector)->detect_edid; |
4774 | if (edid) | |
1aad7ac0 | 4775 | has_audio = drm_detect_monitor_audio(edid); |
671dedd2 | 4776 | |
1aad7ac0 CW |
4777 | return has_audio; |
4778 | } | |
4779 | ||
f684960e CW |
4780 | static int |
4781 | intel_dp_set_property(struct drm_connector *connector, | |
4782 | struct drm_property *property, | |
4783 | uint64_t val) | |
4784 | { | |
fac5e23e | 4785 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
53b41837 | 4786 | struct intel_connector *intel_connector = to_intel_connector(connector); |
da63a9f2 PZ |
4787 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
4788 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
f684960e CW |
4789 | int ret; |
4790 | ||
662595df | 4791 | ret = drm_object_property_set_value(&connector->base, property, val); |
f684960e CW |
4792 | if (ret) |
4793 | return ret; | |
4794 | ||
3f43c48d | 4795 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
4796 | int i = val; |
4797 | bool has_audio; | |
4798 | ||
4799 | if (i == intel_dp->force_audio) | |
f684960e CW |
4800 | return 0; |
4801 | ||
1aad7ac0 | 4802 | intel_dp->force_audio = i; |
f684960e | 4803 | |
c3e5f67b | 4804 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
4805 | has_audio = intel_dp_detect_audio(connector); |
4806 | else | |
c3e5f67b | 4807 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
4808 | |
4809 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
4810 | return 0; |
4811 | ||
1aad7ac0 | 4812 | intel_dp->has_audio = has_audio; |
f684960e CW |
4813 | goto done; |
4814 | } | |
4815 | ||
e953fd7b | 4816 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 | 4817 | bool old_auto = intel_dp->color_range_auto; |
0f2a2a75 | 4818 | bool old_range = intel_dp->limited_color_range; |
ae4edb80 | 4819 | |
55bc60db VS |
4820 | switch (val) { |
4821 | case INTEL_BROADCAST_RGB_AUTO: | |
4822 | intel_dp->color_range_auto = true; | |
4823 | break; | |
4824 | case INTEL_BROADCAST_RGB_FULL: | |
4825 | intel_dp->color_range_auto = false; | |
0f2a2a75 | 4826 | intel_dp->limited_color_range = false; |
55bc60db VS |
4827 | break; |
4828 | case INTEL_BROADCAST_RGB_LIMITED: | |
4829 | intel_dp->color_range_auto = false; | |
0f2a2a75 | 4830 | intel_dp->limited_color_range = true; |
55bc60db VS |
4831 | break; |
4832 | default: | |
4833 | return -EINVAL; | |
4834 | } | |
ae4edb80 DV |
4835 | |
4836 | if (old_auto == intel_dp->color_range_auto && | |
0f2a2a75 | 4837 | old_range == intel_dp->limited_color_range) |
ae4edb80 DV |
4838 | return 0; |
4839 | ||
e953fd7b CW |
4840 | goto done; |
4841 | } | |
4842 | ||
53b41837 YN |
4843 | if (is_edp(intel_dp) && |
4844 | property == connector->dev->mode_config.scaling_mode_property) { | |
4845 | if (val == DRM_MODE_SCALE_NONE) { | |
4846 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
4847 | return -EINVAL; | |
4848 | } | |
234126c6 VS |
4849 | if (HAS_GMCH_DISPLAY(dev_priv) && |
4850 | val == DRM_MODE_SCALE_CENTER) { | |
4851 | DRM_DEBUG_KMS("centering not supported\n"); | |
4852 | return -EINVAL; | |
4853 | } | |
53b41837 YN |
4854 | |
4855 | if (intel_connector->panel.fitting_mode == val) { | |
4856 | /* the eDP scaling property is not changed */ | |
4857 | return 0; | |
4858 | } | |
4859 | intel_connector->panel.fitting_mode = val; | |
4860 | ||
4861 | goto done; | |
4862 | } | |
4863 | ||
f684960e CW |
4864 | return -EINVAL; |
4865 | ||
4866 | done: | |
c0c36b94 CW |
4867 | if (intel_encoder->base.crtc) |
4868 | intel_crtc_restore_mode(intel_encoder->base.crtc); | |
f684960e CW |
4869 | |
4870 | return 0; | |
4871 | } | |
4872 | ||
7a418e34 CW |
4873 | static int |
4874 | intel_dp_connector_register(struct drm_connector *connector) | |
4875 | { | |
4876 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1ebaa0b9 CW |
4877 | int ret; |
4878 | ||
4879 | ret = intel_connector_register(connector); | |
4880 | if (ret) | |
4881 | return ret; | |
7a418e34 CW |
4882 | |
4883 | i915_debugfs_connector_add(connector); | |
4884 | ||
4885 | DRM_DEBUG_KMS("registering %s bus for %s\n", | |
4886 | intel_dp->aux.name, connector->kdev->kobj.name); | |
4887 | ||
4888 | intel_dp->aux.dev = connector->kdev; | |
4889 | return drm_dp_aux_register(&intel_dp->aux); | |
4890 | } | |
4891 | ||
c191eca1 CW |
4892 | static void |
4893 | intel_dp_connector_unregister(struct drm_connector *connector) | |
4894 | { | |
4895 | drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); | |
4896 | intel_connector_unregister(connector); | |
4897 | } | |
4898 | ||
a4fc5ed6 | 4899 | static void |
73845adf | 4900 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 4901 | { |
1d508706 | 4902 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 4903 | |
10e972d3 | 4904 | kfree(intel_connector->detect_edid); |
beb60608 | 4905 | |
9cd300e0 JN |
4906 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4907 | kfree(intel_connector->edid); | |
4908 | ||
acd8db10 PZ |
4909 | /* Can't call is_edp() since the encoder may have been destroyed |
4910 | * already. */ | |
4911 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
1d508706 | 4912 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 4913 | |
a4fc5ed6 | 4914 | drm_connector_cleanup(connector); |
55f78c43 | 4915 | kfree(connector); |
a4fc5ed6 KP |
4916 | } |
4917 | ||
00c09d70 | 4918 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 4919 | { |
da63a9f2 PZ |
4920 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4921 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
24d05927 | 4922 | |
0e32b39c | 4923 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
bd943159 KP |
4924 | if (is_edp(intel_dp)) { |
4925 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
951468f3 VS |
4926 | /* |
4927 | * vdd might still be enabled do to the delayed vdd off. | |
4928 | * Make sure vdd is actually turned off here. | |
4929 | */ | |
773538e8 | 4930 | pps_lock(intel_dp); |
4be73780 | 4931 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 VS |
4932 | pps_unlock(intel_dp); |
4933 | ||
01527b31 CT |
4934 | if (intel_dp->edp_notifier.notifier_call) { |
4935 | unregister_reboot_notifier(&intel_dp->edp_notifier); | |
4936 | intel_dp->edp_notifier.notifier_call = NULL; | |
4937 | } | |
bd943159 | 4938 | } |
99681886 CW |
4939 | |
4940 | intel_dp_aux_fini(intel_dp); | |
4941 | ||
c8bd0e49 | 4942 | drm_encoder_cleanup(encoder); |
da63a9f2 | 4943 | kfree(intel_dig_port); |
24d05927 DV |
4944 | } |
4945 | ||
bf93ba67 | 4946 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
07f9cd0b ID |
4947 | { |
4948 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
4949 | ||
4950 | if (!is_edp(intel_dp)) | |
4951 | return; | |
4952 | ||
951468f3 VS |
4953 | /* |
4954 | * vdd might still be enabled do to the delayed vdd off. | |
4955 | * Make sure vdd is actually turned off here. | |
4956 | */ | |
afa4e53a | 4957 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
773538e8 | 4958 | pps_lock(intel_dp); |
07f9cd0b | 4959 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 | 4960 | pps_unlock(intel_dp); |
07f9cd0b ID |
4961 | } |
4962 | ||
49e6bc51 VS |
4963 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
4964 | { | |
4965 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4966 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 4967 | struct drm_i915_private *dev_priv = to_i915(dev); |
49e6bc51 VS |
4968 | enum intel_display_power_domain power_domain; |
4969 | ||
4970 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4971 | ||
4972 | if (!edp_have_panel_vdd(intel_dp)) | |
4973 | return; | |
4974 | ||
4975 | /* | |
4976 | * The VDD bit needs a power domain reference, so if the bit is | |
4977 | * already enabled when we boot or resume, grab this reference and | |
4978 | * schedule a vdd off, so we don't hold on to the reference | |
4979 | * indefinitely. | |
4980 | */ | |
4981 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); | |
25f78f58 | 4982 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
49e6bc51 VS |
4983 | intel_display_power_get(dev_priv, power_domain); |
4984 | ||
4985 | edp_panel_vdd_schedule_off(intel_dp); | |
4986 | } | |
4987 | ||
9f2bdb00 VS |
4988 | static enum pipe vlv_active_pipe(struct intel_dp *intel_dp) |
4989 | { | |
4990 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); | |
4991 | ||
4992 | if ((intel_dp->DP & DP_PORT_EN) == 0) | |
4993 | return INVALID_PIPE; | |
4994 | ||
4995 | if (IS_CHERRYVIEW(dev_priv)) | |
4996 | return DP_PORT_TO_PIPE_CHV(intel_dp->DP); | |
4997 | else | |
4998 | return PORT_TO_PIPE(intel_dp->DP); | |
4999 | } | |
5000 | ||
bf93ba67 | 5001 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
6d93c0c4 | 5002 | { |
64989ca4 | 5003 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
dd75f6dd ID |
5004 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
5005 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); | |
64989ca4 VS |
5006 | |
5007 | if (!HAS_DDI(dev_priv)) | |
5008 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
49e6bc51 | 5009 | |
dd75f6dd | 5010 | if (lspcon->active) |
910530c0 SS |
5011 | lspcon_resume(lspcon); |
5012 | ||
49e6bc51 VS |
5013 | pps_lock(intel_dp); |
5014 | ||
9f2bdb00 VS |
5015 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
5016 | intel_dp->active_pipe = vlv_active_pipe(intel_dp); | |
5017 | ||
5018 | if (is_edp(intel_dp)) { | |
5019 | /* Reinit the power sequencer, in case BIOS did something with it. */ | |
5020 | intel_dp_pps_init(encoder->dev, intel_dp); | |
5021 | intel_edp_panel_vdd_sanitize(intel_dp); | |
5022 | } | |
49e6bc51 VS |
5023 | |
5024 | pps_unlock(intel_dp); | |
6d93c0c4 ID |
5025 | } |
5026 | ||
a4fc5ed6 | 5027 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
4d688a2a | 5028 | .dpms = drm_atomic_helper_connector_dpms, |
a4fc5ed6 | 5029 | .detect = intel_dp_detect, |
beb60608 | 5030 | .force = intel_dp_force, |
a4fc5ed6 | 5031 | .fill_modes = drm_helper_probe_single_connector_modes, |
f684960e | 5032 | .set_property = intel_dp_set_property, |
2545e4a6 | 5033 | .atomic_get_property = intel_connector_atomic_get_property, |
7a418e34 | 5034 | .late_register = intel_dp_connector_register, |
c191eca1 | 5035 | .early_unregister = intel_dp_connector_unregister, |
73845adf | 5036 | .destroy = intel_dp_connector_destroy, |
c6f95f27 | 5037 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 5038 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
a4fc5ed6 KP |
5039 | }; |
5040 | ||
5041 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
5042 | .get_modes = intel_dp_get_modes, | |
5043 | .mode_valid = intel_dp_mode_valid, | |
a4fc5ed6 KP |
5044 | }; |
5045 | ||
a4fc5ed6 | 5046 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
6d93c0c4 | 5047 | .reset = intel_dp_encoder_reset, |
24d05927 | 5048 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
5049 | }; |
5050 | ||
b2c5c181 | 5051 | enum irqreturn |
13cf5504 DA |
5052 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
5053 | { | |
5054 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1c767b33 | 5055 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
0e32b39c | 5056 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 5057 | struct drm_i915_private *dev_priv = to_i915(dev); |
1c767b33 | 5058 | enum intel_display_power_domain power_domain; |
b2c5c181 | 5059 | enum irqreturn ret = IRQ_NONE; |
1c767b33 | 5060 | |
2540058f TI |
5061 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
5062 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) | |
cca0502b | 5063 | intel_dig_port->base.type = INTEL_OUTPUT_DP; |
13cf5504 | 5064 | |
7a7f84cc VS |
5065 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
5066 | /* | |
5067 | * vdd off can generate a long pulse on eDP which | |
5068 | * would require vdd on to handle it, and thus we | |
5069 | * would end up in an endless cycle of | |
5070 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." | |
5071 | */ | |
5072 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", | |
5073 | port_name(intel_dig_port->port)); | |
a8b3d52f | 5074 | return IRQ_HANDLED; |
7a7f84cc VS |
5075 | } |
5076 | ||
26fbb774 VS |
5077 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
5078 | port_name(intel_dig_port->port), | |
0e32b39c | 5079 | long_hpd ? "long" : "short"); |
13cf5504 | 5080 | |
27d4efc5 VS |
5081 | if (long_hpd) { |
5082 | intel_dp->detect_done = false; | |
5083 | return IRQ_NONE; | |
5084 | } | |
5085 | ||
25f78f58 | 5086 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1c767b33 ID |
5087 | intel_display_power_get(dev_priv, power_domain); |
5088 | ||
27d4efc5 VS |
5089 | if (intel_dp->is_mst) { |
5090 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { | |
5091 | /* | |
5092 | * If we were in MST mode, and device is not | |
5093 | * there, get out of MST mode | |
5094 | */ | |
5095 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
5096 | intel_dp->is_mst, intel_dp->mst_mgr.mst_state); | |
5097 | intel_dp->is_mst = false; | |
5098 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
5099 | intel_dp->is_mst); | |
5100 | intel_dp->detect_done = false; | |
5101 | goto put_power; | |
0e32b39c | 5102 | } |
27d4efc5 | 5103 | } |
0e32b39c | 5104 | |
27d4efc5 VS |
5105 | if (!intel_dp->is_mst) { |
5106 | if (!intel_dp_short_pulse(intel_dp)) { | |
5107 | intel_dp->detect_done = false; | |
5108 | goto put_power; | |
39ff747b | 5109 | } |
0e32b39c | 5110 | } |
b2c5c181 DV |
5111 | |
5112 | ret = IRQ_HANDLED; | |
5113 | ||
1c767b33 ID |
5114 | put_power: |
5115 | intel_display_power_put(dev_priv, power_domain); | |
5116 | ||
5117 | return ret; | |
13cf5504 DA |
5118 | } |
5119 | ||
477ec328 | 5120 | /* check the VBT to see whether the eDP is on another port */ |
dd11bc10 | 5121 | bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port) |
36e83a18 | 5122 | { |
53ce81a7 VS |
5123 | /* |
5124 | * eDP not supported on g4x. so bail out early just | |
5125 | * for a bit extra safety in case the VBT is bonkers. | |
5126 | */ | |
dd11bc10 | 5127 | if (INTEL_GEN(dev_priv) < 5) |
53ce81a7 VS |
5128 | return false; |
5129 | ||
a98d9c1d | 5130 | if (INTEL_GEN(dev_priv) < 9 && port == PORT_A) |
3b32a35b VS |
5131 | return true; |
5132 | ||
951d9efe | 5133 | return intel_bios_is_port_edp(dev_priv, port); |
36e83a18 ZY |
5134 | } |
5135 | ||
0e32b39c | 5136 | void |
f684960e CW |
5137 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
5138 | { | |
53b41837 YN |
5139 | struct intel_connector *intel_connector = to_intel_connector(connector); |
5140 | ||
3f43c48d | 5141 | intel_attach_force_audio_property(connector); |
e953fd7b | 5142 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 5143 | intel_dp->color_range_auto = true; |
53b41837 YN |
5144 | |
5145 | if (is_edp(intel_dp)) { | |
5146 | drm_mode_create_scaling_mode_property(connector->dev); | |
6de6d846 RC |
5147 | drm_object_attach_property( |
5148 | &connector->base, | |
53b41837 | 5149 | connector->dev->mode_config.scaling_mode_property, |
8e740cd1 YN |
5150 | DRM_MODE_SCALE_ASPECT); |
5151 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
53b41837 | 5152 | } |
f684960e CW |
5153 | } |
5154 | ||
dada1a9f ID |
5155 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
5156 | { | |
d28d4731 | 5157 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
dada1a9f ID |
5158 | intel_dp->last_power_on = jiffies; |
5159 | intel_dp->last_backlight_off = jiffies; | |
5160 | } | |
5161 | ||
67a54566 | 5162 | static void |
54648618 ID |
5163 | intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, |
5164 | struct intel_dp *intel_dp, struct edp_power_seq *seq) | |
67a54566 | 5165 | { |
b0a08bec | 5166 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
8e8232d5 | 5167 | struct pps_registers regs; |
453c5420 | 5168 | |
8e8232d5 | 5169 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
67a54566 DV |
5170 | |
5171 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
5172 | * the very first thing. */ | |
b0a08bec | 5173 | pp_ctl = ironlake_get_pp_control(intel_dp); |
67a54566 | 5174 | |
8e8232d5 ID |
5175 | pp_on = I915_READ(regs.pp_on); |
5176 | pp_off = I915_READ(regs.pp_off); | |
cc3f90f0 | 5177 | if (!IS_GEN9_LP(dev_priv)) { |
8e8232d5 ID |
5178 | I915_WRITE(regs.pp_ctrl, pp_ctl); |
5179 | pp_div = I915_READ(regs.pp_div); | |
b0a08bec | 5180 | } |
67a54566 DV |
5181 | |
5182 | /* Pull timing values out of registers */ | |
54648618 ID |
5183 | seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
5184 | PANEL_POWER_UP_DELAY_SHIFT; | |
67a54566 | 5185 | |
54648618 ID |
5186 | seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
5187 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
67a54566 | 5188 | |
54648618 ID |
5189 | seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
5190 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
67a54566 | 5191 | |
54648618 ID |
5192 | seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
5193 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
67a54566 | 5194 | |
cc3f90f0 | 5195 | if (IS_GEN9_LP(dev_priv)) { |
b0a08bec VK |
5196 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
5197 | BXT_POWER_CYCLE_DELAY_SHIFT; | |
5198 | if (tmp > 0) | |
54648618 | 5199 | seq->t11_t12 = (tmp - 1) * 1000; |
b0a08bec | 5200 | else |
54648618 | 5201 | seq->t11_t12 = 0; |
b0a08bec | 5202 | } else { |
54648618 | 5203 | seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
67a54566 | 5204 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
b0a08bec | 5205 | } |
54648618 ID |
5206 | } |
5207 | ||
de9c1b6b ID |
5208 | static void |
5209 | intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) | |
5210 | { | |
5211 | DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
5212 | state_name, | |
5213 | seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); | |
5214 | } | |
5215 | ||
5216 | static void | |
5217 | intel_pps_verify_state(struct drm_i915_private *dev_priv, | |
5218 | struct intel_dp *intel_dp) | |
5219 | { | |
5220 | struct edp_power_seq hw; | |
5221 | struct edp_power_seq *sw = &intel_dp->pps_delays; | |
5222 | ||
5223 | intel_pps_readout_hw_state(dev_priv, intel_dp, &hw); | |
5224 | ||
5225 | if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || | |
5226 | hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { | |
5227 | DRM_ERROR("PPS state mismatch\n"); | |
5228 | intel_pps_dump_state("sw", sw); | |
5229 | intel_pps_dump_state("hw", &hw); | |
5230 | } | |
5231 | } | |
5232 | ||
54648618 ID |
5233 | static void |
5234 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
5235 | struct intel_dp *intel_dp) | |
5236 | { | |
fac5e23e | 5237 | struct drm_i915_private *dev_priv = to_i915(dev); |
54648618 ID |
5238 | struct edp_power_seq cur, vbt, spec, |
5239 | *final = &intel_dp->pps_delays; | |
5240 | ||
5241 | lockdep_assert_held(&dev_priv->pps_mutex); | |
5242 | ||
5243 | /* already initialized? */ | |
5244 | if (final->t11_t12 != 0) | |
5245 | return; | |
5246 | ||
5247 | intel_pps_readout_hw_state(dev_priv, intel_dp, &cur); | |
67a54566 | 5248 | |
de9c1b6b | 5249 | intel_pps_dump_state("cur", &cur); |
67a54566 | 5250 | |
6aa23e65 | 5251 | vbt = dev_priv->vbt.edp.pps; |
67a54566 DV |
5252 | |
5253 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
5254 | * our hw here, which are all in 100usec. */ | |
5255 | spec.t1_t3 = 210 * 10; | |
5256 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
5257 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
5258 | spec.t10 = 500 * 10; | |
5259 | /* This one is special and actually in units of 100ms, but zero | |
5260 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
5261 | * table multiplies it with 1000 to make it in units of 100usec, | |
5262 | * too. */ | |
5263 | spec.t11_t12 = (510 + 100) * 10; | |
5264 | ||
de9c1b6b | 5265 | intel_pps_dump_state("vbt", &vbt); |
67a54566 DV |
5266 | |
5267 | /* Use the max of the register settings and vbt. If both are | |
5268 | * unset, fall back to the spec limits. */ | |
36b5f425 | 5269 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
67a54566 DV |
5270 | spec.field : \ |
5271 | max(cur.field, vbt.field)) | |
5272 | assign_final(t1_t3); | |
5273 | assign_final(t8); | |
5274 | assign_final(t9); | |
5275 | assign_final(t10); | |
5276 | assign_final(t11_t12); | |
5277 | #undef assign_final | |
5278 | ||
36b5f425 | 5279 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
67a54566 DV |
5280 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
5281 | intel_dp->backlight_on_delay = get_delay(t8); | |
5282 | intel_dp->backlight_off_delay = get_delay(t9); | |
5283 | intel_dp->panel_power_down_delay = get_delay(t10); | |
5284 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
5285 | #undef get_delay | |
5286 | ||
f30d26e4 JN |
5287 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
5288 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
5289 | intel_dp->panel_power_cycle_delay); | |
5290 | ||
5291 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
5292 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
de9c1b6b ID |
5293 | |
5294 | /* | |
5295 | * We override the HW backlight delays to 1 because we do manual waits | |
5296 | * on them. For T8, even BSpec recommends doing it. For T9, if we | |
5297 | * don't do this, we'll end up waiting for the backlight off delay | |
5298 | * twice: once when we do the manual sleep, and once when we disable | |
5299 | * the panel and wait for the PP_STATUS bit to become zero. | |
5300 | */ | |
5301 | final->t8 = 1; | |
5302 | final->t9 = 1; | |
f30d26e4 JN |
5303 | } |
5304 | ||
5305 | static void | |
5306 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
5d5ab2d2 VS |
5307 | struct intel_dp *intel_dp, |
5308 | bool force_disable_vdd) | |
f30d26e4 | 5309 | { |
fac5e23e | 5310 | struct drm_i915_private *dev_priv = to_i915(dev); |
453c5420 | 5311 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
e7dc33f3 | 5312 | int div = dev_priv->rawclk_freq / 1000; |
8e8232d5 | 5313 | struct pps_registers regs; |
ad933b56 | 5314 | enum port port = dp_to_dig_port(intel_dp)->port; |
36b5f425 | 5315 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
453c5420 | 5316 | |
e39b999a | 5317 | lockdep_assert_held(&dev_priv->pps_mutex); |
453c5420 | 5318 | |
8e8232d5 | 5319 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
453c5420 | 5320 | |
5d5ab2d2 VS |
5321 | /* |
5322 | * On some VLV machines the BIOS can leave the VDD | |
5323 | * enabled even on power seqeuencers which aren't | |
5324 | * hooked up to any port. This would mess up the | |
5325 | * power domain tracking the first time we pick | |
5326 | * one of these power sequencers for use since | |
5327 | * edp_panel_vdd_on() would notice that the VDD was | |
5328 | * already on and therefore wouldn't grab the power | |
5329 | * domain reference. Disable VDD first to avoid this. | |
5330 | * This also avoids spuriously turning the VDD on as | |
5331 | * soon as the new power seqeuencer gets initialized. | |
5332 | */ | |
5333 | if (force_disable_vdd) { | |
5334 | u32 pp = ironlake_get_pp_control(intel_dp); | |
5335 | ||
5336 | WARN(pp & PANEL_POWER_ON, "Panel power already on\n"); | |
5337 | ||
5338 | if (pp & EDP_FORCE_VDD) | |
5339 | DRM_DEBUG_KMS("VDD already on, disabling first\n"); | |
5340 | ||
5341 | pp &= ~EDP_FORCE_VDD; | |
5342 | ||
5343 | I915_WRITE(regs.pp_ctrl, pp); | |
5344 | } | |
5345 | ||
f30d26e4 | 5346 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
de9c1b6b ID |
5347 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
5348 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 5349 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
5350 | /* Compute the divisor for the pp clock, simply match the Bspec |
5351 | * formula. */ | |
cc3f90f0 | 5352 | if (IS_GEN9_LP(dev_priv)) { |
8e8232d5 | 5353 | pp_div = I915_READ(regs.pp_ctrl); |
b0a08bec VK |
5354 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
5355 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) | |
5356 | << BXT_POWER_CYCLE_DELAY_SHIFT); | |
5357 | } else { | |
5358 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; | |
5359 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) | |
5360 | << PANEL_POWER_CYCLE_DELAY_SHIFT); | |
5361 | } | |
67a54566 DV |
5362 | |
5363 | /* Haswell doesn't have any port selection bits for the panel | |
5364 | * power sequencer any more. */ | |
920a14b2 | 5365 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
ad933b56 | 5366 | port_sel = PANEL_PORT_SELECT_VLV(port); |
6e266956 | 5367 | } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
ad933b56 | 5368 | if (port == PORT_A) |
a24c144c | 5369 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 5370 | else |
a24c144c | 5371 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
5372 | } |
5373 | ||
453c5420 JB |
5374 | pp_on |= port_sel; |
5375 | ||
8e8232d5 ID |
5376 | I915_WRITE(regs.pp_on, pp_on); |
5377 | I915_WRITE(regs.pp_off, pp_off); | |
cc3f90f0 | 5378 | if (IS_GEN9_LP(dev_priv)) |
8e8232d5 | 5379 | I915_WRITE(regs.pp_ctrl, pp_div); |
b0a08bec | 5380 | else |
8e8232d5 | 5381 | I915_WRITE(regs.pp_div, pp_div); |
67a54566 | 5382 | |
67a54566 | 5383 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
8e8232d5 ID |
5384 | I915_READ(regs.pp_on), |
5385 | I915_READ(regs.pp_off), | |
cc3f90f0 | 5386 | IS_GEN9_LP(dev_priv) ? |
8e8232d5 ID |
5387 | (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : |
5388 | I915_READ(regs.pp_div)); | |
f684960e CW |
5389 | } |
5390 | ||
335f752b ID |
5391 | static void intel_dp_pps_init(struct drm_device *dev, |
5392 | struct intel_dp *intel_dp) | |
5393 | { | |
920a14b2 TU |
5394 | struct drm_i915_private *dev_priv = to_i915(dev); |
5395 | ||
5396 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
335f752b ID |
5397 | vlv_initial_power_sequencer_setup(intel_dp); |
5398 | } else { | |
5399 | intel_dp_init_panel_power_sequencer(dev, intel_dp); | |
5d5ab2d2 | 5400 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false); |
335f752b ID |
5401 | } |
5402 | } | |
5403 | ||
b33a2815 VK |
5404 | /** |
5405 | * intel_dp_set_drrs_state - program registers for RR switch to take effect | |
5423adf1 | 5406 | * @dev_priv: i915 device |
e896402c | 5407 | * @crtc_state: a pointer to the active intel_crtc_state |
b33a2815 VK |
5408 | * @refresh_rate: RR to be programmed |
5409 | * | |
5410 | * This function gets called when refresh rate (RR) has to be changed from | |
5411 | * one frequency to another. Switches can be between high and low RR | |
5412 | * supported by the panel or to any other RR based on media playback (in | |
5413 | * this case, RR value needs to be passed from user space). | |
5414 | * | |
5415 | * The caller of this function needs to take a lock on dev_priv->drrs. | |
5416 | */ | |
85cb48a1 ML |
5417 | static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, |
5418 | struct intel_crtc_state *crtc_state, | |
5419 | int refresh_rate) | |
439d7ac0 | 5420 | { |
439d7ac0 | 5421 | struct intel_encoder *encoder; |
96178eeb VK |
5422 | struct intel_digital_port *dig_port = NULL; |
5423 | struct intel_dp *intel_dp = dev_priv->drrs.dp; | |
85cb48a1 | 5424 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
96178eeb | 5425 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
439d7ac0 PB |
5426 | |
5427 | if (refresh_rate <= 0) { | |
5428 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); | |
5429 | return; | |
5430 | } | |
5431 | ||
96178eeb VK |
5432 | if (intel_dp == NULL) { |
5433 | DRM_DEBUG_KMS("DRRS not supported.\n"); | |
439d7ac0 PB |
5434 | return; |
5435 | } | |
5436 | ||
1fcc9d1c | 5437 | /* |
e4d59f6b RV |
5438 | * FIXME: This needs proper synchronization with psr state for some |
5439 | * platforms that cannot have PSR and DRRS enabled at the same time. | |
1fcc9d1c | 5440 | */ |
439d7ac0 | 5441 | |
96178eeb VK |
5442 | dig_port = dp_to_dig_port(intel_dp); |
5443 | encoder = &dig_port->base; | |
723f9aab | 5444 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
439d7ac0 PB |
5445 | |
5446 | if (!intel_crtc) { | |
5447 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); | |
5448 | return; | |
5449 | } | |
5450 | ||
96178eeb | 5451 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
439d7ac0 PB |
5452 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5453 | return; | |
5454 | } | |
5455 | ||
96178eeb VK |
5456 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5457 | refresh_rate) | |
439d7ac0 PB |
5458 | index = DRRS_LOW_RR; |
5459 | ||
96178eeb | 5460 | if (index == dev_priv->drrs.refresh_rate_type) { |
439d7ac0 PB |
5461 | DRM_DEBUG_KMS( |
5462 | "DRRS requested for previously set RR...ignoring\n"); | |
5463 | return; | |
5464 | } | |
5465 | ||
85cb48a1 | 5466 | if (!crtc_state->base.active) { |
439d7ac0 PB |
5467 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
5468 | return; | |
5469 | } | |
5470 | ||
85cb48a1 | 5471 | if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { |
a4c30b1d VK |
5472 | switch (index) { |
5473 | case DRRS_HIGH_RR: | |
5474 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
5475 | break; | |
5476 | case DRRS_LOW_RR: | |
5477 | intel_dp_set_m_n(intel_crtc, M2_N2); | |
5478 | break; | |
5479 | case DRRS_MAX_RR: | |
5480 | default: | |
5481 | DRM_ERROR("Unsupported refreshrate type\n"); | |
5482 | } | |
85cb48a1 ML |
5483 | } else if (INTEL_GEN(dev_priv) > 6) { |
5484 | i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); | |
649636ef | 5485 | u32 val; |
a4c30b1d | 5486 | |
649636ef | 5487 | val = I915_READ(reg); |
439d7ac0 | 5488 | if (index > DRRS_HIGH_RR) { |
85cb48a1 | 5489 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
5490 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5491 | else | |
5492 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 5493 | } else { |
85cb48a1 | 5494 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
5495 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5496 | else | |
5497 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 PB |
5498 | } |
5499 | I915_WRITE(reg, val); | |
5500 | } | |
5501 | ||
4e9ac947 VK |
5502 | dev_priv->drrs.refresh_rate_type = index; |
5503 | ||
5504 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); | |
5505 | } | |
5506 | ||
b33a2815 VK |
5507 | /** |
5508 | * intel_edp_drrs_enable - init drrs struct if supported | |
5509 | * @intel_dp: DP struct | |
5423adf1 | 5510 | * @crtc_state: A pointer to the active crtc state. |
b33a2815 VK |
5511 | * |
5512 | * Initializes frontbuffer_bits and drrs.dp | |
5513 | */ | |
85cb48a1 ML |
5514 | void intel_edp_drrs_enable(struct intel_dp *intel_dp, |
5515 | struct intel_crtc_state *crtc_state) | |
c395578e VK |
5516 | { |
5517 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 5518 | struct drm_i915_private *dev_priv = to_i915(dev); |
c395578e | 5519 | |
85cb48a1 | 5520 | if (!crtc_state->has_drrs) { |
c395578e VK |
5521 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
5522 | return; | |
5523 | } | |
5524 | ||
5525 | mutex_lock(&dev_priv->drrs.mutex); | |
5526 | if (WARN_ON(dev_priv->drrs.dp)) { | |
5527 | DRM_ERROR("DRRS already enabled\n"); | |
5528 | goto unlock; | |
5529 | } | |
5530 | ||
5531 | dev_priv->drrs.busy_frontbuffer_bits = 0; | |
5532 | ||
5533 | dev_priv->drrs.dp = intel_dp; | |
5534 | ||
5535 | unlock: | |
5536 | mutex_unlock(&dev_priv->drrs.mutex); | |
5537 | } | |
5538 | ||
b33a2815 VK |
5539 | /** |
5540 | * intel_edp_drrs_disable - Disable DRRS | |
5541 | * @intel_dp: DP struct | |
5423adf1 | 5542 | * @old_crtc_state: Pointer to old crtc_state. |
b33a2815 VK |
5543 | * |
5544 | */ | |
85cb48a1 ML |
5545 | void intel_edp_drrs_disable(struct intel_dp *intel_dp, |
5546 | struct intel_crtc_state *old_crtc_state) | |
c395578e VK |
5547 | { |
5548 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 5549 | struct drm_i915_private *dev_priv = to_i915(dev); |
c395578e | 5550 | |
85cb48a1 | 5551 | if (!old_crtc_state->has_drrs) |
c395578e VK |
5552 | return; |
5553 | ||
5554 | mutex_lock(&dev_priv->drrs.mutex); | |
5555 | if (!dev_priv->drrs.dp) { | |
5556 | mutex_unlock(&dev_priv->drrs.mutex); | |
5557 | return; | |
5558 | } | |
5559 | ||
5560 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) | |
85cb48a1 ML |
5561 | intel_dp_set_drrs_state(dev_priv, old_crtc_state, |
5562 | intel_dp->attached_connector->panel.fixed_mode->vrefresh); | |
c395578e VK |
5563 | |
5564 | dev_priv->drrs.dp = NULL; | |
5565 | mutex_unlock(&dev_priv->drrs.mutex); | |
5566 | ||
5567 | cancel_delayed_work_sync(&dev_priv->drrs.work); | |
5568 | } | |
5569 | ||
4e9ac947 VK |
5570 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5571 | { | |
5572 | struct drm_i915_private *dev_priv = | |
5573 | container_of(work, typeof(*dev_priv), drrs.work.work); | |
5574 | struct intel_dp *intel_dp; | |
5575 | ||
5576 | mutex_lock(&dev_priv->drrs.mutex); | |
5577 | ||
5578 | intel_dp = dev_priv->drrs.dp; | |
5579 | ||
5580 | if (!intel_dp) | |
5581 | goto unlock; | |
5582 | ||
439d7ac0 | 5583 | /* |
4e9ac947 VK |
5584 | * The delayed work can race with an invalidate hence we need to |
5585 | * recheck. | |
439d7ac0 PB |
5586 | */ |
5587 | ||
4e9ac947 VK |
5588 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5589 | goto unlock; | |
439d7ac0 | 5590 | |
85cb48a1 ML |
5591 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { |
5592 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; | |
5593 | ||
5594 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, | |
5595 | intel_dp->attached_connector->panel.downclock_mode->vrefresh); | |
5596 | } | |
439d7ac0 | 5597 | |
4e9ac947 | 5598 | unlock: |
4e9ac947 | 5599 | mutex_unlock(&dev_priv->drrs.mutex); |
439d7ac0 PB |
5600 | } |
5601 | ||
b33a2815 | 5602 | /** |
0ddfd203 | 5603 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5748b6a1 | 5604 | * @dev_priv: i915 device |
b33a2815 VK |
5605 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5606 | * | |
0ddfd203 R |
5607 | * This function gets called everytime rendering on the given planes start. |
5608 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). | |
b33a2815 VK |
5609 | * |
5610 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5611 | */ | |
5748b6a1 CW |
5612 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
5613 | unsigned int frontbuffer_bits) | |
a93fad0f | 5614 | { |
a93fad0f VK |
5615 | struct drm_crtc *crtc; |
5616 | enum pipe pipe; | |
5617 | ||
9da7d693 | 5618 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5619 | return; |
5620 | ||
88f933a8 | 5621 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5622 | |
a93fad0f | 5623 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5624 | if (!dev_priv->drrs.dp) { |
5625 | mutex_unlock(&dev_priv->drrs.mutex); | |
5626 | return; | |
5627 | } | |
5628 | ||
a93fad0f VK |
5629 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5630 | pipe = to_intel_crtc(crtc)->pipe; | |
5631 | ||
c1d038c6 DV |
5632 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5633 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; | |
5634 | ||
0ddfd203 | 5635 | /* invalidate means busy screen hence upclock */ |
c1d038c6 | 5636 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
5637 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
5638 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
a93fad0f | 5639 | |
a93fad0f VK |
5640 | mutex_unlock(&dev_priv->drrs.mutex); |
5641 | } | |
5642 | ||
b33a2815 | 5643 | /** |
0ddfd203 | 5644 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5748b6a1 | 5645 | * @dev_priv: i915 device |
b33a2815 VK |
5646 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5647 | * | |
0ddfd203 R |
5648 | * This function gets called every time rendering on the given planes has |
5649 | * completed or flip on a crtc is completed. So DRRS should be upclocked | |
5650 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, | |
5651 | * if no other planes are dirty. | |
b33a2815 VK |
5652 | * |
5653 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5654 | */ | |
5748b6a1 CW |
5655 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, |
5656 | unsigned int frontbuffer_bits) | |
a93fad0f | 5657 | { |
a93fad0f VK |
5658 | struct drm_crtc *crtc; |
5659 | enum pipe pipe; | |
5660 | ||
9da7d693 | 5661 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5662 | return; |
5663 | ||
88f933a8 | 5664 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5665 | |
a93fad0f | 5666 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5667 | if (!dev_priv->drrs.dp) { |
5668 | mutex_unlock(&dev_priv->drrs.mutex); | |
5669 | return; | |
5670 | } | |
5671 | ||
a93fad0f VK |
5672 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5673 | pipe = to_intel_crtc(crtc)->pipe; | |
c1d038c6 DV |
5674 | |
5675 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
a93fad0f VK |
5676 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5677 | ||
0ddfd203 | 5678 | /* flush means busy screen hence upclock */ |
c1d038c6 | 5679 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
5680 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
5681 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
0ddfd203 R |
5682 | |
5683 | /* | |
5684 | * flush also means no more activity hence schedule downclock, if all | |
5685 | * other fbs are quiescent too | |
5686 | */ | |
5687 | if (!dev_priv->drrs.busy_frontbuffer_bits) | |
a93fad0f VK |
5688 | schedule_delayed_work(&dev_priv->drrs.work, |
5689 | msecs_to_jiffies(1000)); | |
5690 | mutex_unlock(&dev_priv->drrs.mutex); | |
5691 | } | |
5692 | ||
b33a2815 VK |
5693 | /** |
5694 | * DOC: Display Refresh Rate Switching (DRRS) | |
5695 | * | |
5696 | * Display Refresh Rate Switching (DRRS) is a power conservation feature | |
5697 | * which enables swtching between low and high refresh rates, | |
5698 | * dynamically, based on the usage scenario. This feature is applicable | |
5699 | * for internal panels. | |
5700 | * | |
5701 | * Indication that the panel supports DRRS is given by the panel EDID, which | |
5702 | * would list multiple refresh rates for one resolution. | |
5703 | * | |
5704 | * DRRS is of 2 types - static and seamless. | |
5705 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset | |
5706 | * (may appear as a blink on screen) and is used in dock-undock scenario. | |
5707 | * Seamless DRRS involves changing RR without any visual effect to the user | |
5708 | * and can be used during normal system usage. This is done by programming | |
5709 | * certain registers. | |
5710 | * | |
5711 | * Support for static/seamless DRRS may be indicated in the VBT based on | |
5712 | * inputs from the panel spec. | |
5713 | * | |
5714 | * DRRS saves power by switching to low RR based on usage scenarios. | |
5715 | * | |
2e7a5701 DV |
5716 | * The implementation is based on frontbuffer tracking implementation. When |
5717 | * there is a disturbance on the screen triggered by user activity or a periodic | |
5718 | * system activity, DRRS is disabled (RR is changed to high RR). When there is | |
5719 | * no movement on screen, after a timeout of 1 second, a switch to low RR is | |
5720 | * made. | |
5721 | * | |
5722 | * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() | |
5723 | * and intel_edp_drrs_flush() are called. | |
b33a2815 VK |
5724 | * |
5725 | * DRRS can be further extended to support other internal panels and also | |
5726 | * the scenario of video playback wherein RR is set based on the rate | |
5727 | * requested by userspace. | |
5728 | */ | |
5729 | ||
5730 | /** | |
5731 | * intel_dp_drrs_init - Init basic DRRS work and mutex. | |
5732 | * @intel_connector: eDP connector | |
5733 | * @fixed_mode: preferred mode of panel | |
5734 | * | |
5735 | * This function is called only once at driver load to initialize basic | |
5736 | * DRRS stuff. | |
5737 | * | |
5738 | * Returns: | |
5739 | * Downclock mode if panel supports it, else return NULL. | |
5740 | * DRRS support is determined by the presence of downclock mode (apart | |
5741 | * from VBT setting). | |
5742 | */ | |
4f9db5b5 | 5743 | static struct drm_display_mode * |
96178eeb VK |
5744 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5745 | struct drm_display_mode *fixed_mode) | |
4f9db5b5 PB |
5746 | { |
5747 | struct drm_connector *connector = &intel_connector->base; | |
96178eeb | 5748 | struct drm_device *dev = connector->dev; |
fac5e23e | 5749 | struct drm_i915_private *dev_priv = to_i915(dev); |
4f9db5b5 PB |
5750 | struct drm_display_mode *downclock_mode = NULL; |
5751 | ||
9da7d693 DV |
5752 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5753 | mutex_init(&dev_priv->drrs.mutex); | |
5754 | ||
dd11bc10 | 5755 | if (INTEL_GEN(dev_priv) <= 6) { |
4f9db5b5 PB |
5756 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
5757 | return NULL; | |
5758 | } | |
5759 | ||
5760 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
4079b8d1 | 5761 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
4f9db5b5 PB |
5762 | return NULL; |
5763 | } | |
5764 | ||
5765 | downclock_mode = intel_find_panel_downclock | |
a318b4c4 | 5766 | (dev_priv, fixed_mode, connector); |
4f9db5b5 PB |
5767 | |
5768 | if (!downclock_mode) { | |
a1d26342 | 5769 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
4f9db5b5 PB |
5770 | return NULL; |
5771 | } | |
5772 | ||
96178eeb | 5773 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
4f9db5b5 | 5774 | |
96178eeb | 5775 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
4079b8d1 | 5776 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
4f9db5b5 PB |
5777 | return downclock_mode; |
5778 | } | |
5779 | ||
ed92f0b2 | 5780 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 5781 | struct intel_connector *intel_connector) |
ed92f0b2 PZ |
5782 | { |
5783 | struct drm_connector *connector = &intel_connector->base; | |
5784 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
63635217 PZ |
5785 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5786 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 5787 | struct drm_i915_private *dev_priv = to_i915(dev); |
ed92f0b2 | 5788 | struct drm_display_mode *fixed_mode = NULL; |
4f9db5b5 | 5789 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 PZ |
5790 | bool has_dpcd; |
5791 | struct drm_display_mode *scan; | |
5792 | struct edid *edid; | |
6517d273 | 5793 | enum pipe pipe = INVALID_PIPE; |
ed92f0b2 PZ |
5794 | |
5795 | if (!is_edp(intel_dp)) | |
5796 | return true; | |
5797 | ||
97a824e1 ID |
5798 | /* |
5799 | * On IBX/CPT we may get here with LVDS already registered. Since the | |
5800 | * driver uses the only internal power sequencer available for both | |
5801 | * eDP and LVDS bail out early in this case to prevent interfering | |
5802 | * with an already powered-on LVDS power sequencer. | |
5803 | */ | |
5804 | if (intel_get_lvds_encoder(dev)) { | |
5805 | WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); | |
5806 | DRM_INFO("LVDS was detected, not registering eDP\n"); | |
5807 | ||
5808 | return false; | |
5809 | } | |
5810 | ||
49e6bc51 | 5811 | pps_lock(intel_dp); |
b4d06ede ID |
5812 | |
5813 | intel_dp_init_panel_power_timestamps(intel_dp); | |
335f752b | 5814 | intel_dp_pps_init(dev, intel_dp); |
49e6bc51 | 5815 | intel_edp_panel_vdd_sanitize(intel_dp); |
b4d06ede | 5816 | |
49e6bc51 | 5817 | pps_unlock(intel_dp); |
63635217 | 5818 | |
ed92f0b2 | 5819 | /* Cache DPCD and EDID for edp. */ |
fe5a66f9 | 5820 | has_dpcd = intel_edp_init_dpcd(intel_dp); |
ed92f0b2 | 5821 | |
fe5a66f9 | 5822 | if (!has_dpcd) { |
ed92f0b2 PZ |
5823 | /* if this fails, presume the device is a ghost */ |
5824 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
b4d06ede | 5825 | goto out_vdd_off; |
ed92f0b2 PZ |
5826 | } |
5827 | ||
060c8778 | 5828 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 5829 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
5830 | if (edid) { |
5831 | if (drm_add_edid_modes(connector, edid)) { | |
5832 | drm_mode_connector_update_edid_property(connector, | |
5833 | edid); | |
5834 | drm_edid_to_eld(connector, edid); | |
5835 | } else { | |
5836 | kfree(edid); | |
5837 | edid = ERR_PTR(-EINVAL); | |
5838 | } | |
5839 | } else { | |
5840 | edid = ERR_PTR(-ENOENT); | |
5841 | } | |
5842 | intel_connector->edid = edid; | |
5843 | ||
5844 | /* prefer fixed mode from EDID if available */ | |
5845 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
5846 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
5847 | fixed_mode = drm_mode_duplicate(dev, scan); | |
4f9db5b5 | 5848 | downclock_mode = intel_dp_drrs_init( |
4f9db5b5 | 5849 | intel_connector, fixed_mode); |
ed92f0b2 PZ |
5850 | break; |
5851 | } | |
5852 | } | |
5853 | ||
5854 | /* fallback to VBT if available for eDP */ | |
5855 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
5856 | fixed_mode = drm_mode_duplicate(dev, | |
5857 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
df457245 | 5858 | if (fixed_mode) { |
ed92f0b2 | 5859 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
df457245 VS |
5860 | connector->display_info.width_mm = fixed_mode->width_mm; |
5861 | connector->display_info.height_mm = fixed_mode->height_mm; | |
5862 | } | |
ed92f0b2 | 5863 | } |
060c8778 | 5864 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 5865 | |
920a14b2 | 5866 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
01527b31 CT |
5867 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
5868 | register_reboot_notifier(&intel_dp->edp_notifier); | |
6517d273 VS |
5869 | |
5870 | /* | |
5871 | * Figure out the current pipe for the initial backlight setup. | |
5872 | * If the current pipe isn't valid, try the PPS pipe, and if that | |
5873 | * fails just assume pipe A. | |
5874 | */ | |
9f2bdb00 | 5875 | pipe = vlv_active_pipe(intel_dp); |
6517d273 VS |
5876 | |
5877 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5878 | pipe = intel_dp->pps_pipe; | |
5879 | ||
5880 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5881 | pipe = PIPE_A; | |
5882 | ||
5883 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", | |
5884 | pipe_name(pipe)); | |
01527b31 CT |
5885 | } |
5886 | ||
4f9db5b5 | 5887 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5507faeb | 5888 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
6517d273 | 5889 | intel_panel_setup_backlight(connector, pipe); |
ed92f0b2 PZ |
5890 | |
5891 | return true; | |
b4d06ede ID |
5892 | |
5893 | out_vdd_off: | |
5894 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
5895 | /* | |
5896 | * vdd might still be enabled do to the delayed vdd off. | |
5897 | * Make sure vdd is actually turned off here. | |
5898 | */ | |
5899 | pps_lock(intel_dp); | |
5900 | edp_panel_vdd_off_sync(intel_dp); | |
5901 | pps_unlock(intel_dp); | |
5902 | ||
5903 | return false; | |
ed92f0b2 PZ |
5904 | } |
5905 | ||
16c25533 | 5906 | bool |
f0fec3f2 PZ |
5907 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5908 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 5909 | { |
f0fec3f2 PZ |
5910 | struct drm_connector *connector = &intel_connector->base; |
5911 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
5912 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
5913 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 5914 | struct drm_i915_private *dev_priv = to_i915(dev); |
174edf1f | 5915 | enum port port = intel_dig_port->port; |
7a418e34 | 5916 | int type; |
a4fc5ed6 | 5917 | |
ccb1a831 VS |
5918 | if (WARN(intel_dig_port->max_lanes < 1, |
5919 | "Not enough lanes (%d) for DP on port %c\n", | |
5920 | intel_dig_port->max_lanes, port_name(port))) | |
5921 | return false; | |
5922 | ||
a4a5d2f8 | 5923 | intel_dp->pps_pipe = INVALID_PIPE; |
9f2bdb00 | 5924 | intel_dp->active_pipe = INVALID_PIPE; |
a4a5d2f8 | 5925 | |
ec5b01dd | 5926 | /* intel_dp vfuncs */ |
dd11bc10 | 5927 | if (INTEL_GEN(dev_priv) >= 9) |
b6b5e383 | 5928 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
8652744b | 5929 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ec5b01dd | 5930 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
6e266956 | 5931 | else if (HAS_PCH_SPLIT(dev_priv)) |
ec5b01dd DL |
5932 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
5933 | else | |
6ffb1be7 | 5934 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; |
ec5b01dd | 5935 | |
dd11bc10 | 5936 | if (INTEL_GEN(dev_priv) >= 9) |
b9ca5fad DL |
5937 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
5938 | else | |
6ffb1be7 | 5939 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; |
153b1100 | 5940 | |
4f8036a2 | 5941 | if (HAS_DDI(dev_priv)) |
ad64217b ACO |
5942 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; |
5943 | ||
0767935e DV |
5944 | /* Preserve the current hw state. */ |
5945 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 5946 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 5947 | |
dd11bc10 | 5948 | if (intel_dp_is_edp(dev_priv, port)) |
b329530c | 5949 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
5950 | else |
5951 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 5952 | |
9f2bdb00 VS |
5953 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
5954 | intel_dp->active_pipe = vlv_active_pipe(intel_dp); | |
5955 | ||
f7d24902 ID |
5956 | /* |
5957 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
5958 | * for DP the encoder type can be set by the caller to | |
5959 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
5960 | */ | |
5961 | if (type == DRM_MODE_CONNECTOR_eDP) | |
5962 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
5963 | ||
c17ed5b5 | 5964 | /* eDP only on port B and/or C on vlv/chv */ |
920a14b2 | 5965 | if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 5966 | is_edp(intel_dp) && port != PORT_B && port != PORT_C)) |
c17ed5b5 VS |
5967 | return false; |
5968 | ||
e7281eab ID |
5969 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
5970 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
5971 | port_name(port)); | |
5972 | ||
b329530c | 5973 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
5974 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
5975 | ||
a4fc5ed6 KP |
5976 | connector->interlace_allowed = true; |
5977 | connector->doublescan_allowed = 0; | |
5978 | ||
b6339585 | 5979 | intel_dp_aux_init(intel_dp); |
7a418e34 | 5980 | |
f0fec3f2 | 5981 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 5982 | edp_panel_vdd_work); |
a4fc5ed6 | 5983 | |
df0e9248 | 5984 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 | 5985 | |
4f8036a2 | 5986 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
5987 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
5988 | else | |
5989 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
5990 | ||
0b99836f | 5991 | /* Set up the hotplug pin. */ |
ab9d7c30 PZ |
5992 | switch (port) { |
5993 | case PORT_A: | |
1d843f9d | 5994 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
5995 | break; |
5996 | case PORT_B: | |
1d843f9d | 5997 | intel_encoder->hpd_pin = HPD_PORT_B; |
e2d214ae | 5998 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
cf1d5883 | 5999 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
6000 | break; |
6001 | case PORT_C: | |
1d843f9d | 6002 | intel_encoder->hpd_pin = HPD_PORT_C; |
ab9d7c30 PZ |
6003 | break; |
6004 | case PORT_D: | |
1d843f9d | 6005 | intel_encoder->hpd_pin = HPD_PORT_D; |
ab9d7c30 | 6006 | break; |
26951caf XZ |
6007 | case PORT_E: |
6008 | intel_encoder->hpd_pin = HPD_PORT_E; | |
6009 | break; | |
ab9d7c30 | 6010 | default: |
ad1c0b19 | 6011 | BUG(); |
5eb08b69 ZW |
6012 | } |
6013 | ||
0e32b39c | 6014 | /* init MST on ports that can support it */ |
56b857a5 | 6015 | if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) && |
0c9b3715 JN |
6016 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
6017 | intel_dp_mst_encoder_init(intel_dig_port, | |
6018 | intel_connector->base.base.id); | |
0e32b39c | 6019 | |
36b5f425 | 6020 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
a121f4e5 VS |
6021 | intel_dp_aux_fini(intel_dp); |
6022 | intel_dp_mst_encoder_cleanup(intel_dig_port); | |
6023 | goto fail; | |
b2f246a8 | 6024 | } |
32f9d658 | 6025 | |
f684960e CW |
6026 | intel_dp_add_properties(intel_dp, connector); |
6027 | ||
a4fc5ed6 KP |
6028 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
6029 | * 0xd. Failure to do so will result in spurious interrupts being | |
6030 | * generated on the port when a cable is not attached. | |
6031 | */ | |
50a0bc90 | 6032 | if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { |
a4fc5ed6 KP |
6033 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
6034 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
6035 | } | |
16c25533 PZ |
6036 | |
6037 | return true; | |
a121f4e5 VS |
6038 | |
6039 | fail: | |
a121f4e5 VS |
6040 | drm_connector_cleanup(connector); |
6041 | ||
6042 | return false; | |
a4fc5ed6 | 6043 | } |
f0fec3f2 | 6044 | |
c39055b0 | 6045 | bool intel_dp_init(struct drm_i915_private *dev_priv, |
457c52d8 CW |
6046 | i915_reg_t output_reg, |
6047 | enum port port) | |
f0fec3f2 PZ |
6048 | { |
6049 | struct intel_digital_port *intel_dig_port; | |
6050 | struct intel_encoder *intel_encoder; | |
6051 | struct drm_encoder *encoder; | |
6052 | struct intel_connector *intel_connector; | |
6053 | ||
b14c5679 | 6054 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 | 6055 | if (!intel_dig_port) |
457c52d8 | 6056 | return false; |
f0fec3f2 | 6057 | |
08d9bc92 | 6058 | intel_connector = intel_connector_alloc(); |
11aee0f6 SM |
6059 | if (!intel_connector) |
6060 | goto err_connector_alloc; | |
f0fec3f2 PZ |
6061 | |
6062 | intel_encoder = &intel_dig_port->base; | |
6063 | encoder = &intel_encoder->base; | |
6064 | ||
c39055b0 ACO |
6065 | if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
6066 | &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
6067 | "DP %c", port_name(port))) | |
893da0c9 | 6068 | goto err_encoder_init; |
f0fec3f2 | 6069 | |
5bfe2ac0 | 6070 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 6071 | intel_encoder->disable = intel_disable_dp; |
00c09d70 | 6072 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 6073 | intel_encoder->get_config = intel_dp_get_config; |
07f9cd0b | 6074 | intel_encoder->suspend = intel_dp_encoder_suspend; |
920a14b2 | 6075 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 6076 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
e4a1d846 CML |
6077 | intel_encoder->pre_enable = chv_pre_enable_dp; |
6078 | intel_encoder->enable = vlv_enable_dp; | |
580d3811 | 6079 | intel_encoder->post_disable = chv_post_disable_dp; |
d6db995f | 6080 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
11a914c2 | 6081 | } else if (IS_VALLEYVIEW(dev_priv)) { |
ecff4f3b | 6082 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
6083 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
6084 | intel_encoder->enable = vlv_enable_dp; | |
49277c31 | 6085 | intel_encoder->post_disable = vlv_post_disable_dp; |
ab1f90f9 | 6086 | } else { |
ecff4f3b JN |
6087 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
6088 | intel_encoder->enable = g4x_enable_dp; | |
dd11bc10 | 6089 | if (INTEL_GEN(dev_priv) >= 5) |
08aff3fe | 6090 | intel_encoder->post_disable = ilk_post_disable_dp; |
ab1f90f9 | 6091 | } |
f0fec3f2 | 6092 | |
174edf1f | 6093 | intel_dig_port->port = port; |
f0fec3f2 | 6094 | intel_dig_port->dp.output_reg = output_reg; |
ccb1a831 | 6095 | intel_dig_port->max_lanes = 4; |
f0fec3f2 | 6096 | |
cca0502b | 6097 | intel_encoder->type = INTEL_OUTPUT_DP; |
920a14b2 | 6098 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 VS |
6099 | if (port == PORT_D) |
6100 | intel_encoder->crtc_mask = 1 << 2; | |
6101 | else | |
6102 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
6103 | } else { | |
6104 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
6105 | } | |
bc079e8b | 6106 | intel_encoder->cloneable = 0; |
03cdc1d4 | 6107 | intel_encoder->port = port; |
f0fec3f2 | 6108 | |
13cf5504 | 6109 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
5fcece80 | 6110 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
13cf5504 | 6111 | |
11aee0f6 SM |
6112 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
6113 | goto err_init_connector; | |
6114 | ||
457c52d8 | 6115 | return true; |
11aee0f6 SM |
6116 | |
6117 | err_init_connector: | |
6118 | drm_encoder_cleanup(encoder); | |
893da0c9 | 6119 | err_encoder_init: |
11aee0f6 SM |
6120 | kfree(intel_connector); |
6121 | err_connector_alloc: | |
6122 | kfree(intel_dig_port); | |
457c52d8 | 6123 | return false; |
f0fec3f2 | 6124 | } |
0e32b39c DA |
6125 | |
6126 | void intel_dp_mst_suspend(struct drm_device *dev) | |
6127 | { | |
fac5e23e | 6128 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
6129 | int i; |
6130 | ||
6131 | /* disable MST */ | |
6132 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 6133 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 VS |
6134 | |
6135 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) | |
0e32b39c DA |
6136 | continue; |
6137 | ||
5aa56969 VS |
6138 | if (intel_dig_port->dp.is_mst) |
6139 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); | |
0e32b39c DA |
6140 | } |
6141 | } | |
6142 | ||
6143 | void intel_dp_mst_resume(struct drm_device *dev) | |
6144 | { | |
fac5e23e | 6145 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
6146 | int i; |
6147 | ||
6148 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 6149 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 | 6150 | int ret; |
0e32b39c | 6151 | |
5aa56969 VS |
6152 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) |
6153 | continue; | |
0e32b39c | 6154 | |
5aa56969 VS |
6155 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
6156 | if (ret) | |
6157 | intel_dp_check_mst_status(&intel_dig_port->dp); | |
0e32b39c DA |
6158 | } |
6159 | } |