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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
a4fc5ed6 KP |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "drm_crtc_helper.h" | |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
ab2c0672 | 37 | #include "drm_dp_helper.h" |
a4fc5ed6 | 38 | |
a2006cf5 | 39 | #define DP_RECEIVER_CAP_SIZE 0xf |
a4fc5ed6 KP |
40 | #define DP_LINK_STATUS_SIZE 6 |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) | |
42 | ||
43 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
44 | ||
ea5b213a CW |
45 | struct intel_dp { |
46 | struct intel_encoder base; | |
a4fc5ed6 KP |
47 | uint32_t output_reg; |
48 | uint32_t DP; | |
49 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
a4fc5ed6 | 50 | bool has_audio; |
f684960e | 51 | int force_audio; |
e953fd7b | 52 | uint32_t color_range; |
d2b996ac | 53 | int dpms_mode; |
a4fc5ed6 KP |
54 | uint8_t link_bw; |
55 | uint8_t lane_count; | |
a2006cf5 | 56 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
a4fc5ed6 KP |
57 | struct i2c_adapter adapter; |
58 | struct i2c_algo_dp_aux_data algo; | |
f0917379 | 59 | bool is_pch_edp; |
33a34e4e JB |
60 | uint8_t train_set[4]; |
61 | uint8_t link_status[DP_LINK_STATUS_SIZE]; | |
f01eca2e KP |
62 | int panel_power_up_delay; |
63 | int panel_power_down_delay; | |
64 | int panel_power_cycle_delay; | |
65 | int backlight_on_delay; | |
66 | int backlight_off_delay; | |
d15456de | 67 | struct drm_display_mode *panel_fixed_mode; /* for eDP */ |
bd943159 KP |
68 | struct delayed_work panel_vdd_work; |
69 | bool want_panel_vdd; | |
70 | unsigned long panel_off_jiffies; | |
a4fc5ed6 KP |
71 | }; |
72 | ||
cfcb0fc9 JB |
73 | /** |
74 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
75 | * @intel_dp: DP struct | |
76 | * | |
77 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
78 | * will return true, and false otherwise. | |
79 | */ | |
80 | static bool is_edp(struct intel_dp *intel_dp) | |
81 | { | |
82 | return intel_dp->base.type == INTEL_OUTPUT_EDP; | |
83 | } | |
84 | ||
85 | /** | |
86 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? | |
87 | * @intel_dp: DP struct | |
88 | * | |
89 | * Returns true if the given DP struct corresponds to a PCH DP port attached | |
90 | * to an eDP panel, false otherwise. Helpful for determining whether we | |
91 | * may need FDI resources for a given DP output or not. | |
92 | */ | |
93 | static bool is_pch_edp(struct intel_dp *intel_dp) | |
94 | { | |
95 | return intel_dp->is_pch_edp; | |
96 | } | |
97 | ||
1c95822a AJ |
98 | /** |
99 | * is_cpu_edp - is the port on the CPU and attached to an eDP panel? | |
100 | * @intel_dp: DP struct | |
101 | * | |
102 | * Returns true if the given DP struct corresponds to a CPU eDP port. | |
103 | */ | |
104 | static bool is_cpu_edp(struct intel_dp *intel_dp) | |
105 | { | |
106 | return is_edp(intel_dp) && !is_pch_edp(intel_dp); | |
107 | } | |
108 | ||
ea5b213a CW |
109 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
110 | { | |
4ef69c7a | 111 | return container_of(encoder, struct intel_dp, base.base); |
ea5b213a | 112 | } |
a4fc5ed6 | 113 | |
df0e9248 CW |
114 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
115 | { | |
116 | return container_of(intel_attached_encoder(connector), | |
117 | struct intel_dp, base); | |
118 | } | |
119 | ||
814948ad JB |
120 | /** |
121 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? | |
122 | * @encoder: DRM encoder | |
123 | * | |
124 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed | |
125 | * by intel_display.c. | |
126 | */ | |
127 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) | |
128 | { | |
129 | struct intel_dp *intel_dp; | |
130 | ||
131 | if (!encoder) | |
132 | return false; | |
133 | ||
134 | intel_dp = enc_to_intel_dp(encoder); | |
135 | ||
136 | return is_pch_edp(intel_dp); | |
137 | } | |
138 | ||
33a34e4e JB |
139 | static void intel_dp_start_link_train(struct intel_dp *intel_dp); |
140 | static void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
ea5b213a | 141 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
a4fc5ed6 | 142 | |
32f9d658 | 143 | void |
0206e353 | 144 | intel_edp_link_config(struct intel_encoder *intel_encoder, |
ea5b213a | 145 | int *lane_num, int *link_bw) |
32f9d658 | 146 | { |
ea5b213a | 147 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
32f9d658 | 148 | |
ea5b213a CW |
149 | *lane_num = intel_dp->lane_count; |
150 | if (intel_dp->link_bw == DP_LINK_BW_1_62) | |
32f9d658 | 151 | *link_bw = 162000; |
ea5b213a | 152 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
32f9d658 ZW |
153 | *link_bw = 270000; |
154 | } | |
155 | ||
a4fc5ed6 | 156 | static int |
ea5b213a | 157 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
a4fc5ed6 | 158 | { |
a4fc5ed6 KP |
159 | int max_lane_count = 4; |
160 | ||
7183dc29 JB |
161 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
162 | max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; | |
a4fc5ed6 KP |
163 | switch (max_lane_count) { |
164 | case 1: case 2: case 4: | |
165 | break; | |
166 | default: | |
167 | max_lane_count = 4; | |
168 | } | |
169 | } | |
170 | return max_lane_count; | |
171 | } | |
172 | ||
173 | static int | |
ea5b213a | 174 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 175 | { |
7183dc29 | 176 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
177 | |
178 | switch (max_link_bw) { | |
179 | case DP_LINK_BW_1_62: | |
180 | case DP_LINK_BW_2_7: | |
181 | break; | |
182 | default: | |
183 | max_link_bw = DP_LINK_BW_1_62; | |
184 | break; | |
185 | } | |
186 | return max_link_bw; | |
187 | } | |
188 | ||
189 | static int | |
190 | intel_dp_link_clock(uint8_t link_bw) | |
191 | { | |
192 | if (link_bw == DP_LINK_BW_2_7) | |
193 | return 270000; | |
194 | else | |
195 | return 162000; | |
196 | } | |
197 | ||
cd9dde44 AJ |
198 | /* |
199 | * The units on the numbers in the next two are... bizarre. Examples will | |
200 | * make it clearer; this one parallels an example in the eDP spec. | |
201 | * | |
202 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
203 | * | |
204 | * 270000 * 1 * 8 / 10 == 216000 | |
205 | * | |
206 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
207 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
208 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
209 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
210 | * | |
211 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
212 | * get the result in decakilobits instead of kilobits. | |
213 | */ | |
214 | ||
a4fc5ed6 | 215 | static int |
cd9dde44 | 216 | intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock) |
a4fc5ed6 | 217 | { |
89c61432 JB |
218 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
219 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
220 | int bpp = 24; | |
885a5fb5 | 221 | |
89c61432 JB |
222 | if (intel_crtc) |
223 | bpp = intel_crtc->bpp; | |
224 | ||
cd9dde44 | 225 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
226 | } |
227 | ||
fe27d53e DA |
228 | static int |
229 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
230 | { | |
231 | return (max_link_clock * max_lanes * 8) / 10; | |
232 | } | |
233 | ||
a4fc5ed6 KP |
234 | static int |
235 | intel_dp_mode_valid(struct drm_connector *connector, | |
236 | struct drm_display_mode *mode) | |
237 | { | |
df0e9248 | 238 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
ea5b213a CW |
239 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
240 | int max_lanes = intel_dp_max_lane_count(intel_dp); | |
a4fc5ed6 | 241 | |
d15456de KP |
242 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
243 | if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay) | |
7de56f43 ZY |
244 | return MODE_PANEL; |
245 | ||
d15456de | 246 | if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay) |
7de56f43 ZY |
247 | return MODE_PANEL; |
248 | } | |
249 | ||
dc22ee6f AJ |
250 | if (intel_dp_link_required(intel_dp, mode->clock) |
251 | > intel_dp_max_data_rate(max_link_clock, max_lanes)) | |
a4fc5ed6 KP |
252 | return MODE_CLOCK_HIGH; |
253 | ||
254 | if (mode->clock < 10000) | |
255 | return MODE_CLOCK_LOW; | |
256 | ||
257 | return MODE_OK; | |
258 | } | |
259 | ||
260 | static uint32_t | |
261 | pack_aux(uint8_t *src, int src_bytes) | |
262 | { | |
263 | int i; | |
264 | uint32_t v = 0; | |
265 | ||
266 | if (src_bytes > 4) | |
267 | src_bytes = 4; | |
268 | for (i = 0; i < src_bytes; i++) | |
269 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
270 | return v; | |
271 | } | |
272 | ||
273 | static void | |
274 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
275 | { | |
276 | int i; | |
277 | if (dst_bytes > 4) | |
278 | dst_bytes = 4; | |
279 | for (i = 0; i < dst_bytes; i++) | |
280 | dst[i] = src >> ((3-i) * 8); | |
281 | } | |
282 | ||
fb0f8fbf KP |
283 | /* hrawclock is 1/4 the FSB frequency */ |
284 | static int | |
285 | intel_hrawclk(struct drm_device *dev) | |
286 | { | |
287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
288 | uint32_t clkcfg; | |
289 | ||
290 | clkcfg = I915_READ(CLKCFG); | |
291 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
292 | case CLKCFG_FSB_400: | |
293 | return 100; | |
294 | case CLKCFG_FSB_533: | |
295 | return 133; | |
296 | case CLKCFG_FSB_667: | |
297 | return 166; | |
298 | case CLKCFG_FSB_800: | |
299 | return 200; | |
300 | case CLKCFG_FSB_1067: | |
301 | return 266; | |
302 | case CLKCFG_FSB_1333: | |
303 | return 333; | |
304 | /* these two are just a guess; one of them might be right */ | |
305 | case CLKCFG_FSB_1600: | |
306 | case CLKCFG_FSB_1600_ALT: | |
307 | return 400; | |
308 | default: | |
309 | return 133; | |
310 | } | |
311 | } | |
312 | ||
ebf33b18 KP |
313 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
314 | { | |
315 | struct drm_device *dev = intel_dp->base.base.dev; | |
316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
317 | ||
318 | return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; | |
319 | } | |
320 | ||
321 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) | |
322 | { | |
323 | struct drm_device *dev = intel_dp->base.base.dev; | |
324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
325 | ||
326 | return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; | |
327 | } | |
328 | ||
9b984dae KP |
329 | static void |
330 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
331 | { | |
332 | struct drm_device *dev = intel_dp->base.base.dev; | |
333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ebf33b18 | 334 | |
9b984dae KP |
335 | if (!is_edp(intel_dp)) |
336 | return; | |
ebf33b18 | 337 | if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
338 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
339 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
ebf33b18 | 340 | I915_READ(PCH_PP_STATUS), |
9b984dae KP |
341 | I915_READ(PCH_PP_CONTROL)); |
342 | } | |
343 | } | |
344 | ||
a4fc5ed6 | 345 | static int |
ea5b213a | 346 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
347 | uint8_t *send, int send_bytes, |
348 | uint8_t *recv, int recv_size) | |
349 | { | |
ea5b213a | 350 | uint32_t output_reg = intel_dp->output_reg; |
4ef69c7a | 351 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 KP |
352 | struct drm_i915_private *dev_priv = dev->dev_private; |
353 | uint32_t ch_ctl = output_reg + 0x10; | |
354 | uint32_t ch_data = ch_ctl + 4; | |
355 | int i; | |
356 | int recv_bytes; | |
a4fc5ed6 | 357 | uint32_t status; |
fb0f8fbf | 358 | uint32_t aux_clock_divider; |
e3421a18 | 359 | int try, precharge; |
a4fc5ed6 | 360 | |
9b984dae | 361 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 | 362 | /* The clock divider is based off the hrawclk, |
fb0f8fbf KP |
363 | * and would like to run at 2MHz. So, take the |
364 | * hrawclk value and divide by 2 and use that | |
6176b8f9 JB |
365 | * |
366 | * Note that PCH attached eDP panels should use a 125MHz input | |
367 | * clock divider. | |
a4fc5ed6 | 368 | */ |
1c95822a | 369 | if (is_cpu_edp(intel_dp)) { |
e3421a18 ZW |
370 | if (IS_GEN6(dev)) |
371 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ | |
372 | else | |
373 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
374 | } else if (HAS_PCH_SPLIT(dev)) | |
f2b115e6 | 375 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
5eb08b69 ZW |
376 | else |
377 | aux_clock_divider = intel_hrawclk(dev) / 2; | |
378 | ||
e3421a18 ZW |
379 | if (IS_GEN6(dev)) |
380 | precharge = 3; | |
381 | else | |
382 | precharge = 5; | |
383 | ||
11bee43e JB |
384 | /* Try to wait for any previous AUX channel activity */ |
385 | for (try = 0; try < 3; try++) { | |
386 | status = I915_READ(ch_ctl); | |
387 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
388 | break; | |
389 | msleep(1); | |
390 | } | |
391 | ||
392 | if (try == 3) { | |
393 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
394 | I915_READ(ch_ctl)); | |
4f7f7b7e CW |
395 | return -EBUSY; |
396 | } | |
397 | ||
fb0f8fbf KP |
398 | /* Must try at least 3 times according to DP spec */ |
399 | for (try = 0; try < 5; try++) { | |
400 | /* Load the send data into the aux channel data registers */ | |
4f7f7b7e CW |
401 | for (i = 0; i < send_bytes; i += 4) |
402 | I915_WRITE(ch_data + i, | |
403 | pack_aux(send + i, send_bytes - i)); | |
0206e353 | 404 | |
fb0f8fbf | 405 | /* Send the command and wait for it to complete */ |
4f7f7b7e CW |
406 | I915_WRITE(ch_ctl, |
407 | DP_AUX_CH_CTL_SEND_BUSY | | |
408 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
409 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
410 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
411 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
412 | DP_AUX_CH_CTL_DONE | | |
413 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
414 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
fb0f8fbf | 415 | for (;;) { |
fb0f8fbf KP |
416 | status = I915_READ(ch_ctl); |
417 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
418 | break; | |
4f7f7b7e | 419 | udelay(100); |
fb0f8fbf | 420 | } |
0206e353 | 421 | |
fb0f8fbf | 422 | /* Clear done status and any errors */ |
4f7f7b7e CW |
423 | I915_WRITE(ch_ctl, |
424 | status | | |
425 | DP_AUX_CH_CTL_DONE | | |
426 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
427 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
428 | if (status & DP_AUX_CH_CTL_DONE) | |
a4fc5ed6 KP |
429 | break; |
430 | } | |
431 | ||
a4fc5ed6 | 432 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 433 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
a5b3da54 | 434 | return -EBUSY; |
a4fc5ed6 KP |
435 | } |
436 | ||
437 | /* Check for timeout or receive error. | |
438 | * Timeouts occur when the sink is not connected | |
439 | */ | |
a5b3da54 | 440 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 441 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
a5b3da54 KP |
442 | return -EIO; |
443 | } | |
1ae8c0a5 KP |
444 | |
445 | /* Timeouts occur when the device isn't connected, so they're | |
446 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 447 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 448 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
a5b3da54 | 449 | return -ETIMEDOUT; |
a4fc5ed6 KP |
450 | } |
451 | ||
452 | /* Unload any bytes sent back from the other side */ | |
453 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
454 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
455 | if (recv_bytes > recv_size) |
456 | recv_bytes = recv_size; | |
0206e353 | 457 | |
4f7f7b7e CW |
458 | for (i = 0; i < recv_bytes; i += 4) |
459 | unpack_aux(I915_READ(ch_data + i), | |
460 | recv + i, recv_bytes - i); | |
a4fc5ed6 KP |
461 | |
462 | return recv_bytes; | |
463 | } | |
464 | ||
465 | /* Write data to the aux channel in native mode */ | |
466 | static int | |
ea5b213a | 467 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
468 | uint16_t address, uint8_t *send, int send_bytes) |
469 | { | |
470 | int ret; | |
471 | uint8_t msg[20]; | |
472 | int msg_bytes; | |
473 | uint8_t ack; | |
474 | ||
9b984dae | 475 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
476 | if (send_bytes > 16) |
477 | return -1; | |
478 | msg[0] = AUX_NATIVE_WRITE << 4; | |
479 | msg[1] = address >> 8; | |
eebc863e | 480 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
481 | msg[3] = send_bytes - 1; |
482 | memcpy(&msg[4], send, send_bytes); | |
483 | msg_bytes = send_bytes + 4; | |
484 | for (;;) { | |
ea5b213a | 485 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
486 | if (ret < 0) |
487 | return ret; | |
488 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
489 | break; | |
490 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
491 | udelay(100); | |
492 | else | |
a5b3da54 | 493 | return -EIO; |
a4fc5ed6 KP |
494 | } |
495 | return send_bytes; | |
496 | } | |
497 | ||
498 | /* Write a single byte to the aux channel in native mode */ | |
499 | static int | |
ea5b213a | 500 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
501 | uint16_t address, uint8_t byte) |
502 | { | |
ea5b213a | 503 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
504 | } |
505 | ||
506 | /* read bytes from a native aux channel */ | |
507 | static int | |
ea5b213a | 508 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
509 | uint16_t address, uint8_t *recv, int recv_bytes) |
510 | { | |
511 | uint8_t msg[4]; | |
512 | int msg_bytes; | |
513 | uint8_t reply[20]; | |
514 | int reply_bytes; | |
515 | uint8_t ack; | |
516 | int ret; | |
517 | ||
9b984dae | 518 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
519 | msg[0] = AUX_NATIVE_READ << 4; |
520 | msg[1] = address >> 8; | |
521 | msg[2] = address & 0xff; | |
522 | msg[3] = recv_bytes - 1; | |
523 | ||
524 | msg_bytes = 4; | |
525 | reply_bytes = recv_bytes + 1; | |
526 | ||
527 | for (;;) { | |
ea5b213a | 528 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 529 | reply, reply_bytes); |
a5b3da54 KP |
530 | if (ret == 0) |
531 | return -EPROTO; | |
532 | if (ret < 0) | |
a4fc5ed6 KP |
533 | return ret; |
534 | ack = reply[0]; | |
535 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
536 | memcpy(recv, reply + 1, ret - 1); | |
537 | return ret - 1; | |
538 | } | |
539 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
540 | udelay(100); | |
541 | else | |
a5b3da54 | 542 | return -EIO; |
a4fc5ed6 KP |
543 | } |
544 | } | |
545 | ||
546 | static int | |
ab2c0672 DA |
547 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
548 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 549 | { |
ab2c0672 | 550 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
551 | struct intel_dp *intel_dp = container_of(adapter, |
552 | struct intel_dp, | |
553 | adapter); | |
ab2c0672 DA |
554 | uint16_t address = algo_data->address; |
555 | uint8_t msg[5]; | |
556 | uint8_t reply[2]; | |
8316f337 | 557 | unsigned retry; |
ab2c0672 DA |
558 | int msg_bytes; |
559 | int reply_bytes; | |
560 | int ret; | |
561 | ||
9b984dae | 562 | intel_dp_check_edp(intel_dp); |
ab2c0672 DA |
563 | /* Set up the command byte */ |
564 | if (mode & MODE_I2C_READ) | |
565 | msg[0] = AUX_I2C_READ << 4; | |
566 | else | |
567 | msg[0] = AUX_I2C_WRITE << 4; | |
568 | ||
569 | if (!(mode & MODE_I2C_STOP)) | |
570 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 571 | |
ab2c0672 DA |
572 | msg[1] = address >> 8; |
573 | msg[2] = address; | |
574 | ||
575 | switch (mode) { | |
576 | case MODE_I2C_WRITE: | |
577 | msg[3] = 0; | |
578 | msg[4] = write_byte; | |
579 | msg_bytes = 5; | |
580 | reply_bytes = 1; | |
581 | break; | |
582 | case MODE_I2C_READ: | |
583 | msg[3] = 0; | |
584 | msg_bytes = 4; | |
585 | reply_bytes = 2; | |
586 | break; | |
587 | default: | |
588 | msg_bytes = 3; | |
589 | reply_bytes = 1; | |
590 | break; | |
591 | } | |
592 | ||
8316f337 DF |
593 | for (retry = 0; retry < 5; retry++) { |
594 | ret = intel_dp_aux_ch(intel_dp, | |
595 | msg, msg_bytes, | |
596 | reply, reply_bytes); | |
ab2c0672 | 597 | if (ret < 0) { |
3ff99164 | 598 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
599 | return ret; |
600 | } | |
8316f337 DF |
601 | |
602 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { | |
603 | case AUX_NATIVE_REPLY_ACK: | |
604 | /* I2C-over-AUX Reply field is only valid | |
605 | * when paired with AUX ACK. | |
606 | */ | |
607 | break; | |
608 | case AUX_NATIVE_REPLY_NACK: | |
609 | DRM_DEBUG_KMS("aux_ch native nack\n"); | |
610 | return -EREMOTEIO; | |
611 | case AUX_NATIVE_REPLY_DEFER: | |
612 | udelay(100); | |
613 | continue; | |
614 | default: | |
615 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", | |
616 | reply[0]); | |
617 | return -EREMOTEIO; | |
618 | } | |
619 | ||
ab2c0672 DA |
620 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
621 | case AUX_I2C_REPLY_ACK: | |
622 | if (mode == MODE_I2C_READ) { | |
623 | *read_byte = reply[1]; | |
624 | } | |
625 | return reply_bytes - 1; | |
626 | case AUX_I2C_REPLY_NACK: | |
8316f337 | 627 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
ab2c0672 DA |
628 | return -EREMOTEIO; |
629 | case AUX_I2C_REPLY_DEFER: | |
8316f337 | 630 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
ab2c0672 DA |
631 | udelay(100); |
632 | break; | |
633 | default: | |
8316f337 | 634 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
ab2c0672 DA |
635 | return -EREMOTEIO; |
636 | } | |
637 | } | |
8316f337 DF |
638 | |
639 | DRM_ERROR("too many retries, giving up\n"); | |
640 | return -EREMOTEIO; | |
a4fc5ed6 KP |
641 | } |
642 | ||
0b5c541b | 643 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
bd943159 | 644 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
0b5c541b | 645 | |
a4fc5ed6 | 646 | static int |
ea5b213a | 647 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 648 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 649 | { |
0b5c541b KP |
650 | int ret; |
651 | ||
d54e9d28 | 652 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
653 | intel_dp->algo.running = false; |
654 | intel_dp->algo.address = 0; | |
655 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
656 | ||
0206e353 | 657 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
ea5b213a CW |
658 | intel_dp->adapter.owner = THIS_MODULE; |
659 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
0206e353 | 660 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
ea5b213a CW |
661 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
662 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
663 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
664 | ||
0b5c541b KP |
665 | ironlake_edp_panel_vdd_on(intel_dp); |
666 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); | |
bd943159 | 667 | ironlake_edp_panel_vdd_off(intel_dp, false); |
0b5c541b | 668 | return ret; |
a4fc5ed6 KP |
669 | } |
670 | ||
671 | static bool | |
672 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
673 | struct drm_display_mode *adjusted_mode) | |
674 | { | |
0d3a1bee | 675 | struct drm_device *dev = encoder->dev; |
ea5b213a | 676 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4fc5ed6 | 677 | int lane_count, clock; |
ea5b213a CW |
678 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
679 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; | |
a4fc5ed6 KP |
680 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
681 | ||
d15456de KP |
682 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
683 | intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode); | |
1d8e1c75 CW |
684 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, |
685 | mode, adjusted_mode); | |
0d3a1bee ZY |
686 | /* |
687 | * the mode->clock is used to calculate the Data&Link M/N | |
688 | * of the pipe. For the eDP the fixed clock should be used. | |
689 | */ | |
d15456de | 690 | mode->clock = intel_dp->panel_fixed_mode->clock; |
0d3a1bee ZY |
691 | } |
692 | ||
a4fc5ed6 KP |
693 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
694 | for (clock = 0; clock <= max_clock; clock++) { | |
fe27d53e | 695 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
a4fc5ed6 | 696 | |
cd9dde44 | 697 | if (intel_dp_link_required(intel_dp, mode->clock) |
885a5fb5 | 698 | <= link_avail) { |
ea5b213a CW |
699 | intel_dp->link_bw = bws[clock]; |
700 | intel_dp->lane_count = lane_count; | |
701 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
28c97730 ZY |
702 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
703 | "count %d clock %d\n", | |
ea5b213a | 704 | intel_dp->link_bw, intel_dp->lane_count, |
a4fc5ed6 KP |
705 | adjusted_mode->clock); |
706 | return true; | |
707 | } | |
708 | } | |
709 | } | |
fe27d53e | 710 | |
a4fc5ed6 KP |
711 | return false; |
712 | } | |
713 | ||
714 | struct intel_dp_m_n { | |
715 | uint32_t tu; | |
716 | uint32_t gmch_m; | |
717 | uint32_t gmch_n; | |
718 | uint32_t link_m; | |
719 | uint32_t link_n; | |
720 | }; | |
721 | ||
722 | static void | |
723 | intel_reduce_ratio(uint32_t *num, uint32_t *den) | |
724 | { | |
725 | while (*num > 0xffffff || *den > 0xffffff) { | |
726 | *num >>= 1; | |
727 | *den >>= 1; | |
728 | } | |
729 | } | |
730 | ||
731 | static void | |
36e83a18 | 732 | intel_dp_compute_m_n(int bpp, |
a4fc5ed6 KP |
733 | int nlanes, |
734 | int pixel_clock, | |
735 | int link_clock, | |
736 | struct intel_dp_m_n *m_n) | |
737 | { | |
738 | m_n->tu = 64; | |
36e83a18 | 739 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
a4fc5ed6 KP |
740 | m_n->gmch_n = link_clock * nlanes; |
741 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
742 | m_n->link_m = pixel_clock; | |
743 | m_n->link_n = link_clock; | |
744 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
745 | } | |
746 | ||
747 | void | |
748 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
749 | struct drm_display_mode *adjusted_mode) | |
750 | { | |
751 | struct drm_device *dev = crtc->dev; | |
752 | struct drm_mode_config *mode_config = &dev->mode_config; | |
55f78c43 | 753 | struct drm_encoder *encoder; |
a4fc5ed6 KP |
754 | struct drm_i915_private *dev_priv = dev->dev_private; |
755 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
858fa035 | 756 | int lane_count = 4; |
a4fc5ed6 | 757 | struct intel_dp_m_n m_n; |
9db4a9c7 | 758 | int pipe = intel_crtc->pipe; |
a4fc5ed6 KP |
759 | |
760 | /* | |
21d40d37 | 761 | * Find the lane count in the intel_encoder private |
a4fc5ed6 | 762 | */ |
55f78c43 | 763 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
ea5b213a | 764 | struct intel_dp *intel_dp; |
a4fc5ed6 | 765 | |
d8201ab6 | 766 | if (encoder->crtc != crtc) |
a4fc5ed6 KP |
767 | continue; |
768 | ||
ea5b213a CW |
769 | intel_dp = enc_to_intel_dp(encoder); |
770 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
771 | lane_count = intel_dp->lane_count; | |
51190667 JB |
772 | break; |
773 | } else if (is_edp(intel_dp)) { | |
774 | lane_count = dev_priv->edp.lanes; | |
a4fc5ed6 KP |
775 | break; |
776 | } | |
777 | } | |
778 | ||
779 | /* | |
780 | * Compute the GMCH and Link ratios. The '3' here is | |
781 | * the number of bytes_per_pixel post-LUT, which we always | |
782 | * set up for 8-bits of R/G/B, or 3 bytes total. | |
783 | */ | |
858fa035 | 784 | intel_dp_compute_m_n(intel_crtc->bpp, lane_count, |
a4fc5ed6 KP |
785 | mode->clock, adjusted_mode->clock, &m_n); |
786 | ||
c619eed4 | 787 | if (HAS_PCH_SPLIT(dev)) { |
9db4a9c7 JB |
788 | I915_WRITE(TRANSDATA_M1(pipe), |
789 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
790 | m_n.gmch_m); | |
791 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); | |
792 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); | |
793 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); | |
a4fc5ed6 | 794 | } else { |
9db4a9c7 JB |
795 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
796 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
797 | m_n.gmch_m); | |
798 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); | |
799 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); | |
800 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); | |
a4fc5ed6 KP |
801 | } |
802 | } | |
803 | ||
f01eca2e KP |
804 | static void ironlake_edp_pll_on(struct drm_encoder *encoder); |
805 | static void ironlake_edp_pll_off(struct drm_encoder *encoder); | |
806 | ||
a4fc5ed6 KP |
807 | static void |
808 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
809 | struct drm_display_mode *adjusted_mode) | |
810 | { | |
e3421a18 | 811 | struct drm_device *dev = encoder->dev; |
ea5b213a | 812 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4ef69c7a | 813 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
a4fc5ed6 KP |
814 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
815 | ||
f01eca2e KP |
816 | /* Turn on the eDP PLL if needed */ |
817 | if (is_edp(intel_dp)) { | |
818 | if (!is_pch_edp(intel_dp)) | |
819 | ironlake_edp_pll_on(encoder); | |
820 | else | |
821 | ironlake_edp_pll_off(encoder); | |
822 | } | |
823 | ||
e953fd7b CW |
824 | intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
825 | intel_dp->DP |= intel_dp->color_range; | |
9c9e7927 AJ |
826 | |
827 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
ea5b213a | 828 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
9c9e7927 | 829 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
ea5b213a | 830 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
a4fc5ed6 | 831 | |
82d16555 | 832 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
ea5b213a | 833 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3421a18 | 834 | else |
ea5b213a | 835 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
a4fc5ed6 | 836 | |
ea5b213a | 837 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 838 | case 1: |
ea5b213a | 839 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
840 | break; |
841 | case 2: | |
ea5b213a | 842 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
843 | break; |
844 | case 4: | |
ea5b213a | 845 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
846 | break; |
847 | } | |
e0dac65e WF |
848 | if (intel_dp->has_audio) { |
849 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", | |
850 | pipe_name(intel_crtc->pipe)); | |
ea5b213a | 851 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
e0dac65e WF |
852 | intel_write_eld(encoder, adjusted_mode); |
853 | } | |
a4fc5ed6 | 854 | |
ea5b213a CW |
855 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
856 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
857 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
a2cab1b2 | 858 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
a4fc5ed6 KP |
859 | |
860 | /* | |
9962c925 | 861 | * Check for DPCD version > 1.1 and enhanced framing support |
a4fc5ed6 | 862 | */ |
7183dc29 JB |
863 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
864 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { | |
ea5b213a CW |
865 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
866 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
a4fc5ed6 KP |
867 | } |
868 | ||
e3421a18 ZW |
869 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ |
870 | if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) | |
ea5b213a | 871 | intel_dp->DP |= DP_PIPEB_SELECT; |
32f9d658 | 872 | |
1c95822a | 873 | if (is_cpu_edp(intel_dp)) { |
32f9d658 | 874 | /* don't miss out required setting for eDP */ |
ea5b213a | 875 | intel_dp->DP |= DP_PLL_ENABLE; |
32f9d658 | 876 | if (adjusted_mode->clock < 200000) |
ea5b213a | 877 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
32f9d658 | 878 | else |
ea5b213a | 879 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
32f9d658 | 880 | } |
a4fc5ed6 KP |
881 | } |
882 | ||
bd943159 KP |
883 | static void ironlake_wait_panel_off(struct intel_dp *intel_dp) |
884 | { | |
885 | unsigned long off_time; | |
886 | unsigned long delay; | |
32ce697c | 887 | |
bd943159 | 888 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
32ce697c KP |
889 | |
890 | if (ironlake_edp_have_panel_power(intel_dp) || | |
891 | ironlake_edp_have_panel_vdd(intel_dp)) | |
892 | { | |
893 | DRM_DEBUG_KMS("Panel still on, no delay needed\n"); | |
894 | return; | |
895 | } | |
896 | ||
bd943159 KP |
897 | off_time = intel_dp->panel_off_jiffies + msecs_to_jiffies(intel_dp->panel_power_down_delay); |
898 | if (time_after(jiffies, off_time)) { | |
899 | DRM_DEBUG_KMS("Time already passed"); | |
900 | return; | |
901 | } | |
902 | delay = jiffies_to_msecs(off_time - jiffies); | |
903 | if (delay > intel_dp->panel_power_down_delay) | |
904 | delay = intel_dp->panel_power_down_delay; | |
905 | DRM_DEBUG_KMS("Waiting an additional %ld ms\n", delay); | |
906 | msleep(delay); | |
907 | } | |
908 | ||
832dd3c1 KP |
909 | /* Read the current pp_control value, unlocking the register if it |
910 | * is locked | |
911 | */ | |
912 | ||
913 | static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv) | |
914 | { | |
915 | u32 control = I915_READ(PCH_PP_CONTROL); | |
916 | ||
917 | control &= ~PANEL_UNLOCK_MASK; | |
918 | control |= PANEL_UNLOCK_REGS; | |
919 | return control; | |
920 | } | |
921 | ||
5d613501 JB |
922 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
923 | { | |
924 | struct drm_device *dev = intel_dp->base.base.dev; | |
925 | struct drm_i915_private *dev_priv = dev->dev_private; | |
926 | u32 pp; | |
927 | ||
97af61f5 KP |
928 | if (!is_edp(intel_dp)) |
929 | return; | |
f01eca2e | 930 | DRM_DEBUG_KMS("Turn eDP VDD on\n"); |
5d613501 | 931 | |
bd943159 KP |
932 | WARN(intel_dp->want_panel_vdd, |
933 | "eDP VDD already requested on\n"); | |
934 | ||
935 | intel_dp->want_panel_vdd = true; | |
936 | if (ironlake_edp_have_panel_vdd(intel_dp)) { | |
937 | DRM_DEBUG_KMS("eDP VDD already on\n"); | |
938 | return; | |
939 | } | |
940 | ||
941 | ironlake_wait_panel_off(intel_dp); | |
832dd3c1 | 942 | pp = ironlake_get_pp_control(dev_priv); |
5d613501 JB |
943 | pp |= EDP_FORCE_VDD; |
944 | I915_WRITE(PCH_PP_CONTROL, pp); | |
945 | POSTING_READ(PCH_PP_CONTROL); | |
f01eca2e KP |
946 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
947 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); | |
ebf33b18 KP |
948 | |
949 | /* | |
950 | * If the panel wasn't on, delay before accessing aux channel | |
951 | */ | |
952 | if (!ironlake_edp_have_panel_power(intel_dp)) { | |
bd943159 | 953 | DRM_DEBUG_KMS("eDP was not running\n"); |
f01eca2e | 954 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 955 | } |
5d613501 JB |
956 | } |
957 | ||
bd943159 | 958 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 JB |
959 | { |
960 | struct drm_device *dev = intel_dp->base.base.dev; | |
961 | struct drm_i915_private *dev_priv = dev->dev_private; | |
962 | u32 pp; | |
963 | ||
bd943159 | 964 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
832dd3c1 | 965 | pp = ironlake_get_pp_control(dev_priv); |
bd943159 KP |
966 | pp &= ~EDP_FORCE_VDD; |
967 | I915_WRITE(PCH_PP_CONTROL, pp); | |
968 | POSTING_READ(PCH_PP_CONTROL); | |
969 | ||
970 | /* Make sure sequencer is idle before allowing subsequent activity */ | |
971 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", | |
972 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); | |
973 | intel_dp->panel_off_jiffies = jiffies; | |
974 | } | |
975 | } | |
5d613501 | 976 | |
bd943159 KP |
977 | static void ironlake_panel_vdd_work(struct work_struct *__work) |
978 | { | |
979 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
980 | struct intel_dp, panel_vdd_work); | |
981 | struct drm_device *dev = intel_dp->base.base.dev; | |
982 | ||
627f7675 | 983 | mutex_lock(&dev->mode_config.mutex); |
bd943159 | 984 | ironlake_panel_vdd_off_sync(intel_dp); |
627f7675 | 985 | mutex_unlock(&dev->mode_config.mutex); |
bd943159 KP |
986 | } |
987 | ||
988 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) | |
989 | { | |
97af61f5 KP |
990 | if (!is_edp(intel_dp)) |
991 | return; | |
5d613501 | 992 | |
bd943159 KP |
993 | DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); |
994 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); | |
995 | ||
996 | intel_dp->want_panel_vdd = false; | |
997 | ||
998 | if (sync) { | |
999 | ironlake_panel_vdd_off_sync(intel_dp); | |
1000 | } else { | |
1001 | /* | |
1002 | * Queue the timer to fire a long | |
1003 | * time from now (relative to the power down delay) | |
1004 | * to keep the panel power up across a sequence of operations | |
1005 | */ | |
1006 | schedule_delayed_work(&intel_dp->panel_vdd_work, | |
1007 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
1008 | } | |
5d613501 JB |
1009 | } |
1010 | ||
7eaf5547 | 1011 | /* Returns true if the panel was already on when called */ |
86a3073e | 1012 | static void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 1013 | { |
01cb9ea6 | 1014 | struct drm_device *dev = intel_dp->base.base.dev; |
9934c132 | 1015 | struct drm_i915_private *dev_priv = dev->dev_private; |
01cb9ea6 | 1016 | u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE; |
9934c132 | 1017 | |
97af61f5 | 1018 | if (!is_edp(intel_dp)) |
bd943159 | 1019 | return; |
ebf33b18 | 1020 | if (ironlake_edp_have_panel_power(intel_dp)) |
7d639f35 | 1021 | return; |
9934c132 | 1022 | |
bd943159 | 1023 | ironlake_wait_panel_off(intel_dp); |
832dd3c1 | 1024 | pp = ironlake_get_pp_control(dev_priv); |
37c6c9b0 | 1025 | |
05ce1a49 KP |
1026 | if (IS_GEN5(dev)) { |
1027 | /* ILK workaround: disable reset around power sequence */ | |
1028 | pp &= ~PANEL_POWER_RESET; | |
1029 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1030 | POSTING_READ(PCH_PP_CONTROL); | |
1031 | } | |
37c6c9b0 | 1032 | |
1c0ae80a | 1033 | pp |= POWER_TARGET_ON; |
9934c132 | 1034 | I915_WRITE(PCH_PP_CONTROL, pp); |
01cb9ea6 | 1035 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 | 1036 | |
01cb9ea6 JB |
1037 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, |
1038 | 5000)) | |
913d8d11 CW |
1039 | DRM_ERROR("panel on wait timed out: 0x%08x\n", |
1040 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 1041 | |
05ce1a49 KP |
1042 | if (IS_GEN5(dev)) { |
1043 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
1044 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1045 | POSTING_READ(PCH_PP_CONTROL); | |
1046 | } | |
9934c132 JB |
1047 | } |
1048 | ||
f01eca2e | 1049 | static void ironlake_edp_panel_off(struct drm_encoder *encoder) |
9934c132 | 1050 | { |
f01eca2e KP |
1051 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1052 | struct drm_device *dev = encoder->dev; | |
9934c132 | 1053 | struct drm_i915_private *dev_priv = dev->dev_private; |
01cb9ea6 JB |
1054 | u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | |
1055 | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK; | |
9934c132 | 1056 | |
97af61f5 KP |
1057 | if (!is_edp(intel_dp)) |
1058 | return; | |
832dd3c1 | 1059 | pp = ironlake_get_pp_control(dev_priv); |
37c6c9b0 | 1060 | |
05ce1a49 KP |
1061 | if (IS_GEN5(dev)) { |
1062 | /* ILK workaround: disable reset around power sequence */ | |
1063 | pp &= ~PANEL_POWER_RESET; | |
1064 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1065 | POSTING_READ(PCH_PP_CONTROL); | |
1066 | } | |
37c6c9b0 | 1067 | |
05ce1a49 | 1068 | intel_dp->panel_off_jiffies = jiffies; |
37c6c9b0 | 1069 | |
05ce1a49 KP |
1070 | if (IS_GEN5(dev)) { |
1071 | pp &= ~POWER_TARGET_ON; | |
1072 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1073 | POSTING_READ(PCH_PP_CONTROL); | |
1074 | pp &= ~POWER_TARGET_ON; | |
1075 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1076 | POSTING_READ(PCH_PP_CONTROL); | |
1077 | msleep(intel_dp->panel_power_cycle_delay); | |
9934c132 | 1078 | |
05ce1a49 KP |
1079 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000)) |
1080 | DRM_ERROR("panel off wait timed out: 0x%08x\n", | |
1081 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 1082 | |
05ce1a49 KP |
1083 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
1084 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1085 | POSTING_READ(PCH_PP_CONTROL); | |
1086 | } | |
9934c132 JB |
1087 | } |
1088 | ||
86a3073e | 1089 | static void ironlake_edp_backlight_on(struct intel_dp *intel_dp) |
32f9d658 | 1090 | { |
f01eca2e | 1091 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1092 | struct drm_i915_private *dev_priv = dev->dev_private; |
1093 | u32 pp; | |
1094 | ||
f01eca2e KP |
1095 | if (!is_edp(intel_dp)) |
1096 | return; | |
1097 | ||
28c97730 | 1098 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
1099 | /* |
1100 | * If we enable the backlight right away following a panel power | |
1101 | * on, we may see slight flicker as the panel syncs with the eDP | |
1102 | * link. So delay a bit to make sure the image is solid before | |
1103 | * allowing it to appear. | |
1104 | */ | |
f01eca2e | 1105 | msleep(intel_dp->backlight_on_delay); |
832dd3c1 | 1106 | pp = ironlake_get_pp_control(dev_priv); |
32f9d658 ZW |
1107 | pp |= EDP_BLC_ENABLE; |
1108 | I915_WRITE(PCH_PP_CONTROL, pp); | |
f01eca2e | 1109 | POSTING_READ(PCH_PP_CONTROL); |
32f9d658 ZW |
1110 | } |
1111 | ||
86a3073e | 1112 | static void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
32f9d658 | 1113 | { |
f01eca2e | 1114 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1115 | struct drm_i915_private *dev_priv = dev->dev_private; |
1116 | u32 pp; | |
1117 | ||
f01eca2e KP |
1118 | if (!is_edp(intel_dp)) |
1119 | return; | |
1120 | ||
28c97730 | 1121 | DRM_DEBUG_KMS("\n"); |
832dd3c1 | 1122 | pp = ironlake_get_pp_control(dev_priv); |
32f9d658 ZW |
1123 | pp &= ~EDP_BLC_ENABLE; |
1124 | I915_WRITE(PCH_PP_CONTROL, pp); | |
f01eca2e KP |
1125 | POSTING_READ(PCH_PP_CONTROL); |
1126 | msleep(intel_dp->backlight_off_delay); | |
32f9d658 | 1127 | } |
a4fc5ed6 | 1128 | |
d240f20f JB |
1129 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
1130 | { | |
1131 | struct drm_device *dev = encoder->dev; | |
1132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1133 | u32 dpa_ctl; | |
1134 | ||
1135 | DRM_DEBUG_KMS("\n"); | |
1136 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 1137 | dpa_ctl |= DP_PLL_ENABLE; |
d240f20f | 1138 | I915_WRITE(DP_A, dpa_ctl); |
298b0b39 JB |
1139 | POSTING_READ(DP_A); |
1140 | udelay(200); | |
d240f20f JB |
1141 | } |
1142 | ||
1143 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) | |
1144 | { | |
1145 | struct drm_device *dev = encoder->dev; | |
1146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1147 | u32 dpa_ctl; | |
1148 | ||
1149 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 1150 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 1151 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 1152 | POSTING_READ(DP_A); |
d240f20f JB |
1153 | udelay(200); |
1154 | } | |
1155 | ||
c7ad3810 JB |
1156 | /* If the sink supports it, try to set the power state appropriately */ |
1157 | static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) | |
1158 | { | |
1159 | int ret, i; | |
1160 | ||
1161 | /* Should have a valid DPCD by this point */ | |
1162 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
1163 | return; | |
1164 | ||
1165 | if (mode != DRM_MODE_DPMS_ON) { | |
1166 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, | |
1167 | DP_SET_POWER_D3); | |
1168 | if (ret != 1) | |
1169 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
1170 | } else { | |
1171 | /* | |
1172 | * When turning on, we need to retry for 1ms to give the sink | |
1173 | * time to wake up. | |
1174 | */ | |
1175 | for (i = 0; i < 3; i++) { | |
1176 | ret = intel_dp_aux_native_write_1(intel_dp, | |
1177 | DP_SET_POWER, | |
1178 | DP_SET_POWER_D0); | |
1179 | if (ret == 1) | |
1180 | break; | |
1181 | msleep(1); | |
1182 | } | |
1183 | } | |
1184 | } | |
1185 | ||
d240f20f JB |
1186 | static void intel_dp_prepare(struct drm_encoder *encoder) |
1187 | { | |
1188 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
d240f20f | 1189 | |
c7ad3810 | 1190 | /* Wake up the sink first */ |
f58ff854 | 1191 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1192 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
bd943159 | 1193 | ironlake_edp_panel_vdd_off(intel_dp, false); |
c7ad3810 | 1194 | |
f01eca2e KP |
1195 | /* Make sure the panel is off before trying to |
1196 | * change the mode | |
1197 | */ | |
1198 | ironlake_edp_backlight_off(intel_dp); | |
736085bc | 1199 | intel_dp_link_down(intel_dp); |
f01eca2e | 1200 | ironlake_edp_panel_off(encoder); |
d240f20f JB |
1201 | } |
1202 | ||
1203 | static void intel_dp_commit(struct drm_encoder *encoder) | |
1204 | { | |
1205 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
d4270e57 JB |
1206 | struct drm_device *dev = encoder->dev; |
1207 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); | |
5d613501 | 1208 | |
97af61f5 | 1209 | ironlake_edp_panel_vdd_on(intel_dp); |
f01eca2e | 1210 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 1211 | intel_dp_start_link_train(intel_dp); |
97af61f5 | 1212 | ironlake_edp_panel_on(intel_dp); |
bd943159 | 1213 | ironlake_edp_panel_vdd_off(intel_dp, true); |
33a34e4e JB |
1214 | |
1215 | intel_dp_complete_link_train(intel_dp); | |
f01eca2e | 1216 | ironlake_edp_backlight_on(intel_dp); |
d2b996ac KP |
1217 | |
1218 | intel_dp->dpms_mode = DRM_MODE_DPMS_ON; | |
d4270e57 JB |
1219 | |
1220 | if (HAS_PCH_CPT(dev)) | |
1221 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
d240f20f JB |
1222 | } |
1223 | ||
a4fc5ed6 KP |
1224 | static void |
1225 | intel_dp_dpms(struct drm_encoder *encoder, int mode) | |
1226 | { | |
ea5b213a | 1227 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
55f78c43 | 1228 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 | 1229 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1230 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
a4fc5ed6 KP |
1231 | |
1232 | if (mode != DRM_MODE_DPMS_ON) { | |
245e2708 | 1233 | ironlake_edp_panel_vdd_on(intel_dp); |
01cb9ea6 | 1234 | if (is_edp(intel_dp)) |
f01eca2e | 1235 | ironlake_edp_backlight_off(intel_dp); |
c7ad3810 | 1236 | intel_dp_sink_dpms(intel_dp, mode); |
736085bc | 1237 | intel_dp_link_down(intel_dp); |
f01eca2e | 1238 | ironlake_edp_panel_off(encoder); |
01cb9ea6 | 1239 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) |
d240f20f | 1240 | ironlake_edp_pll_off(encoder); |
bd943159 | 1241 | ironlake_edp_panel_vdd_off(intel_dp, false); |
a4fc5ed6 | 1242 | } else { |
97af61f5 | 1243 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1244 | intel_dp_sink_dpms(intel_dp, mode); |
32f9d658 | 1245 | if (!(dp_reg & DP_PORT_EN)) { |
01cb9ea6 | 1246 | intel_dp_start_link_train(intel_dp); |
97af61f5 | 1247 | ironlake_edp_panel_on(intel_dp); |
bd943159 | 1248 | ironlake_edp_panel_vdd_off(intel_dp, true); |
33a34e4e | 1249 | intel_dp_complete_link_train(intel_dp); |
f01eca2e | 1250 | ironlake_edp_backlight_on(intel_dp); |
bee7eb2d | 1251 | } else |
bd943159 KP |
1252 | ironlake_edp_panel_vdd_off(intel_dp, false); |
1253 | ironlake_edp_backlight_on(intel_dp); | |
a4fc5ed6 | 1254 | } |
d2b996ac | 1255 | intel_dp->dpms_mode = mode; |
a4fc5ed6 KP |
1256 | } |
1257 | ||
1258 | /* | |
df0c237d JB |
1259 | * Native read with retry for link status and receiver capability reads for |
1260 | * cases where the sink may still be asleep. | |
a4fc5ed6 KP |
1261 | */ |
1262 | static bool | |
df0c237d JB |
1263 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
1264 | uint8_t *recv, int recv_bytes) | |
a4fc5ed6 | 1265 | { |
61da5fab JB |
1266 | int ret, i; |
1267 | ||
df0c237d JB |
1268 | /* |
1269 | * Sinks are *supposed* to come up within 1ms from an off state, | |
1270 | * but we're also supposed to retry 3 times per the spec. | |
1271 | */ | |
61da5fab | 1272 | for (i = 0; i < 3; i++) { |
df0c237d JB |
1273 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
1274 | recv_bytes); | |
1275 | if (ret == recv_bytes) | |
61da5fab JB |
1276 | return true; |
1277 | msleep(1); | |
1278 | } | |
a4fc5ed6 | 1279 | |
61da5fab | 1280 | return false; |
a4fc5ed6 KP |
1281 | } |
1282 | ||
1283 | /* | |
1284 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
1285 | * link status information | |
1286 | */ | |
1287 | static bool | |
33a34e4e | 1288 | intel_dp_get_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1289 | { |
df0c237d JB |
1290 | return intel_dp_aux_native_read_retry(intel_dp, |
1291 | DP_LANE0_1_STATUS, | |
1292 | intel_dp->link_status, | |
1293 | DP_LINK_STATUS_SIZE); | |
a4fc5ed6 KP |
1294 | } |
1295 | ||
1296 | static uint8_t | |
1297 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1298 | int r) | |
1299 | { | |
1300 | return link_status[r - DP_LANE0_1_STATUS]; | |
1301 | } | |
1302 | ||
a4fc5ed6 KP |
1303 | static uint8_t |
1304 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1305 | int lane) | |
1306 | { | |
1307 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
1308 | int s = ((lane & 1) ? | |
1309 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
1310 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
1311 | uint8_t l = intel_dp_link_status(link_status, i); | |
1312 | ||
1313 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
1314 | } | |
1315 | ||
1316 | static uint8_t | |
1317 | intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1318 | int lane) | |
1319 | { | |
1320 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
1321 | int s = ((lane & 1) ? | |
1322 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
1323 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
1324 | uint8_t l = intel_dp_link_status(link_status, i); | |
1325 | ||
1326 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
1327 | } | |
1328 | ||
1329 | ||
1330 | #if 0 | |
1331 | static char *voltage_names[] = { | |
1332 | "0.4V", "0.6V", "0.8V", "1.2V" | |
1333 | }; | |
1334 | static char *pre_emph_names[] = { | |
1335 | "0dB", "3.5dB", "6dB", "9.5dB" | |
1336 | }; | |
1337 | static char *link_train_names[] = { | |
1338 | "pattern 1", "pattern 2", "idle", "off" | |
1339 | }; | |
1340 | #endif | |
1341 | ||
1342 | /* | |
1343 | * These are source-specific values; current Intel hardware supports | |
1344 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1345 | */ | |
1346 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 | |
1347 | ||
1348 | static uint8_t | |
1349 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) | |
1350 | { | |
1351 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1352 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1353 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1354 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1355 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1356 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1357 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1358 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1359 | default: | |
1360 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1361 | } | |
1362 | } | |
1363 | ||
1364 | static void | |
33a34e4e | 1365 | intel_get_adjust_train(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1366 | { |
1367 | uint8_t v = 0; | |
1368 | uint8_t p = 0; | |
1369 | int lane; | |
1370 | ||
33a34e4e JB |
1371 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1372 | uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane); | |
1373 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1374 | |
1375 | if (this_v > v) | |
1376 | v = this_v; | |
1377 | if (this_p > p) | |
1378 | p = this_p; | |
1379 | } | |
1380 | ||
1381 | if (v >= I830_DP_VOLTAGE_MAX) | |
1382 | v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; | |
1383 | ||
1384 | if (p >= intel_dp_pre_emphasis_max(v)) | |
1385 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
1386 | ||
1387 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 1388 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
1389 | } |
1390 | ||
1391 | static uint32_t | |
3cf2efb1 | 1392 | intel_dp_signal_levels(uint8_t train_set, int lane_count) |
a4fc5ed6 | 1393 | { |
3cf2efb1 | 1394 | uint32_t signal_levels = 0; |
a4fc5ed6 | 1395 | |
3cf2efb1 | 1396 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
1397 | case DP_TRAIN_VOLTAGE_SWING_400: |
1398 | default: | |
1399 | signal_levels |= DP_VOLTAGE_0_4; | |
1400 | break; | |
1401 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1402 | signal_levels |= DP_VOLTAGE_0_6; | |
1403 | break; | |
1404 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1405 | signal_levels |= DP_VOLTAGE_0_8; | |
1406 | break; | |
1407 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1408 | signal_levels |= DP_VOLTAGE_1_2; | |
1409 | break; | |
1410 | } | |
3cf2efb1 | 1411 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
1412 | case DP_TRAIN_PRE_EMPHASIS_0: |
1413 | default: | |
1414 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1415 | break; | |
1416 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1417 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1418 | break; | |
1419 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1420 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1421 | break; | |
1422 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1423 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1424 | break; | |
1425 | } | |
1426 | return signal_levels; | |
1427 | } | |
1428 | ||
e3421a18 ZW |
1429 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1430 | static uint32_t | |
1431 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1432 | { | |
3c5a62b5 YL |
1433 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1434 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1435 | switch (signal_levels) { | |
e3421a18 | 1436 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1437 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
1438 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
1439 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1440 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 1441 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
1442 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
1443 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 1444 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
1445 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
1446 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 1447 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1448 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
1449 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 1450 | default: |
3c5a62b5 YL |
1451 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
1452 | "0x%x\n", signal_levels); | |
1453 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
1454 | } |
1455 | } | |
1456 | ||
a4fc5ed6 KP |
1457 | static uint8_t |
1458 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1459 | int lane) | |
1460 | { | |
1461 | int i = DP_LANE0_1_STATUS + (lane >> 1); | |
1462 | int s = (lane & 1) * 4; | |
1463 | uint8_t l = intel_dp_link_status(link_status, i); | |
1464 | ||
1465 | return (l >> s) & 0xf; | |
1466 | } | |
1467 | ||
1468 | /* Check for clock recovery is done on all channels */ | |
1469 | static bool | |
1470 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1471 | { | |
1472 | int lane; | |
1473 | uint8_t lane_status; | |
1474 | ||
1475 | for (lane = 0; lane < lane_count; lane++) { | |
1476 | lane_status = intel_get_lane_status(link_status, lane); | |
1477 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
1478 | return false; | |
1479 | } | |
1480 | return true; | |
1481 | } | |
1482 | ||
1483 | /* Check to see if channel eq is done on all channels */ | |
1484 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ | |
1485 | DP_LANE_CHANNEL_EQ_DONE|\ | |
1486 | DP_LANE_SYMBOL_LOCKED) | |
1487 | static bool | |
33a34e4e | 1488 | intel_channel_eq_ok(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1489 | { |
1490 | uint8_t lane_align; | |
1491 | uint8_t lane_status; | |
1492 | int lane; | |
1493 | ||
33a34e4e | 1494 | lane_align = intel_dp_link_status(intel_dp->link_status, |
a4fc5ed6 KP |
1495 | DP_LANE_ALIGN_STATUS_UPDATED); |
1496 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
1497 | return false; | |
33a34e4e JB |
1498 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1499 | lane_status = intel_get_lane_status(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1500 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
1501 | return false; | |
1502 | } | |
1503 | return true; | |
1504 | } | |
1505 | ||
1506 | static bool | |
ea5b213a | 1507 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 | 1508 | uint32_t dp_reg_value, |
58e10eb9 | 1509 | uint8_t dp_train_pat) |
a4fc5ed6 | 1510 | { |
4ef69c7a | 1511 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1512 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1513 | int ret; |
1514 | ||
ea5b213a CW |
1515 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1516 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1517 | |
ea5b213a | 1518 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1519 | DP_TRAINING_PATTERN_SET, |
1520 | dp_train_pat); | |
1521 | ||
ea5b213a | 1522 | ret = intel_dp_aux_native_write(intel_dp, |
58e10eb9 CW |
1523 | DP_TRAINING_LANE0_SET, |
1524 | intel_dp->train_set, 4); | |
a4fc5ed6 KP |
1525 | if (ret != 4) |
1526 | return false; | |
1527 | ||
1528 | return true; | |
1529 | } | |
1530 | ||
33a34e4e | 1531 | /* Enable corresponding port and start training pattern 1 */ |
a4fc5ed6 | 1532 | static void |
33a34e4e | 1533 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1534 | { |
4ef69c7a | 1535 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1536 | struct drm_i915_private *dev_priv = dev->dev_private; |
58e10eb9 | 1537 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); |
a4fc5ed6 KP |
1538 | int i; |
1539 | uint8_t voltage; | |
1540 | bool clock_recovery = false; | |
a4fc5ed6 | 1541 | int tries; |
e3421a18 | 1542 | u32 reg; |
ea5b213a | 1543 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1544 | |
e8519464 AJ |
1545 | /* |
1546 | * On CPT we have to enable the port in training pattern 1, which | |
1547 | * will happen below in intel_dp_set_link_train. Otherwise, enable | |
1548 | * the port and wait for it to become active. | |
1549 | */ | |
1550 | if (!HAS_PCH_CPT(dev)) { | |
1551 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
1552 | POSTING_READ(intel_dp->output_reg); | |
1553 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1554 | } | |
a4fc5ed6 | 1555 | |
3cf2efb1 CW |
1556 | /* Write the link configuration data */ |
1557 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, | |
1558 | intel_dp->link_configuration, | |
1559 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
1560 | |
1561 | DP |= DP_PORT_EN; | |
82d16555 | 1562 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
e3421a18 ZW |
1563 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1564 | else | |
1565 | DP &= ~DP_LINK_TRAIN_MASK; | |
33a34e4e | 1566 | memset(intel_dp->train_set, 0, 4); |
a4fc5ed6 KP |
1567 | voltage = 0xff; |
1568 | tries = 0; | |
1569 | clock_recovery = false; | |
1570 | for (;;) { | |
33a34e4e | 1571 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 | 1572 | uint32_t signal_levels; |
cfcb0fc9 | 1573 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
33a34e4e | 1574 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1575 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1576 | } else { | |
3cf2efb1 | 1577 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1578 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1579 | } | |
a4fc5ed6 | 1580 | |
82d16555 | 1581 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
e3421a18 ZW |
1582 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
1583 | else | |
1584 | reg = DP | DP_LINK_TRAIN_PAT_1; | |
1585 | ||
ea5b213a | 1586 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1587 | DP_TRAINING_PATTERN_1 | |
1588 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 | 1589 | break; |
a4fc5ed6 KP |
1590 | /* Set training pattern 1 */ |
1591 | ||
3cf2efb1 CW |
1592 | udelay(100); |
1593 | if (!intel_dp_get_link_status(intel_dp)) | |
a4fc5ed6 | 1594 | break; |
a4fc5ed6 | 1595 | |
3cf2efb1 CW |
1596 | if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { |
1597 | clock_recovery = true; | |
1598 | break; | |
1599 | } | |
1600 | ||
1601 | /* Check to see if we've tried the max voltage */ | |
1602 | for (i = 0; i < intel_dp->lane_count; i++) | |
1603 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 1604 | break; |
3cf2efb1 CW |
1605 | if (i == intel_dp->lane_count) |
1606 | break; | |
a4fc5ed6 | 1607 | |
3cf2efb1 CW |
1608 | /* Check to see if we've tried the same voltage 5 times */ |
1609 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { | |
1610 | ++tries; | |
1611 | if (tries == 5) | |
a4fc5ed6 | 1612 | break; |
3cf2efb1 CW |
1613 | } else |
1614 | tries = 0; | |
1615 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 1616 | |
3cf2efb1 CW |
1617 | /* Compute new intel_dp->train_set as requested by target */ |
1618 | intel_get_adjust_train(intel_dp); | |
a4fc5ed6 KP |
1619 | } |
1620 | ||
33a34e4e JB |
1621 | intel_dp->DP = DP; |
1622 | } | |
1623 | ||
1624 | static void | |
1625 | intel_dp_complete_link_train(struct intel_dp *intel_dp) | |
1626 | { | |
4ef69c7a | 1627 | struct drm_device *dev = intel_dp->base.base.dev; |
33a34e4e JB |
1628 | struct drm_i915_private *dev_priv = dev->dev_private; |
1629 | bool channel_eq = false; | |
37f80975 | 1630 | int tries, cr_tries; |
33a34e4e JB |
1631 | u32 reg; |
1632 | uint32_t DP = intel_dp->DP; | |
1633 | ||
a4fc5ed6 KP |
1634 | /* channel equalization */ |
1635 | tries = 0; | |
37f80975 | 1636 | cr_tries = 0; |
a4fc5ed6 KP |
1637 | channel_eq = false; |
1638 | for (;;) { | |
33a34e4e | 1639 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 ZW |
1640 | uint32_t signal_levels; |
1641 | ||
37f80975 JB |
1642 | if (cr_tries > 5) { |
1643 | DRM_ERROR("failed to train DP, aborting\n"); | |
1644 | intel_dp_link_down(intel_dp); | |
1645 | break; | |
1646 | } | |
1647 | ||
cfcb0fc9 | 1648 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
33a34e4e | 1649 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1650 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1651 | } else { | |
3cf2efb1 | 1652 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1653 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1654 | } | |
1655 | ||
82d16555 | 1656 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
e3421a18 ZW |
1657 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
1658 | else | |
1659 | reg = DP | DP_LINK_TRAIN_PAT_2; | |
a4fc5ed6 KP |
1660 | |
1661 | /* channel eq pattern */ | |
ea5b213a | 1662 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1663 | DP_TRAINING_PATTERN_2 | |
1664 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 KP |
1665 | break; |
1666 | ||
3cf2efb1 CW |
1667 | udelay(400); |
1668 | if (!intel_dp_get_link_status(intel_dp)) | |
a4fc5ed6 | 1669 | break; |
a4fc5ed6 | 1670 | |
37f80975 JB |
1671 | /* Make sure clock is still ok */ |
1672 | if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { | |
1673 | intel_dp_start_link_train(intel_dp); | |
1674 | cr_tries++; | |
1675 | continue; | |
1676 | } | |
1677 | ||
3cf2efb1 CW |
1678 | if (intel_channel_eq_ok(intel_dp)) { |
1679 | channel_eq = true; | |
1680 | break; | |
1681 | } | |
a4fc5ed6 | 1682 | |
37f80975 JB |
1683 | /* Try 5 times, then try clock recovery if that fails */ |
1684 | if (tries > 5) { | |
1685 | intel_dp_link_down(intel_dp); | |
1686 | intel_dp_start_link_train(intel_dp); | |
1687 | tries = 0; | |
1688 | cr_tries++; | |
1689 | continue; | |
1690 | } | |
a4fc5ed6 | 1691 | |
3cf2efb1 CW |
1692 | /* Compute new intel_dp->train_set as requested by target */ |
1693 | intel_get_adjust_train(intel_dp); | |
1694 | ++tries; | |
869184a6 | 1695 | } |
3cf2efb1 | 1696 | |
82d16555 | 1697 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
e3421a18 ZW |
1698 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
1699 | else | |
1700 | reg = DP | DP_LINK_TRAIN_OFF; | |
1701 | ||
ea5b213a CW |
1702 | I915_WRITE(intel_dp->output_reg, reg); |
1703 | POSTING_READ(intel_dp->output_reg); | |
1704 | intel_dp_aux_native_write_1(intel_dp, | |
a4fc5ed6 KP |
1705 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
1706 | } | |
1707 | ||
1708 | static void | |
ea5b213a | 1709 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 1710 | { |
4ef69c7a | 1711 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1712 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1713 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1714 | |
1b39d6f3 CW |
1715 | if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) |
1716 | return; | |
1717 | ||
28c97730 | 1718 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1719 | |
cfcb0fc9 | 1720 | if (is_edp(intel_dp)) { |
32f9d658 | 1721 | DP &= ~DP_PLL_ENABLE; |
ea5b213a CW |
1722 | I915_WRITE(intel_dp->output_reg, DP); |
1723 | POSTING_READ(intel_dp->output_reg); | |
32f9d658 ZW |
1724 | udelay(100); |
1725 | } | |
1726 | ||
82d16555 | 1727 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) { |
e3421a18 | 1728 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 1729 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
1730 | } else { |
1731 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 1732 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 1733 | } |
fe255d00 | 1734 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 1735 | |
fe255d00 | 1736 | msleep(17); |
5eb08b69 | 1737 | |
cfcb0fc9 | 1738 | if (is_edp(intel_dp)) |
32f9d658 | 1739 | DP |= DP_LINK_TRAIN_OFF; |
5bddd17f | 1740 | |
1b39d6f3 CW |
1741 | if (!HAS_PCH_CPT(dev) && |
1742 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { | |
31acbcc4 CW |
1743 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
1744 | ||
5bddd17f EA |
1745 | /* Hardware workaround: leaving our transcoder select |
1746 | * set to transcoder B while it's off will prevent the | |
1747 | * corresponding HDMI output on transcoder A. | |
1748 | * | |
1749 | * Combine this with another hardware workaround: | |
1750 | * transcoder select bit can only be cleared while the | |
1751 | * port is enabled. | |
1752 | */ | |
1753 | DP &= ~DP_PIPEB_SELECT; | |
1754 | I915_WRITE(intel_dp->output_reg, DP); | |
1755 | ||
1756 | /* Changes to enable or select take place the vblank | |
1757 | * after being written. | |
1758 | */ | |
31acbcc4 CW |
1759 | if (crtc == NULL) { |
1760 | /* We can arrive here never having been attached | |
1761 | * to a CRTC, for instance, due to inheriting | |
1762 | * random state from the BIOS. | |
1763 | * | |
1764 | * If the pipe is not running, play safe and | |
1765 | * wait for the clocks to stabilise before | |
1766 | * continuing. | |
1767 | */ | |
1768 | POSTING_READ(intel_dp->output_reg); | |
1769 | msleep(50); | |
1770 | } else | |
1771 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
5bddd17f EA |
1772 | } |
1773 | ||
ea5b213a CW |
1774 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
1775 | POSTING_READ(intel_dp->output_reg); | |
f01eca2e | 1776 | msleep(intel_dp->panel_power_down_delay); |
a4fc5ed6 KP |
1777 | } |
1778 | ||
26d61aad KP |
1779 | static bool |
1780 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 1781 | { |
92fd8fd1 | 1782 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
0206e353 | 1783 | sizeof(intel_dp->dpcd)) && |
92fd8fd1 | 1784 | (intel_dp->dpcd[DP_DPCD_REV] != 0)) { |
26d61aad | 1785 | return true; |
92fd8fd1 KP |
1786 | } |
1787 | ||
26d61aad | 1788 | return false; |
92fd8fd1 KP |
1789 | } |
1790 | ||
a60f0e38 JB |
1791 | static bool |
1792 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
1793 | { | |
1794 | int ret; | |
1795 | ||
1796 | ret = intel_dp_aux_native_read_retry(intel_dp, | |
1797 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
1798 | sink_irq_vector, 1); | |
1799 | if (!ret) | |
1800 | return false; | |
1801 | ||
1802 | return true; | |
1803 | } | |
1804 | ||
1805 | static void | |
1806 | intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
1807 | { | |
1808 | /* NAK by default */ | |
1809 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK); | |
1810 | } | |
1811 | ||
a4fc5ed6 KP |
1812 | /* |
1813 | * According to DP spec | |
1814 | * 5.1.2: | |
1815 | * 1. Read DPCD | |
1816 | * 2. Configure link according to Receiver Capabilities | |
1817 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
1818 | * 4. Check link status on receipt of hot-plug interrupt | |
1819 | */ | |
1820 | ||
1821 | static void | |
ea5b213a | 1822 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1823 | { |
a60f0e38 JB |
1824 | u8 sink_irq_vector; |
1825 | ||
d2b996ac KP |
1826 | if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON) |
1827 | return; | |
59cd09e1 | 1828 | |
4ef69c7a | 1829 | if (!intel_dp->base.base.crtc) |
a4fc5ed6 KP |
1830 | return; |
1831 | ||
92fd8fd1 | 1832 | /* Try to read receiver status if the link appears to be up */ |
33a34e4e | 1833 | if (!intel_dp_get_link_status(intel_dp)) { |
ea5b213a | 1834 | intel_dp_link_down(intel_dp); |
a4fc5ed6 KP |
1835 | return; |
1836 | } | |
1837 | ||
92fd8fd1 | 1838 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 1839 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
1840 | intel_dp_link_down(intel_dp); |
1841 | return; | |
1842 | } | |
1843 | ||
a60f0e38 JB |
1844 | /* Try to read the source of the interrupt */ |
1845 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
1846 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
1847 | /* Clear interrupt source */ | |
1848 | intel_dp_aux_native_write_1(intel_dp, | |
1849 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
1850 | sink_irq_vector); | |
1851 | ||
1852 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
1853 | intel_dp_handle_test_request(intel_dp); | |
1854 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
1855 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
1856 | } | |
1857 | ||
33a34e4e | 1858 | if (!intel_channel_eq_ok(intel_dp)) { |
92fd8fd1 KP |
1859 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
1860 | drm_get_encoder_name(&intel_dp->base.base)); | |
33a34e4e JB |
1861 | intel_dp_start_link_train(intel_dp); |
1862 | intel_dp_complete_link_train(intel_dp); | |
1863 | } | |
a4fc5ed6 | 1864 | } |
a4fc5ed6 | 1865 | |
71ba9000 | 1866 | static enum drm_connector_status |
26d61aad | 1867 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 1868 | { |
26d61aad KP |
1869 | if (intel_dp_get_dpcd(intel_dp)) |
1870 | return connector_status_connected; | |
1871 | return connector_status_disconnected; | |
71ba9000 AJ |
1872 | } |
1873 | ||
5eb08b69 | 1874 | static enum drm_connector_status |
a9756bb5 | 1875 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 1876 | { |
5eb08b69 ZW |
1877 | enum drm_connector_status status; |
1878 | ||
fe16d949 CW |
1879 | /* Can't disconnect eDP, but you can close the lid... */ |
1880 | if (is_edp(intel_dp)) { | |
1881 | status = intel_panel_detect(intel_dp->base.base.dev); | |
1882 | if (status == connector_status_unknown) | |
1883 | status = connector_status_connected; | |
1884 | return status; | |
1885 | } | |
01cb9ea6 | 1886 | |
26d61aad | 1887 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
1888 | } |
1889 | ||
a4fc5ed6 | 1890 | static enum drm_connector_status |
a9756bb5 | 1891 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 1892 | { |
4ef69c7a | 1893 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1894 | struct drm_i915_private *dev_priv = dev->dev_private; |
a9756bb5 | 1895 | uint32_t temp, bit; |
5eb08b69 | 1896 | |
ea5b213a | 1897 | switch (intel_dp->output_reg) { |
a4fc5ed6 KP |
1898 | case DP_B: |
1899 | bit = DPB_HOTPLUG_INT_STATUS; | |
1900 | break; | |
1901 | case DP_C: | |
1902 | bit = DPC_HOTPLUG_INT_STATUS; | |
1903 | break; | |
1904 | case DP_D: | |
1905 | bit = DPD_HOTPLUG_INT_STATUS; | |
1906 | break; | |
1907 | default: | |
1908 | return connector_status_unknown; | |
1909 | } | |
1910 | ||
1911 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
1912 | ||
1913 | if ((temp & bit) == 0) | |
1914 | return connector_status_disconnected; | |
1915 | ||
26d61aad | 1916 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
1917 | } |
1918 | ||
8c241fef KP |
1919 | static struct edid * |
1920 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
1921 | { | |
1922 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1923 | struct edid *edid; | |
1924 | ||
1925 | ironlake_edp_panel_vdd_on(intel_dp); | |
1926 | edid = drm_get_edid(connector, adapter); | |
bd943159 | 1927 | ironlake_edp_panel_vdd_off(intel_dp, false); |
8c241fef KP |
1928 | return edid; |
1929 | } | |
1930 | ||
1931 | static int | |
1932 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) | |
1933 | { | |
1934 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1935 | int ret; | |
1936 | ||
1937 | ironlake_edp_panel_vdd_on(intel_dp); | |
1938 | ret = intel_ddc_get_modes(connector, adapter); | |
bd943159 | 1939 | ironlake_edp_panel_vdd_off(intel_dp, false); |
8c241fef KP |
1940 | return ret; |
1941 | } | |
1942 | ||
1943 | ||
a9756bb5 ZW |
1944 | /** |
1945 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. | |
1946 | * | |
1947 | * \return true if DP port is connected. | |
1948 | * \return false if DP port is disconnected. | |
1949 | */ | |
1950 | static enum drm_connector_status | |
1951 | intel_dp_detect(struct drm_connector *connector, bool force) | |
1952 | { | |
1953 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1954 | struct drm_device *dev = intel_dp->base.base.dev; | |
1955 | enum drm_connector_status status; | |
1956 | struct edid *edid = NULL; | |
1957 | ||
1958 | intel_dp->has_audio = false; | |
1959 | ||
1960 | if (HAS_PCH_SPLIT(dev)) | |
1961 | status = ironlake_dp_detect(intel_dp); | |
1962 | else | |
1963 | status = g4x_dp_detect(intel_dp); | |
1b9be9d0 | 1964 | |
ac66ae83 AJ |
1965 | DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", |
1966 | intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], | |
1967 | intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], | |
1968 | intel_dp->dpcd[6], intel_dp->dpcd[7]); | |
1b9be9d0 | 1969 | |
a9756bb5 ZW |
1970 | if (status != connector_status_connected) |
1971 | return status; | |
1972 | ||
f684960e CW |
1973 | if (intel_dp->force_audio) { |
1974 | intel_dp->has_audio = intel_dp->force_audio > 0; | |
1975 | } else { | |
8c241fef | 1976 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
f684960e CW |
1977 | if (edid) { |
1978 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
1979 | connector->display_info.raw_edid = NULL; | |
1980 | kfree(edid); | |
1981 | } | |
a9756bb5 ZW |
1982 | } |
1983 | ||
1984 | return connector_status_connected; | |
a4fc5ed6 KP |
1985 | } |
1986 | ||
1987 | static int intel_dp_get_modes(struct drm_connector *connector) | |
1988 | { | |
df0e9248 | 1989 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4ef69c7a | 1990 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1991 | struct drm_i915_private *dev_priv = dev->dev_private; |
1992 | int ret; | |
a4fc5ed6 KP |
1993 | |
1994 | /* We should parse the EDID data and find out if it has an audio sink | |
1995 | */ | |
1996 | ||
8c241fef | 1997 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
b9efc480 | 1998 | if (ret) { |
d15456de | 1999 | if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) { |
b9efc480 ZY |
2000 | struct drm_display_mode *newmode; |
2001 | list_for_each_entry(newmode, &connector->probed_modes, | |
2002 | head) { | |
d15456de KP |
2003 | if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) { |
2004 | intel_dp->panel_fixed_mode = | |
b9efc480 ZY |
2005 | drm_mode_duplicate(dev, newmode); |
2006 | break; | |
2007 | } | |
2008 | } | |
2009 | } | |
32f9d658 | 2010 | return ret; |
b9efc480 | 2011 | } |
32f9d658 ZW |
2012 | |
2013 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ | |
4d926461 | 2014 | if (is_edp(intel_dp)) { |
47f0eb22 | 2015 | /* initialize panel mode from VBT if available for eDP */ |
d15456de KP |
2016 | if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) { |
2017 | intel_dp->panel_fixed_mode = | |
47f0eb22 | 2018 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
d15456de KP |
2019 | if (intel_dp->panel_fixed_mode) { |
2020 | intel_dp->panel_fixed_mode->type |= | |
47f0eb22 KP |
2021 | DRM_MODE_TYPE_PREFERRED; |
2022 | } | |
2023 | } | |
d15456de | 2024 | if (intel_dp->panel_fixed_mode) { |
32f9d658 | 2025 | struct drm_display_mode *mode; |
d15456de | 2026 | mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode); |
32f9d658 ZW |
2027 | drm_mode_probed_add(connector, mode); |
2028 | return 1; | |
2029 | } | |
2030 | } | |
2031 | return 0; | |
a4fc5ed6 KP |
2032 | } |
2033 | ||
1aad7ac0 CW |
2034 | static bool |
2035 | intel_dp_detect_audio(struct drm_connector *connector) | |
2036 | { | |
2037 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
2038 | struct edid *edid; | |
2039 | bool has_audio = false; | |
2040 | ||
8c241fef | 2041 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
1aad7ac0 CW |
2042 | if (edid) { |
2043 | has_audio = drm_detect_monitor_audio(edid); | |
2044 | ||
2045 | connector->display_info.raw_edid = NULL; | |
2046 | kfree(edid); | |
2047 | } | |
2048 | ||
2049 | return has_audio; | |
2050 | } | |
2051 | ||
f684960e CW |
2052 | static int |
2053 | intel_dp_set_property(struct drm_connector *connector, | |
2054 | struct drm_property *property, | |
2055 | uint64_t val) | |
2056 | { | |
e953fd7b | 2057 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
f684960e CW |
2058 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
2059 | int ret; | |
2060 | ||
2061 | ret = drm_connector_property_set_value(connector, property, val); | |
2062 | if (ret) | |
2063 | return ret; | |
2064 | ||
3f43c48d | 2065 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
2066 | int i = val; |
2067 | bool has_audio; | |
2068 | ||
2069 | if (i == intel_dp->force_audio) | |
f684960e CW |
2070 | return 0; |
2071 | ||
1aad7ac0 | 2072 | intel_dp->force_audio = i; |
f684960e | 2073 | |
1aad7ac0 CW |
2074 | if (i == 0) |
2075 | has_audio = intel_dp_detect_audio(connector); | |
2076 | else | |
2077 | has_audio = i > 0; | |
2078 | ||
2079 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
2080 | return 0; |
2081 | ||
1aad7ac0 | 2082 | intel_dp->has_audio = has_audio; |
f684960e CW |
2083 | goto done; |
2084 | } | |
2085 | ||
e953fd7b CW |
2086 | if (property == dev_priv->broadcast_rgb_property) { |
2087 | if (val == !!intel_dp->color_range) | |
2088 | return 0; | |
2089 | ||
2090 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; | |
2091 | goto done; | |
2092 | } | |
2093 | ||
f684960e CW |
2094 | return -EINVAL; |
2095 | ||
2096 | done: | |
2097 | if (intel_dp->base.base.crtc) { | |
2098 | struct drm_crtc *crtc = intel_dp->base.base.crtc; | |
2099 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
2100 | crtc->x, crtc->y, | |
2101 | crtc->fb); | |
2102 | } | |
2103 | ||
2104 | return 0; | |
2105 | } | |
2106 | ||
a4fc5ed6 | 2107 | static void |
0206e353 | 2108 | intel_dp_destroy(struct drm_connector *connector) |
a4fc5ed6 | 2109 | { |
aaa6fd2a MG |
2110 | struct drm_device *dev = connector->dev; |
2111 | ||
2112 | if (intel_dpd_is_edp(dev)) | |
2113 | intel_panel_destroy_backlight(dev); | |
2114 | ||
a4fc5ed6 KP |
2115 | drm_sysfs_connector_remove(connector); |
2116 | drm_connector_cleanup(connector); | |
55f78c43 | 2117 | kfree(connector); |
a4fc5ed6 KP |
2118 | } |
2119 | ||
24d05927 DV |
2120 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
2121 | { | |
2122 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
2123 | ||
2124 | i2c_del_adapter(&intel_dp->adapter); | |
2125 | drm_encoder_cleanup(encoder); | |
bd943159 KP |
2126 | if (is_edp(intel_dp)) { |
2127 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
2128 | ironlake_panel_vdd_off_sync(intel_dp); | |
2129 | } | |
24d05927 DV |
2130 | kfree(intel_dp); |
2131 | } | |
2132 | ||
a4fc5ed6 KP |
2133 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
2134 | .dpms = intel_dp_dpms, | |
2135 | .mode_fixup = intel_dp_mode_fixup, | |
d240f20f | 2136 | .prepare = intel_dp_prepare, |
a4fc5ed6 | 2137 | .mode_set = intel_dp_mode_set, |
d240f20f | 2138 | .commit = intel_dp_commit, |
a4fc5ed6 KP |
2139 | }; |
2140 | ||
2141 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
2142 | .dpms = drm_helper_connector_dpms, | |
a4fc5ed6 KP |
2143 | .detect = intel_dp_detect, |
2144 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 2145 | .set_property = intel_dp_set_property, |
a4fc5ed6 KP |
2146 | .destroy = intel_dp_destroy, |
2147 | }; | |
2148 | ||
2149 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
2150 | .get_modes = intel_dp_get_modes, | |
2151 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 2152 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
2153 | }; |
2154 | ||
a4fc5ed6 | 2155 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 2156 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
2157 | }; |
2158 | ||
995b6762 | 2159 | static void |
21d40d37 | 2160 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 2161 | { |
ea5b213a | 2162 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
c8110e52 | 2163 | |
885a5014 | 2164 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 2165 | } |
6207937d | 2166 | |
e3421a18 ZW |
2167 | /* Return which DP Port should be selected for Transcoder DP control */ |
2168 | int | |
0206e353 | 2169 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
e3421a18 ZW |
2170 | { |
2171 | struct drm_device *dev = crtc->dev; | |
2172 | struct drm_mode_config *mode_config = &dev->mode_config; | |
2173 | struct drm_encoder *encoder; | |
e3421a18 ZW |
2174 | |
2175 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a CW |
2176 | struct intel_dp *intel_dp; |
2177 | ||
d8201ab6 | 2178 | if (encoder->crtc != crtc) |
e3421a18 ZW |
2179 | continue; |
2180 | ||
ea5b213a CW |
2181 | intel_dp = enc_to_intel_dp(encoder); |
2182 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) | |
2183 | return intel_dp->output_reg; | |
e3421a18 | 2184 | } |
ea5b213a | 2185 | |
e3421a18 ZW |
2186 | return -1; |
2187 | } | |
2188 | ||
36e83a18 | 2189 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 2190 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
2191 | { |
2192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2193 | struct child_device_config *p_child; | |
2194 | int i; | |
2195 | ||
2196 | if (!dev_priv->child_dev_num) | |
2197 | return false; | |
2198 | ||
2199 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
2200 | p_child = dev_priv->child_dev + i; | |
2201 | ||
2202 | if (p_child->dvo_port == PORT_IDPD && | |
2203 | p_child->device_type == DEVICE_TYPE_eDP) | |
2204 | return true; | |
2205 | } | |
2206 | return false; | |
2207 | } | |
2208 | ||
f684960e CW |
2209 | static void |
2210 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
2211 | { | |
3f43c48d | 2212 | intel_attach_force_audio_property(connector); |
e953fd7b | 2213 | intel_attach_broadcast_rgb_property(connector); |
f684960e CW |
2214 | } |
2215 | ||
a4fc5ed6 KP |
2216 | void |
2217 | intel_dp_init(struct drm_device *dev, int output_reg) | |
2218 | { | |
2219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2220 | struct drm_connector *connector; | |
ea5b213a | 2221 | struct intel_dp *intel_dp; |
21d40d37 | 2222 | struct intel_encoder *intel_encoder; |
55f78c43 | 2223 | struct intel_connector *intel_connector; |
5eb08b69 | 2224 | const char *name = NULL; |
b329530c | 2225 | int type; |
a4fc5ed6 | 2226 | |
ea5b213a CW |
2227 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
2228 | if (!intel_dp) | |
a4fc5ed6 KP |
2229 | return; |
2230 | ||
3d3dc149 | 2231 | intel_dp->output_reg = output_reg; |
d2b996ac | 2232 | intel_dp->dpms_mode = -1; |
3d3dc149 | 2233 | |
55f78c43 ZW |
2234 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
2235 | if (!intel_connector) { | |
ea5b213a | 2236 | kfree(intel_dp); |
55f78c43 ZW |
2237 | return; |
2238 | } | |
ea5b213a | 2239 | intel_encoder = &intel_dp->base; |
55f78c43 | 2240 | |
ea5b213a | 2241 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
b329530c | 2242 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 2243 | intel_dp->is_pch_edp = true; |
b329530c | 2244 | |
cfcb0fc9 | 2245 | if (output_reg == DP_A || is_pch_edp(intel_dp)) { |
b329530c AJ |
2246 | type = DRM_MODE_CONNECTOR_eDP; |
2247 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
2248 | } else { | |
2249 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
2250 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
2251 | } | |
2252 | ||
55f78c43 | 2253 | connector = &intel_connector->base; |
b329530c | 2254 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
2255 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
2256 | ||
eb1f8e4f DA |
2257 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
2258 | ||
652af9d7 | 2259 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
21d40d37 | 2260 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
652af9d7 | 2261 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
21d40d37 | 2262 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
652af9d7 | 2263 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
21d40d37 | 2264 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
f8aed700 | 2265 | |
bd943159 | 2266 | if (is_edp(intel_dp)) { |
21d40d37 | 2267 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
bd943159 KP |
2268 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
2269 | ironlake_panel_vdd_work); | |
2270 | } | |
6251ec0a | 2271 | |
27f8227b | 2272 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
a4fc5ed6 KP |
2273 | connector->interlace_allowed = true; |
2274 | connector->doublescan_allowed = 0; | |
2275 | ||
4ef69c7a | 2276 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
a4fc5ed6 | 2277 | DRM_MODE_ENCODER_TMDS); |
4ef69c7a | 2278 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
a4fc5ed6 | 2279 | |
df0e9248 | 2280 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
2281 | drm_sysfs_connector_add(connector); |
2282 | ||
2283 | /* Set up the DDC bus. */ | |
5eb08b69 | 2284 | switch (output_reg) { |
32f9d658 ZW |
2285 | case DP_A: |
2286 | name = "DPDDC-A"; | |
2287 | break; | |
5eb08b69 ZW |
2288 | case DP_B: |
2289 | case PCH_DP_B: | |
b01f2c3a JB |
2290 | dev_priv->hotplug_supported_mask |= |
2291 | HDMIB_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2292 | name = "DPDDC-B"; |
2293 | break; | |
2294 | case DP_C: | |
2295 | case PCH_DP_C: | |
b01f2c3a JB |
2296 | dev_priv->hotplug_supported_mask |= |
2297 | HDMIC_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2298 | name = "DPDDC-C"; |
2299 | break; | |
2300 | case DP_D: | |
2301 | case PCH_DP_D: | |
b01f2c3a JB |
2302 | dev_priv->hotplug_supported_mask |= |
2303 | HDMID_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2304 | name = "DPDDC-D"; |
2305 | break; | |
2306 | } | |
2307 | ||
89667383 JB |
2308 | /* Cache some DPCD data in the eDP case */ |
2309 | if (is_edp(intel_dp)) { | |
59f3e272 | 2310 | bool ret; |
f01eca2e KP |
2311 | struct edp_power_seq cur, vbt; |
2312 | u32 pp_on, pp_off, pp_div; | |
5d613501 JB |
2313 | |
2314 | pp_on = I915_READ(PCH_PP_ON_DELAYS); | |
f01eca2e | 2315 | pp_off = I915_READ(PCH_PP_OFF_DELAYS); |
5d613501 | 2316 | pp_div = I915_READ(PCH_PP_DIVISOR); |
89667383 | 2317 | |
f01eca2e KP |
2318 | /* Pull timing values out of registers */ |
2319 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
2320 | PANEL_POWER_UP_DELAY_SHIFT; | |
2321 | ||
2322 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
2323 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
2324 | ||
2325 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
2326 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
2327 | ||
2328 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
2329 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
2330 | ||
2331 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
2332 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
2333 | ||
2334 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2335 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
2336 | ||
2337 | vbt = dev_priv->edp.pps; | |
2338 | ||
2339 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2340 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
2341 | ||
2342 | #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10) | |
2343 | ||
2344 | intel_dp->panel_power_up_delay = get_delay(t1_t3); | |
2345 | intel_dp->backlight_on_delay = get_delay(t8); | |
2346 | intel_dp->backlight_off_delay = get_delay(t9); | |
2347 | intel_dp->panel_power_down_delay = get_delay(t10); | |
2348 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
2349 | ||
2350 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", | |
2351 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
2352 | intel_dp->panel_power_cycle_delay); | |
2353 | ||
2354 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
2355 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
5d613501 | 2356 | |
bd943159 | 2357 | intel_dp->panel_off_jiffies = jiffies - intel_dp->panel_power_down_delay; |
5d613501 JB |
2358 | |
2359 | ironlake_edp_panel_vdd_on(intel_dp); | |
59f3e272 | 2360 | ret = intel_dp_get_dpcd(intel_dp); |
bd943159 | 2361 | ironlake_edp_panel_vdd_off(intel_dp, false); |
59f3e272 | 2362 | if (ret) { |
7183dc29 JB |
2363 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
2364 | dev_priv->no_aux_handshake = | |
2365 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
89667383 JB |
2366 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
2367 | } else { | |
3d3dc149 | 2368 | /* if this fails, presume the device is a ghost */ |
48898b03 | 2369 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
3d3dc149 | 2370 | intel_dp_encoder_destroy(&intel_dp->base.base); |
48898b03 | 2371 | intel_dp_destroy(&intel_connector->base); |
3d3dc149 | 2372 | return; |
89667383 | 2373 | } |
89667383 JB |
2374 | } |
2375 | ||
552fb0b7 KP |
2376 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
2377 | ||
21d40d37 | 2378 | intel_encoder->hot_plug = intel_dp_hot_plug; |
a4fc5ed6 | 2379 | |
4d926461 | 2380 | if (is_edp(intel_dp)) { |
aaa6fd2a MG |
2381 | dev_priv->int_edp_connector = connector; |
2382 | intel_panel_setup_backlight(dev); | |
32f9d658 ZW |
2383 | } |
2384 | ||
f684960e CW |
2385 | intel_dp_add_properties(intel_dp, connector); |
2386 | ||
a4fc5ed6 KP |
2387 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
2388 | * 0xd. Failure to do so will result in spurious interrupts being | |
2389 | * generated on the port when a cable is not attached. | |
2390 | */ | |
2391 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
2392 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
2393 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2394 | } | |
2395 | } |