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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
a4fc5ed6 KP |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "drm_crtc.h" | |
34 | #include "drm_crtc_helper.h" | |
35 | #include "intel_drv.h" | |
36 | #include "i915_drm.h" | |
37 | #include "i915_drv.h" | |
ab2c0672 | 38 | #include "drm_dp_helper.h" |
a4fc5ed6 | 39 | |
a2006cf5 | 40 | #define DP_RECEIVER_CAP_SIZE 0xf |
a4fc5ed6 KP |
41 | #define DP_LINK_STATUS_SIZE 6 |
42 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) | |
43 | ||
44 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
45 | ||
ea5b213a CW |
46 | struct intel_dp { |
47 | struct intel_encoder base; | |
a4fc5ed6 KP |
48 | uint32_t output_reg; |
49 | uint32_t DP; | |
50 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
a4fc5ed6 | 51 | bool has_audio; |
f684960e | 52 | int force_audio; |
e953fd7b | 53 | uint32_t color_range; |
d2b996ac | 54 | int dpms_mode; |
a4fc5ed6 KP |
55 | uint8_t link_bw; |
56 | uint8_t lane_count; | |
a2006cf5 | 57 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
a4fc5ed6 KP |
58 | struct i2c_adapter adapter; |
59 | struct i2c_algo_dp_aux_data algo; | |
f0917379 | 60 | bool is_pch_edp; |
33a34e4e | 61 | uint8_t train_set[4]; |
f01eca2e KP |
62 | int panel_power_up_delay; |
63 | int panel_power_down_delay; | |
64 | int panel_power_cycle_delay; | |
65 | int backlight_on_delay; | |
66 | int backlight_off_delay; | |
d15456de | 67 | struct drm_display_mode *panel_fixed_mode; /* for eDP */ |
bd943159 KP |
68 | struct delayed_work panel_vdd_work; |
69 | bool want_panel_vdd; | |
a4fc5ed6 KP |
70 | }; |
71 | ||
cfcb0fc9 JB |
72 | /** |
73 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
74 | * @intel_dp: DP struct | |
75 | * | |
76 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
77 | * will return true, and false otherwise. | |
78 | */ | |
79 | static bool is_edp(struct intel_dp *intel_dp) | |
80 | { | |
81 | return intel_dp->base.type == INTEL_OUTPUT_EDP; | |
82 | } | |
83 | ||
84 | /** | |
85 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? | |
86 | * @intel_dp: DP struct | |
87 | * | |
88 | * Returns true if the given DP struct corresponds to a PCH DP port attached | |
89 | * to an eDP panel, false otherwise. Helpful for determining whether we | |
90 | * may need FDI resources for a given DP output or not. | |
91 | */ | |
92 | static bool is_pch_edp(struct intel_dp *intel_dp) | |
93 | { | |
94 | return intel_dp->is_pch_edp; | |
95 | } | |
96 | ||
1c95822a AJ |
97 | /** |
98 | * is_cpu_edp - is the port on the CPU and attached to an eDP panel? | |
99 | * @intel_dp: DP struct | |
100 | * | |
101 | * Returns true if the given DP struct corresponds to a CPU eDP port. | |
102 | */ | |
103 | static bool is_cpu_edp(struct intel_dp *intel_dp) | |
104 | { | |
105 | return is_edp(intel_dp) && !is_pch_edp(intel_dp); | |
106 | } | |
107 | ||
ea5b213a CW |
108 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
109 | { | |
4ef69c7a | 110 | return container_of(encoder, struct intel_dp, base.base); |
ea5b213a | 111 | } |
a4fc5ed6 | 112 | |
df0e9248 CW |
113 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
114 | { | |
115 | return container_of(intel_attached_encoder(connector), | |
116 | struct intel_dp, base); | |
117 | } | |
118 | ||
814948ad JB |
119 | /** |
120 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? | |
121 | * @encoder: DRM encoder | |
122 | * | |
123 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed | |
124 | * by intel_display.c. | |
125 | */ | |
126 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) | |
127 | { | |
128 | struct intel_dp *intel_dp; | |
129 | ||
130 | if (!encoder) | |
131 | return false; | |
132 | ||
133 | intel_dp = enc_to_intel_dp(encoder); | |
134 | ||
135 | return is_pch_edp(intel_dp); | |
136 | } | |
137 | ||
33a34e4e JB |
138 | static void intel_dp_start_link_train(struct intel_dp *intel_dp); |
139 | static void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
ea5b213a | 140 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
a4fc5ed6 | 141 | |
32f9d658 | 142 | void |
0206e353 | 143 | intel_edp_link_config(struct intel_encoder *intel_encoder, |
ea5b213a | 144 | int *lane_num, int *link_bw) |
32f9d658 | 145 | { |
ea5b213a | 146 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
32f9d658 | 147 | |
ea5b213a CW |
148 | *lane_num = intel_dp->lane_count; |
149 | if (intel_dp->link_bw == DP_LINK_BW_1_62) | |
32f9d658 | 150 | *link_bw = 162000; |
ea5b213a | 151 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
32f9d658 ZW |
152 | *link_bw = 270000; |
153 | } | |
154 | ||
a4fc5ed6 | 155 | static int |
ea5b213a | 156 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
a4fc5ed6 | 157 | { |
9a10f401 KP |
158 | int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; |
159 | switch (max_lane_count) { | |
160 | case 1: case 2: case 4: | |
161 | break; | |
162 | default: | |
163 | max_lane_count = 4; | |
a4fc5ed6 KP |
164 | } |
165 | return max_lane_count; | |
166 | } | |
167 | ||
168 | static int | |
ea5b213a | 169 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 170 | { |
7183dc29 | 171 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
172 | |
173 | switch (max_link_bw) { | |
174 | case DP_LINK_BW_1_62: | |
175 | case DP_LINK_BW_2_7: | |
176 | break; | |
177 | default: | |
178 | max_link_bw = DP_LINK_BW_1_62; | |
179 | break; | |
180 | } | |
181 | return max_link_bw; | |
182 | } | |
183 | ||
184 | static int | |
185 | intel_dp_link_clock(uint8_t link_bw) | |
186 | { | |
187 | if (link_bw == DP_LINK_BW_2_7) | |
188 | return 270000; | |
189 | else | |
190 | return 162000; | |
191 | } | |
192 | ||
cd9dde44 AJ |
193 | /* |
194 | * The units on the numbers in the next two are... bizarre. Examples will | |
195 | * make it clearer; this one parallels an example in the eDP spec. | |
196 | * | |
197 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
198 | * | |
199 | * 270000 * 1 * 8 / 10 == 216000 | |
200 | * | |
201 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
202 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
203 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
204 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
205 | * | |
206 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
207 | * get the result in decakilobits instead of kilobits. | |
208 | */ | |
209 | ||
a4fc5ed6 | 210 | static int |
cd9dde44 | 211 | intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock) |
a4fc5ed6 | 212 | { |
89c61432 JB |
213 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
215 | int bpp = 24; | |
885a5fb5 | 216 | |
89c61432 JB |
217 | if (intel_crtc) |
218 | bpp = intel_crtc->bpp; | |
219 | ||
cd9dde44 | 220 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
221 | } |
222 | ||
fe27d53e DA |
223 | static int |
224 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
225 | { | |
226 | return (max_link_clock * max_lanes * 8) / 10; | |
227 | } | |
228 | ||
a4fc5ed6 KP |
229 | static int |
230 | intel_dp_mode_valid(struct drm_connector *connector, | |
231 | struct drm_display_mode *mode) | |
232 | { | |
df0e9248 | 233 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
ea5b213a CW |
234 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
235 | int max_lanes = intel_dp_max_lane_count(intel_dp); | |
a4fc5ed6 | 236 | |
d15456de KP |
237 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
238 | if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay) | |
7de56f43 ZY |
239 | return MODE_PANEL; |
240 | ||
d15456de | 241 | if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay) |
7de56f43 ZY |
242 | return MODE_PANEL; |
243 | } | |
244 | ||
dc22ee6f AJ |
245 | if (intel_dp_link_required(intel_dp, mode->clock) |
246 | > intel_dp_max_data_rate(max_link_clock, max_lanes)) | |
a4fc5ed6 KP |
247 | return MODE_CLOCK_HIGH; |
248 | ||
249 | if (mode->clock < 10000) | |
250 | return MODE_CLOCK_LOW; | |
251 | ||
252 | return MODE_OK; | |
253 | } | |
254 | ||
255 | static uint32_t | |
256 | pack_aux(uint8_t *src, int src_bytes) | |
257 | { | |
258 | int i; | |
259 | uint32_t v = 0; | |
260 | ||
261 | if (src_bytes > 4) | |
262 | src_bytes = 4; | |
263 | for (i = 0; i < src_bytes; i++) | |
264 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
265 | return v; | |
266 | } | |
267 | ||
268 | static void | |
269 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
270 | { | |
271 | int i; | |
272 | if (dst_bytes > 4) | |
273 | dst_bytes = 4; | |
274 | for (i = 0; i < dst_bytes; i++) | |
275 | dst[i] = src >> ((3-i) * 8); | |
276 | } | |
277 | ||
fb0f8fbf KP |
278 | /* hrawclock is 1/4 the FSB frequency */ |
279 | static int | |
280 | intel_hrawclk(struct drm_device *dev) | |
281 | { | |
282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
283 | uint32_t clkcfg; | |
284 | ||
285 | clkcfg = I915_READ(CLKCFG); | |
286 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
287 | case CLKCFG_FSB_400: | |
288 | return 100; | |
289 | case CLKCFG_FSB_533: | |
290 | return 133; | |
291 | case CLKCFG_FSB_667: | |
292 | return 166; | |
293 | case CLKCFG_FSB_800: | |
294 | return 200; | |
295 | case CLKCFG_FSB_1067: | |
296 | return 266; | |
297 | case CLKCFG_FSB_1333: | |
298 | return 333; | |
299 | /* these two are just a guess; one of them might be right */ | |
300 | case CLKCFG_FSB_1600: | |
301 | case CLKCFG_FSB_1600_ALT: | |
302 | return 400; | |
303 | default: | |
304 | return 133; | |
305 | } | |
306 | } | |
307 | ||
ebf33b18 KP |
308 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
309 | { | |
310 | struct drm_device *dev = intel_dp->base.base.dev; | |
311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
312 | ||
313 | return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; | |
314 | } | |
315 | ||
316 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) | |
317 | { | |
318 | struct drm_device *dev = intel_dp->base.base.dev; | |
319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
320 | ||
321 | return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; | |
322 | } | |
323 | ||
9b984dae KP |
324 | static void |
325 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
326 | { | |
327 | struct drm_device *dev = intel_dp->base.base.dev; | |
328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ebf33b18 | 329 | |
9b984dae KP |
330 | if (!is_edp(intel_dp)) |
331 | return; | |
ebf33b18 | 332 | if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
333 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
334 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
ebf33b18 | 335 | I915_READ(PCH_PP_STATUS), |
9b984dae KP |
336 | I915_READ(PCH_PP_CONTROL)); |
337 | } | |
338 | } | |
339 | ||
a4fc5ed6 | 340 | static int |
ea5b213a | 341 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
342 | uint8_t *send, int send_bytes, |
343 | uint8_t *recv, int recv_size) | |
344 | { | |
ea5b213a | 345 | uint32_t output_reg = intel_dp->output_reg; |
4ef69c7a | 346 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 KP |
347 | struct drm_i915_private *dev_priv = dev->dev_private; |
348 | uint32_t ch_ctl = output_reg + 0x10; | |
349 | uint32_t ch_data = ch_ctl + 4; | |
350 | int i; | |
351 | int recv_bytes; | |
a4fc5ed6 | 352 | uint32_t status; |
fb0f8fbf | 353 | uint32_t aux_clock_divider; |
e3421a18 | 354 | int try, precharge; |
a4fc5ed6 | 355 | |
9b984dae | 356 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 | 357 | /* The clock divider is based off the hrawclk, |
fb0f8fbf KP |
358 | * and would like to run at 2MHz. So, take the |
359 | * hrawclk value and divide by 2 and use that | |
6176b8f9 JB |
360 | * |
361 | * Note that PCH attached eDP panels should use a 125MHz input | |
362 | * clock divider. | |
a4fc5ed6 | 363 | */ |
1c95822a | 364 | if (is_cpu_edp(intel_dp)) { |
e3421a18 ZW |
365 | if (IS_GEN6(dev)) |
366 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ | |
367 | else | |
368 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
369 | } else if (HAS_PCH_SPLIT(dev)) | |
f2b115e6 | 370 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
5eb08b69 ZW |
371 | else |
372 | aux_clock_divider = intel_hrawclk(dev) / 2; | |
373 | ||
e3421a18 ZW |
374 | if (IS_GEN6(dev)) |
375 | precharge = 3; | |
376 | else | |
377 | precharge = 5; | |
378 | ||
11bee43e JB |
379 | /* Try to wait for any previous AUX channel activity */ |
380 | for (try = 0; try < 3; try++) { | |
381 | status = I915_READ(ch_ctl); | |
382 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
383 | break; | |
384 | msleep(1); | |
385 | } | |
386 | ||
387 | if (try == 3) { | |
388 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
389 | I915_READ(ch_ctl)); | |
4f7f7b7e CW |
390 | return -EBUSY; |
391 | } | |
392 | ||
fb0f8fbf KP |
393 | /* Must try at least 3 times according to DP spec */ |
394 | for (try = 0; try < 5; try++) { | |
395 | /* Load the send data into the aux channel data registers */ | |
4f7f7b7e CW |
396 | for (i = 0; i < send_bytes; i += 4) |
397 | I915_WRITE(ch_data + i, | |
398 | pack_aux(send + i, send_bytes - i)); | |
0206e353 | 399 | |
fb0f8fbf | 400 | /* Send the command and wait for it to complete */ |
4f7f7b7e CW |
401 | I915_WRITE(ch_ctl, |
402 | DP_AUX_CH_CTL_SEND_BUSY | | |
403 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
404 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
405 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
406 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
407 | DP_AUX_CH_CTL_DONE | | |
408 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
409 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
fb0f8fbf | 410 | for (;;) { |
fb0f8fbf KP |
411 | status = I915_READ(ch_ctl); |
412 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
413 | break; | |
4f7f7b7e | 414 | udelay(100); |
fb0f8fbf | 415 | } |
0206e353 | 416 | |
fb0f8fbf | 417 | /* Clear done status and any errors */ |
4f7f7b7e CW |
418 | I915_WRITE(ch_ctl, |
419 | status | | |
420 | DP_AUX_CH_CTL_DONE | | |
421 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
422 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
423 | if (status & DP_AUX_CH_CTL_DONE) | |
a4fc5ed6 KP |
424 | break; |
425 | } | |
426 | ||
a4fc5ed6 | 427 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 428 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
a5b3da54 | 429 | return -EBUSY; |
a4fc5ed6 KP |
430 | } |
431 | ||
432 | /* Check for timeout or receive error. | |
433 | * Timeouts occur when the sink is not connected | |
434 | */ | |
a5b3da54 | 435 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 436 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
a5b3da54 KP |
437 | return -EIO; |
438 | } | |
1ae8c0a5 KP |
439 | |
440 | /* Timeouts occur when the device isn't connected, so they're | |
441 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 442 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 443 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
a5b3da54 | 444 | return -ETIMEDOUT; |
a4fc5ed6 KP |
445 | } |
446 | ||
447 | /* Unload any bytes sent back from the other side */ | |
448 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
449 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
450 | if (recv_bytes > recv_size) |
451 | recv_bytes = recv_size; | |
0206e353 | 452 | |
4f7f7b7e CW |
453 | for (i = 0; i < recv_bytes; i += 4) |
454 | unpack_aux(I915_READ(ch_data + i), | |
455 | recv + i, recv_bytes - i); | |
a4fc5ed6 KP |
456 | |
457 | return recv_bytes; | |
458 | } | |
459 | ||
460 | /* Write data to the aux channel in native mode */ | |
461 | static int | |
ea5b213a | 462 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
463 | uint16_t address, uint8_t *send, int send_bytes) |
464 | { | |
465 | int ret; | |
466 | uint8_t msg[20]; | |
467 | int msg_bytes; | |
468 | uint8_t ack; | |
469 | ||
9b984dae | 470 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
471 | if (send_bytes > 16) |
472 | return -1; | |
473 | msg[0] = AUX_NATIVE_WRITE << 4; | |
474 | msg[1] = address >> 8; | |
eebc863e | 475 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
476 | msg[3] = send_bytes - 1; |
477 | memcpy(&msg[4], send, send_bytes); | |
478 | msg_bytes = send_bytes + 4; | |
479 | for (;;) { | |
ea5b213a | 480 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
481 | if (ret < 0) |
482 | return ret; | |
483 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
484 | break; | |
485 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
486 | udelay(100); | |
487 | else | |
a5b3da54 | 488 | return -EIO; |
a4fc5ed6 KP |
489 | } |
490 | return send_bytes; | |
491 | } | |
492 | ||
493 | /* Write a single byte to the aux channel in native mode */ | |
494 | static int | |
ea5b213a | 495 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
496 | uint16_t address, uint8_t byte) |
497 | { | |
ea5b213a | 498 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
499 | } |
500 | ||
501 | /* read bytes from a native aux channel */ | |
502 | static int | |
ea5b213a | 503 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
504 | uint16_t address, uint8_t *recv, int recv_bytes) |
505 | { | |
506 | uint8_t msg[4]; | |
507 | int msg_bytes; | |
508 | uint8_t reply[20]; | |
509 | int reply_bytes; | |
510 | uint8_t ack; | |
511 | int ret; | |
512 | ||
9b984dae | 513 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
514 | msg[0] = AUX_NATIVE_READ << 4; |
515 | msg[1] = address >> 8; | |
516 | msg[2] = address & 0xff; | |
517 | msg[3] = recv_bytes - 1; | |
518 | ||
519 | msg_bytes = 4; | |
520 | reply_bytes = recv_bytes + 1; | |
521 | ||
522 | for (;;) { | |
ea5b213a | 523 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 524 | reply, reply_bytes); |
a5b3da54 KP |
525 | if (ret == 0) |
526 | return -EPROTO; | |
527 | if (ret < 0) | |
a4fc5ed6 KP |
528 | return ret; |
529 | ack = reply[0]; | |
530 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
531 | memcpy(recv, reply + 1, ret - 1); | |
532 | return ret - 1; | |
533 | } | |
534 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
535 | udelay(100); | |
536 | else | |
a5b3da54 | 537 | return -EIO; |
a4fc5ed6 KP |
538 | } |
539 | } | |
540 | ||
541 | static int | |
ab2c0672 DA |
542 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
543 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 544 | { |
ab2c0672 | 545 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
546 | struct intel_dp *intel_dp = container_of(adapter, |
547 | struct intel_dp, | |
548 | adapter); | |
ab2c0672 DA |
549 | uint16_t address = algo_data->address; |
550 | uint8_t msg[5]; | |
551 | uint8_t reply[2]; | |
8316f337 | 552 | unsigned retry; |
ab2c0672 DA |
553 | int msg_bytes; |
554 | int reply_bytes; | |
555 | int ret; | |
556 | ||
9b984dae | 557 | intel_dp_check_edp(intel_dp); |
ab2c0672 DA |
558 | /* Set up the command byte */ |
559 | if (mode & MODE_I2C_READ) | |
560 | msg[0] = AUX_I2C_READ << 4; | |
561 | else | |
562 | msg[0] = AUX_I2C_WRITE << 4; | |
563 | ||
564 | if (!(mode & MODE_I2C_STOP)) | |
565 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 566 | |
ab2c0672 DA |
567 | msg[1] = address >> 8; |
568 | msg[2] = address; | |
569 | ||
570 | switch (mode) { | |
571 | case MODE_I2C_WRITE: | |
572 | msg[3] = 0; | |
573 | msg[4] = write_byte; | |
574 | msg_bytes = 5; | |
575 | reply_bytes = 1; | |
576 | break; | |
577 | case MODE_I2C_READ: | |
578 | msg[3] = 0; | |
579 | msg_bytes = 4; | |
580 | reply_bytes = 2; | |
581 | break; | |
582 | default: | |
583 | msg_bytes = 3; | |
584 | reply_bytes = 1; | |
585 | break; | |
586 | } | |
587 | ||
8316f337 DF |
588 | for (retry = 0; retry < 5; retry++) { |
589 | ret = intel_dp_aux_ch(intel_dp, | |
590 | msg, msg_bytes, | |
591 | reply, reply_bytes); | |
ab2c0672 | 592 | if (ret < 0) { |
3ff99164 | 593 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
594 | return ret; |
595 | } | |
8316f337 DF |
596 | |
597 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { | |
598 | case AUX_NATIVE_REPLY_ACK: | |
599 | /* I2C-over-AUX Reply field is only valid | |
600 | * when paired with AUX ACK. | |
601 | */ | |
602 | break; | |
603 | case AUX_NATIVE_REPLY_NACK: | |
604 | DRM_DEBUG_KMS("aux_ch native nack\n"); | |
605 | return -EREMOTEIO; | |
606 | case AUX_NATIVE_REPLY_DEFER: | |
607 | udelay(100); | |
608 | continue; | |
609 | default: | |
610 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", | |
611 | reply[0]); | |
612 | return -EREMOTEIO; | |
613 | } | |
614 | ||
ab2c0672 DA |
615 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
616 | case AUX_I2C_REPLY_ACK: | |
617 | if (mode == MODE_I2C_READ) { | |
618 | *read_byte = reply[1]; | |
619 | } | |
620 | return reply_bytes - 1; | |
621 | case AUX_I2C_REPLY_NACK: | |
8316f337 | 622 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
ab2c0672 DA |
623 | return -EREMOTEIO; |
624 | case AUX_I2C_REPLY_DEFER: | |
8316f337 | 625 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
ab2c0672 DA |
626 | udelay(100); |
627 | break; | |
628 | default: | |
8316f337 | 629 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
ab2c0672 DA |
630 | return -EREMOTEIO; |
631 | } | |
632 | } | |
8316f337 DF |
633 | |
634 | DRM_ERROR("too many retries, giving up\n"); | |
635 | return -EREMOTEIO; | |
a4fc5ed6 KP |
636 | } |
637 | ||
0b5c541b | 638 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
bd943159 | 639 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
0b5c541b | 640 | |
a4fc5ed6 | 641 | static int |
ea5b213a | 642 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 643 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 644 | { |
0b5c541b KP |
645 | int ret; |
646 | ||
d54e9d28 | 647 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
648 | intel_dp->algo.running = false; |
649 | intel_dp->algo.address = 0; | |
650 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
651 | ||
0206e353 | 652 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
ea5b213a CW |
653 | intel_dp->adapter.owner = THIS_MODULE; |
654 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
0206e353 | 655 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
ea5b213a CW |
656 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
657 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
658 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
659 | ||
0b5c541b KP |
660 | ironlake_edp_panel_vdd_on(intel_dp); |
661 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); | |
bd943159 | 662 | ironlake_edp_panel_vdd_off(intel_dp, false); |
0b5c541b | 663 | return ret; |
a4fc5ed6 KP |
664 | } |
665 | ||
666 | static bool | |
667 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
668 | struct drm_display_mode *adjusted_mode) | |
669 | { | |
0d3a1bee | 670 | struct drm_device *dev = encoder->dev; |
ea5b213a | 671 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4fc5ed6 | 672 | int lane_count, clock; |
ea5b213a CW |
673 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
674 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; | |
a4fc5ed6 KP |
675 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
676 | ||
d15456de KP |
677 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
678 | intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode); | |
1d8e1c75 CW |
679 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, |
680 | mode, adjusted_mode); | |
0d3a1bee ZY |
681 | /* |
682 | * the mode->clock is used to calculate the Data&Link M/N | |
683 | * of the pipe. For the eDP the fixed clock should be used. | |
684 | */ | |
d15456de | 685 | mode->clock = intel_dp->panel_fixed_mode->clock; |
0d3a1bee ZY |
686 | } |
687 | ||
a4fc5ed6 KP |
688 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
689 | for (clock = 0; clock <= max_clock; clock++) { | |
fe27d53e | 690 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
a4fc5ed6 | 691 | |
cd9dde44 | 692 | if (intel_dp_link_required(intel_dp, mode->clock) |
885a5fb5 | 693 | <= link_avail) { |
ea5b213a CW |
694 | intel_dp->link_bw = bws[clock]; |
695 | intel_dp->lane_count = lane_count; | |
696 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
28c97730 ZY |
697 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
698 | "count %d clock %d\n", | |
ea5b213a | 699 | intel_dp->link_bw, intel_dp->lane_count, |
a4fc5ed6 KP |
700 | adjusted_mode->clock); |
701 | return true; | |
702 | } | |
703 | } | |
704 | } | |
fe27d53e | 705 | |
a4fc5ed6 KP |
706 | return false; |
707 | } | |
708 | ||
709 | struct intel_dp_m_n { | |
710 | uint32_t tu; | |
711 | uint32_t gmch_m; | |
712 | uint32_t gmch_n; | |
713 | uint32_t link_m; | |
714 | uint32_t link_n; | |
715 | }; | |
716 | ||
717 | static void | |
718 | intel_reduce_ratio(uint32_t *num, uint32_t *den) | |
719 | { | |
720 | while (*num > 0xffffff || *den > 0xffffff) { | |
721 | *num >>= 1; | |
722 | *den >>= 1; | |
723 | } | |
724 | } | |
725 | ||
726 | static void | |
36e83a18 | 727 | intel_dp_compute_m_n(int bpp, |
a4fc5ed6 KP |
728 | int nlanes, |
729 | int pixel_clock, | |
730 | int link_clock, | |
731 | struct intel_dp_m_n *m_n) | |
732 | { | |
733 | m_n->tu = 64; | |
36e83a18 | 734 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
a4fc5ed6 KP |
735 | m_n->gmch_n = link_clock * nlanes; |
736 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
737 | m_n->link_m = pixel_clock; | |
738 | m_n->link_n = link_clock; | |
739 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
740 | } | |
741 | ||
742 | void | |
743 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
744 | struct drm_display_mode *adjusted_mode) | |
745 | { | |
746 | struct drm_device *dev = crtc->dev; | |
747 | struct drm_mode_config *mode_config = &dev->mode_config; | |
55f78c43 | 748 | struct drm_encoder *encoder; |
a4fc5ed6 KP |
749 | struct drm_i915_private *dev_priv = dev->dev_private; |
750 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
858fa035 | 751 | int lane_count = 4; |
a4fc5ed6 | 752 | struct intel_dp_m_n m_n; |
9db4a9c7 | 753 | int pipe = intel_crtc->pipe; |
a4fc5ed6 KP |
754 | |
755 | /* | |
21d40d37 | 756 | * Find the lane count in the intel_encoder private |
a4fc5ed6 | 757 | */ |
55f78c43 | 758 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
ea5b213a | 759 | struct intel_dp *intel_dp; |
a4fc5ed6 | 760 | |
d8201ab6 | 761 | if (encoder->crtc != crtc) |
a4fc5ed6 KP |
762 | continue; |
763 | ||
ea5b213a | 764 | intel_dp = enc_to_intel_dp(encoder); |
9a10f401 KP |
765 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || |
766 | intel_dp->base.type == INTEL_OUTPUT_EDP) | |
767 | { | |
ea5b213a | 768 | lane_count = intel_dp->lane_count; |
51190667 | 769 | break; |
a4fc5ed6 KP |
770 | } |
771 | } | |
772 | ||
773 | /* | |
774 | * Compute the GMCH and Link ratios. The '3' here is | |
775 | * the number of bytes_per_pixel post-LUT, which we always | |
776 | * set up for 8-bits of R/G/B, or 3 bytes total. | |
777 | */ | |
858fa035 | 778 | intel_dp_compute_m_n(intel_crtc->bpp, lane_count, |
a4fc5ed6 KP |
779 | mode->clock, adjusted_mode->clock, &m_n); |
780 | ||
c619eed4 | 781 | if (HAS_PCH_SPLIT(dev)) { |
9db4a9c7 JB |
782 | I915_WRITE(TRANSDATA_M1(pipe), |
783 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
784 | m_n.gmch_m); | |
785 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); | |
786 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); | |
787 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); | |
a4fc5ed6 | 788 | } else { |
9db4a9c7 JB |
789 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
790 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
791 | m_n.gmch_m); | |
792 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); | |
793 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); | |
794 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); | |
a4fc5ed6 KP |
795 | } |
796 | } | |
797 | ||
f01eca2e KP |
798 | static void ironlake_edp_pll_on(struct drm_encoder *encoder); |
799 | static void ironlake_edp_pll_off(struct drm_encoder *encoder); | |
800 | ||
a4fc5ed6 KP |
801 | static void |
802 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
803 | struct drm_display_mode *adjusted_mode) | |
804 | { | |
e3421a18 | 805 | struct drm_device *dev = encoder->dev; |
417e822d | 806 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 807 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4ef69c7a | 808 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
a4fc5ed6 KP |
809 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
810 | ||
f01eca2e KP |
811 | /* Turn on the eDP PLL if needed */ |
812 | if (is_edp(intel_dp)) { | |
813 | if (!is_pch_edp(intel_dp)) | |
814 | ironlake_edp_pll_on(encoder); | |
815 | else | |
816 | ironlake_edp_pll_off(encoder); | |
817 | } | |
818 | ||
417e822d KP |
819 | /* |
820 | * There are three kinds of DP registers: | |
821 | * | |
822 | * IBX PCH | |
823 | * CPU | |
824 | * CPT PCH | |
825 | * | |
826 | * IBX PCH and CPU are the same for almost everything, | |
827 | * except that the CPU DP PLL is configured in this | |
828 | * register | |
829 | * | |
830 | * CPT PCH is quite different, having many bits moved | |
831 | * to the TRANS_DP_CTL register instead. That | |
832 | * configuration happens (oddly) in ironlake_pch_enable | |
833 | */ | |
9c9e7927 | 834 | |
417e822d KP |
835 | /* Preserve the BIOS-computed detected bit. This is |
836 | * supposed to be read-only. | |
837 | */ | |
838 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
839 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
a4fc5ed6 | 840 | |
417e822d KP |
841 | /* Handle DP bits in common between all three register formats */ |
842 | ||
843 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
a4fc5ed6 | 844 | |
ea5b213a | 845 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 846 | case 1: |
ea5b213a | 847 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
848 | break; |
849 | case 2: | |
ea5b213a | 850 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
851 | break; |
852 | case 4: | |
ea5b213a | 853 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
854 | break; |
855 | } | |
e0dac65e WF |
856 | if (intel_dp->has_audio) { |
857 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", | |
858 | pipe_name(intel_crtc->pipe)); | |
ea5b213a | 859 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
e0dac65e WF |
860 | intel_write_eld(encoder, adjusted_mode); |
861 | } | |
ea5b213a CW |
862 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
863 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
864 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
a2cab1b2 | 865 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
a4fc5ed6 | 866 | /* |
9962c925 | 867 | * Check for DPCD version > 1.1 and enhanced framing support |
a4fc5ed6 | 868 | */ |
7183dc29 JB |
869 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
870 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { | |
ea5b213a | 871 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
a4fc5ed6 KP |
872 | } |
873 | ||
417e822d | 874 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 875 | |
417e822d KP |
876 | if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { |
877 | intel_dp->DP |= intel_dp->color_range; | |
878 | ||
879 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
880 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
881 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
882 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
883 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
884 | ||
885 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) | |
886 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
887 | ||
888 | if (intel_crtc->pipe == 1) | |
889 | intel_dp->DP |= DP_PIPEB_SELECT; | |
890 | ||
891 | if (is_cpu_edp(intel_dp)) { | |
892 | /* don't miss out required setting for eDP */ | |
893 | intel_dp->DP |= DP_PLL_ENABLE; | |
894 | if (adjusted_mode->clock < 200000) | |
895 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; | |
896 | else | |
897 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
898 | } | |
899 | } else { | |
900 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
32f9d658 | 901 | } |
a4fc5ed6 KP |
902 | } |
903 | ||
99ea7127 KP |
904 | #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
905 | #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
906 | ||
907 | #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) | |
908 | #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
909 | ||
910 | #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) | |
911 | #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
912 | ||
913 | static void ironlake_wait_panel_status(struct intel_dp *intel_dp, | |
914 | u32 mask, | |
915 | u32 value) | |
bd943159 | 916 | { |
99ea7127 KP |
917 | struct drm_device *dev = intel_dp->base.base.dev; |
918 | struct drm_i915_private *dev_priv = dev->dev_private; | |
32ce697c | 919 | |
99ea7127 KP |
920 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
921 | mask, value, | |
922 | I915_READ(PCH_PP_STATUS), | |
923 | I915_READ(PCH_PP_CONTROL)); | |
32ce697c | 924 | |
99ea7127 KP |
925 | if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) { |
926 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", | |
927 | I915_READ(PCH_PP_STATUS), | |
928 | I915_READ(PCH_PP_CONTROL)); | |
32ce697c | 929 | } |
99ea7127 | 930 | } |
32ce697c | 931 | |
99ea7127 KP |
932 | static void ironlake_wait_panel_on(struct intel_dp *intel_dp) |
933 | { | |
934 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
935 | ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); | |
bd943159 KP |
936 | } |
937 | ||
99ea7127 KP |
938 | static void ironlake_wait_panel_off(struct intel_dp *intel_dp) |
939 | { | |
940 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
941 | ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); | |
942 | } | |
943 | ||
944 | static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) | |
945 | { | |
946 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); | |
947 | ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); | |
948 | } | |
949 | ||
950 | ||
832dd3c1 KP |
951 | /* Read the current pp_control value, unlocking the register if it |
952 | * is locked | |
953 | */ | |
954 | ||
955 | static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv) | |
956 | { | |
957 | u32 control = I915_READ(PCH_PP_CONTROL); | |
958 | ||
959 | control &= ~PANEL_UNLOCK_MASK; | |
960 | control |= PANEL_UNLOCK_REGS; | |
961 | return control; | |
bd943159 KP |
962 | } |
963 | ||
5d613501 JB |
964 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
965 | { | |
966 | struct drm_device *dev = intel_dp->base.base.dev; | |
967 | struct drm_i915_private *dev_priv = dev->dev_private; | |
968 | u32 pp; | |
969 | ||
97af61f5 KP |
970 | if (!is_edp(intel_dp)) |
971 | return; | |
f01eca2e | 972 | DRM_DEBUG_KMS("Turn eDP VDD on\n"); |
5d613501 | 973 | |
bd943159 KP |
974 | WARN(intel_dp->want_panel_vdd, |
975 | "eDP VDD already requested on\n"); | |
976 | ||
977 | intel_dp->want_panel_vdd = true; | |
99ea7127 | 978 | |
bd943159 KP |
979 | if (ironlake_edp_have_panel_vdd(intel_dp)) { |
980 | DRM_DEBUG_KMS("eDP VDD already on\n"); | |
981 | return; | |
982 | } | |
983 | ||
99ea7127 KP |
984 | if (!ironlake_edp_have_panel_power(intel_dp)) |
985 | ironlake_wait_panel_power_cycle(intel_dp); | |
986 | ||
832dd3c1 | 987 | pp = ironlake_get_pp_control(dev_priv); |
5d613501 JB |
988 | pp |= EDP_FORCE_VDD; |
989 | I915_WRITE(PCH_PP_CONTROL, pp); | |
990 | POSTING_READ(PCH_PP_CONTROL); | |
f01eca2e KP |
991 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
992 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); | |
ebf33b18 KP |
993 | |
994 | /* | |
995 | * If the panel wasn't on, delay before accessing aux channel | |
996 | */ | |
997 | if (!ironlake_edp_have_panel_power(intel_dp)) { | |
bd943159 | 998 | DRM_DEBUG_KMS("eDP was not running\n"); |
f01eca2e | 999 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 1000 | } |
5d613501 JB |
1001 | } |
1002 | ||
bd943159 | 1003 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 JB |
1004 | { |
1005 | struct drm_device *dev = intel_dp->base.base.dev; | |
1006 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1007 | u32 pp; | |
1008 | ||
bd943159 | 1009 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
832dd3c1 | 1010 | pp = ironlake_get_pp_control(dev_priv); |
bd943159 KP |
1011 | pp &= ~EDP_FORCE_VDD; |
1012 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1013 | POSTING_READ(PCH_PP_CONTROL); | |
1014 | ||
1015 | /* Make sure sequencer is idle before allowing subsequent activity */ | |
1016 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", | |
1017 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); | |
99ea7127 KP |
1018 | |
1019 | msleep(intel_dp->panel_power_down_delay); | |
bd943159 KP |
1020 | } |
1021 | } | |
5d613501 | 1022 | |
bd943159 KP |
1023 | static void ironlake_panel_vdd_work(struct work_struct *__work) |
1024 | { | |
1025 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
1026 | struct intel_dp, panel_vdd_work); | |
1027 | struct drm_device *dev = intel_dp->base.base.dev; | |
1028 | ||
627f7675 | 1029 | mutex_lock(&dev->mode_config.mutex); |
bd943159 | 1030 | ironlake_panel_vdd_off_sync(intel_dp); |
627f7675 | 1031 | mutex_unlock(&dev->mode_config.mutex); |
bd943159 KP |
1032 | } |
1033 | ||
1034 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) | |
1035 | { | |
97af61f5 KP |
1036 | if (!is_edp(intel_dp)) |
1037 | return; | |
5d613501 | 1038 | |
bd943159 KP |
1039 | DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); |
1040 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); | |
f2e8b18a | 1041 | |
bd943159 KP |
1042 | intel_dp->want_panel_vdd = false; |
1043 | ||
1044 | if (sync) { | |
1045 | ironlake_panel_vdd_off_sync(intel_dp); | |
1046 | } else { | |
1047 | /* | |
1048 | * Queue the timer to fire a long | |
1049 | * time from now (relative to the power down delay) | |
1050 | * to keep the panel power up across a sequence of operations | |
1051 | */ | |
1052 | schedule_delayed_work(&intel_dp->panel_vdd_work, | |
1053 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
1054 | } | |
5d613501 JB |
1055 | } |
1056 | ||
86a3073e | 1057 | static void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 1058 | { |
01cb9ea6 | 1059 | struct drm_device *dev = intel_dp->base.base.dev; |
9934c132 | 1060 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1061 | u32 pp; |
9934c132 | 1062 | |
97af61f5 | 1063 | if (!is_edp(intel_dp)) |
bd943159 | 1064 | return; |
99ea7127 KP |
1065 | |
1066 | DRM_DEBUG_KMS("Turn eDP power on\n"); | |
1067 | ||
1068 | if (ironlake_edp_have_panel_power(intel_dp)) { | |
1069 | DRM_DEBUG_KMS("eDP power already on\n"); | |
7d639f35 | 1070 | return; |
99ea7127 | 1071 | } |
9934c132 | 1072 | |
99ea7127 | 1073 | ironlake_wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 1074 | |
99ea7127 | 1075 | pp = ironlake_get_pp_control(dev_priv); |
05ce1a49 KP |
1076 | if (IS_GEN5(dev)) { |
1077 | /* ILK workaround: disable reset around power sequence */ | |
1078 | pp &= ~PANEL_POWER_RESET; | |
1079 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1080 | POSTING_READ(PCH_PP_CONTROL); | |
1081 | } | |
37c6c9b0 | 1082 | |
1c0ae80a | 1083 | pp |= POWER_TARGET_ON; |
99ea7127 KP |
1084 | if (!IS_GEN5(dev)) |
1085 | pp |= PANEL_POWER_RESET; | |
1086 | ||
9934c132 | 1087 | I915_WRITE(PCH_PP_CONTROL, pp); |
01cb9ea6 | 1088 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 | 1089 | |
99ea7127 | 1090 | ironlake_wait_panel_on(intel_dp); |
9934c132 | 1091 | |
05ce1a49 KP |
1092 | if (IS_GEN5(dev)) { |
1093 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
1094 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1095 | POSTING_READ(PCH_PP_CONTROL); | |
1096 | } | |
9934c132 JB |
1097 | } |
1098 | ||
99ea7127 | 1099 | static void ironlake_edp_panel_off(struct intel_dp *intel_dp) |
9934c132 | 1100 | { |
99ea7127 | 1101 | struct drm_device *dev = intel_dp->base.base.dev; |
9934c132 | 1102 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1103 | u32 pp; |
9934c132 | 1104 | |
97af61f5 KP |
1105 | if (!is_edp(intel_dp)) |
1106 | return; | |
37c6c9b0 | 1107 | |
99ea7127 | 1108 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
37c6c9b0 | 1109 | |
99ea7127 | 1110 | WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n"); |
37c6c9b0 | 1111 | |
99ea7127 KP |
1112 | pp = ironlake_get_pp_control(dev_priv); |
1113 | pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); | |
1114 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1115 | POSTING_READ(PCH_PP_CONTROL); | |
9934c132 | 1116 | |
99ea7127 | 1117 | ironlake_wait_panel_off(intel_dp); |
9934c132 JB |
1118 | } |
1119 | ||
86a3073e | 1120 | static void ironlake_edp_backlight_on(struct intel_dp *intel_dp) |
32f9d658 | 1121 | { |
f01eca2e | 1122 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1123 | struct drm_i915_private *dev_priv = dev->dev_private; |
1124 | u32 pp; | |
1125 | ||
f01eca2e KP |
1126 | if (!is_edp(intel_dp)) |
1127 | return; | |
1128 | ||
28c97730 | 1129 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
1130 | /* |
1131 | * If we enable the backlight right away following a panel power | |
1132 | * on, we may see slight flicker as the panel syncs with the eDP | |
1133 | * link. So delay a bit to make sure the image is solid before | |
1134 | * allowing it to appear. | |
1135 | */ | |
f01eca2e | 1136 | msleep(intel_dp->backlight_on_delay); |
832dd3c1 | 1137 | pp = ironlake_get_pp_control(dev_priv); |
32f9d658 ZW |
1138 | pp |= EDP_BLC_ENABLE; |
1139 | I915_WRITE(PCH_PP_CONTROL, pp); | |
f01eca2e | 1140 | POSTING_READ(PCH_PP_CONTROL); |
32f9d658 ZW |
1141 | } |
1142 | ||
86a3073e | 1143 | static void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
32f9d658 | 1144 | { |
f01eca2e | 1145 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1146 | struct drm_i915_private *dev_priv = dev->dev_private; |
1147 | u32 pp; | |
1148 | ||
f01eca2e KP |
1149 | if (!is_edp(intel_dp)) |
1150 | return; | |
1151 | ||
28c97730 | 1152 | DRM_DEBUG_KMS("\n"); |
832dd3c1 | 1153 | pp = ironlake_get_pp_control(dev_priv); |
32f9d658 ZW |
1154 | pp &= ~EDP_BLC_ENABLE; |
1155 | I915_WRITE(PCH_PP_CONTROL, pp); | |
f01eca2e KP |
1156 | POSTING_READ(PCH_PP_CONTROL); |
1157 | msleep(intel_dp->backlight_off_delay); | |
32f9d658 | 1158 | } |
a4fc5ed6 | 1159 | |
d240f20f JB |
1160 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
1161 | { | |
1162 | struct drm_device *dev = encoder->dev; | |
1163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1164 | u32 dpa_ctl; | |
1165 | ||
1166 | DRM_DEBUG_KMS("\n"); | |
1167 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 1168 | dpa_ctl |= DP_PLL_ENABLE; |
d240f20f | 1169 | I915_WRITE(DP_A, dpa_ctl); |
298b0b39 JB |
1170 | POSTING_READ(DP_A); |
1171 | udelay(200); | |
d240f20f JB |
1172 | } |
1173 | ||
1174 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) | |
1175 | { | |
1176 | struct drm_device *dev = encoder->dev; | |
1177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1178 | u32 dpa_ctl; | |
1179 | ||
1180 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 1181 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 1182 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 1183 | POSTING_READ(DP_A); |
d240f20f JB |
1184 | udelay(200); |
1185 | } | |
1186 | ||
c7ad3810 JB |
1187 | /* If the sink supports it, try to set the power state appropriately */ |
1188 | static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) | |
1189 | { | |
1190 | int ret, i; | |
1191 | ||
1192 | /* Should have a valid DPCD by this point */ | |
1193 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
1194 | return; | |
1195 | ||
1196 | if (mode != DRM_MODE_DPMS_ON) { | |
1197 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, | |
1198 | DP_SET_POWER_D3); | |
1199 | if (ret != 1) | |
1200 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
1201 | } else { | |
1202 | /* | |
1203 | * When turning on, we need to retry for 1ms to give the sink | |
1204 | * time to wake up. | |
1205 | */ | |
1206 | for (i = 0; i < 3; i++) { | |
1207 | ret = intel_dp_aux_native_write_1(intel_dp, | |
1208 | DP_SET_POWER, | |
1209 | DP_SET_POWER_D0); | |
1210 | if (ret == 1) | |
1211 | break; | |
1212 | msleep(1); | |
1213 | } | |
1214 | } | |
1215 | } | |
1216 | ||
d240f20f JB |
1217 | static void intel_dp_prepare(struct drm_encoder *encoder) |
1218 | { | |
1219 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
d240f20f | 1220 | |
21264c63 KP |
1221 | ironlake_edp_backlight_off(intel_dp); |
1222 | ironlake_edp_panel_off(intel_dp); | |
1223 | ||
c7ad3810 | 1224 | /* Wake up the sink first */ |
f58ff854 | 1225 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1226 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
21264c63 | 1227 | intel_dp_link_down(intel_dp); |
bd943159 | 1228 | ironlake_edp_panel_vdd_off(intel_dp, false); |
c7ad3810 | 1229 | |
f01eca2e KP |
1230 | /* Make sure the panel is off before trying to |
1231 | * change the mode | |
1232 | */ | |
d240f20f JB |
1233 | } |
1234 | ||
1235 | static void intel_dp_commit(struct drm_encoder *encoder) | |
1236 | { | |
1237 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
d4270e57 JB |
1238 | struct drm_device *dev = encoder->dev; |
1239 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); | |
5d613501 | 1240 | |
97af61f5 | 1241 | ironlake_edp_panel_vdd_on(intel_dp); |
f01eca2e | 1242 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 1243 | intel_dp_start_link_train(intel_dp); |
97af61f5 | 1244 | ironlake_edp_panel_on(intel_dp); |
bd943159 | 1245 | ironlake_edp_panel_vdd_off(intel_dp, true); |
33a34e4e | 1246 | intel_dp_complete_link_train(intel_dp); |
f01eca2e | 1247 | ironlake_edp_backlight_on(intel_dp); |
d2b996ac KP |
1248 | |
1249 | intel_dp->dpms_mode = DRM_MODE_DPMS_ON; | |
d4270e57 JB |
1250 | |
1251 | if (HAS_PCH_CPT(dev)) | |
1252 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
d240f20f JB |
1253 | } |
1254 | ||
a4fc5ed6 KP |
1255 | static void |
1256 | intel_dp_dpms(struct drm_encoder *encoder, int mode) | |
1257 | { | |
ea5b213a | 1258 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
55f78c43 | 1259 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 | 1260 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1261 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
a4fc5ed6 KP |
1262 | |
1263 | if (mode != DRM_MODE_DPMS_ON) { | |
21264c63 KP |
1264 | ironlake_edp_backlight_off(intel_dp); |
1265 | ironlake_edp_panel_off(intel_dp); | |
1266 | ||
245e2708 | 1267 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1268 | intel_dp_sink_dpms(intel_dp, mode); |
736085bc | 1269 | intel_dp_link_down(intel_dp); |
bd943159 | 1270 | ironlake_edp_panel_vdd_off(intel_dp, false); |
21264c63 KP |
1271 | |
1272 | if (is_cpu_edp(intel_dp)) | |
1273 | ironlake_edp_pll_off(encoder); | |
a4fc5ed6 | 1274 | } else { |
21264c63 KP |
1275 | if (is_cpu_edp(intel_dp)) |
1276 | ironlake_edp_pll_on(encoder); | |
1277 | ||
97af61f5 | 1278 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1279 | intel_dp_sink_dpms(intel_dp, mode); |
32f9d658 | 1280 | if (!(dp_reg & DP_PORT_EN)) { |
01cb9ea6 | 1281 | intel_dp_start_link_train(intel_dp); |
97af61f5 | 1282 | ironlake_edp_panel_on(intel_dp); |
bd943159 | 1283 | ironlake_edp_panel_vdd_off(intel_dp, true); |
33a34e4e | 1284 | intel_dp_complete_link_train(intel_dp); |
bee7eb2d | 1285 | } else |
bd943159 KP |
1286 | ironlake_edp_panel_vdd_off(intel_dp, false); |
1287 | ironlake_edp_backlight_on(intel_dp); | |
a4fc5ed6 | 1288 | } |
d2b996ac | 1289 | intel_dp->dpms_mode = mode; |
a4fc5ed6 KP |
1290 | } |
1291 | ||
1292 | /* | |
df0c237d JB |
1293 | * Native read with retry for link status and receiver capability reads for |
1294 | * cases where the sink may still be asleep. | |
a4fc5ed6 KP |
1295 | */ |
1296 | static bool | |
df0c237d JB |
1297 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
1298 | uint8_t *recv, int recv_bytes) | |
a4fc5ed6 | 1299 | { |
61da5fab JB |
1300 | int ret, i; |
1301 | ||
df0c237d JB |
1302 | /* |
1303 | * Sinks are *supposed* to come up within 1ms from an off state, | |
1304 | * but we're also supposed to retry 3 times per the spec. | |
1305 | */ | |
61da5fab | 1306 | for (i = 0; i < 3; i++) { |
df0c237d JB |
1307 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
1308 | recv_bytes); | |
1309 | if (ret == recv_bytes) | |
61da5fab JB |
1310 | return true; |
1311 | msleep(1); | |
1312 | } | |
a4fc5ed6 | 1313 | |
61da5fab | 1314 | return false; |
a4fc5ed6 KP |
1315 | } |
1316 | ||
1317 | /* | |
1318 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
1319 | * link status information | |
1320 | */ | |
1321 | static bool | |
93f62dad | 1322 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 1323 | { |
df0c237d JB |
1324 | return intel_dp_aux_native_read_retry(intel_dp, |
1325 | DP_LANE0_1_STATUS, | |
93f62dad | 1326 | link_status, |
df0c237d | 1327 | DP_LINK_STATUS_SIZE); |
a4fc5ed6 KP |
1328 | } |
1329 | ||
1330 | static uint8_t | |
1331 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1332 | int r) | |
1333 | { | |
1334 | return link_status[r - DP_LANE0_1_STATUS]; | |
1335 | } | |
1336 | ||
a4fc5ed6 | 1337 | static uint8_t |
93f62dad | 1338 | intel_get_adjust_request_voltage(uint8_t adjust_request[2], |
a4fc5ed6 KP |
1339 | int lane) |
1340 | { | |
a4fc5ed6 KP |
1341 | int s = ((lane & 1) ? |
1342 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
1343 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
93f62dad | 1344 | uint8_t l = adjust_request[lane>>1]; |
a4fc5ed6 KP |
1345 | |
1346 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
1347 | } | |
1348 | ||
1349 | static uint8_t | |
93f62dad | 1350 | intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2], |
a4fc5ed6 KP |
1351 | int lane) |
1352 | { | |
a4fc5ed6 KP |
1353 | int s = ((lane & 1) ? |
1354 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
1355 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
93f62dad | 1356 | uint8_t l = adjust_request[lane>>1]; |
a4fc5ed6 KP |
1357 | |
1358 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
1359 | } | |
1360 | ||
1361 | ||
1362 | #if 0 | |
1363 | static char *voltage_names[] = { | |
1364 | "0.4V", "0.6V", "0.8V", "1.2V" | |
1365 | }; | |
1366 | static char *pre_emph_names[] = { | |
1367 | "0dB", "3.5dB", "6dB", "9.5dB" | |
1368 | }; | |
1369 | static char *link_train_names[] = { | |
1370 | "pattern 1", "pattern 2", "idle", "off" | |
1371 | }; | |
1372 | #endif | |
1373 | ||
1374 | /* | |
1375 | * These are source-specific values; current Intel hardware supports | |
1376 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1377 | */ | |
1378 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 | |
417e822d | 1379 | #define I830_DP_VOLTAGE_MAX_CPT DP_TRAIN_VOLTAGE_SWING_1200 |
a4fc5ed6 KP |
1380 | |
1381 | static uint8_t | |
1382 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) | |
1383 | { | |
1384 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1385 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1386 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1387 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1388 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1389 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1390 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1391 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1392 | default: | |
1393 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1394 | } | |
1395 | } | |
1396 | ||
1397 | static void | |
93f62dad | 1398 | intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 1399 | { |
93f62dad | 1400 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 KP |
1401 | uint8_t v = 0; |
1402 | uint8_t p = 0; | |
1403 | int lane; | |
93f62dad KP |
1404 | uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS); |
1405 | int voltage_max; | |
a4fc5ed6 | 1406 | |
33a34e4e | 1407 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
93f62dad KP |
1408 | uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane); |
1409 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane); | |
a4fc5ed6 KP |
1410 | |
1411 | if (this_v > v) | |
1412 | v = this_v; | |
1413 | if (this_p > p) | |
1414 | p = this_p; | |
1415 | } | |
1416 | ||
417e822d KP |
1417 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
1418 | voltage_max = I830_DP_VOLTAGE_MAX_CPT; | |
1419 | else | |
1420 | voltage_max = I830_DP_VOLTAGE_MAX; | |
1421 | if (v >= voltage_max) | |
1422 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; | |
a4fc5ed6 KP |
1423 | |
1424 | if (p >= intel_dp_pre_emphasis_max(v)) | |
1425 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
1426 | ||
1427 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 1428 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
1429 | } |
1430 | ||
1431 | static uint32_t | |
93f62dad | 1432 | intel_dp_signal_levels(uint8_t train_set) |
a4fc5ed6 | 1433 | { |
3cf2efb1 | 1434 | uint32_t signal_levels = 0; |
a4fc5ed6 | 1435 | |
3cf2efb1 | 1436 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
1437 | case DP_TRAIN_VOLTAGE_SWING_400: |
1438 | default: | |
1439 | signal_levels |= DP_VOLTAGE_0_4; | |
1440 | break; | |
1441 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1442 | signal_levels |= DP_VOLTAGE_0_6; | |
1443 | break; | |
1444 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1445 | signal_levels |= DP_VOLTAGE_0_8; | |
1446 | break; | |
1447 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1448 | signal_levels |= DP_VOLTAGE_1_2; | |
1449 | break; | |
1450 | } | |
3cf2efb1 | 1451 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
1452 | case DP_TRAIN_PRE_EMPHASIS_0: |
1453 | default: | |
1454 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1455 | break; | |
1456 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1457 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1458 | break; | |
1459 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1460 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1461 | break; | |
1462 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1463 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1464 | break; | |
1465 | } | |
1466 | return signal_levels; | |
1467 | } | |
1468 | ||
e3421a18 ZW |
1469 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1470 | static uint32_t | |
1471 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1472 | { | |
3c5a62b5 YL |
1473 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1474 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1475 | switch (signal_levels) { | |
e3421a18 | 1476 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1477 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
1478 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
1479 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1480 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 1481 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
1482 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
1483 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 1484 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
1485 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
1486 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 1487 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1488 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
1489 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 1490 | default: |
3c5a62b5 YL |
1491 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
1492 | "0x%x\n", signal_levels); | |
1493 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
1494 | } |
1495 | } | |
1496 | ||
a4fc5ed6 KP |
1497 | static uint8_t |
1498 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1499 | int lane) | |
1500 | { | |
a4fc5ed6 | 1501 | int s = (lane & 1) * 4; |
93f62dad | 1502 | uint8_t l = link_status[lane>>1]; |
a4fc5ed6 KP |
1503 | |
1504 | return (l >> s) & 0xf; | |
1505 | } | |
1506 | ||
1507 | /* Check for clock recovery is done on all channels */ | |
1508 | static bool | |
1509 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1510 | { | |
1511 | int lane; | |
1512 | uint8_t lane_status; | |
1513 | ||
1514 | for (lane = 0; lane < lane_count; lane++) { | |
1515 | lane_status = intel_get_lane_status(link_status, lane); | |
1516 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
1517 | return false; | |
1518 | } | |
1519 | return true; | |
1520 | } | |
1521 | ||
1522 | /* Check to see if channel eq is done on all channels */ | |
1523 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ | |
1524 | DP_LANE_CHANNEL_EQ_DONE|\ | |
1525 | DP_LANE_SYMBOL_LOCKED) | |
1526 | static bool | |
93f62dad | 1527 | intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 KP |
1528 | { |
1529 | uint8_t lane_align; | |
1530 | uint8_t lane_status; | |
1531 | int lane; | |
1532 | ||
93f62dad | 1533 | lane_align = intel_dp_link_status(link_status, |
a4fc5ed6 KP |
1534 | DP_LANE_ALIGN_STATUS_UPDATED); |
1535 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
1536 | return false; | |
33a34e4e | 1537 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
93f62dad | 1538 | lane_status = intel_get_lane_status(link_status, lane); |
a4fc5ed6 KP |
1539 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
1540 | return false; | |
1541 | } | |
1542 | return true; | |
1543 | } | |
1544 | ||
1545 | static bool | |
ea5b213a | 1546 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 | 1547 | uint32_t dp_reg_value, |
58e10eb9 | 1548 | uint8_t dp_train_pat) |
a4fc5ed6 | 1549 | { |
4ef69c7a | 1550 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1551 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1552 | int ret; |
1553 | ||
ea5b213a CW |
1554 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1555 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1556 | |
ea5b213a | 1557 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1558 | DP_TRAINING_PATTERN_SET, |
1559 | dp_train_pat); | |
1560 | ||
ea5b213a | 1561 | ret = intel_dp_aux_native_write(intel_dp, |
58e10eb9 | 1562 | DP_TRAINING_LANE0_SET, |
b34f1f09 KP |
1563 | intel_dp->train_set, |
1564 | intel_dp->lane_count); | |
1565 | if (ret != intel_dp->lane_count) | |
a4fc5ed6 KP |
1566 | return false; |
1567 | ||
1568 | return true; | |
1569 | } | |
1570 | ||
33a34e4e | 1571 | /* Enable corresponding port and start training pattern 1 */ |
a4fc5ed6 | 1572 | static void |
33a34e4e | 1573 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1574 | { |
4ef69c7a | 1575 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1576 | struct drm_i915_private *dev_priv = dev->dev_private; |
58e10eb9 | 1577 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); |
a4fc5ed6 KP |
1578 | int i; |
1579 | uint8_t voltage; | |
1580 | bool clock_recovery = false; | |
cdb0e95b | 1581 | int voltage_tries, loop_tries; |
e3421a18 | 1582 | u32 reg; |
ea5b213a | 1583 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1584 | |
e8519464 AJ |
1585 | /* |
1586 | * On CPT we have to enable the port in training pattern 1, which | |
1587 | * will happen below in intel_dp_set_link_train. Otherwise, enable | |
1588 | * the port and wait for it to become active. | |
1589 | */ | |
1590 | if (!HAS_PCH_CPT(dev)) { | |
1591 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
1592 | POSTING_READ(intel_dp->output_reg); | |
1593 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1594 | } | |
a4fc5ed6 | 1595 | |
3cf2efb1 CW |
1596 | /* Write the link configuration data */ |
1597 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, | |
1598 | intel_dp->link_configuration, | |
1599 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
1600 | |
1601 | DP |= DP_PORT_EN; | |
82d16555 | 1602 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
e3421a18 ZW |
1603 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1604 | else | |
1605 | DP &= ~DP_LINK_TRAIN_MASK; | |
33a34e4e | 1606 | memset(intel_dp->train_set, 0, 4); |
a4fc5ed6 | 1607 | voltage = 0xff; |
cdb0e95b KP |
1608 | voltage_tries = 0; |
1609 | loop_tries = 0; | |
a4fc5ed6 KP |
1610 | clock_recovery = false; |
1611 | for (;;) { | |
33a34e4e | 1612 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
93f62dad | 1613 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
e3421a18 | 1614 | uint32_t signal_levels; |
417e822d KP |
1615 | |
1616 | if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { | |
33a34e4e | 1617 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1618 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1619 | } else { | |
93f62dad KP |
1620 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); |
1621 | DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels); | |
e3421a18 ZW |
1622 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1623 | } | |
a4fc5ed6 | 1624 | |
82d16555 | 1625 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
e3421a18 ZW |
1626 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
1627 | else | |
1628 | reg = DP | DP_LINK_TRAIN_PAT_1; | |
1629 | ||
ea5b213a | 1630 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1631 | DP_TRAINING_PATTERN_1 | |
1632 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 | 1633 | break; |
a4fc5ed6 KP |
1634 | /* Set training pattern 1 */ |
1635 | ||
3cf2efb1 | 1636 | udelay(100); |
93f62dad KP |
1637 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
1638 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 1639 | break; |
93f62dad | 1640 | } |
a4fc5ed6 | 1641 | |
93f62dad KP |
1642 | if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
1643 | DRM_DEBUG_KMS("clock recovery OK\n"); | |
3cf2efb1 CW |
1644 | clock_recovery = true; |
1645 | break; | |
1646 | } | |
1647 | ||
1648 | /* Check to see if we've tried the max voltage */ | |
1649 | for (i = 0; i < intel_dp->lane_count; i++) | |
1650 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 1651 | break; |
cdb0e95b KP |
1652 | if (i == intel_dp->lane_count) { |
1653 | ++loop_tries; | |
1654 | if (loop_tries == 5) { | |
1655 | DRM_DEBUG_KMS("too many full retries, give up\n"); | |
1656 | break; | |
1657 | } | |
1658 | memset(intel_dp->train_set, 0, 4); | |
1659 | voltage_tries = 0; | |
1660 | continue; | |
1661 | } | |
a4fc5ed6 | 1662 | |
3cf2efb1 CW |
1663 | /* Check to see if we've tried the same voltage 5 times */ |
1664 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { | |
cdb0e95b KP |
1665 | ++voltage_tries; |
1666 | if (voltage_tries == 5) { | |
1667 | DRM_DEBUG_KMS("too many voltage retries, give up\n"); | |
a4fc5ed6 | 1668 | break; |
cdb0e95b | 1669 | } |
3cf2efb1 | 1670 | } else |
cdb0e95b | 1671 | voltage_tries = 0; |
3cf2efb1 | 1672 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
a4fc5ed6 | 1673 | |
3cf2efb1 | 1674 | /* Compute new intel_dp->train_set as requested by target */ |
93f62dad | 1675 | intel_get_adjust_train(intel_dp, link_status); |
a4fc5ed6 KP |
1676 | } |
1677 | ||
33a34e4e JB |
1678 | intel_dp->DP = DP; |
1679 | } | |
1680 | ||
1681 | static void | |
1682 | intel_dp_complete_link_train(struct intel_dp *intel_dp) | |
1683 | { | |
4ef69c7a | 1684 | struct drm_device *dev = intel_dp->base.base.dev; |
33a34e4e JB |
1685 | struct drm_i915_private *dev_priv = dev->dev_private; |
1686 | bool channel_eq = false; | |
37f80975 | 1687 | int tries, cr_tries; |
33a34e4e JB |
1688 | u32 reg; |
1689 | uint32_t DP = intel_dp->DP; | |
1690 | ||
a4fc5ed6 KP |
1691 | /* channel equalization */ |
1692 | tries = 0; | |
37f80975 | 1693 | cr_tries = 0; |
a4fc5ed6 KP |
1694 | channel_eq = false; |
1695 | for (;;) { | |
33a34e4e | 1696 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 | 1697 | uint32_t signal_levels; |
93f62dad | 1698 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
e3421a18 | 1699 | |
37f80975 JB |
1700 | if (cr_tries > 5) { |
1701 | DRM_ERROR("failed to train DP, aborting\n"); | |
1702 | intel_dp_link_down(intel_dp); | |
1703 | break; | |
1704 | } | |
1705 | ||
417e822d | 1706 | if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
33a34e4e | 1707 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1708 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1709 | } else { | |
93f62dad | 1710 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1711 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1712 | } | |
1713 | ||
82d16555 | 1714 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
e3421a18 ZW |
1715 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
1716 | else | |
1717 | reg = DP | DP_LINK_TRAIN_PAT_2; | |
a4fc5ed6 KP |
1718 | |
1719 | /* channel eq pattern */ | |
ea5b213a | 1720 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1721 | DP_TRAINING_PATTERN_2 | |
1722 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 KP |
1723 | break; |
1724 | ||
3cf2efb1 | 1725 | udelay(400); |
93f62dad | 1726 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
a4fc5ed6 | 1727 | break; |
a4fc5ed6 | 1728 | |
37f80975 | 1729 | /* Make sure clock is still ok */ |
93f62dad | 1730 | if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
37f80975 JB |
1731 | intel_dp_start_link_train(intel_dp); |
1732 | cr_tries++; | |
1733 | continue; | |
1734 | } | |
1735 | ||
93f62dad | 1736 | if (intel_channel_eq_ok(intel_dp, link_status)) { |
3cf2efb1 CW |
1737 | channel_eq = true; |
1738 | break; | |
1739 | } | |
a4fc5ed6 | 1740 | |
37f80975 JB |
1741 | /* Try 5 times, then try clock recovery if that fails */ |
1742 | if (tries > 5) { | |
1743 | intel_dp_link_down(intel_dp); | |
1744 | intel_dp_start_link_train(intel_dp); | |
1745 | tries = 0; | |
1746 | cr_tries++; | |
1747 | continue; | |
1748 | } | |
a4fc5ed6 | 1749 | |
3cf2efb1 | 1750 | /* Compute new intel_dp->train_set as requested by target */ |
93f62dad | 1751 | intel_get_adjust_train(intel_dp, link_status); |
3cf2efb1 | 1752 | ++tries; |
869184a6 | 1753 | } |
3cf2efb1 | 1754 | |
82d16555 | 1755 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
e3421a18 ZW |
1756 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
1757 | else | |
1758 | reg = DP | DP_LINK_TRAIN_OFF; | |
1759 | ||
ea5b213a CW |
1760 | I915_WRITE(intel_dp->output_reg, reg); |
1761 | POSTING_READ(intel_dp->output_reg); | |
1762 | intel_dp_aux_native_write_1(intel_dp, | |
a4fc5ed6 KP |
1763 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
1764 | } | |
1765 | ||
1766 | static void | |
ea5b213a | 1767 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 1768 | { |
4ef69c7a | 1769 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1770 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1771 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1772 | |
1b39d6f3 CW |
1773 | if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) |
1774 | return; | |
1775 | ||
28c97730 | 1776 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1777 | |
cfcb0fc9 | 1778 | if (is_edp(intel_dp)) { |
32f9d658 | 1779 | DP &= ~DP_PLL_ENABLE; |
ea5b213a CW |
1780 | I915_WRITE(intel_dp->output_reg, DP); |
1781 | POSTING_READ(intel_dp->output_reg); | |
32f9d658 ZW |
1782 | udelay(100); |
1783 | } | |
1784 | ||
82d16555 | 1785 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) { |
e3421a18 | 1786 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 1787 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
1788 | } else { |
1789 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 1790 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 1791 | } |
fe255d00 | 1792 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 1793 | |
fe255d00 | 1794 | msleep(17); |
5eb08b69 | 1795 | |
417e822d KP |
1796 | if (is_edp(intel_dp)) { |
1797 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) | |
1798 | DP |= DP_LINK_TRAIN_OFF_CPT; | |
1799 | else | |
1800 | DP |= DP_LINK_TRAIN_OFF; | |
1801 | } | |
5bddd17f | 1802 | |
1b39d6f3 CW |
1803 | if (!HAS_PCH_CPT(dev) && |
1804 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { | |
31acbcc4 CW |
1805 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
1806 | ||
5bddd17f EA |
1807 | /* Hardware workaround: leaving our transcoder select |
1808 | * set to transcoder B while it's off will prevent the | |
1809 | * corresponding HDMI output on transcoder A. | |
1810 | * | |
1811 | * Combine this with another hardware workaround: | |
1812 | * transcoder select bit can only be cleared while the | |
1813 | * port is enabled. | |
1814 | */ | |
1815 | DP &= ~DP_PIPEB_SELECT; | |
1816 | I915_WRITE(intel_dp->output_reg, DP); | |
1817 | ||
1818 | /* Changes to enable or select take place the vblank | |
1819 | * after being written. | |
1820 | */ | |
31acbcc4 CW |
1821 | if (crtc == NULL) { |
1822 | /* We can arrive here never having been attached | |
1823 | * to a CRTC, for instance, due to inheriting | |
1824 | * random state from the BIOS. | |
1825 | * | |
1826 | * If the pipe is not running, play safe and | |
1827 | * wait for the clocks to stabilise before | |
1828 | * continuing. | |
1829 | */ | |
1830 | POSTING_READ(intel_dp->output_reg); | |
1831 | msleep(50); | |
1832 | } else | |
1833 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
5bddd17f EA |
1834 | } |
1835 | ||
ea5b213a CW |
1836 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
1837 | POSTING_READ(intel_dp->output_reg); | |
f01eca2e | 1838 | msleep(intel_dp->panel_power_down_delay); |
a4fc5ed6 KP |
1839 | } |
1840 | ||
26d61aad KP |
1841 | static bool |
1842 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 1843 | { |
92fd8fd1 | 1844 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
0206e353 | 1845 | sizeof(intel_dp->dpcd)) && |
92fd8fd1 | 1846 | (intel_dp->dpcd[DP_DPCD_REV] != 0)) { |
26d61aad | 1847 | return true; |
92fd8fd1 KP |
1848 | } |
1849 | ||
26d61aad | 1850 | return false; |
92fd8fd1 KP |
1851 | } |
1852 | ||
a60f0e38 JB |
1853 | static bool |
1854 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
1855 | { | |
1856 | int ret; | |
1857 | ||
1858 | ret = intel_dp_aux_native_read_retry(intel_dp, | |
1859 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
1860 | sink_irq_vector, 1); | |
1861 | if (!ret) | |
1862 | return false; | |
1863 | ||
1864 | return true; | |
1865 | } | |
1866 | ||
1867 | static void | |
1868 | intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
1869 | { | |
1870 | /* NAK by default */ | |
1871 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK); | |
1872 | } | |
1873 | ||
a4fc5ed6 KP |
1874 | /* |
1875 | * According to DP spec | |
1876 | * 5.1.2: | |
1877 | * 1. Read DPCD | |
1878 | * 2. Configure link according to Receiver Capabilities | |
1879 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
1880 | * 4. Check link status on receipt of hot-plug interrupt | |
1881 | */ | |
1882 | ||
1883 | static void | |
ea5b213a | 1884 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1885 | { |
a60f0e38 | 1886 | u8 sink_irq_vector; |
93f62dad | 1887 | u8 link_status[DP_LINK_STATUS_SIZE]; |
a60f0e38 | 1888 | |
d2b996ac KP |
1889 | if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON) |
1890 | return; | |
59cd09e1 | 1891 | |
4ef69c7a | 1892 | if (!intel_dp->base.base.crtc) |
a4fc5ed6 KP |
1893 | return; |
1894 | ||
92fd8fd1 | 1895 | /* Try to read receiver status if the link appears to be up */ |
93f62dad | 1896 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
ea5b213a | 1897 | intel_dp_link_down(intel_dp); |
a4fc5ed6 KP |
1898 | return; |
1899 | } | |
1900 | ||
92fd8fd1 | 1901 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 1902 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
1903 | intel_dp_link_down(intel_dp); |
1904 | return; | |
1905 | } | |
1906 | ||
a60f0e38 JB |
1907 | /* Try to read the source of the interrupt */ |
1908 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
1909 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
1910 | /* Clear interrupt source */ | |
1911 | intel_dp_aux_native_write_1(intel_dp, | |
1912 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
1913 | sink_irq_vector); | |
1914 | ||
1915 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
1916 | intel_dp_handle_test_request(intel_dp); | |
1917 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
1918 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
1919 | } | |
1920 | ||
93f62dad | 1921 | if (!intel_channel_eq_ok(intel_dp, link_status)) { |
92fd8fd1 KP |
1922 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
1923 | drm_get_encoder_name(&intel_dp->base.base)); | |
33a34e4e JB |
1924 | intel_dp_start_link_train(intel_dp); |
1925 | intel_dp_complete_link_train(intel_dp); | |
1926 | } | |
a4fc5ed6 | 1927 | } |
a4fc5ed6 | 1928 | |
71ba9000 | 1929 | static enum drm_connector_status |
26d61aad | 1930 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 1931 | { |
26d61aad KP |
1932 | if (intel_dp_get_dpcd(intel_dp)) |
1933 | return connector_status_connected; | |
1934 | return connector_status_disconnected; | |
71ba9000 AJ |
1935 | } |
1936 | ||
5eb08b69 | 1937 | static enum drm_connector_status |
a9756bb5 | 1938 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 1939 | { |
5eb08b69 ZW |
1940 | enum drm_connector_status status; |
1941 | ||
fe16d949 CW |
1942 | /* Can't disconnect eDP, but you can close the lid... */ |
1943 | if (is_edp(intel_dp)) { | |
1944 | status = intel_panel_detect(intel_dp->base.base.dev); | |
1945 | if (status == connector_status_unknown) | |
1946 | status = connector_status_connected; | |
1947 | return status; | |
1948 | } | |
01cb9ea6 | 1949 | |
26d61aad | 1950 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
1951 | } |
1952 | ||
a4fc5ed6 | 1953 | static enum drm_connector_status |
a9756bb5 | 1954 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 1955 | { |
4ef69c7a | 1956 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1957 | struct drm_i915_private *dev_priv = dev->dev_private; |
a9756bb5 | 1958 | uint32_t temp, bit; |
5eb08b69 | 1959 | |
ea5b213a | 1960 | switch (intel_dp->output_reg) { |
a4fc5ed6 KP |
1961 | case DP_B: |
1962 | bit = DPB_HOTPLUG_INT_STATUS; | |
1963 | break; | |
1964 | case DP_C: | |
1965 | bit = DPC_HOTPLUG_INT_STATUS; | |
1966 | break; | |
1967 | case DP_D: | |
1968 | bit = DPD_HOTPLUG_INT_STATUS; | |
1969 | break; | |
1970 | default: | |
1971 | return connector_status_unknown; | |
1972 | } | |
1973 | ||
1974 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
1975 | ||
1976 | if ((temp & bit) == 0) | |
1977 | return connector_status_disconnected; | |
1978 | ||
26d61aad | 1979 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
1980 | } |
1981 | ||
8c241fef KP |
1982 | static struct edid * |
1983 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
1984 | { | |
1985 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1986 | struct edid *edid; | |
1987 | ||
1988 | ironlake_edp_panel_vdd_on(intel_dp); | |
1989 | edid = drm_get_edid(connector, adapter); | |
bd943159 | 1990 | ironlake_edp_panel_vdd_off(intel_dp, false); |
8c241fef KP |
1991 | return edid; |
1992 | } | |
1993 | ||
1994 | static int | |
1995 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) | |
1996 | { | |
1997 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1998 | int ret; | |
1999 | ||
2000 | ironlake_edp_panel_vdd_on(intel_dp); | |
2001 | ret = intel_ddc_get_modes(connector, adapter); | |
bd943159 | 2002 | ironlake_edp_panel_vdd_off(intel_dp, false); |
8c241fef KP |
2003 | return ret; |
2004 | } | |
2005 | ||
2006 | ||
a9756bb5 ZW |
2007 | /** |
2008 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. | |
2009 | * | |
2010 | * \return true if DP port is connected. | |
2011 | * \return false if DP port is disconnected. | |
2012 | */ | |
2013 | static enum drm_connector_status | |
2014 | intel_dp_detect(struct drm_connector *connector, bool force) | |
2015 | { | |
2016 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
2017 | struct drm_device *dev = intel_dp->base.base.dev; | |
2018 | enum drm_connector_status status; | |
2019 | struct edid *edid = NULL; | |
2020 | ||
2021 | intel_dp->has_audio = false; | |
2022 | ||
2023 | if (HAS_PCH_SPLIT(dev)) | |
2024 | status = ironlake_dp_detect(intel_dp); | |
2025 | else | |
2026 | status = g4x_dp_detect(intel_dp); | |
1b9be9d0 | 2027 | |
ac66ae83 AJ |
2028 | DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", |
2029 | intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], | |
2030 | intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], | |
2031 | intel_dp->dpcd[6], intel_dp->dpcd[7]); | |
1b9be9d0 | 2032 | |
a9756bb5 ZW |
2033 | if (status != connector_status_connected) |
2034 | return status; | |
2035 | ||
f684960e CW |
2036 | if (intel_dp->force_audio) { |
2037 | intel_dp->has_audio = intel_dp->force_audio > 0; | |
2038 | } else { | |
8c241fef | 2039 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
f684960e CW |
2040 | if (edid) { |
2041 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
2042 | connector->display_info.raw_edid = NULL; | |
2043 | kfree(edid); | |
2044 | } | |
a9756bb5 ZW |
2045 | } |
2046 | ||
2047 | return connector_status_connected; | |
a4fc5ed6 KP |
2048 | } |
2049 | ||
2050 | static int intel_dp_get_modes(struct drm_connector *connector) | |
2051 | { | |
df0e9248 | 2052 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4ef69c7a | 2053 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
2054 | struct drm_i915_private *dev_priv = dev->dev_private; |
2055 | int ret; | |
a4fc5ed6 KP |
2056 | |
2057 | /* We should parse the EDID data and find out if it has an audio sink | |
2058 | */ | |
2059 | ||
8c241fef | 2060 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
b9efc480 | 2061 | if (ret) { |
d15456de | 2062 | if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) { |
b9efc480 ZY |
2063 | struct drm_display_mode *newmode; |
2064 | list_for_each_entry(newmode, &connector->probed_modes, | |
2065 | head) { | |
d15456de KP |
2066 | if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) { |
2067 | intel_dp->panel_fixed_mode = | |
b9efc480 ZY |
2068 | drm_mode_duplicate(dev, newmode); |
2069 | break; | |
2070 | } | |
2071 | } | |
2072 | } | |
32f9d658 | 2073 | return ret; |
b9efc480 | 2074 | } |
32f9d658 ZW |
2075 | |
2076 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ | |
4d926461 | 2077 | if (is_edp(intel_dp)) { |
47f0eb22 | 2078 | /* initialize panel mode from VBT if available for eDP */ |
d15456de KP |
2079 | if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) { |
2080 | intel_dp->panel_fixed_mode = | |
47f0eb22 | 2081 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
d15456de KP |
2082 | if (intel_dp->panel_fixed_mode) { |
2083 | intel_dp->panel_fixed_mode->type |= | |
47f0eb22 KP |
2084 | DRM_MODE_TYPE_PREFERRED; |
2085 | } | |
2086 | } | |
d15456de | 2087 | if (intel_dp->panel_fixed_mode) { |
32f9d658 | 2088 | struct drm_display_mode *mode; |
d15456de | 2089 | mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode); |
32f9d658 ZW |
2090 | drm_mode_probed_add(connector, mode); |
2091 | return 1; | |
2092 | } | |
2093 | } | |
2094 | return 0; | |
a4fc5ed6 KP |
2095 | } |
2096 | ||
1aad7ac0 CW |
2097 | static bool |
2098 | intel_dp_detect_audio(struct drm_connector *connector) | |
2099 | { | |
2100 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
2101 | struct edid *edid; | |
2102 | bool has_audio = false; | |
2103 | ||
8c241fef | 2104 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
1aad7ac0 CW |
2105 | if (edid) { |
2106 | has_audio = drm_detect_monitor_audio(edid); | |
2107 | ||
2108 | connector->display_info.raw_edid = NULL; | |
2109 | kfree(edid); | |
2110 | } | |
2111 | ||
2112 | return has_audio; | |
2113 | } | |
2114 | ||
f684960e CW |
2115 | static int |
2116 | intel_dp_set_property(struct drm_connector *connector, | |
2117 | struct drm_property *property, | |
2118 | uint64_t val) | |
2119 | { | |
e953fd7b | 2120 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
f684960e CW |
2121 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
2122 | int ret; | |
2123 | ||
2124 | ret = drm_connector_property_set_value(connector, property, val); | |
2125 | if (ret) | |
2126 | return ret; | |
2127 | ||
3f43c48d | 2128 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
2129 | int i = val; |
2130 | bool has_audio; | |
2131 | ||
2132 | if (i == intel_dp->force_audio) | |
f684960e CW |
2133 | return 0; |
2134 | ||
1aad7ac0 | 2135 | intel_dp->force_audio = i; |
f684960e | 2136 | |
1aad7ac0 CW |
2137 | if (i == 0) |
2138 | has_audio = intel_dp_detect_audio(connector); | |
2139 | else | |
2140 | has_audio = i > 0; | |
2141 | ||
2142 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
2143 | return 0; |
2144 | ||
1aad7ac0 | 2145 | intel_dp->has_audio = has_audio; |
f684960e CW |
2146 | goto done; |
2147 | } | |
2148 | ||
e953fd7b CW |
2149 | if (property == dev_priv->broadcast_rgb_property) { |
2150 | if (val == !!intel_dp->color_range) | |
2151 | return 0; | |
2152 | ||
2153 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; | |
2154 | goto done; | |
2155 | } | |
2156 | ||
f684960e CW |
2157 | return -EINVAL; |
2158 | ||
2159 | done: | |
2160 | if (intel_dp->base.base.crtc) { | |
2161 | struct drm_crtc *crtc = intel_dp->base.base.crtc; | |
2162 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
2163 | crtc->x, crtc->y, | |
2164 | crtc->fb); | |
2165 | } | |
2166 | ||
2167 | return 0; | |
2168 | } | |
2169 | ||
a4fc5ed6 | 2170 | static void |
0206e353 | 2171 | intel_dp_destroy(struct drm_connector *connector) |
a4fc5ed6 | 2172 | { |
aaa6fd2a MG |
2173 | struct drm_device *dev = connector->dev; |
2174 | ||
2175 | if (intel_dpd_is_edp(dev)) | |
2176 | intel_panel_destroy_backlight(dev); | |
2177 | ||
a4fc5ed6 KP |
2178 | drm_sysfs_connector_remove(connector); |
2179 | drm_connector_cleanup(connector); | |
55f78c43 | 2180 | kfree(connector); |
a4fc5ed6 KP |
2181 | } |
2182 | ||
24d05927 DV |
2183 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
2184 | { | |
2185 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
2186 | ||
2187 | i2c_del_adapter(&intel_dp->adapter); | |
2188 | drm_encoder_cleanup(encoder); | |
bd943159 KP |
2189 | if (is_edp(intel_dp)) { |
2190 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
2191 | ironlake_panel_vdd_off_sync(intel_dp); | |
2192 | } | |
24d05927 DV |
2193 | kfree(intel_dp); |
2194 | } | |
2195 | ||
a4fc5ed6 KP |
2196 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
2197 | .dpms = intel_dp_dpms, | |
2198 | .mode_fixup = intel_dp_mode_fixup, | |
d240f20f | 2199 | .prepare = intel_dp_prepare, |
a4fc5ed6 | 2200 | .mode_set = intel_dp_mode_set, |
d240f20f | 2201 | .commit = intel_dp_commit, |
a4fc5ed6 KP |
2202 | }; |
2203 | ||
2204 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
2205 | .dpms = drm_helper_connector_dpms, | |
a4fc5ed6 KP |
2206 | .detect = intel_dp_detect, |
2207 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 2208 | .set_property = intel_dp_set_property, |
a4fc5ed6 KP |
2209 | .destroy = intel_dp_destroy, |
2210 | }; | |
2211 | ||
2212 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
2213 | .get_modes = intel_dp_get_modes, | |
2214 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 2215 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
2216 | }; |
2217 | ||
a4fc5ed6 | 2218 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 2219 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
2220 | }; |
2221 | ||
995b6762 | 2222 | static void |
21d40d37 | 2223 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 2224 | { |
ea5b213a | 2225 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
c8110e52 | 2226 | |
885a5014 | 2227 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 2228 | } |
6207937d | 2229 | |
e3421a18 ZW |
2230 | /* Return which DP Port should be selected for Transcoder DP control */ |
2231 | int | |
0206e353 | 2232 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
e3421a18 ZW |
2233 | { |
2234 | struct drm_device *dev = crtc->dev; | |
2235 | struct drm_mode_config *mode_config = &dev->mode_config; | |
2236 | struct drm_encoder *encoder; | |
e3421a18 ZW |
2237 | |
2238 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a CW |
2239 | struct intel_dp *intel_dp; |
2240 | ||
d8201ab6 | 2241 | if (encoder->crtc != crtc) |
e3421a18 ZW |
2242 | continue; |
2243 | ||
ea5b213a | 2244 | intel_dp = enc_to_intel_dp(encoder); |
417e822d KP |
2245 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || |
2246 | intel_dp->base.type == INTEL_OUTPUT_EDP) | |
ea5b213a | 2247 | return intel_dp->output_reg; |
e3421a18 | 2248 | } |
ea5b213a | 2249 | |
e3421a18 ZW |
2250 | return -1; |
2251 | } | |
2252 | ||
36e83a18 | 2253 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 2254 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
2255 | { |
2256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2257 | struct child_device_config *p_child; | |
2258 | int i; | |
2259 | ||
2260 | if (!dev_priv->child_dev_num) | |
2261 | return false; | |
2262 | ||
2263 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
2264 | p_child = dev_priv->child_dev + i; | |
2265 | ||
2266 | if (p_child->dvo_port == PORT_IDPD && | |
2267 | p_child->device_type == DEVICE_TYPE_eDP) | |
2268 | return true; | |
2269 | } | |
2270 | return false; | |
2271 | } | |
2272 | ||
f684960e CW |
2273 | static void |
2274 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
2275 | { | |
3f43c48d | 2276 | intel_attach_force_audio_property(connector); |
e953fd7b | 2277 | intel_attach_broadcast_rgb_property(connector); |
f684960e CW |
2278 | } |
2279 | ||
a4fc5ed6 KP |
2280 | void |
2281 | intel_dp_init(struct drm_device *dev, int output_reg) | |
2282 | { | |
2283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2284 | struct drm_connector *connector; | |
ea5b213a | 2285 | struct intel_dp *intel_dp; |
21d40d37 | 2286 | struct intel_encoder *intel_encoder; |
55f78c43 | 2287 | struct intel_connector *intel_connector; |
5eb08b69 | 2288 | const char *name = NULL; |
b329530c | 2289 | int type; |
a4fc5ed6 | 2290 | |
ea5b213a CW |
2291 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
2292 | if (!intel_dp) | |
a4fc5ed6 KP |
2293 | return; |
2294 | ||
3d3dc149 | 2295 | intel_dp->output_reg = output_reg; |
d2b996ac | 2296 | intel_dp->dpms_mode = -1; |
3d3dc149 | 2297 | |
55f78c43 ZW |
2298 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
2299 | if (!intel_connector) { | |
ea5b213a | 2300 | kfree(intel_dp); |
55f78c43 ZW |
2301 | return; |
2302 | } | |
ea5b213a | 2303 | intel_encoder = &intel_dp->base; |
55f78c43 | 2304 | |
ea5b213a | 2305 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
b329530c | 2306 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 2307 | intel_dp->is_pch_edp = true; |
b329530c | 2308 | |
cfcb0fc9 | 2309 | if (output_reg == DP_A || is_pch_edp(intel_dp)) { |
b329530c AJ |
2310 | type = DRM_MODE_CONNECTOR_eDP; |
2311 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
2312 | } else { | |
2313 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
2314 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
2315 | } | |
2316 | ||
55f78c43 | 2317 | connector = &intel_connector->base; |
b329530c | 2318 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
2319 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
2320 | ||
eb1f8e4f DA |
2321 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
2322 | ||
652af9d7 | 2323 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
21d40d37 | 2324 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
652af9d7 | 2325 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
21d40d37 | 2326 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
652af9d7 | 2327 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
21d40d37 | 2328 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
f8aed700 | 2329 | |
bd943159 | 2330 | if (is_edp(intel_dp)) { |
21d40d37 | 2331 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
bd943159 KP |
2332 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
2333 | ironlake_panel_vdd_work); | |
2334 | } | |
6251ec0a | 2335 | |
27f8227b | 2336 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
a4fc5ed6 KP |
2337 | connector->interlace_allowed = true; |
2338 | connector->doublescan_allowed = 0; | |
2339 | ||
4ef69c7a | 2340 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
a4fc5ed6 | 2341 | DRM_MODE_ENCODER_TMDS); |
4ef69c7a | 2342 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
a4fc5ed6 | 2343 | |
df0e9248 | 2344 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
2345 | drm_sysfs_connector_add(connector); |
2346 | ||
2347 | /* Set up the DDC bus. */ | |
5eb08b69 | 2348 | switch (output_reg) { |
32f9d658 ZW |
2349 | case DP_A: |
2350 | name = "DPDDC-A"; | |
2351 | break; | |
5eb08b69 ZW |
2352 | case DP_B: |
2353 | case PCH_DP_B: | |
b01f2c3a JB |
2354 | dev_priv->hotplug_supported_mask |= |
2355 | HDMIB_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2356 | name = "DPDDC-B"; |
2357 | break; | |
2358 | case DP_C: | |
2359 | case PCH_DP_C: | |
b01f2c3a JB |
2360 | dev_priv->hotplug_supported_mask |= |
2361 | HDMIC_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2362 | name = "DPDDC-C"; |
2363 | break; | |
2364 | case DP_D: | |
2365 | case PCH_DP_D: | |
b01f2c3a JB |
2366 | dev_priv->hotplug_supported_mask |= |
2367 | HDMID_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2368 | name = "DPDDC-D"; |
2369 | break; | |
2370 | } | |
2371 | ||
89667383 JB |
2372 | /* Cache some DPCD data in the eDP case */ |
2373 | if (is_edp(intel_dp)) { | |
59f3e272 | 2374 | bool ret; |
f01eca2e KP |
2375 | struct edp_power_seq cur, vbt; |
2376 | u32 pp_on, pp_off, pp_div; | |
5d613501 JB |
2377 | |
2378 | pp_on = I915_READ(PCH_PP_ON_DELAYS); | |
f01eca2e | 2379 | pp_off = I915_READ(PCH_PP_OFF_DELAYS); |
5d613501 | 2380 | pp_div = I915_READ(PCH_PP_DIVISOR); |
89667383 | 2381 | |
f01eca2e KP |
2382 | /* Pull timing values out of registers */ |
2383 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
2384 | PANEL_POWER_UP_DELAY_SHIFT; | |
2385 | ||
2386 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
2387 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
f2e8b18a | 2388 | |
f01eca2e KP |
2389 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
2390 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
2391 | ||
2392 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
2393 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
2394 | ||
2395 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
2396 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
2397 | ||
2398 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2399 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
2400 | ||
2401 | vbt = dev_priv->edp.pps; | |
2402 | ||
2403 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2404 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
2405 | ||
2406 | #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10) | |
2407 | ||
2408 | intel_dp->panel_power_up_delay = get_delay(t1_t3); | |
2409 | intel_dp->backlight_on_delay = get_delay(t8); | |
2410 | intel_dp->backlight_off_delay = get_delay(t9); | |
2411 | intel_dp->panel_power_down_delay = get_delay(t10); | |
2412 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
2413 | ||
2414 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", | |
2415 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
2416 | intel_dp->panel_power_cycle_delay); | |
2417 | ||
2418 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
2419 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
5d613501 JB |
2420 | |
2421 | ironlake_edp_panel_vdd_on(intel_dp); | |
59f3e272 | 2422 | ret = intel_dp_get_dpcd(intel_dp); |
bd943159 | 2423 | ironlake_edp_panel_vdd_off(intel_dp, false); |
99ea7127 | 2424 | |
59f3e272 | 2425 | if (ret) { |
7183dc29 JB |
2426 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
2427 | dev_priv->no_aux_handshake = | |
2428 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
89667383 JB |
2429 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
2430 | } else { | |
3d3dc149 | 2431 | /* if this fails, presume the device is a ghost */ |
48898b03 | 2432 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
3d3dc149 | 2433 | intel_dp_encoder_destroy(&intel_dp->base.base); |
48898b03 | 2434 | intel_dp_destroy(&intel_connector->base); |
3d3dc149 | 2435 | return; |
89667383 | 2436 | } |
89667383 JB |
2437 | } |
2438 | ||
552fb0b7 KP |
2439 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
2440 | ||
21d40d37 | 2441 | intel_encoder->hot_plug = intel_dp_hot_plug; |
a4fc5ed6 | 2442 | |
4d926461 | 2443 | if (is_edp(intel_dp)) { |
aaa6fd2a MG |
2444 | dev_priv->int_edp_connector = connector; |
2445 | intel_panel_setup_backlight(dev); | |
32f9d658 ZW |
2446 | } |
2447 | ||
f684960e CW |
2448 | intel_dp_add_properties(intel_dp, connector); |
2449 | ||
a4fc5ed6 KP |
2450 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
2451 | * 0xd. Failure to do so will result in spurious interrupts being | |
2452 | * generated on the port when a cable is not attached. | |
2453 | */ | |
2454 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
2455 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
2456 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2457 | } | |
2458 | } |