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drm/i915: Deduplicate PPS register retrieval
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf 50struct dp_link_dpll {
840b32b7 51 int clock;
9dd4ffdf
CML		 52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
840b32b7 56 { 162000,
9dd4ffdf 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
840b32b7 58 { 270000,
9dd4ffdf
CML		 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
840b32b7 63 { 162000,
9dd4ffdf 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
840b32b7 65 { 270000,
9dd4ffdf
CML		 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5 69static const struct dp_link_dpll vlv_dpll[] = {
840b32b7 70 { 162000,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
840b32b7 72 { 270000,
65ce4bf5
CML		 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
840b32b7 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
ef9348c8 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
840b32b7 88 { 270000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
840b32b7 90 { 540000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8
CML		 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15
VS		 97 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 99
cfcb0fc9
JB		 100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
da63a9f2
PZ		 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 112}
113
68b4d824 114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 115{
68b4d824
ID		 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 119}
120
df0e9248
CW		 121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
fa90ecef 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 124}
125
ea5b213a 126static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
f21a2198 132static void intel_dp_unset_edid(struct intel_dp *intel_dp);
a4fc5ed6 133
ed4e9c1d
VS		 134static int
135intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 136{
7183dc29 137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 138
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
141 case DP_LINK_BW_2_7:
1db10e28 142 case DP_LINK_BW_5_4:
d4eead50 143 break;
a4fc5ed6 144 default:
d4eead50
ID		 145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
146 max_link_bw);
a4fc5ed6
KP		 147 max_link_bw = DP_LINK_BW_1_62;
148 break;
149 }
150 return max_link_bw;
151}
152
eeb6324d
PZ		 153static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
154{
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
eeb6324d
PZ		 156 u8 source_max, sink_max;
157
ccb1a831 158 source_max = intel_dig_port->max_lanes;
eeb6324d
PZ		 159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
160
161 return min(source_max, sink_max);
162}
163
cd9dde44
AJ		 164/*
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
167 *
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
169 *
170 * 270000 * 1 * 8 / 10 == 216000
171 *
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
176 *
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
179 */
180
a4fc5ed6 181static int
c898261c 182intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 183{
cd9dde44 184 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 185}
186
fe27d53e
DA		 187static int
188intel_dp_max_data_rate(int max_link_clock, int max_lanes)
189{
190 return (max_link_clock * max_lanes * 8) / 10;
191}
192
c19de8eb 193static enum drm_mode_status
a4fc5ed6
KP		 194intel_dp_mode_valid(struct drm_connector *connector,
195 struct drm_display_mode *mode)
196{
df0e9248 197 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 198 struct intel_connector *intel_connector = to_intel_connector(connector);
199 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 200 int target_clock = mode->clock;
201 int max_rate, mode_rate, max_lanes, max_link_clock;
799487f5 202 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
a4fc5ed6 203
dd06f90e
JN		 204 if (is_edp(intel_dp) && fixed_mode) {
205 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 206 return MODE_PANEL;
207
dd06f90e 208 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 209 return MODE_PANEL;
03afc4a2
DV		 210
211 target_clock = fixed_mode->clock;
7de56f43
ZY		 212 }
213
50fec21a 214 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 215 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 216
217 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
218 mode_rate = intel_dp_link_required(target_clock, 18);
219
799487f5 220 if (mode_rate > max_rate || target_clock > max_dotclk)
c4867936 221 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 222
223 if (mode->clock < 10000)
224 return MODE_CLOCK_LOW;
225
0af78a2b
DV		 226 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
227 return MODE_H_ILLEGAL;
228
a4fc5ed6
KP		 229 return MODE_OK;
230}
231
a4f1289e 232uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 233{
234 int i;
235 uint32_t v = 0;
236
237 if (src_bytes > 4)
238 src_bytes = 4;
239 for (i = 0; i < src_bytes; i++)
240 v |= ((uint32_t) src[i]) << ((3-i) * 8);
241 return v;
242}
243
c2af70e2 244static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 245{
246 int i;
247 if (dst_bytes > 4)
248 dst_bytes = 4;
249 for (i = 0; i < dst_bytes; i++)
250 dst[i] = src >> ((3-i) * 8);
251}
252
bf13e81b
JN		 253static void
254intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 255 struct intel_dp *intel_dp);
bf13e81b
JN		 256static void
257intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 258 struct intel_dp *intel_dp);
bf13e81b 259
773538e8
VS		 260static void pps_lock(struct intel_dp *intel_dp)
261{
262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
263 struct intel_encoder *encoder = &intel_dig_port->base;
264 struct drm_device *dev = encoder->base.dev;
265 struct drm_i915_private *dev_priv = dev->dev_private;
266 enum intel_display_power_domain power_domain;
267
268 /*
269 * See vlv_power_sequencer_reset() why we need
270 * a power domain reference here.
271 */
25f78f58 272 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 273 intel_display_power_get(dev_priv, power_domain);
274
275 mutex_lock(&dev_priv->pps_mutex);
276}
277
278static void pps_unlock(struct intel_dp *intel_dp)
279{
280 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
281 struct intel_encoder *encoder = &intel_dig_port->base;
282 struct drm_device *dev = encoder->base.dev;
283 struct drm_i915_private *dev_priv = dev->dev_private;
284 enum intel_display_power_domain power_domain;
285
286 mutex_unlock(&dev_priv->pps_mutex);
287
25f78f58 288 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 289 intel_display_power_put(dev_priv, power_domain);
290}
291
961a0db0
VS		 292static void
293vlv_power_sequencer_kick(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct drm_device *dev = intel_dig_port->base.base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum pipe pipe = intel_dp->pps_pipe;
0047eedc
VS		 299 bool pll_enabled, release_cl_override = false;
300 enum dpio_phy phy = DPIO_PHY(pipe);
301 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
961a0db0
VS		 302 uint32_t DP;
303
304 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
305 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
306 pipe_name(pipe), port_name(intel_dig_port->port)))
307 return;
308
309 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
310 pipe_name(pipe), port_name(intel_dig_port->port));
311
312 /* Preserve the BIOS-computed detected bit. This is
313 * supposed to be read-only.
314 */
315 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
316 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
317 DP |= DP_PORT_WIDTH(1);
318 DP |= DP_LINK_TRAIN_PAT_1;
319
320 if (IS_CHERRYVIEW(dev))
321 DP |= DP_PIPE_SELECT_CHV(pipe);
322 else if (pipe == PIPE_B)
323 DP |= DP_PIPEB_SELECT;
324
d288f65f
VS		 325 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
326
327 /*
328 * The DPLL for the pipe must be enabled for this to work.
329 * So enable temporarily it if it's not already enabled.
330 */
0047eedc
VS		 331 if (!pll_enabled) {
332 release_cl_override = IS_CHERRYVIEW(dev) &&
333 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
334
3f36b937
TU		 335 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
336 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
337 DRM_ERROR("Failed to force on pll for pipe %c!\n",
338 pipe_name(pipe));
339 return;
340 }
0047eedc 341 }
d288f65f 342
961a0db0
VS		 343 /*
344 * Similar magic as in intel_dp_enable_port().
345 * We _must_ do this port enable + disable trick
346 * to make this power seqeuencer lock onto the port.
347 * Otherwise even VDD force bit won't work.
348 */
349 I915_WRITE(intel_dp->output_reg, DP);
350 POSTING_READ(intel_dp->output_reg);
351
352 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
353 POSTING_READ(intel_dp->output_reg);
354
355 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
356 POSTING_READ(intel_dp->output_reg);
d288f65f 357
0047eedc 358 if (!pll_enabled) {
d288f65f 359 vlv_force_pll_off(dev, pipe);
0047eedc
VS		 360
361 if (release_cl_override)
362 chv_phy_powergate_ch(dev_priv, phy, ch, false);
363 }
961a0db0
VS		 364}
365
bf13e81b
JN		 366static enum pipe
367vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
368{
369 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 370 struct drm_device *dev = intel_dig_port->base.base.dev;
371 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 372 struct intel_encoder *encoder;
373 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 374 enum pipe pipe;
bf13e81b 375
e39b999a 376 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 377
a8c3344e
VS		 378 /* We should never land here with regular DP ports */
379 WARN_ON(!is_edp(intel_dp));
380
a4a5d2f8
VS		 381 if (intel_dp->pps_pipe != INVALID_PIPE)
382 return intel_dp->pps_pipe;
383
384 /*
385 * We don't have power sequencer currently.
386 * Pick one that's not used by other ports.
387 */
19c8054c 388 for_each_intel_encoder(dev, encoder) {
a4a5d2f8
VS		 389 struct intel_dp *tmp;
390
391 if (encoder->type != INTEL_OUTPUT_EDP)
392 continue;
393
394 tmp = enc_to_intel_dp(&encoder->base);
395
396 if (tmp->pps_pipe != INVALID_PIPE)
397 pipes &= ~(1 << tmp->pps_pipe);
398 }
399
400 /*
401 * Didn't find one. This should not happen since there
402 * are two power sequencers and up to two eDP ports.
403 */
404 if (WARN_ON(pipes == 0))
a8c3344e
VS		 405 pipe = PIPE_A;
406 else
407 pipe = ffs(pipes) - 1;
a4a5d2f8 408
a8c3344e
VS		 409 vlv_steal_power_sequencer(dev, pipe);
410 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 411
412 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
413 pipe_name(intel_dp->pps_pipe),
414 port_name(intel_dig_port->port));
415
416 /* init power sequencer on this pipe and port */
36b5f425
VS		 417 intel_dp_init_panel_power_sequencer(dev, intel_dp);
418 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 419
961a0db0
VS		 420 /*
421 * Even vdd force doesn't work until we've made
422 * the power sequencer lock in on the port.
423 */
424 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 425
426 return intel_dp->pps_pipe;
427}
428
78597996
ID		 429static int
430bxt_power_sequencer_idx(struct intel_dp *intel_dp)
431{
432 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
433 struct drm_device *dev = intel_dig_port->base.base.dev;
434 struct drm_i915_private *dev_priv = dev->dev_private;
435
436 lockdep_assert_held(&dev_priv->pps_mutex);
437
438 /* We should never land here with regular DP ports */
439 WARN_ON(!is_edp(intel_dp));
440
441 /*
442 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
443 * mapping needs to be retrieved from VBT, for now just hard-code to
444 * use instance #0 always.
445 */
446 if (!intel_dp->pps_reset)
447 return 0;
448
449 intel_dp->pps_reset = false;
450
451 /*
452 * Only the HW needs to be reprogrammed, the SW state is fixed and
453 * has been setup during connector init.
454 */
455 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
456
457 return 0;
458}
459
6491ab27
VS		 460typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
461 enum pipe pipe);
462
463static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
464 enum pipe pipe)
465{
466 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
467}
468
469static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
470 enum pipe pipe)
471{
472 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
473}
474
475static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
476 enum pipe pipe)
477{
478 return true;
479}
bf13e81b 480
a4a5d2f8 481static enum pipe
6491ab27
VS		 482vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
483 enum port port,
484 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 485{
486 enum pipe pipe;
bf13e81b 487
bf13e81b
JN		 488 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
489 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
490 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 491
492 if (port_sel != PANEL_PORT_SELECT_VLV(port))
493 continue;
494
6491ab27
VS		 495 if (!pipe_check(dev_priv, pipe))
496 continue;
497
a4a5d2f8 498 return pipe;
bf13e81b
JN		 499 }
500
a4a5d2f8
VS		 501 return INVALID_PIPE;
502}
503
504static void
505vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
506{
507 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
508 struct drm_device *dev = intel_dig_port->base.base.dev;
509 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 510 enum port port = intel_dig_port->port;
511
512 lockdep_assert_held(&dev_priv->pps_mutex);
513
514 /* try to find a pipe with this port selected */
6491ab27
VS		 515 /* first pick one where the panel is on */
516 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
517 vlv_pipe_has_pp_on);
518 /* didn't find one? pick one where vdd is on */
519 if (intel_dp->pps_pipe == INVALID_PIPE)
520 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
521 vlv_pipe_has_vdd_on);
522 /* didn't find one? pick one with just the correct port */
523 if (intel_dp->pps_pipe == INVALID_PIPE)
524 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
525 vlv_pipe_any);
a4a5d2f8
VS		 526
527 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
528 if (intel_dp->pps_pipe == INVALID_PIPE) {
529 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
530 port_name(port));
531 return;
bf13e81b
JN		 532 }
533
a4a5d2f8
VS		 534 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
535 port_name(port), pipe_name(intel_dp->pps_pipe));
536
36b5f425
VS		 537 intel_dp_init_panel_power_sequencer(dev, intel_dp);
538 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 539}
540
78597996 541void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
773538e8
VS		 542{
543 struct drm_device *dev = dev_priv->dev;
544 struct intel_encoder *encoder;
545
78597996
ID		 546 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
547 !IS_BROXTON(dev)))
773538e8
VS		 548 return;
549
550 /*
551 * We can't grab pps_mutex here due to deadlock with power_domain
552 * mutex when power_domain functions are called while holding pps_mutex.
553 * That also means that in order to use pps_pipe the code needs to
554 * hold both a power domain reference and pps_mutex, and the power domain
555 * reference get/put must be done while _not_ holding pps_mutex.
556 * pps_{lock,unlock}() do these steps in the correct order, so one
557 * should use them always.
558 */
559
19c8054c 560 for_each_intel_encoder(dev, encoder) {
773538e8
VS		 561 struct intel_dp *intel_dp;
562
563 if (encoder->type != INTEL_OUTPUT_EDP)
564 continue;
565
566 intel_dp = enc_to_intel_dp(&encoder->base);
78597996
ID		 567 if (IS_BROXTON(dev))
568 intel_dp->pps_reset = true;
569 else
570 intel_dp->pps_pipe = INVALID_PIPE;
773538e8 571 }
bf13e81b
JN		 572}
573
8e8232d5
ID		 574struct pps_registers {
575 i915_reg_t pp_ctrl;
576 i915_reg_t pp_stat;
577 i915_reg_t pp_on;
578 i915_reg_t pp_off;
579 i915_reg_t pp_div;
580};
581
582static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
583 struct intel_dp *intel_dp,
584 struct pps_registers *regs)
585{
586 memset(regs, 0, sizeof(*regs));
587
588 if (IS_BROXTON(dev_priv)) {
589 int idx = bxt_power_sequencer_idx(intel_dp);
590
591 regs->pp_ctrl = BXT_PP_CONTROL(idx);
592 regs->pp_stat = BXT_PP_STATUS(idx);
593 regs->pp_on = BXT_PP_ON_DELAYS(idx);
594 regs->pp_off = BXT_PP_OFF_DELAYS(idx);
595 } else if (HAS_PCH_SPLIT(dev_priv)) {
596 regs->pp_ctrl = PCH_PP_CONTROL;
597 regs->pp_stat = PCH_PP_STATUS;
598 regs->pp_on = PCH_PP_ON_DELAYS;
599 regs->pp_off = PCH_PP_OFF_DELAYS;
600 regs->pp_div = PCH_PP_DIVISOR;
601 } else {
602 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
603
604 regs->pp_ctrl = VLV_PIPE_PP_CONTROL(pipe);
605 regs->pp_stat = VLV_PIPE_PP_STATUS(pipe);
606 regs->pp_on = VLV_PIPE_PP_ON_DELAYS(pipe);
607 regs->pp_off = VLV_PIPE_PP_OFF_DELAYS(pipe);
608 regs->pp_div = VLV_PIPE_PP_DIVISOR(pipe);
609 }
610}
611
f0f59a00
VS		 612static i915_reg_t
613_pp_ctrl_reg(struct intel_dp *intel_dp)
bf13e81b 614{
8e8232d5 615 struct pps_registers regs;
bf13e81b 616
8e8232d5
ID		 617 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
618 &regs);
619
620 return regs.pp_ctrl;
bf13e81b
JN		 621}
622
f0f59a00
VS		 623static i915_reg_t
624_pp_stat_reg(struct intel_dp *intel_dp)
bf13e81b 625{
8e8232d5 626 struct pps_registers regs;
bf13e81b 627
8e8232d5
ID		 628 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
629 &regs);
630
631 return regs.pp_stat;
bf13e81b
JN		 632}
633
01527b31
CT		 634/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
635 This function only applicable when panel PM state is not to be tracked */
636static int edp_notify_handler(struct notifier_block *this, unsigned long code,
637 void *unused)
638{
639 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
640 edp_notifier);
641 struct drm_device *dev = intel_dp_to_dev(intel_dp);
642 struct drm_i915_private *dev_priv = dev->dev_private;
01527b31
CT		 643
644 if (!is_edp(intel_dp) || code != SYS_RESTART)
645 return 0;
646
773538e8 647 pps_lock(intel_dp);
e39b999a 648
666a4537 649 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e39b999a 650 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
f0f59a00 651 i915_reg_t pp_ctrl_reg, pp_div_reg;
649636ef 652 u32 pp_div;
e39b999a 653
01527b31
CT		 654 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
655 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
656 pp_div = I915_READ(pp_div_reg);
657 pp_div &= PP_REFERENCE_DIVIDER_MASK;
658
659 /* 0x1F write to PP_DIV_REG sets max cycle delay */
660 I915_WRITE(pp_div_reg, pp_div | 0x1F);
661 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
662 msleep(intel_dp->panel_power_cycle_delay);
663 }
664
773538e8 665 pps_unlock(intel_dp);
e39b999a 666
01527b31
CT		 667 return 0;
668}
669
4be73780 670static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 671{
30add22d 672 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 673 struct drm_i915_private *dev_priv = dev->dev_private;
674
e39b999a
VS		 675 lockdep_assert_held(&dev_priv->pps_mutex);
676
666a4537 677 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 678 intel_dp->pps_pipe == INVALID_PIPE)
679 return false;
680
bf13e81b 681 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 682}
683
4be73780 684static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 685{
30add22d 686 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 687 struct drm_i915_private *dev_priv = dev->dev_private;
688
e39b999a
VS		 689 lockdep_assert_held(&dev_priv->pps_mutex);
690
666a4537 691 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 692 intel_dp->pps_pipe == INVALID_PIPE)
693 return false;
694
773538e8 695 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 696}
697
9b984dae
KP		 698static void
699intel_dp_check_edp(struct intel_dp *intel_dp)
700{
30add22d 701 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 702 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 703
9b984dae
KP		 704 if (!is_edp(intel_dp))
705 return;
453c5420 706
4be73780 707 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 708 WARN(1, "eDP powered off while attempting aux channel communication.\n");
709 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 710 I915_READ(_pp_stat_reg(intel_dp)),
711 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 712 }
713}
714
9ee32fea
DV		 715static uint32_t
716intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
717{
718 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
719 struct drm_device *dev = intel_dig_port->base.base.dev;
720 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 721 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 722 uint32_t status;
723 bool done;
724
ef04f00d 725#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 726 if (has_aux_irq)
b18ac466 727 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 728 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 729 else
730 done = wait_for_atomic(C, 10) == 0;
731 if (!done)
732 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
733 has_aux_irq);
734#undef C
735
736 return status;
737}
738
6ffb1be7 739static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 740{
174edf1f 741 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
e7dc33f3 742 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
9ee32fea 743
a457f54b
VS		 744 if (index)
745 return 0;
746
ec5b01dd
DL		 747 /*
748 * The clock divider is based off the hrawclk, and would like to run at
a457f54b 749 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
a4fc5ed6 750 */
a457f54b 751 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 752}
753
754static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
755{
756 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 757 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd
DL		 758
759 if (index)
760 return 0;
761
a457f54b
VS		 762 /*
763 * The clock divider is based off the cdclk or PCH rawclk, and would
764 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
765 * divide by 2000 and use that
766 */
e7dc33f3 767 if (intel_dig_port->port == PORT_A)
fce18c4c 768 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
e7dc33f3
VS		 769 else
770 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 771}
772
773static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
774{
775 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 776 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd 777
a457f54b 778 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
2c55c336 779 /* Workaround for non-ULT HSW */
bc86625a
CW		 780 switch (index) {
781 case 0: return 63;
782 case 1: return 72;
783 default: return 0;
784 }
2c55c336 785 }
a457f54b
VS		 786
787 return ilk_get_aux_clock_divider(intel_dp, index);
b84a1cf8
RV		 788}
789
b6b5e383
DL		 790static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
791{
792 /*
793 * SKL doesn't need us to program the AUX clock divider (Hardware will
794 * derive the clock from CDCLK automatically). We still implement the
795 * get_aux_clock_divider vfunc to plug-in into the existing code.
796 */
797 return index ? 0 : 1;
798}
799
6ffb1be7
VS		 800static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
801 bool has_aux_irq,
802 int send_bytes,
803 uint32_t aux_clock_divider)
5ed12a19
DL		 804{
805 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
806 struct drm_device *dev = intel_dig_port->base.base.dev;
807 uint32_t precharge, timeout;
808
809 if (IS_GEN6(dev))
810 precharge = 3;
811 else
812 precharge = 5;
813
f3c6a3a7 814 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
5ed12a19
DL		 815 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
816 else
817 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
818
819 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 820 DP_AUX_CH_CTL_DONE |
5ed12a19 821 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 822 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 823 timeout |
788d4433 824 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 825 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
826 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 827 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 828}
829
b9ca5fad
DL		 830static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
831 bool has_aux_irq,
832 int send_bytes,
833 uint32_t unused)
834{
835 return DP_AUX_CH_CTL_SEND_BUSY |
836 DP_AUX_CH_CTL_DONE |
837 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
838 DP_AUX_CH_CTL_TIME_OUT_ERROR |
839 DP_AUX_CH_CTL_TIME_OUT_1600us |
840 DP_AUX_CH_CTL_RECEIVE_ERROR |
841 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
d4dcbdce 842 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
b9ca5fad
DL		 843 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
844}
845
b84a1cf8
RV		 846static int
847intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 848 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 849 uint8_t *recv, int recv_size)
850{
851 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
852 struct drm_device *dev = intel_dig_port->base.base.dev;
853 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 854 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
bc86625a 855 uint32_t aux_clock_divider;
b84a1cf8
RV		 856 int i, ret, recv_bytes;
857 uint32_t status;
5ed12a19 858 int try, clock = 0;
4e6b788c 859 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 860 bool vdd;
861
773538e8 862 pps_lock(intel_dp);
e39b999a 863
72c3500a
VS		 864 /*
865 * We will be called with VDD already enabled for dpcd/edid/oui reads.
866 * In such cases we want to leave VDD enabled and it's up to upper layers
867 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
868 * ourselves.
869 */
1e0560e0 870 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 871
872 /* dp aux is extremely sensitive to irq latency, hence request the
873 * lowest possible wakeup latency and so prevent the cpu from going into
874 * deep sleep states.
875 */
876 pm_qos_update_request(&dev_priv->pm_qos, 0);
877
878 intel_dp_check_edp(intel_dp);
5eb08b69 879
11bee43e
JB		 880 /* Try to wait for any previous AUX channel activity */
881 for (try = 0; try < 3; try++) {
ef04f00d 882 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 883 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
884 break;
885 msleep(1);
886 }
887
888 if (try == 3) {
02196c77
MK		 889 static u32 last_status = -1;
890 const u32 status = I915_READ(ch_ctl);
891
892 if (status != last_status) {
893 WARN(1, "dp_aux_ch not started status 0x%08x\n",
894 status);
895 last_status = status;
896 }
897
9ee32fea
DV		 898 ret = -EBUSY;
899 goto out;
4f7f7b7e
CW		 900 }
901
46a5ae9f
PZ		 902 /* Only 5 data registers! */
903 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
904 ret = -E2BIG;
905 goto out;
906 }
907
ec5b01dd 908 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 909 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
910 has_aux_irq,
911 send_bytes,
912 aux_clock_divider);
5ed12a19 913
bc86625a
CW		 914 /* Must try at least 3 times according to DP spec */
915 for (try = 0; try < 5; try++) {
916 /* Load the send data into the aux channel data registers */
917 for (i = 0; i < send_bytes; i += 4)
330e20ec 918 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
a4f1289e
RV		 919 intel_dp_pack_aux(send + i,
920 send_bytes - i));
bc86625a
CW		 921
922 /* Send the command and wait for it to complete */
5ed12a19 923 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 924
925 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
926
927 /* Clear done status and any errors */
928 I915_WRITE(ch_ctl,
929 status |
930 DP_AUX_CH_CTL_DONE |
931 DP_AUX_CH_CTL_TIME_OUT_ERROR |
932 DP_AUX_CH_CTL_RECEIVE_ERROR);
933
74ebf294 934 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 935 continue;
74ebf294
TP		 936
937 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
938 * 400us delay required for errors and timeouts
939 * Timeout errors from the HW already meet this
940 * requirement so skip to next iteration
941 */
942 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
943 usleep_range(400, 500);
bc86625a 944 continue;
74ebf294 945 }
bc86625a 946 if (status & DP_AUX_CH_CTL_DONE)
e058c945 947 goto done;
bc86625a 948 }
a4fc5ed6
KP		 949 }
950
a4fc5ed6 951 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 952 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 953 ret = -EBUSY;
954 goto out;
a4fc5ed6
KP		 955 }
956
e058c945 957done:
a4fc5ed6
KP		 958 /* Check for timeout or receive error.
959 * Timeouts occur when the sink is not connected
960 */
a5b3da54 961 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 962 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 963 ret = -EIO;
964 goto out;
a5b3da54 965 }
1ae8c0a5
KP		 966
967 /* Timeouts occur when the device isn't connected, so they're
968 * "normal" -- don't fill the kernel log with these */
a5b3da54 969 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 970 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 971 ret = -ETIMEDOUT;
972 goto out;
a4fc5ed6
KP		 973 }
974
975 /* Unload any bytes sent back from the other side */
976 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
977 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
14e01889
RV		 978
979 /*
980 * By BSpec: "Message sizes of 0 or >20 are not allowed."
981 * We have no idea of what happened so we return -EBUSY so
982 * drm layer takes care for the necessary retries.
983 */
984 if (recv_bytes == 0 || recv_bytes > 20) {
985 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
986 recv_bytes);
987 /*
988 * FIXME: This patch was created on top of a series that
989 * organize the retries at drm level. There EBUSY should
990 * also take care for 1ms wait before retrying.
991 * That aux retries re-org is still needed and after that is
992 * merged we remove this sleep from here.
993 */
994 usleep_range(1000, 1500);
995 ret = -EBUSY;
996 goto out;
997 }
998
a4fc5ed6
KP		 999 if (recv_bytes > recv_size)
1000 recv_bytes = recv_size;
0206e353 1001
4f7f7b7e 1002 for (i = 0; i < recv_bytes; i += 4)
330e20ec 1003 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
a4f1289e 1004 recv + i, recv_bytes - i);
a4fc5ed6 1005
9ee32fea
DV		 1006 ret = recv_bytes;
1007out:
1008 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1009
884f19e9
JN		 1010 if (vdd)
1011 edp_panel_vdd_off(intel_dp, false);
1012
773538e8 1013 pps_unlock(intel_dp);
e39b999a 1014
9ee32fea 1015 return ret;
a4fc5ed6
KP		 1016}
1017
a6c8aff0
JN		 1018#define BARE_ADDRESS_SIZE 3
1019#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 1020static ssize_t
1021intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 1022{
9d1a1031
JN		 1023 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1024 uint8_t txbuf[20], rxbuf[20];
1025 size_t txsize, rxsize;
a4fc5ed6 1026 int ret;
a4fc5ed6 1027
d2d9cbbd
VS		 1028 txbuf[0] = (msg->request << 4) |
1029 ((msg->address >> 16) & 0xf);
1030 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 1031 txbuf[2] = msg->address & 0xff;
1032 txbuf[3] = msg->size - 1;
46a5ae9f 1033
9d1a1031
JN		 1034 switch (msg->request & ~DP_AUX_I2C_MOT) {
1035 case DP_AUX_NATIVE_WRITE:
1036 case DP_AUX_I2C_WRITE:
c1e74122 1037 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
a6c8aff0 1038 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 1039 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 1040
9d1a1031
JN		 1041 if (WARN_ON(txsize > 20))
1042 return -E2BIG;
a4fc5ed6 1043
d81a67cc
ID		 1044 if (msg->buffer)
1045 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1046 else
1047 WARN_ON(msg->size);
a4fc5ed6 1048
9d1a1031
JN		 1049 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1050 if (ret > 0) {
1051 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 1052
a1ddefd8
JN		 1053 if (ret > 1) {
1054 /* Number of bytes written in a short write. */
1055 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1056 } else {
1057 /* Return payload size. */
1058 ret = msg->size;
1059 }
9d1a1031
JN		 1060 }
1061 break;
46a5ae9f 1062
9d1a1031
JN		 1063 case DP_AUX_NATIVE_READ:
1064 case DP_AUX_I2C_READ:
a6c8aff0 1065 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 1066 rxsize = msg->size + 1;
a4fc5ed6 1067
9d1a1031
JN		 1068 if (WARN_ON(rxsize > 20))
1069 return -E2BIG;
a4fc5ed6 1070
9d1a1031
JN		 1071 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1072 if (ret > 0) {
1073 msg->reply = rxbuf[0] >> 4;
1074 /*
1075 * Assume happy day, and copy the data. The caller is
1076 * expected to check msg->reply before touching it.
1077 *
1078 * Return payload size.
1079 */
1080 ret--;
1081 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1082 }
9d1a1031
JN		 1083 break;
1084
1085 default:
1086 ret = -EINVAL;
1087 break;
a4fc5ed6 1088 }
f51a44b9 1089
9d1a1031 1090 return ret;
a4fc5ed6
KP		 1091}
1092
f0f59a00
VS		 1093static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1094 enum port port)
da00bdcf
VS		 1095{
1096 switch (port) {
1097 case PORT_B:
1098 case PORT_C:
1099 case PORT_D:
1100 return DP_AUX_CH_CTL(port);
1101 default:
1102 MISSING_CASE(port);
1103 return DP_AUX_CH_CTL(PORT_B);
1104 }
1105}
1106
f0f59a00
VS		 1107static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1108 enum port port, int index)
330e20ec
VS		 1109{
1110 switch (port) {
1111 case PORT_B:
1112 case PORT_C:
1113 case PORT_D:
1114 return DP_AUX_CH_DATA(port, index);
1115 default:
1116 MISSING_CASE(port);
1117 return DP_AUX_CH_DATA(PORT_B, index);
1118 }
1119}
1120
f0f59a00
VS		 1121static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1122 enum port port)
da00bdcf
VS		 1123{
1124 switch (port) {
1125 case PORT_A:
1126 return DP_AUX_CH_CTL(port);
1127 case PORT_B:
1128 case PORT_C:
1129 case PORT_D:
1130 return PCH_DP_AUX_CH_CTL(port);
1131 default:
1132 MISSING_CASE(port);
1133 return DP_AUX_CH_CTL(PORT_A);
1134 }
1135}
1136
f0f59a00
VS		 1137static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1138 enum port port, int index)
330e20ec
VS		 1139{
1140 switch (port) {
1141 case PORT_A:
1142 return DP_AUX_CH_DATA(port, index);
1143 case PORT_B:
1144 case PORT_C:
1145 case PORT_D:
1146 return PCH_DP_AUX_CH_DATA(port, index);
1147 default:
1148 MISSING_CASE(port);
1149 return DP_AUX_CH_DATA(PORT_A, index);
1150 }
1151}
1152
da00bdcf
VS		 1153/*
1154 * On SKL we don't have Aux for port E so we rely
1155 * on VBT to set a proper alternate aux channel.
1156 */
1157static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1158{
1159 const struct ddi_vbt_port_info *info =
1160 &dev_priv->vbt.ddi_port_info[PORT_E];
1161
1162 switch (info->alternate_aux_channel) {
1163 case DP_AUX_A:
1164 return PORT_A;
1165 case DP_AUX_B:
1166 return PORT_B;
1167 case DP_AUX_C:
1168 return PORT_C;
1169 case DP_AUX_D:
1170 return PORT_D;
1171 default:
1172 MISSING_CASE(info->alternate_aux_channel);
1173 return PORT_A;
1174 }
1175}
1176
f0f59a00
VS		 1177static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1178 enum port port)
da00bdcf
VS		 1179{
1180 if (port == PORT_E)
1181 port = skl_porte_aux_port(dev_priv);
1182
1183 switch (port) {
1184 case PORT_A:
1185 case PORT_B:
1186 case PORT_C:
1187 case PORT_D:
1188 return DP_AUX_CH_CTL(port);
1189 default:
1190 MISSING_CASE(port);
1191 return DP_AUX_CH_CTL(PORT_A);
1192 }
1193}
1194
f0f59a00
VS		 1195static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1196 enum port port, int index)
330e20ec
VS		 1197{
1198 if (port == PORT_E)
1199 port = skl_porte_aux_port(dev_priv);
1200
1201 switch (port) {
1202 case PORT_A:
1203 case PORT_B:
1204 case PORT_C:
1205 case PORT_D:
1206 return DP_AUX_CH_DATA(port, index);
1207 default:
1208 MISSING_CASE(port);
1209 return DP_AUX_CH_DATA(PORT_A, index);
1210 }
1211}
1212
f0f59a00
VS		 1213static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1214 enum port port)
330e20ec
VS		 1215{
1216 if (INTEL_INFO(dev_priv)->gen >= 9)
1217 return skl_aux_ctl_reg(dev_priv, port);
1218 else if (HAS_PCH_SPLIT(dev_priv))
1219 return ilk_aux_ctl_reg(dev_priv, port);
1220 else
1221 return g4x_aux_ctl_reg(dev_priv, port);
1222}
1223
f0f59a00
VS		 1224static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1225 enum port port, int index)
330e20ec
VS		 1226{
1227 if (INTEL_INFO(dev_priv)->gen >= 9)
1228 return skl_aux_data_reg(dev_priv, port, index);
1229 else if (HAS_PCH_SPLIT(dev_priv))
1230 return ilk_aux_data_reg(dev_priv, port, index);
1231 else
1232 return g4x_aux_data_reg(dev_priv, port, index);
1233}
1234
1235static void intel_aux_reg_init(struct intel_dp *intel_dp)
1236{
1237 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1238 enum port port = dp_to_dig_port(intel_dp)->port;
1239 int i;
1240
1241 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1242 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1243 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1244}
1245
9d1a1031 1246static void
a121f4e5
VS		 1247intel_dp_aux_fini(struct intel_dp *intel_dp)
1248{
1249 drm_dp_aux_unregister(&intel_dp->aux);
1250 kfree(intel_dp->aux.name);
1251}
1252
1253static int
9d1a1031
JN		 1254intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1255{
33ad6626
JN		 1256 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1257 enum port port = intel_dig_port->port;
ab2c0672
DA		 1258 int ret;
1259
330e20ec 1260 intel_aux_reg_init(intel_dp);
8316f337 1261
a121f4e5
VS		 1262 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1263 if (!intel_dp->aux.name)
1264 return -ENOMEM;
1265
4d32c0d8 1266 intel_dp->aux.dev = connector->base.kdev;
9d1a1031 1267 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1268
a121f4e5
VS		 1269 DRM_DEBUG_KMS("registering %s bus for %s\n",
1270 intel_dp->aux.name,
0b99836f 1271 connector->base.kdev->kobj.name);
8316f337 1272
4f71d0cb 1273 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1274 if (ret < 0) {
4f71d0cb 1275 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
a121f4e5
VS		 1276 intel_dp->aux.name, ret);
1277 kfree(intel_dp->aux.name);
1278 return ret;
ab2c0672 1279 }
8a5e6aeb 1280
a121f4e5 1281 return 0;
a4fc5ed6
KP		 1282}
1283
80f65de3
ID		 1284static void
1285intel_dp_connector_unregister(struct intel_connector *intel_connector)
1286{
1287 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1288
4d32c0d8 1289 intel_dp_aux_fini(intel_dp);
80f65de3
ID		 1290 intel_connector_unregister(intel_connector);
1291}
1292
fc0f8e25 1293static int
12f6a2e2 1294intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1295{
94ca719e
VS		 1296 if (intel_dp->num_sink_rates) {
1297 *sink_rates = intel_dp->sink_rates;
1298 return intel_dp->num_sink_rates;
fc0f8e25 1299 }
12f6a2e2
VS		 1300
1301 *sink_rates = default_rates;
1302
1303 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1304}
1305
e588fa18 1306bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
ed63baaf 1307{
e588fa18
ACO		 1308 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1309 struct drm_device *dev = dig_port->base.base.dev;
1310
ed63baaf 1311 /* WaDisableHBR2:skl */
e87a005d 1312 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
ed63baaf
TS		 1313 return false;
1314
1315 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1316 (INTEL_INFO(dev)->gen >= 9))
1317 return true;
1318 else
1319 return false;
1320}
1321
a8f3ef61 1322static int
e588fa18 1323intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
a8f3ef61 1324{
e588fa18
ACO		 1325 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1326 struct drm_device *dev = dig_port->base.base.dev;
af7080f5
TS		 1327 int size;
1328
64987fc5
SJ		 1329 if (IS_BROXTON(dev)) {
1330 *source_rates = bxt_rates;
af7080f5 1331 size = ARRAY_SIZE(bxt_rates);
ef11bdb3 1332 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
637a9c63 1333 *source_rates = skl_rates;
af7080f5
TS		 1334 size = ARRAY_SIZE(skl_rates);
1335 } else {
1336 *source_rates = default_rates;
1337 size = ARRAY_SIZE(default_rates);
a8f3ef61 1338 }
636280ba 1339
ed63baaf 1340 /* This depends on the fact that 5.4 is last value in the array */
e588fa18 1341 if (!intel_dp_source_supports_hbr2(intel_dp))
af7080f5 1342 size--;
636280ba 1343
af7080f5 1344 return size;
a8f3ef61
SJ		 1345}
1346
c6bb3538
DV		 1347static void
1348intel_dp_set_clock(struct intel_encoder *encoder,
840b32b7 1349 struct intel_crtc_state *pipe_config)
c6bb3538
DV		 1350{
1351 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1352 const struct dp_link_dpll *divisor = NULL;
1353 int i, count = 0;
c6bb3538
DV		 1354
1355 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1356 divisor = gen4_dpll;
1357 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1358 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1359 divisor = pch_dpll;
1360 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1361 } else if (IS_CHERRYVIEW(dev)) {
1362 divisor = chv_dpll;
1363 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1364 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1365 divisor = vlv_dpll;
1366 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1367 }
9dd4ffdf
CML		 1368
1369 if (divisor && count) {
1370 for (i = 0; i < count; i++) {
840b32b7 1371 if (pipe_config->port_clock == divisor[i].clock) {
9dd4ffdf
CML		 1372 pipe_config->dpll = divisor[i].dpll;
1373 pipe_config->clock_set = true;
1374 break;
1375 }
1376 }
c6bb3538
DV		 1377 }
1378}
1379
2ecae76a
VS		 1380static int intersect_rates(const int *source_rates, int source_len,
1381 const int *sink_rates, int sink_len,
94ca719e 1382 int *common_rates)
a8f3ef61
SJ		 1383{
1384 int i = 0, j = 0, k = 0;
1385
a8f3ef61
SJ		 1386 while (i < source_len && j < sink_len) {
1387 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1388 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1389 return k;
94ca719e 1390 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1391 ++k;
1392 ++i;
1393 ++j;
1394 } else if (source_rates[i] < sink_rates[j]) {
1395 ++i;
1396 } else {
1397 ++j;
1398 }
1399 }
1400 return k;
1401}
1402
94ca719e
VS		 1403static int intel_dp_common_rates(struct intel_dp *intel_dp,
1404 int *common_rates)
2ecae76a 1405{
2ecae76a
VS		 1406 const int *source_rates, *sink_rates;
1407 int source_len, sink_len;
1408
1409 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
e588fa18 1410 source_len = intel_dp_source_rates(intel_dp, &source_rates);
2ecae76a
VS		 1411
1412 return intersect_rates(source_rates, source_len,
1413 sink_rates, sink_len,
94ca719e 1414 common_rates);
2ecae76a
VS		 1415}
1416
0336400e
VS		 1417static void snprintf_int_array(char *str, size_t len,
1418 const int *array, int nelem)
1419{
1420 int i;
1421
1422 str[0] = '\0';
1423
1424 for (i = 0; i < nelem; i++) {
b2f505be 1425 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1426 if (r >= len)
1427 return;
1428 str += r;
1429 len -= r;
1430 }
1431}
1432
1433static void intel_dp_print_rates(struct intel_dp *intel_dp)
1434{
0336400e 1435 const int *source_rates, *sink_rates;
94ca719e
VS		 1436 int source_len, sink_len, common_len;
1437 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1438 char str[128]; /* FIXME: too big for stack? */
1439
1440 if ((drm_debug & DRM_UT_KMS) == 0)
1441 return;
1442
e588fa18 1443 source_len = intel_dp_source_rates(intel_dp, &source_rates);
0336400e
VS		 1444 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1445 DRM_DEBUG_KMS("source rates: %s\n", str);
1446
1447 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1448 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1449 DRM_DEBUG_KMS("sink rates: %s\n", str);
1450
94ca719e
VS		 1451 common_len = intel_dp_common_rates(intel_dp, common_rates);
1452 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1453 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1454}
1455
f4896f15 1456static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1457{
1458 int i = 0;
1459
1460 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1461 if (find == rates[i])
1462 break;
1463
1464 return i;
1465}
1466
50fec21a
VS		 1467int
1468intel_dp_max_link_rate(struct intel_dp *intel_dp)
1469{
1470 int rates[DP_MAX_SUPPORTED_RATES] = {};
1471 int len;
1472
94ca719e 1473 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1474 if (WARN_ON(len <= 0))
1475 return 162000;
1476
1477 return rates[rate_to_index(0, rates) - 1];
1478}
1479
ed4e9c1d
VS		 1480int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1481{
94ca719e 1482 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1483}
1484
94223d04
ACO		 1485void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1486 uint8_t *link_bw, uint8_t *rate_select)
04a60f9f
VS		 1487{
1488 if (intel_dp->num_sink_rates) {
1489 *link_bw = 0;
1490 *rate_select =
1491 intel_dp_rate_select(intel_dp, port_clock);
1492 } else {
1493 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1494 *rate_select = 0;
1495 }
1496}
1497
00c09d70 1498bool
5bfe2ac0 1499intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1500 struct intel_crtc_state *pipe_config)
a4fc5ed6 1501{
5bfe2ac0 1502 struct drm_device *dev = encoder->base.dev;
36008365 1503 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1504 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1505 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1506 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1507 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1508 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1509 int lane_count, clock;
56071a20 1510 int min_lane_count = 1;
eeb6324d 1511 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1512 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1513 int min_clock = 0;
a8f3ef61 1514 int max_clock;
083f9560 1515 int bpp, mode_rate;
ff9a6750 1516 int link_avail, link_clock;
94ca719e
VS		 1517 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1518 int common_len;
04a60f9f 1519 uint8_t link_bw, rate_select;
a8f3ef61 1520
94ca719e 1521 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1522
1523 /* No common link rates between source and sink */
94ca719e 1524 WARN_ON(common_len <= 0);
a8f3ef61 1525
94ca719e 1526 max_clock = common_len - 1;
a4fc5ed6 1527
bc7d38a4 1528 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1529 pipe_config->has_pch_encoder = true;
1530
03afc4a2 1531 pipe_config->has_dp_encoder = true;
f769cd24 1532 pipe_config->has_drrs = false;
9fcb1704 1533 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1534
dd06f90e
JN		 1535 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1536 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1537 adjusted_mode);
a1b2278e
CK		 1538
1539 if (INTEL_INFO(dev)->gen >= 9) {
1540 int ret;
e435d6e5 1541 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1542 if (ret)
1543 return ret;
1544 }
1545
b5667627 1546 if (HAS_GMCH_DISPLAY(dev))
2dd24552
JB		 1547 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1548 intel_connector->panel.fitting_mode);
1549 else
b074cec8
JB		 1550 intel_pch_panel_fitting(intel_crtc, pipe_config,
1551 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1552 }
1553
cb1793ce 1554 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1555 return false;
1556
083f9560 1557 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1558 "max bw %d pixel clock %iKHz\n",
94ca719e 1559 max_lane_count, common_rates[max_clock],
241bfc38 1560 adjusted_mode->crtc_clock);
083f9560 1561
36008365
DV		 1562 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1563 * bpc in between. */
3e7ca985 1564 bpp = pipe_config->pipe_bpp;
56071a20 1565 if (is_edp(intel_dp)) {
22ce5628
TS		 1566
1567 /* Get bpp from vbt only for panels that dont have bpp in edid */
1568 if (intel_connector->base.display_info.bpc == 0 &&
6aa23e65 1569 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
56071a20 1570 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
6aa23e65
JN		 1571 dev_priv->vbt.edp.bpp);
1572 bpp = dev_priv->vbt.edp.bpp;
56071a20
JN		 1573 }
1574
344c5bbc
JN		 1575 /*
1576 * Use the maximum clock and number of lanes the eDP panel
1577 * advertizes being capable of. The panels are generally
1578 * designed to support only a single clock and lane
1579 * configuration, and typically these values correspond to the
1580 * native resolution of the panel.
1581 */
1582 min_lane_count = max_lane_count;
1583 min_clock = max_clock;
7984211e 1584 }
657445fe 1585
36008365 1586 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1587 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1588 bpp);
36008365 1589
c6930992 1590 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1591 for (lane_count = min_lane_count;
1592 lane_count <= max_lane_count;
1593 lane_count <<= 1) {
1594
94ca719e 1595 link_clock = common_rates[clock];
36008365
DV		 1596 link_avail = intel_dp_max_data_rate(link_clock,
1597 lane_count);
1598
1599 if (mode_rate <= link_avail) {
1600 goto found;
1601 }
1602 }
1603 }
1604 }
c4867936 1605
36008365 1606 return false;
3685a8f3 1607
36008365 1608found:
55bc60db
VS		 1609 if (intel_dp->color_range_auto) {
1610 /*
1611 * See:
1612 * CEA-861-E - 5.1 Default Encoding Parameters
1613 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1614 */
0f2a2a75
VS		 1615 pipe_config->limited_color_range =
1616 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1617 } else {
1618 pipe_config->limited_color_range =
1619 intel_dp->limited_color_range;
55bc60db
VS		 1620 }
1621
90a6b7b0 1622 pipe_config->lane_count = lane_count;
a8f3ef61 1623
657445fe 1624 pipe_config->pipe_bpp = bpp;
94ca719e 1625 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1626
04a60f9f
VS		 1627 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1628 &link_bw, &rate_select);
1629
1630 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1631 link_bw, rate_select, pipe_config->lane_count,
ff9a6750 1632 pipe_config->port_clock, bpp);
36008365
DV		 1633 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1634 mode_rate, link_avail);
a4fc5ed6 1635
03afc4a2 1636 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1637 adjusted_mode->crtc_clock,
1638 pipe_config->port_clock,
03afc4a2 1639 &pipe_config->dp_m_n);
9d1a455b 1640
439d7ac0 1641 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1642 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1643 pipe_config->has_drrs = true;
439d7ac0
PB		 1644 intel_link_compute_m_n(bpp, lane_count,
1645 intel_connector->panel.downclock_mode->clock,
1646 pipe_config->port_clock,
1647 &pipe_config->dp_m2_n2);
1648 }
1649
14d41b3b
VS		 1650 /*
1651 * DPLL0 VCO may need to be adjusted to get the correct
1652 * clock for eDP. This will affect cdclk as well.
1653 */
1654 if (is_edp(intel_dp) &&
1655 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1656 int vco;
1657
1658 switch (pipe_config->port_clock / 2) {
1659 case 108000:
1660 case 216000:
63911d72 1661 vco = 8640000;
14d41b3b
VS		 1662 break;
1663 default:
63911d72 1664 vco = 8100000;
14d41b3b
VS		 1665 break;
1666 }
1667
1668 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1669 }
1670
a3c988ea 1671 if (!HAS_DDI(dev))
840b32b7 1672 intel_dp_set_clock(encoder, pipe_config);
c6bb3538 1673
03afc4a2 1674 return true;
a4fc5ed6
KP		 1675}
1676
901c2daf
VS		 1677void intel_dp_set_link_params(struct intel_dp *intel_dp,
1678 const struct intel_crtc_state *pipe_config)
1679{
1680 intel_dp->link_rate = pipe_config->port_clock;
1681 intel_dp->lane_count = pipe_config->lane_count;
1682}
1683
8ac33ed3 1684static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1685{
b934223d 1686 struct drm_device *dev = encoder->base.dev;
417e822d 1687 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1688 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1689 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1690 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
7c5f93b0 1691 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1692
901c2daf
VS		 1693 intel_dp_set_link_params(intel_dp, crtc->config);
1694
417e822d 1695 /*
1a2eb460 1696 * There are four kinds of DP registers:
417e822d
KP		 1697 *
1698 * IBX PCH
1a2eb460
KP		 1699 * SNB CPU
1700 * IVB CPU
417e822d
KP		 1701 * CPT PCH
1702 *
1703 * IBX PCH and CPU are the same for almost everything,
1704 * except that the CPU DP PLL is configured in this
1705 * register
1706 *
1707 * CPT PCH is quite different, having many bits moved
1708 * to the TRANS_DP_CTL register instead. That
1709 * configuration happens (oddly) in ironlake_pch_enable
1710 */
9c9e7927 1711
417e822d
KP		 1712 /* Preserve the BIOS-computed detected bit. This is
1713 * supposed to be read-only.
1714 */
1715 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1716
417e822d 1717 /* Handle DP bits in common between all three register formats */
417e822d 1718 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
90a6b7b0 1719 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
a4fc5ed6 1720
417e822d 1721 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1722
39e5fa88 1723 if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1724 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1725 intel_dp->DP |= DP_SYNC_HS_HIGH;
1726 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1727 intel_dp->DP |= DP_SYNC_VS_HIGH;
1728 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1729
6aba5b6c 1730 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1731 intel_dp->DP |= DP_ENHANCED_FRAMING;
1732
7c62a164 1733 intel_dp->DP |= crtc->pipe << 29;
39e5fa88 1734 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
e3ef4479
VS		 1735 u32 trans_dp;
1736
39e5fa88 1737 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1738
1739 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1740 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1741 trans_dp |= TRANS_DP_ENH_FRAMING;
1742 else
1743 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1744 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1745 } else {
0f2a2a75 1746 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 1747 !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
0f2a2a75 1748 intel_dp->DP |= DP_COLOR_RANGE_16_235;
417e822d
KP		 1749
1750 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1751 intel_dp->DP |= DP_SYNC_HS_HIGH;
1752 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1753 intel_dp->DP |= DP_SYNC_VS_HIGH;
1754 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1755
6aba5b6c 1756 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1757 intel_dp->DP |= DP_ENHANCED_FRAMING;
1758
39e5fa88 1759 if (IS_CHERRYVIEW(dev))
44f37d1f 1760 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1761 else if (crtc->pipe == PIPE_B)
1762 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1763 }
a4fc5ed6
KP		 1764}
1765
ffd6749d
PZ		 1766#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1767#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1768
1a5ef5b7
PZ		 1769#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1770#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1771
ffd6749d
PZ		 1772#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1773#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1774
4be73780 1775static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1776 u32 mask,
1777 u32 value)
bd943159 1778{
30add22d 1779 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1780 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 1781 i915_reg_t pp_stat_reg, pp_ctrl_reg;
453c5420 1782
e39b999a
VS		 1783 lockdep_assert_held(&dev_priv->pps_mutex);
1784
bf13e81b
JN		 1785 pp_stat_reg = _pp_stat_reg(intel_dp);
1786 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1787
99ea7127 1788 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1789 mask, value,
1790 I915_READ(pp_stat_reg),
1791 I915_READ(pp_ctrl_reg));
32ce697c 1792
3f177625
TU		 1793 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value,
1794 5 * USEC_PER_SEC, 10 * USEC_PER_MSEC))
99ea7127 1795 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1796 I915_READ(pp_stat_reg),
1797 I915_READ(pp_ctrl_reg));
54c136d4
CW		 1798
1799 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1800}
32ce697c 1801
4be73780 1802static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1803{
1804 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1805 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1806}
1807
4be73780 1808static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1809{
1810 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1811 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1812}
1813
4be73780 1814static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127 1815{
d28d4731
AK		 1816 ktime_t panel_power_on_time;
1817 s64 panel_power_off_duration;
1818
99ea7127 1819 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c 1820
d28d4731
AK		 1821 /* take the difference of currrent time and panel power off time
1822 * and then make panel wait for t11_t12 if needed. */
1823 panel_power_on_time = ktime_get_boottime();
1824 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1825
dce56b3c
PZ		 1826 /* When we disable the VDD override bit last we have to do the manual
1827 * wait. */
d28d4731
AK		 1828 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1829 wait_remaining_ms_from_jiffies(jiffies,
1830 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
dce56b3c 1831
4be73780 1832 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1833}
1834
4be73780 1835static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1836{
1837 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1838 intel_dp->backlight_on_delay);
1839}
1840
4be73780 1841static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1842{
1843 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1844 intel_dp->backlight_off_delay);
1845}
99ea7127 1846
832dd3c1
KP		 1847/* Read the current pp_control value, unlocking the register if it
1848 * is locked
1849 */
1850
453c5420 1851static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1852{
453c5420
JB		 1853 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1854 struct drm_i915_private *dev_priv = dev->dev_private;
1855 u32 control;
832dd3c1 1856
e39b999a
VS		 1857 lockdep_assert_held(&dev_priv->pps_mutex);
1858
bf13e81b 1859 control = I915_READ(_pp_ctrl_reg(intel_dp));
b0a08bec
VK		 1860 if (!IS_BROXTON(dev)) {
1861 control &= ~PANEL_UNLOCK_MASK;
1862 control |= PANEL_UNLOCK_REGS;
1863 }
832dd3c1 1864 return control;
bd943159
KP		 1865}
1866
951468f3
VS		 1867/*
1868 * Must be paired with edp_panel_vdd_off().
1869 * Must hold pps_mutex around the whole on/off sequence.
1870 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1871 */
1e0560e0 1872static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1873{
30add22d 1874 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1875 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1876 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1877 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1878 enum intel_display_power_domain power_domain;
5d613501 1879 u32 pp;
f0f59a00 1880 i915_reg_t pp_stat_reg, pp_ctrl_reg;
adddaaf4 1881 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1882
e39b999a
VS		 1883 lockdep_assert_held(&dev_priv->pps_mutex);
1884
97af61f5 1885 if (!is_edp(intel_dp))
adddaaf4 1886 return false;
bd943159 1887
2c623c11 1888 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1889 intel_dp->want_panel_vdd = true;
99ea7127 1890
4be73780 1891 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1892 return need_to_disable;
b0665d57 1893
25f78f58 1894 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 1895 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1896
3936fcf4
VS		 1897 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1898 port_name(intel_dig_port->port));
bd943159 1899
4be73780
DV		 1900 if (!edp_have_panel_power(intel_dp))
1901 wait_panel_power_cycle(intel_dp);
99ea7127 1902
453c5420 1903 pp = ironlake_get_pp_control(intel_dp);
5d613501 1904 pp |= EDP_FORCE_VDD;
ebf33b18 1905
bf13e81b
JN		 1906 pp_stat_reg = _pp_stat_reg(intel_dp);
1907 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1908
1909 I915_WRITE(pp_ctrl_reg, pp);
1910 POSTING_READ(pp_ctrl_reg);
1911 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1912 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1913 /*
1914 * If the panel wasn't on, delay before accessing aux channel
1915 */
4be73780 1916 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1917 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1918 port_name(intel_dig_port->port));
f01eca2e 1919 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1920 }
adddaaf4
JN		 1921
1922 return need_to_disable;
1923}
1924
951468f3
VS		 1925/*
1926 * Must be paired with intel_edp_panel_vdd_off() or
1927 * intel_edp_panel_off().
1928 * Nested calls to these functions are not allowed since
1929 * we drop the lock. Caller must use some higher level
1930 * locking to prevent nested calls from other threads.
1931 */
b80d6c78 1932void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1933{
c695b6b6 1934 bool vdd;
adddaaf4 1935
c695b6b6
VS		 1936 if (!is_edp(intel_dp))
1937 return;
1938
773538e8 1939 pps_lock(intel_dp);
c695b6b6 1940 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1941 pps_unlock(intel_dp);
c695b6b6 1942
e2c719b7 1943 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1944 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1945}
1946
4be73780 1947static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1948{
30add22d 1949 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1950 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1951 struct intel_digital_port *intel_dig_port =
1952 dp_to_dig_port(intel_dp);
1953 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1954 enum intel_display_power_domain power_domain;
5d613501 1955 u32 pp;
f0f59a00 1956 i915_reg_t pp_stat_reg, pp_ctrl_reg;
5d613501 1957
e39b999a 1958 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1959
15e899a0 1960 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1961
15e899a0 1962 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1963 return;
b0665d57 1964
3936fcf4
VS		 1965 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1966 port_name(intel_dig_port->port));
bd943159 1967
be2c9196
VS		 1968 pp = ironlake_get_pp_control(intel_dp);
1969 pp &= ~EDP_FORCE_VDD;
453c5420 1970
be2c9196
VS		 1971 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1972 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1973
be2c9196
VS		 1974 I915_WRITE(pp_ctrl_reg, pp);
1975 POSTING_READ(pp_ctrl_reg);
90791a5c 1976
be2c9196
VS		 1977 /* Make sure sequencer is idle before allowing subsequent activity */
1978 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1979 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1980
be2c9196 1981 if ((pp & POWER_TARGET_ON) == 0)
d28d4731 1982 intel_dp->panel_power_off_time = ktime_get_boottime();
e9cb81a2 1983
25f78f58 1984 power_domain = intel_display_port_aux_power_domain(intel_encoder);
be2c9196 1985 intel_display_power_put(dev_priv, power_domain);
bd943159 1986}
5d613501 1987
4be73780 1988static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1989{
1990 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1991 struct intel_dp, panel_vdd_work);
bd943159 1992
773538e8 1993 pps_lock(intel_dp);
15e899a0
VS		 1994 if (!intel_dp->want_panel_vdd)
1995 edp_panel_vdd_off_sync(intel_dp);
773538e8 1996 pps_unlock(intel_dp);
bd943159
KP		 1997}
1998
aba86890
ID		 1999static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2000{
2001 unsigned long delay;
2002
2003 /*
2004 * Queue the timer to fire a long time from now (relative to the power
2005 * down delay) to keep the panel power up across a sequence of
2006 * operations.
2007 */
2008 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2009 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2010}
2011
951468f3
VS		 2012/*
2013 * Must be paired with edp_panel_vdd_on().
2014 * Must hold pps_mutex around the whole on/off sequence.
2015 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2016 */
4be73780 2017static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 2018{
e39b999a
VS		 2019 struct drm_i915_private *dev_priv =
2020 intel_dp_to_dev(intel_dp)->dev_private;
2021
2022 lockdep_assert_held(&dev_priv->pps_mutex);
2023
97af61f5
KP		 2024 if (!is_edp(intel_dp))
2025 return;
5d613501 2026
e2c719b7 2027 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 2028 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 2029
bd943159
KP		 2030 intel_dp->want_panel_vdd = false;
2031
aba86890 2032 if (sync)
4be73780 2033 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 2034 else
2035 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 2036}
2037
9f0fb5be 2038static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 2039{
30add22d 2040 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 2041 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 2042 u32 pp;
f0f59a00 2043 i915_reg_t pp_ctrl_reg;
9934c132 2044
9f0fb5be
VS		 2045 lockdep_assert_held(&dev_priv->pps_mutex);
2046
97af61f5 2047 if (!is_edp(intel_dp))
bd943159 2048 return;
99ea7127 2049
3936fcf4
VS		 2050 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2051 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 2052
e7a89ace
VS		 2053 if (WARN(edp_have_panel_power(intel_dp),
2054 "eDP port %c panel power already on\n",
2055 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 2056 return;
9934c132 2057
4be73780 2058 wait_panel_power_cycle(intel_dp);
37c6c9b0 2059
bf13e81b 2060 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2061 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 2062 if (IS_GEN5(dev)) {
2063 /* ILK workaround: disable reset around power sequence */
2064 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 2065 I915_WRITE(pp_ctrl_reg, pp);
2066 POSTING_READ(pp_ctrl_reg);
05ce1a49 2067 }
37c6c9b0 2068
1c0ae80a 2069 pp |= POWER_TARGET_ON;
99ea7127
KP		 2070 if (!IS_GEN5(dev))
2071 pp |= PANEL_POWER_RESET;
2072
453c5420
JB		 2073 I915_WRITE(pp_ctrl_reg, pp);
2074 POSTING_READ(pp_ctrl_reg);
9934c132 2075
4be73780 2076 wait_panel_on(intel_dp);
dce56b3c 2077 intel_dp->last_power_on = jiffies;
9934c132 2078
05ce1a49
KP		 2079 if (IS_GEN5(dev)) {
2080 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 2081 I915_WRITE(pp_ctrl_reg, pp);
2082 POSTING_READ(pp_ctrl_reg);
05ce1a49 2083 }
9f0fb5be 2084}
e39b999a 2085
9f0fb5be
VS		 2086void intel_edp_panel_on(struct intel_dp *intel_dp)
2087{
2088 if (!is_edp(intel_dp))
2089 return;
2090
2091 pps_lock(intel_dp);
2092 edp_panel_on(intel_dp);
773538e8 2093 pps_unlock(intel_dp);
9934c132
JB		 2094}
2095
9f0fb5be
VS		 2096
2097static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 2098{
4e6e1a54
ID		 2099 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2100 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 2101 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 2102 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 2103 enum intel_display_power_domain power_domain;
99ea7127 2104 u32 pp;
f0f59a00 2105 i915_reg_t pp_ctrl_reg;
9934c132 2106
9f0fb5be
VS		 2107 lockdep_assert_held(&dev_priv->pps_mutex);
2108
97af61f5
KP		 2109 if (!is_edp(intel_dp))
2110 return;
37c6c9b0 2111
3936fcf4
VS		 2112 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2113 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 2114
3936fcf4
VS		 2115 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2116 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 2117
453c5420 2118 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 2119 /* We need to switch off panel power _and_ force vdd, for otherwise some
2120 * panels get very unhappy and cease to work. */
b3064154
PJ		 2121 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2122 EDP_BLC_ENABLE);
453c5420 2123
bf13e81b 2124 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2125
849e39f5
PZ		 2126 intel_dp->want_panel_vdd = false;
2127
453c5420
JB		 2128 I915_WRITE(pp_ctrl_reg, pp);
2129 POSTING_READ(pp_ctrl_reg);
9934c132 2130
d28d4731 2131 intel_dp->panel_power_off_time = ktime_get_boottime();
4be73780 2132 wait_panel_off(intel_dp);
849e39f5
PZ		 2133
2134 /* We got a reference when we enabled the VDD. */
25f78f58 2135 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 2136 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 2137}
e39b999a 2138
9f0fb5be
VS		 2139void intel_edp_panel_off(struct intel_dp *intel_dp)
2140{
2141 if (!is_edp(intel_dp))
2142 return;
e39b999a 2143
9f0fb5be
VS		 2144 pps_lock(intel_dp);
2145 edp_panel_off(intel_dp);
773538e8 2146 pps_unlock(intel_dp);
9934c132
JB		 2147}
2148
1250d107
JN		 2149/* Enable backlight in the panel power control. */
2150static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2151{
da63a9f2
PZ		 2152 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2153 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 2154 struct drm_i915_private *dev_priv = dev->dev_private;
2155 u32 pp;
f0f59a00 2156 i915_reg_t pp_ctrl_reg;
32f9d658 2157
01cb9ea6
JB		 2158 /*
2159 * If we enable the backlight right away following a panel power
2160 * on, we may see slight flicker as the panel syncs with the eDP
2161 * link. So delay a bit to make sure the image is solid before
2162 * allowing it to appear.
2163 */
4be73780 2164 wait_backlight_on(intel_dp);
e39b999a 2165
773538e8 2166 pps_lock(intel_dp);
e39b999a 2167
453c5420 2168 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2169 pp |= EDP_BLC_ENABLE;
453c5420 2170
bf13e81b 2171 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2172
2173 I915_WRITE(pp_ctrl_reg, pp);
2174 POSTING_READ(pp_ctrl_reg);
e39b999a 2175
773538e8 2176 pps_unlock(intel_dp);
32f9d658
ZW		 2177}
2178
1250d107
JN		 2179/* Enable backlight PWM and backlight PP control. */
2180void intel_edp_backlight_on(struct intel_dp *intel_dp)
2181{
2182 if (!is_edp(intel_dp))
2183 return;
2184
2185 DRM_DEBUG_KMS("\n");
2186
2187 intel_panel_enable_backlight(intel_dp->attached_connector);
2188 _intel_edp_backlight_on(intel_dp);
2189}
2190
2191/* Disable backlight in the panel power control. */
2192static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2193{
30add22d 2194 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 2195 struct drm_i915_private *dev_priv = dev->dev_private;
2196 u32 pp;
f0f59a00 2197 i915_reg_t pp_ctrl_reg;
32f9d658 2198
f01eca2e
KP		 2199 if (!is_edp(intel_dp))
2200 return;
2201
773538e8 2202 pps_lock(intel_dp);
e39b999a 2203
453c5420 2204 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2205 pp &= ~EDP_BLC_ENABLE;
453c5420 2206
bf13e81b 2207 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2208
2209 I915_WRITE(pp_ctrl_reg, pp);
2210 POSTING_READ(pp_ctrl_reg);
f7d2323c 2211
773538e8 2212 pps_unlock(intel_dp);
e39b999a
VS		 2213
2214 intel_dp->last_backlight_off = jiffies;
f7d2323c 2215 edp_wait_backlight_off(intel_dp);
1250d107 2216}
f7d2323c 2217
1250d107
JN		 2218/* Disable backlight PP control and backlight PWM. */
2219void intel_edp_backlight_off(struct intel_dp *intel_dp)
2220{
2221 if (!is_edp(intel_dp))
2222 return;
2223
2224 DRM_DEBUG_KMS("\n");
f7d2323c 2225
1250d107 2226 _intel_edp_backlight_off(intel_dp);
f7d2323c 2227 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2228}
a4fc5ed6 2229
73580fb7
JN		 2230/*
2231 * Hook for controlling the panel power control backlight through the bl_power
2232 * sysfs attribute. Take care to handle multiple calls.
2233 */
2234static void intel_edp_backlight_power(struct intel_connector *connector,
2235 bool enable)
2236{
2237 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2238 bool is_enabled;
2239
773538e8 2240 pps_lock(intel_dp);
e39b999a 2241 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2242 pps_unlock(intel_dp);
73580fb7
JN		 2243
2244 if (is_enabled == enable)
2245 return;
2246
23ba9373
JN		 2247 DRM_DEBUG_KMS("panel power control backlight %s\n",
2248 enable ? "enable" : "disable");
73580fb7
JN		 2249
2250 if (enable)
2251 _intel_edp_backlight_on(intel_dp);
2252 else
2253 _intel_edp_backlight_off(intel_dp);
2254}
2255
64e1077a
VS		 2256static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2257{
2258 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2259 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2260 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2261
2262 I915_STATE_WARN(cur_state != state,
2263 "DP port %c state assertion failure (expected %s, current %s)\n",
2264 port_name(dig_port->port),
87ad3212 2265 onoff(state), onoff(cur_state));
64e1077a
VS		 2266}
2267#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2268
2269static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2270{
2271 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2272
2273 I915_STATE_WARN(cur_state != state,
2274 "eDP PLL state assertion failure (expected %s, current %s)\n",
87ad3212 2275 onoff(state), onoff(cur_state));
64e1077a
VS		 2276}
2277#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2278#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2279
2bd2ad64 2280static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2281{
da63a9f2 2282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2283 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2284 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2285
64e1077a
VS		 2286 assert_pipe_disabled(dev_priv, crtc->pipe);
2287 assert_dp_port_disabled(intel_dp);
2288 assert_edp_pll_disabled(dev_priv);
2bd2ad64 2289
abfce949
VS		 2290 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2291 crtc->config->port_clock);
2292
2293 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2294
2295 if (crtc->config->port_clock == 162000)
2296 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2297 else
2298 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2299
2300 I915_WRITE(DP_A, intel_dp->DP);
2301 POSTING_READ(DP_A);
2302 udelay(500);
2303
6b23f3e8
VS		 2304 /*
2305 * [DevILK] Work around required when enabling DP PLL
2306 * while a pipe is enabled going to FDI:
2307 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2308 * 2. Program DP PLL enable
2309 */
2310 if (IS_GEN5(dev_priv))
2311 intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe);
2312
0767935e 2313 intel_dp->DP |= DP_PLL_ENABLE;
6fec7662 2314
0767935e 2315 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2316 POSTING_READ(DP_A);
2317 udelay(200);
d240f20f
JB		 2318}
2319
2bd2ad64 2320static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2321{
da63a9f2 2322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2323 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2324 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2325
64e1077a
VS		 2326 assert_pipe_disabled(dev_priv, crtc->pipe);
2327 assert_dp_port_disabled(intel_dp);
2328 assert_edp_pll_enabled(dev_priv);
2bd2ad64 2329
abfce949
VS		 2330 DRM_DEBUG_KMS("disabling eDP PLL\n");
2331
6fec7662 2332 intel_dp->DP &= ~DP_PLL_ENABLE;
0767935e 2333
6fec7662 2334 I915_WRITE(DP_A, intel_dp->DP);
1af5fa1b 2335 POSTING_READ(DP_A);
d240f20f
JB		 2336 udelay(200);
2337}
2338
c7ad3810 2339/* If the sink supports it, try to set the power state appropriately */
c19b0669 2340void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2341{
2342 int ret, i;
2343
2344 /* Should have a valid DPCD by this point */
2345 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2346 return;
2347
2348 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2349 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2350 DP_SET_POWER_D3);
c7ad3810
JB		 2351 } else {
2352 /*
2353 * When turning on, we need to retry for 1ms to give the sink
2354 * time to wake up.
2355 */
2356 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2357 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2358 DP_SET_POWER_D0);
c7ad3810
JB		 2359 if (ret == 1)
2360 break;
2361 msleep(1);
2362 }
2363 }
f9cac721
JN		 2364
2365 if (ret != 1)
2366 DRM_DEBUG_KMS("failed to %s sink power state\n",
2367 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2368}
2369
19d8fe15
DV		 2370static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2371 enum pipe *pipe)
d240f20f 2372{
19d8fe15 2373 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2374 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2375 struct drm_device *dev = encoder->base.dev;
2376 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2377 enum intel_display_power_domain power_domain;
2378 u32 tmp;
6fa9a5ec 2379 bool ret;
6d129bea
ID		 2380
2381 power_domain = intel_display_port_power_domain(encoder);
6fa9a5ec 2382 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 2383 return false;
2384
6fa9a5ec
ID		 2385 ret = false;
2386
6d129bea 2387 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2388
2389 if (!(tmp & DP_PORT_EN))
6fa9a5ec 2390 goto out;
19d8fe15 2391
39e5fa88 2392 if (IS_GEN7(dev) && port == PORT_A) {
19d8fe15 2393 *pipe = PORT_TO_PIPE_CPT(tmp);
39e5fa88 2394 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
adc289d7 2395 enum pipe p;
19d8fe15 2396
adc289d7
VS		 2397 for_each_pipe(dev_priv, p) {
2398 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2399 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2400 *pipe = p;
6fa9a5ec
ID		 2401 ret = true;
2402
2403 goto out;
19d8fe15
DV		 2404 }
2405 }
19d8fe15 2406
4a0833ec 2407 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
f0f59a00 2408 i915_mmio_reg_offset(intel_dp->output_reg));
39e5fa88
VS		 2409 } else if (IS_CHERRYVIEW(dev)) {
2410 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2411 } else {
2412 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2413 }
d240f20f 2414
6fa9a5ec
ID		 2415 ret = true;
2416
2417out:
2418 intel_display_power_put(dev_priv, power_domain);
2419
2420 return ret;
19d8fe15 2421}
d240f20f 2422
045ac3b5 2423static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2424 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2425{
2426 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2427 u32 tmp, flags = 0;
63000ef6
XZ		 2428 struct drm_device *dev = encoder->base.dev;
2429 struct drm_i915_private *dev_priv = dev->dev_private;
2430 enum port port = dp_to_dig_port(intel_dp)->port;
2431 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 2432
9ed109a7 2433 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2434
2435 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2436
39e5fa88 2437 if (HAS_PCH_CPT(dev) && port != PORT_A) {
b81e34c2
VS		 2438 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2439
2440 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2441 flags |= DRM_MODE_FLAG_PHSYNC;
2442 else
2443 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2444
b81e34c2 2445 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2446 flags |= DRM_MODE_FLAG_PVSYNC;
2447 else
2448 flags |= DRM_MODE_FLAG_NVSYNC;
2449 } else {
39e5fa88 2450 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2451 flags |= DRM_MODE_FLAG_PHSYNC;
2452 else
2453 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2454
39e5fa88 2455 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2456 flags |= DRM_MODE_FLAG_PVSYNC;
2457 else
2458 flags |= DRM_MODE_FLAG_NVSYNC;
2459 }
045ac3b5 2460
2d112de7 2461 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2462
8c875fca 2463 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 2464 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
8c875fca
VS		 2465 pipe_config->limited_color_range = true;
2466
eb14cb74
VS		 2467 pipe_config->has_dp_encoder = true;
2468
90a6b7b0
VS		 2469 pipe_config->lane_count =
2470 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2471
eb14cb74
VS		 2472 intel_dp_get_m_n(crtc, pipe_config);
2473
18442d08 2474 if (port == PORT_A) {
b377e0df 2475 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
f1f644dc
JB		 2476 pipe_config->port_clock = 162000;
2477 else
2478 pipe_config->port_clock = 270000;
2479 }
18442d08 2480
e3b247da
VS		 2481 pipe_config->base.adjusted_mode.crtc_clock =
2482 intel_dotclock_calculate(pipe_config->port_clock,
2483 &pipe_config->dp_m_n);
7f16e5c1 2484
6aa23e65
JN		 2485 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2486 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
c6cd2ee2
JN		 2487 /*
2488 * This is a big fat ugly hack.
2489 *
2490 * Some machines in UEFI boot mode provide us a VBT that has 18
2491 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2492 * unknown we fail to light up. Yet the same BIOS boots up with
2493 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2494 * max, not what it tells us to use.
2495 *
2496 * Note: This will still be broken if the eDP panel is not lit
2497 * up by the BIOS, and thus we can't get the mode at module
2498 * load.
2499 */
2500 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2501 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2502 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
c6cd2ee2 2503 }
045ac3b5
JB		 2504}
2505
e8cb4558 2506static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2507{
e8cb4558 2508 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2509 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2510 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2511
6e3c9717 2512 if (crtc->config->has_audio)
495a5bb8 2513 intel_audio_codec_disable(encoder);
6cb49835 2514
b32c6f48
RV		 2515 if (HAS_PSR(dev) && !HAS_DDI(dev))
2516 intel_psr_disable(intel_dp);
2517
6cb49835
DV		 2518 /* Make sure the panel is off before trying to change the mode. But also
2519 * ensure that we have vdd while we switch off the panel. */
24f3e092 2520 intel_edp_panel_vdd_on(intel_dp);
4be73780 2521 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2522 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2523 intel_edp_panel_off(intel_dp);
3739850b 2524
08aff3fe
VS		 2525 /* disable the port before the pipe on g4x */
2526 if (INTEL_INFO(dev)->gen < 5)
3739850b 2527 intel_dp_link_down(intel_dp);
d240f20f
JB		 2528}
2529
08aff3fe 2530static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2531{
2bd2ad64 2532 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2533 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2534
49277c31 2535 intel_dp_link_down(intel_dp);
abfce949
VS		 2536
2537 /* Only ilk+ has port A */
08aff3fe
VS		 2538 if (port == PORT_A)
2539 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2540}
2541
2542static void vlv_post_disable_dp(struct intel_encoder *encoder)
2543{
2544 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2545
2546 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2547}
2548
a8f327fb
VS		 2549static void chv_post_disable_dp(struct intel_encoder *encoder)
2550{
2551 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2552 struct drm_device *dev = encoder->base.dev;
2553 struct drm_i915_private *dev_priv = dev->dev_private;
97fd4d5c 2554
a8f327fb
VS		 2555 intel_dp_link_down(intel_dp);
2556
2557 mutex_lock(&dev_priv->sb_lock);
2558
2559 /* Assert data lane reset */
2560 chv_data_lane_soft_reset(encoder, true);
580d3811 2561
a580516d 2562 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2563}
2564
7b13b58a
VS		 2565static void
2566_intel_dp_set_link_train(struct intel_dp *intel_dp,
2567 uint32_t *DP,
2568 uint8_t dp_train_pat)
2569{
2570 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2571 struct drm_device *dev = intel_dig_port->base.base.dev;
2572 struct drm_i915_private *dev_priv = dev->dev_private;
2573 enum port port = intel_dig_port->port;
2574
2575 if (HAS_DDI(dev)) {
2576 uint32_t temp = I915_READ(DP_TP_CTL(port));
2577
2578 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2579 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2580 else
2581 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2582
2583 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2584 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2585 case DP_TRAINING_PATTERN_DISABLE:
2586 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2587
2588 break;
2589 case DP_TRAINING_PATTERN_1:
2590 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2591 break;
2592 case DP_TRAINING_PATTERN_2:
2593 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2594 break;
2595 case DP_TRAINING_PATTERN_3:
2596 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2597 break;
2598 }
2599 I915_WRITE(DP_TP_CTL(port), temp);
2600
39e5fa88
VS		 2601 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2602 (HAS_PCH_CPT(dev) && port != PORT_A)) {
7b13b58a
VS		 2603 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2604
2605 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2606 case DP_TRAINING_PATTERN_DISABLE:
2607 *DP |= DP_LINK_TRAIN_OFF_CPT;
2608 break;
2609 case DP_TRAINING_PATTERN_1:
2610 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2611 break;
2612 case DP_TRAINING_PATTERN_2:
2613 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2614 break;
2615 case DP_TRAINING_PATTERN_3:
2616 DRM_ERROR("DP training pattern 3 not supported\n");
2617 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2618 break;
2619 }
2620
2621 } else {
2622 if (IS_CHERRYVIEW(dev))
2623 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2624 else
2625 *DP &= ~DP_LINK_TRAIN_MASK;
2626
2627 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2628 case DP_TRAINING_PATTERN_DISABLE:
2629 *DP |= DP_LINK_TRAIN_OFF;
2630 break;
2631 case DP_TRAINING_PATTERN_1:
2632 *DP |= DP_LINK_TRAIN_PAT_1;
2633 break;
2634 case DP_TRAINING_PATTERN_2:
2635 *DP |= DP_LINK_TRAIN_PAT_2;
2636 break;
2637 case DP_TRAINING_PATTERN_3:
2638 if (IS_CHERRYVIEW(dev)) {
2639 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2640 } else {
2641 DRM_ERROR("DP training pattern 3 not supported\n");
2642 *DP |= DP_LINK_TRAIN_PAT_2;
2643 }
2644 break;
2645 }
2646 }
2647}
2648
2649static void intel_dp_enable_port(struct intel_dp *intel_dp)
2650{
2651 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2652 struct drm_i915_private *dev_priv = dev->dev_private;
6fec7662
VS		 2653 struct intel_crtc *crtc =
2654 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
7b13b58a 2655
7b13b58a
VS		 2656 /* enable with pattern 1 (as per spec) */
2657 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2658 DP_TRAINING_PATTERN_1);
2659
2660 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2661 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2662
2663 /*
2664 * Magic for VLV/CHV. We _must_ first set up the register
2665 * without actually enabling the port, and then do another
2666 * write to enable the port. Otherwise link training will
2667 * fail when the power sequencer is freshly used for this port.
2668 */
2669 intel_dp->DP |= DP_PORT_EN;
6fec7662
VS		 2670 if (crtc->config->has_audio)
2671 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
7b713f50
VS		 2672
2673 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2674 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2675}
2676
e8cb4558 2677static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2678{
e8cb4558
DV		 2679 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2680 struct drm_device *dev = encoder->base.dev;
2681 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2682 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2683 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
d6fbdd15 2684 enum pipe pipe = crtc->pipe;
5d613501 2685
0c33d8d7
DV		 2686 if (WARN_ON(dp_reg & DP_PORT_EN))
2687 return;
5d613501 2688
093e3f13
VS		 2689 pps_lock(intel_dp);
2690
666a4537 2691 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
093e3f13
VS		 2692 vlv_init_panel_power_sequencer(intel_dp);
2693
7b13b58a 2694 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2695
2696 edp_panel_vdd_on(intel_dp);
2697 edp_panel_on(intel_dp);
2698 edp_panel_vdd_off(intel_dp, true);
2699
2700 pps_unlock(intel_dp);
2701
666a4537 2702 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e0fce78f
VS		 2703 unsigned int lane_mask = 0x0;
2704
2705 if (IS_CHERRYVIEW(dev))
2706 lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2707
9b6de0a1
VS		 2708 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2709 lane_mask);
e0fce78f 2710 }
61234fa5 2711
f01eca2e 2712 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2713 intel_dp_start_link_train(intel_dp);
3ab9c637 2714 intel_dp_stop_link_train(intel_dp);
c1dec79a 2715
6e3c9717 2716 if (crtc->config->has_audio) {
c1dec79a 2717 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
d6fbdd15 2718 pipe_name(pipe));
c1dec79a
JN		 2719 intel_audio_codec_enable(encoder);
2720 }
ab1f90f9 2721}
89b667f8 2722
ecff4f3b
JN		 2723static void g4x_enable_dp(struct intel_encoder *encoder)
2724{
828f5c6e
JN		 2725 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2726
ecff4f3b 2727 intel_enable_dp(encoder);
4be73780 2728 intel_edp_backlight_on(intel_dp);
ab1f90f9 2729}
89b667f8 2730
ab1f90f9
JN		 2731static void vlv_enable_dp(struct intel_encoder *encoder)
2732{
828f5c6e
JN		 2733 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2734
4be73780 2735 intel_edp_backlight_on(intel_dp);
b32c6f48 2736 intel_psr_enable(intel_dp);
d240f20f
JB		 2737}
2738
ecff4f3b 2739static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2740{
2741 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6fbdd15 2742 enum port port = dp_to_dig_port(intel_dp)->port;
ab1f90f9 2743
8ac33ed3
DV		 2744 intel_dp_prepare(encoder);
2745
d41f1efb 2746 /* Only ilk+ has port A */
abfce949 2747 if (port == PORT_A)
ab1f90f9
JN		 2748 ironlake_edp_pll_on(intel_dp);
2749}
2750
83b84597
VS		 2751static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2752{
2753 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2754 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2755 enum pipe pipe = intel_dp->pps_pipe;
f0f59a00 2756 i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
83b84597
VS		 2757
2758 edp_panel_vdd_off_sync(intel_dp);
2759
2760 /*
2761 * VLV seems to get confused when multiple power seqeuencers
2762 * have the same port selected (even if only one has power/vdd
2763 * enabled). The failure manifests as vlv_wait_port_ready() failing
2764 * CHV on the other hand doesn't seem to mind having the same port
2765 * selected in multiple power seqeuencers, but let's clear the
2766 * port select always when logically disconnecting a power sequencer
2767 * from a port.
2768 */
2769 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2770 pipe_name(pipe), port_name(intel_dig_port->port));
2771 I915_WRITE(pp_on_reg, 0);
2772 POSTING_READ(pp_on_reg);
2773
2774 intel_dp->pps_pipe = INVALID_PIPE;
2775}
2776
a4a5d2f8
VS		 2777static void vlv_steal_power_sequencer(struct drm_device *dev,
2778 enum pipe pipe)
2779{
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_encoder *encoder;
2782
2783 lockdep_assert_held(&dev_priv->pps_mutex);
2784
ac3c12e4
VS		 2785 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2786 return;
2787
19c8054c 2788 for_each_intel_encoder(dev, encoder) {
a4a5d2f8 2789 struct intel_dp *intel_dp;
773538e8 2790 enum port port;
a4a5d2f8
VS		 2791
2792 if (encoder->type != INTEL_OUTPUT_EDP)
2793 continue;
2794
2795 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2796 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2797
2798 if (intel_dp->pps_pipe != pipe)
2799 continue;
2800
2801 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2802 pipe_name(pipe), port_name(port));
a4a5d2f8 2803
e02f9a06 2804 WARN(encoder->base.crtc,
034e43c6
VS		 2805 "stealing pipe %c power sequencer from active eDP port %c\n",
2806 pipe_name(pipe), port_name(port));
a4a5d2f8 2807
a4a5d2f8 2808 /* make sure vdd is off before we steal it */
83b84597 2809 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2810 }
2811}
2812
2813static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2814{
2815 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2816 struct intel_encoder *encoder = &intel_dig_port->base;
2817 struct drm_device *dev = encoder->base.dev;
2818 struct drm_i915_private *dev_priv = dev->dev_private;
2819 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2820
2821 lockdep_assert_held(&dev_priv->pps_mutex);
2822
093e3f13
VS		 2823 if (!is_edp(intel_dp))
2824 return;
2825
a4a5d2f8
VS		 2826 if (intel_dp->pps_pipe == crtc->pipe)
2827 return;
2828
2829 /*
2830 * If another power sequencer was being used on this
2831 * port previously make sure to turn off vdd there while
2832 * we still have control of it.
2833 */
2834 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2835 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2836
2837 /*
2838 * We may be stealing the power
2839 * sequencer from another port.
2840 */
2841 vlv_steal_power_sequencer(dev, crtc->pipe);
2842
2843 /* now it's all ours */
2844 intel_dp->pps_pipe = crtc->pipe;
2845
2846 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2847 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2848
2849 /* init power sequencer on this pipe and port */
36b5f425
VS		 2850 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2851 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2852}
2853
ab1f90f9 2854static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2855{
5f68c275 2856 vlv_phy_pre_encoder_enable(encoder);
ab1f90f9
JN		 2857
2858 intel_enable_dp(encoder);
89b667f8
JB		 2859}
2860
ecff4f3b 2861static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8 2862{
8ac33ed3
DV		 2863 intel_dp_prepare(encoder);
2864
6da2e616 2865 vlv_phy_pre_pll_enable(encoder);
a4fc5ed6
KP		 2866}
2867
e4a1d846
CML		 2868static void chv_pre_enable_dp(struct intel_encoder *encoder)
2869{
e7d2a717 2870 chv_phy_pre_encoder_enable(encoder);
e4a1d846 2871
e4a1d846 2872 intel_enable_dp(encoder);
b0b33846
VS		 2873
2874 /* Second common lane will stay alive on its own now */
e7d2a717 2875 chv_phy_release_cl2_override(encoder);
e4a1d846
CML		 2876}
2877
9197c88b
VS		 2878static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2879{
625695f8
VS		 2880 intel_dp_prepare(encoder);
2881
419b1b7a 2882 chv_phy_pre_pll_enable(encoder);
9197c88b
VS		 2883}
2884
d6db995f
VS		 2885static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
2886{
204970b5 2887 chv_phy_post_pll_disable(encoder);
d6db995f
VS		 2888}
2889
a4fc5ed6
KP		 2890/*
2891 * Fetch AUX CH registers 0x202 - 0x207 which contain
2892 * link status information
2893 */
94223d04 2894bool
93f62dad 2895intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2896{
9f085ebb
L		 2897 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2898 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2899}
2900
1100244e 2901/* These are source-specific values. */
94223d04 2902uint8_t
1a2eb460 2903intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2904{
30add22d 2905 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 2906 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 2907 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2908
9314726b
VK		 2909 if (IS_BROXTON(dev))
2910 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2911 else if (INTEL_INFO(dev)->gen >= 9) {
06411f08 2912 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
7ad14a29 2913 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2914 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
666a4537 2915 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
bd60018a 2916 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2917 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2918 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2919 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2920 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2921 else
bd60018a 2922 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2923}
2924
94223d04 2925uint8_t
1a2eb460
KP		 2926intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2927{
30add22d 2928 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2929 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2930
5a9d1f1a
DL		 2931 if (INTEL_INFO(dev)->gen >= 9) {
2932 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2934 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2936 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2938 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2940 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 2941 default:
2942 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2943 }
2944 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2945 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2946 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2947 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2949 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2950 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2951 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2953 default:
bd60018a 2954 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2955 }
666a4537 2956 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e2fa6fba 2957 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2958 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2959 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2960 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2961 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2962 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2963 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2964 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2965 default:
bd60018a 2966 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2967 }
bc7d38a4 2968 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2969 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2970 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2971 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2972 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2973 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2974 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2975 default:
bd60018a 2976 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2977 }
2978 } else {
2979 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2980 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2981 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2982 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2983 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2984 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2985 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2986 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2987 default:
bd60018a 2988 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2989 }
a4fc5ed6
KP		 2990 }
2991}
2992
5829975c 2993static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba 2994{
53d98725 2995 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
e2fa6fba
P		 2996 unsigned long demph_reg_value, preemph_reg_value,
2997 uniqtranscale_reg_value;
2998 uint8_t train_set = intel_dp->train_set[0];
e2fa6fba
P		 2999
3000 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3001 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3002 preemph_reg_value = 0x0004000;
3003 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3004 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3005 demph_reg_value = 0x2B405555;
3006 uniqtranscale_reg_value = 0x552AB83A;
3007 break;
bd60018a 3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3009 demph_reg_value = 0x2B404040;
3010 uniqtranscale_reg_value = 0x5548B83A;
3011 break;
bd60018a 3012 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3013 demph_reg_value = 0x2B245555;
3014 uniqtranscale_reg_value = 0x5560B83A;
3015 break;
bd60018a 3016 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3017 demph_reg_value = 0x2B405555;
3018 uniqtranscale_reg_value = 0x5598DA3A;
3019 break;
3020 default:
3021 return 0;
3022 }
3023 break;
bd60018a 3024 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3025 preemph_reg_value = 0x0002000;
3026 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3028 demph_reg_value = 0x2B404040;
3029 uniqtranscale_reg_value = 0x5552B83A;
3030 break;
bd60018a 3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3032 demph_reg_value = 0x2B404848;
3033 uniqtranscale_reg_value = 0x5580B83A;
3034 break;
bd60018a 3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3036 demph_reg_value = 0x2B404040;
3037 uniqtranscale_reg_value = 0x55ADDA3A;
3038 break;
3039 default:
3040 return 0;
3041 }
3042 break;
bd60018a 3043 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3044 preemph_reg_value = 0x0000000;
3045 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3047 demph_reg_value = 0x2B305555;
3048 uniqtranscale_reg_value = 0x5570B83A;
3049 break;
bd60018a 3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3051 demph_reg_value = 0x2B2B4040;
3052 uniqtranscale_reg_value = 0x55ADDA3A;
3053 break;
3054 default:
3055 return 0;
3056 }
3057 break;
bd60018a 3058 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3059 preemph_reg_value = 0x0006000;
3060 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3061 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3062 demph_reg_value = 0x1B405555;
3063 uniqtranscale_reg_value = 0x55ADDA3A;
3064 break;
3065 default:
3066 return 0;
3067 }
3068 break;
3069 default:
3070 return 0;
3071 }
3072
53d98725
ACO		 3073 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3074 uniqtranscale_reg_value, 0);
e2fa6fba
P		 3075
3076 return 0;
3077}
3078
5829975c 3079static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846 3080{
b7fa22d8
ACO		 3081 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3082 u32 deemph_reg_value, margin_reg_value;
3083 bool uniq_trans_scale = false;
e4a1d846 3084 uint8_t train_set = intel_dp->train_set[0];
e4a1d846
CML		 3085
3086 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3087 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3088 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3090 deemph_reg_value = 128;
3091 margin_reg_value = 52;
3092 break;
bd60018a 3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3094 deemph_reg_value = 128;
3095 margin_reg_value = 77;
3096 break;
bd60018a 3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3098 deemph_reg_value = 128;
3099 margin_reg_value = 102;
3100 break;
bd60018a 3101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3102 deemph_reg_value = 128;
3103 margin_reg_value = 154;
b7fa22d8 3104 uniq_trans_scale = true;
e4a1d846
CML		 3105 break;
3106 default:
3107 return 0;
3108 }
3109 break;
bd60018a 3110 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3111 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3112 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3113 deemph_reg_value = 85;
3114 margin_reg_value = 78;
3115 break;
bd60018a 3116 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3117 deemph_reg_value = 85;
3118 margin_reg_value = 116;
3119 break;
bd60018a 3120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3121 deemph_reg_value = 85;
3122 margin_reg_value = 154;
3123 break;
3124 default:
3125 return 0;
3126 }
3127 break;
bd60018a 3128 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3129 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3130 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3131 deemph_reg_value = 64;
3132 margin_reg_value = 104;
3133 break;
bd60018a 3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3135 deemph_reg_value = 64;
3136 margin_reg_value = 154;
3137 break;
3138 default:
3139 return 0;
3140 }
3141 break;
bd60018a 3142 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3143 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3144 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3145 deemph_reg_value = 43;
3146 margin_reg_value = 154;
3147 break;
3148 default:
3149 return 0;
3150 }
3151 break;
3152 default:
3153 return 0;
3154 }
3155
b7fa22d8
ACO		 3156 chv_set_phy_signal_level(encoder, deemph_reg_value,
3157 margin_reg_value, uniq_trans_scale);
e4a1d846
CML		 3158
3159 return 0;
3160}
3161
a4fc5ed6 3162static uint32_t
5829975c 3163gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3164{
3cf2efb1 3165 uint32_t signal_levels = 0;
a4fc5ed6 3166
3cf2efb1 3167 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3168 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3169 default:
3170 signal_levels |= DP_VOLTAGE_0_4;
3171 break;
bd60018a 3172 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3173 signal_levels |= DP_VOLTAGE_0_6;
3174 break;
bd60018a 3175 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3176 signal_levels |= DP_VOLTAGE_0_8;
3177 break;
bd60018a 3178 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3179 signal_levels |= DP_VOLTAGE_1_2;
3180 break;
3181 }
3cf2efb1 3182 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3183 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3184 default:
3185 signal_levels |= DP_PRE_EMPHASIS_0;
3186 break;
bd60018a 3187 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3188 signal_levels |= DP_PRE_EMPHASIS_3_5;
3189 break;
bd60018a 3190 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3191 signal_levels |= DP_PRE_EMPHASIS_6;
3192 break;
bd60018a 3193 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3194 signal_levels |= DP_PRE_EMPHASIS_9_5;
3195 break;
3196 }
3197 return signal_levels;
3198}
3199
e3421a18
ZW		 3200/* Gen6's DP voltage swing and pre-emphasis control */
3201static uint32_t
5829975c 3202gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3203{
3c5a62b5
YL		 3204 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3205 DP_TRAIN_PRE_EMPHASIS_MASK);
3206 switch (signal_levels) {
bd60018a
SJ		 3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3209 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3211 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3214 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3215 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3217 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3220 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3221 default:
3c5a62b5
YL		 3222 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3223 "0x%x\n", signal_levels);
3224 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3225 }
3226}
3227
1a2eb460
KP		 3228/* Gen7's DP voltage swing and pre-emphasis control */
3229static uint32_t
5829975c 3230gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3231{
3232 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3233 DP_TRAIN_PRE_EMPHASIS_MASK);
3234 switch (signal_levels) {
bd60018a 3235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3236 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3237 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3238 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3239 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3240 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3241
bd60018a 3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3243 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3244 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3245 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3246
bd60018a 3247 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3248 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3250 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3251
3252 default:
3253 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3254 "0x%x\n", signal_levels);
3255 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3256 }
3257}
3258
94223d04 3259void
f4eb692e 3260intel_dp_set_signal_levels(struct intel_dp *intel_dp)
f0a3424e
PZ		 3261{
3262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3263 enum port port = intel_dig_port->port;
f0a3424e 3264 struct drm_device *dev = intel_dig_port->base.base.dev;
b905a915 3265 struct drm_i915_private *dev_priv = to_i915(dev);
f8896f5d 3266 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3267 uint8_t train_set = intel_dp->train_set[0];
3268
f8896f5d
DW		 3269 if (HAS_DDI(dev)) {
3270 signal_levels = ddi_signal_levels(intel_dp);
3271
3272 if (IS_BROXTON(dev))
3273 signal_levels = 0;
3274 else
3275 mask = DDI_BUF_EMP_MASK;
e4a1d846 3276 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3277 signal_levels = chv_signal_levels(intel_dp);
e2fa6fba 3278 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3279 signal_levels = vlv_signal_levels(intel_dp);
bc7d38a4 3280 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3281 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3282 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3283 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3284 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3285 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3286 } else {
5829975c 3287 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3288 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3289 }
3290
96fb9f9b
VK		 3291 if (mask)
3292 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3293
3294 DRM_DEBUG_KMS("Using vswing level %d\n",
3295 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3296 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3297 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3298 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e 3299
f4eb692e 3300 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
b905a915
ACO		 3301
3302 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3303 POSTING_READ(intel_dp->output_reg);
f0a3424e
PZ		 3304}
3305
94223d04 3306void
e9c176d5
ACO		 3307intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3308 uint8_t dp_train_pat)
a4fc5ed6 3309{
174edf1f 3310 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3311 struct drm_i915_private *dev_priv =
3312 to_i915(intel_dig_port->base.base.dev);
a4fc5ed6 3313
f4eb692e 3314 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
47ea7542 3315
f4eb692e 3316 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
ea5b213a 3317 POSTING_READ(intel_dp->output_reg);
e9c176d5
ACO		 3318}
3319
94223d04 3320void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3ab9c637
ID		 3321{
3322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3323 struct drm_device *dev = intel_dig_port->base.base.dev;
3324 struct drm_i915_private *dev_priv = dev->dev_private;
3325 enum port port = intel_dig_port->port;
3326 uint32_t val;
3327
3328 if (!HAS_DDI(dev))
3329 return;
3330
3331 val = I915_READ(DP_TP_CTL(port));
3332 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3333 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3334 I915_WRITE(DP_TP_CTL(port), val);
3335
3336 /*
3337 * On PORT_A we can have only eDP in SST mode. There the only reason
3338 * we need to set idle transmission mode is to work around a HW issue
3339 * where we enable the pipe while not in idle link-training mode.
3340 * In this case there is requirement to wait for a minimum number of
3341 * idle patterns to be sent.
3342 */
3343 if (port == PORT_A)
3344 return;
3345
3346 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3347 1))
3348 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3349}
3350
a4fc5ed6 3351static void
ea5b213a 3352intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3353{
da63a9f2 3354 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3355 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3356 enum port port = intel_dig_port->port;
da63a9f2 3357 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3358 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3359 uint32_t DP = intel_dp->DP;
a4fc5ed6 3360
bc76e320 3361 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3362 return;
3363
0c33d8d7 3364 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3365 return;
3366
28c97730 3367 DRM_DEBUG_KMS("\n");
32f9d658 3368
39e5fa88
VS		 3369 if ((IS_GEN7(dev) && port == PORT_A) ||
3370 (HAS_PCH_CPT(dev) && port != PORT_A)) {
e3421a18 3371 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3372 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3373 } else {
aad3d14d
VS		 3374 if (IS_CHERRYVIEW(dev))
3375 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3376 else
3377 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3378 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3379 }
1612c8bd 3380 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3381 POSTING_READ(intel_dp->output_reg);
5eb08b69 3382
1612c8bd
VS		 3383 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3384 I915_WRITE(intel_dp->output_reg, DP);
3385 POSTING_READ(intel_dp->output_reg);
3386
3387 /*
3388 * HW workaround for IBX, we need to move the port
3389 * to transcoder A after disabling it to allow the
3390 * matching HDMI port to be enabled on transcoder A.
3391 */
3392 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
0c241d5b
VS		 3393 /*
3394 * We get CPU/PCH FIFO underruns on the other pipe when
3395 * doing the workaround. Sweep them under the rug.
3396 */
3397 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3398 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3399
1612c8bd
VS		 3400 /* always enable with pattern 1 (as per spec) */
3401 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3402 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3403 I915_WRITE(intel_dp->output_reg, DP);
3404 POSTING_READ(intel_dp->output_reg);
3405
3406 DP &= ~DP_PORT_EN;
5bddd17f 3407 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3408 POSTING_READ(intel_dp->output_reg);
0c241d5b
VS		 3409
3410 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3411 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3412 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5bddd17f
EA		 3413 }
3414
f01eca2e 3415 msleep(intel_dp->panel_power_down_delay);
6fec7662
VS		 3416
3417 intel_dp->DP = DP;
a4fc5ed6
KP		 3418}
3419
26d61aad
KP		 3420static bool
3421intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3422{
a031d709
RV		 3423 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3424 struct drm_device *dev = dig_port->base.base.dev;
3425 struct drm_i915_private *dev_priv = dev->dev_private;
3426
9f085ebb
L		 3427 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3428 sizeof(intel_dp->dpcd)) < 0)
edb39244 3429 return false; /* aux transfer failed */
92fd8fd1 3430
a8e98153 3431 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3432
edb39244
AJ		 3433 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3434 return false; /* DPCD not present */
3435
9f085ebb
L		 3436 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3437 &intel_dp->sink_count, 1) < 0)
30d9aa42
SS		 3438 return false;
3439
3440 /*
3441 * Sink count can change between short pulse hpd hence
3442 * a member variable in intel_dp will track any changes
3443 * between short pulse interrupts.
3444 */
3445 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3446
3447 /*
3448 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3449 * a dongle is present but no display. Unless we require to know
3450 * if a dongle is present or not, we don't need to update
3451 * downstream port information. So, an early return here saves
3452 * time from performing other operations which are not required.
3453 */
1034ce70 3454 if (!is_edp(intel_dp) && !intel_dp->sink_count)
30d9aa42
SS		 3455 return false;
3456
2293bb5c
SK		 3457 /* Check if the panel supports PSR */
3458 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3459 if (is_edp(intel_dp)) {
9f085ebb
L		 3460 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3461 intel_dp->psr_dpcd,
3462 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3463 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3464 dev_priv->psr.sink_support = true;
50003939 3465 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3466 }
474d1ec4
SJ		 3467
3468 if (INTEL_INFO(dev)->gen >= 9 &&
3469 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3470 uint8_t frame_sync_cap;
3471
3472 dev_priv->psr.sink_support = true;
9f085ebb
L		 3473 drm_dp_dpcd_read(&intel_dp->aux,
3474 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3475 &frame_sync_cap, 1);
474d1ec4
SJ		 3476 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3477 /* PSR2 needs frame sync as well */
3478 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3479 DRM_DEBUG_KMS("PSR2 %s on sink",
3480 dev_priv->psr.psr2_support ? "supported" : "not supported");
3481 }
86ee27b5
YA		 3482
3483 /* Read the eDP Display control capabilities registers */
3484 memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
3485 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
9a652cc0 3486 (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
86ee27b5
YA		 3487 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3488 sizeof(intel_dp->edp_dpcd)))
3489 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3490 intel_dp->edp_dpcd);
50003939
JN		 3491 }
3492
bc5133d5 3493 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
e588fa18 3494 yesno(intel_dp_source_supports_hbr2(intel_dp)),
742f491d 3495 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
06ea66b6 3496
fc0f8e25 3497 /* Intermediate frequency support */
86ee27b5 3498 if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */
94ca719e 3499 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3500 int i;
3501
9f085ebb
L		 3502 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3503 sink_rates, sizeof(sink_rates));
ea2d8a42 3504
94ca719e
VS		 3505 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3506 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3507
3508 if (val == 0)
3509 break;
3510
af77b974
SJ		 3511 /* Value read is in kHz while drm clock is saved in deca-kHz */
3512 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3513 }
94ca719e 3514 intel_dp->num_sink_rates = i;
fc0f8e25 3515 }
0336400e
VS		 3516
3517 intel_dp_print_rates(intel_dp);
3518
edb39244
AJ		 3519 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3520 DP_DWN_STRM_PORT_PRESENT))
3521 return true; /* native DP sink */
3522
3523 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3524 return true; /* no per-port downstream info */
3525
9f085ebb
L		 3526 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3527 intel_dp->downstream_ports,
3528 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3529 return false; /* downstream port status fetch failed */
3530
3531 return true;
92fd8fd1
KP		 3532}
3533
0d198328
AJ		 3534static void
3535intel_dp_probe_oui(struct intel_dp *intel_dp)
3536{
3537 u8 buf[3];
3538
3539 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3540 return;
3541
9f085ebb 3542 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3543 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3544 buf[0], buf[1], buf[2]);
3545
9f085ebb 3546 if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3547 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3548 buf[0], buf[1], buf[2]);
3549}
3550
0e32b39c
DA		 3551static bool
3552intel_dp_probe_mst(struct intel_dp *intel_dp)
3553{
3554 u8 buf[1];
3555
7cc96139
NS		 3556 if (!i915.enable_dp_mst)
3557 return false;
3558
0e32b39c
DA		 3559 if (!intel_dp->can_mst)
3560 return false;
3561
3562 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3563 return false;
3564
9f085ebb 3565 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
0e32b39c
DA		 3566 if (buf[0] & DP_MST_CAP) {
3567 DRM_DEBUG_KMS("Sink is MST capable\n");
3568 intel_dp->is_mst = true;
3569 } else {
3570 DRM_DEBUG_KMS("Sink is not MST capable\n");
3571 intel_dp->is_mst = false;
3572 }
3573 }
0e32b39c
DA		 3574
3575 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3576 return intel_dp->is_mst;
3577}
3578
e5a1cab5 3579static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
d2e216d0 3580{
082dcc7c 3581 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3582 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c 3583 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
ad9dc91b 3584 u8 buf;
e5a1cab5 3585 int ret = 0;
c6297843
RV		 3586 int count = 0;
3587 int attempts = 10;
d2e216d0 3588
082dcc7c
RV		 3589 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3590 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3591 ret = -EIO;
3592 goto out;
4373f0f2
PZ		 3593 }
3594
082dcc7c 3595 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
e5a1cab5 3596 buf & ~DP_TEST_SINK_START) < 0) {
082dcc7c 3597 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3598 ret = -EIO;
3599 goto out;
3600 }
d2e216d0 3601
c6297843
RV		 3602 do {
3603 intel_wait_for_vblank(dev, intel_crtc->pipe);
3604
3605 if (drm_dp_dpcd_readb(&intel_dp->aux,
3606 DP_TEST_SINK_MISC, &buf) < 0) {
3607 ret = -EIO;
3608 goto out;
3609 }
3610 count = buf & DP_TEST_COUNT_MASK;
3611 } while (--attempts && count);
3612
3613 if (attempts == 0) {
dc5a9037 3614 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
c6297843
RV		 3615 ret = -ETIMEDOUT;
3616 }
3617
e5a1cab5 3618 out:
082dcc7c 3619 hsw_enable_ips(intel_crtc);
e5a1cab5 3620 return ret;
082dcc7c
RV		 3621}
3622
3623static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3624{
3625 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3626 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c
RV		 3627 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3628 u8 buf;
e5a1cab5
RV		 3629 int ret;
3630
082dcc7c
RV		 3631 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3632 return -EIO;
3633
3634 if (!(buf & DP_TEST_CRC_SUPPORTED))
3635 return -ENOTTY;
3636
3637 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3638 return -EIO;
3639
6d8175da
RV		 3640 if (buf & DP_TEST_SINK_START) {
3641 ret = intel_dp_sink_crc_stop(intel_dp);
3642 if (ret)
3643 return ret;
3644 }
3645
082dcc7c 3646 hsw_disable_ips(intel_crtc);
1dda5f93 3647
9d1a1031 3648 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
082dcc7c
RV		 3649 buf | DP_TEST_SINK_START) < 0) {
3650 hsw_enable_ips(intel_crtc);
3651 return -EIO;
4373f0f2
PZ		 3652 }
3653
d72f9d91 3654 intel_wait_for_vblank(dev, intel_crtc->pipe);
082dcc7c
RV		 3655 return 0;
3656}
3657
3658int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3659{
3660 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3661 struct drm_device *dev = dig_port->base.base.dev;
3662 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3663 u8 buf;
621d4c76 3664 int count, ret;
082dcc7c 3665 int attempts = 6;
082dcc7c
RV		 3666
3667 ret = intel_dp_sink_crc_start(intel_dp);
3668 if (ret)
3669 return ret;
3670
ad9dc91b 3671 do {
621d4c76
RV		 3672 intel_wait_for_vblank(dev, intel_crtc->pipe);
3673
1dda5f93 3674 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 3675 DP_TEST_SINK_MISC, &buf) < 0) {
3676 ret = -EIO;
afe0d67e 3677 goto stop;
4373f0f2 3678 }
621d4c76 3679 count = buf & DP_TEST_COUNT_MASK;
aabc95dc 3680
7e38eeff 3681 } while (--attempts && count == 0);
ad9dc91b
RV		 3682
3683 if (attempts == 0) {
7e38eeff
RV		 3684 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3685 ret = -ETIMEDOUT;
3686 goto stop;
3687 }
3688
3689 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3690 ret = -EIO;
3691 goto stop;
ad9dc91b 3692 }
d2e216d0 3693
afe0d67e 3694stop:
082dcc7c 3695 intel_dp_sink_crc_stop(intel_dp);
4373f0f2 3696 return ret;
d2e216d0
RV		 3697}
3698
a60f0e38
JB		 3699static bool
3700intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3701{
9f085ebb 3702 return drm_dp_dpcd_read(&intel_dp->aux,
9d1a1031
JN		 3703 DP_DEVICE_SERVICE_IRQ_VECTOR,
3704 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3705}
3706
0e32b39c
DA		 3707static bool
3708intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3709{
3710 int ret;
3711
9f085ebb 3712 ret = drm_dp_dpcd_read(&intel_dp->aux,
0e32b39c
DA		 3713 DP_SINK_COUNT_ESI,
3714 sink_irq_vector, 14);
3715 if (ret != 14)
3716 return false;
3717
3718 return true;
3719}
3720
c5d5ab7a
TP		 3721static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3722{
3723 uint8_t test_result = DP_TEST_ACK;
3724 return test_result;
3725}
3726
3727static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3728{
3729 uint8_t test_result = DP_TEST_NAK;
3730 return test_result;
3731}
3732
3733static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 3734{
c5d5ab7a 3735 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 3736 struct intel_connector *intel_connector = intel_dp->attached_connector;
3737 struct drm_connector *connector = &intel_connector->base;
3738
3739 if (intel_connector->detect_edid == NULL ||
ac6f2e29 3740 connector->edid_corrupt ||
559be30c
TP		 3741 intel_dp->aux.i2c_defer_count > 6) {
3742 /* Check EDID read for NACKs, DEFERs and corruption
3743 * (DP CTS 1.2 Core r1.1)
3744 * 4.2.2.4 : Failed EDID read, I2C_NAK
3745 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3746 * 4.2.2.6 : EDID corruption detected
3747 * Use failsafe mode for all cases
3748 */
3749 if (intel_dp->aux.i2c_nack_count > 0 ||
3750 intel_dp->aux.i2c_defer_count > 0)
3751 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3752 intel_dp->aux.i2c_nack_count,
3753 intel_dp->aux.i2c_defer_count);
3754 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3755 } else {
f79b468e
TS		 3756 struct edid *block = intel_connector->detect_edid;
3757
3758 /* We have to write the checksum
3759 * of the last block read
3760 */
3761 block += intel_connector->detect_edid->extensions;
3762
559be30c
TP		 3763 if (!drm_dp_dpcd_write(&intel_dp->aux,
3764 DP_TEST_EDID_CHECKSUM,
f79b468e 3765 &block->checksum,
5a1cc655 3766 1))
559be30c
TP		 3767 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3768
3769 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3770 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3771 }
3772
3773 /* Set test active flag here so userspace doesn't interrupt things */
3774 intel_dp->compliance_test_active = 1;
3775
c5d5ab7a
TP		 3776 return test_result;
3777}
3778
3779static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 3780{
c5d5ab7a
TP		 3781 uint8_t test_result = DP_TEST_NAK;
3782 return test_result;
3783}
3784
3785static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3786{
3787 uint8_t response = DP_TEST_NAK;
3788 uint8_t rxdata = 0;
3789 int status = 0;
3790
c5d5ab7a
TP		 3791 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3792 if (status <= 0) {
3793 DRM_DEBUG_KMS("Could not read test request from sink\n");
3794 goto update_status;
3795 }
3796
3797 switch (rxdata) {
3798 case DP_TEST_LINK_TRAINING:
3799 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3800 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3801 response = intel_dp_autotest_link_training(intel_dp);
3802 break;
3803 case DP_TEST_LINK_VIDEO_PATTERN:
3804 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3805 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3806 response = intel_dp_autotest_video_pattern(intel_dp);
3807 break;
3808 case DP_TEST_LINK_EDID_READ:
3809 DRM_DEBUG_KMS("EDID test requested\n");
3810 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3811 response = intel_dp_autotest_edid(intel_dp);
3812 break;
3813 case DP_TEST_LINK_PHY_TEST_PATTERN:
3814 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3815 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3816 response = intel_dp_autotest_phy_pattern(intel_dp);
3817 break;
3818 default:
3819 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3820 break;
3821 }
3822
3823update_status:
3824 status = drm_dp_dpcd_write(&intel_dp->aux,
3825 DP_TEST_RESPONSE,
3826 &response, 1);
3827 if (status <= 0)
3828 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 3829}
3830
0e32b39c
DA		 3831static int
3832intel_dp_check_mst_status(struct intel_dp *intel_dp)
3833{
3834 bool bret;
3835
3836 if (intel_dp->is_mst) {
3837 u8 esi[16] = { 0 };
3838 int ret = 0;
3839 int retry;
3840 bool handled;
3841 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3842go_again:
3843 if (bret == true) {
3844
3845 /* check link status - esi[10] = 0x200c */
90a6b7b0 3846 if (intel_dp->active_mst_links &&
901c2daf 3847 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
0e32b39c
DA		 3848 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3849 intel_dp_start_link_train(intel_dp);
0e32b39c
DA		 3850 intel_dp_stop_link_train(intel_dp);
3851 }
3852
6f34cc39 3853 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 3854 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3855
3856 if (handled) {
3857 for (retry = 0; retry < 3; retry++) {
3858 int wret;
3859 wret = drm_dp_dpcd_write(&intel_dp->aux,
3860 DP_SINK_COUNT_ESI+1,
3861 &esi[1], 3);
3862 if (wret == 3) {
3863 break;
3864 }
3865 }
3866
3867 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3868 if (bret == true) {
6f34cc39 3869 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 3870 goto go_again;
3871 }
3872 } else
3873 ret = 0;
3874
3875 return ret;
3876 } else {
3877 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3878 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3879 intel_dp->is_mst = false;
3880 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3881 /* send a hotplug event */
3882 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3883 }
3884 }
3885 return -EINVAL;
3886}
3887
5c9114d0
SS		 3888static void
3889intel_dp_check_link_status(struct intel_dp *intel_dp)
3890{
3891 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3892 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3893 u8 link_status[DP_LINK_STATUS_SIZE];
3894
3895 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3896
3897 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3898 DRM_ERROR("Failed to get link status\n");
3899 return;
3900 }
3901
3902 if (!intel_encoder->base.crtc)
3903 return;
3904
3905 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3906 return;
3907
3908 /* if link training is requested we should perform it always */
3909 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
3910 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
3911 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3912 intel_encoder->base.name);
3913 intel_dp_start_link_train(intel_dp);
3914 intel_dp_stop_link_train(intel_dp);
3915 }
3916}
3917
a4fc5ed6
KP		 3918/*
3919 * According to DP spec
3920 * 5.1.2:
3921 * 1. Read DPCD
3922 * 2. Configure link according to Receiver Capabilities
3923 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3924 * 4. Check link status on receipt of hot-plug interrupt
39ff747b
SS		 3925 *
3926 * intel_dp_short_pulse - handles short pulse interrupts
3927 * when full detection is not required.
3928 * Returns %true if short pulse is handled and full detection
3929 * is NOT required and %false otherwise.
a4fc5ed6 3930 */
39ff747b 3931static bool
5c9114d0 3932intel_dp_short_pulse(struct intel_dp *intel_dp)
a4fc5ed6 3933{
5b215bcf 3934 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a60f0e38 3935 u8 sink_irq_vector;
39ff747b
SS		 3936 u8 old_sink_count = intel_dp->sink_count;
3937 bool ret;
5b215bcf 3938
4df6960e
SS		 3939 /*
3940 * Clearing compliance test variables to allow capturing
3941 * of values for next automated test request.
3942 */
3943 intel_dp->compliance_test_active = 0;
3944 intel_dp->compliance_test_type = 0;
3945 intel_dp->compliance_test_data = 0;
3946
39ff747b
SS		 3947 /*
3948 * Now read the DPCD to see if it's actually running
3949 * If the current value of sink count doesn't match with
3950 * the value that was stored earlier or dpcd read failed
3951 * we need to do full detection
3952 */
3953 ret = intel_dp_get_dpcd(intel_dp);
3954
3955 if ((old_sink_count != intel_dp->sink_count) || !ret) {
3956 /* No need to proceed if we are going to do full detect */
3957 return false;
59cd09e1
JB		 3958 }
3959
a60f0e38
JB		 3960 /* Try to read the source of the interrupt */
3961 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3962 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3963 /* Clear interrupt source */
9d1a1031
JN		 3964 drm_dp_dpcd_writeb(&intel_dp->aux,
3965 DP_DEVICE_SERVICE_IRQ_VECTOR,
3966 sink_irq_vector);
a60f0e38
JB		 3967
3968 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 3969 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 3970 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3971 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3972 }
3973
5c9114d0
SS		 3974 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3975 intel_dp_check_link_status(intel_dp);
3976 drm_modeset_unlock(&dev->mode_config.connection_mutex);
39ff747b
SS		 3977
3978 return true;
a4fc5ed6 3979}
a4fc5ed6 3980
caf9ab24 3981/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3982static enum drm_connector_status
26d61aad 3983intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3984{
caf9ab24 3985 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3986 uint8_t type;
3987
3988 if (!intel_dp_get_dpcd(intel_dp))
3989 return connector_status_disconnected;
3990
1034ce70
SS		 3991 if (is_edp(intel_dp))
3992 return connector_status_connected;
3993
caf9ab24
AJ		 3994 /* if there's no downstream port, we're done */
3995 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3996 return connector_status_connected;
caf9ab24
AJ		 3997
3998 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3999 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4000 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
9d1a1031 4001
30d9aa42
SS		 4002 return intel_dp->sink_count ?
4003 connector_status_connected : connector_status_disconnected;
caf9ab24
AJ		 4004 }
4005
4006 /* If no HPD, poke DDC gently */
0b99836f 4007 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4008 return connector_status_connected;
caf9ab24
AJ		 4009
4010 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4011 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4012 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4013 if (type == DP_DS_PORT_TYPE_VGA ||
4014 type == DP_DS_PORT_TYPE_NON_EDID)
4015 return connector_status_unknown;
4016 } else {
4017 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4018 DP_DWN_STRM_PORT_TYPE_MASK;
4019 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4020 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4021 return connector_status_unknown;
4022 }
caf9ab24
AJ		 4023
4024 /* Anything else is out of spec, warn and ignore */
4025 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4026 return connector_status_disconnected;
71ba9000
AJ		 4027}
4028
d410b56d
CW		 4029static enum drm_connector_status
4030edp_detect(struct intel_dp *intel_dp)
4031{
4032 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4033 enum drm_connector_status status;
4034
4035 status = intel_panel_detect(dev);
4036 if (status == connector_status_unknown)
4037 status = connector_status_connected;
4038
4039 return status;
4040}
4041
b93433cc
JN		 4042static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4043 struct intel_digital_port *port)
5eb08b69 4044{
b93433cc 4045 u32 bit;
01cb9ea6 4046
0df53b77
JN		 4047 switch (port->port) {
4048 case PORT_A:
4049 return true;
4050 case PORT_B:
4051 bit = SDE_PORTB_HOTPLUG;
4052 break;
4053 case PORT_C:
4054 bit = SDE_PORTC_HOTPLUG;
4055 break;
4056 case PORT_D:
4057 bit = SDE_PORTD_HOTPLUG;
4058 break;
4059 default:
4060 MISSING_CASE(port->port);
4061 return false;
4062 }
4063
4064 return I915_READ(SDEISR) & bit;
4065}
4066
4067static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4068 struct intel_digital_port *port)
4069{
4070 u32 bit;
4071
4072 switch (port->port) {
4073 case PORT_A:
4074 return true;
4075 case PORT_B:
4076 bit = SDE_PORTB_HOTPLUG_CPT;
4077 break;
4078 case PORT_C:
4079 bit = SDE_PORTC_HOTPLUG_CPT;
4080 break;
4081 case PORT_D:
4082 bit = SDE_PORTD_HOTPLUG_CPT;
4083 break;
a78695d3
JN		 4084 case PORT_E:
4085 bit = SDE_PORTE_HOTPLUG_SPT;
4086 break;
0df53b77
JN		 4087 default:
4088 MISSING_CASE(port->port);
4089 return false;
b93433cc 4090 }
1b469639 4091
b93433cc 4092 return I915_READ(SDEISR) & bit;
5eb08b69
ZW		 4093}
4094
7e66bcf2 4095static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
1d245987 4096 struct intel_digital_port *port)
a4fc5ed6 4097{
9642c81c 4098 u32 bit;
5eb08b69 4099
9642c81c
JN		 4100 switch (port->port) {
4101 case PORT_B:
4102 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4103 break;
4104 case PORT_C:
4105 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4106 break;
4107 case PORT_D:
4108 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4109 break;
4110 default:
4111 MISSING_CASE(port->port);
4112 return false;
4113 }
4114
4115 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4116}
4117
0780cd36
VS		 4118static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4119 struct intel_digital_port *port)
9642c81c
JN		 4120{
4121 u32 bit;
4122
4123 switch (port->port) {
4124 case PORT_B:
0780cd36 4125 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4126 break;
4127 case PORT_C:
0780cd36 4128 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4129 break;
4130 case PORT_D:
0780cd36 4131 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4132 break;
4133 default:
4134 MISSING_CASE(port->port);
4135 return false;
a4fc5ed6
KP		 4136 }
4137
1d245987 4138 return I915_READ(PORT_HOTPLUG_STAT) & bit;
2a592bec
DA		 4139}
4140
e464bfde 4141static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
e2ec35a5 4142 struct intel_digital_port *intel_dig_port)
e464bfde 4143{
e2ec35a5
SJ		 4144 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4145 enum port port;
e464bfde
JN		 4146 u32 bit;
4147
e2ec35a5
SJ		 4148 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4149 switch (port) {
e464bfde
JN		 4150 case PORT_A:
4151 bit = BXT_DE_PORT_HP_DDIA;
4152 break;
4153 case PORT_B:
4154 bit = BXT_DE_PORT_HP_DDIB;
4155 break;
4156 case PORT_C:
4157 bit = BXT_DE_PORT_HP_DDIC;
4158 break;
4159 default:
e2ec35a5 4160 MISSING_CASE(port);
e464bfde
JN		 4161 return false;
4162 }
4163
4164 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4165}
4166
7e66bcf2
JN		 4167/*
4168 * intel_digital_port_connected - is the specified port connected?
4169 * @dev_priv: i915 private structure
4170 * @port: the port to test
4171 *
4172 * Return %true if @port is connected, %false otherwise.
4173 */
237ed86c 4174bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
7e66bcf2
JN		 4175 struct intel_digital_port *port)
4176{
0df53b77 4177 if (HAS_PCH_IBX(dev_priv))
7e66bcf2 4178 return ibx_digital_port_connected(dev_priv, port);
22824fac 4179 else if (HAS_PCH_SPLIT(dev_priv))
0df53b77 4180 return cpt_digital_port_connected(dev_priv, port);
e464bfde
JN		 4181 else if (IS_BROXTON(dev_priv))
4182 return bxt_digital_port_connected(dev_priv, port);
0780cd36
VS		 4183 else if (IS_GM45(dev_priv))
4184 return gm45_digital_port_connected(dev_priv, port);
7e66bcf2
JN		 4185 else
4186 return g4x_digital_port_connected(dev_priv, port);
4187}
4188
8c241fef 4189static struct edid *
beb60608 4190intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4191{
beb60608 4192 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4193
9cd300e0
JN		 4194 /* use cached edid if we have one */
4195 if (intel_connector->edid) {
9cd300e0
JN		 4196 /* invalid edid */
4197 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4198 return NULL;
4199
55e9edeb 4200 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4201 } else
4202 return drm_get_edid(&intel_connector->base,
4203 &intel_dp->aux.ddc);
4204}
8c241fef 4205
beb60608
CW		 4206static void
4207intel_dp_set_edid(struct intel_dp *intel_dp)
4208{
4209 struct intel_connector *intel_connector = intel_dp->attached_connector;
4210 struct edid *edid;
8c241fef 4211
f21a2198 4212 intel_dp_unset_edid(intel_dp);
beb60608
CW		 4213 edid = intel_dp_get_edid(intel_dp);
4214 intel_connector->detect_edid = edid;
4215
4216 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4217 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4218 else
4219 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4220}
4221
beb60608
CW		 4222static void
4223intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4224{
beb60608 4225 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4226
beb60608
CW		 4227 kfree(intel_connector->detect_edid);
4228 intel_connector->detect_edid = NULL;
9cd300e0 4229
beb60608
CW		 4230 intel_dp->has_audio = false;
4231}
d6f24d0f 4232
f21a2198
SS		 4233static void
4234intel_dp_long_pulse(struct intel_connector *intel_connector)
a9756bb5 4235{
f21a2198 4236 struct drm_connector *connector = &intel_connector->base;
a9756bb5 4237 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4238 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4239 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4240 struct drm_device *dev = connector->dev;
a9756bb5 4241 enum drm_connector_status status;
671dedd2 4242 enum intel_display_power_domain power_domain;
0e32b39c 4243 bool ret;
09b1eb13 4244 u8 sink_irq_vector;
a9756bb5 4245
25f78f58
VS		 4246 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4247 intel_display_power_get(to_i915(dev), power_domain);
a9756bb5 4248
d410b56d
CW		 4249 /* Can't disconnect eDP, but you can close the lid... */
4250 if (is_edp(intel_dp))
4251 status = edp_detect(intel_dp);
c555a81d
ACO		 4252 else if (intel_digital_port_connected(to_i915(dev),
4253 dp_to_dig_port(intel_dp)))
4254 status = intel_dp_detect_dpcd(intel_dp);
a9756bb5 4255 else
c555a81d
ACO		 4256 status = connector_status_disconnected;
4257
4df6960e
SS		 4258 if (status != connector_status_connected) {
4259 intel_dp->compliance_test_active = 0;
4260 intel_dp->compliance_test_type = 0;
4261 intel_dp->compliance_test_data = 0;
4262
0e505a08 4263 if (intel_dp->is_mst) {
4264 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4265 intel_dp->is_mst,
4266 intel_dp->mst_mgr.mst_state);
4267 intel_dp->is_mst = false;
4268 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4269 intel_dp->is_mst);
4270 }
4271
c8c8fb33 4272 goto out;
4df6960e 4273 }
a9756bb5 4274
f21a2198
SS		 4275 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4276 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4277
0d198328
AJ		 4278 intel_dp_probe_oui(intel_dp);
4279
0e32b39c
DA		 4280 ret = intel_dp_probe_mst(intel_dp);
4281 if (ret) {
f21a2198
SS		 4282 /*
4283 * If we are in MST mode then this connector
4284 * won't appear connected or have anything
4285 * with EDID on it
4286 */
0e32b39c
DA		 4287 status = connector_status_disconnected;
4288 goto out;
7d23e3c3
SS		 4289 } else if (connector->status == connector_status_connected) {
4290 /*
4291 * If display was connected already and is still connected
4292 * check links status, there has been known issues of
4293 * link loss triggerring long pulse!!!!
4294 */
4295 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4296 intel_dp_check_link_status(intel_dp);
4297 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4298 goto out;
0e32b39c
DA		 4299 }
4300
4df6960e
SS		 4301 /*
4302 * Clearing NACK and defer counts to get their exact values
4303 * while reading EDID which are required by Compliance tests
4304 * 4.2.2.4 and 4.2.2.5
4305 */
4306 intel_dp->aux.i2c_nack_count = 0;
4307 intel_dp->aux.i2c_defer_count = 0;
4308
beb60608 4309 intel_dp_set_edid(intel_dp);
a9756bb5 4310
c8c8fb33 4311 status = connector_status_connected;
7d23e3c3 4312 intel_dp->detect_done = true;
c8c8fb33 4313
09b1eb13
TP		 4314 /* Try to read the source of the interrupt */
4315 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4316 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4317 /* Clear interrupt source */
4318 drm_dp_dpcd_writeb(&intel_dp->aux,
4319 DP_DEVICE_SERVICE_IRQ_VECTOR,
4320 sink_irq_vector);
4321
4322 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4323 intel_dp_handle_test_request(intel_dp);
4324 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4325 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4326 }
4327
c8c8fb33 4328out:
0e505a08 4329 if ((status != connector_status_connected) &&
4330 (intel_dp->is_mst == false))
f21a2198 4331 intel_dp_unset_edid(intel_dp);
7d23e3c3 4332
25f78f58 4333 intel_display_power_put(to_i915(dev), power_domain);
f21a2198
SS		 4334 return;
4335}
4336
4337static enum drm_connector_status
4338intel_dp_detect(struct drm_connector *connector, bool force)
4339{
4340 struct intel_dp *intel_dp = intel_attached_dp(connector);
4341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4342 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4343 struct intel_connector *intel_connector = to_intel_connector(connector);
4344
4345 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4346 connector->base.id, connector->name);
4347
4348 if (intel_dp->is_mst) {
4349 /* MST devices are disconnected from a monitor POV */
4350 intel_dp_unset_edid(intel_dp);
4351 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4352 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4353 return connector_status_disconnected;
4354 }
4355
7d23e3c3
SS		 4356 /* If full detect is not performed yet, do a full detect */
4357 if (!intel_dp->detect_done)
4358 intel_dp_long_pulse(intel_dp->attached_connector);
4359
4360 intel_dp->detect_done = false;
f21a2198
SS		 4361
4362 if (intel_connector->detect_edid)
4363 return connector_status_connected;
4364 else
4365 return connector_status_disconnected;
a4fc5ed6
KP		 4366}
4367
beb60608
CW		 4368static void
4369intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4370{
df0e9248 4371 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4372 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
25f78f58 4373 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
671dedd2 4374 enum intel_display_power_domain power_domain;
a4fc5ed6 4375
beb60608
CW		 4376 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4377 connector->base.id, connector->name);
4378 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4379
beb60608
CW		 4380 if (connector->status != connector_status_connected)
4381 return;
671dedd2 4382
25f78f58
VS		 4383 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4384 intel_display_power_get(dev_priv, power_domain);
beb60608
CW		 4385
4386 intel_dp_set_edid(intel_dp);
4387
25f78f58 4388 intel_display_power_put(dev_priv, power_domain);
beb60608
CW		 4389
4390 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4391 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4392}
4393
4394static int intel_dp_get_modes(struct drm_connector *connector)
4395{
4396 struct intel_connector *intel_connector = to_intel_connector(connector);
4397 struct edid *edid;
4398
4399 edid = intel_connector->detect_edid;
4400 if (edid) {
4401 int ret = intel_connector_update_modes(connector, edid);
4402 if (ret)
4403 return ret;
4404 }
32f9d658 4405
f8779fda 4406 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4407 if (is_edp(intel_attached_dp(connector)) &&
4408 intel_connector->panel.fixed_mode) {
f8779fda 4409 struct drm_display_mode *mode;
beb60608
CW		 4410
4411 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4412 intel_connector->panel.fixed_mode);
f8779fda 4413 if (mode) {
32f9d658
ZW		 4414 drm_mode_probed_add(connector, mode);
4415 return 1;
4416 }
4417 }
beb60608 4418
32f9d658 4419 return 0;
a4fc5ed6
KP		 4420}
4421
1aad7ac0
CW		 4422static bool
4423intel_dp_detect_audio(struct drm_connector *connector)
4424{
1aad7ac0 4425 bool has_audio = false;
beb60608 4426 struct edid *edid;
1aad7ac0 4427
beb60608
CW		 4428 edid = to_intel_connector(connector)->detect_edid;
4429 if (edid)
1aad7ac0 4430 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4431
1aad7ac0
CW		 4432 return has_audio;
4433}
4434
f684960e
CW		 4435static int
4436intel_dp_set_property(struct drm_connector *connector,
4437 struct drm_property *property,
4438 uint64_t val)
4439{
e953fd7b 4440 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4441 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4442 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4443 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4444 int ret;
4445
662595df 4446 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4447 if (ret)
4448 return ret;
4449
3f43c48d 4450 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4451 int i = val;
4452 bool has_audio;
4453
4454 if (i == intel_dp->force_audio)
f684960e
CW		 4455 return 0;
4456
1aad7ac0 4457 intel_dp->force_audio = i;
f684960e 4458
c3e5f67b 4459 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4460 has_audio = intel_dp_detect_audio(connector);
4461 else
c3e5f67b 4462 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4463
4464 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4465 return 0;
4466
1aad7ac0 4467 intel_dp->has_audio = has_audio;
f684960e
CW		 4468 goto done;
4469 }
4470
e953fd7b 4471 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 4472 bool old_auto = intel_dp->color_range_auto;
0f2a2a75 4473 bool old_range = intel_dp->limited_color_range;
ae4edb80 4474
55bc60db
VS		 4475 switch (val) {
4476 case INTEL_BROADCAST_RGB_AUTO:
4477 intel_dp->color_range_auto = true;
4478 break;
4479 case INTEL_BROADCAST_RGB_FULL:
4480 intel_dp->color_range_auto = false;
0f2a2a75 4481 intel_dp->limited_color_range = false;
55bc60db
VS		 4482 break;
4483 case INTEL_BROADCAST_RGB_LIMITED:
4484 intel_dp->color_range_auto = false;
0f2a2a75 4485 intel_dp->limited_color_range = true;
55bc60db
VS		 4486 break;
4487 default:
4488 return -EINVAL;
4489 }
ae4edb80
DV		 4490
4491 if (old_auto == intel_dp->color_range_auto &&
0f2a2a75 4492 old_range == intel_dp->limited_color_range)
ae4edb80
DV		 4493 return 0;
4494
e953fd7b
CW		 4495 goto done;
4496 }
4497
53b41837
YN		 4498 if (is_edp(intel_dp) &&
4499 property == connector->dev->mode_config.scaling_mode_property) {
4500 if (val == DRM_MODE_SCALE_NONE) {
4501 DRM_DEBUG_KMS("no scaling not supported\n");
4502 return -EINVAL;
4503 }
234126c6
VS		 4504 if (HAS_GMCH_DISPLAY(dev_priv) &&
4505 val == DRM_MODE_SCALE_CENTER) {
4506 DRM_DEBUG_KMS("centering not supported\n");
4507 return -EINVAL;
4508 }
53b41837
YN		 4509
4510 if (intel_connector->panel.fitting_mode == val) {
4511 /* the eDP scaling property is not changed */
4512 return 0;
4513 }
4514 intel_connector->panel.fitting_mode = val;
4515
4516 goto done;
4517 }
4518
f684960e
CW		 4519 return -EINVAL;
4520
4521done:
c0c36b94
CW		 4522 if (intel_encoder->base.crtc)
4523 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4524
4525 return 0;
4526}
4527
a4fc5ed6 4528static void
73845adf 4529intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4530{
1d508706 4531 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4532
10e972d3 4533 kfree(intel_connector->detect_edid);
beb60608 4534
9cd300e0
JN		 4535 if (!IS_ERR_OR_NULL(intel_connector->edid))
4536 kfree(intel_connector->edid);
4537
acd8db10
PZ		 4538 /* Can't call is_edp() since the encoder may have been destroyed
4539 * already. */
4540 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4541 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4542
a4fc5ed6 4543 drm_connector_cleanup(connector);
55f78c43 4544 kfree(connector);
a4fc5ed6
KP		 4545}
4546
00c09d70 4547void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4548{
da63a9f2
PZ		 4549 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4550 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4551
0e32b39c 4552 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4553 if (is_edp(intel_dp)) {
4554 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4555 /*
4556 * vdd might still be enabled do to the delayed vdd off.
4557 * Make sure vdd is actually turned off here.
4558 */
773538e8 4559 pps_lock(intel_dp);
4be73780 4560 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4561 pps_unlock(intel_dp);
4562
01527b31
CT		 4563 if (intel_dp->edp_notifier.notifier_call) {
4564 unregister_reboot_notifier(&intel_dp->edp_notifier);
4565 intel_dp->edp_notifier.notifier_call = NULL;
4566 }
bd943159 4567 }
c8bd0e49 4568 drm_encoder_cleanup(encoder);
da63a9f2 4569 kfree(intel_dig_port);
24d05927
DV		 4570}
4571
bf93ba67 4572void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
07f9cd0b
ID		 4573{
4574 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4575
4576 if (!is_edp(intel_dp))
4577 return;
4578
951468f3
VS		 4579 /*
4580 * vdd might still be enabled do to the delayed vdd off.
4581 * Make sure vdd is actually turned off here.
4582 */
afa4e53a 4583 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4584 pps_lock(intel_dp);
07f9cd0b 4585 edp_panel_vdd_off_sync(intel_dp);
773538e8 4586 pps_unlock(intel_dp);
07f9cd0b
ID		 4587}
4588
49e6bc51
VS		 4589static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4590{
4591 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4592 struct drm_device *dev = intel_dig_port->base.base.dev;
4593 struct drm_i915_private *dev_priv = dev->dev_private;
4594 enum intel_display_power_domain power_domain;
4595
4596 lockdep_assert_held(&dev_priv->pps_mutex);
4597
4598 if (!edp_have_panel_vdd(intel_dp))
4599 return;
4600
4601 /*
4602 * The VDD bit needs a power domain reference, so if the bit is
4603 * already enabled when we boot or resume, grab this reference and
4604 * schedule a vdd off, so we don't hold on to the reference
4605 * indefinitely.
4606 */
4607 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
25f78f58 4608 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
49e6bc51
VS		 4609 intel_display_power_get(dev_priv, power_domain);
4610
4611 edp_panel_vdd_schedule_off(intel_dp);
4612}
4613
bf93ba67 4614void intel_dp_encoder_reset(struct drm_encoder *encoder)
6d93c0c4 4615{
49e6bc51
VS		 4616 struct intel_dp *intel_dp;
4617
4618 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4619 return;
4620
4621 intel_dp = enc_to_intel_dp(encoder);
4622
4623 pps_lock(intel_dp);
4624
4625 /*
4626 * Read out the current power sequencer assignment,
4627 * in case the BIOS did something with it.
4628 */
666a4537 4629 if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
49e6bc51
VS		 4630 vlv_initial_power_sequencer_setup(intel_dp);
4631
4632 intel_edp_panel_vdd_sanitize(intel_dp);
4633
4634 pps_unlock(intel_dp);
6d93c0c4
ID		 4635}
4636
a4fc5ed6 4637static const struct drm_connector_funcs intel_dp_connector_funcs = {
4d688a2a 4638 .dpms = drm_atomic_helper_connector_dpms,
a4fc5ed6 4639 .detect = intel_dp_detect,
beb60608 4640 .force = intel_dp_force,
a4fc5ed6 4641 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4642 .set_property = intel_dp_set_property,
2545e4a6 4643 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4644 .destroy = intel_dp_connector_destroy,
c6f95f27 4645 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4646 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4647};
4648
4649static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4650 .get_modes = intel_dp_get_modes,
4651 .mode_valid = intel_dp_mode_valid,
a4fc5ed6
KP		 4652};
4653
a4fc5ed6 4654static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4655 .reset = intel_dp_encoder_reset,
24d05927 4656 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4657};
4658
b2c5c181 4659enum irqreturn
13cf5504
DA		 4660intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4661{
4662 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4663 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4664 struct drm_device *dev = intel_dig_port->base.base.dev;
4665 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4666 enum intel_display_power_domain power_domain;
b2c5c181 4667 enum irqreturn ret = IRQ_NONE;
1c767b33 4668
2540058f
TI		 4669 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4670 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
0e32b39c 4671 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4672
7a7f84cc
VS		 4673 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4674 /*
4675 * vdd off can generate a long pulse on eDP which
4676 * would require vdd on to handle it, and thus we
4677 * would end up in an endless cycle of
4678 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4679 */
4680 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4681 port_name(intel_dig_port->port));
a8b3d52f 4682 return IRQ_HANDLED;
7a7f84cc
VS		 4683 }
4684
26fbb774
VS		 4685 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4686 port_name(intel_dig_port->port),
0e32b39c 4687 long_hpd ? "long" : "short");
13cf5504 4688
25f78f58 4689 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1c767b33
ID		 4690 intel_display_power_get(dev_priv, power_domain);
4691
0e32b39c 4692 if (long_hpd) {
7d23e3c3
SS		 4693 intel_dp_long_pulse(intel_dp->attached_connector);
4694 if (intel_dp->is_mst)
4695 ret = IRQ_HANDLED;
4696 goto put_power;
0e32b39c 4697
0e32b39c
DA		 4698 } else {
4699 if (intel_dp->is_mst) {
7d23e3c3
SS		 4700 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4701 /*
4702 * If we were in MST mode, and device is not
4703 * there, get out of MST mode
4704 */
4705 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4706 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4707 intel_dp->is_mst = false;
4708 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4709 intel_dp->is_mst);
4710 goto put_power;
4711 }
0e32b39c
DA		 4712 }
4713
39ff747b
SS		 4714 if (!intel_dp->is_mst) {
4715 if (!intel_dp_short_pulse(intel_dp)) {
4716 intel_dp_long_pulse(intel_dp->attached_connector);
4717 goto put_power;
4718 }
4719 }
0e32b39c 4720 }
b2c5c181
DV		 4721
4722 ret = IRQ_HANDLED;
4723
1c767b33
ID		 4724put_power:
4725 intel_display_power_put(dev_priv, power_domain);
4726
4727 return ret;
13cf5504
DA		 4728}
4729
477ec328 4730/* check the VBT to see whether the eDP is on another port */
5d8a7752 4731bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4732{
4733 struct drm_i915_private *dev_priv = dev->dev_private;
36e83a18 4734
53ce81a7
VS		 4735 /*
4736 * eDP not supported on g4x. so bail out early just
4737 * for a bit extra safety in case the VBT is bonkers.
4738 */
4739 if (INTEL_INFO(dev)->gen < 5)
4740 return false;
4741
3b32a35b
VS		 4742 if (port == PORT_A)
4743 return true;
4744
951d9efe 4745 return intel_bios_is_port_edp(dev_priv, port);
36e83a18
ZY		 4746}
4747
0e32b39c 4748void
f684960e
CW		 4749intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4750{
53b41837
YN		 4751 struct intel_connector *intel_connector = to_intel_connector(connector);
4752
3f43c48d 4753 intel_attach_force_audio_property(connector);
e953fd7b 4754 intel_attach_broadcast_rgb_property(connector);
55bc60db 4755 intel_dp->color_range_auto = true;
53b41837
YN		 4756
4757 if (is_edp(intel_dp)) {
4758 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4759 drm_object_attach_property(
4760 &connector->base,
53b41837 4761 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4762 DRM_MODE_SCALE_ASPECT);
4763 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4764 }
f684960e
CW		 4765}
4766
dada1a9f
ID		 4767static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4768{
d28d4731 4769 intel_dp->panel_power_off_time = ktime_get_boottime();
dada1a9f
ID		 4770 intel_dp->last_power_on = jiffies;
4771 intel_dp->last_backlight_off = jiffies;
4772}
4773
67a54566
DV		 4774static void
4775intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4776 struct intel_dp *intel_dp)
67a54566
DV		 4777{
4778 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4779 struct edp_power_seq cur, vbt, spec,
4780 *final = &intel_dp->pps_delays;
b0a08bec 4781 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
8e8232d5 4782 struct pps_registers regs;
453c5420 4783
e39b999a
VS		 4784 lockdep_assert_held(&dev_priv->pps_mutex);
4785
81ddbc69
VS		 4786 /* already initialized? */
4787 if (final->t11_t12 != 0)
4788 return;
4789
8e8232d5 4790 intel_pps_get_registers(dev_priv, intel_dp, &regs);
67a54566
DV		 4791
4792 /* Workaround: Need to write PP_CONTROL with the unlock key as
4793 * the very first thing. */
b0a08bec 4794 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 4795
8e8232d5
ID		 4796 pp_on = I915_READ(regs.pp_on);
4797 pp_off = I915_READ(regs.pp_off);
b0a08bec 4798 if (!IS_BROXTON(dev)) {
8e8232d5
ID		 4799 I915_WRITE(regs.pp_ctrl, pp_ctl);
4800 pp_div = I915_READ(regs.pp_div);
b0a08bec 4801 }
67a54566
DV		 4802
4803 /* Pull timing values out of registers */
4804 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4805 PANEL_POWER_UP_DELAY_SHIFT;
4806
4807 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4808 PANEL_LIGHT_ON_DELAY_SHIFT;
4809
4810 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4811 PANEL_LIGHT_OFF_DELAY_SHIFT;
4812
4813 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4814 PANEL_POWER_DOWN_DELAY_SHIFT;
4815
b0a08bec
VK		 4816 if (IS_BROXTON(dev)) {
4817 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4818 BXT_POWER_CYCLE_DELAY_SHIFT;
4819 if (tmp > 0)
4820 cur.t11_t12 = (tmp - 1) * 1000;
4821 else
4822 cur.t11_t12 = 0;
4823 } else {
4824 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 4825 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 4826 }
67a54566
DV		 4827
4828 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4829 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4830
6aa23e65 4831 vbt = dev_priv->vbt.edp.pps;
67a54566
DV		 4832
4833 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4834 * our hw here, which are all in 100usec. */
4835 spec.t1_t3 = 210 * 10;
4836 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4837 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4838 spec.t10 = 500 * 10;
4839 /* This one is special and actually in units of 100ms, but zero
4840 * based in the hw (so we need to add 100 ms). But the sw vbt
4841 * table multiplies it with 1000 to make it in units of 100usec,
4842 * too. */
4843 spec.t11_t12 = (510 + 100) * 10;
4844
4845 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4846 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4847
4848 /* Use the max of the register settings and vbt. If both are
4849 * unset, fall back to the spec limits. */
36b5f425 4850#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4851 spec.field : \
4852 max(cur.field, vbt.field))
4853 assign_final(t1_t3);
4854 assign_final(t8);
4855 assign_final(t9);
4856 assign_final(t10);
4857 assign_final(t11_t12);
4858#undef assign_final
4859
36b5f425 4860#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4861 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4862 intel_dp->backlight_on_delay = get_delay(t8);
4863 intel_dp->backlight_off_delay = get_delay(t9);
4864 intel_dp->panel_power_down_delay = get_delay(t10);
4865 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4866#undef get_delay
4867
f30d26e4
JN		 4868 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4869 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4870 intel_dp->panel_power_cycle_delay);
4871
4872 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4873 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4874}
4875
4876static void
4877intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4878 struct intel_dp *intel_dp)
f30d26e4
JN		 4879{
4880 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 4881 u32 pp_on, pp_off, pp_div, port_sel = 0;
e7dc33f3 4882 int div = dev_priv->rawclk_freq / 1000;
8e8232d5 4883 struct pps_registers regs;
ad933b56 4884 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4885 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4886
e39b999a 4887 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 4888
8e8232d5 4889 intel_pps_get_registers(dev_priv, intel_dp, &regs);
453c5420 4890
b2f19d1a
PZ		 4891 /*
4892 * And finally store the new values in the power sequencer. The
4893 * backlight delays are set to 1 because we do manual waits on them. For
4894 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4895 * we'll end up waiting for the backlight off delay twice: once when we
4896 * do the manual sleep, and once when we disable the panel and wait for
4897 * the PP_STATUS bit to become zero.
4898 */
f30d26e4 4899 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4900 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4901 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4902 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4903 /* Compute the divisor for the pp clock, simply match the Bspec
4904 * formula. */
b0a08bec 4905 if (IS_BROXTON(dev)) {
8e8232d5 4906 pp_div = I915_READ(regs.pp_ctrl);
b0a08bec
VK		 4907 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
4908 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
4909 << BXT_POWER_CYCLE_DELAY_SHIFT);
4910 } else {
4911 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4912 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4913 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4914 }
67a54566
DV		 4915
4916 /* Haswell doesn't have any port selection bits for the panel
4917 * power sequencer any more. */
666a4537 4918 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
ad933b56 4919 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4920 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4921 if (port == PORT_A)
a24c144c 4922 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4923 else
a24c144c 4924 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4925 }
4926
453c5420
JB		 4927 pp_on |= port_sel;
4928
8e8232d5
ID		 4929 I915_WRITE(regs.pp_on, pp_on);
4930 I915_WRITE(regs.pp_off, pp_off);
b0a08bec 4931 if (IS_BROXTON(dev))
8e8232d5 4932 I915_WRITE(regs.pp_ctrl, pp_div);
b0a08bec 4933 else
8e8232d5 4934 I915_WRITE(regs.pp_div, pp_div);
67a54566 4935
67a54566 4936 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
8e8232d5
ID		 4937 I915_READ(regs.pp_on),
4938 I915_READ(regs.pp_off),
b0a08bec 4939 IS_BROXTON(dev) ?
8e8232d5
ID		 4940 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
4941 I915_READ(regs.pp_div));
f684960e
CW		 4942}
4943
b33a2815
VK		 4944/**
4945 * intel_dp_set_drrs_state - program registers for RR switch to take effect
4946 * @dev: DRM device
4947 * @refresh_rate: RR to be programmed
4948 *
4949 * This function gets called when refresh rate (RR) has to be changed from
4950 * one frequency to another. Switches can be between high and low RR
4951 * supported by the panel or to any other RR based on media playback (in
4952 * this case, RR value needs to be passed from user space).
4953 *
4954 * The caller of this function needs to take a lock on dev_priv->drrs.
4955 */
96178eeb 4956static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 4957{
4958 struct drm_i915_private *dev_priv = dev->dev_private;
4959 struct intel_encoder *encoder;
96178eeb
VK		 4960 struct intel_digital_port *dig_port = NULL;
4961 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 4962 struct intel_crtc_state *config = NULL;
439d7ac0 4963 struct intel_crtc *intel_crtc = NULL;
96178eeb 4964 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 4965
4966 if (refresh_rate <= 0) {
4967 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4968 return;
4969 }
4970
96178eeb
VK		 4971 if (intel_dp == NULL) {
4972 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 4973 return;
4974 }
4975
1fcc9d1c 4976 /*
e4d59f6b
RV		 4977 * FIXME: This needs proper synchronization with psr state for some
4978 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 4979 */
439d7ac0 4980
96178eeb
VK		 4981 dig_port = dp_to_dig_port(intel_dp);
4982 encoder = &dig_port->base;
723f9aab 4983 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 4984
4985 if (!intel_crtc) {
4986 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4987 return;
4988 }
4989
6e3c9717 4990 config = intel_crtc->config;
439d7ac0 4991
96178eeb 4992 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 4993 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4994 return;
4995 }
4996
96178eeb
VK		 4997 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
4998 refresh_rate)
439d7ac0
PB		 4999 index = DRRS_LOW_RR;
5000
96178eeb 5001 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5002 DRM_DEBUG_KMS(
5003 "DRRS requested for previously set RR...ignoring\n");
5004 return;
5005 }
5006
5007 if (!intel_crtc->active) {
5008 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5009 return;
5010 }
5011
44395bfe 5012 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5013 switch (index) {
5014 case DRRS_HIGH_RR:
5015 intel_dp_set_m_n(intel_crtc, M1_N1);
5016 break;
5017 case DRRS_LOW_RR:
5018 intel_dp_set_m_n(intel_crtc, M2_N2);
5019 break;
5020 case DRRS_MAX_RR:
5021 default:
5022 DRM_ERROR("Unsupported refreshrate type\n");
5023 }
5024 } else if (INTEL_INFO(dev)->gen > 6) {
f0f59a00 5025 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
649636ef 5026 u32 val;
a4c30b1d 5027
649636ef 5028 val = I915_READ(reg);
439d7ac0 5029 if (index > DRRS_HIGH_RR) {
666a4537 5030 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6fa7aec1
VK		 5031 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5032 else
5033 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5034 } else {
666a4537 5035 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6fa7aec1
VK		 5036 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5037 else
5038 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5039 }
5040 I915_WRITE(reg, val);
5041 }
5042
4e9ac947
VK		 5043 dev_priv->drrs.refresh_rate_type = index;
5044
5045 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5046}
5047
b33a2815
VK		 5048/**
5049 * intel_edp_drrs_enable - init drrs struct if supported
5050 * @intel_dp: DP struct
5051 *
5052 * Initializes frontbuffer_bits and drrs.dp
5053 */
c395578e
VK		 5054void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5055{
5056 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5057 struct drm_i915_private *dev_priv = dev->dev_private;
5058 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5059 struct drm_crtc *crtc = dig_port->base.base.crtc;
5060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5061
5062 if (!intel_crtc->config->has_drrs) {
5063 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5064 return;
5065 }
5066
5067 mutex_lock(&dev_priv->drrs.mutex);
5068 if (WARN_ON(dev_priv->drrs.dp)) {
5069 DRM_ERROR("DRRS already enabled\n");
5070 goto unlock;
5071 }
5072
5073 dev_priv->drrs.busy_frontbuffer_bits = 0;
5074
5075 dev_priv->drrs.dp = intel_dp;
5076
5077unlock:
5078 mutex_unlock(&dev_priv->drrs.mutex);
5079}
5080
b33a2815
VK		 5081/**
5082 * intel_edp_drrs_disable - Disable DRRS
5083 * @intel_dp: DP struct
5084 *
5085 */
c395578e
VK		 5086void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5087{
5088 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5089 struct drm_i915_private *dev_priv = dev->dev_private;
5090 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5091 struct drm_crtc *crtc = dig_port->base.base.crtc;
5092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5093
5094 if (!intel_crtc->config->has_drrs)
5095 return;
5096
5097 mutex_lock(&dev_priv->drrs.mutex);
5098 if (!dev_priv->drrs.dp) {
5099 mutex_unlock(&dev_priv->drrs.mutex);
5100 return;
5101 }
5102
5103 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5104 intel_dp_set_drrs_state(dev_priv->dev,
5105 intel_dp->attached_connector->panel.
5106 fixed_mode->vrefresh);
5107
5108 dev_priv->drrs.dp = NULL;
5109 mutex_unlock(&dev_priv->drrs.mutex);
5110
5111 cancel_delayed_work_sync(&dev_priv->drrs.work);
5112}
5113
4e9ac947
VK		 5114static void intel_edp_drrs_downclock_work(struct work_struct *work)
5115{
5116 struct drm_i915_private *dev_priv =
5117 container_of(work, typeof(*dev_priv), drrs.work.work);
5118 struct intel_dp *intel_dp;
5119
5120 mutex_lock(&dev_priv->drrs.mutex);
5121
5122 intel_dp = dev_priv->drrs.dp;
5123
5124 if (!intel_dp)
5125 goto unlock;
5126
439d7ac0 5127 /*
4e9ac947
VK		 5128 * The delayed work can race with an invalidate hence we need to
5129 * recheck.
439d7ac0
PB		 5130 */
5131
4e9ac947
VK		 5132 if (dev_priv->drrs.busy_frontbuffer_bits)
5133 goto unlock;
439d7ac0 5134
4e9ac947
VK		 5135 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5136 intel_dp_set_drrs_state(dev_priv->dev,
5137 intel_dp->attached_connector->panel.
5138 downclock_mode->vrefresh);
439d7ac0 5139
4e9ac947 5140unlock:
4e9ac947 5141 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5142}
5143
b33a2815 5144/**
0ddfd203 5145 * intel_edp_drrs_invalidate - Disable Idleness DRRS
b33a2815
VK		 5146 * @dev: DRM device
5147 * @frontbuffer_bits: frontbuffer plane tracking bits
5148 *
0ddfd203
R		 5149 * This function gets called everytime rendering on the given planes start.
5150 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5151 *
5152 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5153 */
a93fad0f
VK		 5154void intel_edp_drrs_invalidate(struct drm_device *dev,
5155 unsigned frontbuffer_bits)
5156{
5157 struct drm_i915_private *dev_priv = dev->dev_private;
5158 struct drm_crtc *crtc;
5159 enum pipe pipe;
5160
9da7d693 5161 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5162 return;
5163
88f933a8 5164 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5165
a93fad0f 5166 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5167 if (!dev_priv->drrs.dp) {
5168 mutex_unlock(&dev_priv->drrs.mutex);
5169 return;
5170 }
5171
a93fad0f
VK		 5172 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5173 pipe = to_intel_crtc(crtc)->pipe;
5174
c1d038c6
DV		 5175 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5176 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5177
0ddfd203 5178 /* invalidate means busy screen hence upclock */
c1d038c6 5179 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
a93fad0f
VK		 5180 intel_dp_set_drrs_state(dev_priv->dev,
5181 dev_priv->drrs.dp->attached_connector->panel.
5182 fixed_mode->vrefresh);
a93fad0f 5183
a93fad0f
VK		 5184 mutex_unlock(&dev_priv->drrs.mutex);
5185}
5186
b33a2815 5187/**
0ddfd203 5188 * intel_edp_drrs_flush - Restart Idleness DRRS
b33a2815
VK		 5189 * @dev: DRM device
5190 * @frontbuffer_bits: frontbuffer plane tracking bits
5191 *
0ddfd203
R		 5192 * This function gets called every time rendering on the given planes has
5193 * completed or flip on a crtc is completed. So DRRS should be upclocked
5194 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5195 * if no other planes are dirty.
b33a2815
VK		 5196 *
5197 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5198 */
a93fad0f
VK		 5199void intel_edp_drrs_flush(struct drm_device *dev,
5200 unsigned frontbuffer_bits)
5201{
5202 struct drm_i915_private *dev_priv = dev->dev_private;
5203 struct drm_crtc *crtc;
5204 enum pipe pipe;
5205
9da7d693 5206 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5207 return;
5208
88f933a8 5209 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5210
a93fad0f 5211 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5212 if (!dev_priv->drrs.dp) {
5213 mutex_unlock(&dev_priv->drrs.mutex);
5214 return;
5215 }
5216
a93fad0f
VK		 5217 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5218 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5219
5220 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5221 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5222
0ddfd203 5223 /* flush means busy screen hence upclock */
c1d038c6 5224 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
0ddfd203
R		 5225 intel_dp_set_drrs_state(dev_priv->dev,
5226 dev_priv->drrs.dp->attached_connector->panel.
5227 fixed_mode->vrefresh);
5228
5229 /*
5230 * flush also means no more activity hence schedule downclock, if all
5231 * other fbs are quiescent too
5232 */
5233 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5234 schedule_delayed_work(&dev_priv->drrs.work,
5235 msecs_to_jiffies(1000));
5236 mutex_unlock(&dev_priv->drrs.mutex);
5237}
5238
b33a2815
VK		 5239/**
5240 * DOC: Display Refresh Rate Switching (DRRS)
5241 *
5242 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5243 * which enables swtching between low and high refresh rates,
5244 * dynamically, based on the usage scenario. This feature is applicable
5245 * for internal panels.
5246 *
5247 * Indication that the panel supports DRRS is given by the panel EDID, which
5248 * would list multiple refresh rates for one resolution.
5249 *
5250 * DRRS is of 2 types - static and seamless.
5251 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5252 * (may appear as a blink on screen) and is used in dock-undock scenario.
5253 * Seamless DRRS involves changing RR without any visual effect to the user
5254 * and can be used during normal system usage. This is done by programming
5255 * certain registers.
5256 *
5257 * Support for static/seamless DRRS may be indicated in the VBT based on
5258 * inputs from the panel spec.
5259 *
5260 * DRRS saves power by switching to low RR based on usage scenarios.
5261 *
2e7a5701
DV		 5262 * The implementation is based on frontbuffer tracking implementation. When
5263 * there is a disturbance on the screen triggered by user activity or a periodic
5264 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5265 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5266 * made.
5267 *
5268 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5269 * and intel_edp_drrs_flush() are called.
b33a2815
VK		 5270 *
5271 * DRRS can be further extended to support other internal panels and also
5272 * the scenario of video playback wherein RR is set based on the rate
5273 * requested by userspace.
5274 */
5275
5276/**
5277 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5278 * @intel_connector: eDP connector
5279 * @fixed_mode: preferred mode of panel
5280 *
5281 * This function is called only once at driver load to initialize basic
5282 * DRRS stuff.
5283 *
5284 * Returns:
5285 * Downclock mode if panel supports it, else return NULL.
5286 * DRRS support is determined by the presence of downclock mode (apart
5287 * from VBT setting).
5288 */
4f9db5b5 5289static struct drm_display_mode *
96178eeb
VK		 5290intel_dp_drrs_init(struct intel_connector *intel_connector,
5291 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5292{
5293 struct drm_connector *connector = &intel_connector->base;
96178eeb 5294 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5295 struct drm_i915_private *dev_priv = dev->dev_private;
5296 struct drm_display_mode *downclock_mode = NULL;
5297
9da7d693
DV		 5298 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5299 mutex_init(&dev_priv->drrs.mutex);
5300
4f9db5b5
PB		 5301 if (INTEL_INFO(dev)->gen <= 6) {
5302 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5303 return NULL;
5304 }
5305
5306 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5307 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5308 return NULL;
5309 }
5310
5311 downclock_mode = intel_find_panel_downclock
5312 (dev, fixed_mode, connector);
5313
5314 if (!downclock_mode) {
a1d26342 5315 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5316 return NULL;
5317 }
5318
96178eeb 5319 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5320
96178eeb 5321 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5322 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5323 return downclock_mode;
5324}
5325
ed92f0b2 5326static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5327 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5328{
5329 struct drm_connector *connector = &intel_connector->base;
5330 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5331 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5332 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5333 struct drm_i915_private *dev_priv = dev->dev_private;
5334 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5335 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5336 bool has_dpcd;
5337 struct drm_display_mode *scan;
5338 struct edid *edid;
6517d273 5339 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5340
5341 if (!is_edp(intel_dp))
5342 return true;
5343
97a824e1
ID		 5344 /*
5345 * On IBX/CPT we may get here with LVDS already registered. Since the
5346 * driver uses the only internal power sequencer available for both
5347 * eDP and LVDS bail out early in this case to prevent interfering
5348 * with an already powered-on LVDS power sequencer.
5349 */
5350 if (intel_get_lvds_encoder(dev)) {
5351 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5352 DRM_INFO("LVDS was detected, not registering eDP\n");
5353
5354 return false;
5355 }
5356
49e6bc51 5357 pps_lock(intel_dp);
b4d06ede
ID		 5358
5359 intel_dp_init_panel_power_timestamps(intel_dp);
5360
5361 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5362 vlv_initial_power_sequencer_setup(intel_dp);
5363 } else {
5364 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5365 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5366 }
5367
49e6bc51 5368 intel_edp_panel_vdd_sanitize(intel_dp);
b4d06ede 5369
49e6bc51 5370 pps_unlock(intel_dp);
63635217 5371
ed92f0b2 5372 /* Cache DPCD and EDID for edp. */
ed92f0b2 5373 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5374
5375 if (has_dpcd) {
5376 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5377 dev_priv->no_aux_handshake =
5378 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5379 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5380 } else {
5381 /* if this fails, presume the device is a ghost */
5382 DRM_INFO("failed to retrieve link info, disabling eDP\n");
b4d06ede 5383 goto out_vdd_off;
ed92f0b2
PZ		 5384 }
5385
060c8778 5386 mutex_lock(&dev->mode_config.mutex);
0b99836f 5387 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5388 if (edid) {
5389 if (drm_add_edid_modes(connector, edid)) {
5390 drm_mode_connector_update_edid_property(connector,
5391 edid);
5392 drm_edid_to_eld(connector, edid);
5393 } else {
5394 kfree(edid);
5395 edid = ERR_PTR(-EINVAL);
5396 }
5397 } else {
5398 edid = ERR_PTR(-ENOENT);
5399 }
5400 intel_connector->edid = edid;
5401
5402 /* prefer fixed mode from EDID if available */
5403 list_for_each_entry(scan, &connector->probed_modes, head) {
5404 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5405 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5406 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5407 intel_connector, fixed_mode);
ed92f0b2
PZ		 5408 break;
5409 }
5410 }
5411
5412 /* fallback to VBT if available for eDP */
5413 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5414 fixed_mode = drm_mode_duplicate(dev,
5415 dev_priv->vbt.lfp_lvds_vbt_mode);
df457245 5416 if (fixed_mode) {
ed92f0b2 5417 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
df457245
VS		 5418 connector->display_info.width_mm = fixed_mode->width_mm;
5419 connector->display_info.height_mm = fixed_mode->height_mm;
5420 }
ed92f0b2 5421 }
060c8778 5422 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5423
666a4537 5424 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
01527b31
CT		 5425 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5426 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5427
5428 /*
5429 * Figure out the current pipe for the initial backlight setup.
5430 * If the current pipe isn't valid, try the PPS pipe, and if that
5431 * fails just assume pipe A.
5432 */
5433 if (IS_CHERRYVIEW(dev))
5434 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5435 else
5436 pipe = PORT_TO_PIPE(intel_dp->DP);
5437
5438 if (pipe != PIPE_A && pipe != PIPE_B)
5439 pipe = intel_dp->pps_pipe;
5440
5441 if (pipe != PIPE_A && pipe != PIPE_B)
5442 pipe = PIPE_A;
5443
5444 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5445 pipe_name(pipe));
01527b31
CT		 5446 }
5447
4f9db5b5 5448 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5507faeb 5449 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6517d273 5450 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5451
5452 return true;
b4d06ede
ID		 5453
5454out_vdd_off:
5455 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5456 /*
5457 * vdd might still be enabled do to the delayed vdd off.
5458 * Make sure vdd is actually turned off here.
5459 */
5460 pps_lock(intel_dp);
5461 edp_panel_vdd_off_sync(intel_dp);
5462 pps_unlock(intel_dp);
5463
5464 return false;
ed92f0b2
PZ		 5465}
5466
16c25533 5467bool
f0fec3f2
PZ		 5468intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5469 struct intel_connector *intel_connector)
a4fc5ed6 5470{
f0fec3f2
PZ		 5471 struct drm_connector *connector = &intel_connector->base;
5472 struct intel_dp *intel_dp = &intel_dig_port->dp;
5473 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5474 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5475 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5476 enum port port = intel_dig_port->port;
a121f4e5 5477 int type, ret;
a4fc5ed6 5478
ccb1a831
VS		 5479 if (WARN(intel_dig_port->max_lanes < 1,
5480 "Not enough lanes (%d) for DP on port %c\n",
5481 intel_dig_port->max_lanes, port_name(port)))
5482 return false;
5483
a4a5d2f8
VS		 5484 intel_dp->pps_pipe = INVALID_PIPE;
5485
ec5b01dd 5486 /* intel_dp vfuncs */
b6b5e383
DL		 5487 if (INTEL_INFO(dev)->gen >= 9)
5488 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
ec5b01dd
DL		 5489 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5490 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5491 else if (HAS_PCH_SPLIT(dev))
5492 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5493 else
6ffb1be7 5494 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
ec5b01dd 5495
b9ca5fad
DL		 5496 if (INTEL_INFO(dev)->gen >= 9)
5497 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5498 else
6ffb1be7 5499 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
153b1100 5500
ad64217b
ACO		 5501 if (HAS_DDI(dev))
5502 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5503
0767935e
DV		 5504 /* Preserve the current hw state. */
5505 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5506 intel_dp->attached_connector = intel_connector;
3d3dc149 5507
3b32a35b 5508 if (intel_dp_is_edp(dev, port))
b329530c 5509 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5510 else
5511 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5512
f7d24902
ID		 5513 /*
5514 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5515 * for DP the encoder type can be set by the caller to
5516 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5517 */
5518 if (type == DRM_MODE_CONNECTOR_eDP)
5519 intel_encoder->type = INTEL_OUTPUT_EDP;
5520
c17ed5b5 5521 /* eDP only on port B and/or C on vlv/chv */
666a4537
WB		 5522 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5523 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
c17ed5b5
VS		 5524 return false;
5525
e7281eab
ID		 5526 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5527 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5528 port_name(port));
5529
b329530c 5530 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5531 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5532
a4fc5ed6
KP		 5533 connector->interlace_allowed = true;
5534 connector->doublescan_allowed = 0;
5535
f0fec3f2 5536 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5537 edp_panel_vdd_work);
a4fc5ed6 5538
df0e9248 5539 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5540 drm_connector_register(connector);
a4fc5ed6 5541
affa9354 5542 if (HAS_DDI(dev))
bcbc889b
PZ		 5543 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5544 else
5545 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5546 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5547
0b99836f 5548 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5549 switch (port) {
5550 case PORT_A:
1d843f9d 5551 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5552 break;
5553 case PORT_B:
1d843f9d 5554 intel_encoder->hpd_pin = HPD_PORT_B;
e87a005d 5555 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
cf1d5883 5556 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5557 break;
5558 case PORT_C:
1d843f9d 5559 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5560 break;
5561 case PORT_D:
1d843f9d 5562 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30 5563 break;
26951caf
XZ		 5564 case PORT_E:
5565 intel_encoder->hpd_pin = HPD_PORT_E;
5566 break;
ab9d7c30 5567 default:
ad1c0b19 5568 BUG();
5eb08b69
ZW		 5569 }
5570
a121f4e5
VS		 5571 ret = intel_dp_aux_init(intel_dp, intel_connector);
5572 if (ret)
5573 goto fail;
c1f05264 5574
0e32b39c 5575 /* init MST on ports that can support it */
0c9b3715
JN		 5576 if (HAS_DP_MST(dev) &&
5577 (port == PORT_B || port == PORT_C || port == PORT_D))
5578 intel_dp_mst_encoder_init(intel_dig_port,
5579 intel_connector->base.base.id);
0e32b39c 5580
36b5f425 5581 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
a121f4e5
VS		 5582 intel_dp_aux_fini(intel_dp);
5583 intel_dp_mst_encoder_cleanup(intel_dig_port);
5584 goto fail;
b2f246a8 5585 }
32f9d658 5586
f684960e
CW		 5587 intel_dp_add_properties(intel_dp, connector);
5588
a4fc5ed6
KP		 5589 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5590 * 0xd. Failure to do so will result in spurious interrupts being
5591 * generated on the port when a cable is not attached.
5592 */
5593 if (IS_G4X(dev) && !IS_GM45(dev)) {
5594 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5595 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5596 }
16c25533 5597
aa7471d2
JN		 5598 i915_debugfs_connector_add(connector);
5599
16c25533 5600 return true;
a121f4e5
VS		 5601
5602fail:
a121f4e5
VS		 5603 drm_connector_unregister(connector);
5604 drm_connector_cleanup(connector);
5605
5606 return false;
a4fc5ed6 5607}
f0fec3f2 5608
457c52d8
CW		 5609bool intel_dp_init(struct drm_device *dev,
5610 i915_reg_t output_reg,
5611 enum port port)
f0fec3f2 5612{
13cf5504 5613 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5614 struct intel_digital_port *intel_dig_port;
5615 struct intel_encoder *intel_encoder;
5616 struct drm_encoder *encoder;
5617 struct intel_connector *intel_connector;
5618
b14c5679 5619 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2 5620 if (!intel_dig_port)
457c52d8 5621 return false;
f0fec3f2 5622
08d9bc92 5623 intel_connector = intel_connector_alloc();
11aee0f6
SM		 5624 if (!intel_connector)
5625 goto err_connector_alloc;
f0fec3f2
PZ		 5626
5627 intel_encoder = &intel_dig_port->base;
5628 encoder = &intel_encoder->base;
5629
893da0c9 5630 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
580d8ed5 5631 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
893da0c9 5632 goto err_encoder_init;
f0fec3f2 5633
5bfe2ac0 5634 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5635 intel_encoder->disable = intel_disable_dp;
00c09d70 5636 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5637 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5638 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5639 if (IS_CHERRYVIEW(dev)) {
9197c88b 5640 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5641 intel_encoder->pre_enable = chv_pre_enable_dp;
5642 intel_encoder->enable = vlv_enable_dp;
580d3811 5643 intel_encoder->post_disable = chv_post_disable_dp;
d6db995f 5644 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
e4a1d846 5645 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5646 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5647 intel_encoder->pre_enable = vlv_pre_enable_dp;
5648 intel_encoder->enable = vlv_enable_dp;
49277c31 5649 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5650 } else {
ecff4f3b
JN		 5651 intel_encoder->pre_enable = g4x_pre_enable_dp;
5652 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5653 if (INTEL_INFO(dev)->gen >= 5)
5654 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5655 }
f0fec3f2 5656
174edf1f 5657 intel_dig_port->port = port;
f0fec3f2 5658 intel_dig_port->dp.output_reg = output_reg;
ccb1a831 5659 intel_dig_port->max_lanes = 4;
f0fec3f2 5660
00c09d70 5661 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5662 if (IS_CHERRYVIEW(dev)) {
5663 if (port == PORT_D)
5664 intel_encoder->crtc_mask = 1 << 2;
5665 else
5666 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5667 } else {
5668 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5669 }
bc079e8b 5670 intel_encoder->cloneable = 0;
f0fec3f2 5671
13cf5504 5672 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 5673 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 5674
11aee0f6
SM		 5675 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5676 goto err_init_connector;
5677
457c52d8 5678 return true;
11aee0f6
SM		 5679
5680err_init_connector:
5681 drm_encoder_cleanup(encoder);
893da0c9 5682err_encoder_init:
11aee0f6
SM		 5683 kfree(intel_connector);
5684err_connector_alloc:
5685 kfree(intel_dig_port);
457c52d8 5686 return false;
f0fec3f2 5687}
0e32b39c
DA		 5688
5689void intel_dp_mst_suspend(struct drm_device *dev)
5690{
5691 struct drm_i915_private *dev_priv = dev->dev_private;
5692 int i;
5693
5694 /* disable MST */
5695 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5696 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 5697 if (!intel_dig_port)
5698 continue;
5699
5700 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5701 if (!intel_dig_port->dp.can_mst)
5702 continue;
5703 if (intel_dig_port->dp.is_mst)
5704 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5705 }
5706 }
5707}
5708
5709void intel_dp_mst_resume(struct drm_device *dev)
5710{
5711 struct drm_i915_private *dev_priv = dev->dev_private;
5712 int i;
5713
5714 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5715 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 5716 if (!intel_dig_port)
5717 continue;
5718 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5719 int ret;
5720
5721 if (!intel_dig_port->dp.can_mst)
5722 continue;
5723
5724 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5725 if (ret != 0) {
5726 intel_dp_check_mst_status(&intel_dig_port->dp);
5727 }
5728 }
5729 }
5730}
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