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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
a4fc5ed6 KP |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "drm_crtc_helper.h" | |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
ab2c0672 | 37 | #include "drm_dp_helper.h" |
a4fc5ed6 | 38 | |
ae266c98 | 39 | |
a4fc5ed6 KP |
40 | #define DP_LINK_STATUS_SIZE 6 |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) | |
42 | ||
43 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
44 | ||
ea5b213a CW |
45 | struct intel_dp { |
46 | struct intel_encoder base; | |
a4fc5ed6 KP |
47 | uint32_t output_reg; |
48 | uint32_t DP; | |
49 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
a4fc5ed6 | 50 | bool has_audio; |
c8110e52 | 51 | int dpms_mode; |
a4fc5ed6 KP |
52 | uint8_t link_bw; |
53 | uint8_t lane_count; | |
54 | uint8_t dpcd[4]; | |
a4fc5ed6 KP |
55 | struct i2c_adapter adapter; |
56 | struct i2c_algo_dp_aux_data algo; | |
f0917379 | 57 | bool is_pch_edp; |
33a34e4e JB |
58 | uint8_t train_set[4]; |
59 | uint8_t link_status[DP_LINK_STATUS_SIZE]; | |
a4fc5ed6 KP |
60 | }; |
61 | ||
cfcb0fc9 JB |
62 | /** |
63 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
64 | * @intel_dp: DP struct | |
65 | * | |
66 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
67 | * will return true, and false otherwise. | |
68 | */ | |
69 | static bool is_edp(struct intel_dp *intel_dp) | |
70 | { | |
71 | return intel_dp->base.type == INTEL_OUTPUT_EDP; | |
72 | } | |
73 | ||
74 | /** | |
75 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? | |
76 | * @intel_dp: DP struct | |
77 | * | |
78 | * Returns true if the given DP struct corresponds to a PCH DP port attached | |
79 | * to an eDP panel, false otherwise. Helpful for determining whether we | |
80 | * may need FDI resources for a given DP output or not. | |
81 | */ | |
82 | static bool is_pch_edp(struct intel_dp *intel_dp) | |
83 | { | |
84 | return intel_dp->is_pch_edp; | |
85 | } | |
86 | ||
ea5b213a CW |
87 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
88 | { | |
4ef69c7a | 89 | return container_of(encoder, struct intel_dp, base.base); |
ea5b213a | 90 | } |
a4fc5ed6 | 91 | |
df0e9248 CW |
92 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
93 | { | |
94 | return container_of(intel_attached_encoder(connector), | |
95 | struct intel_dp, base); | |
96 | } | |
97 | ||
814948ad JB |
98 | /** |
99 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? | |
100 | * @encoder: DRM encoder | |
101 | * | |
102 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed | |
103 | * by intel_display.c. | |
104 | */ | |
105 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) | |
106 | { | |
107 | struct intel_dp *intel_dp; | |
108 | ||
109 | if (!encoder) | |
110 | return false; | |
111 | ||
112 | intel_dp = enc_to_intel_dp(encoder); | |
113 | ||
114 | return is_pch_edp(intel_dp); | |
115 | } | |
116 | ||
33a34e4e JB |
117 | static void intel_dp_start_link_train(struct intel_dp *intel_dp); |
118 | static void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
ea5b213a | 119 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
a4fc5ed6 | 120 | |
32f9d658 | 121 | void |
21d40d37 | 122 | intel_edp_link_config (struct intel_encoder *intel_encoder, |
ea5b213a | 123 | int *lane_num, int *link_bw) |
32f9d658 | 124 | { |
ea5b213a | 125 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
32f9d658 | 126 | |
ea5b213a CW |
127 | *lane_num = intel_dp->lane_count; |
128 | if (intel_dp->link_bw == DP_LINK_BW_1_62) | |
32f9d658 | 129 | *link_bw = 162000; |
ea5b213a | 130 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
32f9d658 ZW |
131 | *link_bw = 270000; |
132 | } | |
133 | ||
a4fc5ed6 | 134 | static int |
ea5b213a | 135 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
a4fc5ed6 | 136 | { |
a4fc5ed6 KP |
137 | int max_lane_count = 4; |
138 | ||
ea5b213a CW |
139 | if (intel_dp->dpcd[0] >= 0x11) { |
140 | max_lane_count = intel_dp->dpcd[2] & 0x1f; | |
a4fc5ed6 KP |
141 | switch (max_lane_count) { |
142 | case 1: case 2: case 4: | |
143 | break; | |
144 | default: | |
145 | max_lane_count = 4; | |
146 | } | |
147 | } | |
148 | return max_lane_count; | |
149 | } | |
150 | ||
151 | static int | |
ea5b213a | 152 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 153 | { |
ea5b213a | 154 | int max_link_bw = intel_dp->dpcd[1]; |
a4fc5ed6 KP |
155 | |
156 | switch (max_link_bw) { | |
157 | case DP_LINK_BW_1_62: | |
158 | case DP_LINK_BW_2_7: | |
159 | break; | |
160 | default: | |
161 | max_link_bw = DP_LINK_BW_1_62; | |
162 | break; | |
163 | } | |
164 | return max_link_bw; | |
165 | } | |
166 | ||
167 | static int | |
168 | intel_dp_link_clock(uint8_t link_bw) | |
169 | { | |
170 | if (link_bw == DP_LINK_BW_2_7) | |
171 | return 270000; | |
172 | else | |
173 | return 162000; | |
174 | } | |
175 | ||
176 | /* I think this is a fiction */ | |
177 | static int | |
ea5b213a | 178 | intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) |
a4fc5ed6 | 179 | { |
885a5fb5 ZW |
180 | struct drm_i915_private *dev_priv = dev->dev_private; |
181 | ||
4d926461 | 182 | if (is_edp(intel_dp)) |
5ceb0f9b | 183 | return (pixel_clock * dev_priv->edp.bpp + 7) / 8; |
885a5fb5 ZW |
184 | else |
185 | return pixel_clock * 3; | |
a4fc5ed6 KP |
186 | } |
187 | ||
fe27d53e DA |
188 | static int |
189 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
190 | { | |
191 | return (max_link_clock * max_lanes * 8) / 10; | |
192 | } | |
193 | ||
a4fc5ed6 KP |
194 | static int |
195 | intel_dp_mode_valid(struct drm_connector *connector, | |
196 | struct drm_display_mode *mode) | |
197 | { | |
df0e9248 | 198 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
7de56f43 ZY |
199 | struct drm_device *dev = connector->dev; |
200 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a CW |
201 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
202 | int max_lanes = intel_dp_max_lane_count(intel_dp); | |
a4fc5ed6 | 203 | |
4d926461 | 204 | if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { |
7de56f43 ZY |
205 | if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) |
206 | return MODE_PANEL; | |
207 | ||
208 | if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay) | |
209 | return MODE_PANEL; | |
210 | } | |
211 | ||
fe27d53e DA |
212 | /* only refuse the mode on non eDP since we have seen some wierd eDP panels |
213 | which are outside spec tolerances but somehow work by magic */ | |
cfcb0fc9 | 214 | if (!is_edp(intel_dp) && |
ea5b213a | 215 | (intel_dp_link_required(connector->dev, intel_dp, mode->clock) |
fe27d53e | 216 | > intel_dp_max_data_rate(max_link_clock, max_lanes))) |
a4fc5ed6 KP |
217 | return MODE_CLOCK_HIGH; |
218 | ||
219 | if (mode->clock < 10000) | |
220 | return MODE_CLOCK_LOW; | |
221 | ||
222 | return MODE_OK; | |
223 | } | |
224 | ||
225 | static uint32_t | |
226 | pack_aux(uint8_t *src, int src_bytes) | |
227 | { | |
228 | int i; | |
229 | uint32_t v = 0; | |
230 | ||
231 | if (src_bytes > 4) | |
232 | src_bytes = 4; | |
233 | for (i = 0; i < src_bytes; i++) | |
234 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
235 | return v; | |
236 | } | |
237 | ||
238 | static void | |
239 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
240 | { | |
241 | int i; | |
242 | if (dst_bytes > 4) | |
243 | dst_bytes = 4; | |
244 | for (i = 0; i < dst_bytes; i++) | |
245 | dst[i] = src >> ((3-i) * 8); | |
246 | } | |
247 | ||
fb0f8fbf KP |
248 | /* hrawclock is 1/4 the FSB frequency */ |
249 | static int | |
250 | intel_hrawclk(struct drm_device *dev) | |
251 | { | |
252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
253 | uint32_t clkcfg; | |
254 | ||
255 | clkcfg = I915_READ(CLKCFG); | |
256 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
257 | case CLKCFG_FSB_400: | |
258 | return 100; | |
259 | case CLKCFG_FSB_533: | |
260 | return 133; | |
261 | case CLKCFG_FSB_667: | |
262 | return 166; | |
263 | case CLKCFG_FSB_800: | |
264 | return 200; | |
265 | case CLKCFG_FSB_1067: | |
266 | return 266; | |
267 | case CLKCFG_FSB_1333: | |
268 | return 333; | |
269 | /* these two are just a guess; one of them might be right */ | |
270 | case CLKCFG_FSB_1600: | |
271 | case CLKCFG_FSB_1600_ALT: | |
272 | return 400; | |
273 | default: | |
274 | return 133; | |
275 | } | |
276 | } | |
277 | ||
a4fc5ed6 | 278 | static int |
ea5b213a | 279 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
280 | uint8_t *send, int send_bytes, |
281 | uint8_t *recv, int recv_size) | |
282 | { | |
ea5b213a | 283 | uint32_t output_reg = intel_dp->output_reg; |
4ef69c7a | 284 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 KP |
285 | struct drm_i915_private *dev_priv = dev->dev_private; |
286 | uint32_t ch_ctl = output_reg + 0x10; | |
287 | uint32_t ch_data = ch_ctl + 4; | |
288 | int i; | |
289 | int recv_bytes; | |
a4fc5ed6 | 290 | uint32_t status; |
fb0f8fbf | 291 | uint32_t aux_clock_divider; |
e3421a18 | 292 | int try, precharge; |
a4fc5ed6 KP |
293 | |
294 | /* The clock divider is based off the hrawclk, | |
fb0f8fbf KP |
295 | * and would like to run at 2MHz. So, take the |
296 | * hrawclk value and divide by 2 and use that | |
6176b8f9 JB |
297 | * |
298 | * Note that PCH attached eDP panels should use a 125MHz input | |
299 | * clock divider. | |
a4fc5ed6 | 300 | */ |
cfcb0fc9 | 301 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
e3421a18 ZW |
302 | if (IS_GEN6(dev)) |
303 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ | |
304 | else | |
305 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
306 | } else if (HAS_PCH_SPLIT(dev)) | |
f2b115e6 | 307 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
5eb08b69 ZW |
308 | else |
309 | aux_clock_divider = intel_hrawclk(dev) / 2; | |
310 | ||
e3421a18 ZW |
311 | if (IS_GEN6(dev)) |
312 | precharge = 3; | |
313 | else | |
314 | precharge = 5; | |
315 | ||
4f7f7b7e CW |
316 | if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { |
317 | DRM_ERROR("dp_aux_ch not started status 0x%08x\n", | |
318 | I915_READ(ch_ctl)); | |
319 | return -EBUSY; | |
320 | } | |
321 | ||
fb0f8fbf KP |
322 | /* Must try at least 3 times according to DP spec */ |
323 | for (try = 0; try < 5; try++) { | |
324 | /* Load the send data into the aux channel data registers */ | |
4f7f7b7e CW |
325 | for (i = 0; i < send_bytes; i += 4) |
326 | I915_WRITE(ch_data + i, | |
327 | pack_aux(send + i, send_bytes - i)); | |
fb0f8fbf KP |
328 | |
329 | /* Send the command and wait for it to complete */ | |
4f7f7b7e CW |
330 | I915_WRITE(ch_ctl, |
331 | DP_AUX_CH_CTL_SEND_BUSY | | |
332 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
333 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
334 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
335 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
336 | DP_AUX_CH_CTL_DONE | | |
337 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
338 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
fb0f8fbf | 339 | for (;;) { |
fb0f8fbf KP |
340 | status = I915_READ(ch_ctl); |
341 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
342 | break; | |
4f7f7b7e | 343 | udelay(100); |
fb0f8fbf KP |
344 | } |
345 | ||
346 | /* Clear done status and any errors */ | |
4f7f7b7e CW |
347 | I915_WRITE(ch_ctl, |
348 | status | | |
349 | DP_AUX_CH_CTL_DONE | | |
350 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
351 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
352 | if (status & DP_AUX_CH_CTL_DONE) | |
a4fc5ed6 KP |
353 | break; |
354 | } | |
355 | ||
a4fc5ed6 | 356 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 357 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
a5b3da54 | 358 | return -EBUSY; |
a4fc5ed6 KP |
359 | } |
360 | ||
361 | /* Check for timeout or receive error. | |
362 | * Timeouts occur when the sink is not connected | |
363 | */ | |
a5b3da54 | 364 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 365 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
a5b3da54 KP |
366 | return -EIO; |
367 | } | |
1ae8c0a5 KP |
368 | |
369 | /* Timeouts occur when the device isn't connected, so they're | |
370 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 371 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 372 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
a5b3da54 | 373 | return -ETIMEDOUT; |
a4fc5ed6 KP |
374 | } |
375 | ||
376 | /* Unload any bytes sent back from the other side */ | |
377 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
378 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
379 | if (recv_bytes > recv_size) |
380 | recv_bytes = recv_size; | |
381 | ||
4f7f7b7e CW |
382 | for (i = 0; i < recv_bytes; i += 4) |
383 | unpack_aux(I915_READ(ch_data + i), | |
384 | recv + i, recv_bytes - i); | |
a4fc5ed6 KP |
385 | |
386 | return recv_bytes; | |
387 | } | |
388 | ||
389 | /* Write data to the aux channel in native mode */ | |
390 | static int | |
ea5b213a | 391 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
392 | uint16_t address, uint8_t *send, int send_bytes) |
393 | { | |
394 | int ret; | |
395 | uint8_t msg[20]; | |
396 | int msg_bytes; | |
397 | uint8_t ack; | |
398 | ||
399 | if (send_bytes > 16) | |
400 | return -1; | |
401 | msg[0] = AUX_NATIVE_WRITE << 4; | |
402 | msg[1] = address >> 8; | |
eebc863e | 403 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
404 | msg[3] = send_bytes - 1; |
405 | memcpy(&msg[4], send, send_bytes); | |
406 | msg_bytes = send_bytes + 4; | |
407 | for (;;) { | |
ea5b213a | 408 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
409 | if (ret < 0) |
410 | return ret; | |
411 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
412 | break; | |
413 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
414 | udelay(100); | |
415 | else | |
a5b3da54 | 416 | return -EIO; |
a4fc5ed6 KP |
417 | } |
418 | return send_bytes; | |
419 | } | |
420 | ||
421 | /* Write a single byte to the aux channel in native mode */ | |
422 | static int | |
ea5b213a | 423 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
424 | uint16_t address, uint8_t byte) |
425 | { | |
ea5b213a | 426 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
427 | } |
428 | ||
429 | /* read bytes from a native aux channel */ | |
430 | static int | |
ea5b213a | 431 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
432 | uint16_t address, uint8_t *recv, int recv_bytes) |
433 | { | |
434 | uint8_t msg[4]; | |
435 | int msg_bytes; | |
436 | uint8_t reply[20]; | |
437 | int reply_bytes; | |
438 | uint8_t ack; | |
439 | int ret; | |
440 | ||
441 | msg[0] = AUX_NATIVE_READ << 4; | |
442 | msg[1] = address >> 8; | |
443 | msg[2] = address & 0xff; | |
444 | msg[3] = recv_bytes - 1; | |
445 | ||
446 | msg_bytes = 4; | |
447 | reply_bytes = recv_bytes + 1; | |
448 | ||
449 | for (;;) { | |
ea5b213a | 450 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 451 | reply, reply_bytes); |
a5b3da54 KP |
452 | if (ret == 0) |
453 | return -EPROTO; | |
454 | if (ret < 0) | |
a4fc5ed6 KP |
455 | return ret; |
456 | ack = reply[0]; | |
457 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
458 | memcpy(recv, reply + 1, ret - 1); | |
459 | return ret - 1; | |
460 | } | |
461 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
462 | udelay(100); | |
463 | else | |
a5b3da54 | 464 | return -EIO; |
a4fc5ed6 KP |
465 | } |
466 | } | |
467 | ||
468 | static int | |
ab2c0672 DA |
469 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
470 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 471 | { |
ab2c0672 | 472 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
473 | struct intel_dp *intel_dp = container_of(adapter, |
474 | struct intel_dp, | |
475 | adapter); | |
ab2c0672 DA |
476 | uint16_t address = algo_data->address; |
477 | uint8_t msg[5]; | |
478 | uint8_t reply[2]; | |
479 | int msg_bytes; | |
480 | int reply_bytes; | |
481 | int ret; | |
482 | ||
483 | /* Set up the command byte */ | |
484 | if (mode & MODE_I2C_READ) | |
485 | msg[0] = AUX_I2C_READ << 4; | |
486 | else | |
487 | msg[0] = AUX_I2C_WRITE << 4; | |
488 | ||
489 | if (!(mode & MODE_I2C_STOP)) | |
490 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 491 | |
ab2c0672 DA |
492 | msg[1] = address >> 8; |
493 | msg[2] = address; | |
494 | ||
495 | switch (mode) { | |
496 | case MODE_I2C_WRITE: | |
497 | msg[3] = 0; | |
498 | msg[4] = write_byte; | |
499 | msg_bytes = 5; | |
500 | reply_bytes = 1; | |
501 | break; | |
502 | case MODE_I2C_READ: | |
503 | msg[3] = 0; | |
504 | msg_bytes = 4; | |
505 | reply_bytes = 2; | |
506 | break; | |
507 | default: | |
508 | msg_bytes = 3; | |
509 | reply_bytes = 1; | |
510 | break; | |
511 | } | |
512 | ||
513 | for (;;) { | |
ea5b213a | 514 | ret = intel_dp_aux_ch(intel_dp, |
ab2c0672 DA |
515 | msg, msg_bytes, |
516 | reply, reply_bytes); | |
517 | if (ret < 0) { | |
3ff99164 | 518 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
519 | return ret; |
520 | } | |
521 | switch (reply[0] & AUX_I2C_REPLY_MASK) { | |
522 | case AUX_I2C_REPLY_ACK: | |
523 | if (mode == MODE_I2C_READ) { | |
524 | *read_byte = reply[1]; | |
525 | } | |
526 | return reply_bytes - 1; | |
527 | case AUX_I2C_REPLY_NACK: | |
3ff99164 | 528 | DRM_DEBUG_KMS("aux_ch nack\n"); |
ab2c0672 DA |
529 | return -EREMOTEIO; |
530 | case AUX_I2C_REPLY_DEFER: | |
3ff99164 | 531 | DRM_DEBUG_KMS("aux_ch defer\n"); |
ab2c0672 DA |
532 | udelay(100); |
533 | break; | |
534 | default: | |
535 | DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]); | |
536 | return -EREMOTEIO; | |
537 | } | |
538 | } | |
a4fc5ed6 KP |
539 | } |
540 | ||
541 | static int | |
ea5b213a | 542 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 543 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 544 | { |
d54e9d28 | 545 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
546 | intel_dp->algo.running = false; |
547 | intel_dp->algo.address = 0; | |
548 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
549 | ||
550 | memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); | |
551 | intel_dp->adapter.owner = THIS_MODULE; | |
552 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
553 | strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); | |
554 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; | |
555 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
556 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
557 | ||
558 | return i2c_dp_aux_add_bus(&intel_dp->adapter); | |
a4fc5ed6 KP |
559 | } |
560 | ||
561 | static bool | |
562 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
563 | struct drm_display_mode *adjusted_mode) | |
564 | { | |
0d3a1bee ZY |
565 | struct drm_device *dev = encoder->dev; |
566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 567 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4fc5ed6 | 568 | int lane_count, clock; |
ea5b213a CW |
569 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
570 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; | |
a4fc5ed6 KP |
571 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
572 | ||
4d926461 | 573 | if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { |
1d8e1c75 CW |
574 | intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); |
575 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, | |
576 | mode, adjusted_mode); | |
0d3a1bee ZY |
577 | /* |
578 | * the mode->clock is used to calculate the Data&Link M/N | |
579 | * of the pipe. For the eDP the fixed clock should be used. | |
580 | */ | |
581 | mode->clock = dev_priv->panel_fixed_mode->clock; | |
582 | } | |
583 | ||
869184a6 JB |
584 | /* Just use VBT values for eDP */ |
585 | if (is_edp(intel_dp)) { | |
586 | intel_dp->lane_count = dev_priv->edp.lanes; | |
587 | intel_dp->link_bw = dev_priv->edp.rate; | |
588 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
589 | DRM_DEBUG_KMS("eDP link bw %02x lane count %d clock %d\n", | |
590 | intel_dp->link_bw, intel_dp->lane_count, | |
591 | adjusted_mode->clock); | |
592 | return true; | |
593 | } | |
594 | ||
a4fc5ed6 KP |
595 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
596 | for (clock = 0; clock <= max_clock; clock++) { | |
fe27d53e | 597 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
a4fc5ed6 | 598 | |
ea5b213a | 599 | if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) |
885a5fb5 | 600 | <= link_avail) { |
ea5b213a CW |
601 | intel_dp->link_bw = bws[clock]; |
602 | intel_dp->lane_count = lane_count; | |
603 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
28c97730 ZY |
604 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
605 | "count %d clock %d\n", | |
ea5b213a | 606 | intel_dp->link_bw, intel_dp->lane_count, |
a4fc5ed6 KP |
607 | adjusted_mode->clock); |
608 | return true; | |
609 | } | |
610 | } | |
611 | } | |
fe27d53e | 612 | |
a4fc5ed6 KP |
613 | return false; |
614 | } | |
615 | ||
616 | struct intel_dp_m_n { | |
617 | uint32_t tu; | |
618 | uint32_t gmch_m; | |
619 | uint32_t gmch_n; | |
620 | uint32_t link_m; | |
621 | uint32_t link_n; | |
622 | }; | |
623 | ||
624 | static void | |
625 | intel_reduce_ratio(uint32_t *num, uint32_t *den) | |
626 | { | |
627 | while (*num > 0xffffff || *den > 0xffffff) { | |
628 | *num >>= 1; | |
629 | *den >>= 1; | |
630 | } | |
631 | } | |
632 | ||
633 | static void | |
36e83a18 | 634 | intel_dp_compute_m_n(int bpp, |
a4fc5ed6 KP |
635 | int nlanes, |
636 | int pixel_clock, | |
637 | int link_clock, | |
638 | struct intel_dp_m_n *m_n) | |
639 | { | |
640 | m_n->tu = 64; | |
36e83a18 | 641 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
a4fc5ed6 KP |
642 | m_n->gmch_n = link_clock * nlanes; |
643 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
644 | m_n->link_m = pixel_clock; | |
645 | m_n->link_n = link_clock; | |
646 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
647 | } | |
648 | ||
649 | void | |
650 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
651 | struct drm_display_mode *adjusted_mode) | |
652 | { | |
653 | struct drm_device *dev = crtc->dev; | |
654 | struct drm_mode_config *mode_config = &dev->mode_config; | |
55f78c43 | 655 | struct drm_encoder *encoder; |
a4fc5ed6 KP |
656 | struct drm_i915_private *dev_priv = dev->dev_private; |
657 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
36e83a18 | 658 | int lane_count = 4, bpp = 24; |
a4fc5ed6 KP |
659 | struct intel_dp_m_n m_n; |
660 | ||
661 | /* | |
21d40d37 | 662 | * Find the lane count in the intel_encoder private |
a4fc5ed6 | 663 | */ |
55f78c43 | 664 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
ea5b213a | 665 | struct intel_dp *intel_dp; |
a4fc5ed6 | 666 | |
d8201ab6 | 667 | if (encoder->crtc != crtc) |
a4fc5ed6 KP |
668 | continue; |
669 | ||
ea5b213a CW |
670 | intel_dp = enc_to_intel_dp(encoder); |
671 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
672 | lane_count = intel_dp->lane_count; | |
51190667 JB |
673 | break; |
674 | } else if (is_edp(intel_dp)) { | |
675 | lane_count = dev_priv->edp.lanes; | |
676 | bpp = dev_priv->edp.bpp; | |
a4fc5ed6 KP |
677 | break; |
678 | } | |
679 | } | |
680 | ||
681 | /* | |
682 | * Compute the GMCH and Link ratios. The '3' here is | |
683 | * the number of bytes_per_pixel post-LUT, which we always | |
684 | * set up for 8-bits of R/G/B, or 3 bytes total. | |
685 | */ | |
36e83a18 | 686 | intel_dp_compute_m_n(bpp, lane_count, |
a4fc5ed6 KP |
687 | mode->clock, adjusted_mode->clock, &m_n); |
688 | ||
c619eed4 | 689 | if (HAS_PCH_SPLIT(dev)) { |
5eb08b69 ZW |
690 | if (intel_crtc->pipe == 0) { |
691 | I915_WRITE(TRANSA_DATA_M1, | |
692 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
693 | m_n.gmch_m); | |
694 | I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n); | |
695 | I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m); | |
696 | I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n); | |
697 | } else { | |
698 | I915_WRITE(TRANSB_DATA_M1, | |
699 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
700 | m_n.gmch_m); | |
701 | I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n); | |
702 | I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m); | |
703 | I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n); | |
704 | } | |
a4fc5ed6 | 705 | } else { |
5eb08b69 ZW |
706 | if (intel_crtc->pipe == 0) { |
707 | I915_WRITE(PIPEA_GMCH_DATA_M, | |
708 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
709 | m_n.gmch_m); | |
710 | I915_WRITE(PIPEA_GMCH_DATA_N, | |
711 | m_n.gmch_n); | |
712 | I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m); | |
713 | I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n); | |
714 | } else { | |
715 | I915_WRITE(PIPEB_GMCH_DATA_M, | |
716 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
717 | m_n.gmch_m); | |
718 | I915_WRITE(PIPEB_GMCH_DATA_N, | |
719 | m_n.gmch_n); | |
720 | I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m); | |
721 | I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n); | |
722 | } | |
a4fc5ed6 KP |
723 | } |
724 | } | |
725 | ||
726 | static void | |
727 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
728 | struct drm_display_mode *adjusted_mode) | |
729 | { | |
e3421a18 | 730 | struct drm_device *dev = encoder->dev; |
ea5b213a | 731 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4ef69c7a | 732 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
a4fc5ed6 KP |
733 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
734 | ||
ea5b213a | 735 | intel_dp->DP = (DP_VOLTAGE_0_4 | |
9c9e7927 AJ |
736 | DP_PRE_EMPHASIS_0); |
737 | ||
738 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
ea5b213a | 739 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
9c9e7927 | 740 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
ea5b213a | 741 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
a4fc5ed6 | 742 | |
cfcb0fc9 | 743 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
ea5b213a | 744 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3421a18 | 745 | else |
ea5b213a | 746 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
a4fc5ed6 | 747 | |
ea5b213a | 748 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 749 | case 1: |
ea5b213a | 750 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
751 | break; |
752 | case 2: | |
ea5b213a | 753 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
754 | break; |
755 | case 4: | |
ea5b213a | 756 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
757 | break; |
758 | } | |
ea5b213a CW |
759 | if (intel_dp->has_audio) |
760 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; | |
a4fc5ed6 | 761 | |
ea5b213a CW |
762 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
763 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
764 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
a4fc5ed6 KP |
765 | |
766 | /* | |
9962c925 | 767 | * Check for DPCD version > 1.1 and enhanced framing support |
a4fc5ed6 | 768 | */ |
ea5b213a CW |
769 | if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) { |
770 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; | |
771 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
a4fc5ed6 KP |
772 | } |
773 | ||
e3421a18 ZW |
774 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ |
775 | if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) | |
ea5b213a | 776 | intel_dp->DP |= DP_PIPEB_SELECT; |
32f9d658 | 777 | |
895692be | 778 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
32f9d658 | 779 | /* don't miss out required setting for eDP */ |
ea5b213a | 780 | intel_dp->DP |= DP_PLL_ENABLE; |
32f9d658 | 781 | if (adjusted_mode->clock < 200000) |
ea5b213a | 782 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
32f9d658 | 783 | else |
ea5b213a | 784 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
32f9d658 | 785 | } |
a4fc5ed6 KP |
786 | } |
787 | ||
7eaf5547 | 788 | /* Returns true if the panel was already on when called */ |
01cb9ea6 | 789 | static bool ironlake_edp_panel_on (struct intel_dp *intel_dp) |
9934c132 | 790 | { |
01cb9ea6 | 791 | struct drm_device *dev = intel_dp->base.base.dev; |
9934c132 | 792 | struct drm_i915_private *dev_priv = dev->dev_private; |
01cb9ea6 | 793 | u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE; |
9934c132 | 794 | |
913d8d11 | 795 | if (I915_READ(PCH_PP_STATUS) & PP_ON) |
7eaf5547 | 796 | return true; |
9934c132 JB |
797 | |
798 | pp = I915_READ(PCH_PP_CONTROL); | |
37c6c9b0 JB |
799 | |
800 | /* ILK workaround: disable reset around power sequence */ | |
801 | pp &= ~PANEL_POWER_RESET; | |
802 | I915_WRITE(PCH_PP_CONTROL, pp); | |
803 | POSTING_READ(PCH_PP_CONTROL); | |
804 | ||
01cb9ea6 | 805 | pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; |
9934c132 | 806 | I915_WRITE(PCH_PP_CONTROL, pp); |
01cb9ea6 | 807 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 | 808 | |
27d64339 HV |
809 | /* Ouch. We need to wait here for some panels, like Dell e6510 |
810 | * https://bugs.freedesktop.org/show_bug.cgi?id=29278i | |
811 | */ | |
812 | msleep(300); | |
813 | ||
01cb9ea6 JB |
814 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, |
815 | 5000)) | |
913d8d11 CW |
816 | DRM_ERROR("panel on wait timed out: 0x%08x\n", |
817 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 818 | |
37c6c9b0 | 819 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 820 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 821 | POSTING_READ(PCH_PP_CONTROL); |
7eaf5547 JB |
822 | |
823 | return false; | |
9934c132 JB |
824 | } |
825 | ||
826 | static void ironlake_edp_panel_off (struct drm_device *dev) | |
827 | { | |
828 | struct drm_i915_private *dev_priv = dev->dev_private; | |
01cb9ea6 JB |
829 | u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | |
830 | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK; | |
9934c132 JB |
831 | |
832 | pp = I915_READ(PCH_PP_CONTROL); | |
37c6c9b0 JB |
833 | |
834 | /* ILK workaround: disable reset around power sequence */ | |
835 | pp &= ~PANEL_POWER_RESET; | |
836 | I915_WRITE(PCH_PP_CONTROL, pp); | |
837 | POSTING_READ(PCH_PP_CONTROL); | |
838 | ||
9934c132 JB |
839 | pp &= ~POWER_TARGET_ON; |
840 | I915_WRITE(PCH_PP_CONTROL, pp); | |
01cb9ea6 | 841 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 | 842 | |
01cb9ea6 | 843 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000)) |
913d8d11 CW |
844 | DRM_ERROR("panel off wait timed out: 0x%08x\n", |
845 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 846 | |
3969c9c9 | 847 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 848 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 849 | POSTING_READ(PCH_PP_CONTROL); |
27d64339 HV |
850 | |
851 | /* Ouch. We need to wait here for some panels, like Dell e6510 | |
852 | * https://bugs.freedesktop.org/show_bug.cgi?id=29278i | |
853 | */ | |
854 | msleep(300); | |
9934c132 JB |
855 | } |
856 | ||
f2b115e6 | 857 | static void ironlake_edp_backlight_on (struct drm_device *dev) |
32f9d658 ZW |
858 | { |
859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
860 | u32 pp; | |
861 | ||
28c97730 | 862 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
863 | /* |
864 | * If we enable the backlight right away following a panel power | |
865 | * on, we may see slight flicker as the panel syncs with the eDP | |
866 | * link. So delay a bit to make sure the image is solid before | |
867 | * allowing it to appear. | |
868 | */ | |
869 | msleep(300); | |
32f9d658 ZW |
870 | pp = I915_READ(PCH_PP_CONTROL); |
871 | pp |= EDP_BLC_ENABLE; | |
872 | I915_WRITE(PCH_PP_CONTROL, pp); | |
873 | } | |
874 | ||
f2b115e6 | 875 | static void ironlake_edp_backlight_off (struct drm_device *dev) |
32f9d658 ZW |
876 | { |
877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
878 | u32 pp; | |
879 | ||
28c97730 | 880 | DRM_DEBUG_KMS("\n"); |
32f9d658 ZW |
881 | pp = I915_READ(PCH_PP_CONTROL); |
882 | pp &= ~EDP_BLC_ENABLE; | |
883 | I915_WRITE(PCH_PP_CONTROL, pp); | |
884 | } | |
a4fc5ed6 | 885 | |
d240f20f JB |
886 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
887 | { | |
888 | struct drm_device *dev = encoder->dev; | |
889 | struct drm_i915_private *dev_priv = dev->dev_private; | |
890 | u32 dpa_ctl; | |
891 | ||
892 | DRM_DEBUG_KMS("\n"); | |
893 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 894 | dpa_ctl |= DP_PLL_ENABLE; |
d240f20f | 895 | I915_WRITE(DP_A, dpa_ctl); |
298b0b39 JB |
896 | POSTING_READ(DP_A); |
897 | udelay(200); | |
d240f20f JB |
898 | } |
899 | ||
900 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) | |
901 | { | |
902 | struct drm_device *dev = encoder->dev; | |
903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
904 | u32 dpa_ctl; | |
905 | ||
906 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 907 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 908 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 909 | POSTING_READ(DP_A); |
d240f20f JB |
910 | udelay(200); |
911 | } | |
912 | ||
913 | static void intel_dp_prepare(struct drm_encoder *encoder) | |
914 | { | |
915 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
916 | struct drm_device *dev = encoder->dev; | |
d240f20f | 917 | |
4d926461 | 918 | if (is_edp(intel_dp)) { |
d240f20f | 919 | ironlake_edp_backlight_off(dev); |
01cb9ea6 JB |
920 | ironlake_edp_panel_on(intel_dp); |
921 | if (!is_pch_edp(intel_dp)) | |
922 | ironlake_edp_pll_on(encoder); | |
923 | else | |
924 | ironlake_edp_pll_off(encoder); | |
d240f20f | 925 | } |
736085bc | 926 | intel_dp_link_down(intel_dp); |
d240f20f JB |
927 | } |
928 | ||
929 | static void intel_dp_commit(struct drm_encoder *encoder) | |
930 | { | |
931 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
932 | struct drm_device *dev = encoder->dev; | |
d240f20f | 933 | |
33a34e4e JB |
934 | intel_dp_start_link_train(intel_dp); |
935 | ||
4d926461 | 936 | if (is_edp(intel_dp)) |
01cb9ea6 | 937 | ironlake_edp_panel_on(intel_dp); |
33a34e4e JB |
938 | |
939 | intel_dp_complete_link_train(intel_dp); | |
940 | ||
4d926461 | 941 | if (is_edp(intel_dp)) |
d240f20f JB |
942 | ironlake_edp_backlight_on(dev); |
943 | } | |
944 | ||
a4fc5ed6 KP |
945 | static void |
946 | intel_dp_dpms(struct drm_encoder *encoder, int mode) | |
947 | { | |
ea5b213a | 948 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
55f78c43 | 949 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 | 950 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 951 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
a4fc5ed6 KP |
952 | |
953 | if (mode != DRM_MODE_DPMS_ON) { | |
01cb9ea6 | 954 | if (is_edp(intel_dp)) |
7643a7fa | 955 | ironlake_edp_backlight_off(dev); |
736085bc | 956 | intel_dp_link_down(intel_dp); |
4d926461 | 957 | if (is_edp(intel_dp)) |
01cb9ea6 JB |
958 | ironlake_edp_panel_off(dev); |
959 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) | |
d240f20f | 960 | ironlake_edp_pll_off(encoder); |
a4fc5ed6 | 961 | } else { |
736085bc JB |
962 | if (is_edp(intel_dp)) |
963 | ironlake_edp_panel_on(intel_dp); | |
32f9d658 | 964 | if (!(dp_reg & DP_PORT_EN)) { |
01cb9ea6 | 965 | intel_dp_start_link_train(intel_dp); |
33a34e4e | 966 | intel_dp_complete_link_train(intel_dp); |
32f9d658 | 967 | } |
736085bc JB |
968 | if (is_edp(intel_dp)) |
969 | ironlake_edp_backlight_on(dev); | |
a4fc5ed6 | 970 | } |
ea5b213a | 971 | intel_dp->dpms_mode = mode; |
a4fc5ed6 KP |
972 | } |
973 | ||
974 | /* | |
975 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
976 | * link status information | |
977 | */ | |
978 | static bool | |
33a34e4e | 979 | intel_dp_get_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
980 | { |
981 | int ret; | |
982 | ||
ea5b213a | 983 | ret = intel_dp_aux_native_read(intel_dp, |
a4fc5ed6 | 984 | DP_LANE0_1_STATUS, |
33a34e4e | 985 | intel_dp->link_status, DP_LINK_STATUS_SIZE); |
a4fc5ed6 KP |
986 | if (ret != DP_LINK_STATUS_SIZE) |
987 | return false; | |
988 | return true; | |
989 | } | |
990 | ||
991 | static uint8_t | |
992 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
993 | int r) | |
994 | { | |
995 | return link_status[r - DP_LANE0_1_STATUS]; | |
996 | } | |
997 | ||
a4fc5ed6 KP |
998 | static uint8_t |
999 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1000 | int lane) | |
1001 | { | |
1002 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
1003 | int s = ((lane & 1) ? | |
1004 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
1005 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
1006 | uint8_t l = intel_dp_link_status(link_status, i); | |
1007 | ||
1008 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
1009 | } | |
1010 | ||
1011 | static uint8_t | |
1012 | intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1013 | int lane) | |
1014 | { | |
1015 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
1016 | int s = ((lane & 1) ? | |
1017 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
1018 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
1019 | uint8_t l = intel_dp_link_status(link_status, i); | |
1020 | ||
1021 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
1022 | } | |
1023 | ||
1024 | ||
1025 | #if 0 | |
1026 | static char *voltage_names[] = { | |
1027 | "0.4V", "0.6V", "0.8V", "1.2V" | |
1028 | }; | |
1029 | static char *pre_emph_names[] = { | |
1030 | "0dB", "3.5dB", "6dB", "9.5dB" | |
1031 | }; | |
1032 | static char *link_train_names[] = { | |
1033 | "pattern 1", "pattern 2", "idle", "off" | |
1034 | }; | |
1035 | #endif | |
1036 | ||
1037 | /* | |
1038 | * These are source-specific values; current Intel hardware supports | |
1039 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1040 | */ | |
1041 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 | |
1042 | ||
1043 | static uint8_t | |
1044 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) | |
1045 | { | |
1046 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1047 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1048 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1049 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1050 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1051 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1052 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1053 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1054 | default: | |
1055 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1056 | } | |
1057 | } | |
1058 | ||
1059 | static void | |
33a34e4e | 1060 | intel_get_adjust_train(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1061 | { |
1062 | uint8_t v = 0; | |
1063 | uint8_t p = 0; | |
1064 | int lane; | |
1065 | ||
33a34e4e JB |
1066 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1067 | uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane); | |
1068 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1069 | |
1070 | if (this_v > v) | |
1071 | v = this_v; | |
1072 | if (this_p > p) | |
1073 | p = this_p; | |
1074 | } | |
1075 | ||
1076 | if (v >= I830_DP_VOLTAGE_MAX) | |
1077 | v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; | |
1078 | ||
1079 | if (p >= intel_dp_pre_emphasis_max(v)) | |
1080 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
1081 | ||
1082 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 1083 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
1084 | } |
1085 | ||
1086 | static uint32_t | |
869184a6 | 1087 | intel_dp_signal_levels(struct intel_dp *intel_dp) |
a4fc5ed6 | 1088 | { |
869184a6 JB |
1089 | struct drm_device *dev = intel_dp->base.base.dev; |
1090 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1091 | uint32_t signal_levels = 0; | |
1092 | u8 train_set = intel_dp->train_set[0]; | |
1093 | u32 vswing = train_set & DP_TRAIN_VOLTAGE_SWING_MASK; | |
1094 | u32 preemphasis = train_set & DP_TRAIN_PRE_EMPHASIS_MASK; | |
a4fc5ed6 | 1095 | |
869184a6 JB |
1096 | if (is_edp(intel_dp)) { |
1097 | vswing = dev_priv->edp.vswing; | |
1098 | preemphasis = dev_priv->edp.preemphasis; | |
1099 | } | |
1100 | ||
1101 | switch (vswing) { | |
a4fc5ed6 KP |
1102 | case DP_TRAIN_VOLTAGE_SWING_400: |
1103 | default: | |
1104 | signal_levels |= DP_VOLTAGE_0_4; | |
1105 | break; | |
1106 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1107 | signal_levels |= DP_VOLTAGE_0_6; | |
1108 | break; | |
1109 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1110 | signal_levels |= DP_VOLTAGE_0_8; | |
1111 | break; | |
1112 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1113 | signal_levels |= DP_VOLTAGE_1_2; | |
1114 | break; | |
1115 | } | |
869184a6 | 1116 | switch (preemphasis) { |
a4fc5ed6 KP |
1117 | case DP_TRAIN_PRE_EMPHASIS_0: |
1118 | default: | |
1119 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1120 | break; | |
1121 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1122 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1123 | break; | |
1124 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1125 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1126 | break; | |
1127 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1128 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1129 | break; | |
1130 | } | |
1131 | return signal_levels; | |
1132 | } | |
1133 | ||
e3421a18 ZW |
1134 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1135 | static uint32_t | |
1136 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1137 | { | |
1138 | switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) { | |
1139 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
1140 | return EDP_LINK_TRAIN_400MV_0DB_SNB_B; | |
1141 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
1142 | return EDP_LINK_TRAIN_400MV_6DB_SNB_B; | |
1143 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1144 | return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B; | |
1145 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | |
1146 | return EDP_LINK_TRAIN_800MV_0DB_SNB_B; | |
1147 | default: | |
1148 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n"); | |
1149 | return EDP_LINK_TRAIN_400MV_0DB_SNB_B; | |
1150 | } | |
1151 | } | |
1152 | ||
a4fc5ed6 KP |
1153 | static uint8_t |
1154 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1155 | int lane) | |
1156 | { | |
1157 | int i = DP_LANE0_1_STATUS + (lane >> 1); | |
1158 | int s = (lane & 1) * 4; | |
1159 | uint8_t l = intel_dp_link_status(link_status, i); | |
1160 | ||
1161 | return (l >> s) & 0xf; | |
1162 | } | |
1163 | ||
1164 | /* Check for clock recovery is done on all channels */ | |
1165 | static bool | |
1166 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1167 | { | |
1168 | int lane; | |
1169 | uint8_t lane_status; | |
1170 | ||
1171 | for (lane = 0; lane < lane_count; lane++) { | |
1172 | lane_status = intel_get_lane_status(link_status, lane); | |
1173 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
1174 | return false; | |
1175 | } | |
1176 | return true; | |
1177 | } | |
1178 | ||
1179 | /* Check to see if channel eq is done on all channels */ | |
1180 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ | |
1181 | DP_LANE_CHANNEL_EQ_DONE|\ | |
1182 | DP_LANE_SYMBOL_LOCKED) | |
1183 | static bool | |
33a34e4e | 1184 | intel_channel_eq_ok(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1185 | { |
1186 | uint8_t lane_align; | |
1187 | uint8_t lane_status; | |
1188 | int lane; | |
1189 | ||
33a34e4e | 1190 | lane_align = intel_dp_link_status(intel_dp->link_status, |
a4fc5ed6 KP |
1191 | DP_LANE_ALIGN_STATUS_UPDATED); |
1192 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
1193 | return false; | |
33a34e4e JB |
1194 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1195 | lane_status = intel_get_lane_status(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1196 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
1197 | return false; | |
1198 | } | |
1199 | return true; | |
1200 | } | |
1201 | ||
869184a6 JB |
1202 | static bool |
1203 | intel_dp_aux_handshake_required(struct intel_dp *intel_dp) | |
1204 | { | |
1205 | struct drm_device *dev = intel_dp->base.base.dev; | |
1206 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1207 | ||
1208 | if (is_edp(intel_dp) && dev_priv->no_aux_handshake) | |
1209 | return false; | |
1210 | ||
1211 | return true; | |
1212 | } | |
1213 | ||
a4fc5ed6 | 1214 | static bool |
ea5b213a | 1215 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 | 1216 | uint32_t dp_reg_value, |
58e10eb9 | 1217 | uint8_t dp_train_pat) |
a4fc5ed6 | 1218 | { |
4ef69c7a | 1219 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1220 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1221 | int ret; |
1222 | ||
ea5b213a CW |
1223 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1224 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1225 | |
869184a6 JB |
1226 | if (!intel_dp_aux_handshake_required(intel_dp)) |
1227 | return true; | |
1228 | ||
ea5b213a | 1229 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1230 | DP_TRAINING_PATTERN_SET, |
1231 | dp_train_pat); | |
1232 | ||
ea5b213a | 1233 | ret = intel_dp_aux_native_write(intel_dp, |
58e10eb9 CW |
1234 | DP_TRAINING_LANE0_SET, |
1235 | intel_dp->train_set, 4); | |
a4fc5ed6 KP |
1236 | if (ret != 4) |
1237 | return false; | |
1238 | ||
1239 | return true; | |
1240 | } | |
1241 | ||
33a34e4e | 1242 | /* Enable corresponding port and start training pattern 1 */ |
a4fc5ed6 | 1243 | static void |
33a34e4e | 1244 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1245 | { |
4ef69c7a | 1246 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1247 | struct drm_i915_private *dev_priv = dev->dev_private; |
58e10eb9 | 1248 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); |
a4fc5ed6 KP |
1249 | int i; |
1250 | uint8_t voltage; | |
1251 | bool clock_recovery = false; | |
a4fc5ed6 | 1252 | int tries; |
e3421a18 | 1253 | u32 reg; |
ea5b213a | 1254 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1255 | |
b99a9d9b KP |
1256 | /* Enable output, wait for it to become active */ |
1257 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
1258 | POSTING_READ(intel_dp->output_reg); | |
1259 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
a4fc5ed6 | 1260 | |
869184a6 JB |
1261 | if (intel_dp_aux_handshake_required(intel_dp)) |
1262 | /* Write the link configuration data */ | |
1263 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, | |
1264 | intel_dp->link_configuration, | |
1265 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
1266 | |
1267 | DP |= DP_PORT_EN; | |
cfcb0fc9 | 1268 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1269 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1270 | else | |
1271 | DP &= ~DP_LINK_TRAIN_MASK; | |
33a34e4e | 1272 | memset(intel_dp->train_set, 0, 4); |
a4fc5ed6 KP |
1273 | voltage = 0xff; |
1274 | tries = 0; | |
1275 | clock_recovery = false; | |
1276 | for (;;) { | |
33a34e4e | 1277 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 | 1278 | uint32_t signal_levels; |
cfcb0fc9 | 1279 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
33a34e4e | 1280 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1281 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1282 | } else { | |
869184a6 | 1283 | signal_levels = intel_dp_signal_levels(intel_dp); |
e3421a18 ZW |
1284 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1285 | } | |
a4fc5ed6 | 1286 | |
cfcb0fc9 | 1287 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1288 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
1289 | else | |
1290 | reg = DP | DP_LINK_TRAIN_PAT_1; | |
1291 | ||
ea5b213a | 1292 | if (!intel_dp_set_link_train(intel_dp, reg, |
58e10eb9 | 1293 | DP_TRAINING_PATTERN_1)) |
a4fc5ed6 | 1294 | break; |
a4fc5ed6 KP |
1295 | /* Set training pattern 1 */ |
1296 | ||
869184a6 JB |
1297 | udelay(500); |
1298 | if (intel_dp_aux_handshake_required(intel_dp)) { | |
a4fc5ed6 | 1299 | break; |
869184a6 JB |
1300 | } else { |
1301 | if (!intel_dp_get_link_status(intel_dp)) | |
1302 | break; | |
a4fc5ed6 | 1303 | |
869184a6 JB |
1304 | if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { |
1305 | clock_recovery = true; | |
a4fc5ed6 | 1306 | break; |
869184a6 | 1307 | } |
a4fc5ed6 | 1308 | |
869184a6 JB |
1309 | /* Check to see if we've tried the max voltage */ |
1310 | for (i = 0; i < intel_dp->lane_count; i++) | |
1311 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
1312 | break; | |
1313 | if (i == intel_dp->lane_count) | |
a4fc5ed6 | 1314 | break; |
a4fc5ed6 | 1315 | |
869184a6 JB |
1316 | /* Check to see if we've tried the same voltage 5 times */ |
1317 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { | |
1318 | ++tries; | |
1319 | if (tries == 5) | |
1320 | break; | |
1321 | } else | |
1322 | tries = 0; | |
1323 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
1324 | ||
1325 | /* Compute new intel_dp->train_set as requested by target */ | |
1326 | intel_get_adjust_train(intel_dp); | |
1327 | } | |
a4fc5ed6 KP |
1328 | } |
1329 | ||
33a34e4e JB |
1330 | intel_dp->DP = DP; |
1331 | } | |
1332 | ||
1333 | static void | |
1334 | intel_dp_complete_link_train(struct intel_dp *intel_dp) | |
1335 | { | |
4ef69c7a | 1336 | struct drm_device *dev = intel_dp->base.base.dev; |
33a34e4e JB |
1337 | struct drm_i915_private *dev_priv = dev->dev_private; |
1338 | bool channel_eq = false; | |
1339 | int tries; | |
1340 | u32 reg; | |
1341 | uint32_t DP = intel_dp->DP; | |
1342 | ||
a4fc5ed6 KP |
1343 | /* channel equalization */ |
1344 | tries = 0; | |
1345 | channel_eq = false; | |
1346 | for (;;) { | |
33a34e4e | 1347 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 ZW |
1348 | uint32_t signal_levels; |
1349 | ||
cfcb0fc9 | 1350 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
33a34e4e | 1351 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1352 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1353 | } else { | |
869184a6 | 1354 | signal_levels = intel_dp_signal_levels(intel_dp); |
e3421a18 ZW |
1355 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1356 | } | |
1357 | ||
cfcb0fc9 | 1358 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1359 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
1360 | else | |
1361 | reg = DP | DP_LINK_TRAIN_PAT_2; | |
a4fc5ed6 KP |
1362 | |
1363 | /* channel eq pattern */ | |
ea5b213a | 1364 | if (!intel_dp_set_link_train(intel_dp, reg, |
58e10eb9 | 1365 | DP_TRAINING_PATTERN_2)) |
a4fc5ed6 KP |
1366 | break; |
1367 | ||
869184a6 | 1368 | udelay(500); |
a4fc5ed6 | 1369 | |
869184a6 | 1370 | if (!intel_dp_aux_handshake_required(intel_dp)) { |
a4fc5ed6 | 1371 | break; |
869184a6 JB |
1372 | } else { |
1373 | if (!intel_dp_get_link_status(intel_dp)) | |
1374 | break; | |
a4fc5ed6 | 1375 | |
869184a6 JB |
1376 | if (intel_channel_eq_ok(intel_dp)) { |
1377 | channel_eq = true; | |
1378 | break; | |
1379 | } | |
a4fc5ed6 | 1380 | |
869184a6 JB |
1381 | /* Try 5 times */ |
1382 | if (tries > 5) | |
1383 | break; | |
a4fc5ed6 | 1384 | |
869184a6 JB |
1385 | /* Compute new intel_dp->train_set as requested by target */ |
1386 | intel_get_adjust_train(intel_dp); | |
1387 | ++tries; | |
1388 | } | |
1389 | } | |
cfcb0fc9 | 1390 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1391 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
1392 | else | |
1393 | reg = DP | DP_LINK_TRAIN_OFF; | |
1394 | ||
ea5b213a CW |
1395 | I915_WRITE(intel_dp->output_reg, reg); |
1396 | POSTING_READ(intel_dp->output_reg); | |
1397 | intel_dp_aux_native_write_1(intel_dp, | |
a4fc5ed6 KP |
1398 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
1399 | } | |
1400 | ||
1401 | static void | |
ea5b213a | 1402 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 1403 | { |
4ef69c7a | 1404 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1405 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1406 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1407 | |
28c97730 | 1408 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1409 | |
cfcb0fc9 | 1410 | if (is_edp(intel_dp)) { |
32f9d658 | 1411 | DP &= ~DP_PLL_ENABLE; |
ea5b213a CW |
1412 | I915_WRITE(intel_dp->output_reg, DP); |
1413 | POSTING_READ(intel_dp->output_reg); | |
32f9d658 ZW |
1414 | udelay(100); |
1415 | } | |
1416 | ||
cfcb0fc9 | 1417 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) { |
e3421a18 | 1418 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 1419 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
1420 | } else { |
1421 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 1422 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 1423 | } |
fe255d00 | 1424 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 1425 | |
fe255d00 | 1426 | msleep(17); |
5eb08b69 | 1427 | |
cfcb0fc9 | 1428 | if (is_edp(intel_dp)) |
32f9d658 | 1429 | DP |= DP_LINK_TRAIN_OFF; |
ea5b213a CW |
1430 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
1431 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 KP |
1432 | } |
1433 | ||
a4fc5ed6 KP |
1434 | /* |
1435 | * According to DP spec | |
1436 | * 5.1.2: | |
1437 | * 1. Read DPCD | |
1438 | * 2. Configure link according to Receiver Capabilities | |
1439 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
1440 | * 4. Check link status on receipt of hot-plug interrupt | |
1441 | */ | |
1442 | ||
1443 | static void | |
ea5b213a | 1444 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1445 | { |
4ef69c7a | 1446 | if (!intel_dp->base.base.crtc) |
a4fc5ed6 KP |
1447 | return; |
1448 | ||
33a34e4e | 1449 | if (!intel_dp_get_link_status(intel_dp)) { |
ea5b213a | 1450 | intel_dp_link_down(intel_dp); |
a4fc5ed6 KP |
1451 | return; |
1452 | } | |
1453 | ||
33a34e4e JB |
1454 | if (!intel_channel_eq_ok(intel_dp)) { |
1455 | intel_dp_start_link_train(intel_dp); | |
1456 | intel_dp_complete_link_train(intel_dp); | |
1457 | } | |
a4fc5ed6 | 1458 | } |
a4fc5ed6 | 1459 | |
5eb08b69 | 1460 | static enum drm_connector_status |
f2b115e6 | 1461 | ironlake_dp_detect(struct drm_connector *connector) |
5eb08b69 | 1462 | { |
df0e9248 | 1463 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
5eb08b69 ZW |
1464 | enum drm_connector_status status; |
1465 | ||
01cb9ea6 | 1466 | /* Can't disconnect eDP */ |
4d926461 | 1467 | if (is_edp(intel_dp)) |
01cb9ea6 JB |
1468 | return connector_status_connected; |
1469 | ||
5eb08b69 | 1470 | status = connector_status_disconnected; |
ea5b213a CW |
1471 | if (intel_dp_aux_native_read(intel_dp, |
1472 | 0x000, intel_dp->dpcd, | |
1473 | sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) | |
5eb08b69 | 1474 | { |
ea5b213a | 1475 | if (intel_dp->dpcd[0] != 0) |
5eb08b69 ZW |
1476 | status = connector_status_connected; |
1477 | } | |
ea5b213a CW |
1478 | DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0], |
1479 | intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]); | |
5eb08b69 ZW |
1480 | return status; |
1481 | } | |
1482 | ||
a4fc5ed6 KP |
1483 | /** |
1484 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. | |
1485 | * | |
1486 | * \return true if DP port is connected. | |
1487 | * \return false if DP port is disconnected. | |
1488 | */ | |
1489 | static enum drm_connector_status | |
930a9e28 | 1490 | intel_dp_detect(struct drm_connector *connector, bool force) |
a4fc5ed6 | 1491 | { |
df0e9248 | 1492 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4ef69c7a | 1493 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1494 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1495 | uint32_t temp, bit; |
1496 | enum drm_connector_status status; | |
1497 | ||
ea5b213a | 1498 | intel_dp->has_audio = false; |
a4fc5ed6 | 1499 | |
c619eed4 | 1500 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1501 | return ironlake_dp_detect(connector); |
5eb08b69 | 1502 | |
ea5b213a | 1503 | switch (intel_dp->output_reg) { |
a4fc5ed6 KP |
1504 | case DP_B: |
1505 | bit = DPB_HOTPLUG_INT_STATUS; | |
1506 | break; | |
1507 | case DP_C: | |
1508 | bit = DPC_HOTPLUG_INT_STATUS; | |
1509 | break; | |
1510 | case DP_D: | |
1511 | bit = DPD_HOTPLUG_INT_STATUS; | |
1512 | break; | |
1513 | default: | |
1514 | return connector_status_unknown; | |
1515 | } | |
1516 | ||
1517 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
1518 | ||
1519 | if ((temp & bit) == 0) | |
1520 | return connector_status_disconnected; | |
1521 | ||
1522 | status = connector_status_disconnected; | |
ea5b213a CW |
1523 | if (intel_dp_aux_native_read(intel_dp, |
1524 | 0x000, intel_dp->dpcd, | |
1525 | sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) | |
a4fc5ed6 | 1526 | { |
ea5b213a | 1527 | if (intel_dp->dpcd[0] != 0) |
a4fc5ed6 KP |
1528 | status = connector_status_connected; |
1529 | } | |
1530 | return status; | |
1531 | } | |
1532 | ||
1533 | static int intel_dp_get_modes(struct drm_connector *connector) | |
1534 | { | |
df0e9248 | 1535 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4ef69c7a | 1536 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1537 | struct drm_i915_private *dev_priv = dev->dev_private; |
1538 | int ret; | |
a4fc5ed6 KP |
1539 | |
1540 | /* We should parse the EDID data and find out if it has an audio sink | |
1541 | */ | |
1542 | ||
f899fc64 | 1543 | ret = intel_ddc_get_modes(connector, &intel_dp->adapter); |
b9efc480 | 1544 | if (ret) { |
4d926461 | 1545 | if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) { |
b9efc480 ZY |
1546 | struct drm_display_mode *newmode; |
1547 | list_for_each_entry(newmode, &connector->probed_modes, | |
1548 | head) { | |
1549 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
1550 | dev_priv->panel_fixed_mode = | |
1551 | drm_mode_duplicate(dev, newmode); | |
1552 | break; | |
1553 | } | |
1554 | } | |
1555 | } | |
1556 | ||
32f9d658 | 1557 | return ret; |
b9efc480 | 1558 | } |
32f9d658 ZW |
1559 | |
1560 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ | |
4d926461 | 1561 | if (is_edp(intel_dp)) { |
32f9d658 ZW |
1562 | if (dev_priv->panel_fixed_mode != NULL) { |
1563 | struct drm_display_mode *mode; | |
1564 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); | |
1565 | drm_mode_probed_add(connector, mode); | |
1566 | return 1; | |
1567 | } | |
1568 | } | |
1569 | return 0; | |
a4fc5ed6 KP |
1570 | } |
1571 | ||
1572 | static void | |
1573 | intel_dp_destroy (struct drm_connector *connector) | |
1574 | { | |
a4fc5ed6 KP |
1575 | drm_sysfs_connector_remove(connector); |
1576 | drm_connector_cleanup(connector); | |
55f78c43 | 1577 | kfree(connector); |
a4fc5ed6 KP |
1578 | } |
1579 | ||
24d05927 DV |
1580 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
1581 | { | |
1582 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1583 | ||
1584 | i2c_del_adapter(&intel_dp->adapter); | |
1585 | drm_encoder_cleanup(encoder); | |
1586 | kfree(intel_dp); | |
1587 | } | |
1588 | ||
a4fc5ed6 KP |
1589 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
1590 | .dpms = intel_dp_dpms, | |
1591 | .mode_fixup = intel_dp_mode_fixup, | |
d240f20f | 1592 | .prepare = intel_dp_prepare, |
a4fc5ed6 | 1593 | .mode_set = intel_dp_mode_set, |
d240f20f | 1594 | .commit = intel_dp_commit, |
a4fc5ed6 KP |
1595 | }; |
1596 | ||
1597 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
1598 | .dpms = drm_helper_connector_dpms, | |
a4fc5ed6 KP |
1599 | .detect = intel_dp_detect, |
1600 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1601 | .destroy = intel_dp_destroy, | |
1602 | }; | |
1603 | ||
1604 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
1605 | .get_modes = intel_dp_get_modes, | |
1606 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 1607 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
1608 | }; |
1609 | ||
a4fc5ed6 | 1610 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 1611 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
1612 | }; |
1613 | ||
995b6762 | 1614 | static void |
21d40d37 | 1615 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 1616 | { |
ea5b213a | 1617 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
c8110e52 | 1618 | |
ea5b213a CW |
1619 | if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON) |
1620 | intel_dp_check_link_status(intel_dp); | |
c8110e52 | 1621 | } |
6207937d | 1622 | |
e3421a18 ZW |
1623 | /* Return which DP Port should be selected for Transcoder DP control */ |
1624 | int | |
1625 | intel_trans_dp_port_sel (struct drm_crtc *crtc) | |
1626 | { | |
1627 | struct drm_device *dev = crtc->dev; | |
1628 | struct drm_mode_config *mode_config = &dev->mode_config; | |
1629 | struct drm_encoder *encoder; | |
e3421a18 ZW |
1630 | |
1631 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a CW |
1632 | struct intel_dp *intel_dp; |
1633 | ||
d8201ab6 | 1634 | if (encoder->crtc != crtc) |
e3421a18 ZW |
1635 | continue; |
1636 | ||
ea5b213a CW |
1637 | intel_dp = enc_to_intel_dp(encoder); |
1638 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) | |
1639 | return intel_dp->output_reg; | |
e3421a18 | 1640 | } |
ea5b213a | 1641 | |
e3421a18 ZW |
1642 | return -1; |
1643 | } | |
1644 | ||
36e83a18 | 1645 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 1646 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
1647 | { |
1648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1649 | struct child_device_config *p_child; | |
1650 | int i; | |
1651 | ||
1652 | if (!dev_priv->child_dev_num) | |
1653 | return false; | |
1654 | ||
1655 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
1656 | p_child = dev_priv->child_dev + i; | |
1657 | ||
1658 | if (p_child->dvo_port == PORT_IDPD && | |
1659 | p_child->device_type == DEVICE_TYPE_eDP) | |
1660 | return true; | |
1661 | } | |
1662 | return false; | |
1663 | } | |
1664 | ||
a4fc5ed6 KP |
1665 | void |
1666 | intel_dp_init(struct drm_device *dev, int output_reg) | |
1667 | { | |
1668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1669 | struct drm_connector *connector; | |
ea5b213a | 1670 | struct intel_dp *intel_dp; |
21d40d37 | 1671 | struct intel_encoder *intel_encoder; |
55f78c43 | 1672 | struct intel_connector *intel_connector; |
5eb08b69 | 1673 | const char *name = NULL; |
b329530c | 1674 | int type; |
a4fc5ed6 | 1675 | |
ea5b213a CW |
1676 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
1677 | if (!intel_dp) | |
a4fc5ed6 KP |
1678 | return; |
1679 | ||
55f78c43 ZW |
1680 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
1681 | if (!intel_connector) { | |
ea5b213a | 1682 | kfree(intel_dp); |
55f78c43 ZW |
1683 | return; |
1684 | } | |
ea5b213a | 1685 | intel_encoder = &intel_dp->base; |
55f78c43 | 1686 | |
ea5b213a | 1687 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
b329530c | 1688 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 1689 | intel_dp->is_pch_edp = true; |
b329530c | 1690 | |
cfcb0fc9 | 1691 | if (output_reg == DP_A || is_pch_edp(intel_dp)) { |
b329530c AJ |
1692 | type = DRM_MODE_CONNECTOR_eDP; |
1693 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
1694 | } else { | |
1695 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
1696 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
1697 | } | |
1698 | ||
55f78c43 | 1699 | connector = &intel_connector->base; |
b329530c | 1700 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
1701 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
1702 | ||
eb1f8e4f DA |
1703 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
1704 | ||
652af9d7 | 1705 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
21d40d37 | 1706 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
652af9d7 | 1707 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
21d40d37 | 1708 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
652af9d7 | 1709 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
21d40d37 | 1710 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
f8aed700 | 1711 | |
cfcb0fc9 | 1712 | if (is_edp(intel_dp)) |
21d40d37 | 1713 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
6251ec0a | 1714 | |
21d40d37 | 1715 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
a4fc5ed6 KP |
1716 | connector->interlace_allowed = true; |
1717 | connector->doublescan_allowed = 0; | |
1718 | ||
ea5b213a CW |
1719 | intel_dp->output_reg = output_reg; |
1720 | intel_dp->has_audio = false; | |
1721 | intel_dp->dpms_mode = DRM_MODE_DPMS_ON; | |
a4fc5ed6 | 1722 | |
4ef69c7a | 1723 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
a4fc5ed6 | 1724 | DRM_MODE_ENCODER_TMDS); |
4ef69c7a | 1725 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
a4fc5ed6 | 1726 | |
df0e9248 | 1727 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
1728 | drm_sysfs_connector_add(connector); |
1729 | ||
1730 | /* Set up the DDC bus. */ | |
5eb08b69 | 1731 | switch (output_reg) { |
32f9d658 ZW |
1732 | case DP_A: |
1733 | name = "DPDDC-A"; | |
1734 | break; | |
5eb08b69 ZW |
1735 | case DP_B: |
1736 | case PCH_DP_B: | |
b01f2c3a JB |
1737 | dev_priv->hotplug_supported_mask |= |
1738 | HDMIB_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1739 | name = "DPDDC-B"; |
1740 | break; | |
1741 | case DP_C: | |
1742 | case PCH_DP_C: | |
b01f2c3a JB |
1743 | dev_priv->hotplug_supported_mask |= |
1744 | HDMIC_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1745 | name = "DPDDC-C"; |
1746 | break; | |
1747 | case DP_D: | |
1748 | case PCH_DP_D: | |
b01f2c3a JB |
1749 | dev_priv->hotplug_supported_mask |= |
1750 | HDMID_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1751 | name = "DPDDC-D"; |
1752 | break; | |
1753 | } | |
1754 | ||
ea5b213a | 1755 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
32f9d658 | 1756 | |
89667383 JB |
1757 | /* Cache some DPCD data in the eDP case */ |
1758 | if (is_edp(intel_dp)) { | |
1759 | int ret; | |
1760 | bool was_on; | |
1761 | ||
1762 | was_on = ironlake_edp_panel_on(intel_dp); | |
1763 | ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV, | |
1764 | intel_dp->dpcd, | |
1765 | sizeof(intel_dp->dpcd)); | |
1766 | if (ret == sizeof(intel_dp->dpcd)) { | |
1767 | if (intel_dp->dpcd[0] >= 0x11) | |
1768 | dev_priv->no_aux_handshake = intel_dp->dpcd[3] & | |
1769 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
1770 | } else { | |
1771 | DRM_ERROR("failed to retrieve link info\n"); | |
1772 | } | |
1773 | if (!was_on) | |
1774 | ironlake_edp_panel_off(dev); | |
1775 | } | |
1776 | ||
21d40d37 | 1777 | intel_encoder->hot_plug = intel_dp_hot_plug; |
a4fc5ed6 | 1778 | |
4d926461 | 1779 | if (is_edp(intel_dp)) { |
32f9d658 ZW |
1780 | /* initialize panel mode from VBT if available for eDP */ |
1781 | if (dev_priv->lfp_lvds_vbt_mode) { | |
1782 | dev_priv->panel_fixed_mode = | |
1783 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); | |
1784 | if (dev_priv->panel_fixed_mode) { | |
1785 | dev_priv->panel_fixed_mode->type |= | |
1786 | DRM_MODE_TYPE_PREFERRED; | |
1787 | } | |
1788 | } | |
1789 | } | |
1790 | ||
a4fc5ed6 KP |
1791 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
1792 | * 0xd. Failure to do so will result in spurious interrupts being | |
1793 | * generated on the port when a cable is not attached. | |
1794 | */ | |
1795 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1796 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1797 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1798 | } | |
1799 | } |