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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
a4fc5ed6 KP |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "drm_crtc_helper.h" | |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
ab2c0672 | 37 | #include "drm_dp_helper.h" |
a4fc5ed6 | 38 | |
ae266c98 | 39 | |
a4fc5ed6 KP |
40 | #define DP_LINK_STATUS_SIZE 6 |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) | |
42 | ||
43 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
44 | ||
ea5b213a CW |
45 | struct intel_dp { |
46 | struct intel_encoder base; | |
a4fc5ed6 KP |
47 | uint32_t output_reg; |
48 | uint32_t DP; | |
49 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
a4fc5ed6 | 50 | bool has_audio; |
f684960e | 51 | int force_audio; |
e953fd7b | 52 | uint32_t color_range; |
a4fc5ed6 KP |
53 | uint8_t link_bw; |
54 | uint8_t lane_count; | |
55 | uint8_t dpcd[4]; | |
a4fc5ed6 KP |
56 | struct i2c_adapter adapter; |
57 | struct i2c_algo_dp_aux_data algo; | |
f0917379 | 58 | bool is_pch_edp; |
33a34e4e JB |
59 | uint8_t train_set[4]; |
60 | uint8_t link_status[DP_LINK_STATUS_SIZE]; | |
a4fc5ed6 KP |
61 | }; |
62 | ||
cfcb0fc9 JB |
63 | /** |
64 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
65 | * @intel_dp: DP struct | |
66 | * | |
67 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
68 | * will return true, and false otherwise. | |
69 | */ | |
70 | static bool is_edp(struct intel_dp *intel_dp) | |
71 | { | |
72 | return intel_dp->base.type == INTEL_OUTPUT_EDP; | |
73 | } | |
74 | ||
75 | /** | |
76 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? | |
77 | * @intel_dp: DP struct | |
78 | * | |
79 | * Returns true if the given DP struct corresponds to a PCH DP port attached | |
80 | * to an eDP panel, false otherwise. Helpful for determining whether we | |
81 | * may need FDI resources for a given DP output or not. | |
82 | */ | |
83 | static bool is_pch_edp(struct intel_dp *intel_dp) | |
84 | { | |
85 | return intel_dp->is_pch_edp; | |
86 | } | |
87 | ||
ea5b213a CW |
88 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
89 | { | |
4ef69c7a | 90 | return container_of(encoder, struct intel_dp, base.base); |
ea5b213a | 91 | } |
a4fc5ed6 | 92 | |
df0e9248 CW |
93 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
94 | { | |
95 | return container_of(intel_attached_encoder(connector), | |
96 | struct intel_dp, base); | |
97 | } | |
98 | ||
814948ad JB |
99 | /** |
100 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? | |
101 | * @encoder: DRM encoder | |
102 | * | |
103 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed | |
104 | * by intel_display.c. | |
105 | */ | |
106 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) | |
107 | { | |
108 | struct intel_dp *intel_dp; | |
109 | ||
110 | if (!encoder) | |
111 | return false; | |
112 | ||
113 | intel_dp = enc_to_intel_dp(encoder); | |
114 | ||
115 | return is_pch_edp(intel_dp); | |
116 | } | |
117 | ||
33a34e4e JB |
118 | static void intel_dp_start_link_train(struct intel_dp *intel_dp); |
119 | static void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
ea5b213a | 120 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
a4fc5ed6 | 121 | |
32f9d658 | 122 | void |
21d40d37 | 123 | intel_edp_link_config (struct intel_encoder *intel_encoder, |
ea5b213a | 124 | int *lane_num, int *link_bw) |
32f9d658 | 125 | { |
ea5b213a | 126 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
32f9d658 | 127 | |
ea5b213a CW |
128 | *lane_num = intel_dp->lane_count; |
129 | if (intel_dp->link_bw == DP_LINK_BW_1_62) | |
32f9d658 | 130 | *link_bw = 162000; |
ea5b213a | 131 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
32f9d658 ZW |
132 | *link_bw = 270000; |
133 | } | |
134 | ||
a4fc5ed6 | 135 | static int |
ea5b213a | 136 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
a4fc5ed6 | 137 | { |
a4fc5ed6 KP |
138 | int max_lane_count = 4; |
139 | ||
7183dc29 JB |
140 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
141 | max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; | |
a4fc5ed6 KP |
142 | switch (max_lane_count) { |
143 | case 1: case 2: case 4: | |
144 | break; | |
145 | default: | |
146 | max_lane_count = 4; | |
147 | } | |
148 | } | |
149 | return max_lane_count; | |
150 | } | |
151 | ||
152 | static int | |
ea5b213a | 153 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 154 | { |
7183dc29 | 155 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
156 | |
157 | switch (max_link_bw) { | |
158 | case DP_LINK_BW_1_62: | |
159 | case DP_LINK_BW_2_7: | |
160 | break; | |
161 | default: | |
162 | max_link_bw = DP_LINK_BW_1_62; | |
163 | break; | |
164 | } | |
165 | return max_link_bw; | |
166 | } | |
167 | ||
168 | static int | |
169 | intel_dp_link_clock(uint8_t link_bw) | |
170 | { | |
171 | if (link_bw == DP_LINK_BW_2_7) | |
172 | return 270000; | |
173 | else | |
174 | return 162000; | |
175 | } | |
176 | ||
177 | /* I think this is a fiction */ | |
178 | static int | |
ea5b213a | 179 | intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) |
a4fc5ed6 | 180 | { |
885a5fb5 ZW |
181 | struct drm_i915_private *dev_priv = dev->dev_private; |
182 | ||
4d926461 | 183 | if (is_edp(intel_dp)) |
5ceb0f9b | 184 | return (pixel_clock * dev_priv->edp.bpp + 7) / 8; |
885a5fb5 ZW |
185 | else |
186 | return pixel_clock * 3; | |
a4fc5ed6 KP |
187 | } |
188 | ||
fe27d53e DA |
189 | static int |
190 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
191 | { | |
192 | return (max_link_clock * max_lanes * 8) / 10; | |
193 | } | |
194 | ||
a4fc5ed6 KP |
195 | static int |
196 | intel_dp_mode_valid(struct drm_connector *connector, | |
197 | struct drm_display_mode *mode) | |
198 | { | |
df0e9248 | 199 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
7de56f43 ZY |
200 | struct drm_device *dev = connector->dev; |
201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a CW |
202 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
203 | int max_lanes = intel_dp_max_lane_count(intel_dp); | |
a4fc5ed6 | 204 | |
4d926461 | 205 | if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { |
7de56f43 ZY |
206 | if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) |
207 | return MODE_PANEL; | |
208 | ||
209 | if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay) | |
210 | return MODE_PANEL; | |
211 | } | |
212 | ||
25985edc | 213 | /* only refuse the mode on non eDP since we have seen some weird eDP panels |
fe27d53e | 214 | which are outside spec tolerances but somehow work by magic */ |
cfcb0fc9 | 215 | if (!is_edp(intel_dp) && |
ea5b213a | 216 | (intel_dp_link_required(connector->dev, intel_dp, mode->clock) |
fe27d53e | 217 | > intel_dp_max_data_rate(max_link_clock, max_lanes))) |
a4fc5ed6 KP |
218 | return MODE_CLOCK_HIGH; |
219 | ||
220 | if (mode->clock < 10000) | |
221 | return MODE_CLOCK_LOW; | |
222 | ||
223 | return MODE_OK; | |
224 | } | |
225 | ||
226 | static uint32_t | |
227 | pack_aux(uint8_t *src, int src_bytes) | |
228 | { | |
229 | int i; | |
230 | uint32_t v = 0; | |
231 | ||
232 | if (src_bytes > 4) | |
233 | src_bytes = 4; | |
234 | for (i = 0; i < src_bytes; i++) | |
235 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
236 | return v; | |
237 | } | |
238 | ||
239 | static void | |
240 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
241 | { | |
242 | int i; | |
243 | if (dst_bytes > 4) | |
244 | dst_bytes = 4; | |
245 | for (i = 0; i < dst_bytes; i++) | |
246 | dst[i] = src >> ((3-i) * 8); | |
247 | } | |
248 | ||
fb0f8fbf KP |
249 | /* hrawclock is 1/4 the FSB frequency */ |
250 | static int | |
251 | intel_hrawclk(struct drm_device *dev) | |
252 | { | |
253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
254 | uint32_t clkcfg; | |
255 | ||
256 | clkcfg = I915_READ(CLKCFG); | |
257 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
258 | case CLKCFG_FSB_400: | |
259 | return 100; | |
260 | case CLKCFG_FSB_533: | |
261 | return 133; | |
262 | case CLKCFG_FSB_667: | |
263 | return 166; | |
264 | case CLKCFG_FSB_800: | |
265 | return 200; | |
266 | case CLKCFG_FSB_1067: | |
267 | return 266; | |
268 | case CLKCFG_FSB_1333: | |
269 | return 333; | |
270 | /* these two are just a guess; one of them might be right */ | |
271 | case CLKCFG_FSB_1600: | |
272 | case CLKCFG_FSB_1600_ALT: | |
273 | return 400; | |
274 | default: | |
275 | return 133; | |
276 | } | |
277 | } | |
278 | ||
a4fc5ed6 | 279 | static int |
ea5b213a | 280 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
281 | uint8_t *send, int send_bytes, |
282 | uint8_t *recv, int recv_size) | |
283 | { | |
ea5b213a | 284 | uint32_t output_reg = intel_dp->output_reg; |
4ef69c7a | 285 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 KP |
286 | struct drm_i915_private *dev_priv = dev->dev_private; |
287 | uint32_t ch_ctl = output_reg + 0x10; | |
288 | uint32_t ch_data = ch_ctl + 4; | |
289 | int i; | |
290 | int recv_bytes; | |
a4fc5ed6 | 291 | uint32_t status; |
fb0f8fbf | 292 | uint32_t aux_clock_divider; |
e3421a18 | 293 | int try, precharge; |
a4fc5ed6 KP |
294 | |
295 | /* The clock divider is based off the hrawclk, | |
fb0f8fbf KP |
296 | * and would like to run at 2MHz. So, take the |
297 | * hrawclk value and divide by 2 and use that | |
6176b8f9 JB |
298 | * |
299 | * Note that PCH attached eDP panels should use a 125MHz input | |
300 | * clock divider. | |
a4fc5ed6 | 301 | */ |
cfcb0fc9 | 302 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
e3421a18 ZW |
303 | if (IS_GEN6(dev)) |
304 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ | |
305 | else | |
306 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
307 | } else if (HAS_PCH_SPLIT(dev)) | |
f2b115e6 | 308 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
5eb08b69 ZW |
309 | else |
310 | aux_clock_divider = intel_hrawclk(dev) / 2; | |
311 | ||
e3421a18 ZW |
312 | if (IS_GEN6(dev)) |
313 | precharge = 3; | |
314 | else | |
315 | precharge = 5; | |
316 | ||
4f7f7b7e CW |
317 | if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { |
318 | DRM_ERROR("dp_aux_ch not started status 0x%08x\n", | |
319 | I915_READ(ch_ctl)); | |
320 | return -EBUSY; | |
321 | } | |
322 | ||
fb0f8fbf KP |
323 | /* Must try at least 3 times according to DP spec */ |
324 | for (try = 0; try < 5; try++) { | |
325 | /* Load the send data into the aux channel data registers */ | |
4f7f7b7e CW |
326 | for (i = 0; i < send_bytes; i += 4) |
327 | I915_WRITE(ch_data + i, | |
328 | pack_aux(send + i, send_bytes - i)); | |
fb0f8fbf KP |
329 | |
330 | /* Send the command and wait for it to complete */ | |
4f7f7b7e CW |
331 | I915_WRITE(ch_ctl, |
332 | DP_AUX_CH_CTL_SEND_BUSY | | |
333 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
334 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
335 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
336 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
337 | DP_AUX_CH_CTL_DONE | | |
338 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
339 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
fb0f8fbf | 340 | for (;;) { |
fb0f8fbf KP |
341 | status = I915_READ(ch_ctl); |
342 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
343 | break; | |
4f7f7b7e | 344 | udelay(100); |
fb0f8fbf KP |
345 | } |
346 | ||
347 | /* Clear done status and any errors */ | |
4f7f7b7e CW |
348 | I915_WRITE(ch_ctl, |
349 | status | | |
350 | DP_AUX_CH_CTL_DONE | | |
351 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
352 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
353 | if (status & DP_AUX_CH_CTL_DONE) | |
a4fc5ed6 KP |
354 | break; |
355 | } | |
356 | ||
a4fc5ed6 | 357 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 358 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
a5b3da54 | 359 | return -EBUSY; |
a4fc5ed6 KP |
360 | } |
361 | ||
362 | /* Check for timeout or receive error. | |
363 | * Timeouts occur when the sink is not connected | |
364 | */ | |
a5b3da54 | 365 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 366 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
a5b3da54 KP |
367 | return -EIO; |
368 | } | |
1ae8c0a5 KP |
369 | |
370 | /* Timeouts occur when the device isn't connected, so they're | |
371 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 372 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 373 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
a5b3da54 | 374 | return -ETIMEDOUT; |
a4fc5ed6 KP |
375 | } |
376 | ||
377 | /* Unload any bytes sent back from the other side */ | |
378 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
379 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
380 | if (recv_bytes > recv_size) |
381 | recv_bytes = recv_size; | |
382 | ||
4f7f7b7e CW |
383 | for (i = 0; i < recv_bytes; i += 4) |
384 | unpack_aux(I915_READ(ch_data + i), | |
385 | recv + i, recv_bytes - i); | |
a4fc5ed6 KP |
386 | |
387 | return recv_bytes; | |
388 | } | |
389 | ||
390 | /* Write data to the aux channel in native mode */ | |
391 | static int | |
ea5b213a | 392 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
393 | uint16_t address, uint8_t *send, int send_bytes) |
394 | { | |
395 | int ret; | |
396 | uint8_t msg[20]; | |
397 | int msg_bytes; | |
398 | uint8_t ack; | |
399 | ||
400 | if (send_bytes > 16) | |
401 | return -1; | |
402 | msg[0] = AUX_NATIVE_WRITE << 4; | |
403 | msg[1] = address >> 8; | |
eebc863e | 404 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
405 | msg[3] = send_bytes - 1; |
406 | memcpy(&msg[4], send, send_bytes); | |
407 | msg_bytes = send_bytes + 4; | |
408 | for (;;) { | |
ea5b213a | 409 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
410 | if (ret < 0) |
411 | return ret; | |
412 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
413 | break; | |
414 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
415 | udelay(100); | |
416 | else | |
a5b3da54 | 417 | return -EIO; |
a4fc5ed6 KP |
418 | } |
419 | return send_bytes; | |
420 | } | |
421 | ||
422 | /* Write a single byte to the aux channel in native mode */ | |
423 | static int | |
ea5b213a | 424 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
425 | uint16_t address, uint8_t byte) |
426 | { | |
ea5b213a | 427 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
428 | } |
429 | ||
430 | /* read bytes from a native aux channel */ | |
431 | static int | |
ea5b213a | 432 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
433 | uint16_t address, uint8_t *recv, int recv_bytes) |
434 | { | |
435 | uint8_t msg[4]; | |
436 | int msg_bytes; | |
437 | uint8_t reply[20]; | |
438 | int reply_bytes; | |
439 | uint8_t ack; | |
440 | int ret; | |
441 | ||
442 | msg[0] = AUX_NATIVE_READ << 4; | |
443 | msg[1] = address >> 8; | |
444 | msg[2] = address & 0xff; | |
445 | msg[3] = recv_bytes - 1; | |
446 | ||
447 | msg_bytes = 4; | |
448 | reply_bytes = recv_bytes + 1; | |
449 | ||
450 | for (;;) { | |
ea5b213a | 451 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 452 | reply, reply_bytes); |
a5b3da54 KP |
453 | if (ret == 0) |
454 | return -EPROTO; | |
455 | if (ret < 0) | |
a4fc5ed6 KP |
456 | return ret; |
457 | ack = reply[0]; | |
458 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
459 | memcpy(recv, reply + 1, ret - 1); | |
460 | return ret - 1; | |
461 | } | |
462 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
463 | udelay(100); | |
464 | else | |
a5b3da54 | 465 | return -EIO; |
a4fc5ed6 KP |
466 | } |
467 | } | |
468 | ||
469 | static int | |
ab2c0672 DA |
470 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
471 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 472 | { |
ab2c0672 | 473 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
474 | struct intel_dp *intel_dp = container_of(adapter, |
475 | struct intel_dp, | |
476 | adapter); | |
ab2c0672 DA |
477 | uint16_t address = algo_data->address; |
478 | uint8_t msg[5]; | |
479 | uint8_t reply[2]; | |
8316f337 | 480 | unsigned retry; |
ab2c0672 DA |
481 | int msg_bytes; |
482 | int reply_bytes; | |
483 | int ret; | |
484 | ||
485 | /* Set up the command byte */ | |
486 | if (mode & MODE_I2C_READ) | |
487 | msg[0] = AUX_I2C_READ << 4; | |
488 | else | |
489 | msg[0] = AUX_I2C_WRITE << 4; | |
490 | ||
491 | if (!(mode & MODE_I2C_STOP)) | |
492 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 493 | |
ab2c0672 DA |
494 | msg[1] = address >> 8; |
495 | msg[2] = address; | |
496 | ||
497 | switch (mode) { | |
498 | case MODE_I2C_WRITE: | |
499 | msg[3] = 0; | |
500 | msg[4] = write_byte; | |
501 | msg_bytes = 5; | |
502 | reply_bytes = 1; | |
503 | break; | |
504 | case MODE_I2C_READ: | |
505 | msg[3] = 0; | |
506 | msg_bytes = 4; | |
507 | reply_bytes = 2; | |
508 | break; | |
509 | default: | |
510 | msg_bytes = 3; | |
511 | reply_bytes = 1; | |
512 | break; | |
513 | } | |
514 | ||
8316f337 DF |
515 | for (retry = 0; retry < 5; retry++) { |
516 | ret = intel_dp_aux_ch(intel_dp, | |
517 | msg, msg_bytes, | |
518 | reply, reply_bytes); | |
ab2c0672 | 519 | if (ret < 0) { |
3ff99164 | 520 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
521 | return ret; |
522 | } | |
8316f337 DF |
523 | |
524 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { | |
525 | case AUX_NATIVE_REPLY_ACK: | |
526 | /* I2C-over-AUX Reply field is only valid | |
527 | * when paired with AUX ACK. | |
528 | */ | |
529 | break; | |
530 | case AUX_NATIVE_REPLY_NACK: | |
531 | DRM_DEBUG_KMS("aux_ch native nack\n"); | |
532 | return -EREMOTEIO; | |
533 | case AUX_NATIVE_REPLY_DEFER: | |
534 | udelay(100); | |
535 | continue; | |
536 | default: | |
537 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", | |
538 | reply[0]); | |
539 | return -EREMOTEIO; | |
540 | } | |
541 | ||
ab2c0672 DA |
542 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
543 | case AUX_I2C_REPLY_ACK: | |
544 | if (mode == MODE_I2C_READ) { | |
545 | *read_byte = reply[1]; | |
546 | } | |
547 | return reply_bytes - 1; | |
548 | case AUX_I2C_REPLY_NACK: | |
8316f337 | 549 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
ab2c0672 DA |
550 | return -EREMOTEIO; |
551 | case AUX_I2C_REPLY_DEFER: | |
8316f337 | 552 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
ab2c0672 DA |
553 | udelay(100); |
554 | break; | |
555 | default: | |
8316f337 | 556 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
ab2c0672 DA |
557 | return -EREMOTEIO; |
558 | } | |
559 | } | |
8316f337 DF |
560 | |
561 | DRM_ERROR("too many retries, giving up\n"); | |
562 | return -EREMOTEIO; | |
a4fc5ed6 KP |
563 | } |
564 | ||
565 | static int | |
ea5b213a | 566 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 567 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 568 | { |
d54e9d28 | 569 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
570 | intel_dp->algo.running = false; |
571 | intel_dp->algo.address = 0; | |
572 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
573 | ||
574 | memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); | |
575 | intel_dp->adapter.owner = THIS_MODULE; | |
576 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
577 | strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); | |
578 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; | |
579 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
580 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
581 | ||
582 | return i2c_dp_aux_add_bus(&intel_dp->adapter); | |
a4fc5ed6 KP |
583 | } |
584 | ||
585 | static bool | |
586 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
587 | struct drm_display_mode *adjusted_mode) | |
588 | { | |
0d3a1bee ZY |
589 | struct drm_device *dev = encoder->dev; |
590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 591 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4fc5ed6 | 592 | int lane_count, clock; |
ea5b213a CW |
593 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
594 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; | |
a4fc5ed6 KP |
595 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
596 | ||
4d926461 | 597 | if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { |
1d8e1c75 CW |
598 | intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); |
599 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, | |
600 | mode, adjusted_mode); | |
0d3a1bee ZY |
601 | /* |
602 | * the mode->clock is used to calculate the Data&Link M/N | |
603 | * of the pipe. For the eDP the fixed clock should be used. | |
604 | */ | |
605 | mode->clock = dev_priv->panel_fixed_mode->clock; | |
606 | } | |
607 | ||
a4fc5ed6 KP |
608 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
609 | for (clock = 0; clock <= max_clock; clock++) { | |
fe27d53e | 610 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
a4fc5ed6 | 611 | |
ea5b213a | 612 | if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) |
885a5fb5 | 613 | <= link_avail) { |
ea5b213a CW |
614 | intel_dp->link_bw = bws[clock]; |
615 | intel_dp->lane_count = lane_count; | |
616 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
28c97730 ZY |
617 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
618 | "count %d clock %d\n", | |
ea5b213a | 619 | intel_dp->link_bw, intel_dp->lane_count, |
a4fc5ed6 KP |
620 | adjusted_mode->clock); |
621 | return true; | |
622 | } | |
623 | } | |
624 | } | |
fe27d53e | 625 | |
3cf2efb1 CW |
626 | if (is_edp(intel_dp)) { |
627 | /* okay we failed just pick the highest */ | |
628 | intel_dp->lane_count = max_lane_count; | |
629 | intel_dp->link_bw = bws[max_clock]; | |
630 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
631 | DRM_DEBUG_KMS("Force picking display port link bw %02x lane " | |
632 | "count %d clock %d\n", | |
633 | intel_dp->link_bw, intel_dp->lane_count, | |
634 | adjusted_mode->clock); | |
635 | ||
636 | return true; | |
637 | } | |
638 | ||
a4fc5ed6 KP |
639 | return false; |
640 | } | |
641 | ||
642 | struct intel_dp_m_n { | |
643 | uint32_t tu; | |
644 | uint32_t gmch_m; | |
645 | uint32_t gmch_n; | |
646 | uint32_t link_m; | |
647 | uint32_t link_n; | |
648 | }; | |
649 | ||
650 | static void | |
651 | intel_reduce_ratio(uint32_t *num, uint32_t *den) | |
652 | { | |
653 | while (*num > 0xffffff || *den > 0xffffff) { | |
654 | *num >>= 1; | |
655 | *den >>= 1; | |
656 | } | |
657 | } | |
658 | ||
659 | static void | |
36e83a18 | 660 | intel_dp_compute_m_n(int bpp, |
a4fc5ed6 KP |
661 | int nlanes, |
662 | int pixel_clock, | |
663 | int link_clock, | |
664 | struct intel_dp_m_n *m_n) | |
665 | { | |
666 | m_n->tu = 64; | |
36e83a18 | 667 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
a4fc5ed6 KP |
668 | m_n->gmch_n = link_clock * nlanes; |
669 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
670 | m_n->link_m = pixel_clock; | |
671 | m_n->link_n = link_clock; | |
672 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
673 | } | |
674 | ||
675 | void | |
676 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
677 | struct drm_display_mode *adjusted_mode) | |
678 | { | |
679 | struct drm_device *dev = crtc->dev; | |
680 | struct drm_mode_config *mode_config = &dev->mode_config; | |
55f78c43 | 681 | struct drm_encoder *encoder; |
a4fc5ed6 KP |
682 | struct drm_i915_private *dev_priv = dev->dev_private; |
683 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
36e83a18 | 684 | int lane_count = 4, bpp = 24; |
a4fc5ed6 | 685 | struct intel_dp_m_n m_n; |
9db4a9c7 | 686 | int pipe = intel_crtc->pipe; |
a4fc5ed6 KP |
687 | |
688 | /* | |
21d40d37 | 689 | * Find the lane count in the intel_encoder private |
a4fc5ed6 | 690 | */ |
55f78c43 | 691 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
ea5b213a | 692 | struct intel_dp *intel_dp; |
a4fc5ed6 | 693 | |
d8201ab6 | 694 | if (encoder->crtc != crtc) |
a4fc5ed6 KP |
695 | continue; |
696 | ||
ea5b213a CW |
697 | intel_dp = enc_to_intel_dp(encoder); |
698 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
699 | lane_count = intel_dp->lane_count; | |
51190667 JB |
700 | break; |
701 | } else if (is_edp(intel_dp)) { | |
702 | lane_count = dev_priv->edp.lanes; | |
703 | bpp = dev_priv->edp.bpp; | |
a4fc5ed6 KP |
704 | break; |
705 | } | |
706 | } | |
707 | ||
708 | /* | |
709 | * Compute the GMCH and Link ratios. The '3' here is | |
710 | * the number of bytes_per_pixel post-LUT, which we always | |
711 | * set up for 8-bits of R/G/B, or 3 bytes total. | |
712 | */ | |
36e83a18 | 713 | intel_dp_compute_m_n(bpp, lane_count, |
a4fc5ed6 KP |
714 | mode->clock, adjusted_mode->clock, &m_n); |
715 | ||
c619eed4 | 716 | if (HAS_PCH_SPLIT(dev)) { |
9db4a9c7 JB |
717 | I915_WRITE(TRANSDATA_M1(pipe), |
718 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
719 | m_n.gmch_m); | |
720 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); | |
721 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); | |
722 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); | |
a4fc5ed6 | 723 | } else { |
9db4a9c7 JB |
724 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
725 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
726 | m_n.gmch_m); | |
727 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); | |
728 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); | |
729 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); | |
a4fc5ed6 KP |
730 | } |
731 | } | |
732 | ||
733 | static void | |
734 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
735 | struct drm_display_mode *adjusted_mode) | |
736 | { | |
e3421a18 | 737 | struct drm_device *dev = encoder->dev; |
ea5b213a | 738 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4ef69c7a | 739 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
a4fc5ed6 KP |
740 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
741 | ||
e953fd7b CW |
742 | intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
743 | intel_dp->DP |= intel_dp->color_range; | |
9c9e7927 AJ |
744 | |
745 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
ea5b213a | 746 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
9c9e7927 | 747 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
ea5b213a | 748 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
a4fc5ed6 | 749 | |
cfcb0fc9 | 750 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
ea5b213a | 751 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3421a18 | 752 | else |
ea5b213a | 753 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
a4fc5ed6 | 754 | |
ea5b213a | 755 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 756 | case 1: |
ea5b213a | 757 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
758 | break; |
759 | case 2: | |
ea5b213a | 760 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
761 | break; |
762 | case 4: | |
ea5b213a | 763 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
764 | break; |
765 | } | |
ea5b213a CW |
766 | if (intel_dp->has_audio) |
767 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; | |
a4fc5ed6 | 768 | |
ea5b213a CW |
769 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
770 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
771 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
a4fc5ed6 KP |
772 | |
773 | /* | |
9962c925 | 774 | * Check for DPCD version > 1.1 and enhanced framing support |
a4fc5ed6 | 775 | */ |
7183dc29 JB |
776 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
777 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { | |
ea5b213a CW |
778 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
779 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
a4fc5ed6 KP |
780 | } |
781 | ||
e3421a18 ZW |
782 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ |
783 | if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) | |
ea5b213a | 784 | intel_dp->DP |= DP_PIPEB_SELECT; |
32f9d658 | 785 | |
895692be | 786 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
32f9d658 | 787 | /* don't miss out required setting for eDP */ |
ea5b213a | 788 | intel_dp->DP |= DP_PLL_ENABLE; |
32f9d658 | 789 | if (adjusted_mode->clock < 200000) |
ea5b213a | 790 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
32f9d658 | 791 | else |
ea5b213a | 792 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
32f9d658 | 793 | } |
a4fc5ed6 KP |
794 | } |
795 | ||
5d613501 JB |
796 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
797 | { | |
798 | struct drm_device *dev = intel_dp->base.base.dev; | |
799 | struct drm_i915_private *dev_priv = dev->dev_private; | |
800 | u32 pp; | |
801 | ||
802 | /* | |
803 | * If the panel wasn't on, make sure there's not a currently | |
804 | * active PP sequence before enabling AUX VDD. | |
805 | */ | |
806 | if (!(I915_READ(PCH_PP_STATUS) & PP_ON)) | |
807 | msleep(dev_priv->panel_t3); | |
808 | ||
809 | pp = I915_READ(PCH_PP_CONTROL); | |
810 | pp |= EDP_FORCE_VDD; | |
811 | I915_WRITE(PCH_PP_CONTROL, pp); | |
812 | POSTING_READ(PCH_PP_CONTROL); | |
813 | } | |
814 | ||
815 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp) | |
816 | { | |
817 | struct drm_device *dev = intel_dp->base.base.dev; | |
818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
819 | u32 pp; | |
820 | ||
821 | pp = I915_READ(PCH_PP_CONTROL); | |
822 | pp &= ~EDP_FORCE_VDD; | |
823 | I915_WRITE(PCH_PP_CONTROL, pp); | |
824 | POSTING_READ(PCH_PP_CONTROL); | |
825 | ||
826 | /* Make sure sequencer is idle before allowing subsequent activity */ | |
827 | msleep(dev_priv->panel_t12); | |
828 | } | |
829 | ||
7eaf5547 | 830 | /* Returns true if the panel was already on when called */ |
01cb9ea6 | 831 | static bool ironlake_edp_panel_on (struct intel_dp *intel_dp) |
9934c132 | 832 | { |
01cb9ea6 | 833 | struct drm_device *dev = intel_dp->base.base.dev; |
9934c132 | 834 | struct drm_i915_private *dev_priv = dev->dev_private; |
01cb9ea6 | 835 | u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE; |
9934c132 | 836 | |
913d8d11 | 837 | if (I915_READ(PCH_PP_STATUS) & PP_ON) |
7eaf5547 | 838 | return true; |
9934c132 JB |
839 | |
840 | pp = I915_READ(PCH_PP_CONTROL); | |
37c6c9b0 JB |
841 | |
842 | /* ILK workaround: disable reset around power sequence */ | |
843 | pp &= ~PANEL_POWER_RESET; | |
844 | I915_WRITE(PCH_PP_CONTROL, pp); | |
845 | POSTING_READ(PCH_PP_CONTROL); | |
846 | ||
01cb9ea6 | 847 | pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; |
9934c132 | 848 | I915_WRITE(PCH_PP_CONTROL, pp); |
01cb9ea6 | 849 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 | 850 | |
01cb9ea6 JB |
851 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, |
852 | 5000)) | |
913d8d11 CW |
853 | DRM_ERROR("panel on wait timed out: 0x%08x\n", |
854 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 855 | |
37c6c9b0 | 856 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 857 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 858 | POSTING_READ(PCH_PP_CONTROL); |
7eaf5547 JB |
859 | |
860 | return false; | |
9934c132 JB |
861 | } |
862 | ||
863 | static void ironlake_edp_panel_off (struct drm_device *dev) | |
864 | { | |
865 | struct drm_i915_private *dev_priv = dev->dev_private; | |
01cb9ea6 JB |
866 | u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | |
867 | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK; | |
9934c132 JB |
868 | |
869 | pp = I915_READ(PCH_PP_CONTROL); | |
37c6c9b0 JB |
870 | |
871 | /* ILK workaround: disable reset around power sequence */ | |
872 | pp &= ~PANEL_POWER_RESET; | |
873 | I915_WRITE(PCH_PP_CONTROL, pp); | |
874 | POSTING_READ(PCH_PP_CONTROL); | |
875 | ||
9934c132 JB |
876 | pp &= ~POWER_TARGET_ON; |
877 | I915_WRITE(PCH_PP_CONTROL, pp); | |
01cb9ea6 | 878 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 | 879 | |
01cb9ea6 | 880 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000)) |
913d8d11 CW |
881 | DRM_ERROR("panel off wait timed out: 0x%08x\n", |
882 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 883 | |
3969c9c9 | 884 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 885 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 886 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 JB |
887 | } |
888 | ||
f2b115e6 | 889 | static void ironlake_edp_backlight_on (struct drm_device *dev) |
32f9d658 ZW |
890 | { |
891 | struct drm_i915_private *dev_priv = dev->dev_private; | |
892 | u32 pp; | |
893 | ||
28c97730 | 894 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
895 | /* |
896 | * If we enable the backlight right away following a panel power | |
897 | * on, we may see slight flicker as the panel syncs with the eDP | |
898 | * link. So delay a bit to make sure the image is solid before | |
899 | * allowing it to appear. | |
900 | */ | |
901 | msleep(300); | |
32f9d658 ZW |
902 | pp = I915_READ(PCH_PP_CONTROL); |
903 | pp |= EDP_BLC_ENABLE; | |
904 | I915_WRITE(PCH_PP_CONTROL, pp); | |
905 | } | |
906 | ||
f2b115e6 | 907 | static void ironlake_edp_backlight_off (struct drm_device *dev) |
32f9d658 ZW |
908 | { |
909 | struct drm_i915_private *dev_priv = dev->dev_private; | |
910 | u32 pp; | |
911 | ||
28c97730 | 912 | DRM_DEBUG_KMS("\n"); |
32f9d658 ZW |
913 | pp = I915_READ(PCH_PP_CONTROL); |
914 | pp &= ~EDP_BLC_ENABLE; | |
915 | I915_WRITE(PCH_PP_CONTROL, pp); | |
916 | } | |
a4fc5ed6 | 917 | |
d240f20f JB |
918 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
919 | { | |
920 | struct drm_device *dev = encoder->dev; | |
921 | struct drm_i915_private *dev_priv = dev->dev_private; | |
922 | u32 dpa_ctl; | |
923 | ||
924 | DRM_DEBUG_KMS("\n"); | |
925 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 926 | dpa_ctl |= DP_PLL_ENABLE; |
d240f20f | 927 | I915_WRITE(DP_A, dpa_ctl); |
298b0b39 JB |
928 | POSTING_READ(DP_A); |
929 | udelay(200); | |
d240f20f JB |
930 | } |
931 | ||
932 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) | |
933 | { | |
934 | struct drm_device *dev = encoder->dev; | |
935 | struct drm_i915_private *dev_priv = dev->dev_private; | |
936 | u32 dpa_ctl; | |
937 | ||
938 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 939 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 940 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 941 | POSTING_READ(DP_A); |
d240f20f JB |
942 | udelay(200); |
943 | } | |
944 | ||
c7ad3810 JB |
945 | /* If the sink supports it, try to set the power state appropriately */ |
946 | static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) | |
947 | { | |
948 | int ret, i; | |
949 | ||
950 | /* Should have a valid DPCD by this point */ | |
951 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
952 | return; | |
953 | ||
954 | if (mode != DRM_MODE_DPMS_ON) { | |
955 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, | |
956 | DP_SET_POWER_D3); | |
957 | if (ret != 1) | |
958 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
959 | } else { | |
960 | /* | |
961 | * When turning on, we need to retry for 1ms to give the sink | |
962 | * time to wake up. | |
963 | */ | |
964 | for (i = 0; i < 3; i++) { | |
965 | ret = intel_dp_aux_native_write_1(intel_dp, | |
966 | DP_SET_POWER, | |
967 | DP_SET_POWER_D0); | |
968 | if (ret == 1) | |
969 | break; | |
970 | msleep(1); | |
971 | } | |
972 | } | |
973 | } | |
974 | ||
d240f20f JB |
975 | static void intel_dp_prepare(struct drm_encoder *encoder) |
976 | { | |
977 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
978 | struct drm_device *dev = encoder->dev; | |
d240f20f | 979 | |
c7ad3810 JB |
980 | /* Wake up the sink first */ |
981 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
982 | ||
4d926461 | 983 | if (is_edp(intel_dp)) { |
d240f20f | 984 | ironlake_edp_backlight_off(dev); |
5d613501 | 985 | ironlake_edp_panel_off(dev); |
01cb9ea6 JB |
986 | if (!is_pch_edp(intel_dp)) |
987 | ironlake_edp_pll_on(encoder); | |
988 | else | |
989 | ironlake_edp_pll_off(encoder); | |
d240f20f | 990 | } |
736085bc | 991 | intel_dp_link_down(intel_dp); |
d240f20f JB |
992 | } |
993 | ||
994 | static void intel_dp_commit(struct drm_encoder *encoder) | |
995 | { | |
996 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
997 | struct drm_device *dev = encoder->dev; | |
d240f20f | 998 | |
5d613501 JB |
999 | if (is_edp(intel_dp)) |
1000 | ironlake_edp_panel_vdd_on(intel_dp); | |
1001 | ||
33a34e4e JB |
1002 | intel_dp_start_link_train(intel_dp); |
1003 | ||
5d613501 | 1004 | if (is_edp(intel_dp)) { |
01cb9ea6 | 1005 | ironlake_edp_panel_on(intel_dp); |
5d613501 JB |
1006 | ironlake_edp_panel_vdd_off(intel_dp); |
1007 | } | |
33a34e4e JB |
1008 | |
1009 | intel_dp_complete_link_train(intel_dp); | |
1010 | ||
4d926461 | 1011 | if (is_edp(intel_dp)) |
d240f20f JB |
1012 | ironlake_edp_backlight_on(dev); |
1013 | } | |
1014 | ||
a4fc5ed6 KP |
1015 | static void |
1016 | intel_dp_dpms(struct drm_encoder *encoder, int mode) | |
1017 | { | |
ea5b213a | 1018 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
55f78c43 | 1019 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 | 1020 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1021 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
a4fc5ed6 KP |
1022 | |
1023 | if (mode != DRM_MODE_DPMS_ON) { | |
01cb9ea6 | 1024 | if (is_edp(intel_dp)) |
7643a7fa | 1025 | ironlake_edp_backlight_off(dev); |
c7ad3810 | 1026 | intel_dp_sink_dpms(intel_dp, mode); |
736085bc | 1027 | intel_dp_link_down(intel_dp); |
4d926461 | 1028 | if (is_edp(intel_dp)) |
01cb9ea6 JB |
1029 | ironlake_edp_panel_off(dev); |
1030 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) | |
d240f20f | 1031 | ironlake_edp_pll_off(encoder); |
a4fc5ed6 | 1032 | } else { |
736085bc | 1033 | if (is_edp(intel_dp)) |
5d613501 | 1034 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1035 | intel_dp_sink_dpms(intel_dp, mode); |
32f9d658 | 1036 | if (!(dp_reg & DP_PORT_EN)) { |
01cb9ea6 | 1037 | intel_dp_start_link_train(intel_dp); |
5d613501 JB |
1038 | if (is_edp(intel_dp)) { |
1039 | ironlake_edp_panel_on(intel_dp); | |
1040 | ironlake_edp_panel_vdd_off(intel_dp); | |
1041 | } | |
33a34e4e | 1042 | intel_dp_complete_link_train(intel_dp); |
32f9d658 | 1043 | } |
736085bc JB |
1044 | if (is_edp(intel_dp)) |
1045 | ironlake_edp_backlight_on(dev); | |
a4fc5ed6 KP |
1046 | } |
1047 | } | |
1048 | ||
1049 | /* | |
df0c237d JB |
1050 | * Native read with retry for link status and receiver capability reads for |
1051 | * cases where the sink may still be asleep. | |
a4fc5ed6 KP |
1052 | */ |
1053 | static bool | |
df0c237d JB |
1054 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
1055 | uint8_t *recv, int recv_bytes) | |
a4fc5ed6 | 1056 | { |
61da5fab JB |
1057 | int ret, i; |
1058 | ||
df0c237d JB |
1059 | /* |
1060 | * Sinks are *supposed* to come up within 1ms from an off state, | |
1061 | * but we're also supposed to retry 3 times per the spec. | |
1062 | */ | |
61da5fab | 1063 | for (i = 0; i < 3; i++) { |
df0c237d JB |
1064 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
1065 | recv_bytes); | |
1066 | if (ret == recv_bytes) | |
61da5fab JB |
1067 | return true; |
1068 | msleep(1); | |
1069 | } | |
a4fc5ed6 | 1070 | |
61da5fab | 1071 | return false; |
a4fc5ed6 KP |
1072 | } |
1073 | ||
df0c237d JB |
1074 | /* |
1075 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
1076 | * link status information | |
1077 | */ | |
1078 | static bool | |
1079 | intel_dp_get_link_status(struct intel_dp *intel_dp) | |
1080 | { | |
1081 | return intel_dp_aux_native_read_retry(intel_dp, | |
1082 | DP_LANE0_1_STATUS, | |
1083 | intel_dp->link_status, | |
1084 | DP_LINK_STATUS_SIZE); | |
1085 | } | |
1086 | ||
a4fc5ed6 KP |
1087 | static uint8_t |
1088 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1089 | int r) | |
1090 | { | |
1091 | return link_status[r - DP_LANE0_1_STATUS]; | |
1092 | } | |
1093 | ||
a4fc5ed6 KP |
1094 | static uint8_t |
1095 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1096 | int lane) | |
1097 | { | |
1098 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
1099 | int s = ((lane & 1) ? | |
1100 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
1101 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
1102 | uint8_t l = intel_dp_link_status(link_status, i); | |
1103 | ||
1104 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
1105 | } | |
1106 | ||
1107 | static uint8_t | |
1108 | intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1109 | int lane) | |
1110 | { | |
1111 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
1112 | int s = ((lane & 1) ? | |
1113 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
1114 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
1115 | uint8_t l = intel_dp_link_status(link_status, i); | |
1116 | ||
1117 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
1118 | } | |
1119 | ||
1120 | ||
1121 | #if 0 | |
1122 | static char *voltage_names[] = { | |
1123 | "0.4V", "0.6V", "0.8V", "1.2V" | |
1124 | }; | |
1125 | static char *pre_emph_names[] = { | |
1126 | "0dB", "3.5dB", "6dB", "9.5dB" | |
1127 | }; | |
1128 | static char *link_train_names[] = { | |
1129 | "pattern 1", "pattern 2", "idle", "off" | |
1130 | }; | |
1131 | #endif | |
1132 | ||
1133 | /* | |
1134 | * These are source-specific values; current Intel hardware supports | |
1135 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1136 | */ | |
1137 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 | |
1138 | ||
1139 | static uint8_t | |
1140 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) | |
1141 | { | |
1142 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1143 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1144 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1145 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1146 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1147 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1148 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1149 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1150 | default: | |
1151 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1152 | } | |
1153 | } | |
1154 | ||
1155 | static void | |
33a34e4e | 1156 | intel_get_adjust_train(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1157 | { |
1158 | uint8_t v = 0; | |
1159 | uint8_t p = 0; | |
1160 | int lane; | |
1161 | ||
33a34e4e JB |
1162 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1163 | uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane); | |
1164 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1165 | |
1166 | if (this_v > v) | |
1167 | v = this_v; | |
1168 | if (this_p > p) | |
1169 | p = this_p; | |
1170 | } | |
1171 | ||
1172 | if (v >= I830_DP_VOLTAGE_MAX) | |
1173 | v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; | |
1174 | ||
1175 | if (p >= intel_dp_pre_emphasis_max(v)) | |
1176 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
1177 | ||
1178 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 1179 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
1180 | } |
1181 | ||
1182 | static uint32_t | |
3cf2efb1 | 1183 | intel_dp_signal_levels(uint8_t train_set, int lane_count) |
a4fc5ed6 | 1184 | { |
3cf2efb1 | 1185 | uint32_t signal_levels = 0; |
a4fc5ed6 | 1186 | |
3cf2efb1 | 1187 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
1188 | case DP_TRAIN_VOLTAGE_SWING_400: |
1189 | default: | |
1190 | signal_levels |= DP_VOLTAGE_0_4; | |
1191 | break; | |
1192 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1193 | signal_levels |= DP_VOLTAGE_0_6; | |
1194 | break; | |
1195 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1196 | signal_levels |= DP_VOLTAGE_0_8; | |
1197 | break; | |
1198 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1199 | signal_levels |= DP_VOLTAGE_1_2; | |
1200 | break; | |
1201 | } | |
3cf2efb1 | 1202 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
1203 | case DP_TRAIN_PRE_EMPHASIS_0: |
1204 | default: | |
1205 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1206 | break; | |
1207 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1208 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1209 | break; | |
1210 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1211 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1212 | break; | |
1213 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1214 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1215 | break; | |
1216 | } | |
1217 | return signal_levels; | |
1218 | } | |
1219 | ||
e3421a18 ZW |
1220 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1221 | static uint32_t | |
1222 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1223 | { | |
3c5a62b5 YL |
1224 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1225 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1226 | switch (signal_levels) { | |
e3421a18 | 1227 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1228 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
1229 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
1230 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1231 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 1232 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
1233 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
1234 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 1235 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
1236 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
1237 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 1238 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1239 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
1240 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 1241 | default: |
3c5a62b5 YL |
1242 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
1243 | "0x%x\n", signal_levels); | |
1244 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
1245 | } |
1246 | } | |
1247 | ||
a4fc5ed6 KP |
1248 | static uint8_t |
1249 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1250 | int lane) | |
1251 | { | |
1252 | int i = DP_LANE0_1_STATUS + (lane >> 1); | |
1253 | int s = (lane & 1) * 4; | |
1254 | uint8_t l = intel_dp_link_status(link_status, i); | |
1255 | ||
1256 | return (l >> s) & 0xf; | |
1257 | } | |
1258 | ||
1259 | /* Check for clock recovery is done on all channels */ | |
1260 | static bool | |
1261 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1262 | { | |
1263 | int lane; | |
1264 | uint8_t lane_status; | |
1265 | ||
1266 | for (lane = 0; lane < lane_count; lane++) { | |
1267 | lane_status = intel_get_lane_status(link_status, lane); | |
1268 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
1269 | return false; | |
1270 | } | |
1271 | return true; | |
1272 | } | |
1273 | ||
1274 | /* Check to see if channel eq is done on all channels */ | |
1275 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ | |
1276 | DP_LANE_CHANNEL_EQ_DONE|\ | |
1277 | DP_LANE_SYMBOL_LOCKED) | |
1278 | static bool | |
33a34e4e | 1279 | intel_channel_eq_ok(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1280 | { |
1281 | uint8_t lane_align; | |
1282 | uint8_t lane_status; | |
1283 | int lane; | |
1284 | ||
33a34e4e | 1285 | lane_align = intel_dp_link_status(intel_dp->link_status, |
a4fc5ed6 KP |
1286 | DP_LANE_ALIGN_STATUS_UPDATED); |
1287 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
1288 | return false; | |
33a34e4e JB |
1289 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1290 | lane_status = intel_get_lane_status(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1291 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
1292 | return false; | |
1293 | } | |
1294 | return true; | |
1295 | } | |
1296 | ||
1297 | static bool | |
ea5b213a | 1298 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 | 1299 | uint32_t dp_reg_value, |
58e10eb9 | 1300 | uint8_t dp_train_pat) |
a4fc5ed6 | 1301 | { |
4ef69c7a | 1302 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1303 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1304 | int ret; |
1305 | ||
ea5b213a CW |
1306 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1307 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1308 | |
ea5b213a | 1309 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1310 | DP_TRAINING_PATTERN_SET, |
1311 | dp_train_pat); | |
1312 | ||
ea5b213a | 1313 | ret = intel_dp_aux_native_write(intel_dp, |
58e10eb9 CW |
1314 | DP_TRAINING_LANE0_SET, |
1315 | intel_dp->train_set, 4); | |
a4fc5ed6 KP |
1316 | if (ret != 4) |
1317 | return false; | |
1318 | ||
1319 | return true; | |
1320 | } | |
1321 | ||
33a34e4e | 1322 | /* Enable corresponding port and start training pattern 1 */ |
a4fc5ed6 | 1323 | static void |
33a34e4e | 1324 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1325 | { |
4ef69c7a | 1326 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1327 | struct drm_i915_private *dev_priv = dev->dev_private; |
58e10eb9 | 1328 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); |
a4fc5ed6 KP |
1329 | int i; |
1330 | uint8_t voltage; | |
1331 | bool clock_recovery = false; | |
a4fc5ed6 | 1332 | int tries; |
e3421a18 | 1333 | u32 reg; |
ea5b213a | 1334 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1335 | |
b99a9d9b KP |
1336 | /* Enable output, wait for it to become active */ |
1337 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
1338 | POSTING_READ(intel_dp->output_reg); | |
1339 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
a4fc5ed6 | 1340 | |
3cf2efb1 CW |
1341 | /* Write the link configuration data */ |
1342 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, | |
1343 | intel_dp->link_configuration, | |
1344 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
1345 | |
1346 | DP |= DP_PORT_EN; | |
cfcb0fc9 | 1347 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1348 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1349 | else | |
1350 | DP &= ~DP_LINK_TRAIN_MASK; | |
33a34e4e | 1351 | memset(intel_dp->train_set, 0, 4); |
a4fc5ed6 KP |
1352 | voltage = 0xff; |
1353 | tries = 0; | |
1354 | clock_recovery = false; | |
1355 | for (;;) { | |
33a34e4e | 1356 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 | 1357 | uint32_t signal_levels; |
cfcb0fc9 | 1358 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
33a34e4e | 1359 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1360 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1361 | } else { | |
3cf2efb1 | 1362 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1363 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1364 | } | |
a4fc5ed6 | 1365 | |
cfcb0fc9 | 1366 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1367 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
1368 | else | |
1369 | reg = DP | DP_LINK_TRAIN_PAT_1; | |
1370 | ||
ea5b213a | 1371 | if (!intel_dp_set_link_train(intel_dp, reg, |
58e10eb9 | 1372 | DP_TRAINING_PATTERN_1)) |
a4fc5ed6 | 1373 | break; |
a4fc5ed6 KP |
1374 | /* Set training pattern 1 */ |
1375 | ||
3cf2efb1 CW |
1376 | udelay(100); |
1377 | if (!intel_dp_get_link_status(intel_dp)) | |
a4fc5ed6 | 1378 | break; |
a4fc5ed6 | 1379 | |
3cf2efb1 CW |
1380 | if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { |
1381 | clock_recovery = true; | |
1382 | break; | |
1383 | } | |
1384 | ||
1385 | /* Check to see if we've tried the max voltage */ | |
1386 | for (i = 0; i < intel_dp->lane_count; i++) | |
1387 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 1388 | break; |
3cf2efb1 CW |
1389 | if (i == intel_dp->lane_count) |
1390 | break; | |
a4fc5ed6 | 1391 | |
3cf2efb1 CW |
1392 | /* Check to see if we've tried the same voltage 5 times */ |
1393 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { | |
1394 | ++tries; | |
1395 | if (tries == 5) | |
a4fc5ed6 | 1396 | break; |
3cf2efb1 CW |
1397 | } else |
1398 | tries = 0; | |
1399 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 1400 | |
3cf2efb1 CW |
1401 | /* Compute new intel_dp->train_set as requested by target */ |
1402 | intel_get_adjust_train(intel_dp); | |
a4fc5ed6 KP |
1403 | } |
1404 | ||
33a34e4e JB |
1405 | intel_dp->DP = DP; |
1406 | } | |
1407 | ||
1408 | static void | |
1409 | intel_dp_complete_link_train(struct intel_dp *intel_dp) | |
1410 | { | |
4ef69c7a | 1411 | struct drm_device *dev = intel_dp->base.base.dev; |
33a34e4e JB |
1412 | struct drm_i915_private *dev_priv = dev->dev_private; |
1413 | bool channel_eq = false; | |
37f80975 | 1414 | int tries, cr_tries; |
33a34e4e JB |
1415 | u32 reg; |
1416 | uint32_t DP = intel_dp->DP; | |
1417 | ||
a4fc5ed6 KP |
1418 | /* channel equalization */ |
1419 | tries = 0; | |
37f80975 | 1420 | cr_tries = 0; |
a4fc5ed6 KP |
1421 | channel_eq = false; |
1422 | for (;;) { | |
33a34e4e | 1423 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 ZW |
1424 | uint32_t signal_levels; |
1425 | ||
37f80975 JB |
1426 | if (cr_tries > 5) { |
1427 | DRM_ERROR("failed to train DP, aborting\n"); | |
1428 | intel_dp_link_down(intel_dp); | |
1429 | break; | |
1430 | } | |
1431 | ||
cfcb0fc9 | 1432 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
33a34e4e | 1433 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1434 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1435 | } else { | |
3cf2efb1 | 1436 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1437 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1438 | } | |
1439 | ||
cfcb0fc9 | 1440 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1441 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
1442 | else | |
1443 | reg = DP | DP_LINK_TRAIN_PAT_2; | |
a4fc5ed6 KP |
1444 | |
1445 | /* channel eq pattern */ | |
ea5b213a | 1446 | if (!intel_dp_set_link_train(intel_dp, reg, |
58e10eb9 | 1447 | DP_TRAINING_PATTERN_2)) |
a4fc5ed6 KP |
1448 | break; |
1449 | ||
3cf2efb1 CW |
1450 | udelay(400); |
1451 | if (!intel_dp_get_link_status(intel_dp)) | |
a4fc5ed6 | 1452 | break; |
a4fc5ed6 | 1453 | |
37f80975 JB |
1454 | /* Make sure clock is still ok */ |
1455 | if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { | |
1456 | intel_dp_start_link_train(intel_dp); | |
1457 | cr_tries++; | |
1458 | continue; | |
1459 | } | |
1460 | ||
3cf2efb1 CW |
1461 | if (intel_channel_eq_ok(intel_dp)) { |
1462 | channel_eq = true; | |
1463 | break; | |
1464 | } | |
a4fc5ed6 | 1465 | |
37f80975 JB |
1466 | /* Try 5 times, then try clock recovery if that fails */ |
1467 | if (tries > 5) { | |
1468 | intel_dp_link_down(intel_dp); | |
1469 | intel_dp_start_link_train(intel_dp); | |
1470 | tries = 0; | |
1471 | cr_tries++; | |
1472 | continue; | |
1473 | } | |
a4fc5ed6 | 1474 | |
3cf2efb1 CW |
1475 | /* Compute new intel_dp->train_set as requested by target */ |
1476 | intel_get_adjust_train(intel_dp); | |
1477 | ++tries; | |
869184a6 | 1478 | } |
3cf2efb1 | 1479 | |
cfcb0fc9 | 1480 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1481 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
1482 | else | |
1483 | reg = DP | DP_LINK_TRAIN_OFF; | |
1484 | ||
ea5b213a CW |
1485 | I915_WRITE(intel_dp->output_reg, reg); |
1486 | POSTING_READ(intel_dp->output_reg); | |
1487 | intel_dp_aux_native_write_1(intel_dp, | |
a4fc5ed6 KP |
1488 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
1489 | } | |
1490 | ||
1491 | static void | |
ea5b213a | 1492 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 1493 | { |
4ef69c7a | 1494 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1495 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1496 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1497 | |
1b39d6f3 CW |
1498 | if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) |
1499 | return; | |
1500 | ||
28c97730 | 1501 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1502 | |
cfcb0fc9 | 1503 | if (is_edp(intel_dp)) { |
32f9d658 | 1504 | DP &= ~DP_PLL_ENABLE; |
ea5b213a CW |
1505 | I915_WRITE(intel_dp->output_reg, DP); |
1506 | POSTING_READ(intel_dp->output_reg); | |
32f9d658 ZW |
1507 | udelay(100); |
1508 | } | |
1509 | ||
cfcb0fc9 | 1510 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) { |
e3421a18 | 1511 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 1512 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
1513 | } else { |
1514 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 1515 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 1516 | } |
fe255d00 | 1517 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 1518 | |
fe255d00 | 1519 | msleep(17); |
5eb08b69 | 1520 | |
cfcb0fc9 | 1521 | if (is_edp(intel_dp)) |
32f9d658 | 1522 | DP |= DP_LINK_TRAIN_OFF; |
5bddd17f | 1523 | |
1b39d6f3 CW |
1524 | if (!HAS_PCH_CPT(dev) && |
1525 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { | |
31acbcc4 CW |
1526 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
1527 | ||
5bddd17f EA |
1528 | /* Hardware workaround: leaving our transcoder select |
1529 | * set to transcoder B while it's off will prevent the | |
1530 | * corresponding HDMI output on transcoder A. | |
1531 | * | |
1532 | * Combine this with another hardware workaround: | |
1533 | * transcoder select bit can only be cleared while the | |
1534 | * port is enabled. | |
1535 | */ | |
1536 | DP &= ~DP_PIPEB_SELECT; | |
1537 | I915_WRITE(intel_dp->output_reg, DP); | |
1538 | ||
1539 | /* Changes to enable or select take place the vblank | |
1540 | * after being written. | |
1541 | */ | |
31acbcc4 CW |
1542 | if (crtc == NULL) { |
1543 | /* We can arrive here never having been attached | |
1544 | * to a CRTC, for instance, due to inheriting | |
1545 | * random state from the BIOS. | |
1546 | * | |
1547 | * If the pipe is not running, play safe and | |
1548 | * wait for the clocks to stabilise before | |
1549 | * continuing. | |
1550 | */ | |
1551 | POSTING_READ(intel_dp->output_reg); | |
1552 | msleep(50); | |
1553 | } else | |
1554 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
5bddd17f EA |
1555 | } |
1556 | ||
ea5b213a CW |
1557 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
1558 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 KP |
1559 | } |
1560 | ||
a4fc5ed6 KP |
1561 | /* |
1562 | * According to DP spec | |
1563 | * 5.1.2: | |
1564 | * 1. Read DPCD | |
1565 | * 2. Configure link according to Receiver Capabilities | |
1566 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
1567 | * 4. Check link status on receipt of hot-plug interrupt | |
1568 | */ | |
1569 | ||
1570 | static void | |
ea5b213a | 1571 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1572 | { |
59cd09e1 JB |
1573 | int ret; |
1574 | ||
4ef69c7a | 1575 | if (!intel_dp->base.base.crtc) |
a4fc5ed6 KP |
1576 | return; |
1577 | ||
33a34e4e | 1578 | if (!intel_dp_get_link_status(intel_dp)) { |
ea5b213a | 1579 | intel_dp_link_down(intel_dp); |
a4fc5ed6 KP |
1580 | return; |
1581 | } | |
1582 | ||
59cd09e1 JB |
1583 | /* Try to read receiver status if the link appears to be up */ |
1584 | ret = intel_dp_aux_native_read(intel_dp, | |
1585 | 0x000, intel_dp->dpcd, | |
1586 | sizeof (intel_dp->dpcd)); | |
1587 | if (ret != sizeof(intel_dp->dpcd)) { | |
1588 | intel_dp_link_down(intel_dp); | |
1589 | return; | |
1590 | } | |
1591 | ||
33a34e4e JB |
1592 | if (!intel_channel_eq_ok(intel_dp)) { |
1593 | intel_dp_start_link_train(intel_dp); | |
1594 | intel_dp_complete_link_train(intel_dp); | |
1595 | } | |
a4fc5ed6 | 1596 | } |
a4fc5ed6 | 1597 | |
5eb08b69 | 1598 | static enum drm_connector_status |
a9756bb5 | 1599 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 1600 | { |
5eb08b69 | 1601 | enum drm_connector_status status; |
df0c237d | 1602 | bool ret; |
5eb08b69 | 1603 | |
fe16d949 CW |
1604 | /* Can't disconnect eDP, but you can close the lid... */ |
1605 | if (is_edp(intel_dp)) { | |
1606 | status = intel_panel_detect(intel_dp->base.base.dev); | |
1607 | if (status == connector_status_unknown) | |
1608 | status = connector_status_connected; | |
1609 | return status; | |
1610 | } | |
01cb9ea6 | 1611 | |
5eb08b69 | 1612 | status = connector_status_disconnected; |
df0c237d JB |
1613 | ret = intel_dp_aux_native_read_retry(intel_dp, |
1614 | 0x000, intel_dp->dpcd, | |
1615 | sizeof (intel_dp->dpcd)); | |
1616 | if (ret && intel_dp->dpcd[DP_DPCD_REV] != 0) | |
1617 | status = connector_status_connected; | |
ea5b213a CW |
1618 | DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0], |
1619 | intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]); | |
5eb08b69 ZW |
1620 | return status; |
1621 | } | |
1622 | ||
a4fc5ed6 | 1623 | static enum drm_connector_status |
a9756bb5 | 1624 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 1625 | { |
4ef69c7a | 1626 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1627 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 | 1628 | enum drm_connector_status status; |
a9756bb5 | 1629 | uint32_t temp, bit; |
5eb08b69 | 1630 | |
ea5b213a | 1631 | switch (intel_dp->output_reg) { |
a4fc5ed6 KP |
1632 | case DP_B: |
1633 | bit = DPB_HOTPLUG_INT_STATUS; | |
1634 | break; | |
1635 | case DP_C: | |
1636 | bit = DPC_HOTPLUG_INT_STATUS; | |
1637 | break; | |
1638 | case DP_D: | |
1639 | bit = DPD_HOTPLUG_INT_STATUS; | |
1640 | break; | |
1641 | default: | |
1642 | return connector_status_unknown; | |
1643 | } | |
1644 | ||
1645 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
1646 | ||
1647 | if ((temp & bit) == 0) | |
1648 | return connector_status_disconnected; | |
1649 | ||
1650 | status = connector_status_disconnected; | |
a9756bb5 | 1651 | if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd, |
ea5b213a | 1652 | sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) |
a4fc5ed6 | 1653 | { |
7183dc29 | 1654 | if (intel_dp->dpcd[DP_DPCD_REV] != 0) |
a4fc5ed6 KP |
1655 | status = connector_status_connected; |
1656 | } | |
a9756bb5 | 1657 | |
dd2b379f | 1658 | return status; |
a9756bb5 ZW |
1659 | } |
1660 | ||
1661 | /** | |
1662 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. | |
1663 | * | |
1664 | * \return true if DP port is connected. | |
1665 | * \return false if DP port is disconnected. | |
1666 | */ | |
1667 | static enum drm_connector_status | |
1668 | intel_dp_detect(struct drm_connector *connector, bool force) | |
1669 | { | |
1670 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1671 | struct drm_device *dev = intel_dp->base.base.dev; | |
1672 | enum drm_connector_status status; | |
1673 | struct edid *edid = NULL; | |
1674 | ||
1675 | intel_dp->has_audio = false; | |
1676 | ||
1677 | if (HAS_PCH_SPLIT(dev)) | |
1678 | status = ironlake_dp_detect(intel_dp); | |
1679 | else | |
1680 | status = g4x_dp_detect(intel_dp); | |
1681 | if (status != connector_status_connected) | |
1682 | return status; | |
1683 | ||
f684960e CW |
1684 | if (intel_dp->force_audio) { |
1685 | intel_dp->has_audio = intel_dp->force_audio > 0; | |
1686 | } else { | |
1687 | edid = drm_get_edid(connector, &intel_dp->adapter); | |
1688 | if (edid) { | |
1689 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
1690 | connector->display_info.raw_edid = NULL; | |
1691 | kfree(edid); | |
1692 | } | |
a9756bb5 ZW |
1693 | } |
1694 | ||
1695 | return connector_status_connected; | |
a4fc5ed6 KP |
1696 | } |
1697 | ||
1698 | static int intel_dp_get_modes(struct drm_connector *connector) | |
1699 | { | |
df0e9248 | 1700 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4ef69c7a | 1701 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1702 | struct drm_i915_private *dev_priv = dev->dev_private; |
1703 | int ret; | |
a4fc5ed6 KP |
1704 | |
1705 | /* We should parse the EDID data and find out if it has an audio sink | |
1706 | */ | |
1707 | ||
f899fc64 | 1708 | ret = intel_ddc_get_modes(connector, &intel_dp->adapter); |
b9efc480 | 1709 | if (ret) { |
4d926461 | 1710 | if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) { |
b9efc480 ZY |
1711 | struct drm_display_mode *newmode; |
1712 | list_for_each_entry(newmode, &connector->probed_modes, | |
1713 | head) { | |
1714 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
1715 | dev_priv->panel_fixed_mode = | |
1716 | drm_mode_duplicate(dev, newmode); | |
1717 | break; | |
1718 | } | |
1719 | } | |
1720 | } | |
1721 | ||
32f9d658 | 1722 | return ret; |
b9efc480 | 1723 | } |
32f9d658 ZW |
1724 | |
1725 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ | |
4d926461 | 1726 | if (is_edp(intel_dp)) { |
32f9d658 ZW |
1727 | if (dev_priv->panel_fixed_mode != NULL) { |
1728 | struct drm_display_mode *mode; | |
1729 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); | |
1730 | drm_mode_probed_add(connector, mode); | |
1731 | return 1; | |
1732 | } | |
1733 | } | |
1734 | return 0; | |
a4fc5ed6 KP |
1735 | } |
1736 | ||
1aad7ac0 CW |
1737 | static bool |
1738 | intel_dp_detect_audio(struct drm_connector *connector) | |
1739 | { | |
1740 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1741 | struct edid *edid; | |
1742 | bool has_audio = false; | |
1743 | ||
1744 | edid = drm_get_edid(connector, &intel_dp->adapter); | |
1745 | if (edid) { | |
1746 | has_audio = drm_detect_monitor_audio(edid); | |
1747 | ||
1748 | connector->display_info.raw_edid = NULL; | |
1749 | kfree(edid); | |
1750 | } | |
1751 | ||
1752 | return has_audio; | |
1753 | } | |
1754 | ||
f684960e CW |
1755 | static int |
1756 | intel_dp_set_property(struct drm_connector *connector, | |
1757 | struct drm_property *property, | |
1758 | uint64_t val) | |
1759 | { | |
e953fd7b | 1760 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
f684960e CW |
1761 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
1762 | int ret; | |
1763 | ||
1764 | ret = drm_connector_property_set_value(connector, property, val); | |
1765 | if (ret) | |
1766 | return ret; | |
1767 | ||
3f43c48d | 1768 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
1769 | int i = val; |
1770 | bool has_audio; | |
1771 | ||
1772 | if (i == intel_dp->force_audio) | |
f684960e CW |
1773 | return 0; |
1774 | ||
1aad7ac0 | 1775 | intel_dp->force_audio = i; |
f684960e | 1776 | |
1aad7ac0 CW |
1777 | if (i == 0) |
1778 | has_audio = intel_dp_detect_audio(connector); | |
1779 | else | |
1780 | has_audio = i > 0; | |
1781 | ||
1782 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
1783 | return 0; |
1784 | ||
1aad7ac0 | 1785 | intel_dp->has_audio = has_audio; |
f684960e CW |
1786 | goto done; |
1787 | } | |
1788 | ||
e953fd7b CW |
1789 | if (property == dev_priv->broadcast_rgb_property) { |
1790 | if (val == !!intel_dp->color_range) | |
1791 | return 0; | |
1792 | ||
1793 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; | |
1794 | goto done; | |
1795 | } | |
1796 | ||
f684960e CW |
1797 | return -EINVAL; |
1798 | ||
1799 | done: | |
1800 | if (intel_dp->base.base.crtc) { | |
1801 | struct drm_crtc *crtc = intel_dp->base.base.crtc; | |
1802 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
1803 | crtc->x, crtc->y, | |
1804 | crtc->fb); | |
1805 | } | |
1806 | ||
1807 | return 0; | |
1808 | } | |
1809 | ||
a4fc5ed6 KP |
1810 | static void |
1811 | intel_dp_destroy (struct drm_connector *connector) | |
1812 | { | |
a4fc5ed6 KP |
1813 | drm_sysfs_connector_remove(connector); |
1814 | drm_connector_cleanup(connector); | |
55f78c43 | 1815 | kfree(connector); |
a4fc5ed6 KP |
1816 | } |
1817 | ||
24d05927 DV |
1818 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
1819 | { | |
1820 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1821 | ||
1822 | i2c_del_adapter(&intel_dp->adapter); | |
1823 | drm_encoder_cleanup(encoder); | |
1824 | kfree(intel_dp); | |
1825 | } | |
1826 | ||
a4fc5ed6 KP |
1827 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
1828 | .dpms = intel_dp_dpms, | |
1829 | .mode_fixup = intel_dp_mode_fixup, | |
d240f20f | 1830 | .prepare = intel_dp_prepare, |
a4fc5ed6 | 1831 | .mode_set = intel_dp_mode_set, |
d240f20f | 1832 | .commit = intel_dp_commit, |
a4fc5ed6 KP |
1833 | }; |
1834 | ||
1835 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
1836 | .dpms = drm_helper_connector_dpms, | |
a4fc5ed6 KP |
1837 | .detect = intel_dp_detect, |
1838 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 1839 | .set_property = intel_dp_set_property, |
a4fc5ed6 KP |
1840 | .destroy = intel_dp_destroy, |
1841 | }; | |
1842 | ||
1843 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
1844 | .get_modes = intel_dp_get_modes, | |
1845 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 1846 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
1847 | }; |
1848 | ||
a4fc5ed6 | 1849 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 1850 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
1851 | }; |
1852 | ||
995b6762 | 1853 | static void |
21d40d37 | 1854 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 1855 | { |
ea5b213a | 1856 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
c8110e52 | 1857 | |
885a5014 | 1858 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 1859 | } |
6207937d | 1860 | |
e3421a18 ZW |
1861 | /* Return which DP Port should be selected for Transcoder DP control */ |
1862 | int | |
1863 | intel_trans_dp_port_sel (struct drm_crtc *crtc) | |
1864 | { | |
1865 | struct drm_device *dev = crtc->dev; | |
1866 | struct drm_mode_config *mode_config = &dev->mode_config; | |
1867 | struct drm_encoder *encoder; | |
e3421a18 ZW |
1868 | |
1869 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a CW |
1870 | struct intel_dp *intel_dp; |
1871 | ||
d8201ab6 | 1872 | if (encoder->crtc != crtc) |
e3421a18 ZW |
1873 | continue; |
1874 | ||
ea5b213a CW |
1875 | intel_dp = enc_to_intel_dp(encoder); |
1876 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) | |
1877 | return intel_dp->output_reg; | |
e3421a18 | 1878 | } |
ea5b213a | 1879 | |
e3421a18 ZW |
1880 | return -1; |
1881 | } | |
1882 | ||
36e83a18 | 1883 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 1884 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
1885 | { |
1886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1887 | struct child_device_config *p_child; | |
1888 | int i; | |
1889 | ||
1890 | if (!dev_priv->child_dev_num) | |
1891 | return false; | |
1892 | ||
1893 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
1894 | p_child = dev_priv->child_dev + i; | |
1895 | ||
1896 | if (p_child->dvo_port == PORT_IDPD && | |
1897 | p_child->device_type == DEVICE_TYPE_eDP) | |
1898 | return true; | |
1899 | } | |
1900 | return false; | |
1901 | } | |
1902 | ||
f684960e CW |
1903 | static void |
1904 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
1905 | { | |
3f43c48d | 1906 | intel_attach_force_audio_property(connector); |
e953fd7b | 1907 | intel_attach_broadcast_rgb_property(connector); |
f684960e CW |
1908 | } |
1909 | ||
a4fc5ed6 KP |
1910 | void |
1911 | intel_dp_init(struct drm_device *dev, int output_reg) | |
1912 | { | |
1913 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1914 | struct drm_connector *connector; | |
ea5b213a | 1915 | struct intel_dp *intel_dp; |
21d40d37 | 1916 | struct intel_encoder *intel_encoder; |
55f78c43 | 1917 | struct intel_connector *intel_connector; |
5eb08b69 | 1918 | const char *name = NULL; |
b329530c | 1919 | int type; |
a4fc5ed6 | 1920 | |
ea5b213a CW |
1921 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
1922 | if (!intel_dp) | |
a4fc5ed6 KP |
1923 | return; |
1924 | ||
3d3dc149 | 1925 | intel_dp->output_reg = output_reg; |
3d3dc149 | 1926 | |
55f78c43 ZW |
1927 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
1928 | if (!intel_connector) { | |
ea5b213a | 1929 | kfree(intel_dp); |
55f78c43 ZW |
1930 | return; |
1931 | } | |
ea5b213a | 1932 | intel_encoder = &intel_dp->base; |
55f78c43 | 1933 | |
ea5b213a | 1934 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
b329530c | 1935 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 1936 | intel_dp->is_pch_edp = true; |
b329530c | 1937 | |
cfcb0fc9 | 1938 | if (output_reg == DP_A || is_pch_edp(intel_dp)) { |
b329530c AJ |
1939 | type = DRM_MODE_CONNECTOR_eDP; |
1940 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
1941 | } else { | |
1942 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
1943 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
1944 | } | |
1945 | ||
55f78c43 | 1946 | connector = &intel_connector->base; |
b329530c | 1947 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
1948 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
1949 | ||
eb1f8e4f DA |
1950 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
1951 | ||
652af9d7 | 1952 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
21d40d37 | 1953 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
652af9d7 | 1954 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
21d40d37 | 1955 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
652af9d7 | 1956 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
21d40d37 | 1957 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
f8aed700 | 1958 | |
cfcb0fc9 | 1959 | if (is_edp(intel_dp)) |
21d40d37 | 1960 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
6251ec0a | 1961 | |
21d40d37 | 1962 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
a4fc5ed6 KP |
1963 | connector->interlace_allowed = true; |
1964 | connector->doublescan_allowed = 0; | |
1965 | ||
4ef69c7a | 1966 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
a4fc5ed6 | 1967 | DRM_MODE_ENCODER_TMDS); |
4ef69c7a | 1968 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
a4fc5ed6 | 1969 | |
df0e9248 | 1970 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
1971 | drm_sysfs_connector_add(connector); |
1972 | ||
1973 | /* Set up the DDC bus. */ | |
5eb08b69 | 1974 | switch (output_reg) { |
32f9d658 ZW |
1975 | case DP_A: |
1976 | name = "DPDDC-A"; | |
1977 | break; | |
5eb08b69 ZW |
1978 | case DP_B: |
1979 | case PCH_DP_B: | |
b01f2c3a JB |
1980 | dev_priv->hotplug_supported_mask |= |
1981 | HDMIB_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1982 | name = "DPDDC-B"; |
1983 | break; | |
1984 | case DP_C: | |
1985 | case PCH_DP_C: | |
b01f2c3a JB |
1986 | dev_priv->hotplug_supported_mask |= |
1987 | HDMIC_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1988 | name = "DPDDC-C"; |
1989 | break; | |
1990 | case DP_D: | |
1991 | case PCH_DP_D: | |
b01f2c3a JB |
1992 | dev_priv->hotplug_supported_mask |= |
1993 | HDMID_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1994 | name = "DPDDC-D"; |
1995 | break; | |
1996 | } | |
1997 | ||
ea5b213a | 1998 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
32f9d658 | 1999 | |
89667383 JB |
2000 | /* Cache some DPCD data in the eDP case */ |
2001 | if (is_edp(intel_dp)) { | |
2002 | int ret; | |
5d613501 JB |
2003 | u32 pp_on, pp_div; |
2004 | ||
2005 | pp_on = I915_READ(PCH_PP_ON_DELAYS); | |
2006 | pp_div = I915_READ(PCH_PP_DIVISOR); | |
89667383 | 2007 | |
5d613501 JB |
2008 | /* Get T3 & T12 values (note: VESA not bspec terminology) */ |
2009 | dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16; | |
2010 | dev_priv->panel_t3 /= 10; /* t3 in 100us units */ | |
2011 | dev_priv->panel_t12 = pp_div & 0xf; | |
2012 | dev_priv->panel_t12 *= 100; /* t12 in 100ms units */ | |
2013 | ||
2014 | ironlake_edp_panel_vdd_on(intel_dp); | |
89667383 JB |
2015 | ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV, |
2016 | intel_dp->dpcd, | |
2017 | sizeof(intel_dp->dpcd)); | |
3d3dc149 | 2018 | ironlake_edp_panel_vdd_off(intel_dp); |
89667383 | 2019 | if (ret == sizeof(intel_dp->dpcd)) { |
7183dc29 JB |
2020 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
2021 | dev_priv->no_aux_handshake = | |
2022 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
89667383 JB |
2023 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
2024 | } else { | |
3d3dc149 | 2025 | /* if this fails, presume the device is a ghost */ |
48898b03 | 2026 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
3d3dc149 | 2027 | intel_dp_encoder_destroy(&intel_dp->base.base); |
48898b03 | 2028 | intel_dp_destroy(&intel_connector->base); |
3d3dc149 | 2029 | return; |
89667383 | 2030 | } |
89667383 JB |
2031 | } |
2032 | ||
21d40d37 | 2033 | intel_encoder->hot_plug = intel_dp_hot_plug; |
a4fc5ed6 | 2034 | |
4d926461 | 2035 | if (is_edp(intel_dp)) { |
32f9d658 ZW |
2036 | /* initialize panel mode from VBT if available for eDP */ |
2037 | if (dev_priv->lfp_lvds_vbt_mode) { | |
2038 | dev_priv->panel_fixed_mode = | |
2039 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); | |
2040 | if (dev_priv->panel_fixed_mode) { | |
2041 | dev_priv->panel_fixed_mode->type |= | |
2042 | DRM_MODE_TYPE_PREFERRED; | |
2043 | } | |
2044 | } | |
2045 | } | |
2046 | ||
f684960e CW |
2047 | intel_dp_add_properties(intel_dp, connector); |
2048 | ||
a4fc5ed6 KP |
2049 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
2050 | * 0xd. Failure to do so will result in spurious interrupts being | |
2051 | * generated on the port when a cable is not attached. | |
2052 | */ | |
2053 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
2054 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
2055 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2056 | } | |
2057 | } |