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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
a4fc5ed6
KP		 31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
34#include "drm_crtc_helper.h"
35#include "intel_drv.h"
36#include "i915_drm.h"
37#include "i915_drv.h"
ab2c0672 38#include "drm_dp_helper.h"
a4fc5ed6 39
a2006cf5 40#define DP_RECEIVER_CAP_SIZE 0xf
a4fc5ed6
KP		 41#define DP_LINK_STATUS_SIZE 6
42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
44#define DP_LINK_CONFIGURATION_SIZE 9
45
ea5b213a
CW		 46struct intel_dp {
47 struct intel_encoder base;
a4fc5ed6
KP		 48 uint32_t output_reg;
49 uint32_t DP;
50 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
a4fc5ed6 51 bool has_audio;
c3e5f67b 52 enum hdmi_force_audio force_audio;
e953fd7b 53 uint32_t color_range;
d2b996ac 54 int dpms_mode;
a4fc5ed6
KP		 55 uint8_t link_bw;
56 uint8_t lane_count;
a2006cf5 57 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
a4fc5ed6
KP		 58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo;
f0917379 60 bool is_pch_edp;
33a34e4e 61 uint8_t train_set[4];
f01eca2e
KP		 62 int panel_power_up_delay;
63 int panel_power_down_delay;
64 int panel_power_cycle_delay;
65 int backlight_on_delay;
66 int backlight_off_delay;
d15456de 67 struct drm_display_mode *panel_fixed_mode; /* for eDP */
bd943159
KP		 68 struct delayed_work panel_vdd_work;
69 bool want_panel_vdd;
a4fc5ed6
KP		 70};
71
cfcb0fc9
JB		 72/**
73 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
74 * @intel_dp: DP struct
75 *
76 * If a CPU or PCH DP output is attached to an eDP panel, this function
77 * will return true, and false otherwise.
78 */
79static bool is_edp(struct intel_dp *intel_dp)
80{
81 return intel_dp->base.type == INTEL_OUTPUT_EDP;
82}
83
84/**
85 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
86 * @intel_dp: DP struct
87 *
88 * Returns true if the given DP struct corresponds to a PCH DP port attached
89 * to an eDP panel, false otherwise. Helpful for determining whether we
90 * may need FDI resources for a given DP output or not.
91 */
92static bool is_pch_edp(struct intel_dp *intel_dp)
93{
94 return intel_dp->is_pch_edp;
95}
96
1c95822a
AJ		 97/**
98 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
99 * @intel_dp: DP struct
100 *
101 * Returns true if the given DP struct corresponds to a CPU eDP port.
102 */
103static bool is_cpu_edp(struct intel_dp *intel_dp)
104{
105 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
106}
107
ea5b213a
CW		 108static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
109{
4ef69c7a 110 return container_of(encoder, struct intel_dp, base.base);
ea5b213a 111}
a4fc5ed6 112
df0e9248
CW		 113static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
114{
115 return container_of(intel_attached_encoder(connector),
116 struct intel_dp, base);
117}
118
814948ad
JB		 119/**
120 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
121 * @encoder: DRM encoder
122 *
123 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
124 * by intel_display.c.
125 */
126bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
127{
128 struct intel_dp *intel_dp;
129
130 if (!encoder)
131 return false;
132
133 intel_dp = enc_to_intel_dp(encoder);
134
135 return is_pch_edp(intel_dp);
136}
137
33a34e4e
JB		 138static void intel_dp_start_link_train(struct intel_dp *intel_dp);
139static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
ea5b213a 140static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 141
32f9d658 142void
0206e353 143intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 144 int *lane_num, int *link_bw)
32f9d658 145{
ea5b213a 146 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 147
ea5b213a
CW		 148 *lane_num = intel_dp->lane_count;
149 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 150 *link_bw = 162000;
ea5b213a 151 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 152 *link_bw = 270000;
153}
154
a4fc5ed6 155static int
ea5b213a 156intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 157{
9a10f401
KP		 158 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
159 switch (max_lane_count) {
160 case 1: case 2: case 4:
161 break;
162 default:
163 max_lane_count = 4;
a4fc5ed6
KP		 164 }
165 return max_lane_count;
166}
167
168static int
ea5b213a 169intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 170{
7183dc29 171 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 172
173 switch (max_link_bw) {
174 case DP_LINK_BW_1_62:
175 case DP_LINK_BW_2_7:
176 break;
177 default:
178 max_link_bw = DP_LINK_BW_1_62;
179 break;
180 }
181 return max_link_bw;
182}
183
184static int
185intel_dp_link_clock(uint8_t link_bw)
186{
187 if (link_bw == DP_LINK_BW_2_7)
188 return 270000;
189 else
190 return 162000;
191}
192
cd9dde44
AJ		 193/*
194 * The units on the numbers in the next two are... bizarre. Examples will
195 * make it clearer; this one parallels an example in the eDP spec.
196 *
197 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
198 *
199 * 270000 * 1 * 8 / 10 == 216000
200 *
201 * The actual data capacity of that configuration is 2.16Gbit/s, so the
202 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
203 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
204 * 119000. At 18bpp that's 2142000 kilobits per second.
205 *
206 * Thus the strange-looking division by 10 in intel_dp_link_required, to
207 * get the result in decakilobits instead of kilobits.
208 */
209
a4fc5ed6 210static int
c898261c 211intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 212{
cd9dde44 213 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 214}
215
fe27d53e
DA		 216static int
217intel_dp_max_data_rate(int max_link_clock, int max_lanes)
218{
219 return (max_link_clock * max_lanes * 8) / 10;
220}
221
c4867936
DV		 222static bool
223intel_dp_adjust_dithering(struct intel_dp *intel_dp,
224 struct drm_display_mode *mode,
225 struct drm_display_mode *adjusted_mode)
226{
227 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
228 int max_lanes = intel_dp_max_lane_count(intel_dp);
229 int max_rate, mode_rate;
230
231 mode_rate = intel_dp_link_required(mode->clock, 24);
232 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
233
234 if (mode_rate > max_rate) {
235 mode_rate = intel_dp_link_required(mode->clock, 18);
236 if (mode_rate > max_rate)
237 return false;
238
239 if (adjusted_mode)
240 adjusted_mode->private_flags
241 |= INTEL_MODE_DP_FORCE_6BPC;
242
243 return true;
244 }
245
246 return true;
247}
248
a4fc5ed6
KP		 249static int
250intel_dp_mode_valid(struct drm_connector *connector,
251 struct drm_display_mode *mode)
252{
df0e9248 253 struct intel_dp *intel_dp = intel_attached_dp(connector);
a4fc5ed6 254
d15456de
KP		 255 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
256 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
7de56f43
ZY		 257 return MODE_PANEL;
258
d15456de 259 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
7de56f43
ZY		 260 return MODE_PANEL;
261 }
262
c4867936
DV		 263 if (!intel_dp_adjust_dithering(intel_dp, mode, NULL))
264 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 265
266 if (mode->clock < 10000)
267 return MODE_CLOCK_LOW;
268
269 return MODE_OK;
270}
271
272static uint32_t
273pack_aux(uint8_t *src, int src_bytes)
274{
275 int i;
276 uint32_t v = 0;
277
278 if (src_bytes > 4)
279 src_bytes = 4;
280 for (i = 0; i < src_bytes; i++)
281 v |= ((uint32_t) src[i]) << ((3-i) * 8);
282 return v;
283}
284
285static void
286unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
287{
288 int i;
289 if (dst_bytes > 4)
290 dst_bytes = 4;
291 for (i = 0; i < dst_bytes; i++)
292 dst[i] = src >> ((3-i) * 8);
293}
294
fb0f8fbf
KP		 295/* hrawclock is 1/4 the FSB frequency */
296static int
297intel_hrawclk(struct drm_device *dev)
298{
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 uint32_t clkcfg;
301
302 clkcfg = I915_READ(CLKCFG);
303 switch (clkcfg & CLKCFG_FSB_MASK) {
304 case CLKCFG_FSB_400:
305 return 100;
306 case CLKCFG_FSB_533:
307 return 133;
308 case CLKCFG_FSB_667:
309 return 166;
310 case CLKCFG_FSB_800:
311 return 200;
312 case CLKCFG_FSB_1067:
313 return 266;
314 case CLKCFG_FSB_1333:
315 return 333;
316 /* these two are just a guess; one of them might be right */
317 case CLKCFG_FSB_1600:
318 case CLKCFG_FSB_1600_ALT:
319 return 400;
320 default:
321 return 133;
322 }
323}
324
ebf33b18
KP		 325static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
326{
327 struct drm_device *dev = intel_dp->base.base.dev;
328 struct drm_i915_private *dev_priv = dev->dev_private;
329
330 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
331}
332
333static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
334{
335 struct drm_device *dev = intel_dp->base.base.dev;
336 struct drm_i915_private *dev_priv = dev->dev_private;
337
338 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
339}
340
9b984dae
KP		 341static void
342intel_dp_check_edp(struct intel_dp *intel_dp)
343{
344 struct drm_device *dev = intel_dp->base.base.dev;
345 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 346
9b984dae
KP		 347 if (!is_edp(intel_dp))
348 return;
ebf33b18 349 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 350 WARN(1, "eDP powered off while attempting aux channel communication.\n");
351 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 352 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 353 I915_READ(PCH_PP_CONTROL));
354 }
355}
356
a4fc5ed6 357static int
ea5b213a 358intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 359 uint8_t *send, int send_bytes,
360 uint8_t *recv, int recv_size)
361{
ea5b213a 362 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 363 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 364 struct drm_i915_private *dev_priv = dev->dev_private;
365 uint32_t ch_ctl = output_reg + 0x10;
366 uint32_t ch_data = ch_ctl + 4;
367 int i;
368 int recv_bytes;
a4fc5ed6 369 uint32_t status;
fb0f8fbf 370 uint32_t aux_clock_divider;
092945e1 371 int try, precharge = 5;
a4fc5ed6 372
9b984dae 373 intel_dp_check_edp(intel_dp);
a4fc5ed6 374 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 375 * and would like to run at 2MHz. So, take the
376 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 377 *
378 * Note that PCH attached eDP panels should use a 125MHz input
379 * clock divider.
a4fc5ed6 380 */
1c95822a 381 if (is_cpu_edp(intel_dp)) {
1a2eb460
KP		 382 if (IS_GEN6(dev) || IS_GEN7(dev))
383 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 384 else
385 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
386 } else if (HAS_PCH_SPLIT(dev))
6919132e 387 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 388 else
389 aux_clock_divider = intel_hrawclk(dev) / 2;
390
11bee43e
JB		 391 /* Try to wait for any previous AUX channel activity */
392 for (try = 0; try < 3; try++) {
393 status = I915_READ(ch_ctl);
394 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
395 break;
396 msleep(1);
397 }
398
399 if (try == 3) {
400 WARN(1, "dp_aux_ch not started status 0x%08x\n",
401 I915_READ(ch_ctl));
4f7f7b7e
CW		 402 return -EBUSY;
403 }
404
fb0f8fbf
KP		 405 /* Must try at least 3 times according to DP spec */
406 for (try = 0; try < 5; try++) {
407 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 408 for (i = 0; i < send_bytes; i += 4)
409 I915_WRITE(ch_data + i,
410 pack_aux(send + i, send_bytes - i));
0206e353 411
fb0f8fbf 412 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 413 I915_WRITE(ch_ctl,
414 DP_AUX_CH_CTL_SEND_BUSY |
415 DP_AUX_CH_CTL_TIME_OUT_400us |
416 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
417 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
418 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
419 DP_AUX_CH_CTL_DONE |
420 DP_AUX_CH_CTL_TIME_OUT_ERROR |
421 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 422 for (;;) {
fb0f8fbf
KP		 423 status = I915_READ(ch_ctl);
424 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
425 break;
4f7f7b7e 426 udelay(100);
fb0f8fbf 427 }
0206e353 428
fb0f8fbf 429 /* Clear done status and any errors */
4f7f7b7e
CW		 430 I915_WRITE(ch_ctl,
431 status |
432 DP_AUX_CH_CTL_DONE |
433 DP_AUX_CH_CTL_TIME_OUT_ERROR |
434 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 435
436 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
437 DP_AUX_CH_CTL_RECEIVE_ERROR))
438 continue;
4f7f7b7e 439 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 440 break;
441 }
442
a4fc5ed6 443 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 444 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 445 return -EBUSY;
a4fc5ed6
KP		 446 }
447
448 /* Check for timeout or receive error.
449 * Timeouts occur when the sink is not connected
450 */
a5b3da54 451 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 452 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 453 return -EIO;
454 }
1ae8c0a5
KP		 455
456 /* Timeouts occur when the device isn't connected, so they're
457 * "normal" -- don't fill the kernel log with these */
a5b3da54 458 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 459 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 460 return -ETIMEDOUT;
a4fc5ed6
KP		 461 }
462
463 /* Unload any bytes sent back from the other side */
464 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
465 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 466 if (recv_bytes > recv_size)
467 recv_bytes = recv_size;
0206e353 468
4f7f7b7e
CW		 469 for (i = 0; i < recv_bytes; i += 4)
470 unpack_aux(I915_READ(ch_data + i),
471 recv + i, recv_bytes - i);
a4fc5ed6
KP		 472
473 return recv_bytes;
474}
475
476/* Write data to the aux channel in native mode */
477static int
ea5b213a 478intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 479 uint16_t address, uint8_t *send, int send_bytes)
480{
481 int ret;
482 uint8_t msg[20];
483 int msg_bytes;
484 uint8_t ack;
485
9b984dae 486 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 487 if (send_bytes > 16)
488 return -1;
489 msg[0] = AUX_NATIVE_WRITE << 4;
490 msg[1] = address >> 8;
eebc863e 491 msg[2] = address & 0xff;
a4fc5ed6
KP		 492 msg[3] = send_bytes - 1;
493 memcpy(&msg[4], send, send_bytes);
494 msg_bytes = send_bytes + 4;
495 for (;;) {
ea5b213a 496 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 497 if (ret < 0)
498 return ret;
499 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
500 break;
501 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
502 udelay(100);
503 else
a5b3da54 504 return -EIO;
a4fc5ed6
KP		 505 }
506 return send_bytes;
507}
508
509/* Write a single byte to the aux channel in native mode */
510static int
ea5b213a 511intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 512 uint16_t address, uint8_t byte)
513{
ea5b213a 514 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 515}
516
517/* read bytes from a native aux channel */
518static int
ea5b213a 519intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 520 uint16_t address, uint8_t *recv, int recv_bytes)
521{
522 uint8_t msg[4];
523 int msg_bytes;
524 uint8_t reply[20];
525 int reply_bytes;
526 uint8_t ack;
527 int ret;
528
9b984dae 529 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 530 msg[0] = AUX_NATIVE_READ << 4;
531 msg[1] = address >> 8;
532 msg[2] = address & 0xff;
533 msg[3] = recv_bytes - 1;
534
535 msg_bytes = 4;
536 reply_bytes = recv_bytes + 1;
537
538 for (;;) {
ea5b213a 539 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 540 reply, reply_bytes);
a5b3da54
KP		 541 if (ret == 0)
542 return -EPROTO;
543 if (ret < 0)
a4fc5ed6
KP		 544 return ret;
545 ack = reply[0];
546 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
547 memcpy(recv, reply + 1, ret - 1);
548 return ret - 1;
549 }
550 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
551 udelay(100);
552 else
a5b3da54 553 return -EIO;
a4fc5ed6
KP		 554 }
555}
556
557static int
ab2c0672
DA		 558intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
559 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 560{
ab2c0672 561 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 562 struct intel_dp *intel_dp = container_of(adapter,
563 struct intel_dp,
564 adapter);
ab2c0672
DA		 565 uint16_t address = algo_data->address;
566 uint8_t msg[5];
567 uint8_t reply[2];
8316f337 568 unsigned retry;
ab2c0672
DA		 569 int msg_bytes;
570 int reply_bytes;
571 int ret;
572
9b984dae 573 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 574 /* Set up the command byte */
575 if (mode & MODE_I2C_READ)
576 msg[0] = AUX_I2C_READ << 4;
577 else
578 msg[0] = AUX_I2C_WRITE << 4;
579
580 if (!(mode & MODE_I2C_STOP))
581 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 582
ab2c0672
DA		 583 msg[1] = address >> 8;
584 msg[2] = address;
585
586 switch (mode) {
587 case MODE_I2C_WRITE:
588 msg[3] = 0;
589 msg[4] = write_byte;
590 msg_bytes = 5;
591 reply_bytes = 1;
592 break;
593 case MODE_I2C_READ:
594 msg[3] = 0;
595 msg_bytes = 4;
596 reply_bytes = 2;
597 break;
598 default:
599 msg_bytes = 3;
600 reply_bytes = 1;
601 break;
602 }
603
8316f337
DF		 604 for (retry = 0; retry < 5; retry++) {
605 ret = intel_dp_aux_ch(intel_dp,
606 msg, msg_bytes,
607 reply, reply_bytes);
ab2c0672 608 if (ret < 0) {
3ff99164 609 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 610 return ret;
611 }
8316f337
DF		 612
613 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
614 case AUX_NATIVE_REPLY_ACK:
615 /* I2C-over-AUX Reply field is only valid
616 * when paired with AUX ACK.
617 */
618 break;
619 case AUX_NATIVE_REPLY_NACK:
620 DRM_DEBUG_KMS("aux_ch native nack\n");
621 return -EREMOTEIO;
622 case AUX_NATIVE_REPLY_DEFER:
623 udelay(100);
624 continue;
625 default:
626 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
627 reply[0]);
628 return -EREMOTEIO;
629 }
630
ab2c0672
DA		 631 switch (reply[0] & AUX_I2C_REPLY_MASK) {
632 case AUX_I2C_REPLY_ACK:
633 if (mode == MODE_I2C_READ) {
634 *read_byte = reply[1];
635 }
636 return reply_bytes - 1;
637 case AUX_I2C_REPLY_NACK:
8316f337 638 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 639 return -EREMOTEIO;
640 case AUX_I2C_REPLY_DEFER:
8316f337 641 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 642 udelay(100);
643 break;
644 default:
8316f337 645 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 646 return -EREMOTEIO;
647 }
648 }
8316f337
DF		 649
650 DRM_ERROR("too many retries, giving up\n");
651 return -EREMOTEIO;
a4fc5ed6
KP		 652}
653
0b5c541b 654static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
bd943159 655static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0b5c541b 656
a4fc5ed6 657static int
ea5b213a 658intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 659 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 660{
0b5c541b
KP		 661 int ret;
662
d54e9d28 663 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 664 intel_dp->algo.running = false;
665 intel_dp->algo.address = 0;
666 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
667
0206e353 668 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 669 intel_dp->adapter.owner = THIS_MODULE;
670 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 671 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 672 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
673 intel_dp->adapter.algo_data = &intel_dp->algo;
674 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
675
0b5c541b
KP		 676 ironlake_edp_panel_vdd_on(intel_dp);
677 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 678 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 679 return ret;
a4fc5ed6
KP		 680}
681
682static bool
683intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
684 struct drm_display_mode *adjusted_mode)
685{
0d3a1bee 686 struct drm_device *dev = encoder->dev;
ea5b213a 687 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 688 int lane_count, clock;
ea5b213a
CW		 689 int max_lane_count = intel_dp_max_lane_count(intel_dp);
690 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 691 int bpp, mode_rate;
a4fc5ed6
KP		 692 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
693
d15456de
KP		 694 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
695 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
1d8e1c75
CW		 696 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
697 mode, adjusted_mode);
0d3a1bee
ZY		 698 /*
699 * the mode->clock is used to calculate the Data&Link M/N
700 * of the pipe. For the eDP the fixed clock should be used.
701 */
d15456de 702 mode->clock = intel_dp->panel_fixed_mode->clock;
0d3a1bee
ZY		 703 }
704
083f9560
DV		 705 DRM_DEBUG_KMS("DP link computation with max lane count %i "
706 "max bw %02x pixel clock %iKHz\n",
707 max_lane_count, bws[max_clock], mode->clock);
708
c4867936
DV		 709 if (!intel_dp_adjust_dithering(intel_dp, mode, adjusted_mode))
710 return false;
711
712 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
083f9560 713 mode_rate = intel_dp_link_required(mode->clock, bpp);
c4867936 714
a4fc5ed6
KP		 715 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
716 for (clock = 0; clock <= max_clock; clock++) {
fe27d53e 717 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 718
083f9560 719 if (mode_rate <= link_avail) {
ea5b213a
CW		 720 intel_dp->link_bw = bws[clock];
721 intel_dp->lane_count = lane_count;
722 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 723 DRM_DEBUG_KMS("DP link bw %02x lane "
724 "count %d clock %d bpp %d\n",
ea5b213a 725 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 726 adjusted_mode->clock, bpp);
727 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
728 mode_rate, link_avail);
a4fc5ed6
KP		 729 return true;
730 }
731 }
732 }
fe27d53e 733
a4fc5ed6
KP		 734 return false;
735}
736
737struct intel_dp_m_n {
738 uint32_t tu;
739 uint32_t gmch_m;
740 uint32_t gmch_n;
741 uint32_t link_m;
742 uint32_t link_n;
743};
744
745static void
746intel_reduce_ratio(uint32_t *num, uint32_t *den)
747{
748 while (*num > 0xffffff || *den > 0xffffff) {
749 *num >>= 1;
750 *den >>= 1;
751 }
752}
753
754static void
36e83a18 755intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 756 int nlanes,
757 int pixel_clock,
758 int link_clock,
759 struct intel_dp_m_n *m_n)
760{
761 m_n->tu = 64;
36e83a18 762 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 763 m_n->gmch_n = link_clock * nlanes;
764 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
765 m_n->link_m = pixel_clock;
766 m_n->link_n = link_clock;
767 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
768}
769
770void
771intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
772 struct drm_display_mode *adjusted_mode)
773{
774 struct drm_device *dev = crtc->dev;
775 struct drm_mode_config *mode_config = &dev->mode_config;
55f78c43 776 struct drm_encoder *encoder;
a4fc5ed6
KP		 777 struct drm_i915_private *dev_priv = dev->dev_private;
778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 779 int lane_count = 4;
a4fc5ed6 780 struct intel_dp_m_n m_n;
9db4a9c7 781 int pipe = intel_crtc->pipe;
a4fc5ed6
KP		 782
783 /*
21d40d37 784 * Find the lane count in the intel_encoder private
a4fc5ed6 785 */
55f78c43 786 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a 787 struct intel_dp *intel_dp;
a4fc5ed6 788
d8201ab6 789 if (encoder->crtc != crtc)
a4fc5ed6
KP		 790 continue;
791
ea5b213a 792 intel_dp = enc_to_intel_dp(encoder);
9a10f401
KP		 793 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
794 intel_dp->base.type == INTEL_OUTPUT_EDP)
795 {
ea5b213a 796 lane_count = intel_dp->lane_count;
51190667 797 break;
a4fc5ed6
KP		 798 }
799 }
800
801 /*
802 * Compute the GMCH and Link ratios. The '3' here is
803 * the number of bytes_per_pixel post-LUT, which we always
804 * set up for 8-bits of R/G/B, or 3 bytes total.
805 */
858fa035 806 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 807 mode->clock, adjusted_mode->clock, &m_n);
808
c619eed4 809 if (HAS_PCH_SPLIT(dev)) {
9db4a9c7
JB		 810 I915_WRITE(TRANSDATA_M1(pipe),
811 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
812 m_n.gmch_m);
813 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
814 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
815 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
a4fc5ed6 816 } else {
9db4a9c7
JB		 817 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
818 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
819 m_n.gmch_m);
820 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
821 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
822 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 823 }
824}
825
f01eca2e
KP		 826static void ironlake_edp_pll_on(struct drm_encoder *encoder);
827static void ironlake_edp_pll_off(struct drm_encoder *encoder);
828
a4fc5ed6
KP		 829static void
830intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
831 struct drm_display_mode *adjusted_mode)
832{
e3421a18 833 struct drm_device *dev = encoder->dev;
417e822d 834 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 835 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 836 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
838
f01eca2e
KP		 839 /* Turn on the eDP PLL if needed */
840 if (is_edp(intel_dp)) {
841 if (!is_pch_edp(intel_dp))
842 ironlake_edp_pll_on(encoder);
843 else
844 ironlake_edp_pll_off(encoder);
845 }
846
417e822d 847 /*
1a2eb460 848 * There are four kinds of DP registers:
417e822d
KP		 849 *
850 * IBX PCH
1a2eb460
KP		 851 * SNB CPU
852 * IVB CPU
417e822d
KP		 853 * CPT PCH
854 *
855 * IBX PCH and CPU are the same for almost everything,
856 * except that the CPU DP PLL is configured in this
857 * register
858 *
859 * CPT PCH is quite different, having many bits moved
860 * to the TRANS_DP_CTL register instead. That
861 * configuration happens (oddly) in ironlake_pch_enable
862 */
9c9e7927 863
417e822d
KP		 864 /* Preserve the BIOS-computed detected bit. This is
865 * supposed to be read-only.
866 */
867 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
868 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 869
417e822d
KP		 870 /* Handle DP bits in common between all three register formats */
871
872 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 873
ea5b213a 874 switch (intel_dp->lane_count) {
a4fc5ed6 875 case 1:
ea5b213a 876 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 877 break;
878 case 2:
ea5b213a 879 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 880 break;
881 case 4:
ea5b213a 882 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 883 break;
884 }
e0dac65e
WF		 885 if (intel_dp->has_audio) {
886 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
887 pipe_name(intel_crtc->pipe));
ea5b213a 888 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 889 intel_write_eld(encoder, adjusted_mode);
890 }
ea5b213a
CW		 891 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
892 intel_dp->link_configuration[0] = intel_dp->link_bw;
893 intel_dp->link_configuration[1] = intel_dp->lane_count;
a2cab1b2 894 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
a4fc5ed6 895 /*
9962c925 896 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 897 */
7183dc29
JB		 898 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
899 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
ea5b213a 900 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
a4fc5ed6
KP		 901 }
902
417e822d 903 /* Split out the IBX/CPU vs CPT settings */
32f9d658 904
1a2eb460
KP		 905 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
906 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
907 intel_dp->DP |= DP_SYNC_HS_HIGH;
908 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
909 intel_dp->DP |= DP_SYNC_VS_HIGH;
910 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
911
912 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
913 intel_dp->DP |= DP_ENHANCED_FRAMING;
914
915 intel_dp->DP |= intel_crtc->pipe << 29;
916
917 /* don't miss out required setting for eDP */
918 intel_dp->DP |= DP_PLL_ENABLE;
919 if (adjusted_mode->clock < 200000)
920 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
921 else
922 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
923 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 924 intel_dp->DP |= intel_dp->color_range;
925
926 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
927 intel_dp->DP |= DP_SYNC_HS_HIGH;
928 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
929 intel_dp->DP |= DP_SYNC_VS_HIGH;
930 intel_dp->DP |= DP_LINK_TRAIN_OFF;
931
932 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
933 intel_dp->DP |= DP_ENHANCED_FRAMING;
934
935 if (intel_crtc->pipe == 1)
936 intel_dp->DP |= DP_PIPEB_SELECT;
937
938 if (is_cpu_edp(intel_dp)) {
939 /* don't miss out required setting for eDP */
940 intel_dp->DP |= DP_PLL_ENABLE;
941 if (adjusted_mode->clock < 200000)
942 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
943 else
944 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
945 }
946 } else {
947 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 948 }
a4fc5ed6
KP		 949}
950
99ea7127
KP		 951#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
952#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
953
954#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
955#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
956
957#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
958#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
959
960static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
961 u32 mask,
962 u32 value)
bd943159 963{
99ea7127
KP		 964 struct drm_device *dev = intel_dp->base.base.dev;
965 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 966
99ea7127
KP		 967 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
968 mask, value,
969 I915_READ(PCH_PP_STATUS),
970 I915_READ(PCH_PP_CONTROL));
32ce697c 971
99ea7127
KP		 972 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
973 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
974 I915_READ(PCH_PP_STATUS),
975 I915_READ(PCH_PP_CONTROL));
32ce697c 976 }
99ea7127 977}
32ce697c 978
99ea7127
KP		 979static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
980{
981 DRM_DEBUG_KMS("Wait for panel power on\n");
982 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 983}
984
99ea7127
KP		 985static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
986{
987 DRM_DEBUG_KMS("Wait for panel power off time\n");
988 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
989}
990
991static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
992{
993 DRM_DEBUG_KMS("Wait for panel power cycle\n");
994 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
995}
996
997
832dd3c1
KP		 998/* Read the current pp_control value, unlocking the register if it
999 * is locked
1000 */
1001
1002static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1003{
1004 u32 control = I915_READ(PCH_PP_CONTROL);
1005
1006 control &= ~PANEL_UNLOCK_MASK;
1007 control |= PANEL_UNLOCK_REGS;
1008 return control;
bd943159
KP		 1009}
1010
5d613501
JB		 1011static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1012{
1013 struct drm_device *dev = intel_dp->base.base.dev;
1014 struct drm_i915_private *dev_priv = dev->dev_private;
1015 u32 pp;
1016
97af61f5
KP		 1017 if (!is_edp(intel_dp))
1018 return;
f01eca2e 1019 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1020
bd943159
KP		 1021 WARN(intel_dp->want_panel_vdd,
1022 "eDP VDD already requested on\n");
1023
1024 intel_dp->want_panel_vdd = true;
99ea7127 1025
bd943159
KP		 1026 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1027 DRM_DEBUG_KMS("eDP VDD already on\n");
1028 return;
1029 }
1030
99ea7127
KP		 1031 if (!ironlake_edp_have_panel_power(intel_dp))
1032 ironlake_wait_panel_power_cycle(intel_dp);
1033
832dd3c1 1034 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1035 pp |= EDP_FORCE_VDD;
1036 I915_WRITE(PCH_PP_CONTROL, pp);
1037 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1038 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1039 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1040
1041 /*
1042 * If the panel wasn't on, delay before accessing aux channel
1043 */
1044 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1045 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1046 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1047 }
5d613501
JB		 1048}
1049
bd943159 1050static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1051{
1052 struct drm_device *dev = intel_dp->base.base.dev;
1053 struct drm_i915_private *dev_priv = dev->dev_private;
1054 u32 pp;
1055
bd943159 1056 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1057 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1058 pp &= ~EDP_FORCE_VDD;
1059 I915_WRITE(PCH_PP_CONTROL, pp);
1060 POSTING_READ(PCH_PP_CONTROL);
1061
1062 /* Make sure sequencer is idle before allowing subsequent activity */
1063 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1064 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1065
1066 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1067 }
1068}
5d613501 1069
bd943159
KP		 1070static void ironlake_panel_vdd_work(struct work_struct *__work)
1071{
1072 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1073 struct intel_dp, panel_vdd_work);
1074 struct drm_device *dev = intel_dp->base.base.dev;
1075
627f7675 1076 mutex_lock(&dev->mode_config.mutex);
bd943159 1077 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1078 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1079}
1080
1081static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1082{
97af61f5
KP		 1083 if (!is_edp(intel_dp))
1084 return;
5d613501 1085
bd943159
KP		 1086 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1087 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1088
bd943159
KP		 1089 intel_dp->want_panel_vdd = false;
1090
1091 if (sync) {
1092 ironlake_panel_vdd_off_sync(intel_dp);
1093 } else {
1094 /*
1095 * Queue the timer to fire a long
1096 * time from now (relative to the power down delay)
1097 * to keep the panel power up across a sequence of operations
1098 */
1099 schedule_delayed_work(&intel_dp->panel_vdd_work,
1100 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1101 }
5d613501
JB		 1102}
1103
86a3073e 1104static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1105{
01cb9ea6 1106 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1107 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1108 u32 pp;
9934c132 1109
97af61f5 1110 if (!is_edp(intel_dp))
bd943159 1111 return;
99ea7127
KP		 1112
1113 DRM_DEBUG_KMS("Turn eDP power on\n");
1114
1115 if (ironlake_edp_have_panel_power(intel_dp)) {
1116 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1117 return;
99ea7127 1118 }
9934c132 1119
99ea7127 1120 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1121
99ea7127 1122 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1123 if (IS_GEN5(dev)) {
1124 /* ILK workaround: disable reset around power sequence */
1125 pp &= ~PANEL_POWER_RESET;
1126 I915_WRITE(PCH_PP_CONTROL, pp);
1127 POSTING_READ(PCH_PP_CONTROL);
1128 }
37c6c9b0 1129
1c0ae80a 1130 pp |= POWER_TARGET_ON;
99ea7127
KP		 1131 if (!IS_GEN5(dev))
1132 pp |= PANEL_POWER_RESET;
1133
9934c132 1134 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1135 POSTING_READ(PCH_PP_CONTROL);
9934c132 1136
99ea7127 1137 ironlake_wait_panel_on(intel_dp);
9934c132 1138
05ce1a49
KP		 1139 if (IS_GEN5(dev)) {
1140 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1141 I915_WRITE(PCH_PP_CONTROL, pp);
1142 POSTING_READ(PCH_PP_CONTROL);
1143 }
9934c132
JB		 1144}
1145
99ea7127 1146static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1147{
99ea7127 1148 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1149 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1150 u32 pp;
9934c132 1151
97af61f5
KP		 1152 if (!is_edp(intel_dp))
1153 return;
37c6c9b0 1154
99ea7127 1155 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1156
6cb49835 1157 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1158
99ea7127 1159 pp = ironlake_get_pp_control(dev_priv);
6cb49835 1160 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1161 I915_WRITE(PCH_PP_CONTROL, pp);
1162 POSTING_READ(PCH_PP_CONTROL);
9934c132 1163
99ea7127 1164 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1165}
1166
86a3073e 1167static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1168{
f01eca2e 1169 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1170 struct drm_i915_private *dev_priv = dev->dev_private;
1171 u32 pp;
1172
f01eca2e
KP		 1173 if (!is_edp(intel_dp))
1174 return;
1175
28c97730 1176 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1177 /*
1178 * If we enable the backlight right away following a panel power
1179 * on, we may see slight flicker as the panel syncs with the eDP
1180 * link. So delay a bit to make sure the image is solid before
1181 * allowing it to appear.
1182 */
f01eca2e 1183 msleep(intel_dp->backlight_on_delay);
832dd3c1 1184 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1185 pp |= EDP_BLC_ENABLE;
1186 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1187 POSTING_READ(PCH_PP_CONTROL);
32f9d658
ZW		 1188}
1189
86a3073e 1190static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1191{
f01eca2e 1192 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1193 struct drm_i915_private *dev_priv = dev->dev_private;
1194 u32 pp;
1195
f01eca2e
KP		 1196 if (!is_edp(intel_dp))
1197 return;
1198
28c97730 1199 DRM_DEBUG_KMS("\n");
832dd3c1 1200 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1201 pp &= ~EDP_BLC_ENABLE;
1202 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1203 POSTING_READ(PCH_PP_CONTROL);
1204 msleep(intel_dp->backlight_off_delay);
32f9d658 1205}
a4fc5ed6 1206
d240f20f
JB		 1207static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1208{
1209 struct drm_device *dev = encoder->dev;
1210 struct drm_i915_private *dev_priv = dev->dev_private;
1211 u32 dpa_ctl;
1212
1213 DRM_DEBUG_KMS("\n");
1214 dpa_ctl = I915_READ(DP_A);
298b0b39 1215 dpa_ctl |= DP_PLL_ENABLE;
d240f20f 1216 I915_WRITE(DP_A, dpa_ctl);
298b0b39
JB		 1217 POSTING_READ(DP_A);
1218 udelay(200);
d240f20f
JB		 1219}
1220
1221static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1222{
1223 struct drm_device *dev = encoder->dev;
1224 struct drm_i915_private *dev_priv = dev->dev_private;
1225 u32 dpa_ctl;
1226
1227 dpa_ctl = I915_READ(DP_A);
298b0b39 1228 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1229 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1230 POSTING_READ(DP_A);
d240f20f
JB		 1231 udelay(200);
1232}
1233
c7ad3810
JB		 1234/* If the sink supports it, try to set the power state appropriately */
1235static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1236{
1237 int ret, i;
1238
1239 /* Should have a valid DPCD by this point */
1240 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1241 return;
1242
1243 if (mode != DRM_MODE_DPMS_ON) {
1244 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1245 DP_SET_POWER_D3);
1246 if (ret != 1)
1247 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1248 } else {
1249 /*
1250 * When turning on, we need to retry for 1ms to give the sink
1251 * time to wake up.
1252 */
1253 for (i = 0; i < 3; i++) {
1254 ret = intel_dp_aux_native_write_1(intel_dp,
1255 DP_SET_POWER,
1256 DP_SET_POWER_D0);
1257 if (ret == 1)
1258 break;
1259 msleep(1);
1260 }
1261 }
1262}
1263
d240f20f
JB		 1264static void intel_dp_prepare(struct drm_encoder *encoder)
1265{
1266 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
d240f20f 1267
6cb49835
DV		 1268
1269 /* Make sure the panel is off before trying to change the mode. But also
1270 * ensure that we have vdd while we switch off the panel. */
1271 ironlake_edp_panel_vdd_on(intel_dp);
21264c63
KP		 1272 ironlake_edp_backlight_off(intel_dp);
1273 ironlake_edp_panel_off(intel_dp);
1274
c7ad3810 1275 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
21264c63 1276 intel_dp_link_down(intel_dp);
bd943159 1277 ironlake_edp_panel_vdd_off(intel_dp, false);
d240f20f
JB		 1278}
1279
1280static void intel_dp_commit(struct drm_encoder *encoder)
1281{
1282 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
d4270e57
JB		 1283 struct drm_device *dev = encoder->dev;
1284 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
5d613501 1285
97af61f5 1286 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1287 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1288 intel_dp_start_link_train(intel_dp);
97af61f5 1289 ironlake_edp_panel_on(intel_dp);
bd943159 1290 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1291 intel_dp_complete_link_train(intel_dp);
f01eca2e 1292 ironlake_edp_backlight_on(intel_dp);
d2b996ac
KP		 1293
1294 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
d4270e57
JB		 1295
1296 if (HAS_PCH_CPT(dev))
1297 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
d240f20f
JB		 1298}
1299
a4fc5ed6
KP		 1300static void
1301intel_dp_dpms(struct drm_encoder *encoder, int mode)
1302{
ea5b213a 1303 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
55f78c43 1304 struct drm_device *dev = encoder->dev;
a4fc5ed6 1305 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1306 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
a4fc5ed6
KP		 1307
1308 if (mode != DRM_MODE_DPMS_ON) {
6cb49835
DV		 1309 /* Switching the panel off requires vdd. */
1310 ironlake_edp_panel_vdd_on(intel_dp);
21264c63
KP		 1311 ironlake_edp_backlight_off(intel_dp);
1312 ironlake_edp_panel_off(intel_dp);
1313
c7ad3810 1314 intel_dp_sink_dpms(intel_dp, mode);
736085bc 1315 intel_dp_link_down(intel_dp);
bd943159 1316 ironlake_edp_panel_vdd_off(intel_dp, false);
21264c63
KP		 1317
1318 if (is_cpu_edp(intel_dp))
1319 ironlake_edp_pll_off(encoder);
a4fc5ed6 1320 } else {
21264c63
KP		 1321 if (is_cpu_edp(intel_dp))
1322 ironlake_edp_pll_on(encoder);
1323
97af61f5 1324 ironlake_edp_panel_vdd_on(intel_dp);
c7ad3810 1325 intel_dp_sink_dpms(intel_dp, mode);
32f9d658 1326 if (!(dp_reg & DP_PORT_EN)) {
01cb9ea6 1327 intel_dp_start_link_train(intel_dp);
97af61f5 1328 ironlake_edp_panel_on(intel_dp);
bd943159 1329 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1330 intel_dp_complete_link_train(intel_dp);
bee7eb2d 1331 } else
bd943159
KP		 1332 ironlake_edp_panel_vdd_off(intel_dp, false);
1333 ironlake_edp_backlight_on(intel_dp);
a4fc5ed6 1334 }
d2b996ac 1335 intel_dp->dpms_mode = mode;
a4fc5ed6
KP		 1336}
1337
1338/*
df0c237d
JB		 1339 * Native read with retry for link status and receiver capability reads for
1340 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1341 */
1342static bool
df0c237d
JB		 1343intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1344 uint8_t *recv, int recv_bytes)
a4fc5ed6 1345{
61da5fab
JB		 1346 int ret, i;
1347
df0c237d
JB		 1348 /*
1349 * Sinks are *supposed* to come up within 1ms from an off state,
1350 * but we're also supposed to retry 3 times per the spec.
1351 */
61da5fab 1352 for (i = 0; i < 3; i++) {
df0c237d
JB		 1353 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1354 recv_bytes);
1355 if (ret == recv_bytes)
61da5fab
JB		 1356 return true;
1357 msleep(1);
1358 }
a4fc5ed6 1359
61da5fab 1360 return false;
a4fc5ed6
KP		 1361}
1362
1363/*
1364 * Fetch AUX CH registers 0x202 - 0x207 which contain
1365 * link status information
1366 */
1367static bool
93f62dad 1368intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1369{
df0c237d
JB		 1370 return intel_dp_aux_native_read_retry(intel_dp,
1371 DP_LANE0_1_STATUS,
93f62dad 1372 link_status,
df0c237d 1373 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1374}
1375
1376static uint8_t
1377intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1378 int r)
1379{
1380 return link_status[r - DP_LANE0_1_STATUS];
1381}
1382
a4fc5ed6 1383static uint8_t
93f62dad 1384intel_get_adjust_request_voltage(uint8_t adjust_request[2],
a4fc5ed6
KP		 1385 int lane)
1386{
a4fc5ed6
KP		 1387 int s = ((lane & 1) ?
1388 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1389 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
93f62dad 1390 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1391
1392 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1393}
1394
1395static uint8_t
93f62dad 1396intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
a4fc5ed6
KP		 1397 int lane)
1398{
a4fc5ed6
KP		 1399 int s = ((lane & 1) ?
1400 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1401 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
93f62dad 1402 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1403
1404 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1405}
1406
1407
1408#if 0
1409static char *voltage_names[] = {
1410 "0.4V", "0.6V", "0.8V", "1.2V"
1411};
1412static char *pre_emph_names[] = {
1413 "0dB", "3.5dB", "6dB", "9.5dB"
1414};
1415static char *link_train_names[] = {
1416 "pattern 1", "pattern 2", "idle", "off"
1417};
1418#endif
1419
1420/*
1421 * These are source-specific values; current Intel hardware supports
1422 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1423 */
a4fc5ed6
KP		 1424
1425static uint8_t
1a2eb460 1426intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1427{
1a2eb460
KP		 1428 struct drm_device *dev = intel_dp->base.base.dev;
1429
1430 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1431 return DP_TRAIN_VOLTAGE_SWING_800;
1432 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1433 return DP_TRAIN_VOLTAGE_SWING_1200;
1434 else
1435 return DP_TRAIN_VOLTAGE_SWING_800;
1436}
1437
1438static uint8_t
1439intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1440{
1441 struct drm_device *dev = intel_dp->base.base.dev;
1442
1443 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1444 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1445 case DP_TRAIN_VOLTAGE_SWING_400:
1446 return DP_TRAIN_PRE_EMPHASIS_6;
1447 case DP_TRAIN_VOLTAGE_SWING_600:
1448 case DP_TRAIN_VOLTAGE_SWING_800:
1449 return DP_TRAIN_PRE_EMPHASIS_3_5;
1450 default:
1451 return DP_TRAIN_PRE_EMPHASIS_0;
1452 }
1453 } else {
1454 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1455 case DP_TRAIN_VOLTAGE_SWING_400:
1456 return DP_TRAIN_PRE_EMPHASIS_6;
1457 case DP_TRAIN_VOLTAGE_SWING_600:
1458 return DP_TRAIN_PRE_EMPHASIS_6;
1459 case DP_TRAIN_VOLTAGE_SWING_800:
1460 return DP_TRAIN_PRE_EMPHASIS_3_5;
1461 case DP_TRAIN_VOLTAGE_SWING_1200:
1462 default:
1463 return DP_TRAIN_PRE_EMPHASIS_0;
1464 }
a4fc5ed6
KP		 1465 }
1466}
1467
1468static void
93f62dad 1469intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1470{
1471 uint8_t v = 0;
1472 uint8_t p = 0;
1473 int lane;
93f62dad 1474 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1a2eb460
KP		 1475 uint8_t voltage_max;
1476 uint8_t preemph_max;
a4fc5ed6 1477
33a34e4e 1478 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad
KP		 1479 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1480 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
a4fc5ed6
KP		 1481
1482 if (this_v > v)
1483 v = this_v;
1484 if (this_p > p)
1485 p = this_p;
1486 }
1487
1a2eb460 1488 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1489 if (v >= voltage_max)
1490 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1491
1a2eb460
KP		 1492 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1493 if (p >= preemph_max)
1494 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1495
1496 for (lane = 0; lane < 4; lane++)
33a34e4e 1497 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1498}
1499
1500static uint32_t
93f62dad 1501intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1502{
3cf2efb1 1503 uint32_t signal_levels = 0;
a4fc5ed6 1504
3cf2efb1 1505 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1506 case DP_TRAIN_VOLTAGE_SWING_400:
1507 default:
1508 signal_levels |= DP_VOLTAGE_0_4;
1509 break;
1510 case DP_TRAIN_VOLTAGE_SWING_600:
1511 signal_levels |= DP_VOLTAGE_0_6;
1512 break;
1513 case DP_TRAIN_VOLTAGE_SWING_800:
1514 signal_levels |= DP_VOLTAGE_0_8;
1515 break;
1516 case DP_TRAIN_VOLTAGE_SWING_1200:
1517 signal_levels |= DP_VOLTAGE_1_2;
1518 break;
1519 }
3cf2efb1 1520 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1521 case DP_TRAIN_PRE_EMPHASIS_0:
1522 default:
1523 signal_levels |= DP_PRE_EMPHASIS_0;
1524 break;
1525 case DP_TRAIN_PRE_EMPHASIS_3_5:
1526 signal_levels |= DP_PRE_EMPHASIS_3_5;
1527 break;
1528 case DP_TRAIN_PRE_EMPHASIS_6:
1529 signal_levels |= DP_PRE_EMPHASIS_6;
1530 break;
1531 case DP_TRAIN_PRE_EMPHASIS_9_5:
1532 signal_levels |= DP_PRE_EMPHASIS_9_5;
1533 break;
1534 }
1535 return signal_levels;
1536}
1537
e3421a18
ZW		 1538/* Gen6's DP voltage swing and pre-emphasis control */
1539static uint32_t
1540intel_gen6_edp_signal_levels(uint8_t train_set)
1541{
3c5a62b5
YL		 1542 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1543 DP_TRAIN_PRE_EMPHASIS_MASK);
1544 switch (signal_levels) {
e3421a18 1545 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1546 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1547 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1548 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1549 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1550 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1551 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1552 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1553 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1554 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1555 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1556 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1557 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1558 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1559 default:
3c5a62b5
YL		 1560 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1561 "0x%x\n", signal_levels);
1562 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1563 }
1564}
1565
1a2eb460
KP		 1566/* Gen7's DP voltage swing and pre-emphasis control */
1567static uint32_t
1568intel_gen7_edp_signal_levels(uint8_t train_set)
1569{
1570 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1571 DP_TRAIN_PRE_EMPHASIS_MASK);
1572 switch (signal_levels) {
1573 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1574 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1575 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1576 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1577 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1578 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1579
1580 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1581 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1582 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1583 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1584
1585 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1586 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1587 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1588 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1589
1590 default:
1591 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1592 "0x%x\n", signal_levels);
1593 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1594 }
1595}
1596
a4fc5ed6
KP		 1597static uint8_t
1598intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1599 int lane)
1600{
a4fc5ed6 1601 int s = (lane & 1) * 4;
93f62dad 1602 uint8_t l = link_status[lane>>1];
a4fc5ed6
KP		 1603
1604 return (l >> s) & 0xf;
1605}
1606
1607/* Check for clock recovery is done on all channels */
1608static bool
1609intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1610{
1611 int lane;
1612 uint8_t lane_status;
1613
1614 for (lane = 0; lane < lane_count; lane++) {
1615 lane_status = intel_get_lane_status(link_status, lane);
1616 if ((lane_status & DP_LANE_CR_DONE) == 0)
1617 return false;
1618 }
1619 return true;
1620}
1621
1622/* Check to see if channel eq is done on all channels */
1623#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1624 DP_LANE_CHANNEL_EQ_DONE|\
1625 DP_LANE_SYMBOL_LOCKED)
1626static bool
93f62dad 1627intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1628{
1629 uint8_t lane_align;
1630 uint8_t lane_status;
1631 int lane;
1632
93f62dad 1633 lane_align = intel_dp_link_status(link_status,
a4fc5ed6
KP		 1634 DP_LANE_ALIGN_STATUS_UPDATED);
1635 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1636 return false;
33a34e4e 1637 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad 1638 lane_status = intel_get_lane_status(link_status, lane);
a4fc5ed6
KP		 1639 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1640 return false;
1641 }
1642 return true;
1643}
1644
1645static bool
ea5b213a 1646intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1647 uint32_t dp_reg_value,
58e10eb9 1648 uint8_t dp_train_pat)
a4fc5ed6 1649{
4ef69c7a 1650 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1651 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1652 int ret;
1653
ea5b213a
CW		 1654 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1655 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1656
ea5b213a 1657 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1658 DP_TRAINING_PATTERN_SET,
1659 dp_train_pat);
1660
ea5b213a 1661 ret = intel_dp_aux_native_write(intel_dp,
58e10eb9 1662 DP_TRAINING_LANE0_SET,
b34f1f09
KP		 1663 intel_dp->train_set,
1664 intel_dp->lane_count);
1665 if (ret != intel_dp->lane_count)
a4fc5ed6
KP		 1666 return false;
1667
1668 return true;
1669}
1670
33a34e4e 1671/* Enable corresponding port and start training pattern 1 */
a4fc5ed6 1672static void
33a34e4e 1673intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1674{
4ef69c7a 1675 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1676 struct drm_i915_private *dev_priv = dev->dev_private;
58e10eb9 1677 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
a4fc5ed6
KP		 1678 int i;
1679 uint8_t voltage;
1680 bool clock_recovery = false;
cdb0e95b 1681 int voltage_tries, loop_tries;
e3421a18 1682 u32 reg;
ea5b213a 1683 uint32_t DP = intel_dp->DP;
a4fc5ed6 1684
e8519464
AJ		 1685 /*
1686 * On CPT we have to enable the port in training pattern 1, which
1687 * will happen below in intel_dp_set_link_train. Otherwise, enable
1688 * the port and wait for it to become active.
1689 */
1690 if (!HAS_PCH_CPT(dev)) {
1691 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1692 POSTING_READ(intel_dp->output_reg);
1693 intel_wait_for_vblank(dev, intel_crtc->pipe);
1694 }
a4fc5ed6 1695
3cf2efb1
CW		 1696 /* Write the link configuration data */
1697 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1698 intel_dp->link_configuration,
1699 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1700
1701 DP |= DP_PORT_EN;
1a2eb460
KP		 1702
1703 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1704 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1705 else
1706 DP &= ~DP_LINK_TRAIN_MASK;
33a34e4e 1707 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1708 voltage = 0xff;
cdb0e95b
KP		 1709 voltage_tries = 0;
1710 loop_tries = 0;
a4fc5ed6
KP		 1711 clock_recovery = false;
1712 for (;;) {
33a34e4e 1713 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1714 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1715 uint32_t signal_levels;
417e822d 1716
1a2eb460
KP		 1717
1718 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1719 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1720 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1721 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1722 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1723 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1724 } else {
93f62dad
KP		 1725 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1726 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
e3421a18
ZW		 1727 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1728 }
a4fc5ed6 1729
1a2eb460 1730 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1731 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1732 else
1733 reg = DP | DP_LINK_TRAIN_PAT_1;
1734
ea5b213a 1735 if (!intel_dp_set_link_train(intel_dp, reg,
81055854
AJ		 1736 DP_TRAINING_PATTERN_1 |
1737 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1738 break;
a4fc5ed6
KP		 1739 /* Set training pattern 1 */
1740
3cf2efb1 1741 udelay(100);
93f62dad
KP		 1742 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1743 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1744 break;
93f62dad 1745 }
a4fc5ed6 1746
93f62dad
KP		 1747 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1748 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1749 clock_recovery = true;
1750 break;
1751 }
1752
1753 /* Check to see if we've tried the max voltage */
1754 for (i = 0; i < intel_dp->lane_count; i++)
1755 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1756 break;
cdb0e95b
KP		 1757 if (i == intel_dp->lane_count) {
1758 ++loop_tries;
1759 if (loop_tries == 5) {
1760 DRM_DEBUG_KMS("too many full retries, give up\n");
1761 break;
1762 }
1763 memset(intel_dp->train_set, 0, 4);
1764 voltage_tries = 0;
1765 continue;
1766 }
a4fc5ed6 1767
3cf2efb1
CW		 1768 /* Check to see if we've tried the same voltage 5 times */
1769 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
cdb0e95b
KP		 1770 ++voltage_tries;
1771 if (voltage_tries == 5) {
1772 DRM_DEBUG_KMS("too many voltage retries, give up\n");
a4fc5ed6 1773 break;
cdb0e95b 1774 }
3cf2efb1 1775 } else
cdb0e95b 1776 voltage_tries = 0;
3cf2efb1 1777 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1778
3cf2efb1 1779 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1780 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1781 }
1782
33a34e4e
JB		 1783 intel_dp->DP = DP;
1784}
1785
1786static void
1787intel_dp_complete_link_train(struct intel_dp *intel_dp)
1788{
4ef69c7a 1789 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e
JB		 1790 struct drm_i915_private *dev_priv = dev->dev_private;
1791 bool channel_eq = false;
37f80975 1792 int tries, cr_tries;
33a34e4e
JB		 1793 u32 reg;
1794 uint32_t DP = intel_dp->DP;
1795
a4fc5ed6
KP		 1796 /* channel equalization */
1797 tries = 0;
37f80975 1798 cr_tries = 0;
a4fc5ed6
KP		 1799 channel_eq = false;
1800 for (;;) {
33a34e4e 1801 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1802 uint32_t signal_levels;
93f62dad 1803 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1804
37f80975
JB		 1805 if (cr_tries > 5) {
1806 DRM_ERROR("failed to train DP, aborting\n");
1807 intel_dp_link_down(intel_dp);
1808 break;
1809 }
1810
1a2eb460
KP		 1811 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1812 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1813 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1814 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1815 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1816 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1817 } else {
93f62dad 1818 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1819 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1820 }
1821
1a2eb460 1822 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1823 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1824 else
1825 reg = DP | DP_LINK_TRAIN_PAT_2;
a4fc5ed6
KP		 1826
1827 /* channel eq pattern */
ea5b213a 1828 if (!intel_dp_set_link_train(intel_dp, reg,
81055854
AJ		 1829 DP_TRAINING_PATTERN_2 |
1830 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1831 break;
1832
3cf2efb1 1833 udelay(400);
93f62dad 1834 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1835 break;
a4fc5ed6 1836
37f80975 1837 /* Make sure clock is still ok */
93f62dad 1838 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1839 intel_dp_start_link_train(intel_dp);
1840 cr_tries++;
1841 continue;
1842 }
1843
93f62dad 1844 if (intel_channel_eq_ok(intel_dp, link_status)) {
3cf2efb1
CW		 1845 channel_eq = true;
1846 break;
1847 }
a4fc5ed6 1848
37f80975
JB		 1849 /* Try 5 times, then try clock recovery if that fails */
1850 if (tries > 5) {
1851 intel_dp_link_down(intel_dp);
1852 intel_dp_start_link_train(intel_dp);
1853 tries = 0;
1854 cr_tries++;
1855 continue;
1856 }
a4fc5ed6 1857
3cf2efb1 1858 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1859 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1860 ++tries;
869184a6 1861 }
3cf2efb1 1862
1a2eb460 1863 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1864 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1865 else
1866 reg = DP | DP_LINK_TRAIN_OFF;
1867
ea5b213a
CW		 1868 I915_WRITE(intel_dp->output_reg, reg);
1869 POSTING_READ(intel_dp->output_reg);
1870 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1871 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1872}
1873
1874static void
ea5b213a 1875intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1876{
4ef69c7a 1877 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1878 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1879 uint32_t DP = intel_dp->DP;
a4fc5ed6 1880
1b39d6f3
CW		 1881 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1882 return;
1883
28c97730 1884 DRM_DEBUG_KMS("\n");
32f9d658 1885
cfcb0fc9 1886 if (is_edp(intel_dp)) {
32f9d658 1887 DP &= ~DP_PLL_ENABLE;
ea5b213a
CW		 1888 I915_WRITE(intel_dp->output_reg, DP);
1889 POSTING_READ(intel_dp->output_reg);
32f9d658
ZW		 1890 udelay(100);
1891 }
1892
1a2eb460 1893 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1894 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1895 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1896 } else {
1897 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1898 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1899 }
fe255d00 1900 POSTING_READ(intel_dp->output_reg);
5eb08b69 1901
fe255d00 1902 msleep(17);
5eb08b69 1903
417e822d 1904 if (is_edp(intel_dp)) {
1a2eb460 1905 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
417e822d
KP		 1906 DP |= DP_LINK_TRAIN_OFF_CPT;
1907 else
1908 DP |= DP_LINK_TRAIN_OFF;
1909 }
5bddd17f 1910
1b39d6f3
CW		 1911 if (!HAS_PCH_CPT(dev) &&
1912 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 1913 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1914
5bddd17f
EA		 1915 /* Hardware workaround: leaving our transcoder select
1916 * set to transcoder B while it's off will prevent the
1917 * corresponding HDMI output on transcoder A.
1918 *
1919 * Combine this with another hardware workaround:
1920 * transcoder select bit can only be cleared while the
1921 * port is enabled.
1922 */
1923 DP &= ~DP_PIPEB_SELECT;
1924 I915_WRITE(intel_dp->output_reg, DP);
1925
1926 /* Changes to enable or select take place the vblank
1927 * after being written.
1928 */
31acbcc4
CW		 1929 if (crtc == NULL) {
1930 /* We can arrive here never having been attached
1931 * to a CRTC, for instance, due to inheriting
1932 * random state from the BIOS.
1933 *
1934 * If the pipe is not running, play safe and
1935 * wait for the clocks to stabilise before
1936 * continuing.
1937 */
1938 POSTING_READ(intel_dp->output_reg);
1939 msleep(50);
1940 } else
1941 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 1942 }
1943
832afda6 1944 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 1945 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1946 POSTING_READ(intel_dp->output_reg);
f01eca2e 1947 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 1948}
1949
26d61aad
KP		 1950static bool
1951intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 1952{
92fd8fd1 1953 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
0206e353 1954 sizeof(intel_dp->dpcd)) &&
92fd8fd1 1955 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
26d61aad 1956 return true;
92fd8fd1
KP		 1957 }
1958
26d61aad 1959 return false;
92fd8fd1
KP		 1960}
1961
a60f0e38
JB		 1962static bool
1963intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1964{
1965 int ret;
1966
1967 ret = intel_dp_aux_native_read_retry(intel_dp,
1968 DP_DEVICE_SERVICE_IRQ_VECTOR,
1969 sink_irq_vector, 1);
1970 if (!ret)
1971 return false;
1972
1973 return true;
1974}
1975
1976static void
1977intel_dp_handle_test_request(struct intel_dp *intel_dp)
1978{
1979 /* NAK by default */
1980 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1981}
1982
a4fc5ed6
KP		 1983/*
1984 * According to DP spec
1985 * 5.1.2:
1986 * 1. Read DPCD
1987 * 2. Configure link according to Receiver Capabilities
1988 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1989 * 4. Check link status on receipt of hot-plug interrupt
1990 */
1991
1992static void
ea5b213a 1993intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 1994{
a60f0e38 1995 u8 sink_irq_vector;
93f62dad 1996 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 1997
d2b996ac
KP		 1998 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1999 return;
59cd09e1 2000
4ef69c7a 2001 if (!intel_dp->base.base.crtc)
a4fc5ed6
KP		 2002 return;
2003
92fd8fd1 2004 /* Try to read receiver status if the link appears to be up */
93f62dad 2005 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2006 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2007 return;
2008 }
2009
92fd8fd1 2010 /* Now read the DPCD to see if it's actually running */
26d61aad 2011 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2012 intel_dp_link_down(intel_dp);
2013 return;
2014 }
2015
a60f0e38
JB		 2016 /* Try to read the source of the interrupt */
2017 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2018 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2019 /* Clear interrupt source */
2020 intel_dp_aux_native_write_1(intel_dp,
2021 DP_DEVICE_SERVICE_IRQ_VECTOR,
2022 sink_irq_vector);
2023
2024 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2025 intel_dp_handle_test_request(intel_dp);
2026 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2027 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2028 }
2029
93f62dad 2030 if (!intel_channel_eq_ok(intel_dp, link_status)) {
92fd8fd1
KP		 2031 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2032 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2033 intel_dp_start_link_train(intel_dp);
2034 intel_dp_complete_link_train(intel_dp);
2035 }
a4fc5ed6 2036}
a4fc5ed6 2037
71ba9000 2038static enum drm_connector_status
26d61aad 2039intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2040{
26d61aad
KP		 2041 if (intel_dp_get_dpcd(intel_dp))
2042 return connector_status_connected;
2043 return connector_status_disconnected;
71ba9000
AJ		 2044}
2045
5eb08b69 2046static enum drm_connector_status
a9756bb5 2047ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2048{
5eb08b69
ZW		 2049 enum drm_connector_status status;
2050
fe16d949
CW		 2051 /* Can't disconnect eDP, but you can close the lid... */
2052 if (is_edp(intel_dp)) {
2053 status = intel_panel_detect(intel_dp->base.base.dev);
2054 if (status == connector_status_unknown)
2055 status = connector_status_connected;
2056 return status;
2057 }
01cb9ea6 2058
26d61aad 2059 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2060}
2061
a4fc5ed6 2062static enum drm_connector_status
a9756bb5 2063g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2064{
4ef69c7a 2065 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2066 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 2067 uint32_t temp, bit;
5eb08b69 2068
ea5b213a 2069 switch (intel_dp->output_reg) {
a4fc5ed6
KP		 2070 case DP_B:
2071 bit = DPB_HOTPLUG_INT_STATUS;
2072 break;
2073 case DP_C:
2074 bit = DPC_HOTPLUG_INT_STATUS;
2075 break;
2076 case DP_D:
2077 bit = DPD_HOTPLUG_INT_STATUS;
2078 break;
2079 default:
2080 return connector_status_unknown;
2081 }
2082
2083 temp = I915_READ(PORT_HOTPLUG_STAT);
2084
2085 if ((temp & bit) == 0)
2086 return connector_status_disconnected;
2087
26d61aad 2088 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2089}
2090
8c241fef
KP		 2091static struct edid *
2092intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2093{
2094 struct intel_dp *intel_dp = intel_attached_dp(connector);
2095 struct edid *edid;
2096
2097 ironlake_edp_panel_vdd_on(intel_dp);
2098 edid = drm_get_edid(connector, adapter);
bd943159 2099 ironlake_edp_panel_vdd_off(intel_dp, false);
8c241fef
KP		 2100 return edid;
2101}
2102
2103static int
2104intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2105{
2106 struct intel_dp *intel_dp = intel_attached_dp(connector);
2107 int ret;
2108
2109 ironlake_edp_panel_vdd_on(intel_dp);
2110 ret = intel_ddc_get_modes(connector, adapter);
bd943159 2111 ironlake_edp_panel_vdd_off(intel_dp, false);
8c241fef
KP		 2112 return ret;
2113}
2114
2115
a9756bb5
ZW		 2116/**
2117 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2118 *
2119 * \return true if DP port is connected.
2120 * \return false if DP port is disconnected.
2121 */
2122static enum drm_connector_status
2123intel_dp_detect(struct drm_connector *connector, bool force)
2124{
2125 struct intel_dp *intel_dp = intel_attached_dp(connector);
2126 struct drm_device *dev = intel_dp->base.base.dev;
2127 enum drm_connector_status status;
2128 struct edid *edid = NULL;
2129
2130 intel_dp->has_audio = false;
2131
2132 if (HAS_PCH_SPLIT(dev))
2133 status = ironlake_dp_detect(intel_dp);
2134 else
2135 status = g4x_dp_detect(intel_dp);
1b9be9d0 2136
ac66ae83
AJ		 2137 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2138 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2139 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2140 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 2141
a9756bb5
ZW		 2142 if (status != connector_status_connected)
2143 return status;
2144
c3e5f67b
DV		 2145 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2146 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2147 } else {
8c241fef 2148 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2149 if (edid) {
2150 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2151 connector->display_info.raw_edid = NULL;
2152 kfree(edid);
2153 }
a9756bb5
ZW		 2154 }
2155
2156 return connector_status_connected;
a4fc5ed6
KP		 2157}
2158
2159static int intel_dp_get_modes(struct drm_connector *connector)
2160{
df0e9248 2161 struct intel_dp *intel_dp = intel_attached_dp(connector);
4ef69c7a 2162 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 2163 struct drm_i915_private *dev_priv = dev->dev_private;
2164 int ret;
a4fc5ed6
KP		 2165
2166 /* We should parse the EDID data and find out if it has an audio sink
2167 */
2168
8c241fef 2169 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
b9efc480 2170 if (ret) {
d15456de 2171 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
b9efc480
ZY		 2172 struct drm_display_mode *newmode;
2173 list_for_each_entry(newmode, &connector->probed_modes,
2174 head) {
d15456de
KP		 2175 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2176 intel_dp->panel_fixed_mode =
b9efc480
ZY		 2177 drm_mode_duplicate(dev, newmode);
2178 break;
2179 }
2180 }
2181 }
32f9d658 2182 return ret;
b9efc480 2183 }
32f9d658
ZW		 2184
2185 /* if eDP has no EDID, try to use fixed panel mode from VBT */
4d926461 2186 if (is_edp(intel_dp)) {
47f0eb22 2187 /* initialize panel mode from VBT if available for eDP */
d15456de
KP		 2188 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2189 intel_dp->panel_fixed_mode =
47f0eb22 2190 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
d15456de
KP		 2191 if (intel_dp->panel_fixed_mode) {
2192 intel_dp->panel_fixed_mode->type |=
47f0eb22
KP		 2193 DRM_MODE_TYPE_PREFERRED;
2194 }
2195 }
d15456de 2196 if (intel_dp->panel_fixed_mode) {
32f9d658 2197 struct drm_display_mode *mode;
d15456de 2198 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
32f9d658
ZW		 2199 drm_mode_probed_add(connector, mode);
2200 return 1;
2201 }
2202 }
2203 return 0;
a4fc5ed6
KP		 2204}
2205
1aad7ac0
CW		 2206static bool
2207intel_dp_detect_audio(struct drm_connector *connector)
2208{
2209 struct intel_dp *intel_dp = intel_attached_dp(connector);
2210 struct edid *edid;
2211 bool has_audio = false;
2212
8c241fef 2213 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2214 if (edid) {
2215 has_audio = drm_detect_monitor_audio(edid);
2216
2217 connector->display_info.raw_edid = NULL;
2218 kfree(edid);
2219 }
2220
2221 return has_audio;
2222}
2223
f684960e
CW		 2224static int
2225intel_dp_set_property(struct drm_connector *connector,
2226 struct drm_property *property,
2227 uint64_t val)
2228{
e953fd7b 2229 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2230 struct intel_dp *intel_dp = intel_attached_dp(connector);
2231 int ret;
2232
2233 ret = drm_connector_property_set_value(connector, property, val);
2234 if (ret)
2235 return ret;
2236
3f43c48d 2237 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2238 int i = val;
2239 bool has_audio;
2240
2241 if (i == intel_dp->force_audio)
f684960e
CW		 2242 return 0;
2243
1aad7ac0 2244 intel_dp->force_audio = i;
f684960e 2245
c3e5f67b 2246 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2247 has_audio = intel_dp_detect_audio(connector);
2248 else
c3e5f67b 2249 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2250
2251 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2252 return 0;
2253
1aad7ac0 2254 intel_dp->has_audio = has_audio;
f684960e
CW		 2255 goto done;
2256 }
2257
e953fd7b
CW		 2258 if (property == dev_priv->broadcast_rgb_property) {
2259 if (val == !!intel_dp->color_range)
2260 return 0;
2261
2262 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2263 goto done;
2264 }
2265
f684960e
CW		 2266 return -EINVAL;
2267
2268done:
2269 if (intel_dp->base.base.crtc) {
2270 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2271 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2272 crtc->x, crtc->y,
2273 crtc->fb);
2274 }
2275
2276 return 0;
2277}
2278
a4fc5ed6 2279static void
0206e353 2280intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2281{
aaa6fd2a
MG		 2282 struct drm_device *dev = connector->dev;
2283
2284 if (intel_dpd_is_edp(dev))
2285 intel_panel_destroy_backlight(dev);
2286
a4fc5ed6
KP		 2287 drm_sysfs_connector_remove(connector);
2288 drm_connector_cleanup(connector);
55f78c43 2289 kfree(connector);
a4fc5ed6
KP		 2290}
2291
24d05927
DV		 2292static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2293{
2294 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2295
2296 i2c_del_adapter(&intel_dp->adapter);
2297 drm_encoder_cleanup(encoder);
bd943159
KP		 2298 if (is_edp(intel_dp)) {
2299 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2300 ironlake_panel_vdd_off_sync(intel_dp);
2301 }
24d05927
DV		 2302 kfree(intel_dp);
2303}
2304
a4fc5ed6
KP		 2305static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2306 .dpms = intel_dp_dpms,
2307 .mode_fixup = intel_dp_mode_fixup,
d240f20f 2308 .prepare = intel_dp_prepare,
a4fc5ed6 2309 .mode_set = intel_dp_mode_set,
d240f20f 2310 .commit = intel_dp_commit,
a4fc5ed6
KP		 2311};
2312
2313static const struct drm_connector_funcs intel_dp_connector_funcs = {
2314 .dpms = drm_helper_connector_dpms,
a4fc5ed6
KP		 2315 .detect = intel_dp_detect,
2316 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2317 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2318 .destroy = intel_dp_destroy,
2319};
2320
2321static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2322 .get_modes = intel_dp_get_modes,
2323 .mode_valid = intel_dp_mode_valid,
df0e9248 2324 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2325};
2326
a4fc5ed6 2327static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2328 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2329};
2330
995b6762 2331static void
21d40d37 2332intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2333{
ea5b213a 2334 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2335
885a5014 2336 intel_dp_check_link_status(intel_dp);
c8110e52 2337}
6207937d 2338
e3421a18
ZW		 2339/* Return which DP Port should be selected for Transcoder DP control */
2340int
0206e353 2341intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2342{
2343 struct drm_device *dev = crtc->dev;
2344 struct drm_mode_config *mode_config = &dev->mode_config;
2345 struct drm_encoder *encoder;
e3421a18
ZW		 2346
2347 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
ea5b213a
CW		 2348 struct intel_dp *intel_dp;
2349
d8201ab6 2350 if (encoder->crtc != crtc)
e3421a18
ZW		 2351 continue;
2352
ea5b213a 2353 intel_dp = enc_to_intel_dp(encoder);
417e822d
KP		 2354 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2355 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2356 return intel_dp->output_reg;
e3421a18 2357 }
ea5b213a 2358
e3421a18
ZW		 2359 return -1;
2360}
2361
36e83a18 2362/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2363bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2364{
2365 struct drm_i915_private *dev_priv = dev->dev_private;
2366 struct child_device_config *p_child;
2367 int i;
2368
2369 if (!dev_priv->child_dev_num)
2370 return false;
2371
2372 for (i = 0; i < dev_priv->child_dev_num; i++) {
2373 p_child = dev_priv->child_dev + i;
2374
2375 if (p_child->dvo_port == PORT_IDPD &&
2376 p_child->device_type == DEVICE_TYPE_eDP)
2377 return true;
2378 }
2379 return false;
2380}
2381
f684960e
CW		 2382static void
2383intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2384{
3f43c48d 2385 intel_attach_force_audio_property(connector);
e953fd7b 2386 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2387}
2388
a4fc5ed6
KP		 2389void
2390intel_dp_init(struct drm_device *dev, int output_reg)
2391{
2392 struct drm_i915_private *dev_priv = dev->dev_private;
2393 struct drm_connector *connector;
ea5b213a 2394 struct intel_dp *intel_dp;
21d40d37 2395 struct intel_encoder *intel_encoder;
55f78c43 2396 struct intel_connector *intel_connector;
5eb08b69 2397 const char *name = NULL;
b329530c 2398 int type;
a4fc5ed6 2399
ea5b213a
CW		 2400 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2401 if (!intel_dp)
a4fc5ed6
KP		 2402 return;
2403
3d3dc149 2404 intel_dp->output_reg = output_reg;
d2b996ac 2405 intel_dp->dpms_mode = -1;
3d3dc149 2406
55f78c43
ZW		 2407 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2408 if (!intel_connector) {
ea5b213a 2409 kfree(intel_dp);
55f78c43
ZW		 2410 return;
2411 }
ea5b213a 2412 intel_encoder = &intel_dp->base;
55f78c43 2413
ea5b213a 2414 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2415 if (intel_dpd_is_edp(dev))
ea5b213a 2416 intel_dp->is_pch_edp = true;
b329530c 2417
cfcb0fc9 2418 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2419 type = DRM_MODE_CONNECTOR_eDP;
2420 intel_encoder->type = INTEL_OUTPUT_EDP;
2421 } else {
2422 type = DRM_MODE_CONNECTOR_DisplayPort;
2423 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2424 }
2425
55f78c43 2426 connector = &intel_connector->base;
b329530c 2427 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2428 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2429
eb1f8e4f
DA		 2430 connector->polled = DRM_CONNECTOR_POLL_HPD;
2431
652af9d7 2432 if (output_reg == DP_B || output_reg == PCH_DP_B)
21d40d37 2433 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 2434 else if (output_reg == DP_C || output_reg == PCH_DP_C)
21d40d37 2435 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 2436 else if (output_reg == DP_D || output_reg == PCH_DP_D)
21d40d37 2437 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
f8aed700 2438
bd943159 2439 if (is_edp(intel_dp)) {
21d40d37 2440 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
bd943159
KP		 2441 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2442 ironlake_panel_vdd_work);
2443 }
6251ec0a 2444
27f8227b 2445 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2446
a4fc5ed6
KP		 2447 connector->interlace_allowed = true;
2448 connector->doublescan_allowed = 0;
2449
4ef69c7a 2450 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2451 DRM_MODE_ENCODER_TMDS);
4ef69c7a 2452 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
a4fc5ed6 2453
df0e9248 2454 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2455 drm_sysfs_connector_add(connector);
2456
2457 /* Set up the DDC bus. */
5eb08b69 2458 switch (output_reg) {
32f9d658
ZW		 2459 case DP_A:
2460 name = "DPDDC-A";
2461 break;
5eb08b69
ZW		 2462 case DP_B:
2463 case PCH_DP_B:
b01f2c3a
JB		 2464 dev_priv->hotplug_supported_mask |=
2465 HDMIB_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2466 name = "DPDDC-B";
2467 break;
2468 case DP_C:
2469 case PCH_DP_C:
b01f2c3a
JB		 2470 dev_priv->hotplug_supported_mask |=
2471 HDMIC_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2472 name = "DPDDC-C";
2473 break;
2474 case DP_D:
2475 case PCH_DP_D:
b01f2c3a
JB		 2476 dev_priv->hotplug_supported_mask |=
2477 HDMID_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2478 name = "DPDDC-D";
2479 break;
2480 }
2481
89667383
JB		 2482 /* Cache some DPCD data in the eDP case */
2483 if (is_edp(intel_dp)) {
59f3e272 2484 bool ret;
f01eca2e
KP		 2485 struct edp_power_seq cur, vbt;
2486 u32 pp_on, pp_off, pp_div;
5d613501
JB		 2487
2488 pp_on = I915_READ(PCH_PP_ON_DELAYS);
f01eca2e 2489 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
5d613501 2490 pp_div = I915_READ(PCH_PP_DIVISOR);
89667383 2491
bfa3384a
JB		 2492 if (!pp_on || !pp_off || !pp_div) {
2493 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2494 intel_dp_encoder_destroy(&intel_dp->base.base);
2495 intel_dp_destroy(&intel_connector->base);
2496 return;
2497 }
2498
f01eca2e
KP		 2499 /* Pull timing values out of registers */
2500 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2501 PANEL_POWER_UP_DELAY_SHIFT;
2502
2503 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2504 PANEL_LIGHT_ON_DELAY_SHIFT;
f2e8b18a 2505
f01eca2e
KP		 2506 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2507 PANEL_LIGHT_OFF_DELAY_SHIFT;
2508
2509 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2510 PANEL_POWER_DOWN_DELAY_SHIFT;
2511
2512 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2513 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2514
2515 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2516 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2517
2518 vbt = dev_priv->edp.pps;
2519
2520 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2521 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2522
2523#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2524
2525 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2526 intel_dp->backlight_on_delay = get_delay(t8);
2527 intel_dp->backlight_off_delay = get_delay(t9);
2528 intel_dp->panel_power_down_delay = get_delay(t10);
2529 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2530
2531 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2532 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2533 intel_dp->panel_power_cycle_delay);
2534
2535 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2536 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5d613501
JB		 2537
2538 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2539 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2540 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2541
59f3e272 2542 if (ret) {
7183dc29
JB		 2543 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2544 dev_priv->no_aux_handshake =
2545 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2546 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2547 } else {
3d3dc149 2548 /* if this fails, presume the device is a ghost */
48898b03 2549 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2550 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2551 intel_dp_destroy(&intel_connector->base);
3d3dc149 2552 return;
89667383 2553 }
89667383
JB		 2554 }
2555
552fb0b7
KP		 2556 intel_dp_i2c_init(intel_dp, intel_connector, name);
2557
21d40d37 2558 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2559
4d926461 2560 if (is_edp(intel_dp)) {
aaa6fd2a
MG		 2561 dev_priv->int_edp_connector = connector;
2562 intel_panel_setup_backlight(dev);
32f9d658
ZW		 2563 }
2564
f684960e
CW		 2565 intel_dp_add_properties(intel_dp, connector);
2566
a4fc5ed6
KP		 2567 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2568 * 0xd. Failure to do so will result in spurious interrupts being
2569 * generated on the port when a cable is not attached.
2570 */
2571 if (IS_G4X(dev) && !IS_GM45(dev)) {
2572 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2573 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2574 }
2575}
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