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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
a4fc5ed6 | 37 | #include "i915_drv.h" |
a4fc5ed6 | 38 | |
a4fc5ed6 KP |
39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
40 | ||
9dd4ffdf CML |
41 | struct dp_link_dpll { |
42 | int link_bw; | |
43 | struct dpll dpll; | |
44 | }; | |
45 | ||
46 | static const struct dp_link_dpll gen4_dpll[] = { | |
47 | { DP_LINK_BW_1_62, | |
48 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, | |
49 | { DP_LINK_BW_2_7, | |
50 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } | |
51 | }; | |
52 | ||
53 | static const struct dp_link_dpll pch_dpll[] = { | |
54 | { DP_LINK_BW_1_62, | |
55 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, | |
56 | { DP_LINK_BW_2_7, | |
57 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } | |
58 | }; | |
59 | ||
65ce4bf5 CML |
60 | static const struct dp_link_dpll vlv_dpll[] = { |
61 | { DP_LINK_BW_1_62, | |
58f6e632 | 62 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
65ce4bf5 CML |
63 | { DP_LINK_BW_2_7, |
64 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } | |
65 | }; | |
66 | ||
cfcb0fc9 JB |
67 | /** |
68 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
69 | * @intel_dp: DP struct | |
70 | * | |
71 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
72 | * will return true, and false otherwise. | |
73 | */ | |
74 | static bool is_edp(struct intel_dp *intel_dp) | |
75 | { | |
da63a9f2 PZ |
76 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
77 | ||
78 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
79 | } |
80 | ||
68b4d824 | 81 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 82 | { |
68b4d824 ID |
83 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
84 | ||
85 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
86 | } |
87 | ||
df0e9248 CW |
88 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
89 | { | |
fa90ecef | 90 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
91 | } |
92 | ||
ea5b213a | 93 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
adddaaf4 | 94 | static bool _edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 95 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
a4fc5ed6 | 96 | |
a4fc5ed6 | 97 | static int |
ea5b213a | 98 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 99 | { |
7183dc29 | 100 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
06ea66b6 | 101 | struct drm_device *dev = intel_dp->attached_connector->base.dev; |
a4fc5ed6 KP |
102 | |
103 | switch (max_link_bw) { | |
104 | case DP_LINK_BW_1_62: | |
105 | case DP_LINK_BW_2_7: | |
106 | break; | |
d4eead50 | 107 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ |
06ea66b6 TP |
108 | if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) && |
109 | intel_dp->dpcd[DP_DPCD_REV] >= 0x12) | |
110 | max_link_bw = DP_LINK_BW_5_4; | |
111 | else | |
112 | max_link_bw = DP_LINK_BW_2_7; | |
d4eead50 | 113 | break; |
a4fc5ed6 | 114 | default: |
d4eead50 ID |
115 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
116 | max_link_bw); | |
a4fc5ed6 KP |
117 | max_link_bw = DP_LINK_BW_1_62; |
118 | break; | |
119 | } | |
120 | return max_link_bw; | |
121 | } | |
122 | ||
cd9dde44 AJ |
123 | /* |
124 | * The units on the numbers in the next two are... bizarre. Examples will | |
125 | * make it clearer; this one parallels an example in the eDP spec. | |
126 | * | |
127 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
128 | * | |
129 | * 270000 * 1 * 8 / 10 == 216000 | |
130 | * | |
131 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
132 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
133 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
134 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
135 | * | |
136 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
137 | * get the result in decakilobits instead of kilobits. | |
138 | */ | |
139 | ||
a4fc5ed6 | 140 | static int |
c898261c | 141 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 142 | { |
cd9dde44 | 143 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
144 | } |
145 | ||
fe27d53e DA |
146 | static int |
147 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
148 | { | |
149 | return (max_link_clock * max_lanes * 8) / 10; | |
150 | } | |
151 | ||
c19de8eb | 152 | static enum drm_mode_status |
a4fc5ed6 KP |
153 | intel_dp_mode_valid(struct drm_connector *connector, |
154 | struct drm_display_mode *mode) | |
155 | { | |
df0e9248 | 156 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
157 | struct intel_connector *intel_connector = to_intel_connector(connector); |
158 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
159 | int target_clock = mode->clock; |
160 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
a4fc5ed6 | 161 | |
dd06f90e JN |
162 | if (is_edp(intel_dp) && fixed_mode) { |
163 | if (mode->hdisplay > fixed_mode->hdisplay) | |
7de56f43 ZY |
164 | return MODE_PANEL; |
165 | ||
dd06f90e | 166 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 167 | return MODE_PANEL; |
03afc4a2 DV |
168 | |
169 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
170 | } |
171 | ||
36008365 DV |
172 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
173 | max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); | |
174 | ||
175 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
176 | mode_rate = intel_dp_link_required(target_clock, 18); | |
177 | ||
178 | if (mode_rate > max_rate) | |
c4867936 | 179 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
180 | |
181 | if (mode->clock < 10000) | |
182 | return MODE_CLOCK_LOW; | |
183 | ||
0af78a2b DV |
184 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
185 | return MODE_H_ILLEGAL; | |
186 | ||
a4fc5ed6 KP |
187 | return MODE_OK; |
188 | } | |
189 | ||
190 | static uint32_t | |
191 | pack_aux(uint8_t *src, int src_bytes) | |
192 | { | |
193 | int i; | |
194 | uint32_t v = 0; | |
195 | ||
196 | if (src_bytes > 4) | |
197 | src_bytes = 4; | |
198 | for (i = 0; i < src_bytes; i++) | |
199 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
200 | return v; | |
201 | } | |
202 | ||
203 | static void | |
204 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
205 | { | |
206 | int i; | |
207 | if (dst_bytes > 4) | |
208 | dst_bytes = 4; | |
209 | for (i = 0; i < dst_bytes; i++) | |
210 | dst[i] = src >> ((3-i) * 8); | |
211 | } | |
212 | ||
fb0f8fbf KP |
213 | /* hrawclock is 1/4 the FSB frequency */ |
214 | static int | |
215 | intel_hrawclk(struct drm_device *dev) | |
216 | { | |
217 | struct drm_i915_private *dev_priv = dev->dev_private; | |
218 | uint32_t clkcfg; | |
219 | ||
9473c8f4 VP |
220 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
221 | if (IS_VALLEYVIEW(dev)) | |
222 | return 200; | |
223 | ||
fb0f8fbf KP |
224 | clkcfg = I915_READ(CLKCFG); |
225 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
226 | case CLKCFG_FSB_400: | |
227 | return 100; | |
228 | case CLKCFG_FSB_533: | |
229 | return 133; | |
230 | case CLKCFG_FSB_667: | |
231 | return 166; | |
232 | case CLKCFG_FSB_800: | |
233 | return 200; | |
234 | case CLKCFG_FSB_1067: | |
235 | return 266; | |
236 | case CLKCFG_FSB_1333: | |
237 | return 333; | |
238 | /* these two are just a guess; one of them might be right */ | |
239 | case CLKCFG_FSB_1600: | |
240 | case CLKCFG_FSB_1600_ALT: | |
241 | return 400; | |
242 | default: | |
243 | return 133; | |
244 | } | |
245 | } | |
246 | ||
bf13e81b JN |
247 | static void |
248 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
249 | struct intel_dp *intel_dp, | |
250 | struct edp_power_seq *out); | |
251 | static void | |
252 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
253 | struct intel_dp *intel_dp, | |
254 | struct edp_power_seq *out); | |
255 | ||
256 | static enum pipe | |
257 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
258 | { | |
259 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
260 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
261 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
262 | struct drm_i915_private *dev_priv = dev->dev_private; | |
263 | enum port port = intel_dig_port->port; | |
264 | enum pipe pipe; | |
265 | ||
266 | /* modeset should have pipe */ | |
267 | if (crtc) | |
268 | return to_intel_crtc(crtc)->pipe; | |
269 | ||
270 | /* init time, try to find a pipe with this port selected */ | |
271 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { | |
272 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & | |
273 | PANEL_PORT_SELECT_MASK; | |
274 | if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) | |
275 | return pipe; | |
276 | if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) | |
277 | return pipe; | |
278 | } | |
279 | ||
280 | /* shrug */ | |
281 | return PIPE_A; | |
282 | } | |
283 | ||
284 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) | |
285 | { | |
286 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
287 | ||
288 | if (HAS_PCH_SPLIT(dev)) | |
289 | return PCH_PP_CONTROL; | |
290 | else | |
291 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); | |
292 | } | |
293 | ||
294 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) | |
295 | { | |
296 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
297 | ||
298 | if (HAS_PCH_SPLIT(dev)) | |
299 | return PCH_PP_STATUS; | |
300 | else | |
301 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); | |
302 | } | |
303 | ||
4be73780 | 304 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 305 | { |
30add22d | 306 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
307 | struct drm_i915_private *dev_priv = dev->dev_private; |
308 | ||
bf13e81b | 309 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
310 | } |
311 | ||
4be73780 | 312 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 313 | { |
30add22d | 314 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
315 | struct drm_i915_private *dev_priv = dev->dev_private; |
316 | ||
efbc20ab PZ |
317 | return !dev_priv->pm.suspended && |
318 | (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; | |
ebf33b18 KP |
319 | } |
320 | ||
9b984dae KP |
321 | static void |
322 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
323 | { | |
30add22d | 324 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9b984dae | 325 | struct drm_i915_private *dev_priv = dev->dev_private; |
ebf33b18 | 326 | |
9b984dae KP |
327 | if (!is_edp(intel_dp)) |
328 | return; | |
453c5420 | 329 | |
4be73780 | 330 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
331 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
332 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
333 | I915_READ(_pp_stat_reg(intel_dp)), |
334 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
335 | } |
336 | } | |
337 | ||
9ee32fea DV |
338 | static uint32_t |
339 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
340 | { | |
341 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
342 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
343 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9ed35ab1 | 344 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
345 | uint32_t status; |
346 | bool done; | |
347 | ||
ef04f00d | 348 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 349 | if (has_aux_irq) |
b18ac466 | 350 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 351 | msecs_to_jiffies_timeout(10)); |
9ee32fea DV |
352 | else |
353 | done = wait_for_atomic(C, 10) == 0; | |
354 | if (!done) | |
355 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
356 | has_aux_irq); | |
357 | #undef C | |
358 | ||
359 | return status; | |
360 | } | |
361 | ||
ec5b01dd | 362 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 363 | { |
174edf1f PZ |
364 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
365 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
9ee32fea | 366 | |
ec5b01dd DL |
367 | /* |
368 | * The clock divider is based off the hrawclk, and would like to run at | |
369 | * 2MHz. So, take the hrawclk value and divide by 2 and use that | |
a4fc5ed6 | 370 | */ |
ec5b01dd DL |
371 | return index ? 0 : intel_hrawclk(dev) / 2; |
372 | } | |
373 | ||
374 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
375 | { | |
376 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
377 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
378 | ||
379 | if (index) | |
380 | return 0; | |
381 | ||
382 | if (intel_dig_port->port == PORT_A) { | |
383 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
b84a1cf8 | 384 | return 200; /* SNB & IVB eDP input clock at 400Mhz */ |
e3421a18 | 385 | else |
b84a1cf8 | 386 | return 225; /* eDP input clock at 450Mhz */ |
ec5b01dd DL |
387 | } else { |
388 | return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); | |
389 | } | |
390 | } | |
391 | ||
392 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
393 | { | |
394 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
395 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
396 | struct drm_i915_private *dev_priv = dev->dev_private; | |
397 | ||
398 | if (intel_dig_port->port == PORT_A) { | |
399 | if (index) | |
400 | return 0; | |
401 | return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); | |
2c55c336 JN |
402 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
403 | /* Workaround for non-ULT HSW */ | |
bc86625a CW |
404 | switch (index) { |
405 | case 0: return 63; | |
406 | case 1: return 72; | |
407 | default: return 0; | |
408 | } | |
ec5b01dd | 409 | } else { |
bc86625a | 410 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
2c55c336 | 411 | } |
b84a1cf8 RV |
412 | } |
413 | ||
ec5b01dd DL |
414 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
415 | { | |
416 | return index ? 0 : 100; | |
417 | } | |
418 | ||
5ed12a19 DL |
419 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
420 | bool has_aux_irq, | |
421 | int send_bytes, | |
422 | uint32_t aux_clock_divider) | |
423 | { | |
424 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
425 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
426 | uint32_t precharge, timeout; | |
427 | ||
428 | if (IS_GEN6(dev)) | |
429 | precharge = 3; | |
430 | else | |
431 | precharge = 5; | |
432 | ||
433 | if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) | |
434 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; | |
435 | else | |
436 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
437 | ||
438 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 439 | DP_AUX_CH_CTL_DONE | |
5ed12a19 | 440 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
788d4433 | 441 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 442 | timeout | |
788d4433 | 443 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
444 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
445 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 446 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
447 | } |
448 | ||
b84a1cf8 RV |
449 | static int |
450 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
451 | uint8_t *send, int send_bytes, | |
452 | uint8_t *recv, int recv_size) | |
453 | { | |
454 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
455 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
456 | struct drm_i915_private *dev_priv = dev->dev_private; | |
457 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; | |
458 | uint32_t ch_data = ch_ctl + 4; | |
bc86625a | 459 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
460 | int i, ret, recv_bytes; |
461 | uint32_t status; | |
5ed12a19 | 462 | int try, clock = 0; |
4e6b788c | 463 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
884f19e9 JN |
464 | bool vdd; |
465 | ||
466 | vdd = _edp_panel_vdd_on(intel_dp); | |
b84a1cf8 RV |
467 | |
468 | /* dp aux is extremely sensitive to irq latency, hence request the | |
469 | * lowest possible wakeup latency and so prevent the cpu from going into | |
470 | * deep sleep states. | |
471 | */ | |
472 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
473 | ||
474 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 475 | |
c67a470b PZ |
476 | intel_aux_display_runtime_get(dev_priv); |
477 | ||
11bee43e JB |
478 | /* Try to wait for any previous AUX channel activity */ |
479 | for (try = 0; try < 3; try++) { | |
ef04f00d | 480 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
481 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
482 | break; | |
483 | msleep(1); | |
484 | } | |
485 | ||
486 | if (try == 3) { | |
487 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
488 | I915_READ(ch_ctl)); | |
9ee32fea DV |
489 | ret = -EBUSY; |
490 | goto out; | |
4f7f7b7e CW |
491 | } |
492 | ||
46a5ae9f PZ |
493 | /* Only 5 data registers! */ |
494 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
495 | ret = -E2BIG; | |
496 | goto out; | |
497 | } | |
498 | ||
ec5b01dd | 499 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
153b1100 DL |
500 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
501 | has_aux_irq, | |
502 | send_bytes, | |
503 | aux_clock_divider); | |
5ed12a19 | 504 | |
bc86625a CW |
505 | /* Must try at least 3 times according to DP spec */ |
506 | for (try = 0; try < 5; try++) { | |
507 | /* Load the send data into the aux channel data registers */ | |
508 | for (i = 0; i < send_bytes; i += 4) | |
509 | I915_WRITE(ch_data + i, | |
510 | pack_aux(send + i, send_bytes - i)); | |
511 | ||
512 | /* Send the command and wait for it to complete */ | |
5ed12a19 | 513 | I915_WRITE(ch_ctl, send_ctl); |
bc86625a CW |
514 | |
515 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
516 | ||
517 | /* Clear done status and any errors */ | |
518 | I915_WRITE(ch_ctl, | |
519 | status | | |
520 | DP_AUX_CH_CTL_DONE | | |
521 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
522 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
523 | ||
524 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
525 | DP_AUX_CH_CTL_RECEIVE_ERROR)) | |
526 | continue; | |
527 | if (status & DP_AUX_CH_CTL_DONE) | |
528 | break; | |
529 | } | |
4f7f7b7e | 530 | if (status & DP_AUX_CH_CTL_DONE) |
a4fc5ed6 KP |
531 | break; |
532 | } | |
533 | ||
a4fc5ed6 | 534 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 535 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
536 | ret = -EBUSY; |
537 | goto out; | |
a4fc5ed6 KP |
538 | } |
539 | ||
540 | /* Check for timeout or receive error. | |
541 | * Timeouts occur when the sink is not connected | |
542 | */ | |
a5b3da54 | 543 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 544 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
545 | ret = -EIO; |
546 | goto out; | |
a5b3da54 | 547 | } |
1ae8c0a5 KP |
548 | |
549 | /* Timeouts occur when the device isn't connected, so they're | |
550 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 551 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 552 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
553 | ret = -ETIMEDOUT; |
554 | goto out; | |
a4fc5ed6 KP |
555 | } |
556 | ||
557 | /* Unload any bytes sent back from the other side */ | |
558 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
559 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
560 | if (recv_bytes > recv_size) |
561 | recv_bytes = recv_size; | |
0206e353 | 562 | |
4f7f7b7e CW |
563 | for (i = 0; i < recv_bytes; i += 4) |
564 | unpack_aux(I915_READ(ch_data + i), | |
565 | recv + i, recv_bytes - i); | |
a4fc5ed6 | 566 | |
9ee32fea DV |
567 | ret = recv_bytes; |
568 | out: | |
569 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
c67a470b | 570 | intel_aux_display_runtime_put(dev_priv); |
9ee32fea | 571 | |
884f19e9 JN |
572 | if (vdd) |
573 | edp_panel_vdd_off(intel_dp, false); | |
574 | ||
9ee32fea | 575 | return ret; |
a4fc5ed6 KP |
576 | } |
577 | ||
a6c8aff0 JN |
578 | #define BARE_ADDRESS_SIZE 3 |
579 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
9d1a1031 JN |
580 | static ssize_t |
581 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 582 | { |
9d1a1031 JN |
583 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
584 | uint8_t txbuf[20], rxbuf[20]; | |
585 | size_t txsize, rxsize; | |
a4fc5ed6 | 586 | int ret; |
a4fc5ed6 | 587 | |
9d1a1031 JN |
588 | txbuf[0] = msg->request << 4; |
589 | txbuf[1] = msg->address >> 8; | |
590 | txbuf[2] = msg->address & 0xff; | |
591 | txbuf[3] = msg->size - 1; | |
46a5ae9f | 592 | |
9d1a1031 JN |
593 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
594 | case DP_AUX_NATIVE_WRITE: | |
595 | case DP_AUX_I2C_WRITE: | |
a6c8aff0 | 596 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
9d1a1031 | 597 | rxsize = 1; |
f51a44b9 | 598 | |
9d1a1031 JN |
599 | if (WARN_ON(txsize > 20)) |
600 | return -E2BIG; | |
a4fc5ed6 | 601 | |
9d1a1031 | 602 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
a4fc5ed6 | 603 | |
9d1a1031 JN |
604 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
605 | if (ret > 0) { | |
606 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 607 | |
9d1a1031 JN |
608 | /* Return payload size. */ |
609 | ret = msg->size; | |
610 | } | |
611 | break; | |
46a5ae9f | 612 | |
9d1a1031 JN |
613 | case DP_AUX_NATIVE_READ: |
614 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 615 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 616 | rxsize = msg->size + 1; |
a4fc5ed6 | 617 | |
9d1a1031 JN |
618 | if (WARN_ON(rxsize > 20)) |
619 | return -E2BIG; | |
a4fc5ed6 | 620 | |
9d1a1031 JN |
621 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
622 | if (ret > 0) { | |
623 | msg->reply = rxbuf[0] >> 4; | |
624 | /* | |
625 | * Assume happy day, and copy the data. The caller is | |
626 | * expected to check msg->reply before touching it. | |
627 | * | |
628 | * Return payload size. | |
629 | */ | |
630 | ret--; | |
631 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 632 | } |
9d1a1031 JN |
633 | break; |
634 | ||
635 | default: | |
636 | ret = -EINVAL; | |
637 | break; | |
a4fc5ed6 | 638 | } |
f51a44b9 | 639 | |
9d1a1031 | 640 | return ret; |
a4fc5ed6 KP |
641 | } |
642 | ||
9d1a1031 JN |
643 | static void |
644 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) | |
645 | { | |
646 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
33ad6626 JN |
647 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
648 | enum port port = intel_dig_port->port; | |
0b99836f | 649 | const char *name = NULL; |
ab2c0672 DA |
650 | int ret; |
651 | ||
33ad6626 JN |
652 | switch (port) { |
653 | case PORT_A: | |
654 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; | |
0b99836f | 655 | name = "DPDDC-A"; |
ab2c0672 | 656 | break; |
33ad6626 JN |
657 | case PORT_B: |
658 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; | |
0b99836f | 659 | name = "DPDDC-B"; |
ab2c0672 | 660 | break; |
33ad6626 JN |
661 | case PORT_C: |
662 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; | |
0b99836f | 663 | name = "DPDDC-C"; |
ab2c0672 | 664 | break; |
33ad6626 JN |
665 | case PORT_D: |
666 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; | |
0b99836f | 667 | name = "DPDDC-D"; |
33ad6626 JN |
668 | break; |
669 | default: | |
670 | BUG(); | |
ab2c0672 DA |
671 | } |
672 | ||
33ad6626 JN |
673 | if (!HAS_DDI(dev)) |
674 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; | |
8316f337 | 675 | |
0b99836f | 676 | intel_dp->aux.name = name; |
9d1a1031 JN |
677 | intel_dp->aux.dev = dev->dev; |
678 | intel_dp->aux.transfer = intel_dp_aux_transfer; | |
8316f337 | 679 | |
0b99836f JN |
680 | DRM_DEBUG_KMS("registering %s bus for %s\n", name, |
681 | connector->base.kdev->kobj.name); | |
8316f337 | 682 | |
0b99836f JN |
683 | ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux); |
684 | if (ret < 0) { | |
685 | DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n", | |
686 | name, ret); | |
687 | return; | |
ab2c0672 | 688 | } |
8a5e6aeb | 689 | |
0b99836f JN |
690 | ret = sysfs_create_link(&connector->base.kdev->kobj, |
691 | &intel_dp->aux.ddc.dev.kobj, | |
692 | intel_dp->aux.ddc.dev.kobj.name); | |
693 | if (ret < 0) { | |
694 | DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret); | |
695 | drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); | |
ab2c0672 | 696 | } |
a4fc5ed6 KP |
697 | } |
698 | ||
80f65de3 ID |
699 | static void |
700 | intel_dp_connector_unregister(struct intel_connector *intel_connector) | |
701 | { | |
702 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); | |
703 | ||
704 | sysfs_remove_link(&intel_connector->base.kdev->kobj, | |
0b99836f | 705 | intel_dp->aux.ddc.dev.kobj.name); |
80f65de3 ID |
706 | intel_connector_unregister(intel_connector); |
707 | } | |
708 | ||
c6bb3538 DV |
709 | static void |
710 | intel_dp_set_clock(struct intel_encoder *encoder, | |
711 | struct intel_crtc_config *pipe_config, int link_bw) | |
712 | { | |
713 | struct drm_device *dev = encoder->base.dev; | |
9dd4ffdf CML |
714 | const struct dp_link_dpll *divisor = NULL; |
715 | int i, count = 0; | |
c6bb3538 DV |
716 | |
717 | if (IS_G4X(dev)) { | |
9dd4ffdf CML |
718 | divisor = gen4_dpll; |
719 | count = ARRAY_SIZE(gen4_dpll); | |
c6bb3538 DV |
720 | } else if (IS_HASWELL(dev)) { |
721 | /* Haswell has special-purpose DP DDI clocks. */ | |
722 | } else if (HAS_PCH_SPLIT(dev)) { | |
9dd4ffdf CML |
723 | divisor = pch_dpll; |
724 | count = ARRAY_SIZE(pch_dpll); | |
c6bb3538 | 725 | } else if (IS_VALLEYVIEW(dev)) { |
65ce4bf5 CML |
726 | divisor = vlv_dpll; |
727 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 728 | } |
9dd4ffdf CML |
729 | |
730 | if (divisor && count) { | |
731 | for (i = 0; i < count; i++) { | |
732 | if (link_bw == divisor[i].link_bw) { | |
733 | pipe_config->dpll = divisor[i].dpll; | |
734 | pipe_config->clock_set = true; | |
735 | break; | |
736 | } | |
737 | } | |
c6bb3538 DV |
738 | } |
739 | } | |
740 | ||
00c09d70 | 741 | bool |
5bfe2ac0 DV |
742 | intel_dp_compute_config(struct intel_encoder *encoder, |
743 | struct intel_crtc_config *pipe_config) | |
a4fc5ed6 | 744 | { |
5bfe2ac0 | 745 | struct drm_device *dev = encoder->base.dev; |
36008365 | 746 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfe2ac0 | 747 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
5bfe2ac0 | 748 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 749 | enum port port = dp_to_dig_port(intel_dp)->port; |
2dd24552 | 750 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
dd06f90e | 751 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
a4fc5ed6 | 752 | int lane_count, clock; |
397fe157 | 753 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
06ea66b6 TP |
754 | /* Conveniently, the link BW constants become indices with a shift...*/ |
755 | int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; | |
083f9560 | 756 | int bpp, mode_rate; |
06ea66b6 | 757 | static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; |
ff9a6750 | 758 | int link_avail, link_clock; |
a4fc5ed6 | 759 | |
bc7d38a4 | 760 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
5bfe2ac0 DV |
761 | pipe_config->has_pch_encoder = true; |
762 | ||
03afc4a2 | 763 | pipe_config->has_dp_encoder = true; |
a4fc5ed6 | 764 | |
dd06f90e JN |
765 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
766 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
767 | adjusted_mode); | |
2dd24552 JB |
768 | if (!HAS_PCH_SPLIT(dev)) |
769 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
770 | intel_connector->panel.fitting_mode); | |
771 | else | |
b074cec8 JB |
772 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
773 | intel_connector->panel.fitting_mode); | |
0d3a1bee ZY |
774 | } |
775 | ||
cb1793ce | 776 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
777 | return false; |
778 | ||
083f9560 DV |
779 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
780 | "max bw %02x pixel clock %iKHz\n", | |
241bfc38 DL |
781 | max_lane_count, bws[max_clock], |
782 | adjusted_mode->crtc_clock); | |
083f9560 | 783 | |
36008365 DV |
784 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
785 | * bpc in between. */ | |
3e7ca985 | 786 | bpp = pipe_config->pipe_bpp; |
6da7f10d JN |
787 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
788 | dev_priv->vbt.edp_bpp < bpp) { | |
7984211e ID |
789 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
790 | dev_priv->vbt.edp_bpp); | |
6da7f10d | 791 | bpp = dev_priv->vbt.edp_bpp; |
7984211e | 792 | } |
657445fe | 793 | |
36008365 | 794 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
795 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
796 | bpp); | |
36008365 | 797 | |
38aecea0 DV |
798 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
799 | for (clock = 0; clock <= max_clock; clock++) { | |
36008365 DV |
800 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); |
801 | link_avail = intel_dp_max_data_rate(link_clock, | |
802 | lane_count); | |
803 | ||
804 | if (mode_rate <= link_avail) { | |
805 | goto found; | |
806 | } | |
807 | } | |
808 | } | |
809 | } | |
c4867936 | 810 | |
36008365 | 811 | return false; |
3685a8f3 | 812 | |
36008365 | 813 | found: |
55bc60db VS |
814 | if (intel_dp->color_range_auto) { |
815 | /* | |
816 | * See: | |
817 | * CEA-861-E - 5.1 Default Encoding Parameters | |
818 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
819 | */ | |
18316c8c | 820 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
55bc60db VS |
821 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
822 | else | |
823 | intel_dp->color_range = 0; | |
824 | } | |
825 | ||
3685a8f3 | 826 | if (intel_dp->color_range) |
50f3b016 | 827 | pipe_config->limited_color_range = true; |
a4fc5ed6 | 828 | |
36008365 DV |
829 | intel_dp->link_bw = bws[clock]; |
830 | intel_dp->lane_count = lane_count; | |
657445fe | 831 | pipe_config->pipe_bpp = bpp; |
ff9a6750 | 832 | pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
a4fc5ed6 | 833 | |
36008365 DV |
834 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
835 | intel_dp->link_bw, intel_dp->lane_count, | |
ff9a6750 | 836 | pipe_config->port_clock, bpp); |
36008365 DV |
837 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
838 | mode_rate, link_avail); | |
a4fc5ed6 | 839 | |
03afc4a2 | 840 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
841 | adjusted_mode->crtc_clock, |
842 | pipe_config->port_clock, | |
03afc4a2 | 843 | &pipe_config->dp_m_n); |
9d1a455b | 844 | |
c6bb3538 DV |
845 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); |
846 | ||
03afc4a2 | 847 | return true; |
a4fc5ed6 KP |
848 | } |
849 | ||
7c62a164 | 850 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
ea9b6006 | 851 | { |
7c62a164 DV |
852 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
853 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); | |
854 | struct drm_device *dev = crtc->base.dev; | |
ea9b6006 DV |
855 | struct drm_i915_private *dev_priv = dev->dev_private; |
856 | u32 dpa_ctl; | |
857 | ||
ff9a6750 | 858 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); |
ea9b6006 DV |
859 | dpa_ctl = I915_READ(DP_A); |
860 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
861 | ||
ff9a6750 | 862 | if (crtc->config.port_clock == 162000) { |
1ce17038 DV |
863 | /* For a long time we've carried around a ILK-DevA w/a for the |
864 | * 160MHz clock. If we're really unlucky, it's still required. | |
865 | */ | |
866 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); | |
ea9b6006 | 867 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
7c62a164 | 868 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
ea9b6006 DV |
869 | } else { |
870 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
7c62a164 | 871 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
ea9b6006 | 872 | } |
1ce17038 | 873 | |
ea9b6006 DV |
874 | I915_WRITE(DP_A, dpa_ctl); |
875 | ||
876 | POSTING_READ(DP_A); | |
877 | udelay(500); | |
878 | } | |
879 | ||
b934223d | 880 | static void intel_dp_mode_set(struct intel_encoder *encoder) |
a4fc5ed6 | 881 | { |
b934223d | 882 | struct drm_device *dev = encoder->base.dev; |
417e822d | 883 | struct drm_i915_private *dev_priv = dev->dev_private; |
b934223d | 884 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 885 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d DV |
886 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
887 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
a4fc5ed6 | 888 | |
417e822d | 889 | /* |
1a2eb460 | 890 | * There are four kinds of DP registers: |
417e822d KP |
891 | * |
892 | * IBX PCH | |
1a2eb460 KP |
893 | * SNB CPU |
894 | * IVB CPU | |
417e822d KP |
895 | * CPT PCH |
896 | * | |
897 | * IBX PCH and CPU are the same for almost everything, | |
898 | * except that the CPU DP PLL is configured in this | |
899 | * register | |
900 | * | |
901 | * CPT PCH is quite different, having many bits moved | |
902 | * to the TRANS_DP_CTL register instead. That | |
903 | * configuration happens (oddly) in ironlake_pch_enable | |
904 | */ | |
9c9e7927 | 905 | |
417e822d KP |
906 | /* Preserve the BIOS-computed detected bit. This is |
907 | * supposed to be read-only. | |
908 | */ | |
909 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 910 | |
417e822d | 911 | /* Handle DP bits in common between all three register formats */ |
417e822d | 912 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
17aa6be9 | 913 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
a4fc5ed6 | 914 | |
e0dac65e WF |
915 | if (intel_dp->has_audio) { |
916 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", | |
7c62a164 | 917 | pipe_name(crtc->pipe)); |
ea5b213a | 918 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
b934223d | 919 | intel_write_eld(&encoder->base, adjusted_mode); |
e0dac65e | 920 | } |
247d89f6 | 921 | |
417e822d | 922 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 923 | |
bc7d38a4 | 924 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
1a2eb460 KP |
925 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
926 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
927 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
928 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
929 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
930 | ||
6aba5b6c | 931 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
932 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
933 | ||
7c62a164 | 934 | intel_dp->DP |= crtc->pipe << 29; |
bc7d38a4 | 935 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
b2634017 | 936 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) |
3685a8f3 | 937 | intel_dp->DP |= intel_dp->color_range; |
417e822d KP |
938 | |
939 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
940 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
941 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
942 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
943 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
944 | ||
6aba5b6c | 945 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
946 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
947 | ||
7c62a164 | 948 | if (crtc->pipe == 1) |
417e822d | 949 | intel_dp->DP |= DP_PIPEB_SELECT; |
417e822d KP |
950 | } else { |
951 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
32f9d658 | 952 | } |
ea9b6006 | 953 | |
bc7d38a4 | 954 | if (port == PORT_A && !IS_VALLEYVIEW(dev)) |
7c62a164 | 955 | ironlake_set_pll_cpu_edp(intel_dp); |
a4fc5ed6 KP |
956 | } |
957 | ||
ffd6749d PZ |
958 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
959 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 960 | |
1a5ef5b7 PZ |
961 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
962 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 963 | |
ffd6749d PZ |
964 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
965 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 966 | |
4be73780 | 967 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
968 | u32 mask, |
969 | u32 value) | |
bd943159 | 970 | { |
30add22d | 971 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
99ea7127 | 972 | struct drm_i915_private *dev_priv = dev->dev_private; |
453c5420 JB |
973 | u32 pp_stat_reg, pp_ctrl_reg; |
974 | ||
bf13e81b JN |
975 | pp_stat_reg = _pp_stat_reg(intel_dp); |
976 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 977 | |
99ea7127 | 978 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
979 | mask, value, |
980 | I915_READ(pp_stat_reg), | |
981 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 982 | |
453c5420 | 983 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
99ea7127 | 984 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
985 | I915_READ(pp_stat_reg), |
986 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 987 | } |
54c136d4 CW |
988 | |
989 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 990 | } |
32ce697c | 991 | |
4be73780 | 992 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
993 | { |
994 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 995 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
996 | } |
997 | ||
4be73780 | 998 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
999 | { |
1000 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 1001 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
1002 | } |
1003 | ||
4be73780 | 1004 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 KP |
1005 | { |
1006 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); | |
dce56b3c PZ |
1007 | |
1008 | /* When we disable the VDD override bit last we have to do the manual | |
1009 | * wait. */ | |
1010 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, | |
1011 | intel_dp->panel_power_cycle_delay); | |
1012 | ||
4be73780 | 1013 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
1014 | } |
1015 | ||
4be73780 | 1016 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
1017 | { |
1018 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
1019 | intel_dp->backlight_on_delay); | |
1020 | } | |
1021 | ||
4be73780 | 1022 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
1023 | { |
1024 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
1025 | intel_dp->backlight_off_delay); | |
1026 | } | |
99ea7127 | 1027 | |
832dd3c1 KP |
1028 | /* Read the current pp_control value, unlocking the register if it |
1029 | * is locked | |
1030 | */ | |
1031 | ||
453c5420 | 1032 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 1033 | { |
453c5420 JB |
1034 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1036 | u32 control; | |
832dd3c1 | 1037 | |
bf13e81b | 1038 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
832dd3c1 KP |
1039 | control &= ~PANEL_UNLOCK_MASK; |
1040 | control |= PANEL_UNLOCK_REGS; | |
1041 | return control; | |
bd943159 KP |
1042 | } |
1043 | ||
adddaaf4 | 1044 | static bool _edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 1045 | { |
30add22d | 1046 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5d613501 JB |
1047 | struct drm_i915_private *dev_priv = dev->dev_private; |
1048 | u32 pp; | |
453c5420 | 1049 | u32 pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 1050 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 1051 | |
97af61f5 | 1052 | if (!is_edp(intel_dp)) |
adddaaf4 | 1053 | return false; |
bd943159 KP |
1054 | |
1055 | intel_dp->want_panel_vdd = true; | |
99ea7127 | 1056 | |
4be73780 | 1057 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 1058 | return need_to_disable; |
b0665d57 | 1059 | |
e9cb81a2 PZ |
1060 | intel_runtime_pm_get(dev_priv); |
1061 | ||
b0665d57 | 1062 | DRM_DEBUG_KMS("Turning eDP VDD on\n"); |
bd943159 | 1063 | |
4be73780 DV |
1064 | if (!edp_have_panel_power(intel_dp)) |
1065 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 1066 | |
453c5420 | 1067 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 1068 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 1069 | |
bf13e81b JN |
1070 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1071 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
1072 | |
1073 | I915_WRITE(pp_ctrl_reg, pp); | |
1074 | POSTING_READ(pp_ctrl_reg); | |
1075 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1076 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
1077 | /* |
1078 | * If the panel wasn't on, delay before accessing aux channel | |
1079 | */ | |
4be73780 | 1080 | if (!edp_have_panel_power(intel_dp)) { |
bd943159 | 1081 | DRM_DEBUG_KMS("eDP was not running\n"); |
f01eca2e | 1082 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 1083 | } |
adddaaf4 JN |
1084 | |
1085 | return need_to_disable; | |
1086 | } | |
1087 | ||
b80d6c78 | 1088 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 JN |
1089 | { |
1090 | if (is_edp(intel_dp)) { | |
1091 | bool vdd = _edp_panel_vdd_on(intel_dp); | |
1092 | ||
1093 | WARN(!vdd, "eDP VDD already requested on\n"); | |
1094 | } | |
5d613501 JB |
1095 | } |
1096 | ||
4be73780 | 1097 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 1098 | { |
30add22d | 1099 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5d613501 JB |
1100 | struct drm_i915_private *dev_priv = dev->dev_private; |
1101 | u32 pp; | |
453c5420 | 1102 | u32 pp_stat_reg, pp_ctrl_reg; |
5d613501 | 1103 | |
a0e99e68 DV |
1104 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
1105 | ||
4be73780 | 1106 | if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { |
b0665d57 PZ |
1107 | DRM_DEBUG_KMS("Turning eDP VDD off\n"); |
1108 | ||
453c5420 | 1109 | pp = ironlake_get_pp_control(intel_dp); |
bd943159 | 1110 | pp &= ~EDP_FORCE_VDD; |
bd943159 | 1111 | |
9f08ef59 PZ |
1112 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1113 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
453c5420 JB |
1114 | |
1115 | I915_WRITE(pp_ctrl_reg, pp); | |
1116 | POSTING_READ(pp_ctrl_reg); | |
99ea7127 | 1117 | |
453c5420 JB |
1118 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1119 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1120 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
90791a5c PZ |
1121 | |
1122 | if ((pp & POWER_TARGET_ON) == 0) | |
dce56b3c | 1123 | intel_dp->last_power_cycle = jiffies; |
e9cb81a2 PZ |
1124 | |
1125 | intel_runtime_pm_put(dev_priv); | |
bd943159 KP |
1126 | } |
1127 | } | |
5d613501 | 1128 | |
4be73780 | 1129 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
1130 | { |
1131 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
1132 | struct intel_dp, panel_vdd_work); | |
30add22d | 1133 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bd943159 | 1134 | |
627f7675 | 1135 | mutex_lock(&dev->mode_config.mutex); |
4be73780 | 1136 | edp_panel_vdd_off_sync(intel_dp); |
627f7675 | 1137 | mutex_unlock(&dev->mode_config.mutex); |
bd943159 KP |
1138 | } |
1139 | ||
4be73780 | 1140 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 1141 | { |
97af61f5 KP |
1142 | if (!is_edp(intel_dp)) |
1143 | return; | |
5d613501 | 1144 | |
bd943159 | 1145 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
f2e8b18a | 1146 | |
bd943159 KP |
1147 | intel_dp->want_panel_vdd = false; |
1148 | ||
1149 | if (sync) { | |
4be73780 | 1150 | edp_panel_vdd_off_sync(intel_dp); |
bd943159 KP |
1151 | } else { |
1152 | /* | |
1153 | * Queue the timer to fire a long | |
1154 | * time from now (relative to the power down delay) | |
1155 | * to keep the panel power up across a sequence of operations | |
1156 | */ | |
1157 | schedule_delayed_work(&intel_dp->panel_vdd_work, | |
1158 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
1159 | } | |
5d613501 JB |
1160 | } |
1161 | ||
4be73780 | 1162 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 1163 | { |
30add22d | 1164 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1165 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1166 | u32 pp; |
453c5420 | 1167 | u32 pp_ctrl_reg; |
9934c132 | 1168 | |
97af61f5 | 1169 | if (!is_edp(intel_dp)) |
bd943159 | 1170 | return; |
99ea7127 KP |
1171 | |
1172 | DRM_DEBUG_KMS("Turn eDP power on\n"); | |
1173 | ||
4be73780 | 1174 | if (edp_have_panel_power(intel_dp)) { |
99ea7127 | 1175 | DRM_DEBUG_KMS("eDP power already on\n"); |
7d639f35 | 1176 | return; |
99ea7127 | 1177 | } |
9934c132 | 1178 | |
4be73780 | 1179 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 1180 | |
bf13e81b | 1181 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 1182 | pp = ironlake_get_pp_control(intel_dp); |
05ce1a49 KP |
1183 | if (IS_GEN5(dev)) { |
1184 | /* ILK workaround: disable reset around power sequence */ | |
1185 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
1186 | I915_WRITE(pp_ctrl_reg, pp); |
1187 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1188 | } |
37c6c9b0 | 1189 | |
1c0ae80a | 1190 | pp |= POWER_TARGET_ON; |
99ea7127 KP |
1191 | if (!IS_GEN5(dev)) |
1192 | pp |= PANEL_POWER_RESET; | |
1193 | ||
453c5420 JB |
1194 | I915_WRITE(pp_ctrl_reg, pp); |
1195 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1196 | |
4be73780 | 1197 | wait_panel_on(intel_dp); |
dce56b3c | 1198 | intel_dp->last_power_on = jiffies; |
9934c132 | 1199 | |
05ce1a49 KP |
1200 | if (IS_GEN5(dev)) { |
1201 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
bf13e81b JN |
1202 | I915_WRITE(pp_ctrl_reg, pp); |
1203 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1204 | } |
9934c132 JB |
1205 | } |
1206 | ||
4be73780 | 1207 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
9934c132 | 1208 | { |
30add22d | 1209 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1210 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1211 | u32 pp; |
453c5420 | 1212 | u32 pp_ctrl_reg; |
9934c132 | 1213 | |
97af61f5 KP |
1214 | if (!is_edp(intel_dp)) |
1215 | return; | |
37c6c9b0 | 1216 | |
99ea7127 | 1217 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
37c6c9b0 | 1218 | |
4be73780 | 1219 | edp_wait_backlight_off(intel_dp); |
dce56b3c | 1220 | |
24f3e092 JN |
1221 | WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); |
1222 | ||
453c5420 | 1223 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
1224 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
1225 | * panels get very unhappy and cease to work. */ | |
b3064154 PJ |
1226 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
1227 | EDP_BLC_ENABLE); | |
453c5420 | 1228 | |
bf13e81b | 1229 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 1230 | |
849e39f5 PZ |
1231 | intel_dp->want_panel_vdd = false; |
1232 | ||
453c5420 JB |
1233 | I915_WRITE(pp_ctrl_reg, pp); |
1234 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1235 | |
dce56b3c | 1236 | intel_dp->last_power_cycle = jiffies; |
4be73780 | 1237 | wait_panel_off(intel_dp); |
849e39f5 PZ |
1238 | |
1239 | /* We got a reference when we enabled the VDD. */ | |
1240 | intel_runtime_pm_put(dev_priv); | |
9934c132 JB |
1241 | } |
1242 | ||
4be73780 | 1243 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
32f9d658 | 1244 | { |
da63a9f2 PZ |
1245 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1246 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
32f9d658 ZW |
1247 | struct drm_i915_private *dev_priv = dev->dev_private; |
1248 | u32 pp; | |
453c5420 | 1249 | u32 pp_ctrl_reg; |
32f9d658 | 1250 | |
f01eca2e KP |
1251 | if (!is_edp(intel_dp)) |
1252 | return; | |
1253 | ||
28c97730 | 1254 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
1255 | /* |
1256 | * If we enable the backlight right away following a panel power | |
1257 | * on, we may see slight flicker as the panel syncs with the eDP | |
1258 | * link. So delay a bit to make sure the image is solid before | |
1259 | * allowing it to appear. | |
1260 | */ | |
4be73780 | 1261 | wait_backlight_on(intel_dp); |
453c5420 | 1262 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 1263 | pp |= EDP_BLC_ENABLE; |
453c5420 | 1264 | |
bf13e81b | 1265 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
1266 | |
1267 | I915_WRITE(pp_ctrl_reg, pp); | |
1268 | POSTING_READ(pp_ctrl_reg); | |
035aa3de | 1269 | |
752aa88a | 1270 | intel_panel_enable_backlight(intel_dp->attached_connector); |
32f9d658 ZW |
1271 | } |
1272 | ||
4be73780 | 1273 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
32f9d658 | 1274 | { |
30add22d | 1275 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
32f9d658 ZW |
1276 | struct drm_i915_private *dev_priv = dev->dev_private; |
1277 | u32 pp; | |
453c5420 | 1278 | u32 pp_ctrl_reg; |
32f9d658 | 1279 | |
f01eca2e KP |
1280 | if (!is_edp(intel_dp)) |
1281 | return; | |
1282 | ||
752aa88a | 1283 | intel_panel_disable_backlight(intel_dp->attached_connector); |
035aa3de | 1284 | |
28c97730 | 1285 | DRM_DEBUG_KMS("\n"); |
453c5420 | 1286 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 1287 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 1288 | |
bf13e81b | 1289 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
1290 | |
1291 | I915_WRITE(pp_ctrl_reg, pp); | |
1292 | POSTING_READ(pp_ctrl_reg); | |
dce56b3c | 1293 | intel_dp->last_backlight_off = jiffies; |
32f9d658 | 1294 | } |
a4fc5ed6 | 1295 | |
2bd2ad64 | 1296 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
d240f20f | 1297 | { |
da63a9f2 PZ |
1298 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1299 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
1300 | struct drm_device *dev = crtc->dev; | |
d240f20f JB |
1301 | struct drm_i915_private *dev_priv = dev->dev_private; |
1302 | u32 dpa_ctl; | |
1303 | ||
2bd2ad64 DV |
1304 | assert_pipe_disabled(dev_priv, |
1305 | to_intel_crtc(crtc)->pipe); | |
1306 | ||
d240f20f JB |
1307 | DRM_DEBUG_KMS("\n"); |
1308 | dpa_ctl = I915_READ(DP_A); | |
0767935e DV |
1309 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
1310 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); | |
1311 | ||
1312 | /* We don't adjust intel_dp->DP while tearing down the link, to | |
1313 | * facilitate link retraining (e.g. after hotplug). Hence clear all | |
1314 | * enable bits here to ensure that we don't enable too much. */ | |
1315 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); | |
1316 | intel_dp->DP |= DP_PLL_ENABLE; | |
1317 | I915_WRITE(DP_A, intel_dp->DP); | |
298b0b39 JB |
1318 | POSTING_READ(DP_A); |
1319 | udelay(200); | |
d240f20f JB |
1320 | } |
1321 | ||
2bd2ad64 | 1322 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 1323 | { |
da63a9f2 PZ |
1324 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1325 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
1326 | struct drm_device *dev = crtc->dev; | |
d240f20f JB |
1327 | struct drm_i915_private *dev_priv = dev->dev_private; |
1328 | u32 dpa_ctl; | |
1329 | ||
2bd2ad64 DV |
1330 | assert_pipe_disabled(dev_priv, |
1331 | to_intel_crtc(crtc)->pipe); | |
1332 | ||
d240f20f | 1333 | dpa_ctl = I915_READ(DP_A); |
0767935e DV |
1334 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
1335 | "dp pll off, should be on\n"); | |
1336 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); | |
1337 | ||
1338 | /* We can't rely on the value tracked for the DP register in | |
1339 | * intel_dp->DP because link_down must not change that (otherwise link | |
1340 | * re-training will fail. */ | |
298b0b39 | 1341 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 1342 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 1343 | POSTING_READ(DP_A); |
d240f20f JB |
1344 | udelay(200); |
1345 | } | |
1346 | ||
c7ad3810 | 1347 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 1348 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
1349 | { |
1350 | int ret, i; | |
1351 | ||
1352 | /* Should have a valid DPCD by this point */ | |
1353 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
1354 | return; | |
1355 | ||
1356 | if (mode != DRM_MODE_DPMS_ON) { | |
9d1a1031 JN |
1357 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
1358 | DP_SET_POWER_D3); | |
c7ad3810 JB |
1359 | if (ret != 1) |
1360 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
1361 | } else { | |
1362 | /* | |
1363 | * When turning on, we need to retry for 1ms to give the sink | |
1364 | * time to wake up. | |
1365 | */ | |
1366 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
1367 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
1368 | DP_SET_POWER_D0); | |
c7ad3810 JB |
1369 | if (ret == 1) |
1370 | break; | |
1371 | msleep(1); | |
1372 | } | |
1373 | } | |
1374 | } | |
1375 | ||
19d8fe15 DV |
1376 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
1377 | enum pipe *pipe) | |
d240f20f | 1378 | { |
19d8fe15 | 1379 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1380 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 DV |
1381 | struct drm_device *dev = encoder->base.dev; |
1382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d129bea ID |
1383 | enum intel_display_power_domain power_domain; |
1384 | u32 tmp; | |
1385 | ||
1386 | power_domain = intel_display_port_power_domain(encoder); | |
1387 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
1388 | return false; | |
1389 | ||
1390 | tmp = I915_READ(intel_dp->output_reg); | |
19d8fe15 DV |
1391 | |
1392 | if (!(tmp & DP_PORT_EN)) | |
1393 | return false; | |
1394 | ||
bc7d38a4 | 1395 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
19d8fe15 | 1396 | *pipe = PORT_TO_PIPE_CPT(tmp); |
bc7d38a4 | 1397 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
19d8fe15 DV |
1398 | *pipe = PORT_TO_PIPE(tmp); |
1399 | } else { | |
1400 | u32 trans_sel; | |
1401 | u32 trans_dp; | |
1402 | int i; | |
1403 | ||
1404 | switch (intel_dp->output_reg) { | |
1405 | case PCH_DP_B: | |
1406 | trans_sel = TRANS_DP_PORT_SEL_B; | |
1407 | break; | |
1408 | case PCH_DP_C: | |
1409 | trans_sel = TRANS_DP_PORT_SEL_C; | |
1410 | break; | |
1411 | case PCH_DP_D: | |
1412 | trans_sel = TRANS_DP_PORT_SEL_D; | |
1413 | break; | |
1414 | default: | |
1415 | return true; | |
1416 | } | |
1417 | ||
1418 | for_each_pipe(i) { | |
1419 | trans_dp = I915_READ(TRANS_DP_CTL(i)); | |
1420 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { | |
1421 | *pipe = i; | |
1422 | return true; | |
1423 | } | |
1424 | } | |
19d8fe15 | 1425 | |
4a0833ec DV |
1426 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
1427 | intel_dp->output_reg); | |
1428 | } | |
d240f20f | 1429 | |
19d8fe15 DV |
1430 | return true; |
1431 | } | |
d240f20f | 1432 | |
045ac3b5 JB |
1433 | static void intel_dp_get_config(struct intel_encoder *encoder, |
1434 | struct intel_crtc_config *pipe_config) | |
1435 | { | |
1436 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 1437 | u32 tmp, flags = 0; |
63000ef6 XZ |
1438 | struct drm_device *dev = encoder->base.dev; |
1439 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1440 | enum port port = dp_to_dig_port(intel_dp)->port; | |
1441 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
18442d08 | 1442 | int dotclock; |
045ac3b5 | 1443 | |
63000ef6 XZ |
1444 | if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { |
1445 | tmp = I915_READ(intel_dp->output_reg); | |
1446 | if (tmp & DP_SYNC_HS_HIGH) | |
1447 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1448 | else | |
1449 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 1450 | |
63000ef6 XZ |
1451 | if (tmp & DP_SYNC_VS_HIGH) |
1452 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1453 | else | |
1454 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1455 | } else { | |
1456 | tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
1457 | if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
1458 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1459 | else | |
1460 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 1461 | |
63000ef6 XZ |
1462 | if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
1463 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1464 | else | |
1465 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1466 | } | |
045ac3b5 JB |
1467 | |
1468 | pipe_config->adjusted_mode.flags |= flags; | |
f1f644dc | 1469 | |
eb14cb74 VS |
1470 | pipe_config->has_dp_encoder = true; |
1471 | ||
1472 | intel_dp_get_m_n(crtc, pipe_config); | |
1473 | ||
18442d08 | 1474 | if (port == PORT_A) { |
f1f644dc JB |
1475 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
1476 | pipe_config->port_clock = 162000; | |
1477 | else | |
1478 | pipe_config->port_clock = 270000; | |
1479 | } | |
18442d08 VS |
1480 | |
1481 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, | |
1482 | &pipe_config->dp_m_n); | |
1483 | ||
1484 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) | |
1485 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
1486 | ||
241bfc38 | 1487 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
7f16e5c1 | 1488 | |
c6cd2ee2 JN |
1489 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
1490 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { | |
1491 | /* | |
1492 | * This is a big fat ugly hack. | |
1493 | * | |
1494 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
1495 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
1496 | * unknown we fail to light up. Yet the same BIOS boots up with | |
1497 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
1498 | * max, not what it tells us to use. | |
1499 | * | |
1500 | * Note: This will still be broken if the eDP panel is not lit | |
1501 | * up by the BIOS, and thus we can't get the mode at module | |
1502 | * load. | |
1503 | */ | |
1504 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
1505 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); | |
1506 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; | |
1507 | } | |
045ac3b5 JB |
1508 | } |
1509 | ||
a031d709 | 1510 | static bool is_edp_psr(struct drm_device *dev) |
2293bb5c | 1511 | { |
a031d709 RV |
1512 | struct drm_i915_private *dev_priv = dev->dev_private; |
1513 | ||
1514 | return dev_priv->psr.sink_support; | |
2293bb5c SK |
1515 | } |
1516 | ||
2b28bb1b RV |
1517 | static bool intel_edp_is_psr_enabled(struct drm_device *dev) |
1518 | { | |
1519 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1520 | ||
18b5992c | 1521 | if (!HAS_PSR(dev)) |
2b28bb1b RV |
1522 | return false; |
1523 | ||
18b5992c | 1524 | return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
2b28bb1b RV |
1525 | } |
1526 | ||
1527 | static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, | |
1528 | struct edp_vsc_psr *vsc_psr) | |
1529 | { | |
1530 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
1531 | struct drm_device *dev = dig_port->base.base.dev; | |
1532 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1533 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); | |
1534 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); | |
1535 | u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); | |
1536 | uint32_t *data = (uint32_t *) vsc_psr; | |
1537 | unsigned int i; | |
1538 | ||
1539 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable | |
1540 | the video DIP being updated before program video DIP data buffer | |
1541 | registers for DIP being updated. */ | |
1542 | I915_WRITE(ctl_reg, 0); | |
1543 | POSTING_READ(ctl_reg); | |
1544 | ||
1545 | for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { | |
1546 | if (i < sizeof(struct edp_vsc_psr)) | |
1547 | I915_WRITE(data_reg + i, *data++); | |
1548 | else | |
1549 | I915_WRITE(data_reg + i, 0); | |
1550 | } | |
1551 | ||
1552 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); | |
1553 | POSTING_READ(ctl_reg); | |
1554 | } | |
1555 | ||
1556 | static void intel_edp_psr_setup(struct intel_dp *intel_dp) | |
1557 | { | |
1558 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1559 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1560 | struct edp_vsc_psr psr_vsc; | |
1561 | ||
1562 | if (intel_dp->psr_setup_done) | |
1563 | return; | |
1564 | ||
1565 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ | |
1566 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
1567 | psr_vsc.sdp_header.HB0 = 0; | |
1568 | psr_vsc.sdp_header.HB1 = 0x7; | |
1569 | psr_vsc.sdp_header.HB2 = 0x2; | |
1570 | psr_vsc.sdp_header.HB3 = 0x8; | |
1571 | intel_edp_psr_write_vsc(intel_dp, &psr_vsc); | |
1572 | ||
1573 | /* Avoid continuous PSR exit by masking memup and hpd */ | |
18b5992c | 1574 | I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | |
0cc4b699 | 1575 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); |
2b28bb1b RV |
1576 | |
1577 | intel_dp->psr_setup_done = true; | |
1578 | } | |
1579 | ||
1580 | static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) | |
1581 | { | |
1582 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1583 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ec5b01dd | 1584 | uint32_t aux_clock_divider; |
2b28bb1b RV |
1585 | int precharge = 0x3; |
1586 | int msg_size = 5; /* Header(4) + Message(1) */ | |
1587 | ||
ec5b01dd DL |
1588 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
1589 | ||
2b28bb1b RV |
1590 | /* Enable PSR in sink */ |
1591 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) | |
9d1a1031 JN |
1592 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
1593 | DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); | |
2b28bb1b | 1594 | else |
9d1a1031 JN |
1595 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
1596 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); | |
2b28bb1b RV |
1597 | |
1598 | /* Setup AUX registers */ | |
18b5992c BW |
1599 | I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); |
1600 | I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); | |
1601 | I915_WRITE(EDP_PSR_AUX_CTL(dev), | |
2b28bb1b RV |
1602 | DP_AUX_CH_CTL_TIME_OUT_400us | |
1603 | (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
1604 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
1605 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); | |
1606 | } | |
1607 | ||
1608 | static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) | |
1609 | { | |
1610 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1611 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1612 | uint32_t max_sleep_time = 0x1f; | |
1613 | uint32_t idle_frames = 1; | |
1614 | uint32_t val = 0x0; | |
ed8546ac | 1615 | const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
2b28bb1b RV |
1616 | |
1617 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { | |
1618 | val |= EDP_PSR_LINK_STANDBY; | |
1619 | val |= EDP_PSR_TP2_TP3_TIME_0us; | |
1620 | val |= EDP_PSR_TP1_TIME_0us; | |
1621 | val |= EDP_PSR_SKIP_AUX_EXIT; | |
1622 | } else | |
1623 | val |= EDP_PSR_LINK_DISABLE; | |
1624 | ||
18b5992c | 1625 | I915_WRITE(EDP_PSR_CTL(dev), val | |
24bd9bf5 | 1626 | (IS_BROADWELL(dev) ? 0 : link_entry_time) | |
2b28bb1b RV |
1627 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | |
1628 | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | | |
1629 | EDP_PSR_ENABLE); | |
1630 | } | |
1631 | ||
3f51e471 RV |
1632 | static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) |
1633 | { | |
1634 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
1635 | struct drm_device *dev = dig_port->base.base.dev; | |
1636 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1637 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
1638 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
f4510a27 | 1639 | struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj; |
3f51e471 RV |
1640 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
1641 | ||
a031d709 RV |
1642 | dev_priv->psr.source_ok = false; |
1643 | ||
18b5992c | 1644 | if (!HAS_PSR(dev)) { |
3f51e471 | 1645 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); |
3f51e471 RV |
1646 | return false; |
1647 | } | |
1648 | ||
1649 | if ((intel_encoder->type != INTEL_OUTPUT_EDP) || | |
1650 | (dig_port->port != PORT_A)) { | |
1651 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); | |
3f51e471 RV |
1652 | return false; |
1653 | } | |
1654 | ||
d330a953 | 1655 | if (!i915.enable_psr) { |
105b7c11 | 1656 | DRM_DEBUG_KMS("PSR disable by flag\n"); |
105b7c11 RV |
1657 | return false; |
1658 | } | |
1659 | ||
cd234b0b CW |
1660 | crtc = dig_port->base.base.crtc; |
1661 | if (crtc == NULL) { | |
1662 | DRM_DEBUG_KMS("crtc not active for PSR\n"); | |
cd234b0b CW |
1663 | return false; |
1664 | } | |
1665 | ||
1666 | intel_crtc = to_intel_crtc(crtc); | |
20ddf665 | 1667 | if (!intel_crtc_active(crtc)) { |
3f51e471 | 1668 | DRM_DEBUG_KMS("crtc not active for PSR\n"); |
3f51e471 RV |
1669 | return false; |
1670 | } | |
1671 | ||
f4510a27 | 1672 | obj = to_intel_framebuffer(crtc->primary->fb)->obj; |
3f51e471 RV |
1673 | if (obj->tiling_mode != I915_TILING_X || |
1674 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
1675 | DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); | |
3f51e471 RV |
1676 | return false; |
1677 | } | |
1678 | ||
1679 | if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { | |
1680 | DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); | |
3f51e471 RV |
1681 | return false; |
1682 | } | |
1683 | ||
1684 | if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & | |
1685 | S3D_ENABLE) { | |
1686 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); | |
3f51e471 RV |
1687 | return false; |
1688 | } | |
1689 | ||
ca73b4f0 | 1690 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
3f51e471 | 1691 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
3f51e471 RV |
1692 | return false; |
1693 | } | |
1694 | ||
a031d709 | 1695 | dev_priv->psr.source_ok = true; |
3f51e471 RV |
1696 | return true; |
1697 | } | |
1698 | ||
3d739d92 | 1699 | static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) |
2b28bb1b RV |
1700 | { |
1701 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1702 | ||
3f51e471 RV |
1703 | if (!intel_edp_psr_match_conditions(intel_dp) || |
1704 | intel_edp_is_psr_enabled(dev)) | |
2b28bb1b RV |
1705 | return; |
1706 | ||
1707 | /* Setup PSR once */ | |
1708 | intel_edp_psr_setup(intel_dp); | |
1709 | ||
1710 | /* Enable PSR on the panel */ | |
1711 | intel_edp_psr_enable_sink(intel_dp); | |
1712 | ||
1713 | /* Enable PSR on the host */ | |
1714 | intel_edp_psr_enable_source(intel_dp); | |
1715 | } | |
1716 | ||
3d739d92 RV |
1717 | void intel_edp_psr_enable(struct intel_dp *intel_dp) |
1718 | { | |
1719 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1720 | ||
1721 | if (intel_edp_psr_match_conditions(intel_dp) && | |
1722 | !intel_edp_is_psr_enabled(dev)) | |
1723 | intel_edp_psr_do_enable(intel_dp); | |
1724 | } | |
1725 | ||
2b28bb1b RV |
1726 | void intel_edp_psr_disable(struct intel_dp *intel_dp) |
1727 | { | |
1728 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1729 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1730 | ||
1731 | if (!intel_edp_is_psr_enabled(dev)) | |
1732 | return; | |
1733 | ||
18b5992c BW |
1734 | I915_WRITE(EDP_PSR_CTL(dev), |
1735 | I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); | |
2b28bb1b RV |
1736 | |
1737 | /* Wait till PSR is idle */ | |
18b5992c | 1738 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & |
2b28bb1b RV |
1739 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) |
1740 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); | |
1741 | } | |
1742 | ||
3d739d92 RV |
1743 | void intel_edp_psr_update(struct drm_device *dev) |
1744 | { | |
1745 | struct intel_encoder *encoder; | |
1746 | struct intel_dp *intel_dp = NULL; | |
1747 | ||
1748 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) | |
1749 | if (encoder->type == INTEL_OUTPUT_EDP) { | |
1750 | intel_dp = enc_to_intel_dp(&encoder->base); | |
1751 | ||
a031d709 | 1752 | if (!is_edp_psr(dev)) |
3d739d92 RV |
1753 | return; |
1754 | ||
1755 | if (!intel_edp_psr_match_conditions(intel_dp)) | |
1756 | intel_edp_psr_disable(intel_dp); | |
1757 | else | |
1758 | if (!intel_edp_is_psr_enabled(dev)) | |
1759 | intel_edp_psr_do_enable(intel_dp); | |
1760 | } | |
1761 | } | |
1762 | ||
e8cb4558 | 1763 | static void intel_disable_dp(struct intel_encoder *encoder) |
d240f20f | 1764 | { |
e8cb4558 | 1765 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 ID |
1766 | enum port port = dp_to_dig_port(intel_dp)->port; |
1767 | struct drm_device *dev = encoder->base.dev; | |
6cb49835 DV |
1768 | |
1769 | /* Make sure the panel is off before trying to change the mode. But also | |
1770 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 1771 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 1772 | intel_edp_backlight_off(intel_dp); |
fdbc3b1f | 1773 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 1774 | intel_edp_panel_off(intel_dp); |
3739850b DV |
1775 | |
1776 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ | |
982a3866 | 1777 | if (!(port == PORT_A || IS_VALLEYVIEW(dev))) |
3739850b | 1778 | intel_dp_link_down(intel_dp); |
d240f20f JB |
1779 | } |
1780 | ||
2bd2ad64 | 1781 | static void intel_post_disable_dp(struct intel_encoder *encoder) |
d240f20f | 1782 | { |
2bd2ad64 | 1783 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 1784 | enum port port = dp_to_dig_port(intel_dp)->port; |
b2634017 | 1785 | struct drm_device *dev = encoder->base.dev; |
2bd2ad64 | 1786 | |
982a3866 | 1787 | if (port == PORT_A || IS_VALLEYVIEW(dev)) { |
3739850b | 1788 | intel_dp_link_down(intel_dp); |
b2634017 JB |
1789 | if (!IS_VALLEYVIEW(dev)) |
1790 | ironlake_edp_pll_off(intel_dp); | |
3739850b | 1791 | } |
2bd2ad64 DV |
1792 | } |
1793 | ||
e8cb4558 | 1794 | static void intel_enable_dp(struct intel_encoder *encoder) |
d240f20f | 1795 | { |
e8cb4558 DV |
1796 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1797 | struct drm_device *dev = encoder->base.dev; | |
1798 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1799 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); | |
5d613501 | 1800 | |
0c33d8d7 DV |
1801 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
1802 | return; | |
5d613501 | 1803 | |
24f3e092 | 1804 | intel_edp_panel_vdd_on(intel_dp); |
f01eca2e | 1805 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 1806 | intel_dp_start_link_train(intel_dp); |
4be73780 DV |
1807 | intel_edp_panel_on(intel_dp); |
1808 | edp_panel_vdd_off(intel_dp, true); | |
33a34e4e | 1809 | intel_dp_complete_link_train(intel_dp); |
3ab9c637 | 1810 | intel_dp_stop_link_train(intel_dp); |
ab1f90f9 | 1811 | } |
89b667f8 | 1812 | |
ecff4f3b JN |
1813 | static void g4x_enable_dp(struct intel_encoder *encoder) |
1814 | { | |
828f5c6e JN |
1815 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1816 | ||
ecff4f3b | 1817 | intel_enable_dp(encoder); |
4be73780 | 1818 | intel_edp_backlight_on(intel_dp); |
ab1f90f9 | 1819 | } |
89b667f8 | 1820 | |
ab1f90f9 JN |
1821 | static void vlv_enable_dp(struct intel_encoder *encoder) |
1822 | { | |
828f5c6e JN |
1823 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1824 | ||
4be73780 | 1825 | intel_edp_backlight_on(intel_dp); |
d240f20f JB |
1826 | } |
1827 | ||
ecff4f3b | 1828 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
ab1f90f9 JN |
1829 | { |
1830 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
1831 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
1832 | ||
1833 | if (dport->port == PORT_A) | |
1834 | ironlake_edp_pll_on(intel_dp); | |
1835 | } | |
1836 | ||
1837 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) | |
a4fc5ed6 | 1838 | { |
2bd2ad64 | 1839 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1840 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
b2634017 | 1841 | struct drm_device *dev = encoder->base.dev; |
89b667f8 | 1842 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab1f90f9 | 1843 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
e4607fcf | 1844 | enum dpio_channel port = vlv_dport_to_channel(dport); |
ab1f90f9 | 1845 | int pipe = intel_crtc->pipe; |
bf13e81b | 1846 | struct edp_power_seq power_seq; |
ab1f90f9 | 1847 | u32 val; |
a4fc5ed6 | 1848 | |
ab1f90f9 | 1849 | mutex_lock(&dev_priv->dpio_lock); |
89b667f8 | 1850 | |
ab3c759a | 1851 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
ab1f90f9 JN |
1852 | val = 0; |
1853 | if (pipe) | |
1854 | val |= (1<<21); | |
1855 | else | |
1856 | val &= ~(1<<21); | |
1857 | val |= 0x001000c4; | |
ab3c759a CML |
1858 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
1859 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); | |
1860 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
89b667f8 | 1861 | |
ab1f90f9 JN |
1862 | mutex_unlock(&dev_priv->dpio_lock); |
1863 | ||
2cac613b ID |
1864 | if (is_edp(intel_dp)) { |
1865 | /* init power sequencer on this pipe and port */ | |
1866 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); | |
1867 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, | |
1868 | &power_seq); | |
1869 | } | |
bf13e81b | 1870 | |
ab1f90f9 JN |
1871 | intel_enable_dp(encoder); |
1872 | ||
e4607fcf | 1873 | vlv_wait_port_ready(dev_priv, dport); |
89b667f8 JB |
1874 | } |
1875 | ||
ecff4f3b | 1876 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1877 | { |
1878 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1879 | struct drm_device *dev = encoder->base.dev; | |
1880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1881 | struct intel_crtc *intel_crtc = |
1882 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1883 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1884 | int pipe = intel_crtc->pipe; |
89b667f8 | 1885 | |
89b667f8 | 1886 | /* Program Tx lane resets to default */ |
0980a60f | 1887 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1888 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
1889 | DPIO_PCS_TX_LANE2_RESET | |
1890 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 1891 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
1892 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1893 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1894 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1895 | DPIO_PCS_CLK_SOFT_RESET); | |
1896 | ||
1897 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
1898 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1899 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
1900 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
0980a60f | 1901 | mutex_unlock(&dev_priv->dpio_lock); |
a4fc5ed6 KP |
1902 | } |
1903 | ||
1904 | /* | |
df0c237d JB |
1905 | * Native read with retry for link status and receiver capability reads for |
1906 | * cases where the sink may still be asleep. | |
9d1a1031 JN |
1907 | * |
1908 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also | |
1909 | * supposed to retry 3 times per the spec. | |
a4fc5ed6 | 1910 | */ |
9d1a1031 JN |
1911 | static ssize_t |
1912 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, | |
1913 | void *buffer, size_t size) | |
a4fc5ed6 | 1914 | { |
9d1a1031 JN |
1915 | ssize_t ret; |
1916 | int i; | |
61da5fab | 1917 | |
61da5fab | 1918 | for (i = 0; i < 3; i++) { |
9d1a1031 JN |
1919 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
1920 | if (ret == size) | |
1921 | return ret; | |
61da5fab JB |
1922 | msleep(1); |
1923 | } | |
a4fc5ed6 | 1924 | |
9d1a1031 | 1925 | return ret; |
a4fc5ed6 KP |
1926 | } |
1927 | ||
1928 | /* | |
1929 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
1930 | * link status information | |
1931 | */ | |
1932 | static bool | |
93f62dad | 1933 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 1934 | { |
9d1a1031 JN |
1935 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
1936 | DP_LANE0_1_STATUS, | |
1937 | link_status, | |
1938 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
1939 | } |
1940 | ||
a4fc5ed6 KP |
1941 | /* |
1942 | * These are source-specific values; current Intel hardware supports | |
1943 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1944 | */ | |
a4fc5ed6 KP |
1945 | |
1946 | static uint8_t | |
1a2eb460 | 1947 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 1948 | { |
30add22d | 1949 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 1950 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 1951 | |
8f93f4f1 | 1952 | if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev)) |
e2fa6fba | 1953 | return DP_TRAIN_VOLTAGE_SWING_1200; |
bc7d38a4 | 1954 | else if (IS_GEN7(dev) && port == PORT_A) |
1a2eb460 | 1955 | return DP_TRAIN_VOLTAGE_SWING_800; |
bc7d38a4 | 1956 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
1a2eb460 KP |
1957 | return DP_TRAIN_VOLTAGE_SWING_1200; |
1958 | else | |
1959 | return DP_TRAIN_VOLTAGE_SWING_800; | |
1960 | } | |
1961 | ||
1962 | static uint8_t | |
1963 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) | |
1964 | { | |
30add22d | 1965 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 1966 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 1967 | |
8f93f4f1 PZ |
1968 | if (IS_BROADWELL(dev)) { |
1969 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1970 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1971 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1972 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1973 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1974 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1975 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1976 | default: | |
1977 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1978 | } | |
1979 | } else if (IS_HASWELL(dev)) { | |
d6c0d722 PZ |
1980 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1981 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1982 | return DP_TRAIN_PRE_EMPHASIS_9_5; | |
1983 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1984 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1985 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1986 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1987 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1988 | default: | |
1989 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1990 | } | |
e2fa6fba P |
1991 | } else if (IS_VALLEYVIEW(dev)) { |
1992 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1993 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1994 | return DP_TRAIN_PRE_EMPHASIS_9_5; | |
1995 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1996 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1997 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1998 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1999 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2000 | default: | |
2001 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2002 | } | |
bc7d38a4 | 2003 | } else if (IS_GEN7(dev) && port == PORT_A) { |
1a2eb460 KP |
2004 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2005 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2006 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2007 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2008 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2009 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2010 | default: | |
2011 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2012 | } | |
2013 | } else { | |
2014 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2015 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2016 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2017 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2018 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2019 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2020 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2021 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2022 | default: | |
2023 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2024 | } | |
a4fc5ed6 KP |
2025 | } |
2026 | } | |
2027 | ||
e2fa6fba P |
2028 | static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) |
2029 | { | |
2030 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
2031 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2032 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
5e69f97f CML |
2033 | struct intel_crtc *intel_crtc = |
2034 | to_intel_crtc(dport->base.base.crtc); | |
e2fa6fba P |
2035 | unsigned long demph_reg_value, preemph_reg_value, |
2036 | uniqtranscale_reg_value; | |
2037 | uint8_t train_set = intel_dp->train_set[0]; | |
e4607fcf | 2038 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 2039 | int pipe = intel_crtc->pipe; |
e2fa6fba P |
2040 | |
2041 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
2042 | case DP_TRAIN_PRE_EMPHASIS_0: | |
2043 | preemph_reg_value = 0x0004000; | |
2044 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2045 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2046 | demph_reg_value = 0x2B405555; | |
2047 | uniqtranscale_reg_value = 0x552AB83A; | |
2048 | break; | |
2049 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2050 | demph_reg_value = 0x2B404040; | |
2051 | uniqtranscale_reg_value = 0x5548B83A; | |
2052 | break; | |
2053 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2054 | demph_reg_value = 0x2B245555; | |
2055 | uniqtranscale_reg_value = 0x5560B83A; | |
2056 | break; | |
2057 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2058 | demph_reg_value = 0x2B405555; | |
2059 | uniqtranscale_reg_value = 0x5598DA3A; | |
2060 | break; | |
2061 | default: | |
2062 | return 0; | |
2063 | } | |
2064 | break; | |
2065 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
2066 | preemph_reg_value = 0x0002000; | |
2067 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2068 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2069 | demph_reg_value = 0x2B404040; | |
2070 | uniqtranscale_reg_value = 0x5552B83A; | |
2071 | break; | |
2072 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2073 | demph_reg_value = 0x2B404848; | |
2074 | uniqtranscale_reg_value = 0x5580B83A; | |
2075 | break; | |
2076 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2077 | demph_reg_value = 0x2B404040; | |
2078 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2079 | break; | |
2080 | default: | |
2081 | return 0; | |
2082 | } | |
2083 | break; | |
2084 | case DP_TRAIN_PRE_EMPHASIS_6: | |
2085 | preemph_reg_value = 0x0000000; | |
2086 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2087 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2088 | demph_reg_value = 0x2B305555; | |
2089 | uniqtranscale_reg_value = 0x5570B83A; | |
2090 | break; | |
2091 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2092 | demph_reg_value = 0x2B2B4040; | |
2093 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2094 | break; | |
2095 | default: | |
2096 | return 0; | |
2097 | } | |
2098 | break; | |
2099 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
2100 | preemph_reg_value = 0x0006000; | |
2101 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2102 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2103 | demph_reg_value = 0x1B405555; | |
2104 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2105 | break; | |
2106 | default: | |
2107 | return 0; | |
2108 | } | |
2109 | break; | |
2110 | default: | |
2111 | return 0; | |
2112 | } | |
2113 | ||
0980a60f | 2114 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a CML |
2115 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
2116 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); | |
2117 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), | |
e2fa6fba | 2118 | uniqtranscale_reg_value); |
ab3c759a CML |
2119 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
2120 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
2121 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); | |
2122 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); | |
0980a60f | 2123 | mutex_unlock(&dev_priv->dpio_lock); |
e2fa6fba P |
2124 | |
2125 | return 0; | |
2126 | } | |
2127 | ||
a4fc5ed6 | 2128 | static void |
0301b3ac JN |
2129 | intel_get_adjust_train(struct intel_dp *intel_dp, |
2130 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) | |
a4fc5ed6 KP |
2131 | { |
2132 | uint8_t v = 0; | |
2133 | uint8_t p = 0; | |
2134 | int lane; | |
1a2eb460 KP |
2135 | uint8_t voltage_max; |
2136 | uint8_t preemph_max; | |
a4fc5ed6 | 2137 | |
33a34e4e | 2138 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
0f037bde DV |
2139 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
2140 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); | |
a4fc5ed6 KP |
2141 | |
2142 | if (this_v > v) | |
2143 | v = this_v; | |
2144 | if (this_p > p) | |
2145 | p = this_p; | |
2146 | } | |
2147 | ||
1a2eb460 | 2148 | voltage_max = intel_dp_voltage_max(intel_dp); |
417e822d KP |
2149 | if (v >= voltage_max) |
2150 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; | |
a4fc5ed6 | 2151 | |
1a2eb460 KP |
2152 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
2153 | if (p >= preemph_max) | |
2154 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
a4fc5ed6 KP |
2155 | |
2156 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 2157 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
2158 | } |
2159 | ||
2160 | static uint32_t | |
f0a3424e | 2161 | intel_gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 2162 | { |
3cf2efb1 | 2163 | uint32_t signal_levels = 0; |
a4fc5ed6 | 2164 | |
3cf2efb1 | 2165 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
2166 | case DP_TRAIN_VOLTAGE_SWING_400: |
2167 | default: | |
2168 | signal_levels |= DP_VOLTAGE_0_4; | |
2169 | break; | |
2170 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2171 | signal_levels |= DP_VOLTAGE_0_6; | |
2172 | break; | |
2173 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2174 | signal_levels |= DP_VOLTAGE_0_8; | |
2175 | break; | |
2176 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2177 | signal_levels |= DP_VOLTAGE_1_2; | |
2178 | break; | |
2179 | } | |
3cf2efb1 | 2180 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
2181 | case DP_TRAIN_PRE_EMPHASIS_0: |
2182 | default: | |
2183 | signal_levels |= DP_PRE_EMPHASIS_0; | |
2184 | break; | |
2185 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
2186 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
2187 | break; | |
2188 | case DP_TRAIN_PRE_EMPHASIS_6: | |
2189 | signal_levels |= DP_PRE_EMPHASIS_6; | |
2190 | break; | |
2191 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
2192 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
2193 | break; | |
2194 | } | |
2195 | return signal_levels; | |
2196 | } | |
2197 | ||
e3421a18 ZW |
2198 | /* Gen6's DP voltage swing and pre-emphasis control */ |
2199 | static uint32_t | |
2200 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
2201 | { | |
3c5a62b5 YL |
2202 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2203 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2204 | switch (signal_levels) { | |
e3421a18 | 2205 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
2206 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2207 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
2208 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2209 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 2210 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
2211 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
2212 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 2213 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
2214 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2215 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 2216 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
2217 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
2218 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 2219 | default: |
3c5a62b5 YL |
2220 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
2221 | "0x%x\n", signal_levels); | |
2222 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
2223 | } |
2224 | } | |
2225 | ||
1a2eb460 KP |
2226 | /* Gen7's DP voltage swing and pre-emphasis control */ |
2227 | static uint32_t | |
2228 | intel_gen7_edp_signal_levels(uint8_t train_set) | |
2229 | { | |
2230 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
2231 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2232 | switch (signal_levels) { | |
2233 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
2234 | return EDP_LINK_TRAIN_400MV_0DB_IVB; | |
2235 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2236 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; | |
2237 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
2238 | return EDP_LINK_TRAIN_400MV_6DB_IVB; | |
2239 | ||
2240 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: | |
2241 | return EDP_LINK_TRAIN_600MV_0DB_IVB; | |
2242 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2243 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; | |
2244 | ||
2245 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | |
2246 | return EDP_LINK_TRAIN_800MV_0DB_IVB; | |
2247 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2248 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; | |
2249 | ||
2250 | default: | |
2251 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
2252 | "0x%x\n", signal_levels); | |
2253 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
2254 | } | |
2255 | } | |
2256 | ||
d6c0d722 PZ |
2257 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
2258 | static uint32_t | |
f0a3424e | 2259 | intel_hsw_signal_levels(uint8_t train_set) |
a4fc5ed6 | 2260 | { |
d6c0d722 PZ |
2261 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2262 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2263 | switch (signal_levels) { | |
2264 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
2265 | return DDI_BUF_EMP_400MV_0DB_HSW; | |
2266 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2267 | return DDI_BUF_EMP_400MV_3_5DB_HSW; | |
2268 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
2269 | return DDI_BUF_EMP_400MV_6DB_HSW; | |
2270 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: | |
2271 | return DDI_BUF_EMP_400MV_9_5DB_HSW; | |
a4fc5ed6 | 2272 | |
d6c0d722 PZ |
2273 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2274 | return DDI_BUF_EMP_600MV_0DB_HSW; | |
2275 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2276 | return DDI_BUF_EMP_600MV_3_5DB_HSW; | |
2277 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: | |
2278 | return DDI_BUF_EMP_600MV_6DB_HSW; | |
a4fc5ed6 | 2279 | |
d6c0d722 PZ |
2280 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
2281 | return DDI_BUF_EMP_800MV_0DB_HSW; | |
2282 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2283 | return DDI_BUF_EMP_800MV_3_5DB_HSW; | |
2284 | default: | |
2285 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
2286 | "0x%x\n", signal_levels); | |
2287 | return DDI_BUF_EMP_400MV_0DB_HSW; | |
a4fc5ed6 | 2288 | } |
a4fc5ed6 KP |
2289 | } |
2290 | ||
8f93f4f1 PZ |
2291 | static uint32_t |
2292 | intel_bdw_signal_levels(uint8_t train_set) | |
2293 | { | |
2294 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
2295 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2296 | switch (signal_levels) { | |
2297 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
2298 | return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ | |
2299 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2300 | return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */ | |
2301 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
2302 | return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */ | |
2303 | ||
2304 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: | |
2305 | return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */ | |
2306 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2307 | return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */ | |
2308 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: | |
2309 | return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */ | |
2310 | ||
2311 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | |
2312 | return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */ | |
2313 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2314 | return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */ | |
2315 | ||
2316 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: | |
2317 | return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */ | |
2318 | ||
2319 | default: | |
2320 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
2321 | "0x%x\n", signal_levels); | |
2322 | return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ | |
2323 | } | |
2324 | } | |
2325 | ||
f0a3424e PZ |
2326 | /* Properly updates "DP" with the correct signal levels. */ |
2327 | static void | |
2328 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) | |
2329 | { | |
2330 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 2331 | enum port port = intel_dig_port->port; |
f0a3424e PZ |
2332 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2333 | uint32_t signal_levels, mask; | |
2334 | uint8_t train_set = intel_dp->train_set[0]; | |
2335 | ||
8f93f4f1 PZ |
2336 | if (IS_BROADWELL(dev)) { |
2337 | signal_levels = intel_bdw_signal_levels(train_set); | |
2338 | mask = DDI_BUF_EMP_MASK; | |
2339 | } else if (IS_HASWELL(dev)) { | |
f0a3424e PZ |
2340 | signal_levels = intel_hsw_signal_levels(train_set); |
2341 | mask = DDI_BUF_EMP_MASK; | |
e2fa6fba P |
2342 | } else if (IS_VALLEYVIEW(dev)) { |
2343 | signal_levels = intel_vlv_signal_levels(intel_dp); | |
2344 | mask = 0; | |
bc7d38a4 | 2345 | } else if (IS_GEN7(dev) && port == PORT_A) { |
f0a3424e PZ |
2346 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
2347 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; | |
bc7d38a4 | 2348 | } else if (IS_GEN6(dev) && port == PORT_A) { |
f0a3424e PZ |
2349 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
2350 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; | |
2351 | } else { | |
2352 | signal_levels = intel_gen4_signal_levels(train_set); | |
2353 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; | |
2354 | } | |
2355 | ||
2356 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
2357 | ||
2358 | *DP = (*DP & ~mask) | signal_levels; | |
2359 | } | |
2360 | ||
a4fc5ed6 | 2361 | static bool |
ea5b213a | 2362 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
70aff66c | 2363 | uint32_t *DP, |
58e10eb9 | 2364 | uint8_t dp_train_pat) |
a4fc5ed6 | 2365 | { |
174edf1f PZ |
2366 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2367 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
a4fc5ed6 | 2368 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 2369 | enum port port = intel_dig_port->port; |
2cdfe6c8 JN |
2370 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
2371 | int ret, len; | |
a4fc5ed6 | 2372 | |
22b8bf17 | 2373 | if (HAS_DDI(dev)) { |
3ab9c637 | 2374 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
d6c0d722 PZ |
2375 | |
2376 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2377 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2378 | else | |
2379 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2380 | ||
2381 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2382 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2383 | case DP_TRAINING_PATTERN_DISABLE: | |
d6c0d722 PZ |
2384 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
2385 | ||
2386 | break; | |
2387 | case DP_TRAINING_PATTERN_1: | |
2388 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2389 | break; | |
2390 | case DP_TRAINING_PATTERN_2: | |
2391 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2392 | break; | |
2393 | case DP_TRAINING_PATTERN_3: | |
2394 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2395 | break; | |
2396 | } | |
174edf1f | 2397 | I915_WRITE(DP_TP_CTL(port), temp); |
d6c0d722 | 2398 | |
bc7d38a4 | 2399 | } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
70aff66c | 2400 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
47ea7542 PZ |
2401 | |
2402 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2403 | case DP_TRAINING_PATTERN_DISABLE: | |
70aff66c | 2404 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
47ea7542 PZ |
2405 | break; |
2406 | case DP_TRAINING_PATTERN_1: | |
70aff66c | 2407 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
47ea7542 PZ |
2408 | break; |
2409 | case DP_TRAINING_PATTERN_2: | |
70aff66c | 2410 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
47ea7542 PZ |
2411 | break; |
2412 | case DP_TRAINING_PATTERN_3: | |
2413 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
70aff66c | 2414 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
47ea7542 PZ |
2415 | break; |
2416 | } | |
2417 | ||
2418 | } else { | |
70aff66c | 2419 | *DP &= ~DP_LINK_TRAIN_MASK; |
47ea7542 PZ |
2420 | |
2421 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2422 | case DP_TRAINING_PATTERN_DISABLE: | |
70aff66c | 2423 | *DP |= DP_LINK_TRAIN_OFF; |
47ea7542 PZ |
2424 | break; |
2425 | case DP_TRAINING_PATTERN_1: | |
70aff66c | 2426 | *DP |= DP_LINK_TRAIN_PAT_1; |
47ea7542 PZ |
2427 | break; |
2428 | case DP_TRAINING_PATTERN_2: | |
70aff66c | 2429 | *DP |= DP_LINK_TRAIN_PAT_2; |
47ea7542 PZ |
2430 | break; |
2431 | case DP_TRAINING_PATTERN_3: | |
2432 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
70aff66c | 2433 | *DP |= DP_LINK_TRAIN_PAT_2; |
47ea7542 PZ |
2434 | break; |
2435 | } | |
2436 | } | |
2437 | ||
70aff66c | 2438 | I915_WRITE(intel_dp->output_reg, *DP); |
ea5b213a | 2439 | POSTING_READ(intel_dp->output_reg); |
a4fc5ed6 | 2440 | |
2cdfe6c8 JN |
2441 | buf[0] = dp_train_pat; |
2442 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == | |
47ea7542 | 2443 | DP_TRAINING_PATTERN_DISABLE) { |
2cdfe6c8 JN |
2444 | /* don't write DP_TRAINING_LANEx_SET on disable */ |
2445 | len = 1; | |
2446 | } else { | |
2447 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ | |
2448 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); | |
2449 | len = intel_dp->lane_count + 1; | |
47ea7542 | 2450 | } |
a4fc5ed6 | 2451 | |
9d1a1031 JN |
2452 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, |
2453 | buf, len); | |
2cdfe6c8 JN |
2454 | |
2455 | return ret == len; | |
a4fc5ed6 KP |
2456 | } |
2457 | ||
70aff66c JN |
2458 | static bool |
2459 | intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, | |
2460 | uint8_t dp_train_pat) | |
2461 | { | |
953d22e8 | 2462 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); |
70aff66c JN |
2463 | intel_dp_set_signal_levels(intel_dp, DP); |
2464 | return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); | |
2465 | } | |
2466 | ||
2467 | static bool | |
2468 | intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, | |
0301b3ac | 2469 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
70aff66c JN |
2470 | { |
2471 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2472 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2474 | int ret; | |
2475 | ||
2476 | intel_get_adjust_train(intel_dp, link_status); | |
2477 | intel_dp_set_signal_levels(intel_dp, DP); | |
2478 | ||
2479 | I915_WRITE(intel_dp->output_reg, *DP); | |
2480 | POSTING_READ(intel_dp->output_reg); | |
2481 | ||
9d1a1031 JN |
2482 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, |
2483 | intel_dp->train_set, intel_dp->lane_count); | |
70aff66c JN |
2484 | |
2485 | return ret == intel_dp->lane_count; | |
2486 | } | |
2487 | ||
3ab9c637 ID |
2488 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
2489 | { | |
2490 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2491 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2493 | enum port port = intel_dig_port->port; | |
2494 | uint32_t val; | |
2495 | ||
2496 | if (!HAS_DDI(dev)) | |
2497 | return; | |
2498 | ||
2499 | val = I915_READ(DP_TP_CTL(port)); | |
2500 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2501 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
2502 | I915_WRITE(DP_TP_CTL(port), val); | |
2503 | ||
2504 | /* | |
2505 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
2506 | * we need to set idle transmission mode is to work around a HW issue | |
2507 | * where we enable the pipe while not in idle link-training mode. | |
2508 | * In this case there is requirement to wait for a minimum number of | |
2509 | * idle patterns to be sent. | |
2510 | */ | |
2511 | if (port == PORT_A) | |
2512 | return; | |
2513 | ||
2514 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), | |
2515 | 1)) | |
2516 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); | |
2517 | } | |
2518 | ||
33a34e4e | 2519 | /* Enable corresponding port and start training pattern 1 */ |
c19b0669 | 2520 | void |
33a34e4e | 2521 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 2522 | { |
da63a9f2 | 2523 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
c19b0669 | 2524 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 KP |
2525 | int i; |
2526 | uint8_t voltage; | |
cdb0e95b | 2527 | int voltage_tries, loop_tries; |
ea5b213a | 2528 | uint32_t DP = intel_dp->DP; |
6aba5b6c | 2529 | uint8_t link_config[2]; |
a4fc5ed6 | 2530 | |
affa9354 | 2531 | if (HAS_DDI(dev)) |
c19b0669 PZ |
2532 | intel_ddi_prepare_link_retrain(encoder); |
2533 | ||
3cf2efb1 | 2534 | /* Write the link configuration data */ |
6aba5b6c JN |
2535 | link_config[0] = intel_dp->link_bw; |
2536 | link_config[1] = intel_dp->lane_count; | |
2537 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
2538 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; | |
9d1a1031 | 2539 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); |
6aba5b6c JN |
2540 | |
2541 | link_config[0] = 0; | |
2542 | link_config[1] = DP_SET_ANSI_8B10B; | |
9d1a1031 | 2543 | drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); |
a4fc5ed6 KP |
2544 | |
2545 | DP |= DP_PORT_EN; | |
1a2eb460 | 2546 | |
70aff66c JN |
2547 | /* clock recovery */ |
2548 | if (!intel_dp_reset_link_train(intel_dp, &DP, | |
2549 | DP_TRAINING_PATTERN_1 | | |
2550 | DP_LINK_SCRAMBLING_DISABLE)) { | |
2551 | DRM_ERROR("failed to enable link training\n"); | |
2552 | return; | |
2553 | } | |
2554 | ||
a4fc5ed6 | 2555 | voltage = 0xff; |
cdb0e95b KP |
2556 | voltage_tries = 0; |
2557 | loop_tries = 0; | |
a4fc5ed6 | 2558 | for (;;) { |
70aff66c | 2559 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
a4fc5ed6 | 2560 | |
a7c9655f | 2561 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
93f62dad KP |
2562 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2563 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 2564 | break; |
93f62dad | 2565 | } |
a4fc5ed6 | 2566 | |
01916270 | 2567 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
93f62dad | 2568 | DRM_DEBUG_KMS("clock recovery OK\n"); |
3cf2efb1 CW |
2569 | break; |
2570 | } | |
2571 | ||
2572 | /* Check to see if we've tried the max voltage */ | |
2573 | for (i = 0; i < intel_dp->lane_count; i++) | |
2574 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 2575 | break; |
3b4f819d | 2576 | if (i == intel_dp->lane_count) { |
b06fbda3 DV |
2577 | ++loop_tries; |
2578 | if (loop_tries == 5) { | |
3def84b3 | 2579 | DRM_ERROR("too many full retries, give up\n"); |
cdb0e95b KP |
2580 | break; |
2581 | } | |
70aff66c JN |
2582 | intel_dp_reset_link_train(intel_dp, &DP, |
2583 | DP_TRAINING_PATTERN_1 | | |
2584 | DP_LINK_SCRAMBLING_DISABLE); | |
cdb0e95b KP |
2585 | voltage_tries = 0; |
2586 | continue; | |
2587 | } | |
a4fc5ed6 | 2588 | |
3cf2efb1 | 2589 | /* Check to see if we've tried the same voltage 5 times */ |
b06fbda3 | 2590 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
24773670 | 2591 | ++voltage_tries; |
b06fbda3 | 2592 | if (voltage_tries == 5) { |
3def84b3 | 2593 | DRM_ERROR("too many voltage retries, give up\n"); |
b06fbda3 DV |
2594 | break; |
2595 | } | |
2596 | } else | |
2597 | voltage_tries = 0; | |
2598 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 2599 | |
70aff66c JN |
2600 | /* Update training set as requested by target */ |
2601 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { | |
2602 | DRM_ERROR("failed to update link training\n"); | |
2603 | break; | |
2604 | } | |
a4fc5ed6 KP |
2605 | } |
2606 | ||
33a34e4e JB |
2607 | intel_dp->DP = DP; |
2608 | } | |
2609 | ||
c19b0669 | 2610 | void |
33a34e4e JB |
2611 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
2612 | { | |
33a34e4e | 2613 | bool channel_eq = false; |
37f80975 | 2614 | int tries, cr_tries; |
33a34e4e | 2615 | uint32_t DP = intel_dp->DP; |
06ea66b6 TP |
2616 | uint32_t training_pattern = DP_TRAINING_PATTERN_2; |
2617 | ||
2618 | /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ | |
2619 | if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) | |
2620 | training_pattern = DP_TRAINING_PATTERN_3; | |
33a34e4e | 2621 | |
a4fc5ed6 | 2622 | /* channel equalization */ |
70aff66c | 2623 | if (!intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 2624 | training_pattern | |
70aff66c JN |
2625 | DP_LINK_SCRAMBLING_DISABLE)) { |
2626 | DRM_ERROR("failed to start channel equalization\n"); | |
2627 | return; | |
2628 | } | |
2629 | ||
a4fc5ed6 | 2630 | tries = 0; |
37f80975 | 2631 | cr_tries = 0; |
a4fc5ed6 KP |
2632 | channel_eq = false; |
2633 | for (;;) { | |
70aff66c | 2634 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
e3421a18 | 2635 | |
37f80975 JB |
2636 | if (cr_tries > 5) { |
2637 | DRM_ERROR("failed to train DP, aborting\n"); | |
37f80975 JB |
2638 | break; |
2639 | } | |
2640 | ||
a7c9655f | 2641 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
70aff66c JN |
2642 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2643 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 2644 | break; |
70aff66c | 2645 | } |
a4fc5ed6 | 2646 | |
37f80975 | 2647 | /* Make sure clock is still ok */ |
01916270 | 2648 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
37f80975 | 2649 | intel_dp_start_link_train(intel_dp); |
70aff66c | 2650 | intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 2651 | training_pattern | |
70aff66c | 2652 | DP_LINK_SCRAMBLING_DISABLE); |
37f80975 JB |
2653 | cr_tries++; |
2654 | continue; | |
2655 | } | |
2656 | ||
1ffdff13 | 2657 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
3cf2efb1 CW |
2658 | channel_eq = true; |
2659 | break; | |
2660 | } | |
a4fc5ed6 | 2661 | |
37f80975 JB |
2662 | /* Try 5 times, then try clock recovery if that fails */ |
2663 | if (tries > 5) { | |
2664 | intel_dp_link_down(intel_dp); | |
2665 | intel_dp_start_link_train(intel_dp); | |
70aff66c | 2666 | intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 2667 | training_pattern | |
70aff66c | 2668 | DP_LINK_SCRAMBLING_DISABLE); |
37f80975 JB |
2669 | tries = 0; |
2670 | cr_tries++; | |
2671 | continue; | |
2672 | } | |
a4fc5ed6 | 2673 | |
70aff66c JN |
2674 | /* Update training set as requested by target */ |
2675 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { | |
2676 | DRM_ERROR("failed to update link training\n"); | |
2677 | break; | |
2678 | } | |
3cf2efb1 | 2679 | ++tries; |
869184a6 | 2680 | } |
3cf2efb1 | 2681 | |
3ab9c637 ID |
2682 | intel_dp_set_idle_link_train(intel_dp); |
2683 | ||
2684 | intel_dp->DP = DP; | |
2685 | ||
d6c0d722 | 2686 | if (channel_eq) |
07f42258 | 2687 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
d6c0d722 | 2688 | |
3ab9c637 ID |
2689 | } |
2690 | ||
2691 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) | |
2692 | { | |
70aff66c | 2693 | intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
3ab9c637 | 2694 | DP_TRAINING_PATTERN_DISABLE); |
a4fc5ed6 KP |
2695 | } |
2696 | ||
2697 | static void | |
ea5b213a | 2698 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 2699 | { |
da63a9f2 | 2700 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
bc7d38a4 | 2701 | enum port port = intel_dig_port->port; |
da63a9f2 | 2702 | struct drm_device *dev = intel_dig_port->base.base.dev; |
a4fc5ed6 | 2703 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab527efc DV |
2704 | struct intel_crtc *intel_crtc = |
2705 | to_intel_crtc(intel_dig_port->base.base.crtc); | |
ea5b213a | 2706 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 2707 | |
c19b0669 PZ |
2708 | /* |
2709 | * DDI code has a strict mode set sequence and we should try to respect | |
2710 | * it, otherwise we might hang the machine in many different ways. So we | |
2711 | * really should be disabling the port only on a complete crtc_disable | |
2712 | * sequence. This function is just called under two conditions on DDI | |
2713 | * code: | |
2714 | * - Link train failed while doing crtc_enable, and on this case we | |
2715 | * really should respect the mode set sequence and wait for a | |
2716 | * crtc_disable. | |
2717 | * - Someone turned the monitor off and intel_dp_check_link_status | |
2718 | * called us. We don't need to disable the whole port on this case, so | |
2719 | * when someone turns the monitor on again, | |
2720 | * intel_ddi_prepare_link_retrain will take care of redoing the link | |
2721 | * train. | |
2722 | */ | |
affa9354 | 2723 | if (HAS_DDI(dev)) |
c19b0669 PZ |
2724 | return; |
2725 | ||
0c33d8d7 | 2726 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
2727 | return; |
2728 | ||
28c97730 | 2729 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 2730 | |
bc7d38a4 | 2731 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
e3421a18 | 2732 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 2733 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
2734 | } else { |
2735 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 2736 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 2737 | } |
fe255d00 | 2738 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 2739 | |
ab527efc DV |
2740 | /* We don't really know why we're doing this */ |
2741 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
5eb08b69 | 2742 | |
493a7081 | 2743 | if (HAS_PCH_IBX(dev) && |
1b39d6f3 | 2744 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
da63a9f2 | 2745 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
31acbcc4 | 2746 | |
5bddd17f EA |
2747 | /* Hardware workaround: leaving our transcoder select |
2748 | * set to transcoder B while it's off will prevent the | |
2749 | * corresponding HDMI output on transcoder A. | |
2750 | * | |
2751 | * Combine this with another hardware workaround: | |
2752 | * transcoder select bit can only be cleared while the | |
2753 | * port is enabled. | |
2754 | */ | |
2755 | DP &= ~DP_PIPEB_SELECT; | |
2756 | I915_WRITE(intel_dp->output_reg, DP); | |
2757 | ||
2758 | /* Changes to enable or select take place the vblank | |
2759 | * after being written. | |
2760 | */ | |
ff50afe9 DV |
2761 | if (WARN_ON(crtc == NULL)) { |
2762 | /* We should never try to disable a port without a crtc | |
2763 | * attached. For paranoia keep the code around for a | |
2764 | * bit. */ | |
31acbcc4 CW |
2765 | POSTING_READ(intel_dp->output_reg); |
2766 | msleep(50); | |
2767 | } else | |
ab527efc | 2768 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
5bddd17f EA |
2769 | } |
2770 | ||
832afda6 | 2771 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
ea5b213a CW |
2772 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
2773 | POSTING_READ(intel_dp->output_reg); | |
f01eca2e | 2774 | msleep(intel_dp->panel_power_down_delay); |
a4fc5ed6 KP |
2775 | } |
2776 | ||
26d61aad KP |
2777 | static bool |
2778 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 2779 | { |
a031d709 RV |
2780 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
2781 | struct drm_device *dev = dig_port->base.base.dev; | |
2782 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2783 | ||
577c7a50 DL |
2784 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
2785 | ||
9d1a1031 JN |
2786 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
2787 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 2788 | return false; /* aux transfer failed */ |
92fd8fd1 | 2789 | |
577c7a50 DL |
2790 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
2791 | 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); | |
2792 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); | |
2793 | ||
edb39244 AJ |
2794 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
2795 | return false; /* DPCD not present */ | |
2796 | ||
2293bb5c SK |
2797 | /* Check if the panel supports PSR */ |
2798 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); | |
50003939 | 2799 | if (is_edp(intel_dp)) { |
9d1a1031 JN |
2800 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
2801 | intel_dp->psr_dpcd, | |
2802 | sizeof(intel_dp->psr_dpcd)); | |
a031d709 RV |
2803 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
2804 | dev_priv->psr.sink_support = true; | |
50003939 | 2805 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
a031d709 | 2806 | } |
50003939 JN |
2807 | } |
2808 | ||
06ea66b6 TP |
2809 | /* Training Pattern 3 support */ |
2810 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && | |
2811 | intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { | |
2812 | intel_dp->use_tps3 = true; | |
2813 | DRM_DEBUG_KMS("Displayport TPS3 supported"); | |
2814 | } else | |
2815 | intel_dp->use_tps3 = false; | |
2816 | ||
edb39244 AJ |
2817 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
2818 | DP_DWN_STRM_PORT_PRESENT)) | |
2819 | return true; /* native DP sink */ | |
2820 | ||
2821 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
2822 | return true; /* no per-port downstream info */ | |
2823 | ||
9d1a1031 JN |
2824 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
2825 | intel_dp->downstream_ports, | |
2826 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
2827 | return false; /* downstream port status fetch failed */ |
2828 | ||
2829 | return true; | |
92fd8fd1 KP |
2830 | } |
2831 | ||
0d198328 AJ |
2832 | static void |
2833 | intel_dp_probe_oui(struct intel_dp *intel_dp) | |
2834 | { | |
2835 | u8 buf[3]; | |
2836 | ||
2837 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
2838 | return; | |
2839 | ||
24f3e092 | 2840 | intel_edp_panel_vdd_on(intel_dp); |
351cfc34 | 2841 | |
9d1a1031 | 2842 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
0d198328 AJ |
2843 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
2844 | buf[0], buf[1], buf[2]); | |
2845 | ||
9d1a1031 | 2846 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
0d198328 AJ |
2847 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
2848 | buf[0], buf[1], buf[2]); | |
351cfc34 | 2849 | |
4be73780 | 2850 | edp_panel_vdd_off(intel_dp, false); |
0d198328 AJ |
2851 | } |
2852 | ||
d2e216d0 RV |
2853 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
2854 | { | |
2855 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2856 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2857 | struct intel_crtc *intel_crtc = | |
2858 | to_intel_crtc(intel_dig_port->base.base.crtc); | |
2859 | u8 buf[1]; | |
2860 | ||
9d1a1031 | 2861 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0) |
d2e216d0 RV |
2862 | return -EAGAIN; |
2863 | ||
2864 | if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) | |
2865 | return -ENOTTY; | |
2866 | ||
9d1a1031 JN |
2867 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
2868 | DP_TEST_SINK_START) < 0) | |
d2e216d0 RV |
2869 | return -EAGAIN; |
2870 | ||
2871 | /* Wait 2 vblanks to be sure we will have the correct CRC value */ | |
2872 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
2873 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
2874 | ||
9d1a1031 | 2875 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) |
d2e216d0 RV |
2876 | return -EAGAIN; |
2877 | ||
9d1a1031 | 2878 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0); |
d2e216d0 RV |
2879 | return 0; |
2880 | } | |
2881 | ||
a60f0e38 JB |
2882 | static bool |
2883 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
2884 | { | |
9d1a1031 JN |
2885 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
2886 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
2887 | sink_irq_vector, 1) == 1; | |
a60f0e38 JB |
2888 | } |
2889 | ||
2890 | static void | |
2891 | intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
2892 | { | |
2893 | /* NAK by default */ | |
9d1a1031 | 2894 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); |
a60f0e38 JB |
2895 | } |
2896 | ||
a4fc5ed6 KP |
2897 | /* |
2898 | * According to DP spec | |
2899 | * 5.1.2: | |
2900 | * 1. Read DPCD | |
2901 | * 2. Configure link according to Receiver Capabilities | |
2902 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
2903 | * 4. Check link status on receipt of hot-plug interrupt | |
2904 | */ | |
2905 | ||
00c09d70 | 2906 | void |
ea5b213a | 2907 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 2908 | { |
da63a9f2 | 2909 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
a60f0e38 | 2910 | u8 sink_irq_vector; |
93f62dad | 2911 | u8 link_status[DP_LINK_STATUS_SIZE]; |
a60f0e38 | 2912 | |
da63a9f2 | 2913 | if (!intel_encoder->connectors_active) |
d2b996ac | 2914 | return; |
59cd09e1 | 2915 | |
da63a9f2 | 2916 | if (WARN_ON(!intel_encoder->base.crtc)) |
a4fc5ed6 KP |
2917 | return; |
2918 | ||
92fd8fd1 | 2919 | /* Try to read receiver status if the link appears to be up */ |
93f62dad | 2920 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
a4fc5ed6 KP |
2921 | return; |
2922 | } | |
2923 | ||
92fd8fd1 | 2924 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 2925 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
2926 | return; |
2927 | } | |
2928 | ||
a60f0e38 JB |
2929 | /* Try to read the source of the interrupt */ |
2930 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
2931 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
2932 | /* Clear interrupt source */ | |
9d1a1031 JN |
2933 | drm_dp_dpcd_writeb(&intel_dp->aux, |
2934 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
2935 | sink_irq_vector); | |
a60f0e38 JB |
2936 | |
2937 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
2938 | intel_dp_handle_test_request(intel_dp); | |
2939 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
2940 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
2941 | } | |
2942 | ||
1ffdff13 | 2943 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
92fd8fd1 | 2944 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
da63a9f2 | 2945 | drm_get_encoder_name(&intel_encoder->base)); |
33a34e4e JB |
2946 | intel_dp_start_link_train(intel_dp); |
2947 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 | 2948 | intel_dp_stop_link_train(intel_dp); |
33a34e4e | 2949 | } |
a4fc5ed6 | 2950 | } |
a4fc5ed6 | 2951 | |
caf9ab24 | 2952 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 2953 | static enum drm_connector_status |
26d61aad | 2954 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 2955 | { |
caf9ab24 | 2956 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
2957 | uint8_t type; |
2958 | ||
2959 | if (!intel_dp_get_dpcd(intel_dp)) | |
2960 | return connector_status_disconnected; | |
2961 | ||
2962 | /* if there's no downstream port, we're done */ | |
2963 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) | |
26d61aad | 2964 | return connector_status_connected; |
caf9ab24 AJ |
2965 | |
2966 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
2967 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
2968 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
23235177 | 2969 | uint8_t reg; |
9d1a1031 JN |
2970 | |
2971 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, | |
2972 | ®, 1) < 0) | |
caf9ab24 | 2973 | return connector_status_unknown; |
9d1a1031 | 2974 | |
23235177 AJ |
2975 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
2976 | : connector_status_disconnected; | |
caf9ab24 AJ |
2977 | } |
2978 | ||
2979 | /* If no HPD, poke DDC gently */ | |
0b99836f | 2980 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 2981 | return connector_status_connected; |
caf9ab24 AJ |
2982 | |
2983 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
2984 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
2985 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
2986 | if (type == DP_DS_PORT_TYPE_VGA || | |
2987 | type == DP_DS_PORT_TYPE_NON_EDID) | |
2988 | return connector_status_unknown; | |
2989 | } else { | |
2990 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
2991 | DP_DWN_STRM_PORT_TYPE_MASK; | |
2992 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
2993 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
2994 | return connector_status_unknown; | |
2995 | } | |
caf9ab24 AJ |
2996 | |
2997 | /* Anything else is out of spec, warn and ignore */ | |
2998 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 2999 | return connector_status_disconnected; |
71ba9000 AJ |
3000 | } |
3001 | ||
5eb08b69 | 3002 | static enum drm_connector_status |
a9756bb5 | 3003 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 3004 | { |
30add22d | 3005 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1b469639 DL |
3006 | struct drm_i915_private *dev_priv = dev->dev_private; |
3007 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
5eb08b69 ZW |
3008 | enum drm_connector_status status; |
3009 | ||
fe16d949 CW |
3010 | /* Can't disconnect eDP, but you can close the lid... */ |
3011 | if (is_edp(intel_dp)) { | |
30add22d | 3012 | status = intel_panel_detect(dev); |
fe16d949 CW |
3013 | if (status == connector_status_unknown) |
3014 | status = connector_status_connected; | |
3015 | return status; | |
3016 | } | |
01cb9ea6 | 3017 | |
1b469639 DL |
3018 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
3019 | return connector_status_disconnected; | |
3020 | ||
26d61aad | 3021 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
3022 | } |
3023 | ||
a4fc5ed6 | 3024 | static enum drm_connector_status |
a9756bb5 | 3025 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 3026 | { |
30add22d | 3027 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
a4fc5ed6 | 3028 | struct drm_i915_private *dev_priv = dev->dev_private; |
34f2be46 | 3029 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
10f76a38 | 3030 | uint32_t bit; |
5eb08b69 | 3031 | |
35aad75f JB |
3032 | /* Can't disconnect eDP, but you can close the lid... */ |
3033 | if (is_edp(intel_dp)) { | |
3034 | enum drm_connector_status status; | |
3035 | ||
3036 | status = intel_panel_detect(dev); | |
3037 | if (status == connector_status_unknown) | |
3038 | status = connector_status_connected; | |
3039 | return status; | |
3040 | } | |
3041 | ||
232a6ee9 TP |
3042 | if (IS_VALLEYVIEW(dev)) { |
3043 | switch (intel_dig_port->port) { | |
3044 | case PORT_B: | |
3045 | bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; | |
3046 | break; | |
3047 | case PORT_C: | |
3048 | bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; | |
3049 | break; | |
3050 | case PORT_D: | |
3051 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; | |
3052 | break; | |
3053 | default: | |
3054 | return connector_status_unknown; | |
3055 | } | |
3056 | } else { | |
3057 | switch (intel_dig_port->port) { | |
3058 | case PORT_B: | |
3059 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; | |
3060 | break; | |
3061 | case PORT_C: | |
3062 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; | |
3063 | break; | |
3064 | case PORT_D: | |
3065 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | |
3066 | break; | |
3067 | default: | |
3068 | return connector_status_unknown; | |
3069 | } | |
a4fc5ed6 KP |
3070 | } |
3071 | ||
10f76a38 | 3072 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
a4fc5ed6 KP |
3073 | return connector_status_disconnected; |
3074 | ||
26d61aad | 3075 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
3076 | } |
3077 | ||
8c241fef KP |
3078 | static struct edid * |
3079 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
3080 | { | |
9cd300e0 | 3081 | struct intel_connector *intel_connector = to_intel_connector(connector); |
d6f24d0f | 3082 | |
9cd300e0 JN |
3083 | /* use cached edid if we have one */ |
3084 | if (intel_connector->edid) { | |
9cd300e0 JN |
3085 | /* invalid edid */ |
3086 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
3087 | return NULL; |
3088 | ||
55e9edeb | 3089 | return drm_edid_duplicate(intel_connector->edid); |
d6f24d0f | 3090 | } |
8c241fef | 3091 | |
9cd300e0 | 3092 | return drm_get_edid(connector, adapter); |
8c241fef KP |
3093 | } |
3094 | ||
3095 | static int | |
3096 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) | |
3097 | { | |
9cd300e0 | 3098 | struct intel_connector *intel_connector = to_intel_connector(connector); |
8c241fef | 3099 | |
9cd300e0 JN |
3100 | /* use cached edid if we have one */ |
3101 | if (intel_connector->edid) { | |
3102 | /* invalid edid */ | |
3103 | if (IS_ERR(intel_connector->edid)) | |
3104 | return 0; | |
3105 | ||
3106 | return intel_connector_update_modes(connector, | |
3107 | intel_connector->edid); | |
d6f24d0f JB |
3108 | } |
3109 | ||
9cd300e0 | 3110 | return intel_ddc_get_modes(connector, adapter); |
8c241fef KP |
3111 | } |
3112 | ||
a9756bb5 ZW |
3113 | static enum drm_connector_status |
3114 | intel_dp_detect(struct drm_connector *connector, bool force) | |
3115 | { | |
3116 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
d63885da PZ |
3117 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3118 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 3119 | struct drm_device *dev = connector->dev; |
c8c8fb33 | 3120 | struct drm_i915_private *dev_priv = dev->dev_private; |
a9756bb5 | 3121 | enum drm_connector_status status; |
671dedd2 | 3122 | enum intel_display_power_domain power_domain; |
a9756bb5 ZW |
3123 | struct edid *edid = NULL; |
3124 | ||
c8c8fb33 PZ |
3125 | intel_runtime_pm_get(dev_priv); |
3126 | ||
671dedd2 ID |
3127 | power_domain = intel_display_port_power_domain(intel_encoder); |
3128 | intel_display_power_get(dev_priv, power_domain); | |
3129 | ||
164c8598 CW |
3130 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
3131 | connector->base.id, drm_get_connector_name(connector)); | |
3132 | ||
a9756bb5 ZW |
3133 | intel_dp->has_audio = false; |
3134 | ||
3135 | if (HAS_PCH_SPLIT(dev)) | |
3136 | status = ironlake_dp_detect(intel_dp); | |
3137 | else | |
3138 | status = g4x_dp_detect(intel_dp); | |
1b9be9d0 | 3139 | |
a9756bb5 | 3140 | if (status != connector_status_connected) |
c8c8fb33 | 3141 | goto out; |
a9756bb5 | 3142 | |
0d198328 AJ |
3143 | intel_dp_probe_oui(intel_dp); |
3144 | ||
c3e5f67b DV |
3145 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
3146 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); | |
f684960e | 3147 | } else { |
0b99836f | 3148 | edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); |
f684960e CW |
3149 | if (edid) { |
3150 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
f684960e CW |
3151 | kfree(edid); |
3152 | } | |
a9756bb5 ZW |
3153 | } |
3154 | ||
d63885da PZ |
3155 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
3156 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
c8c8fb33 PZ |
3157 | status = connector_status_connected; |
3158 | ||
3159 | out: | |
671dedd2 ID |
3160 | intel_display_power_put(dev_priv, power_domain); |
3161 | ||
c8c8fb33 | 3162 | intel_runtime_pm_put(dev_priv); |
671dedd2 | 3163 | |
c8c8fb33 | 3164 | return status; |
a4fc5ed6 KP |
3165 | } |
3166 | ||
3167 | static int intel_dp_get_modes(struct drm_connector *connector) | |
3168 | { | |
df0e9248 | 3169 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
671dedd2 ID |
3170 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3171 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
dd06f90e | 3172 | struct intel_connector *intel_connector = to_intel_connector(connector); |
fa90ecef | 3173 | struct drm_device *dev = connector->dev; |
671dedd2 ID |
3174 | struct drm_i915_private *dev_priv = dev->dev_private; |
3175 | enum intel_display_power_domain power_domain; | |
32f9d658 | 3176 | int ret; |
a4fc5ed6 KP |
3177 | |
3178 | /* We should parse the EDID data and find out if it has an audio sink | |
3179 | */ | |
3180 | ||
671dedd2 ID |
3181 | power_domain = intel_display_port_power_domain(intel_encoder); |
3182 | intel_display_power_get(dev_priv, power_domain); | |
3183 | ||
0b99836f | 3184 | ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc); |
671dedd2 | 3185 | intel_display_power_put(dev_priv, power_domain); |
f8779fda | 3186 | if (ret) |
32f9d658 ZW |
3187 | return ret; |
3188 | ||
f8779fda | 3189 | /* if eDP has no EDID, fall back to fixed mode */ |
dd06f90e | 3190 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
f8779fda | 3191 | struct drm_display_mode *mode; |
dd06f90e JN |
3192 | mode = drm_mode_duplicate(dev, |
3193 | intel_connector->panel.fixed_mode); | |
f8779fda | 3194 | if (mode) { |
32f9d658 ZW |
3195 | drm_mode_probed_add(connector, mode); |
3196 | return 1; | |
3197 | } | |
3198 | } | |
3199 | return 0; | |
a4fc5ed6 KP |
3200 | } |
3201 | ||
1aad7ac0 CW |
3202 | static bool |
3203 | intel_dp_detect_audio(struct drm_connector *connector) | |
3204 | { | |
3205 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
671dedd2 ID |
3206 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3207 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
3208 | struct drm_device *dev = connector->dev; | |
3209 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3210 | enum intel_display_power_domain power_domain; | |
1aad7ac0 CW |
3211 | struct edid *edid; |
3212 | bool has_audio = false; | |
3213 | ||
671dedd2 ID |
3214 | power_domain = intel_display_port_power_domain(intel_encoder); |
3215 | intel_display_power_get(dev_priv, power_domain); | |
3216 | ||
0b99836f | 3217 | edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); |
1aad7ac0 CW |
3218 | if (edid) { |
3219 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
3220 | kfree(edid); |
3221 | } | |
3222 | ||
671dedd2 ID |
3223 | intel_display_power_put(dev_priv, power_domain); |
3224 | ||
1aad7ac0 CW |
3225 | return has_audio; |
3226 | } | |
3227 | ||
f684960e CW |
3228 | static int |
3229 | intel_dp_set_property(struct drm_connector *connector, | |
3230 | struct drm_property *property, | |
3231 | uint64_t val) | |
3232 | { | |
e953fd7b | 3233 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
53b41837 | 3234 | struct intel_connector *intel_connector = to_intel_connector(connector); |
da63a9f2 PZ |
3235 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
3236 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
f684960e CW |
3237 | int ret; |
3238 | ||
662595df | 3239 | ret = drm_object_property_set_value(&connector->base, property, val); |
f684960e CW |
3240 | if (ret) |
3241 | return ret; | |
3242 | ||
3f43c48d | 3243 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
3244 | int i = val; |
3245 | bool has_audio; | |
3246 | ||
3247 | if (i == intel_dp->force_audio) | |
f684960e CW |
3248 | return 0; |
3249 | ||
1aad7ac0 | 3250 | intel_dp->force_audio = i; |
f684960e | 3251 | |
c3e5f67b | 3252 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
3253 | has_audio = intel_dp_detect_audio(connector); |
3254 | else | |
c3e5f67b | 3255 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
3256 | |
3257 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
3258 | return 0; |
3259 | ||
1aad7ac0 | 3260 | intel_dp->has_audio = has_audio; |
f684960e CW |
3261 | goto done; |
3262 | } | |
3263 | ||
e953fd7b | 3264 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
3265 | bool old_auto = intel_dp->color_range_auto; |
3266 | uint32_t old_range = intel_dp->color_range; | |
3267 | ||
55bc60db VS |
3268 | switch (val) { |
3269 | case INTEL_BROADCAST_RGB_AUTO: | |
3270 | intel_dp->color_range_auto = true; | |
3271 | break; | |
3272 | case INTEL_BROADCAST_RGB_FULL: | |
3273 | intel_dp->color_range_auto = false; | |
3274 | intel_dp->color_range = 0; | |
3275 | break; | |
3276 | case INTEL_BROADCAST_RGB_LIMITED: | |
3277 | intel_dp->color_range_auto = false; | |
3278 | intel_dp->color_range = DP_COLOR_RANGE_16_235; | |
3279 | break; | |
3280 | default: | |
3281 | return -EINVAL; | |
3282 | } | |
ae4edb80 DV |
3283 | |
3284 | if (old_auto == intel_dp->color_range_auto && | |
3285 | old_range == intel_dp->color_range) | |
3286 | return 0; | |
3287 | ||
e953fd7b CW |
3288 | goto done; |
3289 | } | |
3290 | ||
53b41837 YN |
3291 | if (is_edp(intel_dp) && |
3292 | property == connector->dev->mode_config.scaling_mode_property) { | |
3293 | if (val == DRM_MODE_SCALE_NONE) { | |
3294 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
3295 | return -EINVAL; | |
3296 | } | |
3297 | ||
3298 | if (intel_connector->panel.fitting_mode == val) { | |
3299 | /* the eDP scaling property is not changed */ | |
3300 | return 0; | |
3301 | } | |
3302 | intel_connector->panel.fitting_mode = val; | |
3303 | ||
3304 | goto done; | |
3305 | } | |
3306 | ||
f684960e CW |
3307 | return -EINVAL; |
3308 | ||
3309 | done: | |
c0c36b94 CW |
3310 | if (intel_encoder->base.crtc) |
3311 | intel_crtc_restore_mode(intel_encoder->base.crtc); | |
f684960e CW |
3312 | |
3313 | return 0; | |
3314 | } | |
3315 | ||
a4fc5ed6 | 3316 | static void |
73845adf | 3317 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 3318 | { |
1d508706 | 3319 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 3320 | |
9cd300e0 JN |
3321 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
3322 | kfree(intel_connector->edid); | |
3323 | ||
acd8db10 PZ |
3324 | /* Can't call is_edp() since the encoder may have been destroyed |
3325 | * already. */ | |
3326 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
1d508706 | 3327 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 3328 | |
a4fc5ed6 | 3329 | drm_connector_cleanup(connector); |
55f78c43 | 3330 | kfree(connector); |
a4fc5ed6 KP |
3331 | } |
3332 | ||
00c09d70 | 3333 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 3334 | { |
da63a9f2 PZ |
3335 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
3336 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
bd173813 | 3337 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
24d05927 | 3338 | |
0b99836f | 3339 | drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); |
24d05927 | 3340 | drm_encoder_cleanup(encoder); |
bd943159 KP |
3341 | if (is_edp(intel_dp)) { |
3342 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
bd173813 | 3343 | mutex_lock(&dev->mode_config.mutex); |
4be73780 | 3344 | edp_panel_vdd_off_sync(intel_dp); |
bd173813 | 3345 | mutex_unlock(&dev->mode_config.mutex); |
bd943159 | 3346 | } |
da63a9f2 | 3347 | kfree(intel_dig_port); |
24d05927 DV |
3348 | } |
3349 | ||
a4fc5ed6 | 3350 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
2bd2ad64 | 3351 | .dpms = intel_connector_dpms, |
a4fc5ed6 KP |
3352 | .detect = intel_dp_detect, |
3353 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 3354 | .set_property = intel_dp_set_property, |
73845adf | 3355 | .destroy = intel_dp_connector_destroy, |
a4fc5ed6 KP |
3356 | }; |
3357 | ||
3358 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
3359 | .get_modes = intel_dp_get_modes, | |
3360 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 3361 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
3362 | }; |
3363 | ||
a4fc5ed6 | 3364 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 3365 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
3366 | }; |
3367 | ||
995b6762 | 3368 | static void |
21d40d37 | 3369 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 3370 | { |
fa90ecef | 3371 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
c8110e52 | 3372 | |
885a5014 | 3373 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 3374 | } |
6207937d | 3375 | |
e3421a18 ZW |
3376 | /* Return which DP Port should be selected for Transcoder DP control */ |
3377 | int | |
0206e353 | 3378 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
e3421a18 ZW |
3379 | { |
3380 | struct drm_device *dev = crtc->dev; | |
fa90ecef PZ |
3381 | struct intel_encoder *intel_encoder; |
3382 | struct intel_dp *intel_dp; | |
e3421a18 | 3383 | |
fa90ecef PZ |
3384 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
3385 | intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
e3421a18 | 3386 | |
fa90ecef PZ |
3387 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
3388 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
ea5b213a | 3389 | return intel_dp->output_reg; |
e3421a18 | 3390 | } |
ea5b213a | 3391 | |
e3421a18 ZW |
3392 | return -1; |
3393 | } | |
3394 | ||
36e83a18 | 3395 | /* check the VBT to see whether the eDP is on DP-D port */ |
5d8a7752 | 3396 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
36e83a18 ZY |
3397 | { |
3398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
768f69c9 | 3399 | union child_device_config *p_child; |
36e83a18 | 3400 | int i; |
5d8a7752 VS |
3401 | static const short port_mapping[] = { |
3402 | [PORT_B] = PORT_IDPB, | |
3403 | [PORT_C] = PORT_IDPC, | |
3404 | [PORT_D] = PORT_IDPD, | |
3405 | }; | |
36e83a18 | 3406 | |
3b32a35b VS |
3407 | if (port == PORT_A) |
3408 | return true; | |
3409 | ||
41aa3448 | 3410 | if (!dev_priv->vbt.child_dev_num) |
36e83a18 ZY |
3411 | return false; |
3412 | ||
41aa3448 RV |
3413 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
3414 | p_child = dev_priv->vbt.child_dev + i; | |
36e83a18 | 3415 | |
5d8a7752 | 3416 | if (p_child->common.dvo_port == port_mapping[port] && |
f02586df VS |
3417 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
3418 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) | |
36e83a18 ZY |
3419 | return true; |
3420 | } | |
3421 | return false; | |
3422 | } | |
3423 | ||
f684960e CW |
3424 | static void |
3425 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
3426 | { | |
53b41837 YN |
3427 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3428 | ||
3f43c48d | 3429 | intel_attach_force_audio_property(connector); |
e953fd7b | 3430 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 3431 | intel_dp->color_range_auto = true; |
53b41837 YN |
3432 | |
3433 | if (is_edp(intel_dp)) { | |
3434 | drm_mode_create_scaling_mode_property(connector->dev); | |
6de6d846 RC |
3435 | drm_object_attach_property( |
3436 | &connector->base, | |
53b41837 | 3437 | connector->dev->mode_config.scaling_mode_property, |
8e740cd1 YN |
3438 | DRM_MODE_SCALE_ASPECT); |
3439 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
53b41837 | 3440 | } |
f684960e CW |
3441 | } |
3442 | ||
dada1a9f ID |
3443 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
3444 | { | |
3445 | intel_dp->last_power_cycle = jiffies; | |
3446 | intel_dp->last_power_on = jiffies; | |
3447 | intel_dp->last_backlight_off = jiffies; | |
3448 | } | |
3449 | ||
67a54566 DV |
3450 | static void |
3451 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
f30d26e4 JN |
3452 | struct intel_dp *intel_dp, |
3453 | struct edp_power_seq *out) | |
67a54566 DV |
3454 | { |
3455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3456 | struct edp_power_seq cur, vbt, spec, final; | |
3457 | u32 pp_on, pp_off, pp_div, pp; | |
bf13e81b | 3458 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
453c5420 JB |
3459 | |
3460 | if (HAS_PCH_SPLIT(dev)) { | |
bf13e81b | 3461 | pp_ctrl_reg = PCH_PP_CONTROL; |
453c5420 JB |
3462 | pp_on_reg = PCH_PP_ON_DELAYS; |
3463 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
3464 | pp_div_reg = PCH_PP_DIVISOR; | |
3465 | } else { | |
bf13e81b JN |
3466 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
3467 | ||
3468 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); | |
3469 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
3470 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
3471 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 | 3472 | } |
67a54566 DV |
3473 | |
3474 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
3475 | * the very first thing. */ | |
453c5420 | 3476 | pp = ironlake_get_pp_control(intel_dp); |
bf13e81b | 3477 | I915_WRITE(pp_ctrl_reg, pp); |
67a54566 | 3478 | |
453c5420 JB |
3479 | pp_on = I915_READ(pp_on_reg); |
3480 | pp_off = I915_READ(pp_off_reg); | |
3481 | pp_div = I915_READ(pp_div_reg); | |
67a54566 DV |
3482 | |
3483 | /* Pull timing values out of registers */ | |
3484 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
3485 | PANEL_POWER_UP_DELAY_SHIFT; | |
3486 | ||
3487 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
3488 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
3489 | ||
3490 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
3491 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
3492 | ||
3493 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
3494 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
3495 | ||
3496 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
3497 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
3498 | ||
3499 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
3500 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
3501 | ||
41aa3448 | 3502 | vbt = dev_priv->vbt.edp_pps; |
67a54566 DV |
3503 | |
3504 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
3505 | * our hw here, which are all in 100usec. */ | |
3506 | spec.t1_t3 = 210 * 10; | |
3507 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
3508 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
3509 | spec.t10 = 500 * 10; | |
3510 | /* This one is special and actually in units of 100ms, but zero | |
3511 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
3512 | * table multiplies it with 1000 to make it in units of 100usec, | |
3513 | * too. */ | |
3514 | spec.t11_t12 = (510 + 100) * 10; | |
3515 | ||
3516 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
3517 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
3518 | ||
3519 | /* Use the max of the register settings and vbt. If both are | |
3520 | * unset, fall back to the spec limits. */ | |
3521 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ | |
3522 | spec.field : \ | |
3523 | max(cur.field, vbt.field)) | |
3524 | assign_final(t1_t3); | |
3525 | assign_final(t8); | |
3526 | assign_final(t9); | |
3527 | assign_final(t10); | |
3528 | assign_final(t11_t12); | |
3529 | #undef assign_final | |
3530 | ||
3531 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) | |
3532 | intel_dp->panel_power_up_delay = get_delay(t1_t3); | |
3533 | intel_dp->backlight_on_delay = get_delay(t8); | |
3534 | intel_dp->backlight_off_delay = get_delay(t9); | |
3535 | intel_dp->panel_power_down_delay = get_delay(t10); | |
3536 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
3537 | #undef get_delay | |
3538 | ||
f30d26e4 JN |
3539 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
3540 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
3541 | intel_dp->panel_power_cycle_delay); | |
3542 | ||
3543 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
3544 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
3545 | ||
3546 | if (out) | |
3547 | *out = final; | |
3548 | } | |
3549 | ||
3550 | static void | |
3551 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
3552 | struct intel_dp *intel_dp, | |
3553 | struct edp_power_seq *seq) | |
3554 | { | |
3555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
453c5420 JB |
3556 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
3557 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); | |
3558 | int pp_on_reg, pp_off_reg, pp_div_reg; | |
3559 | ||
3560 | if (HAS_PCH_SPLIT(dev)) { | |
3561 | pp_on_reg = PCH_PP_ON_DELAYS; | |
3562 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
3563 | pp_div_reg = PCH_PP_DIVISOR; | |
3564 | } else { | |
bf13e81b JN |
3565 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
3566 | ||
3567 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
3568 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
3569 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 JB |
3570 | } |
3571 | ||
b2f19d1a PZ |
3572 | /* |
3573 | * And finally store the new values in the power sequencer. The | |
3574 | * backlight delays are set to 1 because we do manual waits on them. For | |
3575 | * T8, even BSpec recommends doing it. For T9, if we don't do this, | |
3576 | * we'll end up waiting for the backlight off delay twice: once when we | |
3577 | * do the manual sleep, and once when we disable the panel and wait for | |
3578 | * the PP_STATUS bit to become zero. | |
3579 | */ | |
f30d26e4 | 3580 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
b2f19d1a PZ |
3581 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
3582 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 3583 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
3584 | /* Compute the divisor for the pp clock, simply match the Bspec |
3585 | * formula. */ | |
453c5420 | 3586 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
f30d26e4 | 3587 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
67a54566 DV |
3588 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
3589 | ||
3590 | /* Haswell doesn't have any port selection bits for the panel | |
3591 | * power sequencer any more. */ | |
bc7d38a4 | 3592 | if (IS_VALLEYVIEW(dev)) { |
bf13e81b JN |
3593 | if (dp_to_dig_port(intel_dp)->port == PORT_B) |
3594 | port_sel = PANEL_PORT_SELECT_DPB_VLV; | |
3595 | else | |
3596 | port_sel = PANEL_PORT_SELECT_DPC_VLV; | |
bc7d38a4 ID |
3597 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
3598 | if (dp_to_dig_port(intel_dp)->port == PORT_A) | |
a24c144c | 3599 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 3600 | else |
a24c144c | 3601 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
3602 | } |
3603 | ||
453c5420 JB |
3604 | pp_on |= port_sel; |
3605 | ||
3606 | I915_WRITE(pp_on_reg, pp_on); | |
3607 | I915_WRITE(pp_off_reg, pp_off); | |
3608 | I915_WRITE(pp_div_reg, pp_div); | |
67a54566 | 3609 | |
67a54566 | 3610 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
453c5420 JB |
3611 | I915_READ(pp_on_reg), |
3612 | I915_READ(pp_off_reg), | |
3613 | I915_READ(pp_div_reg)); | |
f684960e CW |
3614 | } |
3615 | ||
ed92f0b2 | 3616 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
0095e6dc PZ |
3617 | struct intel_connector *intel_connector, |
3618 | struct edp_power_seq *power_seq) | |
ed92f0b2 PZ |
3619 | { |
3620 | struct drm_connector *connector = &intel_connector->base; | |
3621 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3622 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
3623 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3624 | struct drm_display_mode *fixed_mode = NULL; | |
ed92f0b2 PZ |
3625 | bool has_dpcd; |
3626 | struct drm_display_mode *scan; | |
3627 | struct edid *edid; | |
3628 | ||
3629 | if (!is_edp(intel_dp)) | |
3630 | return true; | |
3631 | ||
ed92f0b2 | 3632 | /* Cache DPCD and EDID for edp. */ |
24f3e092 | 3633 | intel_edp_panel_vdd_on(intel_dp); |
ed92f0b2 | 3634 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
4be73780 | 3635 | edp_panel_vdd_off(intel_dp, false); |
ed92f0b2 PZ |
3636 | |
3637 | if (has_dpcd) { | |
3638 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) | |
3639 | dev_priv->no_aux_handshake = | |
3640 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
3641 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
3642 | } else { | |
3643 | /* if this fails, presume the device is a ghost */ | |
3644 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
ed92f0b2 PZ |
3645 | return false; |
3646 | } | |
3647 | ||
3648 | /* We now know it's not a ghost, init power sequence regs. */ | |
0095e6dc | 3649 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); |
ed92f0b2 | 3650 | |
060c8778 | 3651 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 3652 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
3653 | if (edid) { |
3654 | if (drm_add_edid_modes(connector, edid)) { | |
3655 | drm_mode_connector_update_edid_property(connector, | |
3656 | edid); | |
3657 | drm_edid_to_eld(connector, edid); | |
3658 | } else { | |
3659 | kfree(edid); | |
3660 | edid = ERR_PTR(-EINVAL); | |
3661 | } | |
3662 | } else { | |
3663 | edid = ERR_PTR(-ENOENT); | |
3664 | } | |
3665 | intel_connector->edid = edid; | |
3666 | ||
3667 | /* prefer fixed mode from EDID if available */ | |
3668 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
3669 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
3670 | fixed_mode = drm_mode_duplicate(dev, scan); | |
3671 | break; | |
3672 | } | |
3673 | } | |
3674 | ||
3675 | /* fallback to VBT if available for eDP */ | |
3676 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
3677 | fixed_mode = drm_mode_duplicate(dev, | |
3678 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
3679 | if (fixed_mode) | |
3680 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
3681 | } | |
060c8778 | 3682 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 3683 | |
4b6ed685 | 3684 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
ed92f0b2 PZ |
3685 | intel_panel_setup_backlight(connector); |
3686 | ||
3687 | return true; | |
3688 | } | |
3689 | ||
16c25533 | 3690 | bool |
f0fec3f2 PZ |
3691 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
3692 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 3693 | { |
f0fec3f2 PZ |
3694 | struct drm_connector *connector = &intel_connector->base; |
3695 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
3696 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
3697 | struct drm_device *dev = intel_encoder->base.dev; | |
a4fc5ed6 | 3698 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 3699 | enum port port = intel_dig_port->port; |
0095e6dc | 3700 | struct edp_power_seq power_seq = { 0 }; |
0b99836f | 3701 | int type; |
a4fc5ed6 | 3702 | |
ec5b01dd DL |
3703 | /* intel_dp vfuncs */ |
3704 | if (IS_VALLEYVIEW(dev)) | |
3705 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; | |
3706 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
3707 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; | |
3708 | else if (HAS_PCH_SPLIT(dev)) | |
3709 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; | |
3710 | else | |
3711 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; | |
3712 | ||
153b1100 DL |
3713 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
3714 | ||
0767935e DV |
3715 | /* Preserve the current hw state. */ |
3716 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 3717 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 3718 | |
3b32a35b | 3719 | if (intel_dp_is_edp(dev, port)) |
b329530c | 3720 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
3721 | else |
3722 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 3723 | |
f7d24902 ID |
3724 | /* |
3725 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
3726 | * for DP the encoder type can be set by the caller to | |
3727 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
3728 | */ | |
3729 | if (type == DRM_MODE_CONNECTOR_eDP) | |
3730 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
3731 | ||
e7281eab ID |
3732 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
3733 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
3734 | port_name(port)); | |
3735 | ||
b329530c | 3736 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
3737 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
3738 | ||
a4fc5ed6 KP |
3739 | connector->interlace_allowed = true; |
3740 | connector->doublescan_allowed = 0; | |
3741 | ||
f0fec3f2 | 3742 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 3743 | edp_panel_vdd_work); |
a4fc5ed6 | 3744 | |
df0e9248 | 3745 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
3746 | drm_sysfs_connector_add(connector); |
3747 | ||
affa9354 | 3748 | if (HAS_DDI(dev)) |
bcbc889b PZ |
3749 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
3750 | else | |
3751 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
80f65de3 | 3752 | intel_connector->unregister = intel_dp_connector_unregister; |
bcbc889b | 3753 | |
0b99836f | 3754 | /* Set up the hotplug pin. */ |
ab9d7c30 PZ |
3755 | switch (port) { |
3756 | case PORT_A: | |
1d843f9d | 3757 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
3758 | break; |
3759 | case PORT_B: | |
1d843f9d | 3760 | intel_encoder->hpd_pin = HPD_PORT_B; |
ab9d7c30 PZ |
3761 | break; |
3762 | case PORT_C: | |
1d843f9d | 3763 | intel_encoder->hpd_pin = HPD_PORT_C; |
ab9d7c30 PZ |
3764 | break; |
3765 | case PORT_D: | |
1d843f9d | 3766 | intel_encoder->hpd_pin = HPD_PORT_D; |
ab9d7c30 PZ |
3767 | break; |
3768 | default: | |
ad1c0b19 | 3769 | BUG(); |
5eb08b69 ZW |
3770 | } |
3771 | ||
dada1a9f ID |
3772 | if (is_edp(intel_dp)) { |
3773 | intel_dp_init_panel_power_timestamps(intel_dp); | |
0095e6dc | 3774 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
dada1a9f | 3775 | } |
0095e6dc | 3776 | |
9d1a1031 | 3777 | intel_dp_aux_init(intel_dp, intel_connector); |
c1f05264 | 3778 | |
2b28bb1b RV |
3779 | intel_dp->psr_setup_done = false; |
3780 | ||
0095e6dc | 3781 | if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { |
0b99836f | 3782 | drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); |
15b1d171 PZ |
3783 | if (is_edp(intel_dp)) { |
3784 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
3785 | mutex_lock(&dev->mode_config.mutex); | |
4be73780 | 3786 | edp_panel_vdd_off_sync(intel_dp); |
15b1d171 PZ |
3787 | mutex_unlock(&dev->mode_config.mutex); |
3788 | } | |
b2f246a8 PZ |
3789 | drm_sysfs_connector_remove(connector); |
3790 | drm_connector_cleanup(connector); | |
16c25533 | 3791 | return false; |
b2f246a8 | 3792 | } |
32f9d658 | 3793 | |
f684960e CW |
3794 | intel_dp_add_properties(intel_dp, connector); |
3795 | ||
a4fc5ed6 KP |
3796 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
3797 | * 0xd. Failure to do so will result in spurious interrupts being | |
3798 | * generated on the port when a cable is not attached. | |
3799 | */ | |
3800 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
3801 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
3802 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
3803 | } | |
16c25533 PZ |
3804 | |
3805 | return true; | |
a4fc5ed6 | 3806 | } |
f0fec3f2 PZ |
3807 | |
3808 | void | |
3809 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) | |
3810 | { | |
3811 | struct intel_digital_port *intel_dig_port; | |
3812 | struct intel_encoder *intel_encoder; | |
3813 | struct drm_encoder *encoder; | |
3814 | struct intel_connector *intel_connector; | |
3815 | ||
b14c5679 | 3816 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 PZ |
3817 | if (!intel_dig_port) |
3818 | return; | |
3819 | ||
b14c5679 | 3820 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
f0fec3f2 PZ |
3821 | if (!intel_connector) { |
3822 | kfree(intel_dig_port); | |
3823 | return; | |
3824 | } | |
3825 | ||
3826 | intel_encoder = &intel_dig_port->base; | |
3827 | encoder = &intel_encoder->base; | |
3828 | ||
3829 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, | |
3830 | DRM_MODE_ENCODER_TMDS); | |
3831 | ||
5bfe2ac0 | 3832 | intel_encoder->compute_config = intel_dp_compute_config; |
b934223d | 3833 | intel_encoder->mode_set = intel_dp_mode_set; |
00c09d70 PZ |
3834 | intel_encoder->disable = intel_disable_dp; |
3835 | intel_encoder->post_disable = intel_post_disable_dp; | |
3836 | intel_encoder->get_hw_state = intel_dp_get_hw_state; | |
045ac3b5 | 3837 | intel_encoder->get_config = intel_dp_get_config; |
ab1f90f9 | 3838 | if (IS_VALLEYVIEW(dev)) { |
ecff4f3b | 3839 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
3840 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
3841 | intel_encoder->enable = vlv_enable_dp; | |
3842 | } else { | |
ecff4f3b JN |
3843 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
3844 | intel_encoder->enable = g4x_enable_dp; | |
ab1f90f9 | 3845 | } |
f0fec3f2 | 3846 | |
174edf1f | 3847 | intel_dig_port->port = port; |
f0fec3f2 PZ |
3848 | intel_dig_port->dp.output_reg = output_reg; |
3849 | ||
00c09d70 | 3850 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
f0fec3f2 | 3851 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
bc079e8b | 3852 | intel_encoder->cloneable = 0; |
f0fec3f2 PZ |
3853 | intel_encoder->hot_plug = intel_dp_hot_plug; |
3854 | ||
15b1d171 PZ |
3855 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { |
3856 | drm_encoder_cleanup(encoder); | |
3857 | kfree(intel_dig_port); | |
b2f246a8 | 3858 | kfree(intel_connector); |
15b1d171 | 3859 | } |
f0fec3f2 | 3860 | } |