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drm/i915: Handle runtime pm in the CRC setup code
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 116static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 117static void vlv_steal_power_sequencer(struct drm_device *dev,
118 enum pipe pipe);
a4fc5ed6 119
0e32b39c 120int
ea5b213a 121intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 122{
7183dc29 123 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 124 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 125
126 switch (max_link_bw) {
127 case DP_LINK_BW_1_62:
128 case DP_LINK_BW_2_7:
129 break;
d4eead50 130 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 131 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
132 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 133 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
134 max_link_bw = DP_LINK_BW_5_4;
135 else
136 max_link_bw = DP_LINK_BW_2_7;
d4eead50 137 break;
a4fc5ed6 138 default:
d4eead50
ID		 139 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
140 max_link_bw);
a4fc5ed6
KP		 141 max_link_bw = DP_LINK_BW_1_62;
142 break;
143 }
144 return max_link_bw;
145}
146
eeb6324d
PZ		 147static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
148{
149 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
150 struct drm_device *dev = intel_dig_port->base.base.dev;
151 u8 source_max, sink_max;
152
153 source_max = 4;
154 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
155 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
156 source_max = 2;
157
158 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
159
160 return min(source_max, sink_max);
161}
162
cd9dde44
AJ		 163/*
164 * The units on the numbers in the next two are... bizarre. Examples will
165 * make it clearer; this one parallels an example in the eDP spec.
166 *
167 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
168 *
169 * 270000 * 1 * 8 / 10 == 216000
170 *
171 * The actual data capacity of that configuration is 2.16Gbit/s, so the
172 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
173 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
174 * 119000. At 18bpp that's 2142000 kilobits per second.
175 *
176 * Thus the strange-looking division by 10 in intel_dp_link_required, to
177 * get the result in decakilobits instead of kilobits.
178 */
179
a4fc5ed6 180static int
c898261c 181intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 182{
cd9dde44 183 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 184}
185
fe27d53e
DA		 186static int
187intel_dp_max_data_rate(int max_link_clock, int max_lanes)
188{
189 return (max_link_clock * max_lanes * 8) / 10;
190}
191
c19de8eb 192static enum drm_mode_status
a4fc5ed6
KP		 193intel_dp_mode_valid(struct drm_connector *connector,
194 struct drm_display_mode *mode)
195{
df0e9248 196 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 197 struct intel_connector *intel_connector = to_intel_connector(connector);
198 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 199 int target_clock = mode->clock;
200 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 201
dd06f90e
JN		 202 if (is_edp(intel_dp) && fixed_mode) {
203 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 204 return MODE_PANEL;
205
dd06f90e 206 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 207 return MODE_PANEL;
03afc4a2
DV		 208
209 target_clock = fixed_mode->clock;
7de56f43
ZY		 210 }
211
36008365 212 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 213 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 214
215 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
216 mode_rate = intel_dp_link_required(target_clock, 18);
217
218 if (mode_rate > max_rate)
c4867936 219 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 220
221 if (mode->clock < 10000)
222 return MODE_CLOCK_LOW;
223
0af78a2b
DV		 224 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
225 return MODE_H_ILLEGAL;
226
a4fc5ed6
KP		 227 return MODE_OK;
228}
229
a4f1289e 230uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 231{
232 int i;
233 uint32_t v = 0;
234
235 if (src_bytes > 4)
236 src_bytes = 4;
237 for (i = 0; i < src_bytes; i++)
238 v |= ((uint32_t) src[i]) << ((3-i) * 8);
239 return v;
240}
241
a4f1289e 242void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 243{
244 int i;
245 if (dst_bytes > 4)
246 dst_bytes = 4;
247 for (i = 0; i < dst_bytes; i++)
248 dst[i] = src >> ((3-i) * 8);
249}
250
fb0f8fbf
KP		 251/* hrawclock is 1/4 the FSB frequency */
252static int
253intel_hrawclk(struct drm_device *dev)
254{
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 uint32_t clkcfg;
257
9473c8f4
VP		 258 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
259 if (IS_VALLEYVIEW(dev))
260 return 200;
261
fb0f8fbf
KP		 262 clkcfg = I915_READ(CLKCFG);
263 switch (clkcfg & CLKCFG_FSB_MASK) {
264 case CLKCFG_FSB_400:
265 return 100;
266 case CLKCFG_FSB_533:
267 return 133;
268 case CLKCFG_FSB_667:
269 return 166;
270 case CLKCFG_FSB_800:
271 return 200;
272 case CLKCFG_FSB_1067:
273 return 266;
274 case CLKCFG_FSB_1333:
275 return 333;
276 /* these two are just a guess; one of them might be right */
277 case CLKCFG_FSB_1600:
278 case CLKCFG_FSB_1600_ALT:
279 return 400;
280 default:
281 return 133;
282 }
283}
284
bf13e81b
JN		 285static void
286intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 287 struct intel_dp *intel_dp);
bf13e81b
JN		 288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 290 struct intel_dp *intel_dp);
bf13e81b 291
773538e8
VS		 292static void pps_lock(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct intel_encoder *encoder = &intel_dig_port->base;
296 struct drm_device *dev = encoder->base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum intel_display_power_domain power_domain;
299
300 /*
301 * See vlv_power_sequencer_reset() why we need
302 * a power domain reference here.
303 */
304 power_domain = intel_display_port_power_domain(encoder);
305 intel_display_power_get(dev_priv, power_domain);
306
307 mutex_lock(&dev_priv->pps_mutex);
308}
309
310static void pps_unlock(struct intel_dp *intel_dp)
311{
312 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
313 struct intel_encoder *encoder = &intel_dig_port->base;
314 struct drm_device *dev = encoder->base.dev;
315 struct drm_i915_private *dev_priv = dev->dev_private;
316 enum intel_display_power_domain power_domain;
317
318 mutex_unlock(&dev_priv->pps_mutex);
319
320 power_domain = intel_display_port_power_domain(encoder);
321 intel_display_power_put(dev_priv, power_domain);
322}
323
961a0db0
VS		 324static void
325vlv_power_sequencer_kick(struct intel_dp *intel_dp)
326{
327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
328 struct drm_device *dev = intel_dig_port->base.base.dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330 enum pipe pipe = intel_dp->pps_pipe;
d288f65f 331 bool pll_enabled;
961a0db0
VS		 332 uint32_t DP;
333
334 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
335 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
336 pipe_name(pipe), port_name(intel_dig_port->port)))
337 return;
338
339 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
340 pipe_name(pipe), port_name(intel_dig_port->port));
341
342 /* Preserve the BIOS-computed detected bit. This is
343 * supposed to be read-only.
344 */
345 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
346 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
347 DP |= DP_PORT_WIDTH(1);
348 DP |= DP_LINK_TRAIN_PAT_1;
349
350 if (IS_CHERRYVIEW(dev))
351 DP |= DP_PIPE_SELECT_CHV(pipe);
352 else if (pipe == PIPE_B)
353 DP |= DP_PIPEB_SELECT;
354
d288f65f
VS		 355 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
356
357 /*
358 * The DPLL for the pipe must be enabled for this to work.
359 * So enable temporarily it if it's not already enabled.
360 */
361 if (!pll_enabled)
362 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
363 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
364
961a0db0
VS		 365 /*
366 * Similar magic as in intel_dp_enable_port().
367 * We _must_ do this port enable + disable trick
368 * to make this power seqeuencer lock onto the port.
369 * Otherwise even VDD force bit won't work.
370 */
371 I915_WRITE(intel_dp->output_reg, DP);
372 POSTING_READ(intel_dp->output_reg);
373
374 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
375 POSTING_READ(intel_dp->output_reg);
376
377 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
378 POSTING_READ(intel_dp->output_reg);
d288f65f
VS		 379
380 if (!pll_enabled)
381 vlv_force_pll_off(dev, pipe);
961a0db0
VS		 382}
383
bf13e81b
JN		 384static enum pipe
385vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
386{
387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 388 struct drm_device *dev = intel_dig_port->base.base.dev;
389 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 390 struct intel_encoder *encoder;
391 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 392 enum pipe pipe;
bf13e81b 393
e39b999a 394 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 395
a8c3344e
VS		 396 /* We should never land here with regular DP ports */
397 WARN_ON(!is_edp(intel_dp));
398
a4a5d2f8
VS		 399 if (intel_dp->pps_pipe != INVALID_PIPE)
400 return intel_dp->pps_pipe;
401
402 /*
403 * We don't have power sequencer currently.
404 * Pick one that's not used by other ports.
405 */
406 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
407 base.head) {
408 struct intel_dp *tmp;
409
410 if (encoder->type != INTEL_OUTPUT_EDP)
411 continue;
412
413 tmp = enc_to_intel_dp(&encoder->base);
414
415 if (tmp->pps_pipe != INVALID_PIPE)
416 pipes &= ~(1 << tmp->pps_pipe);
417 }
418
419 /*
420 * Didn't find one. This should not happen since there
421 * are two power sequencers and up to two eDP ports.
422 */
423 if (WARN_ON(pipes == 0))
a8c3344e
VS		 424 pipe = PIPE_A;
425 else
426 pipe = ffs(pipes) - 1;
a4a5d2f8 427
a8c3344e
VS		 428 vlv_steal_power_sequencer(dev, pipe);
429 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 430
431 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
432 pipe_name(intel_dp->pps_pipe),
433 port_name(intel_dig_port->port));
434
435 /* init power sequencer on this pipe and port */
36b5f425
VS		 436 intel_dp_init_panel_power_sequencer(dev, intel_dp);
437 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 438
961a0db0
VS		 439 /*
440 * Even vdd force doesn't work until we've made
441 * the power sequencer lock in on the port.
442 */
443 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 444
445 return intel_dp->pps_pipe;
446}
447
6491ab27
VS		 448typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
449 enum pipe pipe);
450
451static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
452 enum pipe pipe)
453{
454 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
455}
456
457static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
458 enum pipe pipe)
459{
460 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
461}
462
463static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
464 enum pipe pipe)
465{
466 return true;
467}
bf13e81b 468
a4a5d2f8 469static enum pipe
6491ab27
VS		 470vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
471 enum port port,
472 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 473{
474 enum pipe pipe;
bf13e81b 475
bf13e81b
JN		 476 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
477 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
478 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 479
480 if (port_sel != PANEL_PORT_SELECT_VLV(port))
481 continue;
482
6491ab27
VS		 483 if (!pipe_check(dev_priv, pipe))
484 continue;
485
a4a5d2f8 486 return pipe;
bf13e81b
JN		 487 }
488
a4a5d2f8
VS		 489 return INVALID_PIPE;
490}
491
492static void
493vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
494{
495 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
496 struct drm_device *dev = intel_dig_port->base.base.dev;
497 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 498 enum port port = intel_dig_port->port;
499
500 lockdep_assert_held(&dev_priv->pps_mutex);
501
502 /* try to find a pipe with this port selected */
6491ab27
VS		 503 /* first pick one where the panel is on */
504 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
505 vlv_pipe_has_pp_on);
506 /* didn't find one? pick one where vdd is on */
507 if (intel_dp->pps_pipe == INVALID_PIPE)
508 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
509 vlv_pipe_has_vdd_on);
510 /* didn't find one? pick one with just the correct port */
511 if (intel_dp->pps_pipe == INVALID_PIPE)
512 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
513 vlv_pipe_any);
a4a5d2f8
VS		 514
515 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
516 if (intel_dp->pps_pipe == INVALID_PIPE) {
517 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
518 port_name(port));
519 return;
bf13e81b
JN		 520 }
521
a4a5d2f8
VS		 522 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
523 port_name(port), pipe_name(intel_dp->pps_pipe));
524
36b5f425
VS		 525 intel_dp_init_panel_power_sequencer(dev, intel_dp);
526 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 527}
528
773538e8
VS		 529void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
530{
531 struct drm_device *dev = dev_priv->dev;
532 struct intel_encoder *encoder;
533
534 if (WARN_ON(!IS_VALLEYVIEW(dev)))
535 return;
536
537 /*
538 * We can't grab pps_mutex here due to deadlock with power_domain
539 * mutex when power_domain functions are called while holding pps_mutex.
540 * That also means that in order to use pps_pipe the code needs to
541 * hold both a power domain reference and pps_mutex, and the power domain
542 * reference get/put must be done while _not_ holding pps_mutex.
543 * pps_{lock,unlock}() do these steps in the correct order, so one
544 * should use them always.
545 */
546
547 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
548 struct intel_dp *intel_dp;
549
550 if (encoder->type != INTEL_OUTPUT_EDP)
551 continue;
552
553 intel_dp = enc_to_intel_dp(&encoder->base);
554 intel_dp->pps_pipe = INVALID_PIPE;
555 }
bf13e81b
JN		 556}
557
558static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
559{
560 struct drm_device *dev = intel_dp_to_dev(intel_dp);
561
562 if (HAS_PCH_SPLIT(dev))
563 return PCH_PP_CONTROL;
564 else
565 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
566}
567
568static u32 _pp_stat_reg(struct intel_dp *intel_dp)
569{
570 struct drm_device *dev = intel_dp_to_dev(intel_dp);
571
572 if (HAS_PCH_SPLIT(dev))
573 return PCH_PP_STATUS;
574 else
575 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
576}
577
01527b31
CT		 578/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
579 This function only applicable when panel PM state is not to be tracked */
580static int edp_notify_handler(struct notifier_block *this, unsigned long code,
581 void *unused)
582{
583 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
584 edp_notifier);
585 struct drm_device *dev = intel_dp_to_dev(intel_dp);
586 struct drm_i915_private *dev_priv = dev->dev_private;
587 u32 pp_div;
588 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 589
590 if (!is_edp(intel_dp) || code != SYS_RESTART)
591 return 0;
592
773538e8 593 pps_lock(intel_dp);
e39b999a 594
01527b31 595 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 596 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
597
01527b31
CT		 598 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
599 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
600 pp_div = I915_READ(pp_div_reg);
601 pp_div &= PP_REFERENCE_DIVIDER_MASK;
602
603 /* 0x1F write to PP_DIV_REG sets max cycle delay */
604 I915_WRITE(pp_div_reg, pp_div | 0x1F);
605 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
606 msleep(intel_dp->panel_power_cycle_delay);
607 }
608
773538e8 609 pps_unlock(intel_dp);
e39b999a 610
01527b31
CT		 611 return 0;
612}
613
4be73780 614static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 615{
30add22d 616 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 617 struct drm_i915_private *dev_priv = dev->dev_private;
618
e39b999a
VS		 619 lockdep_assert_held(&dev_priv->pps_mutex);
620
9a42356b
VS		 621 if (IS_VALLEYVIEW(dev) &&
622 intel_dp->pps_pipe == INVALID_PIPE)
623 return false;
624
bf13e81b 625 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 626}
627
4be73780 628static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 629{
30add22d 630 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 631 struct drm_i915_private *dev_priv = dev->dev_private;
632
e39b999a
VS		 633 lockdep_assert_held(&dev_priv->pps_mutex);
634
9a42356b
VS		 635 if (IS_VALLEYVIEW(dev) &&
636 intel_dp->pps_pipe == INVALID_PIPE)
637 return false;
638
773538e8 639 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 640}
641
9b984dae
KP		 642static void
643intel_dp_check_edp(struct intel_dp *intel_dp)
644{
30add22d 645 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 646 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 647
9b984dae
KP		 648 if (!is_edp(intel_dp))
649 return;
453c5420 650
4be73780 651 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 652 WARN(1, "eDP powered off while attempting aux channel communication.\n");
653 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 654 I915_READ(_pp_stat_reg(intel_dp)),
655 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 656 }
657}
658
9ee32fea
DV		 659static uint32_t
660intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
661{
662 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
663 struct drm_device *dev = intel_dig_port->base.base.dev;
664 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 665 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 666 uint32_t status;
667 bool done;
668
ef04f00d 669#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 670 if (has_aux_irq)
b18ac466 671 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 672 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 673 else
674 done = wait_for_atomic(C, 10) == 0;
675 if (!done)
676 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
677 has_aux_irq);
678#undef C
679
680 return status;
681}
682
ec5b01dd 683static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 684{
174edf1f
PZ		 685 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
686 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 687
ec5b01dd
DL		 688 /*
689 * The clock divider is based off the hrawclk, and would like to run at
690 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 691 */
ec5b01dd
DL		 692 return index ? 0 : intel_hrawclk(dev) / 2;
693}
694
695static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
696{
697 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
698 struct drm_device *dev = intel_dig_port->base.base.dev;
699
700 if (index)
701 return 0;
702
703 if (intel_dig_port->port == PORT_A) {
704 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 705 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 706 else
b84a1cf8 707 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 708 } else {
709 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
710 }
711}
712
713static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
714{
715 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
716 struct drm_device *dev = intel_dig_port->base.base.dev;
717 struct drm_i915_private *dev_priv = dev->dev_private;
718
719 if (intel_dig_port->port == PORT_A) {
720 if (index)
721 return 0;
722 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 723 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
724 /* Workaround for non-ULT HSW */
bc86625a
CW		 725 switch (index) {
726 case 0: return 63;
727 case 1: return 72;
728 default: return 0;
729 }
ec5b01dd 730 } else {
bc86625a 731 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 732 }
b84a1cf8
RV		 733}
734
ec5b01dd
DL		 735static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
736{
737 return index ? 0 : 100;
738}
739
b6b5e383
DL		 740static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
741{
742 /*
743 * SKL doesn't need us to program the AUX clock divider (Hardware will
744 * derive the clock from CDCLK automatically). We still implement the
745 * get_aux_clock_divider vfunc to plug-in into the existing code.
746 */
747 return index ? 0 : 1;
748}
749
5ed12a19
DL		 750static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
751 bool has_aux_irq,
752 int send_bytes,
753 uint32_t aux_clock_divider)
754{
755 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
756 struct drm_device *dev = intel_dig_port->base.base.dev;
757 uint32_t precharge, timeout;
758
759 if (IS_GEN6(dev))
760 precharge = 3;
761 else
762 precharge = 5;
763
764 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
765 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
766 else
767 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
768
769 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 770 DP_AUX_CH_CTL_DONE |
5ed12a19 771 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 772 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 773 timeout |
788d4433 774 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 775 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
776 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 777 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 778}
779
b9ca5fad
DL		 780static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
781 bool has_aux_irq,
782 int send_bytes,
783 uint32_t unused)
784{
785 return DP_AUX_CH_CTL_SEND_BUSY |
786 DP_AUX_CH_CTL_DONE |
787 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788 DP_AUX_CH_CTL_TIME_OUT_ERROR |
789 DP_AUX_CH_CTL_TIME_OUT_1600us |
790 DP_AUX_CH_CTL_RECEIVE_ERROR |
791 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
792 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
793}
794
b84a1cf8
RV		 795static int
796intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 797 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 798 uint8_t *recv, int recv_size)
799{
800 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
801 struct drm_device *dev = intel_dig_port->base.base.dev;
802 struct drm_i915_private *dev_priv = dev->dev_private;
803 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
804 uint32_t ch_data = ch_ctl + 4;
bc86625a 805 uint32_t aux_clock_divider;
b84a1cf8
RV		 806 int i, ret, recv_bytes;
807 uint32_t status;
5ed12a19 808 int try, clock = 0;
4e6b788c 809 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 810 bool vdd;
811
773538e8 812 pps_lock(intel_dp);
e39b999a 813
72c3500a
VS		 814 /*
815 * We will be called with VDD already enabled for dpcd/edid/oui reads.
816 * In such cases we want to leave VDD enabled and it's up to upper layers
817 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
818 * ourselves.
819 */
1e0560e0 820 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 821
822 /* dp aux is extremely sensitive to irq latency, hence request the
823 * lowest possible wakeup latency and so prevent the cpu from going into
824 * deep sleep states.
825 */
826 pm_qos_update_request(&dev_priv->pm_qos, 0);
827
828 intel_dp_check_edp(intel_dp);
5eb08b69 829
c67a470b
PZ		 830 intel_aux_display_runtime_get(dev_priv);
831
11bee43e
JB		 832 /* Try to wait for any previous AUX channel activity */
833 for (try = 0; try < 3; try++) {
ef04f00d 834 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 835 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
836 break;
837 msleep(1);
838 }
839
840 if (try == 3) {
841 WARN(1, "dp_aux_ch not started status 0x%08x\n",
842 I915_READ(ch_ctl));
9ee32fea
DV		 843 ret = -EBUSY;
844 goto out;
4f7f7b7e
CW		 845 }
846
46a5ae9f
PZ		 847 /* Only 5 data registers! */
848 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
849 ret = -E2BIG;
850 goto out;
851 }
852
ec5b01dd 853 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 854 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
855 has_aux_irq,
856 send_bytes,
857 aux_clock_divider);
5ed12a19 858
bc86625a
CW		 859 /* Must try at least 3 times according to DP spec */
860 for (try = 0; try < 5; try++) {
861 /* Load the send data into the aux channel data registers */
862 for (i = 0; i < send_bytes; i += 4)
863 I915_WRITE(ch_data + i,
a4f1289e
RV		 864 intel_dp_pack_aux(send + i,
865 send_bytes - i));
bc86625a
CW		 866
867 /* Send the command and wait for it to complete */
5ed12a19 868 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 869
870 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
871
872 /* Clear done status and any errors */
873 I915_WRITE(ch_ctl,
874 status |
875 DP_AUX_CH_CTL_DONE |
876 DP_AUX_CH_CTL_TIME_OUT_ERROR |
877 DP_AUX_CH_CTL_RECEIVE_ERROR);
878
879 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
880 DP_AUX_CH_CTL_RECEIVE_ERROR))
881 continue;
882 if (status & DP_AUX_CH_CTL_DONE)
883 break;
884 }
4f7f7b7e 885 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 886 break;
887 }
888
a4fc5ed6 889 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 890 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 891 ret = -EBUSY;
892 goto out;
a4fc5ed6
KP		 893 }
894
895 /* Check for timeout or receive error.
896 * Timeouts occur when the sink is not connected
897 */
a5b3da54 898 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 899 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 900 ret = -EIO;
901 goto out;
a5b3da54 902 }
1ae8c0a5
KP		 903
904 /* Timeouts occur when the device isn't connected, so they're
905 * "normal" -- don't fill the kernel log with these */
a5b3da54 906 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 907 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 908 ret = -ETIMEDOUT;
909 goto out;
a4fc5ed6
KP		 910 }
911
912 /* Unload any bytes sent back from the other side */
913 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
914 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 915 if (recv_bytes > recv_size)
916 recv_bytes = recv_size;
0206e353 917
4f7f7b7e 918 for (i = 0; i < recv_bytes; i += 4)
a4f1289e
RV		 919 intel_dp_unpack_aux(I915_READ(ch_data + i),
920 recv + i, recv_bytes - i);
a4fc5ed6 921
9ee32fea
DV		 922 ret = recv_bytes;
923out:
924 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 925 intel_aux_display_runtime_put(dev_priv);
9ee32fea 926
884f19e9
JN		 927 if (vdd)
928 edp_panel_vdd_off(intel_dp, false);
929
773538e8 930 pps_unlock(intel_dp);
e39b999a 931
9ee32fea 932 return ret;
a4fc5ed6
KP		 933}
934
a6c8aff0
JN		 935#define BARE_ADDRESS_SIZE 3
936#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 937static ssize_t
938intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 939{
9d1a1031
JN		 940 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
941 uint8_t txbuf[20], rxbuf[20];
942 size_t txsize, rxsize;
a4fc5ed6 943 int ret;
a4fc5ed6 944
9d1a1031
JN		 945 txbuf[0] = msg->request << 4;
946 txbuf[1] = msg->address >> 8;
947 txbuf[2] = msg->address & 0xff;
948 txbuf[3] = msg->size - 1;
46a5ae9f 949
9d1a1031
JN		 950 switch (msg->request & ~DP_AUX_I2C_MOT) {
951 case DP_AUX_NATIVE_WRITE:
952 case DP_AUX_I2C_WRITE:
a6c8aff0 953 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 954 rxsize = 1;
f51a44b9 955
9d1a1031
JN		 956 if (WARN_ON(txsize > 20))
957 return -E2BIG;
a4fc5ed6 958
9d1a1031 959 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 960
9d1a1031
JN		 961 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
962 if (ret > 0) {
963 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 964
9d1a1031
JN		 965 /* Return payload size. */
966 ret = msg->size;
967 }
968 break;
46a5ae9f 969
9d1a1031
JN		 970 case DP_AUX_NATIVE_READ:
971 case DP_AUX_I2C_READ:
a6c8aff0 972 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 973 rxsize = msg->size + 1;
a4fc5ed6 974
9d1a1031
JN		 975 if (WARN_ON(rxsize > 20))
976 return -E2BIG;
a4fc5ed6 977
9d1a1031
JN		 978 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
979 if (ret > 0) {
980 msg->reply = rxbuf[0] >> 4;
981 /*
982 * Assume happy day, and copy the data. The caller is
983 * expected to check msg->reply before touching it.
984 *
985 * Return payload size.
986 */
987 ret--;
988 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 989 }
9d1a1031
JN		 990 break;
991
992 default:
993 ret = -EINVAL;
994 break;
a4fc5ed6 995 }
f51a44b9 996
9d1a1031 997 return ret;
a4fc5ed6
KP		 998}
999
9d1a1031
JN		 1000static void
1001intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1002{
1003 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 1004 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1005 enum port port = intel_dig_port->port;
0b99836f 1006 const char *name = NULL;
ab2c0672
DA		 1007 int ret;
1008
33ad6626
JN		 1009 switch (port) {
1010 case PORT_A:
1011 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 1012 name = "DPDDC-A";
ab2c0672 1013 break;
33ad6626
JN		 1014 case PORT_B:
1015 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1016 name = "DPDDC-B";
ab2c0672 1017 break;
33ad6626
JN		 1018 case PORT_C:
1019 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1020 name = "DPDDC-C";
ab2c0672 1021 break;
33ad6626
JN		 1022 case PORT_D:
1023 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1024 name = "DPDDC-D";
33ad6626
JN		 1025 break;
1026 default:
1027 BUG();
ab2c0672
DA		 1028 }
1029
1b1aad75
DL		 1030 /*
1031 * The AUX_CTL register is usually DP_CTL + 0x10.
1032 *
1033 * On Haswell and Broadwell though:
1034 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1035 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1036 *
1037 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1038 */
1039 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1040 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1041
0b99836f 1042 intel_dp->aux.name = name;
9d1a1031
JN		 1043 intel_dp->aux.dev = dev->dev;
1044 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1045
0b99836f
JN		 1046 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1047 connector->base.kdev->kobj.name);
8316f337 1048
4f71d0cb 1049 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1050 if (ret < 0) {
4f71d0cb 1051 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1052 name, ret);
1053 return;
ab2c0672 1054 }
8a5e6aeb 1055
0b99836f
JN		 1056 ret = sysfs_create_link(&connector->base.kdev->kobj,
1057 &intel_dp->aux.ddc.dev.kobj,
1058 intel_dp->aux.ddc.dev.kobj.name);
1059 if (ret < 0) {
1060 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1061 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1062 }
a4fc5ed6
KP		 1063}
1064
80f65de3
ID		 1065static void
1066intel_dp_connector_unregister(struct intel_connector *intel_connector)
1067{
1068 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1069
0e32b39c
DA		 1070 if (!intel_connector->mst_port)
1071 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1072 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1073 intel_connector_unregister(intel_connector);
1074}
1075
5416d871
DL		 1076static void
1077skl_edp_set_pll_config(struct intel_crtc_config *pipe_config, int link_bw)
1078{
1079 u32 ctrl1;
1080
1081 pipe_config->ddi_pll_sel = SKL_DPLL0;
1082 pipe_config->dpll_hw_state.cfgcr1 = 0;
1083 pipe_config->dpll_hw_state.cfgcr2 = 0;
1084
1085 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1086 switch (link_bw) {
1087 case DP_LINK_BW_1_62:
1088 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
1089 SKL_DPLL0);
1090 break;
1091 case DP_LINK_BW_2_7:
1092 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
1093 SKL_DPLL0);
1094 break;
1095 case DP_LINK_BW_5_4:
1096 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
1097 SKL_DPLL0);
1098 break;
1099 }
1100 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1101}
1102
0e50338c
DV		 1103static void
1104hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1105{
1106 switch (link_bw) {
1107 case DP_LINK_BW_1_62:
1108 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1109 break;
1110 case DP_LINK_BW_2_7:
1111 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1112 break;
1113 case DP_LINK_BW_5_4:
1114 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1115 break;
1116 }
1117}
1118
c6bb3538
DV		 1119static void
1120intel_dp_set_clock(struct intel_encoder *encoder,
1121 struct intel_crtc_config *pipe_config, int link_bw)
1122{
1123 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1124 const struct dp_link_dpll *divisor = NULL;
1125 int i, count = 0;
c6bb3538
DV		 1126
1127 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1128 divisor = gen4_dpll;
1129 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1130 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1131 divisor = pch_dpll;
1132 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1133 } else if (IS_CHERRYVIEW(dev)) {
1134 divisor = chv_dpll;
1135 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1136 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1137 divisor = vlv_dpll;
1138 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1139 }
9dd4ffdf
CML		 1140
1141 if (divisor && count) {
1142 for (i = 0; i < count; i++) {
1143 if (link_bw == divisor[i].link_bw) {
1144 pipe_config->dpll = divisor[i].dpll;
1145 pipe_config->clock_set = true;
1146 break;
1147 }
1148 }
c6bb3538
DV		 1149 }
1150}
1151
00c09d70 1152bool
5bfe2ac0
DV		 1153intel_dp_compute_config(struct intel_encoder *encoder,
1154 struct intel_crtc_config *pipe_config)
a4fc5ed6 1155{
5bfe2ac0 1156 struct drm_device *dev = encoder->base.dev;
36008365 1157 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1158 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1159 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1160 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1161 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1162 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1163 int lane_count, clock;
56071a20 1164 int min_lane_count = 1;
eeb6324d 1165 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1166 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1167 int min_clock = 0;
06ea66b6 1168 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1169 int bpp, mode_rate;
06ea66b6 1170 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1171 int link_avail, link_clock;
a4fc5ed6 1172
bc7d38a4 1173 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1174 pipe_config->has_pch_encoder = true;
1175
03afc4a2 1176 pipe_config->has_dp_encoder = true;
f769cd24 1177 pipe_config->has_drrs = false;
9ed109a7 1178 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1179
dd06f90e
JN		 1180 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1181 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1182 adjusted_mode);
2dd24552
JB		 1183 if (!HAS_PCH_SPLIT(dev))
1184 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1185 intel_connector->panel.fitting_mode);
1186 else
b074cec8
JB		 1187 intel_pch_panel_fitting(intel_crtc, pipe_config,
1188 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1189 }
1190
cb1793ce 1191 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1192 return false;
1193
083f9560
DV		 1194 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1195 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1196 max_lane_count, bws[max_clock],
1197 adjusted_mode->crtc_clock);
083f9560 1198
36008365
DV		 1199 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1200 * bpc in between. */
3e7ca985 1201 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1202 if (is_edp(intel_dp)) {
1203 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1204 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1205 dev_priv->vbt.edp_bpp);
1206 bpp = dev_priv->vbt.edp_bpp;
1207 }
1208
344c5bbc
JN		 1209 /*
1210 * Use the maximum clock and number of lanes the eDP panel
1211 * advertizes being capable of. The panels are generally
1212 * designed to support only a single clock and lane
1213 * configuration, and typically these values correspond to the
1214 * native resolution of the panel.
1215 */
1216 min_lane_count = max_lane_count;
1217 min_clock = max_clock;
7984211e 1218 }
657445fe 1219
36008365 1220 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1221 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1222 bpp);
36008365 1223
c6930992
DA		 1224 for (clock = min_clock; clock <= max_clock; clock++) {
1225 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1226 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1227 link_avail = intel_dp_max_data_rate(link_clock,
1228 lane_count);
1229
1230 if (mode_rate <= link_avail) {
1231 goto found;
1232 }
1233 }
1234 }
1235 }
c4867936 1236
36008365 1237 return false;
3685a8f3 1238
36008365 1239found:
55bc60db
VS		 1240 if (intel_dp->color_range_auto) {
1241 /*
1242 * See:
1243 * CEA-861-E - 5.1 Default Encoding Parameters
1244 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1245 */
18316c8c 1246 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1247 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1248 else
1249 intel_dp->color_range = 0;
1250 }
1251
3685a8f3 1252 if (intel_dp->color_range)
50f3b016 1253 pipe_config->limited_color_range = true;
a4fc5ed6 1254
36008365
DV		 1255 intel_dp->link_bw = bws[clock];
1256 intel_dp->lane_count = lane_count;
657445fe 1257 pipe_config->pipe_bpp = bpp;
ff9a6750 1258 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1259
36008365
DV		 1260 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1261 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1262 pipe_config->port_clock, bpp);
36008365
DV		 1263 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1264 mode_rate, link_avail);
a4fc5ed6 1265
03afc4a2 1266 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1267 adjusted_mode->crtc_clock,
1268 pipe_config->port_clock,
03afc4a2 1269 &pipe_config->dp_m_n);
9d1a455b 1270
439d7ac0
PB		 1271 if (intel_connector->panel.downclock_mode != NULL &&
1272 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1273 pipe_config->has_drrs = true;
439d7ac0
PB		 1274 intel_link_compute_m_n(bpp, lane_count,
1275 intel_connector->panel.downclock_mode->clock,
1276 pipe_config->port_clock,
1277 &pipe_config->dp_m2_n2);
1278 }
1279
5416d871
DL		 1280 if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1281 skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
1282 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1283 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1284 else
1285 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1286
03afc4a2 1287 return true;
a4fc5ed6
KP		 1288}
1289
7c62a164 1290static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1291{
7c62a164
DV		 1292 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1293 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1294 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1295 struct drm_i915_private *dev_priv = dev->dev_private;
1296 u32 dpa_ctl;
1297
ff9a6750 1298 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1299 dpa_ctl = I915_READ(DP_A);
1300 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1301
ff9a6750 1302 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1303 /* For a long time we've carried around a ILK-DevA w/a for the
1304 * 160MHz clock. If we're really unlucky, it's still required.
1305 */
1306 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1307 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1308 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1309 } else {
1310 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1311 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1312 }
1ce17038 1313
ea9b6006
DV		 1314 I915_WRITE(DP_A, dpa_ctl);
1315
1316 POSTING_READ(DP_A);
1317 udelay(500);
1318}
1319
8ac33ed3 1320static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1321{
b934223d 1322 struct drm_device *dev = encoder->base.dev;
417e822d 1323 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1324 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1325 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1326 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1327 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1328
417e822d 1329 /*
1a2eb460 1330 * There are four kinds of DP registers:
417e822d
KP		 1331 *
1332 * IBX PCH
1a2eb460
KP		 1333 * SNB CPU
1334 * IVB CPU
417e822d
KP		 1335 * CPT PCH
1336 *
1337 * IBX PCH and CPU are the same for almost everything,
1338 * except that the CPU DP PLL is configured in this
1339 * register
1340 *
1341 * CPT PCH is quite different, having many bits moved
1342 * to the TRANS_DP_CTL register instead. That
1343 * configuration happens (oddly) in ironlake_pch_enable
1344 */
9c9e7927 1345
417e822d
KP		 1346 /* Preserve the BIOS-computed detected bit. This is
1347 * supposed to be read-only.
1348 */
1349 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1350
417e822d 1351 /* Handle DP bits in common between all three register formats */
417e822d 1352 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1353 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1354
c1dec79a 1355 if (crtc->config.has_audio)
ea5b213a 1356 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
247d89f6 1357
417e822d 1358 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1359
bc7d38a4 1360 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1361 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1362 intel_dp->DP |= DP_SYNC_HS_HIGH;
1363 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1364 intel_dp->DP |= DP_SYNC_VS_HIGH;
1365 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1366
6aba5b6c 1367 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1368 intel_dp->DP |= DP_ENHANCED_FRAMING;
1369
7c62a164 1370 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1371 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1372 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1373 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1374
1375 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1376 intel_dp->DP |= DP_SYNC_HS_HIGH;
1377 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1378 intel_dp->DP |= DP_SYNC_VS_HIGH;
1379 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1380
6aba5b6c 1381 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1382 intel_dp->DP |= DP_ENHANCED_FRAMING;
1383
44f37d1f
CML		 1384 if (!IS_CHERRYVIEW(dev)) {
1385 if (crtc->pipe == 1)
1386 intel_dp->DP |= DP_PIPEB_SELECT;
1387 } else {
1388 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1389 }
417e822d
KP		 1390 } else {
1391 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1392 }
a4fc5ed6
KP		 1393}
1394
ffd6749d
PZ		 1395#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1396#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1397
1a5ef5b7
PZ		 1398#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1399#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1400
ffd6749d
PZ		 1401#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1402#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1403
4be73780 1404static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1405 u32 mask,
1406 u32 value)
bd943159 1407{
30add22d 1408 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1409 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1410 u32 pp_stat_reg, pp_ctrl_reg;
1411
e39b999a
VS		 1412 lockdep_assert_held(&dev_priv->pps_mutex);
1413
bf13e81b
JN		 1414 pp_stat_reg = _pp_stat_reg(intel_dp);
1415 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1416
99ea7127 1417 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1418 mask, value,
1419 I915_READ(pp_stat_reg),
1420 I915_READ(pp_ctrl_reg));
32ce697c 1421
453c5420 1422 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1423 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1424 I915_READ(pp_stat_reg),
1425 I915_READ(pp_ctrl_reg));
32ce697c 1426 }
54c136d4
CW		 1427
1428 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1429}
32ce697c 1430
4be73780 1431static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1432{
1433 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1434 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1435}
1436
4be73780 1437static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1438{
1439 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1440 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1441}
1442
4be73780 1443static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1444{
1445 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1446
1447 /* When we disable the VDD override bit last we have to do the manual
1448 * wait. */
1449 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1450 intel_dp->panel_power_cycle_delay);
1451
4be73780 1452 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1453}
1454
4be73780 1455static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1456{
1457 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1458 intel_dp->backlight_on_delay);
1459}
1460
4be73780 1461static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1462{
1463 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1464 intel_dp->backlight_off_delay);
1465}
99ea7127 1466
832dd3c1
KP		 1467/* Read the current pp_control value, unlocking the register if it
1468 * is locked
1469 */
1470
453c5420 1471static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1472{
453c5420
JB		 1473 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1474 struct drm_i915_private *dev_priv = dev->dev_private;
1475 u32 control;
832dd3c1 1476
e39b999a
VS		 1477 lockdep_assert_held(&dev_priv->pps_mutex);
1478
bf13e81b 1479 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1480 control &= ~PANEL_UNLOCK_MASK;
1481 control |= PANEL_UNLOCK_REGS;
1482 return control;
bd943159
KP		 1483}
1484
951468f3
VS		 1485/*
1486 * Must be paired with edp_panel_vdd_off().
1487 * Must hold pps_mutex around the whole on/off sequence.
1488 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1489 */
1e0560e0 1490static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1491{
30add22d 1492 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1493 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1494 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1495 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1496 enum intel_display_power_domain power_domain;
5d613501 1497 u32 pp;
453c5420 1498 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1499 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1500
e39b999a
VS		 1501 lockdep_assert_held(&dev_priv->pps_mutex);
1502
97af61f5 1503 if (!is_edp(intel_dp))
adddaaf4 1504 return false;
bd943159
KP		 1505
1506 intel_dp->want_panel_vdd = true;
99ea7127 1507
4be73780 1508 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1509 return need_to_disable;
b0665d57 1510
4e6e1a54
ID		 1511 power_domain = intel_display_port_power_domain(intel_encoder);
1512 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1513
3936fcf4
VS		 1514 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1515 port_name(intel_dig_port->port));
bd943159 1516
4be73780
DV		 1517 if (!edp_have_panel_power(intel_dp))
1518 wait_panel_power_cycle(intel_dp);
99ea7127 1519
453c5420 1520 pp = ironlake_get_pp_control(intel_dp);
5d613501 1521 pp |= EDP_FORCE_VDD;
ebf33b18 1522
bf13e81b
JN		 1523 pp_stat_reg = _pp_stat_reg(intel_dp);
1524 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1525
1526 I915_WRITE(pp_ctrl_reg, pp);
1527 POSTING_READ(pp_ctrl_reg);
1528 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1529 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1530 /*
1531 * If the panel wasn't on, delay before accessing aux channel
1532 */
4be73780 1533 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1534 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1535 port_name(intel_dig_port->port));
f01eca2e 1536 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1537 }
adddaaf4
JN		 1538
1539 return need_to_disable;
1540}
1541
951468f3
VS		 1542/*
1543 * Must be paired with intel_edp_panel_vdd_off() or
1544 * intel_edp_panel_off().
1545 * Nested calls to these functions are not allowed since
1546 * we drop the lock. Caller must use some higher level
1547 * locking to prevent nested calls from other threads.
1548 */
b80d6c78 1549void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1550{
c695b6b6 1551 bool vdd;
adddaaf4 1552
c695b6b6
VS		 1553 if (!is_edp(intel_dp))
1554 return;
1555
773538e8 1556 pps_lock(intel_dp);
c695b6b6 1557 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1558 pps_unlock(intel_dp);
c695b6b6 1559
3936fcf4
VS		 1560 WARN(!vdd, "eDP port %c VDD already requested on\n",
1561 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1562}
1563
4be73780 1564static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1565{
30add22d 1566 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1567 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1568 struct intel_digital_port *intel_dig_port =
1569 dp_to_dig_port(intel_dp);
1570 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1571 enum intel_display_power_domain power_domain;
5d613501 1572 u32 pp;
453c5420 1573 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1574
e39b999a 1575 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1576
15e899a0 1577 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1578
15e899a0 1579 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1580 return;
b0665d57 1581
3936fcf4
VS		 1582 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1583 port_name(intel_dig_port->port));
bd943159 1584
be2c9196
VS		 1585 pp = ironlake_get_pp_control(intel_dp);
1586 pp &= ~EDP_FORCE_VDD;
453c5420 1587
be2c9196
VS		 1588 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1589 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1590
be2c9196
VS		 1591 I915_WRITE(pp_ctrl_reg, pp);
1592 POSTING_READ(pp_ctrl_reg);
90791a5c 1593
be2c9196
VS		 1594 /* Make sure sequencer is idle before allowing subsequent activity */
1595 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1596 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1597
be2c9196
VS		 1598 if ((pp & POWER_TARGET_ON) == 0)
1599 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1600
be2c9196
VS		 1601 power_domain = intel_display_port_power_domain(intel_encoder);
1602 intel_display_power_put(dev_priv, power_domain);
bd943159 1603}
5d613501 1604
4be73780 1605static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1606{
1607 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1608 struct intel_dp, panel_vdd_work);
bd943159 1609
773538e8 1610 pps_lock(intel_dp);
15e899a0
VS		 1611 if (!intel_dp->want_panel_vdd)
1612 edp_panel_vdd_off_sync(intel_dp);
773538e8 1613 pps_unlock(intel_dp);
bd943159
KP		 1614}
1615
aba86890
ID		 1616static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1617{
1618 unsigned long delay;
1619
1620 /*
1621 * Queue the timer to fire a long time from now (relative to the power
1622 * down delay) to keep the panel power up across a sequence of
1623 * operations.
1624 */
1625 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1626 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1627}
1628
951468f3
VS		 1629/*
1630 * Must be paired with edp_panel_vdd_on().
1631 * Must hold pps_mutex around the whole on/off sequence.
1632 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1633 */
4be73780 1634static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1635{
e39b999a
VS		 1636 struct drm_i915_private *dev_priv =
1637 intel_dp_to_dev(intel_dp)->dev_private;
1638
1639 lockdep_assert_held(&dev_priv->pps_mutex);
1640
97af61f5
KP		 1641 if (!is_edp(intel_dp))
1642 return;
5d613501 1643
3936fcf4
VS		 1644 WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1645 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1646
bd943159
KP		 1647 intel_dp->want_panel_vdd = false;
1648
aba86890 1649 if (sync)
4be73780 1650 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1651 else
1652 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1653}
1654
9f0fb5be 1655static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1656{
30add22d 1657 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1658 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1659 u32 pp;
453c5420 1660 u32 pp_ctrl_reg;
9934c132 1661
9f0fb5be
VS		 1662 lockdep_assert_held(&dev_priv->pps_mutex);
1663
97af61f5 1664 if (!is_edp(intel_dp))
bd943159 1665 return;
99ea7127 1666
3936fcf4
VS		 1667 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1668 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1669
e7a89ace
VS		 1670 if (WARN(edp_have_panel_power(intel_dp),
1671 "eDP port %c panel power already on\n",
1672 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1673 return;
9934c132 1674
4be73780 1675 wait_panel_power_cycle(intel_dp);
37c6c9b0 1676
bf13e81b 1677 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1678 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1679 if (IS_GEN5(dev)) {
1680 /* ILK workaround: disable reset around power sequence */
1681 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1682 I915_WRITE(pp_ctrl_reg, pp);
1683 POSTING_READ(pp_ctrl_reg);
05ce1a49 1684 }
37c6c9b0 1685
1c0ae80a 1686 pp |= POWER_TARGET_ON;
99ea7127
KP		 1687 if (!IS_GEN5(dev))
1688 pp |= PANEL_POWER_RESET;
1689
453c5420
JB		 1690 I915_WRITE(pp_ctrl_reg, pp);
1691 POSTING_READ(pp_ctrl_reg);
9934c132 1692
4be73780 1693 wait_panel_on(intel_dp);
dce56b3c 1694 intel_dp->last_power_on = jiffies;
9934c132 1695
05ce1a49
KP		 1696 if (IS_GEN5(dev)) {
1697 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1698 I915_WRITE(pp_ctrl_reg, pp);
1699 POSTING_READ(pp_ctrl_reg);
05ce1a49 1700 }
9f0fb5be 1701}
e39b999a 1702
9f0fb5be
VS		 1703void intel_edp_panel_on(struct intel_dp *intel_dp)
1704{
1705 if (!is_edp(intel_dp))
1706 return;
1707
1708 pps_lock(intel_dp);
1709 edp_panel_on(intel_dp);
773538e8 1710 pps_unlock(intel_dp);
9934c132
JB		 1711}
1712
9f0fb5be
VS		 1713
1714static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1715{
4e6e1a54
ID		 1716 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1717 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1718 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1719 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1720 enum intel_display_power_domain power_domain;
99ea7127 1721 u32 pp;
453c5420 1722 u32 pp_ctrl_reg;
9934c132 1723
9f0fb5be
VS		 1724 lockdep_assert_held(&dev_priv->pps_mutex);
1725
97af61f5
KP		 1726 if (!is_edp(intel_dp))
1727 return;
37c6c9b0 1728
3936fcf4
VS		 1729 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1730 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 1731
3936fcf4
VS		 1732 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1733 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 1734
453c5420 1735 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1736 /* We need to switch off panel power _and_ force vdd, for otherwise some
1737 * panels get very unhappy and cease to work. */
b3064154
PJ		 1738 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1739 EDP_BLC_ENABLE);
453c5420 1740
bf13e81b 1741 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1742
849e39f5
PZ		 1743 intel_dp->want_panel_vdd = false;
1744
453c5420
JB		 1745 I915_WRITE(pp_ctrl_reg, pp);
1746 POSTING_READ(pp_ctrl_reg);
9934c132 1747
dce56b3c 1748 intel_dp->last_power_cycle = jiffies;
4be73780 1749 wait_panel_off(intel_dp);
849e39f5
PZ		 1750
1751 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1752 power_domain = intel_display_port_power_domain(intel_encoder);
1753 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1754}
e39b999a 1755
9f0fb5be
VS		 1756void intel_edp_panel_off(struct intel_dp *intel_dp)
1757{
1758 if (!is_edp(intel_dp))
1759 return;
e39b999a 1760
9f0fb5be
VS		 1761 pps_lock(intel_dp);
1762 edp_panel_off(intel_dp);
773538e8 1763 pps_unlock(intel_dp);
9934c132
JB		 1764}
1765
1250d107
JN		 1766/* Enable backlight in the panel power control. */
1767static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1768{
da63a9f2
PZ		 1769 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1770 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 u32 pp;
453c5420 1773 u32 pp_ctrl_reg;
32f9d658 1774
01cb9ea6
JB		 1775 /*
1776 * If we enable the backlight right away following a panel power
1777 * on, we may see slight flicker as the panel syncs with the eDP
1778 * link. So delay a bit to make sure the image is solid before
1779 * allowing it to appear.
1780 */
4be73780 1781 wait_backlight_on(intel_dp);
e39b999a 1782
773538e8 1783 pps_lock(intel_dp);
e39b999a 1784
453c5420 1785 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1786 pp |= EDP_BLC_ENABLE;
453c5420 1787
bf13e81b 1788 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1789
1790 I915_WRITE(pp_ctrl_reg, pp);
1791 POSTING_READ(pp_ctrl_reg);
e39b999a 1792
773538e8 1793 pps_unlock(intel_dp);
32f9d658
ZW		 1794}
1795
1250d107
JN		 1796/* Enable backlight PWM and backlight PP control. */
1797void intel_edp_backlight_on(struct intel_dp *intel_dp)
1798{
1799 if (!is_edp(intel_dp))
1800 return;
1801
1802 DRM_DEBUG_KMS("\n");
1803
1804 intel_panel_enable_backlight(intel_dp->attached_connector);
1805 _intel_edp_backlight_on(intel_dp);
1806}
1807
1808/* Disable backlight in the panel power control. */
1809static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1810{
30add22d 1811 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1812 struct drm_i915_private *dev_priv = dev->dev_private;
1813 u32 pp;
453c5420 1814 u32 pp_ctrl_reg;
32f9d658 1815
f01eca2e
KP		 1816 if (!is_edp(intel_dp))
1817 return;
1818
773538e8 1819 pps_lock(intel_dp);
e39b999a 1820
453c5420 1821 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1822 pp &= ~EDP_BLC_ENABLE;
453c5420 1823
bf13e81b 1824 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1825
1826 I915_WRITE(pp_ctrl_reg, pp);
1827 POSTING_READ(pp_ctrl_reg);
f7d2323c 1828
773538e8 1829 pps_unlock(intel_dp);
e39b999a
VS		 1830
1831 intel_dp->last_backlight_off = jiffies;
f7d2323c 1832 edp_wait_backlight_off(intel_dp);
1250d107 1833}
f7d2323c 1834
1250d107
JN		 1835/* Disable backlight PP control and backlight PWM. */
1836void intel_edp_backlight_off(struct intel_dp *intel_dp)
1837{
1838 if (!is_edp(intel_dp))
1839 return;
1840
1841 DRM_DEBUG_KMS("\n");
f7d2323c 1842
1250d107 1843 _intel_edp_backlight_off(intel_dp);
f7d2323c 1844 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1845}
a4fc5ed6 1846
73580fb7
JN		 1847/*
1848 * Hook for controlling the panel power control backlight through the bl_power
1849 * sysfs attribute. Take care to handle multiple calls.
1850 */
1851static void intel_edp_backlight_power(struct intel_connector *connector,
1852 bool enable)
1853{
1854 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1855 bool is_enabled;
1856
773538e8 1857 pps_lock(intel_dp);
e39b999a 1858 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1859 pps_unlock(intel_dp);
73580fb7
JN		 1860
1861 if (is_enabled == enable)
1862 return;
1863
23ba9373
JN		 1864 DRM_DEBUG_KMS("panel power control backlight %s\n",
1865 enable ? "enable" : "disable");
73580fb7
JN		 1866
1867 if (enable)
1868 _intel_edp_backlight_on(intel_dp);
1869 else
1870 _intel_edp_backlight_off(intel_dp);
1871}
1872
2bd2ad64 1873static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1874{
da63a9f2
PZ		 1875 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1876 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1877 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 u32 dpa_ctl;
1880
2bd2ad64
DV		 1881 assert_pipe_disabled(dev_priv,
1882 to_intel_crtc(crtc)->pipe);
1883
d240f20f
JB		 1884 DRM_DEBUG_KMS("\n");
1885 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1886 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1887 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1888
1889 /* We don't adjust intel_dp->DP while tearing down the link, to
1890 * facilitate link retraining (e.g. after hotplug). Hence clear all
1891 * enable bits here to ensure that we don't enable too much. */
1892 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1893 intel_dp->DP |= DP_PLL_ENABLE;
1894 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1895 POSTING_READ(DP_A);
1896 udelay(200);
d240f20f
JB		 1897}
1898
2bd2ad64 1899static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1900{
da63a9f2
PZ		 1901 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1902 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1903 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1904 struct drm_i915_private *dev_priv = dev->dev_private;
1905 u32 dpa_ctl;
1906
2bd2ad64
DV		 1907 assert_pipe_disabled(dev_priv,
1908 to_intel_crtc(crtc)->pipe);
1909
d240f20f 1910 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1911 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1912 "dp pll off, should be on\n");
1913 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1914
1915 /* We can't rely on the value tracked for the DP register in
1916 * intel_dp->DP because link_down must not change that (otherwise link
1917 * re-training will fail. */
298b0b39 1918 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1919 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1920 POSTING_READ(DP_A);
d240f20f
JB		 1921 udelay(200);
1922}
1923
c7ad3810 1924/* If the sink supports it, try to set the power state appropriately */
c19b0669 1925void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1926{
1927 int ret, i;
1928
1929 /* Should have a valid DPCD by this point */
1930 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1931 return;
1932
1933 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1934 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1935 DP_SET_POWER_D3);
c7ad3810
JB		 1936 } else {
1937 /*
1938 * When turning on, we need to retry for 1ms to give the sink
1939 * time to wake up.
1940 */
1941 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1942 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1943 DP_SET_POWER_D0);
c7ad3810
JB		 1944 if (ret == 1)
1945 break;
1946 msleep(1);
1947 }
1948 }
f9cac721
JN		 1949
1950 if (ret != 1)
1951 DRM_DEBUG_KMS("failed to %s sink power state\n",
1952 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1953}
1954
19d8fe15
DV		 1955static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1956 enum pipe *pipe)
d240f20f 1957{
19d8fe15 1958 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1959 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1960 struct drm_device *dev = encoder->base.dev;
1961 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1962 enum intel_display_power_domain power_domain;
1963 u32 tmp;
1964
1965 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1966 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1967 return false;
1968
1969 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1970
1971 if (!(tmp & DP_PORT_EN))
1972 return false;
1973
bc7d38a4 1974 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1975 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1976 } else if (IS_CHERRYVIEW(dev)) {
1977 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1978 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1979 *pipe = PORT_TO_PIPE(tmp);
1980 } else {
1981 u32 trans_sel;
1982 u32 trans_dp;
1983 int i;
1984
1985 switch (intel_dp->output_reg) {
1986 case PCH_DP_B:
1987 trans_sel = TRANS_DP_PORT_SEL_B;
1988 break;
1989 case PCH_DP_C:
1990 trans_sel = TRANS_DP_PORT_SEL_C;
1991 break;
1992 case PCH_DP_D:
1993 trans_sel = TRANS_DP_PORT_SEL_D;
1994 break;
1995 default:
1996 return true;
1997 }
1998
055e393f 1999 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 2000 trans_dp = I915_READ(TRANS_DP_CTL(i));
2001 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
2002 *pipe = i;
2003 return true;
2004 }
2005 }
19d8fe15 2006
4a0833ec
DV		 2007 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2008 intel_dp->output_reg);
2009 }
d240f20f 2010
19d8fe15
DV		 2011 return true;
2012}
d240f20f 2013
045ac3b5
JB		 2014static void intel_dp_get_config(struct intel_encoder *encoder,
2015 struct intel_crtc_config *pipe_config)
2016{
2017 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2018 u32 tmp, flags = 0;
63000ef6
XZ		 2019 struct drm_device *dev = encoder->base.dev;
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021 enum port port = dp_to_dig_port(intel_dp)->port;
2022 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 2023 int dotclock;
045ac3b5 2024
9ed109a7
DV		 2025 tmp = I915_READ(intel_dp->output_reg);
2026 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2027 pipe_config->has_audio = true;
2028
63000ef6 2029 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 2030 if (tmp & DP_SYNC_HS_HIGH)
2031 flags |= DRM_MODE_FLAG_PHSYNC;
2032 else
2033 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2034
63000ef6
XZ		 2035 if (tmp & DP_SYNC_VS_HIGH)
2036 flags |= DRM_MODE_FLAG_PVSYNC;
2037 else
2038 flags |= DRM_MODE_FLAG_NVSYNC;
2039 } else {
2040 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2041 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2042 flags |= DRM_MODE_FLAG_PHSYNC;
2043 else
2044 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2045
63000ef6
XZ		 2046 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2047 flags |= DRM_MODE_FLAG_PVSYNC;
2048 else
2049 flags |= DRM_MODE_FLAG_NVSYNC;
2050 }
045ac3b5
JB		 2051
2052 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 2053
8c875fca
VS		 2054 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2055 tmp & DP_COLOR_RANGE_16_235)
2056 pipe_config->limited_color_range = true;
2057
eb14cb74
VS		 2058 pipe_config->has_dp_encoder = true;
2059
2060 intel_dp_get_m_n(crtc, pipe_config);
2061
18442d08 2062 if (port == PORT_A) {
f1f644dc
JB		 2063 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2064 pipe_config->port_clock = 162000;
2065 else
2066 pipe_config->port_clock = 270000;
2067 }
18442d08
VS		 2068
2069 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2070 &pipe_config->dp_m_n);
2071
2072 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2073 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2074
241bfc38 2075 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2076
c6cd2ee2
JN		 2077 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2078 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2079 /*
2080 * This is a big fat ugly hack.
2081 *
2082 * Some machines in UEFI boot mode provide us a VBT that has 18
2083 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2084 * unknown we fail to light up. Yet the same BIOS boots up with
2085 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2086 * max, not what it tells us to use.
2087 *
2088 * Note: This will still be broken if the eDP panel is not lit
2089 * up by the BIOS, and thus we can't get the mode at module
2090 * load.
2091 */
2092 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2093 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2094 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2095 }
045ac3b5
JB		 2096}
2097
e8cb4558 2098static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2099{
e8cb4558 2100 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2101 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2102 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2103
2104 if (crtc->config.has_audio)
2105 intel_audio_codec_disable(encoder);
6cb49835
DV		 2106
2107 /* Make sure the panel is off before trying to change the mode. But also
2108 * ensure that we have vdd while we switch off the panel. */
24f3e092 2109 intel_edp_panel_vdd_on(intel_dp);
4be73780 2110 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2111 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2112 intel_edp_panel_off(intel_dp);
3739850b 2113
08aff3fe
VS		 2114 /* disable the port before the pipe on g4x */
2115 if (INTEL_INFO(dev)->gen < 5)
3739850b 2116 intel_dp_link_down(intel_dp);
d240f20f
JB		 2117}
2118
08aff3fe 2119static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2120{
2bd2ad64 2121 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2122 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2123
49277c31 2124 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2125 if (port == PORT_A)
2126 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2127}
2128
2129static void vlv_post_disable_dp(struct intel_encoder *encoder)
2130{
2131 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2132
2133 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2134}
2135
580d3811
VS		 2136static void chv_post_disable_dp(struct intel_encoder *encoder)
2137{
2138 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2139 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2140 struct drm_device *dev = encoder->base.dev;
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2142 struct intel_crtc *intel_crtc =
2143 to_intel_crtc(encoder->base.crtc);
2144 enum dpio_channel ch = vlv_dport_to_channel(dport);
2145 enum pipe pipe = intel_crtc->pipe;
2146 u32 val;
2147
2148 intel_dp_link_down(intel_dp);
2149
2150 mutex_lock(&dev_priv->dpio_lock);
2151
2152 /* Propagate soft reset to data lane reset */
97fd4d5c 2153 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2154 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2155 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2156
97fd4d5c
VS		 2157 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2158 val |= CHV_PCS_REQ_SOFTRESET_EN;
2159 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2160
2161 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2162 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2163 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2164
2165 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2166 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2167 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2168
2169 mutex_unlock(&dev_priv->dpio_lock);
2170}
2171
7b13b58a
VS		 2172static void
2173_intel_dp_set_link_train(struct intel_dp *intel_dp,
2174 uint32_t *DP,
2175 uint8_t dp_train_pat)
2176{
2177 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2178 struct drm_device *dev = intel_dig_port->base.base.dev;
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 enum port port = intel_dig_port->port;
2181
2182 if (HAS_DDI(dev)) {
2183 uint32_t temp = I915_READ(DP_TP_CTL(port));
2184
2185 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2186 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2187 else
2188 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2189
2190 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2191 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2192 case DP_TRAINING_PATTERN_DISABLE:
2193 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2194
2195 break;
2196 case DP_TRAINING_PATTERN_1:
2197 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2198 break;
2199 case DP_TRAINING_PATTERN_2:
2200 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2201 break;
2202 case DP_TRAINING_PATTERN_3:
2203 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2204 break;
2205 }
2206 I915_WRITE(DP_TP_CTL(port), temp);
2207
2208 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2209 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2210
2211 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2212 case DP_TRAINING_PATTERN_DISABLE:
2213 *DP |= DP_LINK_TRAIN_OFF_CPT;
2214 break;
2215 case DP_TRAINING_PATTERN_1:
2216 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2217 break;
2218 case DP_TRAINING_PATTERN_2:
2219 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2220 break;
2221 case DP_TRAINING_PATTERN_3:
2222 DRM_ERROR("DP training pattern 3 not supported\n");
2223 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2224 break;
2225 }
2226
2227 } else {
2228 if (IS_CHERRYVIEW(dev))
2229 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2230 else
2231 *DP &= ~DP_LINK_TRAIN_MASK;
2232
2233 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2234 case DP_TRAINING_PATTERN_DISABLE:
2235 *DP |= DP_LINK_TRAIN_OFF;
2236 break;
2237 case DP_TRAINING_PATTERN_1:
2238 *DP |= DP_LINK_TRAIN_PAT_1;
2239 break;
2240 case DP_TRAINING_PATTERN_2:
2241 *DP |= DP_LINK_TRAIN_PAT_2;
2242 break;
2243 case DP_TRAINING_PATTERN_3:
2244 if (IS_CHERRYVIEW(dev)) {
2245 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2246 } else {
2247 DRM_ERROR("DP training pattern 3 not supported\n");
2248 *DP |= DP_LINK_TRAIN_PAT_2;
2249 }
2250 break;
2251 }
2252 }
2253}
2254
2255static void intel_dp_enable_port(struct intel_dp *intel_dp)
2256{
2257 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2258 struct drm_i915_private *dev_priv = dev->dev_private;
2259
7b13b58a
VS		 2260 /* enable with pattern 1 (as per spec) */
2261 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2262 DP_TRAINING_PATTERN_1);
2263
2264 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2265 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2266
2267 /*
2268 * Magic for VLV/CHV. We _must_ first set up the register
2269 * without actually enabling the port, and then do another
2270 * write to enable the port. Otherwise link training will
2271 * fail when the power sequencer is freshly used for this port.
2272 */
2273 intel_dp->DP |= DP_PORT_EN;
2274
2275 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2276 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2277}
2278
e8cb4558 2279static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2280{
e8cb4558
DV		 2281 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2282 struct drm_device *dev = encoder->base.dev;
2283 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2284 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2285 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2286
0c33d8d7
DV		 2287 if (WARN_ON(dp_reg & DP_PORT_EN))
2288 return;
5d613501 2289
093e3f13
VS		 2290 pps_lock(intel_dp);
2291
2292 if (IS_VALLEYVIEW(dev))
2293 vlv_init_panel_power_sequencer(intel_dp);
2294
7b13b58a 2295 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2296
2297 edp_panel_vdd_on(intel_dp);
2298 edp_panel_on(intel_dp);
2299 edp_panel_vdd_off(intel_dp, true);
2300
2301 pps_unlock(intel_dp);
2302
61234fa5
VS		 2303 if (IS_VALLEYVIEW(dev))
2304 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2305
f01eca2e 2306 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2307 intel_dp_start_link_train(intel_dp);
33a34e4e 2308 intel_dp_complete_link_train(intel_dp);
3ab9c637 2309 intel_dp_stop_link_train(intel_dp);
c1dec79a
JN		 2310
2311 if (crtc->config.has_audio) {
2312 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2313 pipe_name(crtc->pipe));
2314 intel_audio_codec_enable(encoder);
2315 }
ab1f90f9 2316}
89b667f8 2317
ecff4f3b
JN		 2318static void g4x_enable_dp(struct intel_encoder *encoder)
2319{
828f5c6e
JN		 2320 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2321
ecff4f3b 2322 intel_enable_dp(encoder);
4be73780 2323 intel_edp_backlight_on(intel_dp);
ab1f90f9 2324}
89b667f8 2325
ab1f90f9
JN		 2326static void vlv_enable_dp(struct intel_encoder *encoder)
2327{
828f5c6e
JN		 2328 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2329
4be73780 2330 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2331}
2332
ecff4f3b 2333static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2334{
2335 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2336 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2337
8ac33ed3
DV		 2338 intel_dp_prepare(encoder);
2339
d41f1efb
DV		 2340 /* Only ilk+ has port A */
2341 if (dport->port == PORT_A) {
2342 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2343 ironlake_edp_pll_on(intel_dp);
d41f1efb 2344 }
ab1f90f9
JN		 2345}
2346
83b84597
VS		 2347static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2348{
2349 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2350 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2351 enum pipe pipe = intel_dp->pps_pipe;
2352 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2353
2354 edp_panel_vdd_off_sync(intel_dp);
2355
2356 /*
2357 * VLV seems to get confused when multiple power seqeuencers
2358 * have the same port selected (even if only one has power/vdd
2359 * enabled). The failure manifests as vlv_wait_port_ready() failing
2360 * CHV on the other hand doesn't seem to mind having the same port
2361 * selected in multiple power seqeuencers, but let's clear the
2362 * port select always when logically disconnecting a power sequencer
2363 * from a port.
2364 */
2365 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2366 pipe_name(pipe), port_name(intel_dig_port->port));
2367 I915_WRITE(pp_on_reg, 0);
2368 POSTING_READ(pp_on_reg);
2369
2370 intel_dp->pps_pipe = INVALID_PIPE;
2371}
2372
a4a5d2f8
VS		 2373static void vlv_steal_power_sequencer(struct drm_device *dev,
2374 enum pipe pipe)
2375{
2376 struct drm_i915_private *dev_priv = dev->dev_private;
2377 struct intel_encoder *encoder;
2378
2379 lockdep_assert_held(&dev_priv->pps_mutex);
2380
ac3c12e4
VS		 2381 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2382 return;
2383
a4a5d2f8
VS		 2384 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2385 base.head) {
2386 struct intel_dp *intel_dp;
773538e8 2387 enum port port;
a4a5d2f8
VS		 2388
2389 if (encoder->type != INTEL_OUTPUT_EDP)
2390 continue;
2391
2392 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2393 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2394
2395 if (intel_dp->pps_pipe != pipe)
2396 continue;
2397
2398 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2399 pipe_name(pipe), port_name(port));
a4a5d2f8 2400
034e43c6
VS		 2401 WARN(encoder->connectors_active,
2402 "stealing pipe %c power sequencer from active eDP port %c\n",
2403 pipe_name(pipe), port_name(port));
a4a5d2f8 2404
a4a5d2f8 2405 /* make sure vdd is off before we steal it */
83b84597 2406 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2407 }
2408}
2409
2410static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2411{
2412 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2413 struct intel_encoder *encoder = &intel_dig_port->base;
2414 struct drm_device *dev = encoder->base.dev;
2415 struct drm_i915_private *dev_priv = dev->dev_private;
2416 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2417
2418 lockdep_assert_held(&dev_priv->pps_mutex);
2419
093e3f13
VS		 2420 if (!is_edp(intel_dp))
2421 return;
2422
a4a5d2f8
VS		 2423 if (intel_dp->pps_pipe == crtc->pipe)
2424 return;
2425
2426 /*
2427 * If another power sequencer was being used on this
2428 * port previously make sure to turn off vdd there while
2429 * we still have control of it.
2430 */
2431 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2432 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2433
2434 /*
2435 * We may be stealing the power
2436 * sequencer from another port.
2437 */
2438 vlv_steal_power_sequencer(dev, crtc->pipe);
2439
2440 /* now it's all ours */
2441 intel_dp->pps_pipe = crtc->pipe;
2442
2443 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2444 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2445
2446 /* init power sequencer on this pipe and port */
36b5f425
VS		 2447 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2448 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2449}
2450
ab1f90f9 2451static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2452{
2bd2ad64 2453 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2454 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2455 struct drm_device *dev = encoder->base.dev;
89b667f8 2456 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2457 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2458 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2459 int pipe = intel_crtc->pipe;
2460 u32 val;
a4fc5ed6 2461
ab1f90f9 2462 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2463
ab3c759a 2464 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2465 val = 0;
2466 if (pipe)
2467 val |= (1<<21);
2468 else
2469 val &= ~(1<<21);
2470 val |= 0x001000c4;
ab3c759a
CML		 2471 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2472 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2473 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2474
ab1f90f9
JN		 2475 mutex_unlock(&dev_priv->dpio_lock);
2476
2477 intel_enable_dp(encoder);
89b667f8
JB		 2478}
2479
ecff4f3b 2480static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2481{
2482 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2483 struct drm_device *dev = encoder->base.dev;
2484 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2485 struct intel_crtc *intel_crtc =
2486 to_intel_crtc(encoder->base.crtc);
e4607fcf 2487 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2488 int pipe = intel_crtc->pipe;
89b667f8 2489
8ac33ed3
DV		 2490 intel_dp_prepare(encoder);
2491
89b667f8 2492 /* Program Tx lane resets to default */
0980a60f 2493 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2494 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2495 DPIO_PCS_TX_LANE2_RESET |
2496 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2497 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2498 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2499 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2500 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2501 DPIO_PCS_CLK_SOFT_RESET);
2502
2503 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2504 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2505 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2506 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2507 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2508}
2509
e4a1d846
CML		 2510static void chv_pre_enable_dp(struct intel_encoder *encoder)
2511{
2512 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2513 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2514 struct drm_device *dev = encoder->base.dev;
2515 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2516 struct intel_crtc *intel_crtc =
2517 to_intel_crtc(encoder->base.crtc);
2518 enum dpio_channel ch = vlv_dport_to_channel(dport);
2519 int pipe = intel_crtc->pipe;
2520 int data, i;
949c1d43 2521 u32 val;
e4a1d846 2522
e4a1d846 2523 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2524
570e2a74
VS		 2525 /* allow hardware to manage TX FIFO reset source */
2526 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2527 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2528 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2529
2530 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2531 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2532 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2533
949c1d43 2534 /* Deassert soft data lane reset*/
97fd4d5c 2535 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2536 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2537 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2538
2539 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2540 val |= CHV_PCS_REQ_SOFTRESET_EN;
2541 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2542
2543 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2544 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2545 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2546
97fd4d5c 2547 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2548 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2549 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2550
2551 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2552 for (i = 0; i < 4; i++) {
2553 /* Set the latency optimal bit */
2554 data = (i == 1) ? 0x0 : 0x6;
2555 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2556 data << DPIO_FRC_LATENCY_SHFIT);
2557
2558 /* Set the upar bit */
2559 data = (i == 1) ? 0x0 : 0x1;
2560 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2561 data << DPIO_UPAR_SHIFT);
2562 }
2563
2564 /* Data lane stagger programming */
2565 /* FIXME: Fix up value only after power analysis */
2566
2567 mutex_unlock(&dev_priv->dpio_lock);
2568
e4a1d846 2569 intel_enable_dp(encoder);
e4a1d846
CML		 2570}
2571
9197c88b
VS		 2572static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2573{
2574 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2575 struct drm_device *dev = encoder->base.dev;
2576 struct drm_i915_private *dev_priv = dev->dev_private;
2577 struct intel_crtc *intel_crtc =
2578 to_intel_crtc(encoder->base.crtc);
2579 enum dpio_channel ch = vlv_dport_to_channel(dport);
2580 enum pipe pipe = intel_crtc->pipe;
2581 u32 val;
2582
625695f8
VS		 2583 intel_dp_prepare(encoder);
2584
9197c88b
VS		 2585 mutex_lock(&dev_priv->dpio_lock);
2586
b9e5ac3c
VS		 2587 /* program left/right clock distribution */
2588 if (pipe != PIPE_B) {
2589 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2590 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2591 if (ch == DPIO_CH0)
2592 val |= CHV_BUFLEFTENA1_FORCE;
2593 if (ch == DPIO_CH1)
2594 val |= CHV_BUFRIGHTENA1_FORCE;
2595 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2596 } else {
2597 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2598 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2599 if (ch == DPIO_CH0)
2600 val |= CHV_BUFLEFTENA2_FORCE;
2601 if (ch == DPIO_CH1)
2602 val |= CHV_BUFRIGHTENA2_FORCE;
2603 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2604 }
2605
9197c88b
VS		 2606 /* program clock channel usage */
2607 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2608 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2609 if (pipe != PIPE_B)
2610 val &= ~CHV_PCS_USEDCLKCHANNEL;
2611 else
2612 val |= CHV_PCS_USEDCLKCHANNEL;
2613 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2614
2615 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2616 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2617 if (pipe != PIPE_B)
2618 val &= ~CHV_PCS_USEDCLKCHANNEL;
2619 else
2620 val |= CHV_PCS_USEDCLKCHANNEL;
2621 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2622
2623 /*
2624 * This a a bit weird since generally CL
2625 * matches the pipe, but here we need to
2626 * pick the CL based on the port.
2627 */
2628 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2629 if (pipe != PIPE_B)
2630 val &= ~CHV_CMN_USEDCLKCHANNEL;
2631 else
2632 val |= CHV_CMN_USEDCLKCHANNEL;
2633 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2634
2635 mutex_unlock(&dev_priv->dpio_lock);
2636}
2637
a4fc5ed6 2638/*
df0c237d
JB		 2639 * Native read with retry for link status and receiver capability reads for
2640 * cases where the sink may still be asleep.
9d1a1031
JN		 2641 *
2642 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2643 * supposed to retry 3 times per the spec.
a4fc5ed6 2644 */
9d1a1031
JN		 2645static ssize_t
2646intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2647 void *buffer, size_t size)
a4fc5ed6 2648{
9d1a1031
JN		 2649 ssize_t ret;
2650 int i;
61da5fab 2651
f6a19066
VS		 2652 /*
2653 * Sometime we just get the same incorrect byte repeated
2654 * over the entire buffer. Doing just one throw away read
2655 * initially seems to "solve" it.
2656 */
2657 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2658
61da5fab 2659 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2660 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2661 if (ret == size)
2662 return ret;
61da5fab
JB		 2663 msleep(1);
2664 }
a4fc5ed6 2665
9d1a1031 2666 return ret;
a4fc5ed6
KP		 2667}
2668
2669/*
2670 * Fetch AUX CH registers 0x202 - 0x207 which contain
2671 * link status information
2672 */
2673static bool
93f62dad 2674intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2675{
9d1a1031
JN		 2676 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2677 DP_LANE0_1_STATUS,
2678 link_status,
2679 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2680}
2681
1100244e 2682/* These are source-specific values. */
a4fc5ed6 2683static uint8_t
1a2eb460 2684intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2685{
30add22d 2686 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2687 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2688
5a9d1f1a
DL		 2689 if (INTEL_INFO(dev)->gen >= 9)
2690 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2691 else if (IS_VALLEYVIEW(dev))
bd60018a 2692 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2693 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2694 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2695 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2696 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2697 else
bd60018a 2698 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2699}
2700
2701static uint8_t
2702intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2703{
30add22d 2704 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2705 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2706
5a9d1f1a
DL		 2707 if (INTEL_INFO(dev)->gen >= 9) {
2708 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2709 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2710 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2711 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2712 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2713 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2714 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2715 default:
2716 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2717 }
2718 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2719 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2720 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2721 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2722 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2723 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2724 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2725 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2726 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2727 default:
bd60018a 2728 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2729 }
e2fa6fba
P		 2730 } else if (IS_VALLEYVIEW(dev)) {
2731 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2732 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2733 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2734 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2735 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2736 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2737 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2738 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2739 default:
bd60018a 2740 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2741 }
bc7d38a4 2742 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2743 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2744 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2745 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2746 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2747 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2748 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2749 default:
bd60018a 2750 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2751 }
2752 } else {
2753 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2754 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2755 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2756 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2757 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2758 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2759 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2760 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2761 default:
bd60018a 2762 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2763 }
a4fc5ed6
KP		 2764 }
2765}
2766
e2fa6fba
P		 2767static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2768{
2769 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2770 struct drm_i915_private *dev_priv = dev->dev_private;
2771 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2772 struct intel_crtc *intel_crtc =
2773 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2774 unsigned long demph_reg_value, preemph_reg_value,
2775 uniqtranscale_reg_value;
2776 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2777 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2778 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2779
2780 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2781 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2782 preemph_reg_value = 0x0004000;
2783 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2784 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2785 demph_reg_value = 0x2B405555;
2786 uniqtranscale_reg_value = 0x552AB83A;
2787 break;
bd60018a 2788 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2789 demph_reg_value = 0x2B404040;
2790 uniqtranscale_reg_value = 0x5548B83A;
2791 break;
bd60018a 2792 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2793 demph_reg_value = 0x2B245555;
2794 uniqtranscale_reg_value = 0x5560B83A;
2795 break;
bd60018a 2796 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2797 demph_reg_value = 0x2B405555;
2798 uniqtranscale_reg_value = 0x5598DA3A;
2799 break;
2800 default:
2801 return 0;
2802 }
2803 break;
bd60018a 2804 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2805 preemph_reg_value = 0x0002000;
2806 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2807 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2808 demph_reg_value = 0x2B404040;
2809 uniqtranscale_reg_value = 0x5552B83A;
2810 break;
bd60018a 2811 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2812 demph_reg_value = 0x2B404848;
2813 uniqtranscale_reg_value = 0x5580B83A;
2814 break;
bd60018a 2815 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2816 demph_reg_value = 0x2B404040;
2817 uniqtranscale_reg_value = 0x55ADDA3A;
2818 break;
2819 default:
2820 return 0;
2821 }
2822 break;
bd60018a 2823 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2824 preemph_reg_value = 0x0000000;
2825 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2826 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2827 demph_reg_value = 0x2B305555;
2828 uniqtranscale_reg_value = 0x5570B83A;
2829 break;
bd60018a 2830 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2831 demph_reg_value = 0x2B2B4040;
2832 uniqtranscale_reg_value = 0x55ADDA3A;
2833 break;
2834 default:
2835 return 0;
2836 }
2837 break;
bd60018a 2838 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 2839 preemph_reg_value = 0x0006000;
2840 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2841 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2842 demph_reg_value = 0x1B405555;
2843 uniqtranscale_reg_value = 0x55ADDA3A;
2844 break;
2845 default:
2846 return 0;
2847 }
2848 break;
2849 default:
2850 return 0;
2851 }
2852
0980a60f 2853 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2854 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2855 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2856 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2857 uniqtranscale_reg_value);
ab3c759a
CML		 2858 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2859 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2860 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2861 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2862 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2863
2864 return 0;
2865}
2866
e4a1d846
CML		 2867static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2868{
2869 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2870 struct drm_i915_private *dev_priv = dev->dev_private;
2871 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2872 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2873 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2874 uint8_t train_set = intel_dp->train_set[0];
2875 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2876 enum pipe pipe = intel_crtc->pipe;
2877 int i;
e4a1d846
CML		 2878
2879 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2880 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 2881 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2882 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2883 deemph_reg_value = 128;
2884 margin_reg_value = 52;
2885 break;
bd60018a 2886 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2887 deemph_reg_value = 128;
2888 margin_reg_value = 77;
2889 break;
bd60018a 2890 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2891 deemph_reg_value = 128;
2892 margin_reg_value = 102;
2893 break;
bd60018a 2894 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 2895 deemph_reg_value = 128;
2896 margin_reg_value = 154;
2897 /* FIXME extra to set for 1200 */
2898 break;
2899 default:
2900 return 0;
2901 }
2902 break;
bd60018a 2903 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 2904 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2905 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2906 deemph_reg_value = 85;
2907 margin_reg_value = 78;
2908 break;
bd60018a 2909 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2910 deemph_reg_value = 85;
2911 margin_reg_value = 116;
2912 break;
bd60018a 2913 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2914 deemph_reg_value = 85;
2915 margin_reg_value = 154;
2916 break;
2917 default:
2918 return 0;
2919 }
2920 break;
bd60018a 2921 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 2922 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2923 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2924 deemph_reg_value = 64;
2925 margin_reg_value = 104;
2926 break;
bd60018a 2927 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2928 deemph_reg_value = 64;
2929 margin_reg_value = 154;
2930 break;
2931 default:
2932 return 0;
2933 }
2934 break;
bd60018a 2935 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 2936 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2938 deemph_reg_value = 43;
2939 margin_reg_value = 154;
2940 break;
2941 default:
2942 return 0;
2943 }
2944 break;
2945 default:
2946 return 0;
2947 }
2948
2949 mutex_lock(&dev_priv->dpio_lock);
2950
2951 /* Clear calc init */
1966e59e
VS		 2952 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2953 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 2954 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2955 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 2956 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2957
2958 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2959 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 2960 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2961 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 2962 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 2963
a02ef3c7
VS		 2964 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
2965 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2966 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2967 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
2968
2969 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
2970 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2971 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2972 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
2973
e4a1d846 2974 /* Program swing deemph */
f72df8db
VS		 2975 for (i = 0; i < 4; i++) {
2976 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2977 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2978 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2979 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2980 }
e4a1d846
CML		 2981
2982 /* Program swing margin */
f72df8db
VS		 2983 for (i = 0; i < 4; i++) {
2984 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 2985 val &= ~DPIO_SWING_MARGIN000_MASK;
2986 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 2987 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2988 }
e4a1d846
CML		 2989
2990 /* Disable unique transition scale */
f72df8db
VS		 2991 for (i = 0; i < 4; i++) {
2992 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2993 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2994 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2995 }
e4a1d846
CML		 2996
2997 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 2998 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 2999 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3000 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3001
3002 /*
3003 * The document said it needs to set bit 27 for ch0 and bit 26
3004 * for ch1. Might be a typo in the doc.
3005 * For now, for this unique transition scale selection, set bit
3006 * 27 for ch0 and ch1.
3007 */
f72df8db
VS		 3008 for (i = 0; i < 4; i++) {
3009 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3010 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3011 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3012 }
e4a1d846 3013
f72df8db
VS		 3014 for (i = 0; i < 4; i++) {
3015 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3016 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3017 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3018 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3019 }
e4a1d846
CML		 3020 }
3021
3022 /* Start swing calculation */
1966e59e
VS		 3023 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3024 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3025 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3026
3027 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3028 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3029 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3030
3031 /* LRC Bypass */
3032 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3033 val |= DPIO_LRC_BYPASS;
3034 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3035
3036 mutex_unlock(&dev_priv->dpio_lock);
3037
3038 return 0;
3039}
3040
a4fc5ed6 3041static void
0301b3ac
JN		 3042intel_get_adjust_train(struct intel_dp *intel_dp,
3043 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3044{
3045 uint8_t v = 0;
3046 uint8_t p = 0;
3047 int lane;
1a2eb460
KP		 3048 uint8_t voltage_max;
3049 uint8_t preemph_max;
a4fc5ed6 3050
33a34e4e 3051 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3052 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3053 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3054
3055 if (this_v > v)
3056 v = this_v;
3057 if (this_p > p)
3058 p = this_p;
3059 }
3060
1a2eb460 3061 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3062 if (v >= voltage_max)
3063 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3064
1a2eb460
KP		 3065 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3066 if (p >= preemph_max)
3067 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3068
3069 for (lane = 0; lane < 4; lane++)
33a34e4e 3070 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3071}
3072
3073static uint32_t
f0a3424e 3074intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3075{
3cf2efb1 3076 uint32_t signal_levels = 0;
a4fc5ed6 3077
3cf2efb1 3078 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3079 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3080 default:
3081 signal_levels |= DP_VOLTAGE_0_4;
3082 break;
bd60018a 3083 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3084 signal_levels |= DP_VOLTAGE_0_6;
3085 break;
bd60018a 3086 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3087 signal_levels |= DP_VOLTAGE_0_8;
3088 break;
bd60018a 3089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3090 signal_levels |= DP_VOLTAGE_1_2;
3091 break;
3092 }
3cf2efb1 3093 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3094 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3095 default:
3096 signal_levels |= DP_PRE_EMPHASIS_0;
3097 break;
bd60018a 3098 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3099 signal_levels |= DP_PRE_EMPHASIS_3_5;
3100 break;
bd60018a 3101 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3102 signal_levels |= DP_PRE_EMPHASIS_6;
3103 break;
bd60018a 3104 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3105 signal_levels |= DP_PRE_EMPHASIS_9_5;
3106 break;
3107 }
3108 return signal_levels;
3109}
3110
e3421a18
ZW		 3111/* Gen6's DP voltage swing and pre-emphasis control */
3112static uint32_t
3113intel_gen6_edp_signal_levels(uint8_t train_set)
3114{
3c5a62b5
YL		 3115 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3116 DP_TRAIN_PRE_EMPHASIS_MASK);
3117 switch (signal_levels) {
bd60018a
SJ		 3118 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3119 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3120 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3121 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3122 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3123 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3124 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3125 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3126 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3127 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3128 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3129 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3130 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3131 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3132 default:
3c5a62b5
YL		 3133 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3134 "0x%x\n", signal_levels);
3135 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3136 }
3137}
3138
1a2eb460
KP		 3139/* Gen7's DP voltage swing and pre-emphasis control */
3140static uint32_t
3141intel_gen7_edp_signal_levels(uint8_t train_set)
3142{
3143 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3144 DP_TRAIN_PRE_EMPHASIS_MASK);
3145 switch (signal_levels) {
bd60018a 3146 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3147 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3148 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3149 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3150 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3151 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3152
bd60018a 3153 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3154 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3155 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3156 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3157
bd60018a 3158 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3159 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3160 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3161 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3162
3163 default:
3164 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3165 "0x%x\n", signal_levels);
3166 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3167 }
3168}
3169
d6c0d722
PZ		 3170/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3171static uint32_t
f0a3424e 3172intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3173{
d6c0d722
PZ		 3174 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3175 DP_TRAIN_PRE_EMPHASIS_MASK);
3176 switch (signal_levels) {
bd60018a 3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3178 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3179 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3180 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3181 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3182 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3183 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3184 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3185
bd60018a 3186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3187 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3188 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3189 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3191 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3192
bd60018a 3193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3194 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3196 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3197 default:
3198 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3199 "0x%x\n", signal_levels);
c5fe6a06 3200 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3201 }
a4fc5ed6
KP		 3202}
3203
f0a3424e
PZ		 3204/* Properly updates "DP" with the correct signal levels. */
3205static void
3206intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3207{
3208 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3209 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3210 struct drm_device *dev = intel_dig_port->base.base.dev;
3211 uint32_t signal_levels, mask;
3212 uint8_t train_set = intel_dp->train_set[0];
3213
5a9d1f1a 3214 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3215 signal_levels = intel_hsw_signal_levels(train_set);
3216 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3217 } else if (IS_CHERRYVIEW(dev)) {
3218 signal_levels = intel_chv_signal_levels(intel_dp);
3219 mask = 0;
e2fa6fba
P		 3220 } else if (IS_VALLEYVIEW(dev)) {
3221 signal_levels = intel_vlv_signal_levels(intel_dp);
3222 mask = 0;
bc7d38a4 3223 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3224 signal_levels = intel_gen7_edp_signal_levels(train_set);
3225 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3226 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3227 signal_levels = intel_gen6_edp_signal_levels(train_set);
3228 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3229 } else {
3230 signal_levels = intel_gen4_signal_levels(train_set);
3231 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3232 }
3233
3234 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3235
3236 *DP = (*DP & ~mask) | signal_levels;
3237}
3238
a4fc5ed6 3239static bool
ea5b213a 3240intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3241 uint32_t *DP,
58e10eb9 3242 uint8_t dp_train_pat)
a4fc5ed6 3243{
174edf1f
PZ		 3244 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3245 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3246 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3247 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3248 int ret, len;
a4fc5ed6 3249
7b13b58a 3250 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3251
70aff66c 3252 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3253 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3254
2cdfe6c8
JN		 3255 buf[0] = dp_train_pat;
3256 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3257 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3258 /* don't write DP_TRAINING_LANEx_SET on disable */
3259 len = 1;
3260 } else {
3261 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3262 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3263 len = intel_dp->lane_count + 1;
47ea7542 3264 }
a4fc5ed6 3265
9d1a1031
JN		 3266 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3267 buf, len);
2cdfe6c8
JN		 3268
3269 return ret == len;
a4fc5ed6
KP		 3270}
3271
70aff66c
JN		 3272static bool
3273intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3274 uint8_t dp_train_pat)
3275{
953d22e8 3276 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3277 intel_dp_set_signal_levels(intel_dp, DP);
3278 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3279}
3280
3281static bool
3282intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3283 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3284{
3285 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3286 struct drm_device *dev = intel_dig_port->base.base.dev;
3287 struct drm_i915_private *dev_priv = dev->dev_private;
3288 int ret;
3289
3290 intel_get_adjust_train(intel_dp, link_status);
3291 intel_dp_set_signal_levels(intel_dp, DP);
3292
3293 I915_WRITE(intel_dp->output_reg, *DP);
3294 POSTING_READ(intel_dp->output_reg);
3295
9d1a1031
JN		 3296 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3297 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3298
3299 return ret == intel_dp->lane_count;
3300}
3301
3ab9c637
ID		 3302static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3303{
3304 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3305 struct drm_device *dev = intel_dig_port->base.base.dev;
3306 struct drm_i915_private *dev_priv = dev->dev_private;
3307 enum port port = intel_dig_port->port;
3308 uint32_t val;
3309
3310 if (!HAS_DDI(dev))
3311 return;
3312
3313 val = I915_READ(DP_TP_CTL(port));
3314 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3315 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3316 I915_WRITE(DP_TP_CTL(port), val);
3317
3318 /*
3319 * On PORT_A we can have only eDP in SST mode. There the only reason
3320 * we need to set idle transmission mode is to work around a HW issue
3321 * where we enable the pipe while not in idle link-training mode.
3322 * In this case there is requirement to wait for a minimum number of
3323 * idle patterns to be sent.
3324 */
3325 if (port == PORT_A)
3326 return;
3327
3328 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3329 1))
3330 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3331}
3332
33a34e4e 3333/* Enable corresponding port and start training pattern 1 */
c19b0669 3334void
33a34e4e 3335intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3336{
da63a9f2 3337 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3338 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3339 int i;
3340 uint8_t voltage;
cdb0e95b 3341 int voltage_tries, loop_tries;
ea5b213a 3342 uint32_t DP = intel_dp->DP;
6aba5b6c 3343 uint8_t link_config[2];
a4fc5ed6 3344
affa9354 3345 if (HAS_DDI(dev))
c19b0669
PZ		 3346 intel_ddi_prepare_link_retrain(encoder);
3347
3cf2efb1 3348 /* Write the link configuration data */
6aba5b6c
JN		 3349 link_config[0] = intel_dp->link_bw;
3350 link_config[1] = intel_dp->lane_count;
3351 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3352 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3353 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3354
3355 link_config[0] = 0;
3356 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3357 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3358
3359 DP |= DP_PORT_EN;
1a2eb460 3360
70aff66c
JN		 3361 /* clock recovery */
3362 if (!intel_dp_reset_link_train(intel_dp, &DP,
3363 DP_TRAINING_PATTERN_1 |
3364 DP_LINK_SCRAMBLING_DISABLE)) {
3365 DRM_ERROR("failed to enable link training\n");
3366 return;
3367 }
3368
a4fc5ed6 3369 voltage = 0xff;
cdb0e95b
KP		 3370 voltage_tries = 0;
3371 loop_tries = 0;
a4fc5ed6 3372 for (;;) {
70aff66c 3373 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3374
a7c9655f 3375 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3376 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3377 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3378 break;
93f62dad 3379 }
a4fc5ed6 3380
01916270 3381 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3382 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3383 break;
3384 }
3385
3386 /* Check to see if we've tried the max voltage */
3387 for (i = 0; i < intel_dp->lane_count; i++)
3388 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3389 break;
3b4f819d 3390 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3391 ++loop_tries;
3392 if (loop_tries == 5) {
3def84b3 3393 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3394 break;
3395 }
70aff66c
JN		 3396 intel_dp_reset_link_train(intel_dp, &DP,
3397 DP_TRAINING_PATTERN_1 |
3398 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3399 voltage_tries = 0;
3400 continue;
3401 }
a4fc5ed6 3402
3cf2efb1 3403 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3404 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3405 ++voltage_tries;
b06fbda3 3406 if (voltage_tries == 5) {
3def84b3 3407 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3408 break;
3409 }
3410 } else
3411 voltage_tries = 0;
3412 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3413
70aff66c
JN		 3414 /* Update training set as requested by target */
3415 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3416 DRM_ERROR("failed to update link training\n");
3417 break;
3418 }
a4fc5ed6
KP		 3419 }
3420
33a34e4e
JB		 3421 intel_dp->DP = DP;
3422}
3423
c19b0669 3424void
33a34e4e
JB		 3425intel_dp_complete_link_train(struct intel_dp *intel_dp)
3426{
33a34e4e 3427 bool channel_eq = false;
37f80975 3428 int tries, cr_tries;
33a34e4e 3429 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3430 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3431
3432 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3433 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3434 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3435
a4fc5ed6 3436 /* channel equalization */
70aff66c 3437 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3438 training_pattern |
70aff66c
JN		 3439 DP_LINK_SCRAMBLING_DISABLE)) {
3440 DRM_ERROR("failed to start channel equalization\n");
3441 return;
3442 }
3443
a4fc5ed6 3444 tries = 0;
37f80975 3445 cr_tries = 0;
a4fc5ed6
KP		 3446 channel_eq = false;
3447 for (;;) {
70aff66c 3448 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3449
37f80975
JB		 3450 if (cr_tries > 5) {
3451 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3452 break;
3453 }
3454
a7c9655f 3455 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3456 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3457 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3458 break;
70aff66c 3459 }
a4fc5ed6 3460
37f80975 3461 /* Make sure clock is still ok */
01916270 3462 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3463 intel_dp_start_link_train(intel_dp);
70aff66c 3464 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3465 training_pattern |
70aff66c 3466 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3467 cr_tries++;
3468 continue;
3469 }
3470
1ffdff13 3471 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3472 channel_eq = true;
3473 break;
3474 }
a4fc5ed6 3475
37f80975
JB		 3476 /* Try 5 times, then try clock recovery if that fails */
3477 if (tries > 5) {
37f80975 3478 intel_dp_start_link_train(intel_dp);
70aff66c 3479 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3480 training_pattern |
70aff66c 3481 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3482 tries = 0;
3483 cr_tries++;
3484 continue;
3485 }
a4fc5ed6 3486
70aff66c
JN		 3487 /* Update training set as requested by target */
3488 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3489 DRM_ERROR("failed to update link training\n");
3490 break;
3491 }
3cf2efb1 3492 ++tries;
869184a6 3493 }
3cf2efb1 3494
3ab9c637
ID		 3495 intel_dp_set_idle_link_train(intel_dp);
3496
3497 intel_dp->DP = DP;
3498
d6c0d722 3499 if (channel_eq)
07f42258 3500 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3501
3ab9c637
ID		 3502}
3503
3504void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3505{
70aff66c 3506 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3507 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3508}
3509
3510static void
ea5b213a 3511intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3512{
da63a9f2 3513 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3514 enum port port = intel_dig_port->port;
da63a9f2 3515 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3516 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3517 struct intel_crtc *intel_crtc =
3518 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3519 uint32_t DP = intel_dp->DP;
a4fc5ed6 3520
bc76e320 3521 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3522 return;
3523
0c33d8d7 3524 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3525 return;
3526
28c97730 3527 DRM_DEBUG_KMS("\n");
32f9d658 3528
bc7d38a4 3529 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3530 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3531 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3532 } else {
aad3d14d
VS		 3533 if (IS_CHERRYVIEW(dev))
3534 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3535 else
3536 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3537 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3538 }
fe255d00 3539 POSTING_READ(intel_dp->output_reg);
5eb08b69 3540
493a7081 3541 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3542 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3543 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3544
5bddd17f
EA		 3545 /* Hardware workaround: leaving our transcoder select
3546 * set to transcoder B while it's off will prevent the
3547 * corresponding HDMI output on transcoder A.
3548 *
3549 * Combine this with another hardware workaround:
3550 * transcoder select bit can only be cleared while the
3551 * port is enabled.
3552 */
3553 DP &= ~DP_PIPEB_SELECT;
3554 I915_WRITE(intel_dp->output_reg, DP);
3555
3556 /* Changes to enable or select take place the vblank
3557 * after being written.
3558 */
ff50afe9
DV		 3559 if (WARN_ON(crtc == NULL)) {
3560 /* We should never try to disable a port without a crtc
3561 * attached. For paranoia keep the code around for a
3562 * bit. */
31acbcc4
CW		 3563 POSTING_READ(intel_dp->output_reg);
3564 msleep(50);
3565 } else
ab527efc 3566 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3567 }
3568
832afda6 3569 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3570 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3571 POSTING_READ(intel_dp->output_reg);
f01eca2e 3572 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3573}
3574
26d61aad
KP		 3575static bool
3576intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3577{
a031d709
RV		 3578 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3579 struct drm_device *dev = dig_port->base.base.dev;
3580 struct drm_i915_private *dev_priv = dev->dev_private;
3581
9d1a1031
JN		 3582 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3583 sizeof(intel_dp->dpcd)) < 0)
edb39244 3584 return false; /* aux transfer failed */
92fd8fd1 3585
a8e98153 3586 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3587
edb39244
AJ		 3588 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3589 return false; /* DPCD not present */
3590
2293bb5c
SK		 3591 /* Check if the panel supports PSR */
3592 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3593 if (is_edp(intel_dp)) {
9d1a1031
JN		 3594 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3595 intel_dp->psr_dpcd,
3596 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3597 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3598 dev_priv->psr.sink_support = true;
50003939 3599 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3600 }
50003939
JN		 3601 }
3602
7809a611 3603 /* Training Pattern 3 support, both source and sink */
06ea66b6 3604 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
7809a611
JN		 3605 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3606 (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
06ea66b6 3607 intel_dp->use_tps3 = true;
f8d8a672 3608 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3609 } else
3610 intel_dp->use_tps3 = false;
3611
edb39244
AJ		 3612 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3613 DP_DWN_STRM_PORT_PRESENT))
3614 return true; /* native DP sink */
3615
3616 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3617 return true; /* no per-port downstream info */
3618
9d1a1031
JN		 3619 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3620 intel_dp->downstream_ports,
3621 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3622 return false; /* downstream port status fetch failed */
3623
3624 return true;
92fd8fd1
KP		 3625}
3626
0d198328
AJ		 3627static void
3628intel_dp_probe_oui(struct intel_dp *intel_dp)
3629{
3630 u8 buf[3];
3631
3632 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3633 return;
3634
9d1a1031 3635 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3636 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3637 buf[0], buf[1], buf[2]);
3638
9d1a1031 3639 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3640 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3641 buf[0], buf[1], buf[2]);
3642}
3643
0e32b39c
DA		 3644static bool
3645intel_dp_probe_mst(struct intel_dp *intel_dp)
3646{
3647 u8 buf[1];
3648
3649 if (!intel_dp->can_mst)
3650 return false;
3651
3652 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3653 return false;
3654
0e32b39c
DA		 3655 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3656 if (buf[0] & DP_MST_CAP) {
3657 DRM_DEBUG_KMS("Sink is MST capable\n");
3658 intel_dp->is_mst = true;
3659 } else {
3660 DRM_DEBUG_KMS("Sink is not MST capable\n");
3661 intel_dp->is_mst = false;
3662 }
3663 }
0e32b39c
DA		 3664
3665 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3666 return intel_dp->is_mst;
3667}
3668
d2e216d0
RV		 3669int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3670{
3671 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3672 struct drm_device *dev = intel_dig_port->base.base.dev;
3673 struct intel_crtc *intel_crtc =
3674 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3675 u8 buf;
3676 int test_crc_count;
3677 int attempts = 6;
d2e216d0 3678
ad9dc91b 3679 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3680 return -EIO;
d2e216d0 3681
ad9dc91b 3682 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3683 return -ENOTTY;
3684
1dda5f93
RV		 3685 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3686 return -EIO;
3687
9d1a1031 3688 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3689 buf | DP_TEST_SINK_START) < 0)
bda0381e 3690 return -EIO;
d2e216d0 3691
1dda5f93 3692 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3693 return -EIO;
ad9dc91b 3694 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3695
ad9dc91b 3696 do {
1dda5f93
RV		 3697 if (drm_dp_dpcd_readb(&intel_dp->aux,
3698 DP_TEST_SINK_MISC, &buf) < 0)
3699 return -EIO;
ad9dc91b
RV		 3700 intel_wait_for_vblank(dev, intel_crtc->pipe);
3701 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3702
3703 if (attempts == 0) {
90bd1f46
DV		 3704 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
3705 return -ETIMEDOUT;
ad9dc91b 3706 }
d2e216d0 3707
9d1a1031 3708 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3709 return -EIO;
d2e216d0 3710
1dda5f93
RV		 3711 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3712 return -EIO;
3713 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3714 buf & ~DP_TEST_SINK_START) < 0)
3715 return -EIO;
ce31d9f4 3716
d2e216d0
RV		 3717 return 0;
3718}
3719
a60f0e38
JB		 3720static bool
3721intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3722{
9d1a1031
JN		 3723 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3724 DP_DEVICE_SERVICE_IRQ_VECTOR,
3725 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3726}
3727
0e32b39c
DA		 3728static bool
3729intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3730{
3731 int ret;
3732
3733 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3734 DP_SINK_COUNT_ESI,
3735 sink_irq_vector, 14);
3736 if (ret != 14)
3737 return false;
3738
3739 return true;
3740}
3741
a60f0e38
JB		 3742static void
3743intel_dp_handle_test_request(struct intel_dp *intel_dp)
3744{
3745 /* NAK by default */
9d1a1031 3746 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3747}
3748
0e32b39c
DA		 3749static int
3750intel_dp_check_mst_status(struct intel_dp *intel_dp)
3751{
3752 bool bret;
3753
3754 if (intel_dp->is_mst) {
3755 u8 esi[16] = { 0 };
3756 int ret = 0;
3757 int retry;
3758 bool handled;
3759 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3760go_again:
3761 if (bret == true) {
3762
3763 /* check link status - esi[10] = 0x200c */
3764 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3765 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3766 intel_dp_start_link_train(intel_dp);
3767 intel_dp_complete_link_train(intel_dp);
3768 intel_dp_stop_link_train(intel_dp);
3769 }
3770
3771 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3772 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3773
3774 if (handled) {
3775 for (retry = 0; retry < 3; retry++) {
3776 int wret;
3777 wret = drm_dp_dpcd_write(&intel_dp->aux,
3778 DP_SINK_COUNT_ESI+1,
3779 &esi[1], 3);
3780 if (wret == 3) {
3781 break;
3782 }
3783 }
3784
3785 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3786 if (bret == true) {
3787 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3788 goto go_again;
3789 }
3790 } else
3791 ret = 0;
3792
3793 return ret;
3794 } else {
3795 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3796 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3797 intel_dp->is_mst = false;
3798 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3799 /* send a hotplug event */
3800 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3801 }
3802 }
3803 return -EINVAL;
3804}
3805
a4fc5ed6
KP		 3806/*
3807 * According to DP spec
3808 * 5.1.2:
3809 * 1. Read DPCD
3810 * 2. Configure link according to Receiver Capabilities
3811 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3812 * 4. Check link status on receipt of hot-plug interrupt
3813 */
00c09d70 3814void
ea5b213a 3815intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3816{
5b215bcf 3817 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3818 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3819 u8 sink_irq_vector;
93f62dad 3820 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3821
5b215bcf
DA		 3822 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3823
da63a9f2 3824 if (!intel_encoder->connectors_active)
d2b996ac 3825 return;
59cd09e1 3826
da63a9f2 3827 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3828 return;
3829
1a125d8a
ID		 3830 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3831 return;
3832
92fd8fd1 3833 /* Try to read receiver status if the link appears to be up */
93f62dad 3834 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3835 return;
3836 }
3837
92fd8fd1 3838 /* Now read the DPCD to see if it's actually running */
26d61aad 3839 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3840 return;
3841 }
3842
a60f0e38
JB		 3843 /* Try to read the source of the interrupt */
3844 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3845 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3846 /* Clear interrupt source */
9d1a1031
JN		 3847 drm_dp_dpcd_writeb(&intel_dp->aux,
3848 DP_DEVICE_SERVICE_IRQ_VECTOR,
3849 sink_irq_vector);
a60f0e38
JB		 3850
3851 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3852 intel_dp_handle_test_request(intel_dp);
3853 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3854 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3855 }
3856
1ffdff13 3857 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3858 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3859 intel_encoder->base.name);
33a34e4e
JB		 3860 intel_dp_start_link_train(intel_dp);
3861 intel_dp_complete_link_train(intel_dp);
3ab9c637 3862 intel_dp_stop_link_train(intel_dp);
33a34e4e 3863 }
a4fc5ed6 3864}
a4fc5ed6 3865
caf9ab24 3866/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3867static enum drm_connector_status
26d61aad 3868intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3869{
caf9ab24 3870 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3871 uint8_t type;
3872
3873 if (!intel_dp_get_dpcd(intel_dp))
3874 return connector_status_disconnected;
3875
3876 /* if there's no downstream port, we're done */
3877 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3878 return connector_status_connected;
caf9ab24
AJ		 3879
3880 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3881 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3882 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3883 uint8_t reg;
9d1a1031
JN		 3884
3885 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3886 &reg, 1) < 0)
caf9ab24 3887 return connector_status_unknown;
9d1a1031 3888
23235177
AJ		 3889 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3890 : connector_status_disconnected;
caf9ab24
AJ		 3891 }
3892
3893 /* If no HPD, poke DDC gently */
0b99836f 3894 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3895 return connector_status_connected;
caf9ab24
AJ		 3896
3897 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3898 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3899 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3900 if (type == DP_DS_PORT_TYPE_VGA ||
3901 type == DP_DS_PORT_TYPE_NON_EDID)
3902 return connector_status_unknown;
3903 } else {
3904 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3905 DP_DWN_STRM_PORT_TYPE_MASK;
3906 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3907 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3908 return connector_status_unknown;
3909 }
caf9ab24
AJ		 3910
3911 /* Anything else is out of spec, warn and ignore */
3912 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3913 return connector_status_disconnected;
71ba9000
AJ		 3914}
3915
d410b56d
CW		 3916static enum drm_connector_status
3917edp_detect(struct intel_dp *intel_dp)
3918{
3919 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3920 enum drm_connector_status status;
3921
3922 status = intel_panel_detect(dev);
3923 if (status == connector_status_unknown)
3924 status = connector_status_connected;
3925
3926 return status;
3927}
3928
5eb08b69 3929static enum drm_connector_status
a9756bb5 3930ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3931{
30add22d 3932 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3933 struct drm_i915_private *dev_priv = dev->dev_private;
3934 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 3935
1b469639
DL		 3936 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3937 return connector_status_disconnected;
3938
26d61aad 3939 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3940}
3941
2a592bec
DA		 3942static int g4x_digital_port_connected(struct drm_device *dev,
3943 struct intel_digital_port *intel_dig_port)
a4fc5ed6 3944{
a4fc5ed6 3945 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 3946 uint32_t bit;
5eb08b69 3947
232a6ee9
TP		 3948 if (IS_VALLEYVIEW(dev)) {
3949 switch (intel_dig_port->port) {
3950 case PORT_B:
3951 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3952 break;
3953 case PORT_C:
3954 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3955 break;
3956 case PORT_D:
3957 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3958 break;
3959 default:
2a592bec 3960 return -EINVAL;
232a6ee9
TP		 3961 }
3962 } else {
3963 switch (intel_dig_port->port) {
3964 case PORT_B:
3965 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3966 break;
3967 case PORT_C:
3968 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3969 break;
3970 case PORT_D:
3971 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3972 break;
3973 default:
2a592bec 3974 return -EINVAL;
232a6ee9 3975 }
a4fc5ed6
KP		 3976 }
3977
10f76a38 3978 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 3979 return 0;
3980 return 1;
3981}
3982
3983static enum drm_connector_status
3984g4x_dp_detect(struct intel_dp *intel_dp)
3985{
3986 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3987 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3988 int ret;
3989
3990 /* Can't disconnect eDP, but you can close the lid... */
3991 if (is_edp(intel_dp)) {
3992 enum drm_connector_status status;
3993
3994 status = intel_panel_detect(dev);
3995 if (status == connector_status_unknown)
3996 status = connector_status_connected;
3997 return status;
3998 }
3999
4000 ret = g4x_digital_port_connected(dev, intel_dig_port);
4001 if (ret == -EINVAL)
4002 return connector_status_unknown;
4003 else if (ret == 0)
a4fc5ed6
KP		 4004 return connector_status_disconnected;
4005
26d61aad 4006 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4007}
4008
8c241fef 4009static struct edid *
beb60608 4010intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4011{
beb60608 4012 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4013
9cd300e0
JN		 4014 /* use cached edid if we have one */
4015 if (intel_connector->edid) {
9cd300e0
JN		 4016 /* invalid edid */
4017 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4018 return NULL;
4019
55e9edeb 4020 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4021 } else
4022 return drm_get_edid(&intel_connector->base,
4023 &intel_dp->aux.ddc);
4024}
8c241fef 4025
beb60608
CW		 4026static void
4027intel_dp_set_edid(struct intel_dp *intel_dp)
4028{
4029 struct intel_connector *intel_connector = intel_dp->attached_connector;
4030 struct edid *edid;
8c241fef 4031
beb60608
CW		 4032 edid = intel_dp_get_edid(intel_dp);
4033 intel_connector->detect_edid = edid;
4034
4035 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4036 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4037 else
4038 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4039}
4040
beb60608
CW		 4041static void
4042intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4043{
beb60608 4044 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4045
beb60608
CW		 4046 kfree(intel_connector->detect_edid);
4047 intel_connector->detect_edid = NULL;
9cd300e0 4048
beb60608
CW		 4049 intel_dp->has_audio = false;
4050}
d6f24d0f 4051
beb60608
CW		 4052static enum intel_display_power_domain
4053intel_dp_power_get(struct intel_dp *dp)
4054{
4055 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4056 enum intel_display_power_domain power_domain;
4057
4058 power_domain = intel_display_port_power_domain(encoder);
4059 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4060
4061 return power_domain;
4062}
d6f24d0f 4063
beb60608
CW		 4064static void
4065intel_dp_power_put(struct intel_dp *dp,
4066 enum intel_display_power_domain power_domain)
4067{
4068 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4069 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4070}
4071
a9756bb5
ZW		 4072static enum drm_connector_status
4073intel_dp_detect(struct drm_connector *connector, bool force)
4074{
4075 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4076 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4077 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4078 struct drm_device *dev = connector->dev;
a9756bb5 4079 enum drm_connector_status status;
671dedd2 4080 enum intel_display_power_domain power_domain;
0e32b39c 4081 bool ret;
a9756bb5 4082
164c8598 4083 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4084 connector->base.id, connector->name);
beb60608 4085 intel_dp_unset_edid(intel_dp);
164c8598 4086
0e32b39c
DA		 4087 if (intel_dp->is_mst) {
4088 /* MST devices are disconnected from a monitor POV */
4089 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4090 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4091 return connector_status_disconnected;
0e32b39c
DA		 4092 }
4093
beb60608 4094 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4095
d410b56d
CW		 4096 /* Can't disconnect eDP, but you can close the lid... */
4097 if (is_edp(intel_dp))
4098 status = edp_detect(intel_dp);
4099 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4100 status = ironlake_dp_detect(intel_dp);
4101 else
4102 status = g4x_dp_detect(intel_dp);
4103 if (status != connector_status_connected)
c8c8fb33 4104 goto out;
a9756bb5 4105
0d198328
AJ		 4106 intel_dp_probe_oui(intel_dp);
4107
0e32b39c
DA		 4108 ret = intel_dp_probe_mst(intel_dp);
4109 if (ret) {
4110 /* if we are in MST mode then this connector
4111 won't appear connected or have anything with EDID on it */
4112 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4113 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4114 status = connector_status_disconnected;
4115 goto out;
4116 }
4117
beb60608 4118 intel_dp_set_edid(intel_dp);
a9756bb5 4119
d63885da
PZ		 4120 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4121 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4122 status = connector_status_connected;
4123
4124out:
beb60608 4125 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4126 return status;
a4fc5ed6
KP		 4127}
4128
beb60608
CW		 4129static void
4130intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4131{
df0e9248 4132 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4133 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4134 enum intel_display_power_domain power_domain;
a4fc5ed6 4135
beb60608
CW		 4136 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4137 connector->base.id, connector->name);
4138 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4139
beb60608
CW		 4140 if (connector->status != connector_status_connected)
4141 return;
671dedd2 4142
beb60608
CW		 4143 power_domain = intel_dp_power_get(intel_dp);
4144
4145 intel_dp_set_edid(intel_dp);
4146
4147 intel_dp_power_put(intel_dp, power_domain);
4148
4149 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4150 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4151}
4152
4153static int intel_dp_get_modes(struct drm_connector *connector)
4154{
4155 struct intel_connector *intel_connector = to_intel_connector(connector);
4156 struct edid *edid;
4157
4158 edid = intel_connector->detect_edid;
4159 if (edid) {
4160 int ret = intel_connector_update_modes(connector, edid);
4161 if (ret)
4162 return ret;
4163 }
32f9d658 4164
f8779fda 4165 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4166 if (is_edp(intel_attached_dp(connector)) &&
4167 intel_connector->panel.fixed_mode) {
f8779fda 4168 struct drm_display_mode *mode;
beb60608
CW		 4169
4170 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4171 intel_connector->panel.fixed_mode);
f8779fda 4172 if (mode) {
32f9d658
ZW		 4173 drm_mode_probed_add(connector, mode);
4174 return 1;
4175 }
4176 }
beb60608 4177
32f9d658 4178 return 0;
a4fc5ed6
KP		 4179}
4180
1aad7ac0
CW		 4181static bool
4182intel_dp_detect_audio(struct drm_connector *connector)
4183{
1aad7ac0 4184 bool has_audio = false;
beb60608 4185 struct edid *edid;
1aad7ac0 4186
beb60608
CW		 4187 edid = to_intel_connector(connector)->detect_edid;
4188 if (edid)
1aad7ac0 4189 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4190
1aad7ac0
CW		 4191 return has_audio;
4192}
4193
f684960e
CW		 4194static int
4195intel_dp_set_property(struct drm_connector *connector,
4196 struct drm_property *property,
4197 uint64_t val)
4198{
e953fd7b 4199 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4200 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4201 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4202 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4203 int ret;
4204
662595df 4205 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4206 if (ret)
4207 return ret;
4208
3f43c48d 4209 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4210 int i = val;
4211 bool has_audio;
4212
4213 if (i == intel_dp->force_audio)
f684960e
CW		 4214 return 0;
4215
1aad7ac0 4216 intel_dp->force_audio = i;
f684960e 4217
c3e5f67b 4218 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4219 has_audio = intel_dp_detect_audio(connector);
4220 else
c3e5f67b 4221 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4222
4223 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4224 return 0;
4225
1aad7ac0 4226 intel_dp->has_audio = has_audio;
f684960e
CW		 4227 goto done;
4228 }
4229
e953fd7b 4230 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4231 bool old_auto = intel_dp->color_range_auto;
4232 uint32_t old_range = intel_dp->color_range;
4233
55bc60db
VS		 4234 switch (val) {
4235 case INTEL_BROADCAST_RGB_AUTO:
4236 intel_dp->color_range_auto = true;
4237 break;
4238 case INTEL_BROADCAST_RGB_FULL:
4239 intel_dp->color_range_auto = false;
4240 intel_dp->color_range = 0;
4241 break;
4242 case INTEL_BROADCAST_RGB_LIMITED:
4243 intel_dp->color_range_auto = false;
4244 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4245 break;
4246 default:
4247 return -EINVAL;
4248 }
ae4edb80
DV		 4249
4250 if (old_auto == intel_dp->color_range_auto &&
4251 old_range == intel_dp->color_range)
4252 return 0;
4253
e953fd7b
CW		 4254 goto done;
4255 }
4256
53b41837
YN		 4257 if (is_edp(intel_dp) &&
4258 property == connector->dev->mode_config.scaling_mode_property) {
4259 if (val == DRM_MODE_SCALE_NONE) {
4260 DRM_DEBUG_KMS("no scaling not supported\n");
4261 return -EINVAL;
4262 }
4263
4264 if (intel_connector->panel.fitting_mode == val) {
4265 /* the eDP scaling property is not changed */
4266 return 0;
4267 }
4268 intel_connector->panel.fitting_mode = val;
4269
4270 goto done;
4271 }
4272
f684960e
CW		 4273 return -EINVAL;
4274
4275done:
c0c36b94
CW		 4276 if (intel_encoder->base.crtc)
4277 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4278
4279 return 0;
4280}
4281
a4fc5ed6 4282static void
73845adf 4283intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4284{
1d508706 4285 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4286
10e972d3 4287 kfree(intel_connector->detect_edid);
beb60608 4288
9cd300e0
JN		 4289 if (!IS_ERR_OR_NULL(intel_connector->edid))
4290 kfree(intel_connector->edid);
4291
acd8db10
PZ		 4292 /* Can't call is_edp() since the encoder may have been destroyed
4293 * already. */
4294 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4295 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4296
a4fc5ed6 4297 drm_connector_cleanup(connector);
55f78c43 4298 kfree(connector);
a4fc5ed6
KP		 4299}
4300
00c09d70 4301void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4302{
da63a9f2
PZ		 4303 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4304 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4305
4f71d0cb 4306 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4307 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4308 drm_encoder_cleanup(encoder);
bd943159
KP		 4309 if (is_edp(intel_dp)) {
4310 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4311 /*
4312 * vdd might still be enabled do to the delayed vdd off.
4313 * Make sure vdd is actually turned off here.
4314 */
773538e8 4315 pps_lock(intel_dp);
4be73780 4316 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4317 pps_unlock(intel_dp);
4318
01527b31
CT		 4319 if (intel_dp->edp_notifier.notifier_call) {
4320 unregister_reboot_notifier(&intel_dp->edp_notifier);
4321 intel_dp->edp_notifier.notifier_call = NULL;
4322 }
bd943159 4323 }
da63a9f2 4324 kfree(intel_dig_port);
24d05927
DV		 4325}
4326
07f9cd0b
ID		 4327static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4328{
4329 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4330
4331 if (!is_edp(intel_dp))
4332 return;
4333
951468f3
VS		 4334 /*
4335 * vdd might still be enabled do to the delayed vdd off.
4336 * Make sure vdd is actually turned off here.
4337 */
afa4e53a 4338 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4339 pps_lock(intel_dp);
07f9cd0b 4340 edp_panel_vdd_off_sync(intel_dp);
773538e8 4341 pps_unlock(intel_dp);
07f9cd0b
ID		 4342}
4343
49e6bc51
VS		 4344static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4345{
4346 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4347 struct drm_device *dev = intel_dig_port->base.base.dev;
4348 struct drm_i915_private *dev_priv = dev->dev_private;
4349 enum intel_display_power_domain power_domain;
4350
4351 lockdep_assert_held(&dev_priv->pps_mutex);
4352
4353 if (!edp_have_panel_vdd(intel_dp))
4354 return;
4355
4356 /*
4357 * The VDD bit needs a power domain reference, so if the bit is
4358 * already enabled when we boot or resume, grab this reference and
4359 * schedule a vdd off, so we don't hold on to the reference
4360 * indefinitely.
4361 */
4362 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4363 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4364 intel_display_power_get(dev_priv, power_domain);
4365
4366 edp_panel_vdd_schedule_off(intel_dp);
4367}
4368
6d93c0c4
ID		 4369static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4370{
49e6bc51
VS		 4371 struct intel_dp *intel_dp;
4372
4373 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4374 return;
4375
4376 intel_dp = enc_to_intel_dp(encoder);
4377
4378 pps_lock(intel_dp);
4379
4380 /*
4381 * Read out the current power sequencer assignment,
4382 * in case the BIOS did something with it.
4383 */
4384 if (IS_VALLEYVIEW(encoder->dev))
4385 vlv_initial_power_sequencer_setup(intel_dp);
4386
4387 intel_edp_panel_vdd_sanitize(intel_dp);
4388
4389 pps_unlock(intel_dp);
6d93c0c4
ID		 4390}
4391
a4fc5ed6 4392static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4393 .dpms = intel_connector_dpms,
a4fc5ed6 4394 .detect = intel_dp_detect,
beb60608 4395 .force = intel_dp_force,
a4fc5ed6 4396 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4397 .set_property = intel_dp_set_property,
73845adf 4398 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4399};
4400
4401static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4402 .get_modes = intel_dp_get_modes,
4403 .mode_valid = intel_dp_mode_valid,
df0e9248 4404 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4405};
4406
a4fc5ed6 4407static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4408 .reset = intel_dp_encoder_reset,
24d05927 4409 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4410};
4411
0e32b39c 4412void
21d40d37 4413intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4414{
0e32b39c 4415 return;
c8110e52 4416}
6207937d 4417
13cf5504
DA		 4418bool
4419intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4420{
4421 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4422 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4423 struct drm_device *dev = intel_dig_port->base.base.dev;
4424 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4425 enum intel_display_power_domain power_domain;
4426 bool ret = true;
4427
0e32b39c
DA		 4428 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4429 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4430
7a7f84cc
VS		 4431 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4432 /*
4433 * vdd off can generate a long pulse on eDP which
4434 * would require vdd on to handle it, and thus we
4435 * would end up in an endless cycle of
4436 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4437 */
4438 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4439 port_name(intel_dig_port->port));
4440 return false;
4441 }
4442
26fbb774
VS		 4443 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4444 port_name(intel_dig_port->port),
0e32b39c 4445 long_hpd ? "long" : "short");
13cf5504 4446
1c767b33
ID		 4447 power_domain = intel_display_port_power_domain(intel_encoder);
4448 intel_display_power_get(dev_priv, power_domain);
4449
0e32b39c 4450 if (long_hpd) {
2a592bec
DA		 4451
4452 if (HAS_PCH_SPLIT(dev)) {
4453 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4454 goto mst_fail;
4455 } else {
4456 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4457 goto mst_fail;
4458 }
0e32b39c
DA		 4459
4460 if (!intel_dp_get_dpcd(intel_dp)) {
4461 goto mst_fail;
4462 }
4463
4464 intel_dp_probe_oui(intel_dp);
4465
4466 if (!intel_dp_probe_mst(intel_dp))
4467 goto mst_fail;
4468
4469 } else {
4470 if (intel_dp->is_mst) {
1c767b33 4471 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4472 goto mst_fail;
4473 }
4474
4475 if (!intel_dp->is_mst) {
4476 /*
4477 * we'll check the link status via the normal hot plug path later -
4478 * but for short hpds we should check it now
4479 */
5b215bcf 4480 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4481 intel_dp_check_link_status(intel_dp);
5b215bcf 4482 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4483 }
4484 }
1c767b33
ID		 4485 ret = false;
4486 goto put_power;
0e32b39c
DA		 4487mst_fail:
4488 /* if we were in MST mode, and device is not there get out of MST mode */
4489 if (intel_dp->is_mst) {
4490 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4491 intel_dp->is_mst = false;
4492 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4493 }
1c767b33
ID		 4494put_power:
4495 intel_display_power_put(dev_priv, power_domain);
4496
4497 return ret;
13cf5504
DA		 4498}
4499
e3421a18
ZW		 4500/* Return which DP Port should be selected for Transcoder DP control */
4501int
0206e353 4502intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4503{
4504 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4505 struct intel_encoder *intel_encoder;
4506 struct intel_dp *intel_dp;
e3421a18 4507
fa90ecef
PZ		 4508 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4509 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4510
fa90ecef
PZ		 4511 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4512 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4513 return intel_dp->output_reg;
e3421a18 4514 }
ea5b213a 4515
e3421a18
ZW		 4516 return -1;
4517}
4518
36e83a18 4519/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4520bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4521{
4522 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4523 union child_device_config *p_child;
36e83a18 4524 int i;
5d8a7752
VS		 4525 static const short port_mapping[] = {
4526 [PORT_B] = PORT_IDPB,
4527 [PORT_C] = PORT_IDPC,
4528 [PORT_D] = PORT_IDPD,
4529 };
36e83a18 4530
3b32a35b
VS		 4531 if (port == PORT_A)
4532 return true;
4533
41aa3448 4534 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4535 return false;
4536
41aa3448
RV		 4537 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4538 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4539
5d8a7752 4540 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4541 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4542 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4543 return true;
4544 }
4545 return false;
4546}
4547
0e32b39c 4548void
f684960e
CW		 4549intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4550{
53b41837
YN		 4551 struct intel_connector *intel_connector = to_intel_connector(connector);
4552
3f43c48d 4553 intel_attach_force_audio_property(connector);
e953fd7b 4554 intel_attach_broadcast_rgb_property(connector);
55bc60db 4555 intel_dp->color_range_auto = true;
53b41837
YN		 4556
4557 if (is_edp(intel_dp)) {
4558 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4559 drm_object_attach_property(
4560 &connector->base,
53b41837 4561 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4562 DRM_MODE_SCALE_ASPECT);
4563 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4564 }
f684960e
CW		 4565}
4566
dada1a9f
ID		 4567static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4568{
4569 intel_dp->last_power_cycle = jiffies;
4570 intel_dp->last_power_on = jiffies;
4571 intel_dp->last_backlight_off = jiffies;
4572}
4573
67a54566
DV		 4574static void
4575intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4576 struct intel_dp *intel_dp)
67a54566
DV		 4577{
4578 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4579 struct edp_power_seq cur, vbt, spec,
4580 *final = &intel_dp->pps_delays;
67a54566 4581 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4582 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4583
e39b999a
VS		 4584 lockdep_assert_held(&dev_priv->pps_mutex);
4585
81ddbc69
VS		 4586 /* already initialized? */
4587 if (final->t11_t12 != 0)
4588 return;
4589
453c5420 4590 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4591 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4592 pp_on_reg = PCH_PP_ON_DELAYS;
4593 pp_off_reg = PCH_PP_OFF_DELAYS;
4594 pp_div_reg = PCH_PP_DIVISOR;
4595 } else {
bf13e81b
JN		 4596 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4597
4598 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4599 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4600 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4601 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4602 }
67a54566
DV		 4603
4604 /* Workaround: Need to write PP_CONTROL with the unlock key as
4605 * the very first thing. */
453c5420 4606 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4607 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4608
453c5420
JB		 4609 pp_on = I915_READ(pp_on_reg);
4610 pp_off = I915_READ(pp_off_reg);
4611 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4612
4613 /* Pull timing values out of registers */
4614 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4615 PANEL_POWER_UP_DELAY_SHIFT;
4616
4617 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4618 PANEL_LIGHT_ON_DELAY_SHIFT;
4619
4620 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4621 PANEL_LIGHT_OFF_DELAY_SHIFT;
4622
4623 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4624 PANEL_POWER_DOWN_DELAY_SHIFT;
4625
4626 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4627 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4628
4629 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4630 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4631
41aa3448 4632 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4633
4634 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4635 * our hw here, which are all in 100usec. */
4636 spec.t1_t3 = 210 * 10;
4637 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4638 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4639 spec.t10 = 500 * 10;
4640 /* This one is special and actually in units of 100ms, but zero
4641 * based in the hw (so we need to add 100 ms). But the sw vbt
4642 * table multiplies it with 1000 to make it in units of 100usec,
4643 * too. */
4644 spec.t11_t12 = (510 + 100) * 10;
4645
4646 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4647 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4648
4649 /* Use the max of the register settings and vbt. If both are
4650 * unset, fall back to the spec limits. */
36b5f425 4651#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4652 spec.field : \
4653 max(cur.field, vbt.field))
4654 assign_final(t1_t3);
4655 assign_final(t8);
4656 assign_final(t9);
4657 assign_final(t10);
4658 assign_final(t11_t12);
4659#undef assign_final
4660
36b5f425 4661#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4662 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4663 intel_dp->backlight_on_delay = get_delay(t8);
4664 intel_dp->backlight_off_delay = get_delay(t9);
4665 intel_dp->panel_power_down_delay = get_delay(t10);
4666 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4667#undef get_delay
4668
f30d26e4
JN		 4669 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4670 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4671 intel_dp->panel_power_cycle_delay);
4672
4673 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4674 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4675}
4676
4677static void
4678intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4679 struct intel_dp *intel_dp)
f30d26e4
JN		 4680{
4681 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4682 u32 pp_on, pp_off, pp_div, port_sel = 0;
4683 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4684 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4685 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4686 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4687
e39b999a 4688 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4689
4690 if (HAS_PCH_SPLIT(dev)) {
4691 pp_on_reg = PCH_PP_ON_DELAYS;
4692 pp_off_reg = PCH_PP_OFF_DELAYS;
4693 pp_div_reg = PCH_PP_DIVISOR;
4694 } else {
bf13e81b
JN		 4695 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4696
4697 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4698 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4699 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4700 }
4701
b2f19d1a
PZ		 4702 /*
4703 * And finally store the new values in the power sequencer. The
4704 * backlight delays are set to 1 because we do manual waits on them. For
4705 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4706 * we'll end up waiting for the backlight off delay twice: once when we
4707 * do the manual sleep, and once when we disable the panel and wait for
4708 * the PP_STATUS bit to become zero.
4709 */
f30d26e4 4710 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4711 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4712 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4713 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4714 /* Compute the divisor for the pp clock, simply match the Bspec
4715 * formula. */
453c5420 4716 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4717 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4718 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4719
4720 /* Haswell doesn't have any port selection bits for the panel
4721 * power sequencer any more. */
bc7d38a4 4722 if (IS_VALLEYVIEW(dev)) {
ad933b56 4723 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4724 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4725 if (port == PORT_A)
a24c144c 4726 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4727 else
a24c144c 4728 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4729 }
4730
453c5420
JB		 4731 pp_on |= port_sel;
4732
4733 I915_WRITE(pp_on_reg, pp_on);
4734 I915_WRITE(pp_off_reg, pp_off);
4735 I915_WRITE(pp_div_reg, pp_div);
67a54566 4736
67a54566 4737 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4738 I915_READ(pp_on_reg),
4739 I915_READ(pp_off_reg),
4740 I915_READ(pp_div_reg));
f684960e
CW		 4741}
4742
439d7ac0
PB		 4743void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4744{
4745 struct drm_i915_private *dev_priv = dev->dev_private;
4746 struct intel_encoder *encoder;
4747 struct intel_dp *intel_dp = NULL;
4748 struct intel_crtc_config *config = NULL;
4749 struct intel_crtc *intel_crtc = NULL;
4750 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4751 u32 reg, val;
4752 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4753
4754 if (refresh_rate <= 0) {
4755 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4756 return;
4757 }
4758
4759 if (intel_connector == NULL) {
4760 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4761 return;
4762 }
4763
1fcc9d1c
DV		 4764 /*
4765 * FIXME: This needs proper synchronization with psr state. But really
4766 * hard to tell without seeing the user of this function of this code.
4767 * Check locking and ordering once that lands.
4768 */
0bc12bcb 4769 if (INTEL_INFO(dev)->gen < 8 && intel_psr_is_enabled(dev)) {
439d7ac0
PB		 4770 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4771 return;
4772 }
4773
4774 encoder = intel_attached_encoder(&intel_connector->base);
4775 intel_dp = enc_to_intel_dp(&encoder->base);
4776 intel_crtc = encoder->new_crtc;
4777
4778 if (!intel_crtc) {
4779 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4780 return;
4781 }
4782
4783 config = &intel_crtc->config;
4784
4785 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4786 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4787 return;
4788 }
4789
4790 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4791 index = DRRS_LOW_RR;
4792
4793 if (index == intel_dp->drrs_state.refresh_rate_type) {
4794 DRM_DEBUG_KMS(
4795 "DRRS requested for previously set RR...ignoring\n");
4796 return;
4797 }
4798
4799 if (!intel_crtc->active) {
4800 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4801 return;
4802 }
4803
4804 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4805 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4806 val = I915_READ(reg);
4807 if (index > DRRS_HIGH_RR) {
4808 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4809 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4810 } else {
4811 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4812 }
4813 I915_WRITE(reg, val);
4814 }
4815
4816 /*
4817 * mutex taken to ensure that there is no race between differnt
4818 * drrs calls trying to update refresh rate. This scenario may occur
4819 * in future when idleness detection based DRRS in kernel and
4820 * possible calls from user space to set differnt RR are made.
4821 */
4822
4823 mutex_lock(&intel_dp->drrs_state.mutex);
4824
4825 intel_dp->drrs_state.refresh_rate_type = index;
4826
4827 mutex_unlock(&intel_dp->drrs_state.mutex);
4828
4829 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4830}
4831
4f9db5b5
PB		 4832static struct drm_display_mode *
4833intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4834 struct intel_connector *intel_connector,
4835 struct drm_display_mode *fixed_mode)
4836{
4837 struct drm_connector *connector = &intel_connector->base;
4838 struct intel_dp *intel_dp = &intel_dig_port->dp;
4839 struct drm_device *dev = intel_dig_port->base.base.dev;
4840 struct drm_i915_private *dev_priv = dev->dev_private;
4841 struct drm_display_mode *downclock_mode = NULL;
4842
4843 if (INTEL_INFO(dev)->gen <= 6) {
4844 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4845 return NULL;
4846 }
4847
4848 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4849 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4850 return NULL;
4851 }
4852
4853 downclock_mode = intel_find_panel_downclock
4854 (dev, fixed_mode, connector);
4855
4856 if (!downclock_mode) {
4079b8d1 4857 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4858 return NULL;
4859 }
4860
439d7ac0
PB		 4861 dev_priv->drrs.connector = intel_connector;
4862
4863 mutex_init(&intel_dp->drrs_state.mutex);
4864
4f9db5b5
PB		 4865 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4866
4867 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4868 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4869 return downclock_mode;
4870}
4871
ed92f0b2 4872static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 4873 struct intel_connector *intel_connector)
ed92f0b2
PZ		 4874{
4875 struct drm_connector *connector = &intel_connector->base;
4876 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4877 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4878 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4879 struct drm_i915_private *dev_priv = dev->dev_private;
4880 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4881 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4882 bool has_dpcd;
4883 struct drm_display_mode *scan;
4884 struct edid *edid;
6517d273 4885 enum pipe pipe = INVALID_PIPE;
ed92f0b2 4886
4f9db5b5
PB		 4887 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4888
ed92f0b2
PZ		 4889 if (!is_edp(intel_dp))
4890 return true;
4891
49e6bc51
VS		 4892 pps_lock(intel_dp);
4893 intel_edp_panel_vdd_sanitize(intel_dp);
4894 pps_unlock(intel_dp);
63635217 4895
ed92f0b2 4896 /* Cache DPCD and EDID for edp. */
ed92f0b2 4897 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 4898
4899 if (has_dpcd) {
4900 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4901 dev_priv->no_aux_handshake =
4902 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4903 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4904 } else {
4905 /* if this fails, presume the device is a ghost */
4906 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4907 return false;
4908 }
4909
4910 /* We now know it's not a ghost, init power sequence regs. */
773538e8 4911 pps_lock(intel_dp);
36b5f425 4912 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 4913 pps_unlock(intel_dp);
ed92f0b2 4914
060c8778 4915 mutex_lock(&dev->mode_config.mutex);
0b99836f 4916 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4917 if (edid) {
4918 if (drm_add_edid_modes(connector, edid)) {
4919 drm_mode_connector_update_edid_property(connector,
4920 edid);
4921 drm_edid_to_eld(connector, edid);
4922 } else {
4923 kfree(edid);
4924 edid = ERR_PTR(-EINVAL);
4925 }
4926 } else {
4927 edid = ERR_PTR(-ENOENT);
4928 }
4929 intel_connector->edid = edid;
4930
4931 /* prefer fixed mode from EDID if available */
4932 list_for_each_entry(scan, &connector->probed_modes, head) {
4933 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4934 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4935 downclock_mode = intel_dp_drrs_init(
4936 intel_dig_port,
4937 intel_connector, fixed_mode);
ed92f0b2
PZ		 4938 break;
4939 }
4940 }
4941
4942 /* fallback to VBT if available for eDP */
4943 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4944 fixed_mode = drm_mode_duplicate(dev,
4945 dev_priv->vbt.lfp_lvds_vbt_mode);
4946 if (fixed_mode)
4947 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4948 }
060c8778 4949 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4950
01527b31
CT		 4951 if (IS_VALLEYVIEW(dev)) {
4952 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4953 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 4954
4955 /*
4956 * Figure out the current pipe for the initial backlight setup.
4957 * If the current pipe isn't valid, try the PPS pipe, and if that
4958 * fails just assume pipe A.
4959 */
4960 if (IS_CHERRYVIEW(dev))
4961 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
4962 else
4963 pipe = PORT_TO_PIPE(intel_dp->DP);
4964
4965 if (pipe != PIPE_A && pipe != PIPE_B)
4966 pipe = intel_dp->pps_pipe;
4967
4968 if (pipe != PIPE_A && pipe != PIPE_B)
4969 pipe = PIPE_A;
4970
4971 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
4972 pipe_name(pipe));
01527b31
CT		 4973 }
4974
4f9db5b5 4975 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 4976 intel_connector->panel.backlight_power = intel_edp_backlight_power;
6517d273 4977 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 4978
4979 return true;
4980}
4981
16c25533 4982bool
f0fec3f2
PZ		 4983intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4984 struct intel_connector *intel_connector)
a4fc5ed6 4985{
f0fec3f2
PZ		 4986 struct drm_connector *connector = &intel_connector->base;
4987 struct intel_dp *intel_dp = &intel_dig_port->dp;
4988 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4989 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4990 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4991 enum port port = intel_dig_port->port;
0b99836f 4992 int type;
a4fc5ed6 4993
a4a5d2f8
VS		 4994 intel_dp->pps_pipe = INVALID_PIPE;
4995
ec5b01dd 4996 /* intel_dp vfuncs */
b6b5e383
DL		 4997 if (INTEL_INFO(dev)->gen >= 9)
4998 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
4999 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5000 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5001 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5002 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5003 else if (HAS_PCH_SPLIT(dev))
5004 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5005 else
5006 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5007
b9ca5fad
DL		 5008 if (INTEL_INFO(dev)->gen >= 9)
5009 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5010 else
5011 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5012
0767935e
DV		 5013 /* Preserve the current hw state. */
5014 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5015 intel_dp->attached_connector = intel_connector;
3d3dc149 5016
3b32a35b 5017 if (intel_dp_is_edp(dev, port))
b329530c 5018 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5019 else
5020 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5021
f7d24902
ID		 5022 /*
5023 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5024 * for DP the encoder type can be set by the caller to
5025 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5026 */
5027 if (type == DRM_MODE_CONNECTOR_eDP)
5028 intel_encoder->type = INTEL_OUTPUT_EDP;
5029
c17ed5b5
VS		 5030 /* eDP only on port B and/or C on vlv/chv */
5031 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5032 port != PORT_B && port != PORT_C))
5033 return false;
5034
e7281eab
ID		 5035 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5036 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5037 port_name(port));
5038
b329530c 5039 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5040 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5041
a4fc5ed6
KP		 5042 connector->interlace_allowed = true;
5043 connector->doublescan_allowed = 0;
5044
f0fec3f2 5045 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5046 edp_panel_vdd_work);
a4fc5ed6 5047
df0e9248 5048 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5049 drm_connector_register(connector);
a4fc5ed6 5050
affa9354 5051 if (HAS_DDI(dev))
bcbc889b
PZ		 5052 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5053 else
5054 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5055 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5056
0b99836f 5057 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5058 switch (port) {
5059 case PORT_A:
1d843f9d 5060 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5061 break;
5062 case PORT_B:
1d843f9d 5063 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5064 break;
5065 case PORT_C:
1d843f9d 5066 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5067 break;
5068 case PORT_D:
1d843f9d 5069 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5070 break;
5071 default:
ad1c0b19 5072 BUG();
5eb08b69
ZW		 5073 }
5074
dada1a9f 5075 if (is_edp(intel_dp)) {
773538e8 5076 pps_lock(intel_dp);
1e74a324
VS		 5077 intel_dp_init_panel_power_timestamps(intel_dp);
5078 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5079 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5080 else
36b5f425 5081 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5082 pps_unlock(intel_dp);
dada1a9f 5083 }
0095e6dc 5084
9d1a1031 5085 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5086
0e32b39c
DA		 5087 /* init MST on ports that can support it */
5088 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5089 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5090 intel_dp_mst_encoder_init(intel_dig_port,
5091 intel_connector->base.base.id);
0e32b39c
DA		 5092 }
5093 }
5094
36b5f425 5095 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5096 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5097 if (is_edp(intel_dp)) {
5098 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5099 /*
5100 * vdd might still be enabled do to the delayed vdd off.
5101 * Make sure vdd is actually turned off here.
5102 */
773538e8 5103 pps_lock(intel_dp);
4be73780 5104 edp_panel_vdd_off_sync(intel_dp);
773538e8 5105 pps_unlock(intel_dp);
15b1d171 5106 }
34ea3d38 5107 drm_connector_unregister(connector);
b2f246a8 5108 drm_connector_cleanup(connector);
16c25533 5109 return false;
b2f246a8 5110 }
32f9d658 5111
f684960e
CW		 5112 intel_dp_add_properties(intel_dp, connector);
5113
a4fc5ed6
KP		 5114 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5115 * 0xd. Failure to do so will result in spurious interrupts being
5116 * generated on the port when a cable is not attached.
5117 */
5118 if (IS_G4X(dev) && !IS_GM45(dev)) {
5119 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5120 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5121 }
16c25533
PZ		 5122
5123 return true;
a4fc5ed6 5124}
f0fec3f2
PZ		 5125
5126void
5127intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5128{
13cf5504 5129 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5130 struct intel_digital_port *intel_dig_port;
5131 struct intel_encoder *intel_encoder;
5132 struct drm_encoder *encoder;
5133 struct intel_connector *intel_connector;
5134
b14c5679 5135 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5136 if (!intel_dig_port)
5137 return;
5138
b14c5679 5139 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5140 if (!intel_connector) {
5141 kfree(intel_dig_port);
5142 return;
5143 }
5144
5145 intel_encoder = &intel_dig_port->base;
5146 encoder = &intel_encoder->base;
5147
5148 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5149 DRM_MODE_ENCODER_TMDS);
5150
5bfe2ac0 5151 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5152 intel_encoder->disable = intel_disable_dp;
00c09d70 5153 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5154 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5155 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5156 if (IS_CHERRYVIEW(dev)) {
9197c88b 5157 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5158 intel_encoder->pre_enable = chv_pre_enable_dp;
5159 intel_encoder->enable = vlv_enable_dp;
580d3811 5160 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5161 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5162 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5163 intel_encoder->pre_enable = vlv_pre_enable_dp;
5164 intel_encoder->enable = vlv_enable_dp;
49277c31 5165 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5166 } else {
ecff4f3b
JN		 5167 intel_encoder->pre_enable = g4x_pre_enable_dp;
5168 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5169 if (INTEL_INFO(dev)->gen >= 5)
5170 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5171 }
f0fec3f2 5172
174edf1f 5173 intel_dig_port->port = port;
f0fec3f2
PZ		 5174 intel_dig_port->dp.output_reg = output_reg;
5175
00c09d70 5176 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5177 if (IS_CHERRYVIEW(dev)) {
5178 if (port == PORT_D)
5179 intel_encoder->crtc_mask = 1 << 2;
5180 else
5181 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5182 } else {
5183 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5184 }
bc079e8b 5185 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5186 intel_encoder->hot_plug = intel_dp_hot_plug;
5187
13cf5504
DA		 5188 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5189 dev_priv->hpd_irq_port[port] = intel_dig_port;
5190
15b1d171
PZ		 5191 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5192 drm_encoder_cleanup(encoder);
5193 kfree(intel_dig_port);
b2f246a8 5194 kfree(intel_connector);
15b1d171 5195 }
f0fec3f2 5196}
0e32b39c
DA		 5197
5198void intel_dp_mst_suspend(struct drm_device *dev)
5199{
5200 struct drm_i915_private *dev_priv = dev->dev_private;
5201 int i;
5202
5203 /* disable MST */
5204 for (i = 0; i < I915_MAX_PORTS; i++) {
5205 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5206 if (!intel_dig_port)
5207 continue;
5208
5209 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5210 if (!intel_dig_port->dp.can_mst)
5211 continue;
5212 if (intel_dig_port->dp.is_mst)
5213 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5214 }
5215 }
5216}
5217
5218void intel_dp_mst_resume(struct drm_device *dev)
5219{
5220 struct drm_i915_private *dev_priv = dev->dev_private;
5221 int i;
5222
5223 for (i = 0; i < I915_MAX_PORTS; i++) {
5224 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5225 if (!intel_dig_port)
5226 continue;
5227 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5228 int ret;
5229
5230 if (!intel_dig_port->dp.can_mst)
5231 continue;
5232
5233 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5234 if (ret != 0) {
5235 intel_dp_check_mst_status(&intel_dig_port->dp);
5236 }
5237 }
5238 }
5239}
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