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drm/i915/bxt: Fix HDMI DPLL configuration
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf 50struct dp_link_dpll {
840b32b7 51 int clock;
9dd4ffdf
CML		 52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
840b32b7 56 { 162000,
9dd4ffdf 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
840b32b7 58 { 270000,
9dd4ffdf
CML		 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
840b32b7 63 { 162000,
9dd4ffdf 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
840b32b7 65 { 270000,
9dd4ffdf
CML		 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5 69static const struct dp_link_dpll vlv_dpll[] = {
840b32b7 70 { 162000,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
840b32b7 72 { 270000,
65ce4bf5
CML		 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
840b32b7 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
ef9348c8 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
840b32b7 88 { 270000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
840b32b7 90 { 540000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8
CML		 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15
VS		 97 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 99
cfcb0fc9
JB		 100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
da63a9f2
PZ		 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 112}
113
68b4d824 114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 115{
68b4d824
ID		 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 119}
120
df0e9248
CW		 121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
fa90ecef 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 124}
125
ea5b213a 126static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
f21a2198 132static void intel_dp_unset_edid(struct intel_dp *intel_dp);
a4fc5ed6 133
ed4e9c1d
VS		 134static int
135intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 136{
7183dc29 137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 138
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
141 case DP_LINK_BW_2_7:
1db10e28 142 case DP_LINK_BW_5_4:
d4eead50 143 break;
a4fc5ed6 144 default:
d4eead50
ID		 145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
146 max_link_bw);
a4fc5ed6
KP		 147 max_link_bw = DP_LINK_BW_1_62;
148 break;
149 }
150 return max_link_bw;
151}
152
eeb6324d
PZ		 153static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
154{
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
eeb6324d
PZ		 156 u8 source_max, sink_max;
157
ccb1a831 158 source_max = intel_dig_port->max_lanes;
eeb6324d
PZ		 159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
160
161 return min(source_max, sink_max);
162}
163
cd9dde44
AJ		 164/*
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
167 *
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
169 *
170 * 270000 * 1 * 8 / 10 == 216000
171 *
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
176 *
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
179 */
180
a4fc5ed6 181static int
c898261c 182intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 183{
cd9dde44 184 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 185}
186
fe27d53e
DA		 187static int
188intel_dp_max_data_rate(int max_link_clock, int max_lanes)
189{
190 return (max_link_clock * max_lanes * 8) / 10;
191}
192
70ec0645
MK		 193static int
194intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
195{
196 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
197 struct intel_encoder *encoder = &intel_dig_port->base;
198 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
199 int max_dotclk = dev_priv->max_dotclk_freq;
200 int ds_max_dotclk;
201
202 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
203
204 if (type != DP_DS_PORT_TYPE_VGA)
205 return max_dotclk;
206
207 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
208 intel_dp->downstream_ports);
209
210 if (ds_max_dotclk != 0)
211 max_dotclk = min(max_dotclk, ds_max_dotclk);
212
213 return max_dotclk;
214}
215
c19de8eb 216static enum drm_mode_status
a4fc5ed6
KP		 217intel_dp_mode_valid(struct drm_connector *connector,
218 struct drm_display_mode *mode)
219{
df0e9248 220 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 221 struct intel_connector *intel_connector = to_intel_connector(connector);
222 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 223 int target_clock = mode->clock;
224 int max_rate, mode_rate, max_lanes, max_link_clock;
70ec0645
MK		 225 int max_dotclk;
226
227 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
a4fc5ed6 228
dd06f90e
JN		 229 if (is_edp(intel_dp) && fixed_mode) {
230 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 231 return MODE_PANEL;
232
dd06f90e 233 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 234 return MODE_PANEL;
03afc4a2
DV		 235
236 target_clock = fixed_mode->clock;
7de56f43
ZY		 237 }
238
50fec21a 239 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 240 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 241
242 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
243 mode_rate = intel_dp_link_required(target_clock, 18);
244
799487f5 245 if (mode_rate > max_rate || target_clock > max_dotclk)
c4867936 246 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 247
248 if (mode->clock < 10000)
249 return MODE_CLOCK_LOW;
250
0af78a2b
DV		 251 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
252 return MODE_H_ILLEGAL;
253
a4fc5ed6
KP		 254 return MODE_OK;
255}
256
a4f1289e 257uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 258{
259 int i;
260 uint32_t v = 0;
261
262 if (src_bytes > 4)
263 src_bytes = 4;
264 for (i = 0; i < src_bytes; i++)
265 v |= ((uint32_t) src[i]) << ((3-i) * 8);
266 return v;
267}
268
c2af70e2 269static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 270{
271 int i;
272 if (dst_bytes > 4)
273 dst_bytes = 4;
274 for (i = 0; i < dst_bytes; i++)
275 dst[i] = src >> ((3-i) * 8);
276}
277
bf13e81b
JN		 278static void
279intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 280 struct intel_dp *intel_dp);
bf13e81b
JN		 281static void
282intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 283 struct intel_dp *intel_dp);
335f752b
ID		 284static void
285intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
bf13e81b 286
773538e8
VS		 287static void pps_lock(struct intel_dp *intel_dp)
288{
289 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
290 struct intel_encoder *encoder = &intel_dig_port->base;
291 struct drm_device *dev = encoder->base.dev;
fac5e23e 292 struct drm_i915_private *dev_priv = to_i915(dev);
773538e8
VS		 293 enum intel_display_power_domain power_domain;
294
295 /*
296 * See vlv_power_sequencer_reset() why we need
297 * a power domain reference here.
298 */
25f78f58 299 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 300 intel_display_power_get(dev_priv, power_domain);
301
302 mutex_lock(&dev_priv->pps_mutex);
303}
304
305static void pps_unlock(struct intel_dp *intel_dp)
306{
307 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
308 struct intel_encoder *encoder = &intel_dig_port->base;
309 struct drm_device *dev = encoder->base.dev;
fac5e23e 310 struct drm_i915_private *dev_priv = to_i915(dev);
773538e8
VS		 311 enum intel_display_power_domain power_domain;
312
313 mutex_unlock(&dev_priv->pps_mutex);
314
25f78f58 315 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 316 intel_display_power_put(dev_priv, power_domain);
317}
318
961a0db0
VS		 319static void
320vlv_power_sequencer_kick(struct intel_dp *intel_dp)
321{
322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
323 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 324 struct drm_i915_private *dev_priv = to_i915(dev);
961a0db0 325 enum pipe pipe = intel_dp->pps_pipe;
0047eedc
VS		 326 bool pll_enabled, release_cl_override = false;
327 enum dpio_phy phy = DPIO_PHY(pipe);
328 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
961a0db0
VS		 329 uint32_t DP;
330
331 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
332 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
333 pipe_name(pipe), port_name(intel_dig_port->port)))
334 return;
335
336 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
337 pipe_name(pipe), port_name(intel_dig_port->port));
338
339 /* Preserve the BIOS-computed detected bit. This is
340 * supposed to be read-only.
341 */
342 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
343 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
344 DP |= DP_PORT_WIDTH(1);
345 DP |= DP_LINK_TRAIN_PAT_1;
346
347 if (IS_CHERRYVIEW(dev))
348 DP |= DP_PIPE_SELECT_CHV(pipe);
349 else if (pipe == PIPE_B)
350 DP |= DP_PIPEB_SELECT;
351
d288f65f
VS		 352 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
353
354 /*
355 * The DPLL for the pipe must be enabled for this to work.
356 * So enable temporarily it if it's not already enabled.
357 */
0047eedc
VS		 358 if (!pll_enabled) {
359 release_cl_override = IS_CHERRYVIEW(dev) &&
360 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
361
3f36b937
TU		 362 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
363 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
364 DRM_ERROR("Failed to force on pll for pipe %c!\n",
365 pipe_name(pipe));
366 return;
367 }
0047eedc 368 }
d288f65f 369
961a0db0
VS		 370 /*
371 * Similar magic as in intel_dp_enable_port().
372 * We _must_ do this port enable + disable trick
373 * to make this power seqeuencer lock onto the port.
374 * Otherwise even VDD force bit won't work.
375 */
376 I915_WRITE(intel_dp->output_reg, DP);
377 POSTING_READ(intel_dp->output_reg);
378
379 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
380 POSTING_READ(intel_dp->output_reg);
381
382 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
383 POSTING_READ(intel_dp->output_reg);
d288f65f 384
0047eedc 385 if (!pll_enabled) {
d288f65f 386 vlv_force_pll_off(dev, pipe);
0047eedc
VS		 387
388 if (release_cl_override)
389 chv_phy_powergate_ch(dev_priv, phy, ch, false);
390 }
961a0db0
VS		 391}
392
bf13e81b
JN		 393static enum pipe
394vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
395{
396 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b 397 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 398 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8
VS		 399 struct intel_encoder *encoder;
400 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 401 enum pipe pipe;
bf13e81b 402
e39b999a 403 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 404
a8c3344e
VS		 405 /* We should never land here with regular DP ports */
406 WARN_ON(!is_edp(intel_dp));
407
a4a5d2f8
VS		 408 if (intel_dp->pps_pipe != INVALID_PIPE)
409 return intel_dp->pps_pipe;
410
411 /*
412 * We don't have power sequencer currently.
413 * Pick one that's not used by other ports.
414 */
19c8054c 415 for_each_intel_encoder(dev, encoder) {
a4a5d2f8
VS		 416 struct intel_dp *tmp;
417
418 if (encoder->type != INTEL_OUTPUT_EDP)
419 continue;
420
421 tmp = enc_to_intel_dp(&encoder->base);
422
423 if (tmp->pps_pipe != INVALID_PIPE)
424 pipes &= ~(1 << tmp->pps_pipe);
425 }
426
427 /*
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
430 */
431 if (WARN_ON(pipes == 0))
a8c3344e
VS		 432 pipe = PIPE_A;
433 else
434 pipe = ffs(pipes) - 1;
a4a5d2f8 435
a8c3344e
VS		 436 vlv_steal_power_sequencer(dev, pipe);
437 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 438
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp->pps_pipe),
441 port_name(intel_dig_port->port));
442
443 /* init power sequencer on this pipe and port */
36b5f425
VS		 444 intel_dp_init_panel_power_sequencer(dev, intel_dp);
445 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 446
961a0db0
VS		 447 /*
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
450 */
451 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 452
453 return intel_dp->pps_pipe;
454}
455
78597996
ID		 456static int
457bxt_power_sequencer_idx(struct intel_dp *intel_dp)
458{
459 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
460 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 461 struct drm_i915_private *dev_priv = to_i915(dev);
78597996
ID		 462
463 lockdep_assert_held(&dev_priv->pps_mutex);
464
465 /* We should never land here with regular DP ports */
466 WARN_ON(!is_edp(intel_dp));
467
468 /*
469 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
470 * mapping needs to be retrieved from VBT, for now just hard-code to
471 * use instance #0 always.
472 */
473 if (!intel_dp->pps_reset)
474 return 0;
475
476 intel_dp->pps_reset = false;
477
478 /*
479 * Only the HW needs to be reprogrammed, the SW state is fixed and
480 * has been setup during connector init.
481 */
482 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
483
484 return 0;
485}
486
6491ab27
VS		 487typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
488 enum pipe pipe);
489
490static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
491 enum pipe pipe)
492{
44cb734c 493 return I915_READ(PP_STATUS(pipe)) & PP_ON;
6491ab27
VS		 494}
495
496static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
497 enum pipe pipe)
498{
44cb734c 499 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
6491ab27
VS		 500}
501
502static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
503 enum pipe pipe)
504{
505 return true;
506}
bf13e81b 507
a4a5d2f8 508static enum pipe
6491ab27
VS		 509vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
510 enum port port,
511 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 512{
513 enum pipe pipe;
bf13e81b 514
bf13e81b 515 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
44cb734c 516 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
bf13e81b 517 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 518
519 if (port_sel != PANEL_PORT_SELECT_VLV(port))
520 continue;
521
6491ab27
VS		 522 if (!pipe_check(dev_priv, pipe))
523 continue;
524
a4a5d2f8 525 return pipe;
bf13e81b
JN		 526 }
527
a4a5d2f8
VS		 528 return INVALID_PIPE;
529}
530
531static void
532vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
533{
534 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
535 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 536 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8
VS		 537 enum port port = intel_dig_port->port;
538
539 lockdep_assert_held(&dev_priv->pps_mutex);
540
541 /* try to find a pipe with this port selected */
6491ab27
VS		 542 /* first pick one where the panel is on */
543 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
544 vlv_pipe_has_pp_on);
545 /* didn't find one? pick one where vdd is on */
546 if (intel_dp->pps_pipe == INVALID_PIPE)
547 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
548 vlv_pipe_has_vdd_on);
549 /* didn't find one? pick one with just the correct port */
550 if (intel_dp->pps_pipe == INVALID_PIPE)
551 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
552 vlv_pipe_any);
a4a5d2f8
VS		 553
554 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
555 if (intel_dp->pps_pipe == INVALID_PIPE) {
556 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
557 port_name(port));
558 return;
bf13e81b
JN		 559 }
560
a4a5d2f8
VS		 561 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
562 port_name(port), pipe_name(intel_dp->pps_pipe));
563
36b5f425
VS		 564 intel_dp_init_panel_power_sequencer(dev, intel_dp);
565 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 566}
567
78597996 568void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
773538e8 569{
91c8a326 570 struct drm_device *dev = &dev_priv->drm;
773538e8
VS		 571 struct intel_encoder *encoder;
572
78597996
ID		 573 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
574 !IS_BROXTON(dev)))
773538e8
VS		 575 return;
576
577 /*
578 * We can't grab pps_mutex here due to deadlock with power_domain
579 * mutex when power_domain functions are called while holding pps_mutex.
580 * That also means that in order to use pps_pipe the code needs to
581 * hold both a power domain reference and pps_mutex, and the power domain
582 * reference get/put must be done while _not_ holding pps_mutex.
583 * pps_{lock,unlock}() do these steps in the correct order, so one
584 * should use them always.
585 */
586
19c8054c 587 for_each_intel_encoder(dev, encoder) {
773538e8
VS		 588 struct intel_dp *intel_dp;
589
590 if (encoder->type != INTEL_OUTPUT_EDP)
591 continue;
592
593 intel_dp = enc_to_intel_dp(&encoder->base);
78597996
ID		 594 if (IS_BROXTON(dev))
595 intel_dp->pps_reset = true;
596 else
597 intel_dp->pps_pipe = INVALID_PIPE;
773538e8 598 }
bf13e81b
JN		 599}
600
8e8232d5
ID		 601struct pps_registers {
602 i915_reg_t pp_ctrl;
603 i915_reg_t pp_stat;
604 i915_reg_t pp_on;
605 i915_reg_t pp_off;
606 i915_reg_t pp_div;
607};
608
609static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
610 struct intel_dp *intel_dp,
611 struct pps_registers *regs)
612{
44cb734c
ID		 613 int pps_idx = 0;
614
8e8232d5
ID		 615 memset(regs, 0, sizeof(*regs));
616
44cb734c
ID		 617 if (IS_BROXTON(dev_priv))
618 pps_idx = bxt_power_sequencer_idx(intel_dp);
619 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
620 pps_idx = vlv_power_sequencer_pipe(intel_dp);
8e8232d5 621
44cb734c
ID		 622 regs->pp_ctrl = PP_CONTROL(pps_idx);
623 regs->pp_stat = PP_STATUS(pps_idx);
624 regs->pp_on = PP_ON_DELAYS(pps_idx);
625 regs->pp_off = PP_OFF_DELAYS(pps_idx);
626 if (!IS_BROXTON(dev_priv))
627 regs->pp_div = PP_DIVISOR(pps_idx);
8e8232d5
ID		 628}
629
f0f59a00
VS		 630static i915_reg_t
631_pp_ctrl_reg(struct intel_dp *intel_dp)
bf13e81b 632{
8e8232d5 633 struct pps_registers regs;
bf13e81b 634
8e8232d5
ID		 635 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
636 &regs);
637
638 return regs.pp_ctrl;
bf13e81b
JN		 639}
640
f0f59a00
VS		 641static i915_reg_t
642_pp_stat_reg(struct intel_dp *intel_dp)
bf13e81b 643{
8e8232d5 644 struct pps_registers regs;
bf13e81b 645
8e8232d5
ID		 646 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
647 &regs);
648
649 return regs.pp_stat;
bf13e81b
JN		 650}
651
01527b31
CT		 652/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
653 This function only applicable when panel PM state is not to be tracked */
654static int edp_notify_handler(struct notifier_block *this, unsigned long code,
655 void *unused)
656{
657 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
658 edp_notifier);
659 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 660 struct drm_i915_private *dev_priv = to_i915(dev);
01527b31
CT		 661
662 if (!is_edp(intel_dp) || code != SYS_RESTART)
663 return 0;
664
773538e8 665 pps_lock(intel_dp);
e39b999a 666
666a4537 667 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e39b999a 668 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
f0f59a00 669 i915_reg_t pp_ctrl_reg, pp_div_reg;
649636ef 670 u32 pp_div;
e39b999a 671
44cb734c
ID		 672 pp_ctrl_reg = PP_CONTROL(pipe);
673 pp_div_reg = PP_DIVISOR(pipe);
01527b31
CT		 674 pp_div = I915_READ(pp_div_reg);
675 pp_div &= PP_REFERENCE_DIVIDER_MASK;
676
677 /* 0x1F write to PP_DIV_REG sets max cycle delay */
678 I915_WRITE(pp_div_reg, pp_div | 0x1F);
679 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
680 msleep(intel_dp->panel_power_cycle_delay);
681 }
682
773538e8 683 pps_unlock(intel_dp);
e39b999a 684
01527b31
CT		 685 return 0;
686}
687
4be73780 688static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 689{
30add22d 690 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 691 struct drm_i915_private *dev_priv = to_i915(dev);
ebf33b18 692
e39b999a
VS		 693 lockdep_assert_held(&dev_priv->pps_mutex);
694
666a4537 695 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 696 intel_dp->pps_pipe == INVALID_PIPE)
697 return false;
698
bf13e81b 699 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 700}
701
4be73780 702static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 703{
30add22d 704 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 705 struct drm_i915_private *dev_priv = to_i915(dev);
ebf33b18 706
e39b999a
VS		 707 lockdep_assert_held(&dev_priv->pps_mutex);
708
666a4537 709 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 710 intel_dp->pps_pipe == INVALID_PIPE)
711 return false;
712
773538e8 713 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 714}
715
9b984dae
KP		 716static void
717intel_dp_check_edp(struct intel_dp *intel_dp)
718{
30add22d 719 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 720 struct drm_i915_private *dev_priv = to_i915(dev);
ebf33b18 721
9b984dae
KP		 722 if (!is_edp(intel_dp))
723 return;
453c5420 724
4be73780 725 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 726 WARN(1, "eDP powered off while attempting aux channel communication.\n");
727 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 728 I915_READ(_pp_stat_reg(intel_dp)),
729 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 730 }
731}
732
9ee32fea
DV		 733static uint32_t
734intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
735{
736 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
737 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 738 struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00 739 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 740 uint32_t status;
741 bool done;
742
ef04f00d 743#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 744 if (has_aux_irq)
b18ac466 745 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 746 msecs_to_jiffies_timeout(10));
9ee32fea 747 else
713a6b66 748 done = wait_for(C, 10) == 0;
9ee32fea
DV		 749 if (!done)
750 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
751 has_aux_irq);
752#undef C
753
754 return status;
755}
756
6ffb1be7 757static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 758{
174edf1f 759 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
e7dc33f3 760 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
9ee32fea 761
a457f54b
VS		 762 if (index)
763 return 0;
764
ec5b01dd
DL		 765 /*
766 * The clock divider is based off the hrawclk, and would like to run at
a457f54b 767 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
a4fc5ed6 768 */
a457f54b 769 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 770}
771
772static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
773{
774 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 775 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd
DL		 776
777 if (index)
778 return 0;
779
a457f54b
VS		 780 /*
781 * The clock divider is based off the cdclk or PCH rawclk, and would
782 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
783 * divide by 2000 and use that
784 */
e7dc33f3 785 if (intel_dig_port->port == PORT_A)
fce18c4c 786 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
e7dc33f3
VS		 787 else
788 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 789}
790
791static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
792{
793 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 794 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd 795
a457f54b 796 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
2c55c336 797 /* Workaround for non-ULT HSW */
bc86625a
CW		 798 switch (index) {
799 case 0: return 63;
800 case 1: return 72;
801 default: return 0;
802 }
2c55c336 803 }
a457f54b
VS		 804
805 return ilk_get_aux_clock_divider(intel_dp, index);
b84a1cf8
RV		 806}
807
b6b5e383
DL		 808static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
809{
810 /*
811 * SKL doesn't need us to program the AUX clock divider (Hardware will
812 * derive the clock from CDCLK automatically). We still implement the
813 * get_aux_clock_divider vfunc to plug-in into the existing code.
814 */
815 return index ? 0 : 1;
816}
817
6ffb1be7
VS		 818static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
819 bool has_aux_irq,
820 int send_bytes,
821 uint32_t aux_clock_divider)
5ed12a19
DL		 822{
823 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
824 struct drm_device *dev = intel_dig_port->base.base.dev;
825 uint32_t precharge, timeout;
826
827 if (IS_GEN6(dev))
828 precharge = 3;
829 else
830 precharge = 5;
831
f3c6a3a7 832 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
5ed12a19
DL		 833 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
834 else
835 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
836
837 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 838 DP_AUX_CH_CTL_DONE |
5ed12a19 839 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 840 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 841 timeout |
788d4433 842 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 843 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
844 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 845 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 846}
847
b9ca5fad
DL		 848static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
849 bool has_aux_irq,
850 int send_bytes,
851 uint32_t unused)
852{
853 return DP_AUX_CH_CTL_SEND_BUSY |
854 DP_AUX_CH_CTL_DONE |
855 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
856 DP_AUX_CH_CTL_TIME_OUT_ERROR |
857 DP_AUX_CH_CTL_TIME_OUT_1600us |
858 DP_AUX_CH_CTL_RECEIVE_ERROR |
859 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
d4dcbdce 860 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
b9ca5fad
DL		 861 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
862}
863
b84a1cf8
RV		 864static int
865intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 866 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 867 uint8_t *recv, int recv_size)
868{
869 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
870 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 871 struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00 872 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
bc86625a 873 uint32_t aux_clock_divider;
b84a1cf8
RV		 874 int i, ret, recv_bytes;
875 uint32_t status;
5ed12a19 876 int try, clock = 0;
4e6b788c 877 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 878 bool vdd;
879
773538e8 880 pps_lock(intel_dp);
e39b999a 881
72c3500a
VS		 882 /*
883 * We will be called with VDD already enabled for dpcd/edid/oui reads.
884 * In such cases we want to leave VDD enabled and it's up to upper layers
885 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
886 * ourselves.
887 */
1e0560e0 888 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 889
890 /* dp aux is extremely sensitive to irq latency, hence request the
891 * lowest possible wakeup latency and so prevent the cpu from going into
892 * deep sleep states.
893 */
894 pm_qos_update_request(&dev_priv->pm_qos, 0);
895
896 intel_dp_check_edp(intel_dp);
5eb08b69 897
11bee43e
JB		 898 /* Try to wait for any previous AUX channel activity */
899 for (try = 0; try < 3; try++) {
ef04f00d 900 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 901 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
902 break;
903 msleep(1);
904 }
905
906 if (try == 3) {
02196c77
MK		 907 static u32 last_status = -1;
908 const u32 status = I915_READ(ch_ctl);
909
910 if (status != last_status) {
911 WARN(1, "dp_aux_ch not started status 0x%08x\n",
912 status);
913 last_status = status;
914 }
915
9ee32fea
DV		 916 ret = -EBUSY;
917 goto out;
4f7f7b7e
CW		 918 }
919
46a5ae9f
PZ		 920 /* Only 5 data registers! */
921 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
922 ret = -E2BIG;
923 goto out;
924 }
925
ec5b01dd 926 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 927 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
928 has_aux_irq,
929 send_bytes,
930 aux_clock_divider);
5ed12a19 931
bc86625a
CW		 932 /* Must try at least 3 times according to DP spec */
933 for (try = 0; try < 5; try++) {
934 /* Load the send data into the aux channel data registers */
935 for (i = 0; i < send_bytes; i += 4)
330e20ec 936 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
a4f1289e
RV		 937 intel_dp_pack_aux(send + i,
938 send_bytes - i));
bc86625a
CW		 939
940 /* Send the command and wait for it to complete */
5ed12a19 941 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 942
943 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
944
945 /* Clear done status and any errors */
946 I915_WRITE(ch_ctl,
947 status |
948 DP_AUX_CH_CTL_DONE |
949 DP_AUX_CH_CTL_TIME_OUT_ERROR |
950 DP_AUX_CH_CTL_RECEIVE_ERROR);
951
74ebf294 952 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 953 continue;
74ebf294
TP		 954
955 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
956 * 400us delay required for errors and timeouts
957 * Timeout errors from the HW already meet this
958 * requirement so skip to next iteration
959 */
960 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
961 usleep_range(400, 500);
bc86625a 962 continue;
74ebf294 963 }
bc86625a 964 if (status & DP_AUX_CH_CTL_DONE)
e058c945 965 goto done;
bc86625a 966 }
a4fc5ed6
KP		 967 }
968
a4fc5ed6 969 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 970 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 971 ret = -EBUSY;
972 goto out;
a4fc5ed6
KP		 973 }
974
e058c945 975done:
a4fc5ed6
KP		 976 /* Check for timeout or receive error.
977 * Timeouts occur when the sink is not connected
978 */
a5b3da54 979 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 980 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 981 ret = -EIO;
982 goto out;
a5b3da54 983 }
1ae8c0a5
KP		 984
985 /* Timeouts occur when the device isn't connected, so they're
986 * "normal" -- don't fill the kernel log with these */
a5b3da54 987 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 988 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 989 ret = -ETIMEDOUT;
990 goto out;
a4fc5ed6
KP		 991 }
992
993 /* Unload any bytes sent back from the other side */
994 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
995 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
14e01889
RV		 996
997 /*
998 * By BSpec: "Message sizes of 0 or >20 are not allowed."
999 * We have no idea of what happened so we return -EBUSY so
1000 * drm layer takes care for the necessary retries.
1001 */
1002 if (recv_bytes == 0 || recv_bytes > 20) {
1003 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1004 recv_bytes);
1005 /*
1006 * FIXME: This patch was created on top of a series that
1007 * organize the retries at drm level. There EBUSY should
1008 * also take care for 1ms wait before retrying.
1009 * That aux retries re-org is still needed and after that is
1010 * merged we remove this sleep from here.
1011 */
1012 usleep_range(1000, 1500);
1013 ret = -EBUSY;
1014 goto out;
1015 }
1016
a4fc5ed6
KP		 1017 if (recv_bytes > recv_size)
1018 recv_bytes = recv_size;
0206e353 1019
4f7f7b7e 1020 for (i = 0; i < recv_bytes; i += 4)
330e20ec 1021 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
a4f1289e 1022 recv + i, recv_bytes - i);
a4fc5ed6 1023
9ee32fea
DV		 1024 ret = recv_bytes;
1025out:
1026 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1027
884f19e9
JN		 1028 if (vdd)
1029 edp_panel_vdd_off(intel_dp, false);
1030
773538e8 1031 pps_unlock(intel_dp);
e39b999a 1032
9ee32fea 1033 return ret;
a4fc5ed6
KP		 1034}
1035
a6c8aff0
JN		 1036#define BARE_ADDRESS_SIZE 3
1037#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 1038static ssize_t
1039intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 1040{
9d1a1031
JN		 1041 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1042 uint8_t txbuf[20], rxbuf[20];
1043 size_t txsize, rxsize;
a4fc5ed6 1044 int ret;
a4fc5ed6 1045
d2d9cbbd
VS		 1046 txbuf[0] = (msg->request << 4) |
1047 ((msg->address >> 16) & 0xf);
1048 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 1049 txbuf[2] = msg->address & 0xff;
1050 txbuf[3] = msg->size - 1;
46a5ae9f 1051
9d1a1031
JN		 1052 switch (msg->request & ~DP_AUX_I2C_MOT) {
1053 case DP_AUX_NATIVE_WRITE:
1054 case DP_AUX_I2C_WRITE:
c1e74122 1055 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
a6c8aff0 1056 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 1057 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 1058
9d1a1031
JN		 1059 if (WARN_ON(txsize > 20))
1060 return -E2BIG;
a4fc5ed6 1061
dd788090
VS		 1062 WARN_ON(!msg->buffer != !msg->size);
1063
d81a67cc
ID		 1064 if (msg->buffer)
1065 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 1066
9d1a1031
JN		 1067 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1068 if (ret > 0) {
1069 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 1070
a1ddefd8
JN		 1071 if (ret > 1) {
1072 /* Number of bytes written in a short write. */
1073 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1074 } else {
1075 /* Return payload size. */
1076 ret = msg->size;
1077 }
9d1a1031
JN		 1078 }
1079 break;
46a5ae9f 1080
9d1a1031
JN		 1081 case DP_AUX_NATIVE_READ:
1082 case DP_AUX_I2C_READ:
a6c8aff0 1083 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 1084 rxsize = msg->size + 1;
a4fc5ed6 1085
9d1a1031
JN		 1086 if (WARN_ON(rxsize > 20))
1087 return -E2BIG;
a4fc5ed6 1088
9d1a1031
JN		 1089 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1090 if (ret > 0) {
1091 msg->reply = rxbuf[0] >> 4;
1092 /*
1093 * Assume happy day, and copy the data. The caller is
1094 * expected to check msg->reply before touching it.
1095 *
1096 * Return payload size.
1097 */
1098 ret--;
1099 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1100 }
9d1a1031
JN		 1101 break;
1102
1103 default:
1104 ret = -EINVAL;
1105 break;
a4fc5ed6 1106 }
f51a44b9 1107
9d1a1031 1108 return ret;
a4fc5ed6
KP		 1109}
1110
f0f59a00
VS		 1111static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1112 enum port port)
da00bdcf
VS		 1113{
1114 switch (port) {
1115 case PORT_B:
1116 case PORT_C:
1117 case PORT_D:
1118 return DP_AUX_CH_CTL(port);
1119 default:
1120 MISSING_CASE(port);
1121 return DP_AUX_CH_CTL(PORT_B);
1122 }
1123}
1124
f0f59a00
VS		 1125static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1126 enum port port, int index)
330e20ec
VS		 1127{
1128 switch (port) {
1129 case PORT_B:
1130 case PORT_C:
1131 case PORT_D:
1132 return DP_AUX_CH_DATA(port, index);
1133 default:
1134 MISSING_CASE(port);
1135 return DP_AUX_CH_DATA(PORT_B, index);
1136 }
1137}
1138
f0f59a00
VS		 1139static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1140 enum port port)
da00bdcf
VS		 1141{
1142 switch (port) {
1143 case PORT_A:
1144 return DP_AUX_CH_CTL(port);
1145 case PORT_B:
1146 case PORT_C:
1147 case PORT_D:
1148 return PCH_DP_AUX_CH_CTL(port);
1149 default:
1150 MISSING_CASE(port);
1151 return DP_AUX_CH_CTL(PORT_A);
1152 }
1153}
1154
f0f59a00
VS		 1155static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1156 enum port port, int index)
330e20ec
VS		 1157{
1158 switch (port) {
1159 case PORT_A:
1160 return DP_AUX_CH_DATA(port, index);
1161 case PORT_B:
1162 case PORT_C:
1163 case PORT_D:
1164 return PCH_DP_AUX_CH_DATA(port, index);
1165 default:
1166 MISSING_CASE(port);
1167 return DP_AUX_CH_DATA(PORT_A, index);
1168 }
1169}
1170
da00bdcf
VS		 1171/*
1172 * On SKL we don't have Aux for port E so we rely
1173 * on VBT to set a proper alternate aux channel.
1174 */
1175static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1176{
1177 const struct ddi_vbt_port_info *info =
1178 &dev_priv->vbt.ddi_port_info[PORT_E];
1179
1180 switch (info->alternate_aux_channel) {
1181 case DP_AUX_A:
1182 return PORT_A;
1183 case DP_AUX_B:
1184 return PORT_B;
1185 case DP_AUX_C:
1186 return PORT_C;
1187 case DP_AUX_D:
1188 return PORT_D;
1189 default:
1190 MISSING_CASE(info->alternate_aux_channel);
1191 return PORT_A;
1192 }
1193}
1194
f0f59a00
VS		 1195static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1196 enum port port)
da00bdcf
VS		 1197{
1198 if (port == PORT_E)
1199 port = skl_porte_aux_port(dev_priv);
1200
1201 switch (port) {
1202 case PORT_A:
1203 case PORT_B:
1204 case PORT_C:
1205 case PORT_D:
1206 return DP_AUX_CH_CTL(port);
1207 default:
1208 MISSING_CASE(port);
1209 return DP_AUX_CH_CTL(PORT_A);
1210 }
1211}
1212
f0f59a00
VS		 1213static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1214 enum port port, int index)
330e20ec
VS		 1215{
1216 if (port == PORT_E)
1217 port = skl_porte_aux_port(dev_priv);
1218
1219 switch (port) {
1220 case PORT_A:
1221 case PORT_B:
1222 case PORT_C:
1223 case PORT_D:
1224 return DP_AUX_CH_DATA(port, index);
1225 default:
1226 MISSING_CASE(port);
1227 return DP_AUX_CH_DATA(PORT_A, index);
1228 }
1229}
1230
f0f59a00
VS		 1231static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1232 enum port port)
330e20ec
VS		 1233{
1234 if (INTEL_INFO(dev_priv)->gen >= 9)
1235 return skl_aux_ctl_reg(dev_priv, port);
1236 else if (HAS_PCH_SPLIT(dev_priv))
1237 return ilk_aux_ctl_reg(dev_priv, port);
1238 else
1239 return g4x_aux_ctl_reg(dev_priv, port);
1240}
1241
f0f59a00
VS		 1242static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1243 enum port port, int index)
330e20ec
VS		 1244{
1245 if (INTEL_INFO(dev_priv)->gen >= 9)
1246 return skl_aux_data_reg(dev_priv, port, index);
1247 else if (HAS_PCH_SPLIT(dev_priv))
1248 return ilk_aux_data_reg(dev_priv, port, index);
1249 else
1250 return g4x_aux_data_reg(dev_priv, port, index);
1251}
1252
1253static void intel_aux_reg_init(struct intel_dp *intel_dp)
1254{
1255 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1256 enum port port = dp_to_dig_port(intel_dp)->port;
1257 int i;
1258
1259 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1260 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1261 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1262}
1263
9d1a1031 1264static void
a121f4e5
VS		 1265intel_dp_aux_fini(struct intel_dp *intel_dp)
1266{
a121f4e5
VS		 1267 kfree(intel_dp->aux.name);
1268}
1269
7a418e34 1270static void
b6339585 1271intel_dp_aux_init(struct intel_dp *intel_dp)
9d1a1031 1272{
33ad6626
JN		 1273 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1274 enum port port = intel_dig_port->port;
ab2c0672 1275
330e20ec 1276 intel_aux_reg_init(intel_dp);
7a418e34 1277 drm_dp_aux_init(&intel_dp->aux);
8316f337 1278
7a418e34 1279 /* Failure to allocate our preferred name is not critical */
a121f4e5 1280 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
9d1a1031 1281 intel_dp->aux.transfer = intel_dp_aux_transfer;
a4fc5ed6
KP		 1282}
1283
fc0f8e25 1284static int
12f6a2e2 1285intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1286{
94ca719e
VS		 1287 if (intel_dp->num_sink_rates) {
1288 *sink_rates = intel_dp->sink_rates;
1289 return intel_dp->num_sink_rates;
fc0f8e25 1290 }
12f6a2e2
VS		 1291
1292 *sink_rates = default_rates;
1293
1294 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1295}
1296
e588fa18 1297bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
ed63baaf 1298{
e588fa18
ACO		 1299 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1300 struct drm_device *dev = dig_port->base.base.dev;
1301
ed63baaf
TS		 1302 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1303 (INTEL_INFO(dev)->gen >= 9))
1304 return true;
1305 else
1306 return false;
1307}
1308
a8f3ef61 1309static int
e588fa18 1310intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
a8f3ef61 1311{
e588fa18
ACO		 1312 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1313 struct drm_device *dev = dig_port->base.base.dev;
af7080f5
TS		 1314 int size;
1315
64987fc5
SJ		 1316 if (IS_BROXTON(dev)) {
1317 *source_rates = bxt_rates;
af7080f5 1318 size = ARRAY_SIZE(bxt_rates);
ef11bdb3 1319 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
637a9c63 1320 *source_rates = skl_rates;
af7080f5
TS		 1321 size = ARRAY_SIZE(skl_rates);
1322 } else {
1323 *source_rates = default_rates;
1324 size = ARRAY_SIZE(default_rates);
a8f3ef61 1325 }
636280ba 1326
ed63baaf 1327 /* This depends on the fact that 5.4 is last value in the array */
e588fa18 1328 if (!intel_dp_source_supports_hbr2(intel_dp))
af7080f5 1329 size--;
636280ba 1330
af7080f5 1331 return size;
a8f3ef61
SJ		 1332}
1333
c6bb3538
DV		 1334static void
1335intel_dp_set_clock(struct intel_encoder *encoder,
840b32b7 1336 struct intel_crtc_state *pipe_config)
c6bb3538
DV		 1337{
1338 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1339 const struct dp_link_dpll *divisor = NULL;
1340 int i, count = 0;
c6bb3538
DV		 1341
1342 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1343 divisor = gen4_dpll;
1344 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1345 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1346 divisor = pch_dpll;
1347 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1348 } else if (IS_CHERRYVIEW(dev)) {
1349 divisor = chv_dpll;
1350 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1351 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1352 divisor = vlv_dpll;
1353 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1354 }
9dd4ffdf
CML		 1355
1356 if (divisor && count) {
1357 for (i = 0; i < count; i++) {
840b32b7 1358 if (pipe_config->port_clock == divisor[i].clock) {
9dd4ffdf
CML		 1359 pipe_config->dpll = divisor[i].dpll;
1360 pipe_config->clock_set = true;
1361 break;
1362 }
1363 }
c6bb3538
DV		 1364 }
1365}
1366
2ecae76a
VS		 1367static int intersect_rates(const int *source_rates, int source_len,
1368 const int *sink_rates, int sink_len,
94ca719e 1369 int *common_rates)
a8f3ef61
SJ		 1370{
1371 int i = 0, j = 0, k = 0;
1372
a8f3ef61
SJ		 1373 while (i < source_len && j < sink_len) {
1374 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1375 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1376 return k;
94ca719e 1377 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1378 ++k;
1379 ++i;
1380 ++j;
1381 } else if (source_rates[i] < sink_rates[j]) {
1382 ++i;
1383 } else {
1384 ++j;
1385 }
1386 }
1387 return k;
1388}
1389
94ca719e
VS		 1390static int intel_dp_common_rates(struct intel_dp *intel_dp,
1391 int *common_rates)
2ecae76a 1392{
2ecae76a
VS		 1393 const int *source_rates, *sink_rates;
1394 int source_len, sink_len;
1395
1396 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
e588fa18 1397 source_len = intel_dp_source_rates(intel_dp, &source_rates);
2ecae76a
VS		 1398
1399 return intersect_rates(source_rates, source_len,
1400 sink_rates, sink_len,
94ca719e 1401 common_rates);
2ecae76a
VS		 1402}
1403
0336400e
VS		 1404static void snprintf_int_array(char *str, size_t len,
1405 const int *array, int nelem)
1406{
1407 int i;
1408
1409 str[0] = '\0';
1410
1411 for (i = 0; i < nelem; i++) {
b2f505be 1412 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1413 if (r >= len)
1414 return;
1415 str += r;
1416 len -= r;
1417 }
1418}
1419
1420static void intel_dp_print_rates(struct intel_dp *intel_dp)
1421{
0336400e 1422 const int *source_rates, *sink_rates;
94ca719e
VS		 1423 int source_len, sink_len, common_len;
1424 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1425 char str[128]; /* FIXME: too big for stack? */
1426
1427 if ((drm_debug & DRM_UT_KMS) == 0)
1428 return;
1429
e588fa18 1430 source_len = intel_dp_source_rates(intel_dp, &source_rates);
0336400e
VS		 1431 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1432 DRM_DEBUG_KMS("source rates: %s\n", str);
1433
1434 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1435 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1436 DRM_DEBUG_KMS("sink rates: %s\n", str);
1437
94ca719e
VS		 1438 common_len = intel_dp_common_rates(intel_dp, common_rates);
1439 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1440 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1441}
1442
0e390a33
MK		 1443static void intel_dp_print_hw_revision(struct intel_dp *intel_dp)
1444{
1445 uint8_t rev;
1446 int len;
1447
1448 if ((drm_debug & DRM_UT_KMS) == 0)
1449 return;
1450
1451 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1452 DP_DWN_STRM_PORT_PRESENT))
1453 return;
1454
1455 len = drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_HW_REV, &rev, 1);
1456 if (len < 0)
1457 return;
1458
1459 DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev & 0xf0) >> 4, rev & 0xf);
1460}
1461
1a2724fa
MK		 1462static void intel_dp_print_sw_revision(struct intel_dp *intel_dp)
1463{
1464 uint8_t rev[2];
1465 int len;
1466
1467 if ((drm_debug & DRM_UT_KMS) == 0)
1468 return;
1469
1470 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1471 DP_DWN_STRM_PORT_PRESENT))
1472 return;
1473
1474 len = drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_SW_REV, &rev, 2);
1475 if (len < 0)
1476 return;
1477
1478 DRM_DEBUG_KMS("sink sw revision: %d.%d\n", rev[0], rev[1]);
1479}
1480
f4896f15 1481static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1482{
1483 int i = 0;
1484
1485 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1486 if (find == rates[i])
1487 break;
1488
1489 return i;
1490}
1491
50fec21a
VS		 1492int
1493intel_dp_max_link_rate(struct intel_dp *intel_dp)
1494{
1495 int rates[DP_MAX_SUPPORTED_RATES] = {};
1496 int len;
1497
94ca719e 1498 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1499 if (WARN_ON(len <= 0))
1500 return 162000;
1501
1354f734 1502 return rates[len - 1];
50fec21a
VS		 1503}
1504
ed4e9c1d
VS		 1505int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1506{
94ca719e 1507 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1508}
1509
94223d04
ACO		 1510void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1511 uint8_t *link_bw, uint8_t *rate_select)
04a60f9f
VS		 1512{
1513 if (intel_dp->num_sink_rates) {
1514 *link_bw = 0;
1515 *rate_select =
1516 intel_dp_rate_select(intel_dp, port_clock);
1517 } else {
1518 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1519 *rate_select = 0;
1520 }
1521}
1522
f580bea9
JN		 1523static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1524 struct intel_crtc_state *pipe_config)
f9bb705e
MK		 1525{
1526 int bpp, bpc;
1527
1528 bpp = pipe_config->pipe_bpp;
1529 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1530
1531 if (bpc > 0)
1532 bpp = min(bpp, 3*bpc);
1533
1534 return bpp;
1535}
1536
00c09d70 1537bool
5bfe2ac0 1538intel_dp_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 1539 struct intel_crtc_state *pipe_config,
1540 struct drm_connector_state *conn_state)
a4fc5ed6 1541{
5bfe2ac0 1542 struct drm_device *dev = encoder->base.dev;
fac5e23e 1543 struct drm_i915_private *dev_priv = to_i915(dev);
2d112de7 1544 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1545 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1546 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1547 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1548 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1549 int lane_count, clock;
56071a20 1550 int min_lane_count = 1;
eeb6324d 1551 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1552 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1553 int min_clock = 0;
a8f3ef61 1554 int max_clock;
083f9560 1555 int bpp, mode_rate;
ff9a6750 1556 int link_avail, link_clock;
94ca719e
VS		 1557 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1558 int common_len;
04a60f9f 1559 uint8_t link_bw, rate_select;
a8f3ef61 1560
94ca719e 1561 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1562
1563 /* No common link rates between source and sink */
94ca719e 1564 WARN_ON(common_len <= 0);
a8f3ef61 1565
94ca719e 1566 max_clock = common_len - 1;
a4fc5ed6 1567
bc7d38a4 1568 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1569 pipe_config->has_pch_encoder = true;
1570
f769cd24 1571 pipe_config->has_drrs = false;
9fcb1704 1572 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1573
dd06f90e
JN		 1574 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1575 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1576 adjusted_mode);
a1b2278e
CK		 1577
1578 if (INTEL_INFO(dev)->gen >= 9) {
1579 int ret;
e435d6e5 1580 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1581 if (ret)
1582 return ret;
1583 }
1584
b5667627 1585 if (HAS_GMCH_DISPLAY(dev))
2dd24552
JB		 1586 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1587 intel_connector->panel.fitting_mode);
1588 else
b074cec8
JB		 1589 intel_pch_panel_fitting(intel_crtc, pipe_config,
1590 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1591 }
1592
cb1793ce 1593 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1594 return false;
1595
083f9560 1596 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1597 "max bw %d pixel clock %iKHz\n",
94ca719e 1598 max_lane_count, common_rates[max_clock],
241bfc38 1599 adjusted_mode->crtc_clock);
083f9560 1600
36008365
DV		 1601 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1602 * bpc in between. */
f9bb705e 1603 bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
56071a20 1604 if (is_edp(intel_dp)) {
22ce5628
TS		 1605
1606 /* Get bpp from vbt only for panels that dont have bpp in edid */
1607 if (intel_connector->base.display_info.bpc == 0 &&
6aa23e65 1608 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
56071a20 1609 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
6aa23e65
JN		 1610 dev_priv->vbt.edp.bpp);
1611 bpp = dev_priv->vbt.edp.bpp;
56071a20
JN		 1612 }
1613
344c5bbc
JN		 1614 /*
1615 * Use the maximum clock and number of lanes the eDP panel
1616 * advertizes being capable of. The panels are generally
1617 * designed to support only a single clock and lane
1618 * configuration, and typically these values correspond to the
1619 * native resolution of the panel.
1620 */
1621 min_lane_count = max_lane_count;
1622 min_clock = max_clock;
7984211e 1623 }
657445fe 1624
36008365 1625 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1626 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1627 bpp);
36008365 1628
c6930992 1629 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1630 for (lane_count = min_lane_count;
1631 lane_count <= max_lane_count;
1632 lane_count <<= 1) {
1633
94ca719e 1634 link_clock = common_rates[clock];
36008365
DV		 1635 link_avail = intel_dp_max_data_rate(link_clock,
1636 lane_count);
1637
1638 if (mode_rate <= link_avail) {
1639 goto found;
1640 }
1641 }
1642 }
1643 }
c4867936 1644
36008365 1645 return false;
3685a8f3 1646
36008365 1647found:
55bc60db
VS		 1648 if (intel_dp->color_range_auto) {
1649 /*
1650 * See:
1651 * CEA-861-E - 5.1 Default Encoding Parameters
1652 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1653 */
0f2a2a75
VS		 1654 pipe_config->limited_color_range =
1655 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1656 } else {
1657 pipe_config->limited_color_range =
1658 intel_dp->limited_color_range;
55bc60db
VS		 1659 }
1660
90a6b7b0 1661 pipe_config->lane_count = lane_count;
a8f3ef61 1662
657445fe 1663 pipe_config->pipe_bpp = bpp;
94ca719e 1664 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1665
04a60f9f
VS		 1666 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1667 &link_bw, &rate_select);
1668
1669 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1670 link_bw, rate_select, pipe_config->lane_count,
ff9a6750 1671 pipe_config->port_clock, bpp);
36008365
DV		 1672 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1673 mode_rate, link_avail);
a4fc5ed6 1674
03afc4a2 1675 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1676 adjusted_mode->crtc_clock,
1677 pipe_config->port_clock,
03afc4a2 1678 &pipe_config->dp_m_n);
9d1a455b 1679
439d7ac0 1680 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1681 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1682 pipe_config->has_drrs = true;
439d7ac0
PB		 1683 intel_link_compute_m_n(bpp, lane_count,
1684 intel_connector->panel.downclock_mode->clock,
1685 pipe_config->port_clock,
1686 &pipe_config->dp_m2_n2);
1687 }
1688
14d41b3b
VS		 1689 /*
1690 * DPLL0 VCO may need to be adjusted to get the correct
1691 * clock for eDP. This will affect cdclk as well.
1692 */
1693 if (is_edp(intel_dp) &&
1694 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1695 int vco;
1696
1697 switch (pipe_config->port_clock / 2) {
1698 case 108000:
1699 case 216000:
63911d72 1700 vco = 8640000;
14d41b3b
VS		 1701 break;
1702 default:
63911d72 1703 vco = 8100000;
14d41b3b
VS		 1704 break;
1705 }
1706
1707 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1708 }
1709
a3c988ea 1710 if (!HAS_DDI(dev))
840b32b7 1711 intel_dp_set_clock(encoder, pipe_config);
c6bb3538 1712
03afc4a2 1713 return true;
a4fc5ed6
KP		 1714}
1715
901c2daf 1716void intel_dp_set_link_params(struct intel_dp *intel_dp,
dfa10480
ACO		 1717 int link_rate, uint8_t lane_count,
1718 bool link_mst)
901c2daf 1719{
dfa10480
ACO		 1720 intel_dp->link_rate = link_rate;
1721 intel_dp->lane_count = lane_count;
1722 intel_dp->link_mst = link_mst;
901c2daf
VS		 1723}
1724
85cb48a1
ML		 1725static void intel_dp_prepare(struct intel_encoder *encoder,
1726 struct intel_crtc_state *pipe_config)
a4fc5ed6 1727{
b934223d 1728 struct drm_device *dev = encoder->base.dev;
fac5e23e 1729 struct drm_i915_private *dev_priv = to_i915(dev);
b934223d 1730 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1731 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1732 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
85cb48a1 1733 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
a4fc5ed6 1734
dfa10480
ACO		 1735 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1736 pipe_config->lane_count,
1737 intel_crtc_has_type(pipe_config,
1738 INTEL_OUTPUT_DP_MST));
901c2daf 1739
417e822d 1740 /*
1a2eb460 1741 * There are four kinds of DP registers:
417e822d
KP		 1742 *
1743 * IBX PCH
1a2eb460
KP		 1744 * SNB CPU
1745 * IVB CPU
417e822d
KP		 1746 * CPT PCH
1747 *
1748 * IBX PCH and CPU are the same for almost everything,
1749 * except that the CPU DP PLL is configured in this
1750 * register
1751 *
1752 * CPT PCH is quite different, having many bits moved
1753 * to the TRANS_DP_CTL register instead. That
1754 * configuration happens (oddly) in ironlake_pch_enable
1755 */
9c9e7927 1756
417e822d
KP		 1757 /* Preserve the BIOS-computed detected bit. This is
1758 * supposed to be read-only.
1759 */
1760 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1761
417e822d 1762 /* Handle DP bits in common between all three register formats */
417e822d 1763 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
85cb48a1 1764 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
a4fc5ed6 1765
417e822d 1766 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1767
39e5fa88 1768 if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1769 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1770 intel_dp->DP |= DP_SYNC_HS_HIGH;
1771 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1772 intel_dp->DP |= DP_SYNC_VS_HIGH;
1773 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1774
6aba5b6c 1775 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1776 intel_dp->DP |= DP_ENHANCED_FRAMING;
1777
7c62a164 1778 intel_dp->DP |= crtc->pipe << 29;
39e5fa88 1779 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
e3ef4479
VS		 1780 u32 trans_dp;
1781
39e5fa88 1782 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1783
1784 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1785 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1786 trans_dp |= TRANS_DP_ENH_FRAMING;
1787 else
1788 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1789 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1790 } else {
0f2a2a75 1791 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
85cb48a1 1792 !IS_CHERRYVIEW(dev) && pipe_config->limited_color_range)
0f2a2a75 1793 intel_dp->DP |= DP_COLOR_RANGE_16_235;
417e822d
KP		 1794
1795 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1796 intel_dp->DP |= DP_SYNC_HS_HIGH;
1797 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1798 intel_dp->DP |= DP_SYNC_VS_HIGH;
1799 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1800
6aba5b6c 1801 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1802 intel_dp->DP |= DP_ENHANCED_FRAMING;
1803
39e5fa88 1804 if (IS_CHERRYVIEW(dev))
44f37d1f 1805 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1806 else if (crtc->pipe == PIPE_B)
1807 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1808 }
a4fc5ed6
KP		 1809}
1810
ffd6749d
PZ		 1811#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1812#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1813
1a5ef5b7
PZ		 1814#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1815#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1816
ffd6749d
PZ		 1817#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1818#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1819
de9c1b6b
ID		 1820static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1821 struct intel_dp *intel_dp);
1822
4be73780 1823static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1824 u32 mask,
1825 u32 value)
bd943159 1826{
30add22d 1827 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 1828 struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00 1829 i915_reg_t pp_stat_reg, pp_ctrl_reg;
453c5420 1830
e39b999a
VS		 1831 lockdep_assert_held(&dev_priv->pps_mutex);
1832
de9c1b6b
ID		 1833 intel_pps_verify_state(dev_priv, intel_dp);
1834
bf13e81b
JN		 1835 pp_stat_reg = _pp_stat_reg(intel_dp);
1836 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1837
99ea7127 1838 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1839 mask, value,
1840 I915_READ(pp_stat_reg),
1841 I915_READ(pp_ctrl_reg));
32ce697c 1842
9036ff06
CW		 1843 if (intel_wait_for_register(dev_priv,
1844 pp_stat_reg, mask, value,
1845 5000))
99ea7127 1846 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1847 I915_READ(pp_stat_reg),
1848 I915_READ(pp_ctrl_reg));
54c136d4
CW		 1849
1850 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1851}
32ce697c 1852
4be73780 1853static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1854{
1855 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1856 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1857}
1858
4be73780 1859static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1860{
1861 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1862 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1863}
1864
4be73780 1865static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127 1866{
d28d4731
AK		 1867 ktime_t panel_power_on_time;
1868 s64 panel_power_off_duration;
1869
99ea7127 1870 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c 1871
d28d4731
AK		 1872 /* take the difference of currrent time and panel power off time
1873 * and then make panel wait for t11_t12 if needed. */
1874 panel_power_on_time = ktime_get_boottime();
1875 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1876
dce56b3c
PZ		 1877 /* When we disable the VDD override bit last we have to do the manual
1878 * wait. */
d28d4731
AK		 1879 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1880 wait_remaining_ms_from_jiffies(jiffies,
1881 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
dce56b3c 1882
4be73780 1883 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1884}
1885
4be73780 1886static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1887{
1888 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1889 intel_dp->backlight_on_delay);
1890}
1891
4be73780 1892static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1893{
1894 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1895 intel_dp->backlight_off_delay);
1896}
99ea7127 1897
832dd3c1
KP		 1898/* Read the current pp_control value, unlocking the register if it
1899 * is locked
1900 */
1901
453c5420 1902static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1903{
453c5420 1904 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 1905 struct drm_i915_private *dev_priv = to_i915(dev);
453c5420 1906 u32 control;
832dd3c1 1907
e39b999a
VS		 1908 lockdep_assert_held(&dev_priv->pps_mutex);
1909
bf13e81b 1910 control = I915_READ(_pp_ctrl_reg(intel_dp));
8090ba8c
ID		 1911 if (WARN_ON(!HAS_DDI(dev_priv) &&
1912 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
b0a08bec
VK		 1913 control &= ~PANEL_UNLOCK_MASK;
1914 control |= PANEL_UNLOCK_REGS;
1915 }
832dd3c1 1916 return control;
bd943159
KP		 1917}
1918
951468f3
VS		 1919/*
1920 * Must be paired with edp_panel_vdd_off().
1921 * Must hold pps_mutex around the whole on/off sequence.
1922 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1923 */
1e0560e0 1924static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1925{
30add22d 1926 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1927 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1928 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fac5e23e 1929 struct drm_i915_private *dev_priv = to_i915(dev);
4e6e1a54 1930 enum intel_display_power_domain power_domain;
5d613501 1931 u32 pp;
f0f59a00 1932 i915_reg_t pp_stat_reg, pp_ctrl_reg;
adddaaf4 1933 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1934
e39b999a
VS		 1935 lockdep_assert_held(&dev_priv->pps_mutex);
1936
97af61f5 1937 if (!is_edp(intel_dp))
adddaaf4 1938 return false;
bd943159 1939
2c623c11 1940 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1941 intel_dp->want_panel_vdd = true;
99ea7127 1942
4be73780 1943 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1944 return need_to_disable;
b0665d57 1945
25f78f58 1946 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 1947 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1948
3936fcf4
VS		 1949 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1950 port_name(intel_dig_port->port));
bd943159 1951
4be73780
DV		 1952 if (!edp_have_panel_power(intel_dp))
1953 wait_panel_power_cycle(intel_dp);
99ea7127 1954
453c5420 1955 pp = ironlake_get_pp_control(intel_dp);
5d613501 1956 pp |= EDP_FORCE_VDD;
ebf33b18 1957
bf13e81b
JN		 1958 pp_stat_reg = _pp_stat_reg(intel_dp);
1959 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1960
1961 I915_WRITE(pp_ctrl_reg, pp);
1962 POSTING_READ(pp_ctrl_reg);
1963 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1964 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1965 /*
1966 * If the panel wasn't on, delay before accessing aux channel
1967 */
4be73780 1968 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1969 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1970 port_name(intel_dig_port->port));
f01eca2e 1971 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1972 }
adddaaf4
JN		 1973
1974 return need_to_disable;
1975}
1976
951468f3
VS		 1977/*
1978 * Must be paired with intel_edp_panel_vdd_off() or
1979 * intel_edp_panel_off().
1980 * Nested calls to these functions are not allowed since
1981 * we drop the lock. Caller must use some higher level
1982 * locking to prevent nested calls from other threads.
1983 */
b80d6c78 1984void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1985{
c695b6b6 1986 bool vdd;
adddaaf4 1987
c695b6b6
VS		 1988 if (!is_edp(intel_dp))
1989 return;
1990
773538e8 1991 pps_lock(intel_dp);
c695b6b6 1992 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1993 pps_unlock(intel_dp);
c695b6b6 1994
e2c719b7 1995 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1996 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1997}
1998
4be73780 1999static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 2000{
30add22d 2001 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2002 struct drm_i915_private *dev_priv = to_i915(dev);
be2c9196
VS		 2003 struct intel_digital_port *intel_dig_port =
2004 dp_to_dig_port(intel_dp);
2005 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2006 enum intel_display_power_domain power_domain;
5d613501 2007 u32 pp;
f0f59a00 2008 i915_reg_t pp_stat_reg, pp_ctrl_reg;
5d613501 2009
e39b999a 2010 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 2011
15e899a0 2012 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 2013
15e899a0 2014 if (!edp_have_panel_vdd(intel_dp))
be2c9196 2015 return;
b0665d57 2016
3936fcf4
VS		 2017 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2018 port_name(intel_dig_port->port));
bd943159 2019
be2c9196
VS		 2020 pp = ironlake_get_pp_control(intel_dp);
2021 pp &= ~EDP_FORCE_VDD;
453c5420 2022
be2c9196
VS		 2023 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2024 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 2025
be2c9196
VS		 2026 I915_WRITE(pp_ctrl_reg, pp);
2027 POSTING_READ(pp_ctrl_reg);
90791a5c 2028
be2c9196
VS		 2029 /* Make sure sequencer is idle before allowing subsequent activity */
2030 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2031 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 2032
5a162e22 2033 if ((pp & PANEL_POWER_ON) == 0)
d28d4731 2034 intel_dp->panel_power_off_time = ktime_get_boottime();
e9cb81a2 2035
25f78f58 2036 power_domain = intel_display_port_aux_power_domain(intel_encoder);
be2c9196 2037 intel_display_power_put(dev_priv, power_domain);
bd943159 2038}
5d613501 2039
4be73780 2040static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 2041{
2042 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2043 struct intel_dp, panel_vdd_work);
bd943159 2044
773538e8 2045 pps_lock(intel_dp);
15e899a0
VS		 2046 if (!intel_dp->want_panel_vdd)
2047 edp_panel_vdd_off_sync(intel_dp);
773538e8 2048 pps_unlock(intel_dp);
bd943159
KP		 2049}
2050
aba86890
ID		 2051static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2052{
2053 unsigned long delay;
2054
2055 /*
2056 * Queue the timer to fire a long time from now (relative to the power
2057 * down delay) to keep the panel power up across a sequence of
2058 * operations.
2059 */
2060 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2061 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2062}
2063
951468f3
VS		 2064/*
2065 * Must be paired with edp_panel_vdd_on().
2066 * Must hold pps_mutex around the whole on/off sequence.
2067 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2068 */
4be73780 2069static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 2070{
fac5e23e 2071 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
e39b999a
VS		 2072
2073 lockdep_assert_held(&dev_priv->pps_mutex);
2074
97af61f5
KP		 2075 if (!is_edp(intel_dp))
2076 return;
5d613501 2077
e2c719b7 2078 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 2079 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 2080
bd943159
KP		 2081 intel_dp->want_panel_vdd = false;
2082
aba86890 2083 if (sync)
4be73780 2084 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 2085 else
2086 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 2087}
2088
9f0fb5be 2089static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 2090{
30add22d 2091 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2092 struct drm_i915_private *dev_priv = to_i915(dev);
99ea7127 2093 u32 pp;
f0f59a00 2094 i915_reg_t pp_ctrl_reg;
9934c132 2095
9f0fb5be
VS		 2096 lockdep_assert_held(&dev_priv->pps_mutex);
2097
97af61f5 2098 if (!is_edp(intel_dp))
bd943159 2099 return;
99ea7127 2100
3936fcf4
VS		 2101 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2102 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 2103
e7a89ace
VS		 2104 if (WARN(edp_have_panel_power(intel_dp),
2105 "eDP port %c panel power already on\n",
2106 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 2107 return;
9934c132 2108
4be73780 2109 wait_panel_power_cycle(intel_dp);
37c6c9b0 2110
bf13e81b 2111 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2112 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 2113 if (IS_GEN5(dev)) {
2114 /* ILK workaround: disable reset around power sequence */
2115 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 2116 I915_WRITE(pp_ctrl_reg, pp);
2117 POSTING_READ(pp_ctrl_reg);
05ce1a49 2118 }
37c6c9b0 2119
5a162e22 2120 pp |= PANEL_POWER_ON;
99ea7127
KP		 2121 if (!IS_GEN5(dev))
2122 pp |= PANEL_POWER_RESET;
2123
453c5420
JB		 2124 I915_WRITE(pp_ctrl_reg, pp);
2125 POSTING_READ(pp_ctrl_reg);
9934c132 2126
4be73780 2127 wait_panel_on(intel_dp);
dce56b3c 2128 intel_dp->last_power_on = jiffies;
9934c132 2129
05ce1a49
KP		 2130 if (IS_GEN5(dev)) {
2131 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 2132 I915_WRITE(pp_ctrl_reg, pp);
2133 POSTING_READ(pp_ctrl_reg);
05ce1a49 2134 }
9f0fb5be 2135}
e39b999a 2136
9f0fb5be
VS		 2137void intel_edp_panel_on(struct intel_dp *intel_dp)
2138{
2139 if (!is_edp(intel_dp))
2140 return;
2141
2142 pps_lock(intel_dp);
2143 edp_panel_on(intel_dp);
773538e8 2144 pps_unlock(intel_dp);
9934c132
JB		 2145}
2146
9f0fb5be
VS		 2147
2148static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 2149{
4e6e1a54
ID		 2150 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2151 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 2152 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2153 struct drm_i915_private *dev_priv = to_i915(dev);
4e6e1a54 2154 enum intel_display_power_domain power_domain;
99ea7127 2155 u32 pp;
f0f59a00 2156 i915_reg_t pp_ctrl_reg;
9934c132 2157
9f0fb5be
VS		 2158 lockdep_assert_held(&dev_priv->pps_mutex);
2159
97af61f5
KP		 2160 if (!is_edp(intel_dp))
2161 return;
37c6c9b0 2162
3936fcf4
VS		 2163 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2164 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 2165
3936fcf4
VS		 2166 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2167 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 2168
453c5420 2169 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 2170 /* We need to switch off panel power _and_ force vdd, for otherwise some
2171 * panels get very unhappy and cease to work. */
5a162e22 2172 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
b3064154 2173 EDP_BLC_ENABLE);
453c5420 2174
bf13e81b 2175 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2176
849e39f5
PZ		 2177 intel_dp->want_panel_vdd = false;
2178
453c5420
JB		 2179 I915_WRITE(pp_ctrl_reg, pp);
2180 POSTING_READ(pp_ctrl_reg);
9934c132 2181
d28d4731 2182 intel_dp->panel_power_off_time = ktime_get_boottime();
4be73780 2183 wait_panel_off(intel_dp);
849e39f5
PZ		 2184
2185 /* We got a reference when we enabled the VDD. */
25f78f58 2186 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 2187 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 2188}
e39b999a 2189
9f0fb5be
VS		 2190void intel_edp_panel_off(struct intel_dp *intel_dp)
2191{
2192 if (!is_edp(intel_dp))
2193 return;
e39b999a 2194
9f0fb5be
VS		 2195 pps_lock(intel_dp);
2196 edp_panel_off(intel_dp);
773538e8 2197 pps_unlock(intel_dp);
9934c132
JB		 2198}
2199
1250d107
JN		 2200/* Enable backlight in the panel power control. */
2201static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2202{
da63a9f2
PZ		 2203 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2204 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 2205 struct drm_i915_private *dev_priv = to_i915(dev);
32f9d658 2206 u32 pp;
f0f59a00 2207 i915_reg_t pp_ctrl_reg;
32f9d658 2208
01cb9ea6
JB		 2209 /*
2210 * If we enable the backlight right away following a panel power
2211 * on, we may see slight flicker as the panel syncs with the eDP
2212 * link. So delay a bit to make sure the image is solid before
2213 * allowing it to appear.
2214 */
4be73780 2215 wait_backlight_on(intel_dp);
e39b999a 2216
773538e8 2217 pps_lock(intel_dp);
e39b999a 2218
453c5420 2219 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2220 pp |= EDP_BLC_ENABLE;
453c5420 2221
bf13e81b 2222 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2223
2224 I915_WRITE(pp_ctrl_reg, pp);
2225 POSTING_READ(pp_ctrl_reg);
e39b999a 2226
773538e8 2227 pps_unlock(intel_dp);
32f9d658
ZW		 2228}
2229
1250d107
JN		 2230/* Enable backlight PWM and backlight PP control. */
2231void intel_edp_backlight_on(struct intel_dp *intel_dp)
2232{
2233 if (!is_edp(intel_dp))
2234 return;
2235
2236 DRM_DEBUG_KMS("\n");
2237
2238 intel_panel_enable_backlight(intel_dp->attached_connector);
2239 _intel_edp_backlight_on(intel_dp);
2240}
2241
2242/* Disable backlight in the panel power control. */
2243static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2244{
30add22d 2245 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2246 struct drm_i915_private *dev_priv = to_i915(dev);
32f9d658 2247 u32 pp;
f0f59a00 2248 i915_reg_t pp_ctrl_reg;
32f9d658 2249
f01eca2e
KP		 2250 if (!is_edp(intel_dp))
2251 return;
2252
773538e8 2253 pps_lock(intel_dp);
e39b999a 2254
453c5420 2255 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2256 pp &= ~EDP_BLC_ENABLE;
453c5420 2257
bf13e81b 2258 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2259
2260 I915_WRITE(pp_ctrl_reg, pp);
2261 POSTING_READ(pp_ctrl_reg);
f7d2323c 2262
773538e8 2263 pps_unlock(intel_dp);
e39b999a
VS		 2264
2265 intel_dp->last_backlight_off = jiffies;
f7d2323c 2266 edp_wait_backlight_off(intel_dp);
1250d107 2267}
f7d2323c 2268
1250d107
JN		 2269/* Disable backlight PP control and backlight PWM. */
2270void intel_edp_backlight_off(struct intel_dp *intel_dp)
2271{
2272 if (!is_edp(intel_dp))
2273 return;
2274
2275 DRM_DEBUG_KMS("\n");
f7d2323c 2276
1250d107 2277 _intel_edp_backlight_off(intel_dp);
f7d2323c 2278 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2279}
a4fc5ed6 2280
73580fb7
JN		 2281/*
2282 * Hook for controlling the panel power control backlight through the bl_power
2283 * sysfs attribute. Take care to handle multiple calls.
2284 */
2285static void intel_edp_backlight_power(struct intel_connector *connector,
2286 bool enable)
2287{
2288 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2289 bool is_enabled;
2290
773538e8 2291 pps_lock(intel_dp);
e39b999a 2292 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2293 pps_unlock(intel_dp);
73580fb7
JN		 2294
2295 if (is_enabled == enable)
2296 return;
2297
23ba9373
JN		 2298 DRM_DEBUG_KMS("panel power control backlight %s\n",
2299 enable ? "enable" : "disable");
73580fb7
JN		 2300
2301 if (enable)
2302 _intel_edp_backlight_on(intel_dp);
2303 else
2304 _intel_edp_backlight_off(intel_dp);
2305}
2306
64e1077a
VS		 2307static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2308{
2309 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2310 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2311 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2312
2313 I915_STATE_WARN(cur_state != state,
2314 "DP port %c state assertion failure (expected %s, current %s)\n",
2315 port_name(dig_port->port),
87ad3212 2316 onoff(state), onoff(cur_state));
64e1077a
VS		 2317}
2318#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2319
2320static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2321{
2322 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2323
2324 I915_STATE_WARN(cur_state != state,
2325 "eDP PLL state assertion failure (expected %s, current %s)\n",
87ad3212 2326 onoff(state), onoff(cur_state));
64e1077a
VS		 2327}
2328#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2329#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2330
85cb48a1
ML		 2331static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2332 struct intel_crtc_state *pipe_config)
d240f20f 2333{
85cb48a1 2334 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
64e1077a 2335 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2336
64e1077a
VS		 2337 assert_pipe_disabled(dev_priv, crtc->pipe);
2338 assert_dp_port_disabled(intel_dp);
2339 assert_edp_pll_disabled(dev_priv);
2bd2ad64 2340
abfce949 2341 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
85cb48a1 2342 pipe_config->port_clock);
abfce949
VS		 2343
2344 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2345
85cb48a1 2346 if (pipe_config->port_clock == 162000)
abfce949
VS		 2347 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2348 else
2349 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2350
2351 I915_WRITE(DP_A, intel_dp->DP);
2352 POSTING_READ(DP_A);
2353 udelay(500);
2354
6b23f3e8
VS		 2355 /*
2356 * [DevILK] Work around required when enabling DP PLL
2357 * while a pipe is enabled going to FDI:
2358 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2359 * 2. Program DP PLL enable
2360 */
2361 if (IS_GEN5(dev_priv))
91c8a326 2362 intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe);
6b23f3e8 2363
0767935e 2364 intel_dp->DP |= DP_PLL_ENABLE;
6fec7662 2365
0767935e 2366 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2367 POSTING_READ(DP_A);
2368 udelay(200);
d240f20f
JB		 2369}
2370
2bd2ad64 2371static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2372{
da63a9f2 2373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2374 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2375 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2376
64e1077a
VS		 2377 assert_pipe_disabled(dev_priv, crtc->pipe);
2378 assert_dp_port_disabled(intel_dp);
2379 assert_edp_pll_enabled(dev_priv);
2bd2ad64 2380
abfce949
VS		 2381 DRM_DEBUG_KMS("disabling eDP PLL\n");
2382
6fec7662 2383 intel_dp->DP &= ~DP_PLL_ENABLE;
0767935e 2384
6fec7662 2385 I915_WRITE(DP_A, intel_dp->DP);
1af5fa1b 2386 POSTING_READ(DP_A);
d240f20f
JB		 2387 udelay(200);
2388}
2389
c7ad3810 2390/* If the sink supports it, try to set the power state appropriately */
c19b0669 2391void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2392{
2393 int ret, i;
2394
2395 /* Should have a valid DPCD by this point */
2396 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2397 return;
2398
2399 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2400 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2401 DP_SET_POWER_D3);
c7ad3810
JB		 2402 } else {
2403 /*
2404 * When turning on, we need to retry for 1ms to give the sink
2405 * time to wake up.
2406 */
2407 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2408 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2409 DP_SET_POWER_D0);
c7ad3810
JB		 2410 if (ret == 1)
2411 break;
2412 msleep(1);
2413 }
2414 }
f9cac721
JN		 2415
2416 if (ret != 1)
2417 DRM_DEBUG_KMS("failed to %s sink power state\n",
2418 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2419}
2420
19d8fe15
DV		 2421static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2422 enum pipe *pipe)
d240f20f 2423{
19d8fe15 2424 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2425 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15 2426 struct drm_device *dev = encoder->base.dev;
fac5e23e 2427 struct drm_i915_private *dev_priv = to_i915(dev);
6d129bea
ID		 2428 enum intel_display_power_domain power_domain;
2429 u32 tmp;
6fa9a5ec 2430 bool ret;
6d129bea
ID		 2431
2432 power_domain = intel_display_port_power_domain(encoder);
6fa9a5ec 2433 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 2434 return false;
2435
6fa9a5ec
ID		 2436 ret = false;
2437
6d129bea 2438 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2439
2440 if (!(tmp & DP_PORT_EN))
6fa9a5ec 2441 goto out;
19d8fe15 2442
39e5fa88 2443 if (IS_GEN7(dev) && port == PORT_A) {
19d8fe15 2444 *pipe = PORT_TO_PIPE_CPT(tmp);
39e5fa88 2445 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
adc289d7 2446 enum pipe p;
19d8fe15 2447
adc289d7
VS		 2448 for_each_pipe(dev_priv, p) {
2449 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2450 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2451 *pipe = p;
6fa9a5ec
ID		 2452 ret = true;
2453
2454 goto out;
19d8fe15
DV		 2455 }
2456 }
19d8fe15 2457
4a0833ec 2458 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
f0f59a00 2459 i915_mmio_reg_offset(intel_dp->output_reg));
39e5fa88
VS		 2460 } else if (IS_CHERRYVIEW(dev)) {
2461 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2462 } else {
2463 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2464 }
d240f20f 2465
6fa9a5ec
ID		 2466 ret = true;
2467
2468out:
2469 intel_display_power_put(dev_priv, power_domain);
2470
2471 return ret;
19d8fe15 2472}
d240f20f 2473
045ac3b5 2474static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2475 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2476{
2477 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2478 u32 tmp, flags = 0;
63000ef6 2479 struct drm_device *dev = encoder->base.dev;
fac5e23e 2480 struct drm_i915_private *dev_priv = to_i915(dev);
63000ef6
XZ		 2481 enum port port = dp_to_dig_port(intel_dp)->port;
2482 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 2483
9ed109a7 2484 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2485
2486 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2487
39e5fa88 2488 if (HAS_PCH_CPT(dev) && port != PORT_A) {
b81e34c2
VS		 2489 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2490
2491 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2492 flags |= DRM_MODE_FLAG_PHSYNC;
2493 else
2494 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2495
b81e34c2 2496 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2497 flags |= DRM_MODE_FLAG_PVSYNC;
2498 else
2499 flags |= DRM_MODE_FLAG_NVSYNC;
2500 } else {
39e5fa88 2501 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2502 flags |= DRM_MODE_FLAG_PHSYNC;
2503 else
2504 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2505
39e5fa88 2506 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2507 flags |= DRM_MODE_FLAG_PVSYNC;
2508 else
2509 flags |= DRM_MODE_FLAG_NVSYNC;
2510 }
045ac3b5 2511
2d112de7 2512 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2513
8c875fca 2514 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 2515 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
8c875fca
VS		 2516 pipe_config->limited_color_range = true;
2517
90a6b7b0
VS		 2518 pipe_config->lane_count =
2519 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2520
eb14cb74
VS		 2521 intel_dp_get_m_n(crtc, pipe_config);
2522
18442d08 2523 if (port == PORT_A) {
b377e0df 2524 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
f1f644dc
JB		 2525 pipe_config->port_clock = 162000;
2526 else
2527 pipe_config->port_clock = 270000;
2528 }
18442d08 2529
e3b247da
VS		 2530 pipe_config->base.adjusted_mode.crtc_clock =
2531 intel_dotclock_calculate(pipe_config->port_clock,
2532 &pipe_config->dp_m_n);
7f16e5c1 2533
6aa23e65
JN		 2534 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2535 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
c6cd2ee2
JN		 2536 /*
2537 * This is a big fat ugly hack.
2538 *
2539 * Some machines in UEFI boot mode provide us a VBT that has 18
2540 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2541 * unknown we fail to light up. Yet the same BIOS boots up with
2542 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2543 * max, not what it tells us to use.
2544 *
2545 * Note: This will still be broken if the eDP panel is not lit
2546 * up by the BIOS, and thus we can't get the mode at module
2547 * load.
2548 */
2549 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2550 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2551 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
c6cd2ee2 2552 }
045ac3b5
JB		 2553}
2554
fd6bbda9
ML		 2555static void intel_disable_dp(struct intel_encoder *encoder,
2556 struct intel_crtc_state *old_crtc_state,
2557 struct drm_connector_state *old_conn_state)
d240f20f 2558{
e8cb4558 2559 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
85cb48a1 2560 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
495a5bb8 2561
85cb48a1 2562 if (old_crtc_state->has_audio)
495a5bb8 2563 intel_audio_codec_disable(encoder);
6cb49835 2564
85cb48a1 2565 if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
b32c6f48
RV		 2566 intel_psr_disable(intel_dp);
2567
6cb49835
DV		 2568 /* Make sure the panel is off before trying to change the mode. But also
2569 * ensure that we have vdd while we switch off the panel. */
24f3e092 2570 intel_edp_panel_vdd_on(intel_dp);
4be73780 2571 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2572 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2573 intel_edp_panel_off(intel_dp);
3739850b 2574
08aff3fe 2575 /* disable the port before the pipe on g4x */
85cb48a1 2576 if (INTEL_GEN(dev_priv) < 5)
3739850b 2577 intel_dp_link_down(intel_dp);
d240f20f
JB		 2578}
2579
fd6bbda9
ML		 2580static void ilk_post_disable_dp(struct intel_encoder *encoder,
2581 struct intel_crtc_state *old_crtc_state,
2582 struct drm_connector_state *old_conn_state)
d240f20f 2583{
2bd2ad64 2584 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2585 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2586
49277c31 2587 intel_dp_link_down(intel_dp);
abfce949
VS		 2588
2589 /* Only ilk+ has port A */
08aff3fe
VS		 2590 if (port == PORT_A)
2591 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2592}
2593
fd6bbda9
ML		 2594static void vlv_post_disable_dp(struct intel_encoder *encoder,
2595 struct intel_crtc_state *old_crtc_state,
2596 struct drm_connector_state *old_conn_state)
49277c31
VS		 2597{
2598 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2599
2600 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2601}
2602
fd6bbda9
ML		 2603static void chv_post_disable_dp(struct intel_encoder *encoder,
2604 struct intel_crtc_state *old_crtc_state,
2605 struct drm_connector_state *old_conn_state)
a8f327fb
VS		 2606{
2607 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2608 struct drm_device *dev = encoder->base.dev;
fac5e23e 2609 struct drm_i915_private *dev_priv = to_i915(dev);
97fd4d5c 2610
a8f327fb
VS		 2611 intel_dp_link_down(intel_dp);
2612
2613 mutex_lock(&dev_priv->sb_lock);
2614
2615 /* Assert data lane reset */
2616 chv_data_lane_soft_reset(encoder, true);
580d3811 2617
a580516d 2618 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2619}
2620
7b13b58a
VS		 2621static void
2622_intel_dp_set_link_train(struct intel_dp *intel_dp,
2623 uint32_t *DP,
2624 uint8_t dp_train_pat)
2625{
2626 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2627 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 2628 struct drm_i915_private *dev_priv = to_i915(dev);
7b13b58a
VS		 2629 enum port port = intel_dig_port->port;
2630
8b0878a0
PD		 2631 if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2632 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2633 dp_train_pat & DP_TRAINING_PATTERN_MASK);
2634
7b13b58a
VS		 2635 if (HAS_DDI(dev)) {
2636 uint32_t temp = I915_READ(DP_TP_CTL(port));
2637
2638 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2639 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2640 else
2641 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2642
2643 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2644 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2645 case DP_TRAINING_PATTERN_DISABLE:
2646 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2647
2648 break;
2649 case DP_TRAINING_PATTERN_1:
2650 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2651 break;
2652 case DP_TRAINING_PATTERN_2:
2653 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2654 break;
2655 case DP_TRAINING_PATTERN_3:
2656 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2657 break;
2658 }
2659 I915_WRITE(DP_TP_CTL(port), temp);
2660
39e5fa88
VS		 2661 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2662 (HAS_PCH_CPT(dev) && port != PORT_A)) {
7b13b58a
VS		 2663 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2664
2665 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2666 case DP_TRAINING_PATTERN_DISABLE:
2667 *DP |= DP_LINK_TRAIN_OFF_CPT;
2668 break;
2669 case DP_TRAINING_PATTERN_1:
2670 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2671 break;
2672 case DP_TRAINING_PATTERN_2:
2673 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2674 break;
2675 case DP_TRAINING_PATTERN_3:
8b0878a0 2676 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
7b13b58a
VS		 2677 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2678 break;
2679 }
2680
2681 } else {
2682 if (IS_CHERRYVIEW(dev))
2683 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2684 else
2685 *DP &= ~DP_LINK_TRAIN_MASK;
2686
2687 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2688 case DP_TRAINING_PATTERN_DISABLE:
2689 *DP |= DP_LINK_TRAIN_OFF;
2690 break;
2691 case DP_TRAINING_PATTERN_1:
2692 *DP |= DP_LINK_TRAIN_PAT_1;
2693 break;
2694 case DP_TRAINING_PATTERN_2:
2695 *DP |= DP_LINK_TRAIN_PAT_2;
2696 break;
2697 case DP_TRAINING_PATTERN_3:
2698 if (IS_CHERRYVIEW(dev)) {
2699 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2700 } else {
8b0878a0 2701 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
7b13b58a
VS		 2702 *DP |= DP_LINK_TRAIN_PAT_2;
2703 }
2704 break;
2705 }
2706 }
2707}
2708
85cb48a1
ML		 2709static void intel_dp_enable_port(struct intel_dp *intel_dp,
2710 struct intel_crtc_state *old_crtc_state)
7b13b58a
VS		 2711{
2712 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2713 struct drm_i915_private *dev_priv = to_i915(dev);
7b13b58a 2714
7b13b58a 2715 /* enable with pattern 1 (as per spec) */
7b13b58a 2716
8b0878a0 2717 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
7b713f50
VS		 2718
2719 /*
2720 * Magic for VLV/CHV. We _must_ first set up the register
2721 * without actually enabling the port, and then do another
2722 * write to enable the port. Otherwise link training will
2723 * fail when the power sequencer is freshly used for this port.
2724 */
2725 intel_dp->DP |= DP_PORT_EN;
85cb48a1 2726 if (old_crtc_state->has_audio)
6fec7662 2727 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
7b713f50
VS		 2728
2729 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2730 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2731}
2732
85cb48a1
ML		 2733static void intel_enable_dp(struct intel_encoder *encoder,
2734 struct intel_crtc_state *pipe_config)
d240f20f 2735{
e8cb4558
DV		 2736 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2737 struct drm_device *dev = encoder->base.dev;
fac5e23e 2738 struct drm_i915_private *dev_priv = to_i915(dev);
c1dec79a 2739 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2740 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
d6fbdd15 2741 enum pipe pipe = crtc->pipe;
5d613501 2742
0c33d8d7
DV		 2743 if (WARN_ON(dp_reg & DP_PORT_EN))
2744 return;
5d613501 2745
093e3f13
VS		 2746 pps_lock(intel_dp);
2747
666a4537 2748 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
093e3f13
VS		 2749 vlv_init_panel_power_sequencer(intel_dp);
2750
85cb48a1 2751 intel_dp_enable_port(intel_dp, pipe_config);
093e3f13
VS		 2752
2753 edp_panel_vdd_on(intel_dp);
2754 edp_panel_on(intel_dp);
2755 edp_panel_vdd_off(intel_dp, true);
2756
2757 pps_unlock(intel_dp);
2758
666a4537 2759 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e0fce78f
VS		 2760 unsigned int lane_mask = 0x0;
2761
2762 if (IS_CHERRYVIEW(dev))
85cb48a1 2763 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
e0fce78f 2764
9b6de0a1
VS		 2765 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2766 lane_mask);
e0fce78f 2767 }
61234fa5 2768
f01eca2e 2769 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2770 intel_dp_start_link_train(intel_dp);
3ab9c637 2771 intel_dp_stop_link_train(intel_dp);
c1dec79a 2772
85cb48a1 2773 if (pipe_config->has_audio) {
c1dec79a 2774 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
d6fbdd15 2775 pipe_name(pipe));
c1dec79a
JN		 2776 intel_audio_codec_enable(encoder);
2777 }
ab1f90f9 2778}
89b667f8 2779
fd6bbda9
ML		 2780static void g4x_enable_dp(struct intel_encoder *encoder,
2781 struct intel_crtc_state *pipe_config,
2782 struct drm_connector_state *conn_state)
ecff4f3b 2783{
828f5c6e
JN		 2784 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2785
85cb48a1 2786 intel_enable_dp(encoder, pipe_config);
4be73780 2787 intel_edp_backlight_on(intel_dp);
ab1f90f9 2788}
89b667f8 2789
fd6bbda9
ML		 2790static void vlv_enable_dp(struct intel_encoder *encoder,
2791 struct intel_crtc_state *pipe_config,
2792 struct drm_connector_state *conn_state)
ab1f90f9 2793{
828f5c6e
JN		 2794 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2795
4be73780 2796 intel_edp_backlight_on(intel_dp);
b32c6f48 2797 intel_psr_enable(intel_dp);
d240f20f
JB		 2798}
2799
fd6bbda9
ML		 2800static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2801 struct intel_crtc_state *pipe_config,
2802 struct drm_connector_state *conn_state)
ab1f90f9
JN		 2803{
2804 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6fbdd15 2805 enum port port = dp_to_dig_port(intel_dp)->port;
ab1f90f9 2806
85cb48a1 2807 intel_dp_prepare(encoder, pipe_config);
8ac33ed3 2808
d41f1efb 2809 /* Only ilk+ has port A */
abfce949 2810 if (port == PORT_A)
85cb48a1 2811 ironlake_edp_pll_on(intel_dp, pipe_config);
ab1f90f9
JN		 2812}
2813
83b84597
VS		 2814static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2815{
2816 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
fac5e23e 2817 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
83b84597 2818 enum pipe pipe = intel_dp->pps_pipe;
44cb734c 2819 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
83b84597
VS		 2820
2821 edp_panel_vdd_off_sync(intel_dp);
2822
2823 /*
2824 * VLV seems to get confused when multiple power seqeuencers
2825 * have the same port selected (even if only one has power/vdd
2826 * enabled). The failure manifests as vlv_wait_port_ready() failing
2827 * CHV on the other hand doesn't seem to mind having the same port
2828 * selected in multiple power seqeuencers, but let's clear the
2829 * port select always when logically disconnecting a power sequencer
2830 * from a port.
2831 */
2832 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2833 pipe_name(pipe), port_name(intel_dig_port->port));
2834 I915_WRITE(pp_on_reg, 0);
2835 POSTING_READ(pp_on_reg);
2836
2837 intel_dp->pps_pipe = INVALID_PIPE;
2838}
2839
a4a5d2f8
VS		 2840static void vlv_steal_power_sequencer(struct drm_device *dev,
2841 enum pipe pipe)
2842{
fac5e23e 2843 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8
VS		 2844 struct intel_encoder *encoder;
2845
2846 lockdep_assert_held(&dev_priv->pps_mutex);
2847
ac3c12e4
VS		 2848 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2849 return;
2850
19c8054c 2851 for_each_intel_encoder(dev, encoder) {
a4a5d2f8 2852 struct intel_dp *intel_dp;
773538e8 2853 enum port port;
a4a5d2f8
VS		 2854
2855 if (encoder->type != INTEL_OUTPUT_EDP)
2856 continue;
2857
2858 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2859 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2860
2861 if (intel_dp->pps_pipe != pipe)
2862 continue;
2863
2864 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2865 pipe_name(pipe), port_name(port));
a4a5d2f8 2866
e02f9a06 2867 WARN(encoder->base.crtc,
034e43c6
VS		 2868 "stealing pipe %c power sequencer from active eDP port %c\n",
2869 pipe_name(pipe), port_name(port));
a4a5d2f8 2870
a4a5d2f8 2871 /* make sure vdd is off before we steal it */
83b84597 2872 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2873 }
2874}
2875
2876static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2877{
2878 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2879 struct intel_encoder *encoder = &intel_dig_port->base;
2880 struct drm_device *dev = encoder->base.dev;
fac5e23e 2881 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8 2882 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2883
2884 lockdep_assert_held(&dev_priv->pps_mutex);
2885
093e3f13
VS		 2886 if (!is_edp(intel_dp))
2887 return;
2888
a4a5d2f8
VS		 2889 if (intel_dp->pps_pipe == crtc->pipe)
2890 return;
2891
2892 /*
2893 * If another power sequencer was being used on this
2894 * port previously make sure to turn off vdd there while
2895 * we still have control of it.
2896 */
2897 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2898 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2899
2900 /*
2901 * We may be stealing the power
2902 * sequencer from another port.
2903 */
2904 vlv_steal_power_sequencer(dev, crtc->pipe);
2905
2906 /* now it's all ours */
2907 intel_dp->pps_pipe = crtc->pipe;
2908
2909 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2910 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2911
2912 /* init power sequencer on this pipe and port */
36b5f425
VS		 2913 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2914 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2915}
2916
fd6bbda9
ML		 2917static void vlv_pre_enable_dp(struct intel_encoder *encoder,
2918 struct intel_crtc_state *pipe_config,
2919 struct drm_connector_state *conn_state)
a4fc5ed6 2920{
5f68c275 2921 vlv_phy_pre_encoder_enable(encoder);
ab1f90f9 2922
85cb48a1 2923 intel_enable_dp(encoder, pipe_config);
89b667f8
JB		 2924}
2925
fd6bbda9
ML		 2926static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
2927 struct intel_crtc_state *pipe_config,
2928 struct drm_connector_state *conn_state)
89b667f8 2929{
85cb48a1 2930 intel_dp_prepare(encoder, pipe_config);
8ac33ed3 2931
6da2e616 2932 vlv_phy_pre_pll_enable(encoder);
a4fc5ed6
KP		 2933}
2934
fd6bbda9
ML		 2935static void chv_pre_enable_dp(struct intel_encoder *encoder,
2936 struct intel_crtc_state *pipe_config,
2937 struct drm_connector_state *conn_state)
e4a1d846 2938{
e7d2a717 2939 chv_phy_pre_encoder_enable(encoder);
e4a1d846 2940
85cb48a1 2941 intel_enable_dp(encoder, pipe_config);
b0b33846
VS		 2942
2943 /* Second common lane will stay alive on its own now */
e7d2a717 2944 chv_phy_release_cl2_override(encoder);
e4a1d846
CML		 2945}
2946
fd6bbda9
ML		 2947static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
2948 struct intel_crtc_state *pipe_config,
2949 struct drm_connector_state *conn_state)
9197c88b 2950{
85cb48a1 2951 intel_dp_prepare(encoder, pipe_config);
625695f8 2952
419b1b7a 2953 chv_phy_pre_pll_enable(encoder);
9197c88b
VS		 2954}
2955
fd6bbda9
ML		 2956static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
2957 struct intel_crtc_state *pipe_config,
2958 struct drm_connector_state *conn_state)
d6db995f 2959{
204970b5 2960 chv_phy_post_pll_disable(encoder);
d6db995f
VS		 2961}
2962
a4fc5ed6
KP		 2963/*
2964 * Fetch AUX CH registers 0x202 - 0x207 which contain
2965 * link status information
2966 */
94223d04 2967bool
93f62dad 2968intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2969{
9f085ebb
L		 2970 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2971 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2972}
2973
1100244e 2974/* These are source-specific values. */
94223d04 2975uint8_t
1a2eb460 2976intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2977{
30add22d 2978 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2979 struct drm_i915_private *dev_priv = to_i915(dev);
bc7d38a4 2980 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2981
9314726b
VK		 2982 if (IS_BROXTON(dev))
2983 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2984 else if (INTEL_INFO(dev)->gen >= 9) {
06411f08 2985 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
7ad14a29 2986 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2987 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
666a4537 2988 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
bd60018a 2989 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2990 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2991 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2992 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2993 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2994 else
bd60018a 2995 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2996}
2997
94223d04 2998uint8_t
1a2eb460
KP		 2999intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3000{
30add22d 3001 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 3002 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3003
5a9d1f1a
DL		 3004 if (INTEL_INFO(dev)->gen >= 9) {
3005 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3006 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3007 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3009 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3010 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3011 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 3012 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3013 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 3014 default:
3015 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3016 }
3017 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 3018 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3019 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3020 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3022 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3024 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3025 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 3026 default:
bd60018a 3027 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 3028 }
666a4537 3029 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e2fa6fba 3030 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3032 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3034 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3036 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 3038 default:
bd60018a 3039 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3040 }
bc7d38a4 3041 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 3042 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3044 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3047 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3048 default:
bd60018a 3049 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3050 }
3051 } else {
3052 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3053 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3054 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3056 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3058 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3060 default:
bd60018a 3061 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3062 }
a4fc5ed6
KP		 3063 }
3064}
3065
5829975c 3066static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba 3067{
53d98725 3068 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
e2fa6fba
P		 3069 unsigned long demph_reg_value, preemph_reg_value,
3070 uniqtranscale_reg_value;
3071 uint8_t train_set = intel_dp->train_set[0];
e2fa6fba
P		 3072
3073 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3074 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3075 preemph_reg_value = 0x0004000;
3076 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3077 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3078 demph_reg_value = 0x2B405555;
3079 uniqtranscale_reg_value = 0x552AB83A;
3080 break;
bd60018a 3081 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3082 demph_reg_value = 0x2B404040;
3083 uniqtranscale_reg_value = 0x5548B83A;
3084 break;
bd60018a 3085 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3086 demph_reg_value = 0x2B245555;
3087 uniqtranscale_reg_value = 0x5560B83A;
3088 break;
bd60018a 3089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3090 demph_reg_value = 0x2B405555;
3091 uniqtranscale_reg_value = 0x5598DA3A;
3092 break;
3093 default:
3094 return 0;
3095 }
3096 break;
bd60018a 3097 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3098 preemph_reg_value = 0x0002000;
3099 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3100 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3101 demph_reg_value = 0x2B404040;
3102 uniqtranscale_reg_value = 0x5552B83A;
3103 break;
bd60018a 3104 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3105 demph_reg_value = 0x2B404848;
3106 uniqtranscale_reg_value = 0x5580B83A;
3107 break;
bd60018a 3108 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3109 demph_reg_value = 0x2B404040;
3110 uniqtranscale_reg_value = 0x55ADDA3A;
3111 break;
3112 default:
3113 return 0;
3114 }
3115 break;
bd60018a 3116 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3117 preemph_reg_value = 0x0000000;
3118 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3119 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3120 demph_reg_value = 0x2B305555;
3121 uniqtranscale_reg_value = 0x5570B83A;
3122 break;
bd60018a 3123 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3124 demph_reg_value = 0x2B2B4040;
3125 uniqtranscale_reg_value = 0x55ADDA3A;
3126 break;
3127 default:
3128 return 0;
3129 }
3130 break;
bd60018a 3131 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3132 preemph_reg_value = 0x0006000;
3133 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3135 demph_reg_value = 0x1B405555;
3136 uniqtranscale_reg_value = 0x55ADDA3A;
3137 break;
3138 default:
3139 return 0;
3140 }
3141 break;
3142 default:
3143 return 0;
3144 }
3145
53d98725
ACO		 3146 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3147 uniqtranscale_reg_value, 0);
e2fa6fba
P		 3148
3149 return 0;
3150}
3151
5829975c 3152static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846 3153{
b7fa22d8
ACO		 3154 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3155 u32 deemph_reg_value, margin_reg_value;
3156 bool uniq_trans_scale = false;
e4a1d846 3157 uint8_t train_set = intel_dp->train_set[0];
e4a1d846
CML		 3158
3159 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3160 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3161 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3162 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3163 deemph_reg_value = 128;
3164 margin_reg_value = 52;
3165 break;
bd60018a 3166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3167 deemph_reg_value = 128;
3168 margin_reg_value = 77;
3169 break;
bd60018a 3170 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3171 deemph_reg_value = 128;
3172 margin_reg_value = 102;
3173 break;
bd60018a 3174 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3175 deemph_reg_value = 128;
3176 margin_reg_value = 154;
b7fa22d8 3177 uniq_trans_scale = true;
e4a1d846
CML		 3178 break;
3179 default:
3180 return 0;
3181 }
3182 break;
bd60018a 3183 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3184 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3186 deemph_reg_value = 85;
3187 margin_reg_value = 78;
3188 break;
bd60018a 3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3190 deemph_reg_value = 85;
3191 margin_reg_value = 116;
3192 break;
bd60018a 3193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3194 deemph_reg_value = 85;
3195 margin_reg_value = 154;
3196 break;
3197 default:
3198 return 0;
3199 }
3200 break;
bd60018a 3201 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3202 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3204 deemph_reg_value = 64;
3205 margin_reg_value = 104;
3206 break;
bd60018a 3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3208 deemph_reg_value = 64;
3209 margin_reg_value = 154;
3210 break;
3211 default:
3212 return 0;
3213 }
3214 break;
bd60018a 3215 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3216 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3217 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3218 deemph_reg_value = 43;
3219 margin_reg_value = 154;
3220 break;
3221 default:
3222 return 0;
3223 }
3224 break;
3225 default:
3226 return 0;
3227 }
3228
b7fa22d8
ACO		 3229 chv_set_phy_signal_level(encoder, deemph_reg_value,
3230 margin_reg_value, uniq_trans_scale);
e4a1d846
CML		 3231
3232 return 0;
3233}
3234
a4fc5ed6 3235static uint32_t
5829975c 3236gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3237{
3cf2efb1 3238 uint32_t signal_levels = 0;
a4fc5ed6 3239
3cf2efb1 3240 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3241 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3242 default:
3243 signal_levels |= DP_VOLTAGE_0_4;
3244 break;
bd60018a 3245 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3246 signal_levels |= DP_VOLTAGE_0_6;
3247 break;
bd60018a 3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3249 signal_levels |= DP_VOLTAGE_0_8;
3250 break;
bd60018a 3251 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3252 signal_levels |= DP_VOLTAGE_1_2;
3253 break;
3254 }
3cf2efb1 3255 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3256 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3257 default:
3258 signal_levels |= DP_PRE_EMPHASIS_0;
3259 break;
bd60018a 3260 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3261 signal_levels |= DP_PRE_EMPHASIS_3_5;
3262 break;
bd60018a 3263 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3264 signal_levels |= DP_PRE_EMPHASIS_6;
3265 break;
bd60018a 3266 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3267 signal_levels |= DP_PRE_EMPHASIS_9_5;
3268 break;
3269 }
3270 return signal_levels;
3271}
3272
e3421a18
ZW		 3273/* Gen6's DP voltage swing and pre-emphasis control */
3274static uint32_t
5829975c 3275gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3276{
3c5a62b5
YL		 3277 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3278 DP_TRAIN_PRE_EMPHASIS_MASK);
3279 switch (signal_levels) {
bd60018a
SJ		 3280 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3281 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3282 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3283 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3284 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3287 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3288 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3290 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3291 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3292 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3293 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3294 default:
3c5a62b5
YL		 3295 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3296 "0x%x\n", signal_levels);
3297 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3298 }
3299}
3300
1a2eb460
KP		 3301/* Gen7's DP voltage swing and pre-emphasis control */
3302static uint32_t
5829975c 3303gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3304{
3305 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3306 DP_TRAIN_PRE_EMPHASIS_MASK);
3307 switch (signal_levels) {
bd60018a 3308 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3309 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3310 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3311 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3312 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3313 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3314
bd60018a 3315 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3316 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3317 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3318 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3319
bd60018a 3320 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3321 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3322 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3323 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3324
3325 default:
3326 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3327 "0x%x\n", signal_levels);
3328 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3329 }
3330}
3331
94223d04 3332void
f4eb692e 3333intel_dp_set_signal_levels(struct intel_dp *intel_dp)
f0a3424e
PZ		 3334{
3335 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3336 enum port port = intel_dig_port->port;
f0a3424e 3337 struct drm_device *dev = intel_dig_port->base.base.dev;
b905a915 3338 struct drm_i915_private *dev_priv = to_i915(dev);
f8896f5d 3339 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3340 uint8_t train_set = intel_dp->train_set[0];
3341
f8896f5d
DW		 3342 if (HAS_DDI(dev)) {
3343 signal_levels = ddi_signal_levels(intel_dp);
3344
3345 if (IS_BROXTON(dev))
3346 signal_levels = 0;
3347 else
3348 mask = DDI_BUF_EMP_MASK;
e4a1d846 3349 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3350 signal_levels = chv_signal_levels(intel_dp);
e2fa6fba 3351 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3352 signal_levels = vlv_signal_levels(intel_dp);
bc7d38a4 3353 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3354 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3355 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3356 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3357 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3358 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3359 } else {
5829975c 3360 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3361 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3362 }
3363
96fb9f9b
VK		 3364 if (mask)
3365 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3366
3367 DRM_DEBUG_KMS("Using vswing level %d\n",
3368 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3369 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3370 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3371 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e 3372
f4eb692e 3373 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
b905a915
ACO		 3374
3375 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3376 POSTING_READ(intel_dp->output_reg);
f0a3424e
PZ		 3377}
3378
94223d04 3379void
e9c176d5
ACO		 3380intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3381 uint8_t dp_train_pat)
a4fc5ed6 3382{
174edf1f 3383 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3384 struct drm_i915_private *dev_priv =
3385 to_i915(intel_dig_port->base.base.dev);
a4fc5ed6 3386
f4eb692e 3387 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
47ea7542 3388
f4eb692e 3389 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
ea5b213a 3390 POSTING_READ(intel_dp->output_reg);
e9c176d5
ACO		 3391}
3392
94223d04 3393void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3ab9c637
ID		 3394{
3395 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3396 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 3397 struct drm_i915_private *dev_priv = to_i915(dev);
3ab9c637
ID		 3398 enum port port = intel_dig_port->port;
3399 uint32_t val;
3400
3401 if (!HAS_DDI(dev))
3402 return;
3403
3404 val = I915_READ(DP_TP_CTL(port));
3405 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3406 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3407 I915_WRITE(DP_TP_CTL(port), val);
3408
3409 /*
3410 * On PORT_A we can have only eDP in SST mode. There the only reason
3411 * we need to set idle transmission mode is to work around a HW issue
3412 * where we enable the pipe while not in idle link-training mode.
3413 * In this case there is requirement to wait for a minimum number of
3414 * idle patterns to be sent.
3415 */
3416 if (port == PORT_A)
3417 return;
3418
a767017f
CW		 3419 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3420 DP_TP_STATUS_IDLE_DONE,
3421 DP_TP_STATUS_IDLE_DONE,
3422 1))
3ab9c637
ID		 3423 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3424}
3425
a4fc5ed6 3426static void
ea5b213a 3427intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3428{
da63a9f2 3429 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3430 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3431 enum port port = intel_dig_port->port;
da63a9f2 3432 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 3433 struct drm_i915_private *dev_priv = to_i915(dev);
ea5b213a 3434 uint32_t DP = intel_dp->DP;
a4fc5ed6 3435
bc76e320 3436 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3437 return;
3438
0c33d8d7 3439 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3440 return;
3441
28c97730 3442 DRM_DEBUG_KMS("\n");
32f9d658 3443
39e5fa88
VS		 3444 if ((IS_GEN7(dev) && port == PORT_A) ||
3445 (HAS_PCH_CPT(dev) && port != PORT_A)) {
e3421a18 3446 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3447 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3448 } else {
aad3d14d
VS		 3449 if (IS_CHERRYVIEW(dev))
3450 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3451 else
3452 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3453 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3454 }
1612c8bd 3455 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3456 POSTING_READ(intel_dp->output_reg);
5eb08b69 3457
1612c8bd
VS		 3458 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3459 I915_WRITE(intel_dp->output_reg, DP);
3460 POSTING_READ(intel_dp->output_reg);
3461
3462 /*
3463 * HW workaround for IBX, we need to move the port
3464 * to transcoder A after disabling it to allow the
3465 * matching HDMI port to be enabled on transcoder A.
3466 */
3467 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
0c241d5b
VS		 3468 /*
3469 * We get CPU/PCH FIFO underruns on the other pipe when
3470 * doing the workaround. Sweep them under the rug.
3471 */
3472 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3473 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3474
1612c8bd
VS		 3475 /* always enable with pattern 1 (as per spec) */
3476 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3477 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3478 I915_WRITE(intel_dp->output_reg, DP);
3479 POSTING_READ(intel_dp->output_reg);
3480
3481 DP &= ~DP_PORT_EN;
5bddd17f 3482 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3483 POSTING_READ(intel_dp->output_reg);
0c241d5b 3484
91c8a326 3485 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
0c241d5b
VS		 3486 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3487 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5bddd17f
EA		 3488 }
3489
f01eca2e 3490 msleep(intel_dp->panel_power_down_delay);
6fec7662
VS		 3491
3492 intel_dp->DP = DP;
a4fc5ed6
KP		 3493}
3494
26d61aad 3495static bool
fe5a66f9 3496intel_dp_read_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3497{
9f085ebb
L		 3498 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3499 sizeof(intel_dp->dpcd)) < 0)
edb39244 3500 return false; /* aux transfer failed */
92fd8fd1 3501
a8e98153 3502 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3503
fe5a66f9
VS		 3504 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3505}
edb39244 3506
fe5a66f9
VS		 3507static bool
3508intel_edp_init_dpcd(struct intel_dp *intel_dp)
3509{
3510 struct drm_i915_private *dev_priv =
3511 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
30d9aa42 3512
fe5a66f9
VS		 3513 /* this function is meant to be called only once */
3514 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
30d9aa42 3515
fe5a66f9 3516 if (!intel_dp_read_dpcd(intel_dp))
30d9aa42
SS		 3517 return false;
3518
fe5a66f9
VS		 3519 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3520 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3521 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
474d1ec4 3522
fe5a66f9
VS		 3523 /* Check if the panel supports PSR */
3524 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3525 intel_dp->psr_dpcd,
3526 sizeof(intel_dp->psr_dpcd));
3527 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3528 dev_priv->psr.sink_support = true;
3529 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3530 }
86ee27b5 3531
fe5a66f9
VS		 3532 if (INTEL_GEN(dev_priv) >= 9 &&
3533 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3534 uint8_t frame_sync_cap;
3535
3536 dev_priv->psr.sink_support = true;
3537 drm_dp_dpcd_read(&intel_dp->aux,
3538 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3539 &frame_sync_cap, 1);
3540 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3541 /* PSR2 needs frame sync as well */
3542 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3543 DRM_DEBUG_KMS("PSR2 %s on sink",
3544 dev_priv->psr.psr2_support ? "supported" : "not supported");
50003939
JN		 3545 }
3546
fe5a66f9
VS		 3547 /* Read the eDP Display control capabilities registers */
3548 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3549 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3550 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd) ==
3551 sizeof(intel_dp->edp_dpcd)))
3552 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3553 intel_dp->edp_dpcd);
06ea66b6 3554
fc0f8e25 3555 /* Intermediate frequency support */
fe5a66f9 3556 if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
94ca719e 3557 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3558 int i;
3559
9f085ebb
L		 3560 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3561 sink_rates, sizeof(sink_rates));
ea2d8a42 3562
94ca719e
VS		 3563 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3564 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3565
3566 if (val == 0)
3567 break;
3568
af77b974
SJ		 3569 /* Value read is in kHz while drm clock is saved in deca-kHz */
3570 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3571 }
94ca719e 3572 intel_dp->num_sink_rates = i;
fc0f8e25 3573 }
0336400e 3574
fe5a66f9
VS		 3575 return true;
3576}
3577
3578
3579static bool
3580intel_dp_get_dpcd(struct intel_dp *intel_dp)
3581{
3582 if (!intel_dp_read_dpcd(intel_dp))
3583 return false;
3584
3585 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3586 &intel_dp->sink_count, 1) < 0)
3587 return false;
3588
3589 /*
3590 * Sink count can change between short pulse hpd hence
3591 * a member variable in intel_dp will track any changes
3592 * between short pulse interrupts.
3593 */
3594 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3595
3596 /*
3597 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3598 * a dongle is present but no display. Unless we require to know
3599 * if a dongle is present or not, we don't need to update
3600 * downstream port information. So, an early return here saves
3601 * time from performing other operations which are not required.
3602 */
3603 if (!is_edp(intel_dp) && !intel_dp->sink_count)
3604 return false;
0336400e 3605
edb39244
AJ		 3606 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3607 DP_DWN_STRM_PORT_PRESENT))
3608 return true; /* native DP sink */
3609
3610 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3611 return true; /* no per-port downstream info */
3612
9f085ebb
L		 3613 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3614 intel_dp->downstream_ports,
3615 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3616 return false; /* downstream port status fetch failed */
3617
3618 return true;
92fd8fd1
KP		 3619}
3620
0d198328
AJ		 3621static void
3622intel_dp_probe_oui(struct intel_dp *intel_dp)
3623{
3624 u8 buf[3];
3625
3626 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3627 return;
3628
9f085ebb 3629 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3630 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3631 buf[0], buf[1], buf[2]);
3632
9f085ebb 3633 if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3634 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3635 buf[0], buf[1], buf[2]);
3636}
3637
0e32b39c 3638static bool
c4e3170a 3639intel_dp_can_mst(struct intel_dp *intel_dp)
0e32b39c
DA		 3640{
3641 u8 buf[1];
3642
7cc96139
NS		 3643 if (!i915.enable_dp_mst)
3644 return false;
3645
0e32b39c
DA		 3646 if (!intel_dp->can_mst)
3647 return false;
3648
3649 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3650 return false;
3651
c4e3170a
VS		 3652 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3653 return false;
0e32b39c 3654
c4e3170a
VS		 3655 return buf[0] & DP_MST_CAP;
3656}
3657
3658static void
3659intel_dp_configure_mst(struct intel_dp *intel_dp)
3660{
3661 if (!i915.enable_dp_mst)
3662 return;
3663
3664 if (!intel_dp->can_mst)
3665 return;
3666
3667 intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3668
3669 if (intel_dp->is_mst)
3670 DRM_DEBUG_KMS("Sink is MST capable\n");
3671 else
3672 DRM_DEBUG_KMS("Sink is not MST capable\n");
3673
3674 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3675 intel_dp->is_mst);
0e32b39c
DA		 3676}
3677
e5a1cab5 3678static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
d2e216d0 3679{
082dcc7c 3680 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3681 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c 3682 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
ad9dc91b 3683 u8 buf;
e5a1cab5 3684 int ret = 0;
c6297843
RV		 3685 int count = 0;
3686 int attempts = 10;
d2e216d0 3687
082dcc7c
RV		 3688 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3689 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3690 ret = -EIO;
3691 goto out;
4373f0f2
PZ		 3692 }
3693
082dcc7c 3694 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
e5a1cab5 3695 buf & ~DP_TEST_SINK_START) < 0) {
082dcc7c 3696 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3697 ret = -EIO;
3698 goto out;
3699 }
d2e216d0 3700
c6297843
RV		 3701 do {
3702 intel_wait_for_vblank(dev, intel_crtc->pipe);
3703
3704 if (drm_dp_dpcd_readb(&intel_dp->aux,
3705 DP_TEST_SINK_MISC, &buf) < 0) {
3706 ret = -EIO;
3707 goto out;
3708 }
3709 count = buf & DP_TEST_COUNT_MASK;
3710 } while (--attempts && count);
3711
3712 if (attempts == 0) {
dc5a9037 3713 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
c6297843
RV		 3714 ret = -ETIMEDOUT;
3715 }
3716
e5a1cab5 3717 out:
082dcc7c 3718 hsw_enable_ips(intel_crtc);
e5a1cab5 3719 return ret;
082dcc7c
RV		 3720}
3721
3722static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3723{
3724 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3725 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c
RV		 3726 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3727 u8 buf;
e5a1cab5
RV		 3728 int ret;
3729
082dcc7c
RV		 3730 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3731 return -EIO;
3732
3733 if (!(buf & DP_TEST_CRC_SUPPORTED))
3734 return -ENOTTY;
3735
3736 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3737 return -EIO;
3738
6d8175da
RV		 3739 if (buf & DP_TEST_SINK_START) {
3740 ret = intel_dp_sink_crc_stop(intel_dp);
3741 if (ret)
3742 return ret;
3743 }
3744
082dcc7c 3745 hsw_disable_ips(intel_crtc);
1dda5f93 3746
9d1a1031 3747 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
082dcc7c
RV		 3748 buf | DP_TEST_SINK_START) < 0) {
3749 hsw_enable_ips(intel_crtc);
3750 return -EIO;
4373f0f2
PZ		 3751 }
3752
d72f9d91 3753 intel_wait_for_vblank(dev, intel_crtc->pipe);
082dcc7c
RV		 3754 return 0;
3755}
3756
3757int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3758{
3759 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3760 struct drm_device *dev = dig_port->base.base.dev;
3761 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3762 u8 buf;
621d4c76 3763 int count, ret;
082dcc7c 3764 int attempts = 6;
082dcc7c
RV		 3765
3766 ret = intel_dp_sink_crc_start(intel_dp);
3767 if (ret)
3768 return ret;
3769
ad9dc91b 3770 do {
621d4c76
RV		 3771 intel_wait_for_vblank(dev, intel_crtc->pipe);
3772
1dda5f93 3773 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 3774 DP_TEST_SINK_MISC, &buf) < 0) {
3775 ret = -EIO;
afe0d67e 3776 goto stop;
4373f0f2 3777 }
621d4c76 3778 count = buf & DP_TEST_COUNT_MASK;
aabc95dc 3779
7e38eeff 3780 } while (--attempts && count == 0);
ad9dc91b
RV		 3781
3782 if (attempts == 0) {
7e38eeff
RV		 3783 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3784 ret = -ETIMEDOUT;
3785 goto stop;
3786 }
3787
3788 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3789 ret = -EIO;
3790 goto stop;
ad9dc91b 3791 }
d2e216d0 3792
afe0d67e 3793stop:
082dcc7c 3794 intel_dp_sink_crc_stop(intel_dp);
4373f0f2 3795 return ret;
d2e216d0
RV		 3796}
3797
a60f0e38
JB		 3798static bool
3799intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3800{
9f085ebb 3801 return drm_dp_dpcd_read(&intel_dp->aux,
9d1a1031
JN		 3802 DP_DEVICE_SERVICE_IRQ_VECTOR,
3803 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3804}
3805
0e32b39c
DA		 3806static bool
3807intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3808{
3809 int ret;
3810
9f085ebb 3811 ret = drm_dp_dpcd_read(&intel_dp->aux,
0e32b39c
DA		 3812 DP_SINK_COUNT_ESI,
3813 sink_irq_vector, 14);
3814 if (ret != 14)
3815 return false;
3816
3817 return true;
3818}
3819
c5d5ab7a
TP		 3820static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3821{
3822 uint8_t test_result = DP_TEST_ACK;
3823 return test_result;
3824}
3825
3826static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3827{
3828 uint8_t test_result = DP_TEST_NAK;
3829 return test_result;
3830}
3831
3832static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 3833{
c5d5ab7a 3834 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 3835 struct intel_connector *intel_connector = intel_dp->attached_connector;
3836 struct drm_connector *connector = &intel_connector->base;
3837
3838 if (intel_connector->detect_edid == NULL ||
ac6f2e29 3839 connector->edid_corrupt ||
559be30c
TP		 3840 intel_dp->aux.i2c_defer_count > 6) {
3841 /* Check EDID read for NACKs, DEFERs and corruption
3842 * (DP CTS 1.2 Core r1.1)
3843 * 4.2.2.4 : Failed EDID read, I2C_NAK
3844 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3845 * 4.2.2.6 : EDID corruption detected
3846 * Use failsafe mode for all cases
3847 */
3848 if (intel_dp->aux.i2c_nack_count > 0 ||
3849 intel_dp->aux.i2c_defer_count > 0)
3850 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3851 intel_dp->aux.i2c_nack_count,
3852 intel_dp->aux.i2c_defer_count);
3853 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3854 } else {
f79b468e
TS		 3855 struct edid *block = intel_connector->detect_edid;
3856
3857 /* We have to write the checksum
3858 * of the last block read
3859 */
3860 block += intel_connector->detect_edid->extensions;
3861
559be30c
TP		 3862 if (!drm_dp_dpcd_write(&intel_dp->aux,
3863 DP_TEST_EDID_CHECKSUM,
f79b468e 3864 &block->checksum,
5a1cc655 3865 1))
559be30c
TP		 3866 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3867
3868 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3869 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3870 }
3871
3872 /* Set test active flag here so userspace doesn't interrupt things */
3873 intel_dp->compliance_test_active = 1;
3874
c5d5ab7a
TP		 3875 return test_result;
3876}
3877
3878static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 3879{
c5d5ab7a
TP		 3880 uint8_t test_result = DP_TEST_NAK;
3881 return test_result;
3882}
3883
3884static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3885{
3886 uint8_t response = DP_TEST_NAK;
3887 uint8_t rxdata = 0;
3888 int status = 0;
3889
c5d5ab7a
TP		 3890 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3891 if (status <= 0) {
3892 DRM_DEBUG_KMS("Could not read test request from sink\n");
3893 goto update_status;
3894 }
3895
3896 switch (rxdata) {
3897 case DP_TEST_LINK_TRAINING:
3898 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3899 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3900 response = intel_dp_autotest_link_training(intel_dp);
3901 break;
3902 case DP_TEST_LINK_VIDEO_PATTERN:
3903 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3904 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3905 response = intel_dp_autotest_video_pattern(intel_dp);
3906 break;
3907 case DP_TEST_LINK_EDID_READ:
3908 DRM_DEBUG_KMS("EDID test requested\n");
3909 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3910 response = intel_dp_autotest_edid(intel_dp);
3911 break;
3912 case DP_TEST_LINK_PHY_TEST_PATTERN:
3913 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3914 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3915 response = intel_dp_autotest_phy_pattern(intel_dp);
3916 break;
3917 default:
3918 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3919 break;
3920 }
3921
3922update_status:
3923 status = drm_dp_dpcd_write(&intel_dp->aux,
3924 DP_TEST_RESPONSE,
3925 &response, 1);
3926 if (status <= 0)
3927 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 3928}
3929
0e32b39c
DA		 3930static int
3931intel_dp_check_mst_status(struct intel_dp *intel_dp)
3932{
3933 bool bret;
3934
3935 if (intel_dp->is_mst) {
3936 u8 esi[16] = { 0 };
3937 int ret = 0;
3938 int retry;
3939 bool handled;
3940 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3941go_again:
3942 if (bret == true) {
3943
3944 /* check link status - esi[10] = 0x200c */
19e0b4ca 3945 if (intel_dp->active_mst_links &&
901c2daf 3946 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
0e32b39c
DA		 3947 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3948 intel_dp_start_link_train(intel_dp);
0e32b39c
DA		 3949 intel_dp_stop_link_train(intel_dp);
3950 }
3951
6f34cc39 3952 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 3953 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3954
3955 if (handled) {
3956 for (retry = 0; retry < 3; retry++) {
3957 int wret;
3958 wret = drm_dp_dpcd_write(&intel_dp->aux,
3959 DP_SINK_COUNT_ESI+1,
3960 &esi[1], 3);
3961 if (wret == 3) {
3962 break;
3963 }
3964 }
3965
3966 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3967 if (bret == true) {
6f34cc39 3968 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 3969 goto go_again;
3970 }
3971 } else
3972 ret = 0;
3973
3974 return ret;
3975 } else {
3976 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3977 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3978 intel_dp->is_mst = false;
3979 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3980 /* send a hotplug event */
3981 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3982 }
3983 }
3984 return -EINVAL;
3985}
3986
5c9114d0
SS		 3987static void
3988intel_dp_check_link_status(struct intel_dp *intel_dp)
3989{
3990 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3991 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3992 u8 link_status[DP_LINK_STATUS_SIZE];
3993
3994 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3995
3996 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3997 DRM_ERROR("Failed to get link status\n");
3998 return;
3999 }
4000
4001 if (!intel_encoder->base.crtc)
4002 return;
4003
4004 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4005 return;
4006
4007 /* if link training is requested we should perform it always */
4008 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4009 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4010 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4011 intel_encoder->base.name);
4012 intel_dp_start_link_train(intel_dp);
4013 intel_dp_stop_link_train(intel_dp);
4014 }
4015}
4016
a4fc5ed6
KP		 4017/*
4018 * According to DP spec
4019 * 5.1.2:
4020 * 1. Read DPCD
4021 * 2. Configure link according to Receiver Capabilities
4022 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4023 * 4. Check link status on receipt of hot-plug interrupt
39ff747b
SS		 4024 *
4025 * intel_dp_short_pulse - handles short pulse interrupts
4026 * when full detection is not required.
4027 * Returns %true if short pulse is handled and full detection
4028 * is NOT required and %false otherwise.
a4fc5ed6 4029 */
39ff747b 4030static bool
5c9114d0 4031intel_dp_short_pulse(struct intel_dp *intel_dp)
a4fc5ed6 4032{
5b215bcf 4033 struct drm_device *dev = intel_dp_to_dev(intel_dp);
65fbb4e7 4034 u8 sink_irq_vector = 0;
39ff747b
SS		 4035 u8 old_sink_count = intel_dp->sink_count;
4036 bool ret;
5b215bcf 4037
4df6960e
SS		 4038 /*
4039 * Clearing compliance test variables to allow capturing
4040 * of values for next automated test request.
4041 */
4042 intel_dp->compliance_test_active = 0;
4043 intel_dp->compliance_test_type = 0;
4044 intel_dp->compliance_test_data = 0;
4045
39ff747b
SS		 4046 /*
4047 * Now read the DPCD to see if it's actually running
4048 * If the current value of sink count doesn't match with
4049 * the value that was stored earlier or dpcd read failed
4050 * we need to do full detection
4051 */
4052 ret = intel_dp_get_dpcd(intel_dp);
4053
4054 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4055 /* No need to proceed if we are going to do full detect */
4056 return false;
59cd09e1
JB		 4057 }
4058
a60f0e38
JB		 4059 /* Try to read the source of the interrupt */
4060 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
65fbb4e7
VS		 4061 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4062 sink_irq_vector != 0) {
a60f0e38 4063 /* Clear interrupt source */
9d1a1031
JN		 4064 drm_dp_dpcd_writeb(&intel_dp->aux,
4065 DP_DEVICE_SERVICE_IRQ_VECTOR,
4066 sink_irq_vector);
a60f0e38
JB		 4067
4068 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 4069 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 4070 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4071 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4072 }
4073
5c9114d0
SS		 4074 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4075 intel_dp_check_link_status(intel_dp);
4076 drm_modeset_unlock(&dev->mode_config.connection_mutex);
39ff747b
SS		 4077
4078 return true;
a4fc5ed6 4079}
a4fc5ed6 4080
caf9ab24 4081/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4082static enum drm_connector_status
26d61aad 4083intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4084{
caf9ab24 4085 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4086 uint8_t type;
4087
4088 if (!intel_dp_get_dpcd(intel_dp))
4089 return connector_status_disconnected;
4090
1034ce70
SS		 4091 if (is_edp(intel_dp))
4092 return connector_status_connected;
4093
caf9ab24
AJ		 4094 /* if there's no downstream port, we're done */
4095 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4096 return connector_status_connected;
caf9ab24
AJ		 4097
4098 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4099 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4100 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
9d1a1031 4101
30d9aa42
SS		 4102 return intel_dp->sink_count ?
4103 connector_status_connected : connector_status_disconnected;
caf9ab24
AJ		 4104 }
4105
c4e3170a
VS		 4106 if (intel_dp_can_mst(intel_dp))
4107 return connector_status_connected;
4108
caf9ab24 4109 /* If no HPD, poke DDC gently */
0b99836f 4110 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4111 return connector_status_connected;
caf9ab24
AJ		 4112
4113 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4114 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4115 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4116 if (type == DP_DS_PORT_TYPE_VGA ||
4117 type == DP_DS_PORT_TYPE_NON_EDID)
4118 return connector_status_unknown;
4119 } else {
4120 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4121 DP_DWN_STRM_PORT_TYPE_MASK;
4122 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4123 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4124 return connector_status_unknown;
4125 }
caf9ab24
AJ		 4126
4127 /* Anything else is out of spec, warn and ignore */
4128 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4129 return connector_status_disconnected;
71ba9000
AJ		 4130}
4131
d410b56d
CW		 4132static enum drm_connector_status
4133edp_detect(struct intel_dp *intel_dp)
4134{
4135 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4136 enum drm_connector_status status;
4137
4138 status = intel_panel_detect(dev);
4139 if (status == connector_status_unknown)
4140 status = connector_status_connected;
4141
4142 return status;
4143}
4144
b93433cc
JN		 4145static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4146 struct intel_digital_port *port)
5eb08b69 4147{
b93433cc 4148 u32 bit;
01cb9ea6 4149
0df53b77
JN		 4150 switch (port->port) {
4151 case PORT_A:
4152 return true;
4153 case PORT_B:
4154 bit = SDE_PORTB_HOTPLUG;
4155 break;
4156 case PORT_C:
4157 bit = SDE_PORTC_HOTPLUG;
4158 break;
4159 case PORT_D:
4160 bit = SDE_PORTD_HOTPLUG;
4161 break;
4162 default:
4163 MISSING_CASE(port->port);
4164 return false;
4165 }
4166
4167 return I915_READ(SDEISR) & bit;
4168}
4169
4170static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4171 struct intel_digital_port *port)
4172{
4173 u32 bit;
4174
4175 switch (port->port) {
4176 case PORT_A:
4177 return true;
4178 case PORT_B:
4179 bit = SDE_PORTB_HOTPLUG_CPT;
4180 break;
4181 case PORT_C:
4182 bit = SDE_PORTC_HOTPLUG_CPT;
4183 break;
4184 case PORT_D:
4185 bit = SDE_PORTD_HOTPLUG_CPT;
4186 break;
a78695d3
JN		 4187 case PORT_E:
4188 bit = SDE_PORTE_HOTPLUG_SPT;
4189 break;
0df53b77
JN		 4190 default:
4191 MISSING_CASE(port->port);
4192 return false;
b93433cc 4193 }
1b469639 4194
b93433cc 4195 return I915_READ(SDEISR) & bit;
5eb08b69
ZW		 4196}
4197
7e66bcf2 4198static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
1d245987 4199 struct intel_digital_port *port)
a4fc5ed6 4200{
9642c81c 4201 u32 bit;
5eb08b69 4202
9642c81c
JN		 4203 switch (port->port) {
4204 case PORT_B:
4205 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4206 break;
4207 case PORT_C:
4208 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4209 break;
4210 case PORT_D:
4211 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4212 break;
4213 default:
4214 MISSING_CASE(port->port);
4215 return false;
4216 }
4217
4218 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4219}
4220
0780cd36
VS		 4221static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4222 struct intel_digital_port *port)
9642c81c
JN		 4223{
4224 u32 bit;
4225
4226 switch (port->port) {
4227 case PORT_B:
0780cd36 4228 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4229 break;
4230 case PORT_C:
0780cd36 4231 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4232 break;
4233 case PORT_D:
0780cd36 4234 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4235 break;
4236 default:
4237 MISSING_CASE(port->port);
4238 return false;
a4fc5ed6
KP		 4239 }
4240
1d245987 4241 return I915_READ(PORT_HOTPLUG_STAT) & bit;
2a592bec
DA		 4242}
4243
e464bfde 4244static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
e2ec35a5 4245 struct intel_digital_port *intel_dig_port)
e464bfde 4246{
e2ec35a5
SJ		 4247 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4248 enum port port;
e464bfde
JN		 4249 u32 bit;
4250
e2ec35a5
SJ		 4251 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4252 switch (port) {
e464bfde
JN		 4253 case PORT_A:
4254 bit = BXT_DE_PORT_HP_DDIA;
4255 break;
4256 case PORT_B:
4257 bit = BXT_DE_PORT_HP_DDIB;
4258 break;
4259 case PORT_C:
4260 bit = BXT_DE_PORT_HP_DDIC;
4261 break;
4262 default:
e2ec35a5 4263 MISSING_CASE(port);
e464bfde
JN		 4264 return false;
4265 }
4266
4267 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4268}
4269
7e66bcf2
JN		 4270/*
4271 * intel_digital_port_connected - is the specified port connected?
4272 * @dev_priv: i915 private structure
4273 * @port: the port to test
4274 *
4275 * Return %true if @port is connected, %false otherwise.
4276 */
23f889bd 4277static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
7e66bcf2
JN		 4278 struct intel_digital_port *port)
4279{
0df53b77 4280 if (HAS_PCH_IBX(dev_priv))
7e66bcf2 4281 return ibx_digital_port_connected(dev_priv, port);
22824fac 4282 else if (HAS_PCH_SPLIT(dev_priv))
0df53b77 4283 return cpt_digital_port_connected(dev_priv, port);
e464bfde
JN		 4284 else if (IS_BROXTON(dev_priv))
4285 return bxt_digital_port_connected(dev_priv, port);
0780cd36
VS		 4286 else if (IS_GM45(dev_priv))
4287 return gm45_digital_port_connected(dev_priv, port);
7e66bcf2
JN		 4288 else
4289 return g4x_digital_port_connected(dev_priv, port);
4290}
4291
8c241fef 4292static struct edid *
beb60608 4293intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4294{
beb60608 4295 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4296
9cd300e0
JN		 4297 /* use cached edid if we have one */
4298 if (intel_connector->edid) {
9cd300e0
JN		 4299 /* invalid edid */
4300 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4301 return NULL;
4302
55e9edeb 4303 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4304 } else
4305 return drm_get_edid(&intel_connector->base,
4306 &intel_dp->aux.ddc);
4307}
8c241fef 4308
beb60608
CW		 4309static void
4310intel_dp_set_edid(struct intel_dp *intel_dp)
4311{
4312 struct intel_connector *intel_connector = intel_dp->attached_connector;
4313 struct edid *edid;
8c241fef 4314
f21a2198 4315 intel_dp_unset_edid(intel_dp);
beb60608
CW		 4316 edid = intel_dp_get_edid(intel_dp);
4317 intel_connector->detect_edid = edid;
4318
4319 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4320 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4321 else
4322 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4323}
4324
beb60608
CW		 4325static void
4326intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4327{
beb60608 4328 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4329
beb60608
CW		 4330 kfree(intel_connector->detect_edid);
4331 intel_connector->detect_edid = NULL;
9cd300e0 4332
beb60608
CW		 4333 intel_dp->has_audio = false;
4334}
d6f24d0f 4335
f21a2198
SS		 4336static void
4337intel_dp_long_pulse(struct intel_connector *intel_connector)
a9756bb5 4338{
f21a2198 4339 struct drm_connector *connector = &intel_connector->base;
a9756bb5 4340 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4342 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4343 struct drm_device *dev = connector->dev;
a9756bb5 4344 enum drm_connector_status status;
671dedd2 4345 enum intel_display_power_domain power_domain;
65fbb4e7 4346 u8 sink_irq_vector = 0;
a9756bb5 4347
25f78f58
VS		 4348 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4349 intel_display_power_get(to_i915(dev), power_domain);
a9756bb5 4350
d410b56d
CW		 4351 /* Can't disconnect eDP, but you can close the lid... */
4352 if (is_edp(intel_dp))
4353 status = edp_detect(intel_dp);
c555a81d
ACO		 4354 else if (intel_digital_port_connected(to_i915(dev),
4355 dp_to_dig_port(intel_dp)))
4356 status = intel_dp_detect_dpcd(intel_dp);
a9756bb5 4357 else
c555a81d
ACO		 4358 status = connector_status_disconnected;
4359
4df6960e
SS		 4360 if (status != connector_status_connected) {
4361 intel_dp->compliance_test_active = 0;
4362 intel_dp->compliance_test_type = 0;
4363 intel_dp->compliance_test_data = 0;
4364
0e505a08 4365 if (intel_dp->is_mst) {
4366 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4367 intel_dp->is_mst,
4368 intel_dp->mst_mgr.mst_state);
4369 intel_dp->is_mst = false;
4370 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4371 intel_dp->is_mst);
4372 }
4373
c8c8fb33 4374 goto out;
4df6960e 4375 }
a9756bb5 4376
f21a2198 4377 if (intel_encoder->type != INTEL_OUTPUT_EDP)
cca0502b 4378 intel_encoder->type = INTEL_OUTPUT_DP;
f21a2198 4379
fe5a66f9
VS		 4380 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4381 yesno(intel_dp_source_supports_hbr2(intel_dp)),
4382 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4383
4384 intel_dp_print_rates(intel_dp);
4385
0d198328
AJ		 4386 intel_dp_probe_oui(intel_dp);
4387
0e390a33 4388 intel_dp_print_hw_revision(intel_dp);
1a2724fa 4389 intel_dp_print_sw_revision(intel_dp);
0e390a33 4390
c4e3170a
VS		 4391 intel_dp_configure_mst(intel_dp);
4392
4393 if (intel_dp->is_mst) {
f21a2198
SS		 4394 /*
4395 * If we are in MST mode then this connector
4396 * won't appear connected or have anything
4397 * with EDID on it
4398 */
0e32b39c
DA		 4399 status = connector_status_disconnected;
4400 goto out;
7d23e3c3
SS		 4401 } else if (connector->status == connector_status_connected) {
4402 /*
4403 * If display was connected already and is still connected
4404 * check links status, there has been known issues of
4405 * link loss triggerring long pulse!!!!
4406 */
4407 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4408 intel_dp_check_link_status(intel_dp);
4409 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4410 goto out;
0e32b39c
DA		 4411 }
4412
4df6960e
SS		 4413 /*
4414 * Clearing NACK and defer counts to get their exact values
4415 * while reading EDID which are required by Compliance tests
4416 * 4.2.2.4 and 4.2.2.5
4417 */
4418 intel_dp->aux.i2c_nack_count = 0;
4419 intel_dp->aux.i2c_defer_count = 0;
4420
beb60608 4421 intel_dp_set_edid(intel_dp);
a9756bb5 4422
c8c8fb33 4423 status = connector_status_connected;
7d23e3c3 4424 intel_dp->detect_done = true;
c8c8fb33 4425
09b1eb13
TP		 4426 /* Try to read the source of the interrupt */
4427 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
65fbb4e7
VS		 4428 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4429 sink_irq_vector != 0) {
09b1eb13
TP		 4430 /* Clear interrupt source */
4431 drm_dp_dpcd_writeb(&intel_dp->aux,
4432 DP_DEVICE_SERVICE_IRQ_VECTOR,
4433 sink_irq_vector);
4434
4435 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4436 intel_dp_handle_test_request(intel_dp);
4437 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4438 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4439 }
4440
c8c8fb33 4441out:
0e505a08 4442 if ((status != connector_status_connected) &&
4443 (intel_dp->is_mst == false))
f21a2198 4444 intel_dp_unset_edid(intel_dp);
7d23e3c3 4445
25f78f58 4446 intel_display_power_put(to_i915(dev), power_domain);
f21a2198
SS		 4447 return;
4448}
4449
4450static enum drm_connector_status
4451intel_dp_detect(struct drm_connector *connector, bool force)
4452{
4453 struct intel_dp *intel_dp = intel_attached_dp(connector);
4454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4455 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4456 struct intel_connector *intel_connector = to_intel_connector(connector);
4457
4458 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4459 connector->base.id, connector->name);
4460
4461 if (intel_dp->is_mst) {
4462 /* MST devices are disconnected from a monitor POV */
4463 intel_dp_unset_edid(intel_dp);
4464 if (intel_encoder->type != INTEL_OUTPUT_EDP)
cca0502b 4465 intel_encoder->type = INTEL_OUTPUT_DP;
f21a2198
SS		 4466 return connector_status_disconnected;
4467 }
4468
7d23e3c3
SS		 4469 /* If full detect is not performed yet, do a full detect */
4470 if (!intel_dp->detect_done)
4471 intel_dp_long_pulse(intel_dp->attached_connector);
4472
4473 intel_dp->detect_done = false;
f21a2198 4474
1b7f2c8b 4475 if (is_edp(intel_dp) || intel_connector->detect_edid)
f21a2198
SS		 4476 return connector_status_connected;
4477 else
4478 return connector_status_disconnected;
a4fc5ed6
KP		 4479}
4480
beb60608
CW		 4481static void
4482intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4483{
df0e9248 4484 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4485 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
25f78f58 4486 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
671dedd2 4487 enum intel_display_power_domain power_domain;
a4fc5ed6 4488
beb60608
CW		 4489 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4490 connector->base.id, connector->name);
4491 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4492
beb60608
CW		 4493 if (connector->status != connector_status_connected)
4494 return;
671dedd2 4495
25f78f58
VS		 4496 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4497 intel_display_power_get(dev_priv, power_domain);
beb60608
CW		 4498
4499 intel_dp_set_edid(intel_dp);
4500
25f78f58 4501 intel_display_power_put(dev_priv, power_domain);
beb60608
CW		 4502
4503 if (intel_encoder->type != INTEL_OUTPUT_EDP)
cca0502b 4504 intel_encoder->type = INTEL_OUTPUT_DP;
beb60608
CW		 4505}
4506
4507static int intel_dp_get_modes(struct drm_connector *connector)
4508{
4509 struct intel_connector *intel_connector = to_intel_connector(connector);
4510 struct edid *edid;
4511
4512 edid = intel_connector->detect_edid;
4513 if (edid) {
4514 int ret = intel_connector_update_modes(connector, edid);
4515 if (ret)
4516 return ret;
4517 }
32f9d658 4518
f8779fda 4519 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4520 if (is_edp(intel_attached_dp(connector)) &&
4521 intel_connector->panel.fixed_mode) {
f8779fda 4522 struct drm_display_mode *mode;
beb60608
CW		 4523
4524 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4525 intel_connector->panel.fixed_mode);
f8779fda 4526 if (mode) {
32f9d658
ZW		 4527 drm_mode_probed_add(connector, mode);
4528 return 1;
4529 }
4530 }
beb60608 4531
32f9d658 4532 return 0;
a4fc5ed6
KP		 4533}
4534
1aad7ac0
CW		 4535static bool
4536intel_dp_detect_audio(struct drm_connector *connector)
4537{
1aad7ac0 4538 bool has_audio = false;
beb60608 4539 struct edid *edid;
1aad7ac0 4540
beb60608
CW		 4541 edid = to_intel_connector(connector)->detect_edid;
4542 if (edid)
1aad7ac0 4543 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4544
1aad7ac0
CW		 4545 return has_audio;
4546}
4547
f684960e
CW		 4548static int
4549intel_dp_set_property(struct drm_connector *connector,
4550 struct drm_property *property,
4551 uint64_t val)
4552{
fac5e23e 4553 struct drm_i915_private *dev_priv = to_i915(connector->dev);
53b41837 4554 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4555 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4556 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4557 int ret;
4558
662595df 4559 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4560 if (ret)
4561 return ret;
4562
3f43c48d 4563 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4564 int i = val;
4565 bool has_audio;
4566
4567 if (i == intel_dp->force_audio)
f684960e
CW		 4568 return 0;
4569
1aad7ac0 4570 intel_dp->force_audio = i;
f684960e 4571
c3e5f67b 4572 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4573 has_audio = intel_dp_detect_audio(connector);
4574 else
c3e5f67b 4575 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4576
4577 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4578 return 0;
4579
1aad7ac0 4580 intel_dp->has_audio = has_audio;
f684960e
CW		 4581 goto done;
4582 }
4583
e953fd7b 4584 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 4585 bool old_auto = intel_dp->color_range_auto;
0f2a2a75 4586 bool old_range = intel_dp->limited_color_range;
ae4edb80 4587
55bc60db
VS		 4588 switch (val) {
4589 case INTEL_BROADCAST_RGB_AUTO:
4590 intel_dp->color_range_auto = true;
4591 break;
4592 case INTEL_BROADCAST_RGB_FULL:
4593 intel_dp->color_range_auto = false;
0f2a2a75 4594 intel_dp->limited_color_range = false;
55bc60db
VS		 4595 break;
4596 case INTEL_BROADCAST_RGB_LIMITED:
4597 intel_dp->color_range_auto = false;
0f2a2a75 4598 intel_dp->limited_color_range = true;
55bc60db
VS		 4599 break;
4600 default:
4601 return -EINVAL;
4602 }
ae4edb80
DV		 4603
4604 if (old_auto == intel_dp->color_range_auto &&
0f2a2a75 4605 old_range == intel_dp->limited_color_range)
ae4edb80
DV		 4606 return 0;
4607
e953fd7b
CW		 4608 goto done;
4609 }
4610
53b41837
YN		 4611 if (is_edp(intel_dp) &&
4612 property == connector->dev->mode_config.scaling_mode_property) {
4613 if (val == DRM_MODE_SCALE_NONE) {
4614 DRM_DEBUG_KMS("no scaling not supported\n");
4615 return -EINVAL;
4616 }
234126c6
VS		 4617 if (HAS_GMCH_DISPLAY(dev_priv) &&
4618 val == DRM_MODE_SCALE_CENTER) {
4619 DRM_DEBUG_KMS("centering not supported\n");
4620 return -EINVAL;
4621 }
53b41837
YN		 4622
4623 if (intel_connector->panel.fitting_mode == val) {
4624 /* the eDP scaling property is not changed */
4625 return 0;
4626 }
4627 intel_connector->panel.fitting_mode = val;
4628
4629 goto done;
4630 }
4631
f684960e
CW		 4632 return -EINVAL;
4633
4634done:
c0c36b94
CW		 4635 if (intel_encoder->base.crtc)
4636 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4637
4638 return 0;
4639}
4640
7a418e34
CW		 4641static int
4642intel_dp_connector_register(struct drm_connector *connector)
4643{
4644 struct intel_dp *intel_dp = intel_attached_dp(connector);
1ebaa0b9
CW		 4645 int ret;
4646
4647 ret = intel_connector_register(connector);
4648 if (ret)
4649 return ret;
7a418e34
CW		 4650
4651 i915_debugfs_connector_add(connector);
4652
4653 DRM_DEBUG_KMS("registering %s bus for %s\n",
4654 intel_dp->aux.name, connector->kdev->kobj.name);
4655
4656 intel_dp->aux.dev = connector->kdev;
4657 return drm_dp_aux_register(&intel_dp->aux);
4658}
4659
c191eca1
CW		 4660static void
4661intel_dp_connector_unregister(struct drm_connector *connector)
4662{
4663 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4664 intel_connector_unregister(connector);
4665}
4666
a4fc5ed6 4667static void
73845adf 4668intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4669{
1d508706 4670 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4671
10e972d3 4672 kfree(intel_connector->detect_edid);
beb60608 4673
9cd300e0
JN		 4674 if (!IS_ERR_OR_NULL(intel_connector->edid))
4675 kfree(intel_connector->edid);
4676
acd8db10
PZ		 4677 /* Can't call is_edp() since the encoder may have been destroyed
4678 * already. */
4679 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4680 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4681
a4fc5ed6 4682 drm_connector_cleanup(connector);
55f78c43 4683 kfree(connector);
a4fc5ed6
KP		 4684}
4685
00c09d70 4686void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4687{
da63a9f2
PZ		 4688 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4689 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4690
0e32b39c 4691 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4692 if (is_edp(intel_dp)) {
4693 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4694 /*
4695 * vdd might still be enabled do to the delayed vdd off.
4696 * Make sure vdd is actually turned off here.
4697 */
773538e8 4698 pps_lock(intel_dp);
4be73780 4699 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4700 pps_unlock(intel_dp);
4701
01527b31
CT		 4702 if (intel_dp->edp_notifier.notifier_call) {
4703 unregister_reboot_notifier(&intel_dp->edp_notifier);
4704 intel_dp->edp_notifier.notifier_call = NULL;
4705 }
bd943159 4706 }
99681886
CW		 4707
4708 intel_dp_aux_fini(intel_dp);
4709
c8bd0e49 4710 drm_encoder_cleanup(encoder);
da63a9f2 4711 kfree(intel_dig_port);
24d05927
DV		 4712}
4713
bf93ba67 4714void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
07f9cd0b
ID		 4715{
4716 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4717
4718 if (!is_edp(intel_dp))
4719 return;
4720
951468f3
VS		 4721 /*
4722 * vdd might still be enabled do to the delayed vdd off.
4723 * Make sure vdd is actually turned off here.
4724 */
afa4e53a 4725 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4726 pps_lock(intel_dp);
07f9cd0b 4727 edp_panel_vdd_off_sync(intel_dp);
773538e8 4728 pps_unlock(intel_dp);
07f9cd0b
ID		 4729}
4730
49e6bc51
VS		 4731static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4732{
4733 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4734 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 4735 struct drm_i915_private *dev_priv = to_i915(dev);
49e6bc51
VS		 4736 enum intel_display_power_domain power_domain;
4737
4738 lockdep_assert_held(&dev_priv->pps_mutex);
4739
4740 if (!edp_have_panel_vdd(intel_dp))
4741 return;
4742
4743 /*
4744 * The VDD bit needs a power domain reference, so if the bit is
4745 * already enabled when we boot or resume, grab this reference and
4746 * schedule a vdd off, so we don't hold on to the reference
4747 * indefinitely.
4748 */
4749 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
25f78f58 4750 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
49e6bc51
VS		 4751 intel_display_power_get(dev_priv, power_domain);
4752
4753 edp_panel_vdd_schedule_off(intel_dp);
4754}
4755
bf93ba67 4756void intel_dp_encoder_reset(struct drm_encoder *encoder)
6d93c0c4 4757{
64989ca4
VS		 4758 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4759 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4760
4761 if (!HAS_DDI(dev_priv))
4762 intel_dp->DP = I915_READ(intel_dp->output_reg);
49e6bc51
VS		 4763
4764 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4765 return;
4766
49e6bc51
VS		 4767 pps_lock(intel_dp);
4768
335f752b
ID		 4769 /* Reinit the power sequencer, in case BIOS did something with it. */
4770 intel_dp_pps_init(encoder->dev, intel_dp);
49e6bc51
VS		 4771 intel_edp_panel_vdd_sanitize(intel_dp);
4772
4773 pps_unlock(intel_dp);
6d93c0c4
ID		 4774}
4775
a4fc5ed6 4776static const struct drm_connector_funcs intel_dp_connector_funcs = {
4d688a2a 4777 .dpms = drm_atomic_helper_connector_dpms,
a4fc5ed6 4778 .detect = intel_dp_detect,
beb60608 4779 .force = intel_dp_force,
a4fc5ed6 4780 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4781 .set_property = intel_dp_set_property,
2545e4a6 4782 .atomic_get_property = intel_connector_atomic_get_property,
7a418e34 4783 .late_register = intel_dp_connector_register,
c191eca1 4784 .early_unregister = intel_dp_connector_unregister,
73845adf 4785 .destroy = intel_dp_connector_destroy,
c6f95f27 4786 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4787 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4788};
4789
4790static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4791 .get_modes = intel_dp_get_modes,
4792 .mode_valid = intel_dp_mode_valid,
a4fc5ed6
KP		 4793};
4794
a4fc5ed6 4795static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4796 .reset = intel_dp_encoder_reset,
24d05927 4797 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4798};
4799
b2c5c181 4800enum irqreturn
13cf5504
DA		 4801intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4802{
4803 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4804 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c 4805 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 4806 struct drm_i915_private *dev_priv = to_i915(dev);
1c767b33 4807 enum intel_display_power_domain power_domain;
b2c5c181 4808 enum irqreturn ret = IRQ_NONE;
1c767b33 4809
2540058f
TI		 4810 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4811 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
cca0502b 4812 intel_dig_port->base.type = INTEL_OUTPUT_DP;
13cf5504 4813
7a7f84cc
VS		 4814 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4815 /*
4816 * vdd off can generate a long pulse on eDP which
4817 * would require vdd on to handle it, and thus we
4818 * would end up in an endless cycle of
4819 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4820 */
4821 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4822 port_name(intel_dig_port->port));
a8b3d52f 4823 return IRQ_HANDLED;
7a7f84cc
VS		 4824 }
4825
26fbb774
VS		 4826 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4827 port_name(intel_dig_port->port),
0e32b39c 4828 long_hpd ? "long" : "short");
13cf5504 4829
25f78f58 4830 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1c767b33
ID		 4831 intel_display_power_get(dev_priv, power_domain);
4832
0e32b39c 4833 if (long_hpd) {
7d23e3c3
SS		 4834 intel_dp_long_pulse(intel_dp->attached_connector);
4835 if (intel_dp->is_mst)
4836 ret = IRQ_HANDLED;
4837 goto put_power;
0e32b39c 4838
0e32b39c
DA		 4839 } else {
4840 if (intel_dp->is_mst) {
7d23e3c3
SS		 4841 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4842 /*
4843 * If we were in MST mode, and device is not
4844 * there, get out of MST mode
4845 */
4846 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4847 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4848 intel_dp->is_mst = false;
4849 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4850 intel_dp->is_mst);
4851 goto put_power;
4852 }
0e32b39c
DA		 4853 }
4854
39ff747b
SS		 4855 if (!intel_dp->is_mst) {
4856 if (!intel_dp_short_pulse(intel_dp)) {
4857 intel_dp_long_pulse(intel_dp->attached_connector);
4858 goto put_power;
4859 }
4860 }
0e32b39c 4861 }
b2c5c181
DV		 4862
4863 ret = IRQ_HANDLED;
4864
1c767b33
ID		 4865put_power:
4866 intel_display_power_put(dev_priv, power_domain);
4867
4868 return ret;
13cf5504
DA		 4869}
4870
477ec328 4871/* check the VBT to see whether the eDP is on another port */
5d8a7752 4872bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18 4873{
fac5e23e 4874 struct drm_i915_private *dev_priv = to_i915(dev);
36e83a18 4875
53ce81a7
VS		 4876 /*
4877 * eDP not supported on g4x. so bail out early just
4878 * for a bit extra safety in case the VBT is bonkers.
4879 */
4880 if (INTEL_INFO(dev)->gen < 5)
4881 return false;
4882
3b32a35b
VS		 4883 if (port == PORT_A)
4884 return true;
4885
951d9efe 4886 return intel_bios_is_port_edp(dev_priv, port);
36e83a18
ZY		 4887}
4888
0e32b39c 4889void
f684960e
CW		 4890intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4891{
53b41837
YN		 4892 struct intel_connector *intel_connector = to_intel_connector(connector);
4893
3f43c48d 4894 intel_attach_force_audio_property(connector);
e953fd7b 4895 intel_attach_broadcast_rgb_property(connector);
55bc60db 4896 intel_dp->color_range_auto = true;
53b41837
YN		 4897
4898 if (is_edp(intel_dp)) {
4899 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4900 drm_object_attach_property(
4901 &connector->base,
53b41837 4902 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4903 DRM_MODE_SCALE_ASPECT);
4904 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4905 }
f684960e
CW		 4906}
4907
dada1a9f
ID		 4908static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4909{
d28d4731 4910 intel_dp->panel_power_off_time = ktime_get_boottime();
dada1a9f
ID		 4911 intel_dp->last_power_on = jiffies;
4912 intel_dp->last_backlight_off = jiffies;
4913}
4914
67a54566 4915static void
54648618
ID		 4916intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
4917 struct intel_dp *intel_dp, struct edp_power_seq *seq)
67a54566 4918{
b0a08bec 4919 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
8e8232d5 4920 struct pps_registers regs;
453c5420 4921
8e8232d5 4922 intel_pps_get_registers(dev_priv, intel_dp, &regs);
67a54566
DV		 4923
4924 /* Workaround: Need to write PP_CONTROL with the unlock key as
4925 * the very first thing. */
b0a08bec 4926 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 4927
8e8232d5
ID		 4928 pp_on = I915_READ(regs.pp_on);
4929 pp_off = I915_READ(regs.pp_off);
54648618 4930 if (!IS_BROXTON(dev_priv)) {
8e8232d5
ID		 4931 I915_WRITE(regs.pp_ctrl, pp_ctl);
4932 pp_div = I915_READ(regs.pp_div);
b0a08bec 4933 }
67a54566
DV		 4934
4935 /* Pull timing values out of registers */
54648618
ID		 4936 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4937 PANEL_POWER_UP_DELAY_SHIFT;
67a54566 4938
54648618
ID		 4939 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4940 PANEL_LIGHT_ON_DELAY_SHIFT;
67a54566 4941
54648618
ID		 4942 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4943 PANEL_LIGHT_OFF_DELAY_SHIFT;
67a54566 4944
54648618
ID		 4945 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4946 PANEL_POWER_DOWN_DELAY_SHIFT;
67a54566 4947
54648618 4948 if (IS_BROXTON(dev_priv)) {
b0a08bec
VK		 4949 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4950 BXT_POWER_CYCLE_DELAY_SHIFT;
4951 if (tmp > 0)
54648618 4952 seq->t11_t12 = (tmp - 1) * 1000;
b0a08bec 4953 else
54648618 4954 seq->t11_t12 = 0;
b0a08bec 4955 } else {
54648618 4956 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 4957 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 4958 }
54648618
ID		 4959}
4960
de9c1b6b
ID		 4961static void
4962intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
4963{
4964 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4965 state_name,
4966 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
4967}
4968
4969static void
4970intel_pps_verify_state(struct drm_i915_private *dev_priv,
4971 struct intel_dp *intel_dp)
4972{
4973 struct edp_power_seq hw;
4974 struct edp_power_seq *sw = &intel_dp->pps_delays;
4975
4976 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
4977
4978 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
4979 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
4980 DRM_ERROR("PPS state mismatch\n");
4981 intel_pps_dump_state("sw", sw);
4982 intel_pps_dump_state("hw", &hw);
4983 }
4984}
4985
54648618
ID		 4986static void
4987intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4988 struct intel_dp *intel_dp)
4989{
fac5e23e 4990 struct drm_i915_private *dev_priv = to_i915(dev);
54648618
ID		 4991 struct edp_power_seq cur, vbt, spec,
4992 *final = &intel_dp->pps_delays;
4993
4994 lockdep_assert_held(&dev_priv->pps_mutex);
4995
4996 /* already initialized? */
4997 if (final->t11_t12 != 0)
4998 return;
4999
5000 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
67a54566 5001
de9c1b6b 5002 intel_pps_dump_state("cur", &cur);
67a54566 5003
6aa23e65 5004 vbt = dev_priv->vbt.edp.pps;
67a54566
DV		 5005
5006 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5007 * our hw here, which are all in 100usec. */
5008 spec.t1_t3 = 210 * 10;
5009 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5010 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5011 spec.t10 = 500 * 10;
5012 /* This one is special and actually in units of 100ms, but zero
5013 * based in the hw (so we need to add 100 ms). But the sw vbt
5014 * table multiplies it with 1000 to make it in units of 100usec,
5015 * too. */
5016 spec.t11_t12 = (510 + 100) * 10;
5017
de9c1b6b 5018 intel_pps_dump_state("vbt", &vbt);
67a54566
DV		 5019
5020 /* Use the max of the register settings and vbt. If both are
5021 * unset, fall back to the spec limits. */
36b5f425 5022#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 5023 spec.field : \
5024 max(cur.field, vbt.field))
5025 assign_final(t1_t3);
5026 assign_final(t8);
5027 assign_final(t9);
5028 assign_final(t10);
5029 assign_final(t11_t12);
5030#undef assign_final
5031
36b5f425 5032#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 5033 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5034 intel_dp->backlight_on_delay = get_delay(t8);
5035 intel_dp->backlight_off_delay = get_delay(t9);
5036 intel_dp->panel_power_down_delay = get_delay(t10);
5037 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5038#undef get_delay
5039
f30d26e4
JN		 5040 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5041 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5042 intel_dp->panel_power_cycle_delay);
5043
5044 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5045 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
de9c1b6b
ID		 5046
5047 /*
5048 * We override the HW backlight delays to 1 because we do manual waits
5049 * on them. For T8, even BSpec recommends doing it. For T9, if we
5050 * don't do this, we'll end up waiting for the backlight off delay
5051 * twice: once when we do the manual sleep, and once when we disable
5052 * the panel and wait for the PP_STATUS bit to become zero.
5053 */
5054 final->t8 = 1;
5055 final->t9 = 1;
f30d26e4
JN		 5056}
5057
5058static void
5059intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 5060 struct intel_dp *intel_dp)
f30d26e4 5061{
fac5e23e 5062 struct drm_i915_private *dev_priv = to_i915(dev);
453c5420 5063 u32 pp_on, pp_off, pp_div, port_sel = 0;
e7dc33f3 5064 int div = dev_priv->rawclk_freq / 1000;
8e8232d5 5065 struct pps_registers regs;
ad933b56 5066 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 5067 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 5068
e39b999a 5069 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 5070
8e8232d5 5071 intel_pps_get_registers(dev_priv, intel_dp, &regs);
453c5420 5072
f30d26e4 5073 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
de9c1b6b
ID		 5074 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5075 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5076 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5077 /* Compute the divisor for the pp clock, simply match the Bspec
5078 * formula. */
b0a08bec 5079 if (IS_BROXTON(dev)) {
8e8232d5 5080 pp_div = I915_READ(regs.pp_ctrl);
b0a08bec
VK		 5081 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5082 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5083 << BXT_POWER_CYCLE_DELAY_SHIFT);
5084 } else {
5085 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5086 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5087 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5088 }
67a54566
DV		 5089
5090 /* Haswell doesn't have any port selection bits for the panel
5091 * power sequencer any more. */
666a4537 5092 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
ad933b56 5093 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 5094 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 5095 if (port == PORT_A)
a24c144c 5096 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5097 else
a24c144c 5098 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5099 }
5100
453c5420
JB		 5101 pp_on |= port_sel;
5102
8e8232d5
ID		 5103 I915_WRITE(regs.pp_on, pp_on);
5104 I915_WRITE(regs.pp_off, pp_off);
b0a08bec 5105 if (IS_BROXTON(dev))
8e8232d5 5106 I915_WRITE(regs.pp_ctrl, pp_div);
b0a08bec 5107 else
8e8232d5 5108 I915_WRITE(regs.pp_div, pp_div);
67a54566 5109
67a54566 5110 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
8e8232d5
ID		 5111 I915_READ(regs.pp_on),
5112 I915_READ(regs.pp_off),
b0a08bec 5113 IS_BROXTON(dev) ?
8e8232d5
ID		 5114 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5115 I915_READ(regs.pp_div));
f684960e
CW		 5116}
5117
335f752b
ID		 5118static void intel_dp_pps_init(struct drm_device *dev,
5119 struct intel_dp *intel_dp)
5120{
5121 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5122 vlv_initial_power_sequencer_setup(intel_dp);
5123 } else {
5124 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5125 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5126 }
5127}
5128
b33a2815
VK		 5129/**
5130 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5423adf1 5131 * @dev_priv: i915 device
e896402c 5132 * @crtc_state: a pointer to the active intel_crtc_state
b33a2815
VK		 5133 * @refresh_rate: RR to be programmed
5134 *
5135 * This function gets called when refresh rate (RR) has to be changed from
5136 * one frequency to another. Switches can be between high and low RR
5137 * supported by the panel or to any other RR based on media playback (in
5138 * this case, RR value needs to be passed from user space).
5139 *
5140 * The caller of this function needs to take a lock on dev_priv->drrs.
5141 */
85cb48a1
ML		 5142static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5143 struct intel_crtc_state *crtc_state,
5144 int refresh_rate)
439d7ac0 5145{
439d7ac0 5146 struct intel_encoder *encoder;
96178eeb
VK		 5147 struct intel_digital_port *dig_port = NULL;
5148 struct intel_dp *intel_dp = dev_priv->drrs.dp;
85cb48a1 5149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
96178eeb 5150 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5151
5152 if (refresh_rate <= 0) {
5153 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5154 return;
5155 }
5156
96178eeb
VK		 5157 if (intel_dp == NULL) {
5158 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5159 return;
5160 }
5161
1fcc9d1c 5162 /*
e4d59f6b
RV		 5163 * FIXME: This needs proper synchronization with psr state for some
5164 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5165 */
439d7ac0 5166
96178eeb
VK		 5167 dig_port = dp_to_dig_port(intel_dp);
5168 encoder = &dig_port->base;
723f9aab 5169 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5170
5171 if (!intel_crtc) {
5172 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5173 return;
5174 }
5175
96178eeb 5176 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5177 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5178 return;
5179 }
5180
96178eeb
VK		 5181 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5182 refresh_rate)
439d7ac0
PB		 5183 index = DRRS_LOW_RR;
5184
96178eeb 5185 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5186 DRM_DEBUG_KMS(
5187 "DRRS requested for previously set RR...ignoring\n");
5188 return;
5189 }
5190
85cb48a1 5191 if (!crtc_state->base.active) {
439d7ac0
PB		 5192 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5193 return;
5194 }
5195
85cb48a1 5196 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
a4c30b1d
VK		 5197 switch (index) {
5198 case DRRS_HIGH_RR:
5199 intel_dp_set_m_n(intel_crtc, M1_N1);
5200 break;
5201 case DRRS_LOW_RR:
5202 intel_dp_set_m_n(intel_crtc, M2_N2);
5203 break;
5204 case DRRS_MAX_RR:
5205 default:
5206 DRM_ERROR("Unsupported refreshrate type\n");
5207 }
85cb48a1
ML		 5208 } else if (INTEL_GEN(dev_priv) > 6) {
5209 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
649636ef 5210 u32 val;
a4c30b1d 5211
649636ef 5212 val = I915_READ(reg);
439d7ac0 5213 if (index > DRRS_HIGH_RR) {
85cb48a1 5214 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6fa7aec1
VK		 5215 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5216 else
5217 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5218 } else {
85cb48a1 5219 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6fa7aec1
VK		 5220 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5221 else
5222 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5223 }
5224 I915_WRITE(reg, val);
5225 }
5226
4e9ac947
VK		 5227 dev_priv->drrs.refresh_rate_type = index;
5228
5229 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5230}
5231
b33a2815
VK		 5232/**
5233 * intel_edp_drrs_enable - init drrs struct if supported
5234 * @intel_dp: DP struct
5423adf1 5235 * @crtc_state: A pointer to the active crtc state.
b33a2815
VK		 5236 *
5237 * Initializes frontbuffer_bits and drrs.dp
5238 */
85cb48a1
ML		 5239void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5240 struct intel_crtc_state *crtc_state)
c395578e
VK		 5241{
5242 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 5243 struct drm_i915_private *dev_priv = to_i915(dev);
c395578e 5244
85cb48a1 5245 if (!crtc_state->has_drrs) {
c395578e
VK		 5246 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5247 return;
5248 }
5249
5250 mutex_lock(&dev_priv->drrs.mutex);
5251 if (WARN_ON(dev_priv->drrs.dp)) {
5252 DRM_ERROR("DRRS already enabled\n");
5253 goto unlock;
5254 }
5255
5256 dev_priv->drrs.busy_frontbuffer_bits = 0;
5257
5258 dev_priv->drrs.dp = intel_dp;
5259
5260unlock:
5261 mutex_unlock(&dev_priv->drrs.mutex);
5262}
5263
b33a2815
VK		 5264/**
5265 * intel_edp_drrs_disable - Disable DRRS
5266 * @intel_dp: DP struct
5423adf1 5267 * @old_crtc_state: Pointer to old crtc_state.
b33a2815
VK		 5268 *
5269 */
85cb48a1
ML		 5270void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5271 struct intel_crtc_state *old_crtc_state)
c395578e
VK		 5272{
5273 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 5274 struct drm_i915_private *dev_priv = to_i915(dev);
c395578e 5275
85cb48a1 5276 if (!old_crtc_state->has_drrs)
c395578e
VK		 5277 return;
5278
5279 mutex_lock(&dev_priv->drrs.mutex);
5280 if (!dev_priv->drrs.dp) {
5281 mutex_unlock(&dev_priv->drrs.mutex);
5282 return;
5283 }
5284
5285 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
85cb48a1
ML		 5286 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5287 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
c395578e
VK		 5288
5289 dev_priv->drrs.dp = NULL;
5290 mutex_unlock(&dev_priv->drrs.mutex);
5291
5292 cancel_delayed_work_sync(&dev_priv->drrs.work);
5293}
5294
4e9ac947
VK		 5295static void intel_edp_drrs_downclock_work(struct work_struct *work)
5296{
5297 struct drm_i915_private *dev_priv =
5298 container_of(work, typeof(*dev_priv), drrs.work.work);
5299 struct intel_dp *intel_dp;
5300
5301 mutex_lock(&dev_priv->drrs.mutex);
5302
5303 intel_dp = dev_priv->drrs.dp;
5304
5305 if (!intel_dp)
5306 goto unlock;
5307
439d7ac0 5308 /*
4e9ac947
VK		 5309 * The delayed work can race with an invalidate hence we need to
5310 * recheck.
439d7ac0
PB		 5311 */
5312
4e9ac947
VK		 5313 if (dev_priv->drrs.busy_frontbuffer_bits)
5314 goto unlock;
439d7ac0 5315
85cb48a1
ML		 5316 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5317 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5318
5319 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5320 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5321 }
439d7ac0 5322
4e9ac947 5323unlock:
4e9ac947 5324 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5325}
5326
b33a2815 5327/**
0ddfd203 5328 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5748b6a1 5329 * @dev_priv: i915 device
b33a2815
VK		 5330 * @frontbuffer_bits: frontbuffer plane tracking bits
5331 *
0ddfd203
R		 5332 * This function gets called everytime rendering on the given planes start.
5333 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5334 *
5335 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5336 */
5748b6a1
CW		 5337void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5338 unsigned int frontbuffer_bits)
a93fad0f 5339{
a93fad0f
VK		 5340 struct drm_crtc *crtc;
5341 enum pipe pipe;
5342
9da7d693 5343 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5344 return;
5345
88f933a8 5346 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5347
a93fad0f 5348 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5349 if (!dev_priv->drrs.dp) {
5350 mutex_unlock(&dev_priv->drrs.mutex);
5351 return;
5352 }
5353
a93fad0f
VK		 5354 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5355 pipe = to_intel_crtc(crtc)->pipe;
5356
c1d038c6
DV		 5357 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5358 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5359
0ddfd203 5360 /* invalidate means busy screen hence upclock */
c1d038c6 5361 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
85cb48a1
ML		 5362 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5363 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
a93fad0f 5364
a93fad0f
VK		 5365 mutex_unlock(&dev_priv->drrs.mutex);
5366}
5367
b33a2815 5368/**
0ddfd203 5369 * intel_edp_drrs_flush - Restart Idleness DRRS
5748b6a1 5370 * @dev_priv: i915 device
b33a2815
VK		 5371 * @frontbuffer_bits: frontbuffer plane tracking bits
5372 *
0ddfd203
R		 5373 * This function gets called every time rendering on the given planes has
5374 * completed or flip on a crtc is completed. So DRRS should be upclocked
5375 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5376 * if no other planes are dirty.
b33a2815
VK		 5377 *
5378 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5379 */
5748b6a1
CW		 5380void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5381 unsigned int frontbuffer_bits)
a93fad0f 5382{
a93fad0f
VK		 5383 struct drm_crtc *crtc;
5384 enum pipe pipe;
5385
9da7d693 5386 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5387 return;
5388
88f933a8 5389 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5390
a93fad0f 5391 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5392 if (!dev_priv->drrs.dp) {
5393 mutex_unlock(&dev_priv->drrs.mutex);
5394 return;
5395 }
5396
a93fad0f
VK		 5397 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5398 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5399
5400 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5401 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5402
0ddfd203 5403 /* flush means busy screen hence upclock */
c1d038c6 5404 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
85cb48a1
ML		 5405 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5406 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
0ddfd203
R		 5407
5408 /*
5409 * flush also means no more activity hence schedule downclock, if all
5410 * other fbs are quiescent too
5411 */
5412 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5413 schedule_delayed_work(&dev_priv->drrs.work,
5414 msecs_to_jiffies(1000));
5415 mutex_unlock(&dev_priv->drrs.mutex);
5416}
5417
b33a2815
VK		 5418/**
5419 * DOC: Display Refresh Rate Switching (DRRS)
5420 *
5421 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5422 * which enables swtching between low and high refresh rates,
5423 * dynamically, based on the usage scenario. This feature is applicable
5424 * for internal panels.
5425 *
5426 * Indication that the panel supports DRRS is given by the panel EDID, which
5427 * would list multiple refresh rates for one resolution.
5428 *
5429 * DRRS is of 2 types - static and seamless.
5430 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5431 * (may appear as a blink on screen) and is used in dock-undock scenario.
5432 * Seamless DRRS involves changing RR without any visual effect to the user
5433 * and can be used during normal system usage. This is done by programming
5434 * certain registers.
5435 *
5436 * Support for static/seamless DRRS may be indicated in the VBT based on
5437 * inputs from the panel spec.
5438 *
5439 * DRRS saves power by switching to low RR based on usage scenarios.
5440 *
2e7a5701
DV		 5441 * The implementation is based on frontbuffer tracking implementation. When
5442 * there is a disturbance on the screen triggered by user activity or a periodic
5443 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5444 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5445 * made.
5446 *
5447 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5448 * and intel_edp_drrs_flush() are called.
b33a2815
VK		 5449 *
5450 * DRRS can be further extended to support other internal panels and also
5451 * the scenario of video playback wherein RR is set based on the rate
5452 * requested by userspace.
5453 */
5454
5455/**
5456 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5457 * @intel_connector: eDP connector
5458 * @fixed_mode: preferred mode of panel
5459 *
5460 * This function is called only once at driver load to initialize basic
5461 * DRRS stuff.
5462 *
5463 * Returns:
5464 * Downclock mode if panel supports it, else return NULL.
5465 * DRRS support is determined by the presence of downclock mode (apart
5466 * from VBT setting).
5467 */
4f9db5b5 5468static struct drm_display_mode *
96178eeb
VK		 5469intel_dp_drrs_init(struct intel_connector *intel_connector,
5470 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5471{
5472 struct drm_connector *connector = &intel_connector->base;
96178eeb 5473 struct drm_device *dev = connector->dev;
fac5e23e 5474 struct drm_i915_private *dev_priv = to_i915(dev);
4f9db5b5
PB		 5475 struct drm_display_mode *downclock_mode = NULL;
5476
9da7d693
DV		 5477 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5478 mutex_init(&dev_priv->drrs.mutex);
5479
4f9db5b5
PB		 5480 if (INTEL_INFO(dev)->gen <= 6) {
5481 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5482 return NULL;
5483 }
5484
5485 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5486 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5487 return NULL;
5488 }
5489
5490 downclock_mode = intel_find_panel_downclock
5491 (dev, fixed_mode, connector);
5492
5493 if (!downclock_mode) {
a1d26342 5494 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5495 return NULL;
5496 }
5497
96178eeb 5498 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5499
96178eeb 5500 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5501 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5502 return downclock_mode;
5503}
5504
ed92f0b2 5505static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5506 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5507{
5508 struct drm_connector *connector = &intel_connector->base;
5509 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5510 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5511 struct drm_device *dev = intel_encoder->base.dev;
fac5e23e 5512 struct drm_i915_private *dev_priv = to_i915(dev);
ed92f0b2 5513 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5514 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5515 bool has_dpcd;
5516 struct drm_display_mode *scan;
5517 struct edid *edid;
6517d273 5518 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5519
5520 if (!is_edp(intel_dp))
5521 return true;
5522
97a824e1
ID		 5523 /*
5524 * On IBX/CPT we may get here with LVDS already registered. Since the
5525 * driver uses the only internal power sequencer available for both
5526 * eDP and LVDS bail out early in this case to prevent interfering
5527 * with an already powered-on LVDS power sequencer.
5528 */
5529 if (intel_get_lvds_encoder(dev)) {
5530 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5531 DRM_INFO("LVDS was detected, not registering eDP\n");
5532
5533 return false;
5534 }
5535
49e6bc51 5536 pps_lock(intel_dp);
b4d06ede
ID		 5537
5538 intel_dp_init_panel_power_timestamps(intel_dp);
335f752b 5539 intel_dp_pps_init(dev, intel_dp);
49e6bc51 5540 intel_edp_panel_vdd_sanitize(intel_dp);
b4d06ede 5541
49e6bc51 5542 pps_unlock(intel_dp);
63635217 5543
ed92f0b2 5544 /* Cache DPCD and EDID for edp. */
fe5a66f9 5545 has_dpcd = intel_edp_init_dpcd(intel_dp);
ed92f0b2 5546
fe5a66f9 5547 if (!has_dpcd) {
ed92f0b2
PZ		 5548 /* if this fails, presume the device is a ghost */
5549 DRM_INFO("failed to retrieve link info, disabling eDP\n");
b4d06ede 5550 goto out_vdd_off;
ed92f0b2
PZ		 5551 }
5552
060c8778 5553 mutex_lock(&dev->mode_config.mutex);
0b99836f 5554 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5555 if (edid) {
5556 if (drm_add_edid_modes(connector, edid)) {
5557 drm_mode_connector_update_edid_property(connector,
5558 edid);
5559 drm_edid_to_eld(connector, edid);
5560 } else {
5561 kfree(edid);
5562 edid = ERR_PTR(-EINVAL);
5563 }
5564 } else {
5565 edid = ERR_PTR(-ENOENT);
5566 }
5567 intel_connector->edid = edid;
5568
5569 /* prefer fixed mode from EDID if available */
5570 list_for_each_entry(scan, &connector->probed_modes, head) {
5571 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5572 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5573 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5574 intel_connector, fixed_mode);
ed92f0b2
PZ		 5575 break;
5576 }
5577 }
5578
5579 /* fallback to VBT if available for eDP */
5580 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5581 fixed_mode = drm_mode_duplicate(dev,
5582 dev_priv->vbt.lfp_lvds_vbt_mode);
df457245 5583 if (fixed_mode) {
ed92f0b2 5584 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
df457245
VS		 5585 connector->display_info.width_mm = fixed_mode->width_mm;
5586 connector->display_info.height_mm = fixed_mode->height_mm;
5587 }
ed92f0b2 5588 }
060c8778 5589 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5590
666a4537 5591 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
01527b31
CT		 5592 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5593 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5594
5595 /*
5596 * Figure out the current pipe for the initial backlight setup.
5597 * If the current pipe isn't valid, try the PPS pipe, and if that
5598 * fails just assume pipe A.
5599 */
5600 if (IS_CHERRYVIEW(dev))
5601 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5602 else
5603 pipe = PORT_TO_PIPE(intel_dp->DP);
5604
5605 if (pipe != PIPE_A && pipe != PIPE_B)
5606 pipe = intel_dp->pps_pipe;
5607
5608 if (pipe != PIPE_A && pipe != PIPE_B)
5609 pipe = PIPE_A;
5610
5611 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5612 pipe_name(pipe));
01527b31
CT		 5613 }
5614
4f9db5b5 5615 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5507faeb 5616 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6517d273 5617 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5618
5619 return true;
b4d06ede
ID		 5620
5621out_vdd_off:
5622 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5623 /*
5624 * vdd might still be enabled do to the delayed vdd off.
5625 * Make sure vdd is actually turned off here.
5626 */
5627 pps_lock(intel_dp);
5628 edp_panel_vdd_off_sync(intel_dp);
5629 pps_unlock(intel_dp);
5630
5631 return false;
ed92f0b2
PZ		 5632}
5633
16c25533 5634bool
f0fec3f2
PZ		 5635intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5636 struct intel_connector *intel_connector)
a4fc5ed6 5637{
f0fec3f2
PZ		 5638 struct drm_connector *connector = &intel_connector->base;
5639 struct intel_dp *intel_dp = &intel_dig_port->dp;
5640 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5641 struct drm_device *dev = intel_encoder->base.dev;
fac5e23e 5642 struct drm_i915_private *dev_priv = to_i915(dev);
174edf1f 5643 enum port port = intel_dig_port->port;
7a418e34 5644 int type;
a4fc5ed6 5645
ccb1a831
VS		 5646 if (WARN(intel_dig_port->max_lanes < 1,
5647 "Not enough lanes (%d) for DP on port %c\n",
5648 intel_dig_port->max_lanes, port_name(port)))
5649 return false;
5650
a4a5d2f8
VS		 5651 intel_dp->pps_pipe = INVALID_PIPE;
5652
ec5b01dd 5653 /* intel_dp vfuncs */
b6b5e383
DL		 5654 if (INTEL_INFO(dev)->gen >= 9)
5655 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
ec5b01dd
DL		 5656 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5657 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5658 else if (HAS_PCH_SPLIT(dev))
5659 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5660 else
6ffb1be7 5661 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
ec5b01dd 5662
b9ca5fad
DL		 5663 if (INTEL_INFO(dev)->gen >= 9)
5664 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5665 else
6ffb1be7 5666 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
153b1100 5667
ad64217b
ACO		 5668 if (HAS_DDI(dev))
5669 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5670
0767935e
DV		 5671 /* Preserve the current hw state. */
5672 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5673 intel_dp->attached_connector = intel_connector;
3d3dc149 5674
3b32a35b 5675 if (intel_dp_is_edp(dev, port))
b329530c 5676 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5677 else
5678 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5679
f7d24902
ID		 5680 /*
5681 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5682 * for DP the encoder type can be set by the caller to
5683 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5684 */
5685 if (type == DRM_MODE_CONNECTOR_eDP)
5686 intel_encoder->type = INTEL_OUTPUT_EDP;
5687
c17ed5b5 5688 /* eDP only on port B and/or C on vlv/chv */
666a4537
WB		 5689 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5690 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
c17ed5b5
VS		 5691 return false;
5692
e7281eab
ID		 5693 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5694 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5695 port_name(port));
5696
b329530c 5697 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5698 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5699
a4fc5ed6
KP		 5700 connector->interlace_allowed = true;
5701 connector->doublescan_allowed = 0;
5702
b6339585 5703 intel_dp_aux_init(intel_dp);
7a418e34 5704
f0fec3f2 5705 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5706 edp_panel_vdd_work);
a4fc5ed6 5707
df0e9248 5708 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6 5709
affa9354 5710 if (HAS_DDI(dev))
bcbc889b
PZ		 5711 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5712 else
5713 intel_connector->get_hw_state = intel_connector_get_hw_state;
5714
0b99836f 5715 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5716 switch (port) {
5717 case PORT_A:
1d843f9d 5718 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5719 break;
5720 case PORT_B:
1d843f9d 5721 intel_encoder->hpd_pin = HPD_PORT_B;
e87a005d 5722 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
cf1d5883 5723 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5724 break;
5725 case PORT_C:
1d843f9d 5726 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5727 break;
5728 case PORT_D:
1d843f9d 5729 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30 5730 break;
26951caf
XZ		 5731 case PORT_E:
5732 intel_encoder->hpd_pin = HPD_PORT_E;
5733 break;
ab9d7c30 5734 default:
ad1c0b19 5735 BUG();
5eb08b69
ZW		 5736 }
5737
0e32b39c 5738 /* init MST on ports that can support it */
f8e58ddf 5739 if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
0c9b3715
JN		 5740 (port == PORT_B || port == PORT_C || port == PORT_D))
5741 intel_dp_mst_encoder_init(intel_dig_port,
5742 intel_connector->base.base.id);
0e32b39c 5743
36b5f425 5744 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
a121f4e5
VS		 5745 intel_dp_aux_fini(intel_dp);
5746 intel_dp_mst_encoder_cleanup(intel_dig_port);
5747 goto fail;
b2f246a8 5748 }
32f9d658 5749
f684960e
CW		 5750 intel_dp_add_properties(intel_dp, connector);
5751
a4fc5ed6
KP		 5752 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5753 * 0xd. Failure to do so will result in spurious interrupts being
5754 * generated on the port when a cable is not attached.
5755 */
5756 if (IS_G4X(dev) && !IS_GM45(dev)) {
5757 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5758 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5759 }
16c25533
PZ		 5760
5761 return true;
a121f4e5
VS		 5762
5763fail:
a121f4e5
VS		 5764 drm_connector_cleanup(connector);
5765
5766 return false;
a4fc5ed6 5767}
f0fec3f2 5768
457c52d8
CW		 5769bool intel_dp_init(struct drm_device *dev,
5770 i915_reg_t output_reg,
5771 enum port port)
f0fec3f2 5772{
fac5e23e 5773 struct drm_i915_private *dev_priv = to_i915(dev);
f0fec3f2
PZ		 5774 struct intel_digital_port *intel_dig_port;
5775 struct intel_encoder *intel_encoder;
5776 struct drm_encoder *encoder;
5777 struct intel_connector *intel_connector;
5778
b14c5679 5779 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2 5780 if (!intel_dig_port)
457c52d8 5781 return false;
f0fec3f2 5782
08d9bc92 5783 intel_connector = intel_connector_alloc();
11aee0f6
SM		 5784 if (!intel_connector)
5785 goto err_connector_alloc;
f0fec3f2
PZ		 5786
5787 intel_encoder = &intel_dig_port->base;
5788 encoder = &intel_encoder->base;
5789
893da0c9 5790 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
580d8ed5 5791 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
893da0c9 5792 goto err_encoder_init;
f0fec3f2 5793
5bfe2ac0 5794 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5795 intel_encoder->disable = intel_disable_dp;
00c09d70 5796 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5797 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5798 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5799 if (IS_CHERRYVIEW(dev)) {
9197c88b 5800 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5801 intel_encoder->pre_enable = chv_pre_enable_dp;
5802 intel_encoder->enable = vlv_enable_dp;
580d3811 5803 intel_encoder->post_disable = chv_post_disable_dp;
d6db995f 5804 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
e4a1d846 5805 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5806 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5807 intel_encoder->pre_enable = vlv_pre_enable_dp;
5808 intel_encoder->enable = vlv_enable_dp;
49277c31 5809 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5810 } else {
ecff4f3b
JN		 5811 intel_encoder->pre_enable = g4x_pre_enable_dp;
5812 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5813 if (INTEL_INFO(dev)->gen >= 5)
5814 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5815 }
f0fec3f2 5816
174edf1f 5817 intel_dig_port->port = port;
f0fec3f2 5818 intel_dig_port->dp.output_reg = output_reg;
ccb1a831 5819 intel_dig_port->max_lanes = 4;
f0fec3f2 5820
cca0502b 5821 intel_encoder->type = INTEL_OUTPUT_DP;
882ec384
VS		 5822 if (IS_CHERRYVIEW(dev)) {
5823 if (port == PORT_D)
5824 intel_encoder->crtc_mask = 1 << 2;
5825 else
5826 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5827 } else {
5828 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5829 }
bc079e8b 5830 intel_encoder->cloneable = 0;
03cdc1d4 5831 intel_encoder->port = port;
f0fec3f2 5832
13cf5504 5833 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 5834 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 5835
11aee0f6
SM		 5836 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5837 goto err_init_connector;
5838
457c52d8 5839 return true;
11aee0f6
SM		 5840
5841err_init_connector:
5842 drm_encoder_cleanup(encoder);
893da0c9 5843err_encoder_init:
11aee0f6
SM		 5844 kfree(intel_connector);
5845err_connector_alloc:
5846 kfree(intel_dig_port);
457c52d8 5847 return false;
f0fec3f2 5848}
0e32b39c
DA		 5849
5850void intel_dp_mst_suspend(struct drm_device *dev)
5851{
fac5e23e 5852 struct drm_i915_private *dev_priv = to_i915(dev);
0e32b39c
DA		 5853 int i;
5854
5855 /* disable MST */
5856 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5857 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5aa56969
VS		 5858
5859 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
0e32b39c
DA		 5860 continue;
5861
5aa56969
VS		 5862 if (intel_dig_port->dp.is_mst)
5863 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
0e32b39c
DA		 5864 }
5865}
5866
5867void intel_dp_mst_resume(struct drm_device *dev)
5868{
fac5e23e 5869 struct drm_i915_private *dev_priv = to_i915(dev);
0e32b39c
DA		 5870 int i;
5871
5872 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5873 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5aa56969 5874 int ret;
0e32b39c 5875
5aa56969
VS		 5876 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5877 continue;
0e32b39c 5878
5aa56969
VS		 5879 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5880 if (ret)
5881 intel_dp_check_mst_status(&intel_dig_port->dp);
0e32b39c
DA		 5882 }
5883}
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