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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
a4fc5ed6 KP |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "drm_crtc_helper.h" | |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
ab2c0672 | 37 | #include "drm_dp_helper.h" |
a4fc5ed6 | 38 | |
a2006cf5 | 39 | #define DP_RECEIVER_CAP_SIZE 0xf |
a4fc5ed6 KP |
40 | #define DP_LINK_STATUS_SIZE 6 |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) | |
42 | ||
43 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
44 | ||
ea5b213a CW |
45 | struct intel_dp { |
46 | struct intel_encoder base; | |
a4fc5ed6 KP |
47 | uint32_t output_reg; |
48 | uint32_t DP; | |
49 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
a4fc5ed6 | 50 | bool has_audio; |
f684960e | 51 | int force_audio; |
e953fd7b | 52 | uint32_t color_range; |
d2b996ac | 53 | int dpms_mode; |
a4fc5ed6 KP |
54 | uint8_t link_bw; |
55 | uint8_t lane_count; | |
a2006cf5 | 56 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
a4fc5ed6 KP |
57 | struct i2c_adapter adapter; |
58 | struct i2c_algo_dp_aux_data algo; | |
f0917379 | 59 | bool is_pch_edp; |
33a34e4e JB |
60 | uint8_t train_set[4]; |
61 | uint8_t link_status[DP_LINK_STATUS_SIZE]; | |
f01eca2e KP |
62 | int panel_power_up_delay; |
63 | int panel_power_down_delay; | |
64 | int panel_power_cycle_delay; | |
65 | int backlight_on_delay; | |
66 | int backlight_off_delay; | |
d15456de | 67 | struct drm_display_mode *panel_fixed_mode; /* for eDP */ |
bd943159 KP |
68 | struct delayed_work panel_vdd_work; |
69 | bool want_panel_vdd; | |
70 | unsigned long panel_off_jiffies; | |
a4fc5ed6 KP |
71 | }; |
72 | ||
cfcb0fc9 JB |
73 | /** |
74 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
75 | * @intel_dp: DP struct | |
76 | * | |
77 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
78 | * will return true, and false otherwise. | |
79 | */ | |
80 | static bool is_edp(struct intel_dp *intel_dp) | |
81 | { | |
82 | return intel_dp->base.type == INTEL_OUTPUT_EDP; | |
83 | } | |
84 | ||
85 | /** | |
86 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? | |
87 | * @intel_dp: DP struct | |
88 | * | |
89 | * Returns true if the given DP struct corresponds to a PCH DP port attached | |
90 | * to an eDP panel, false otherwise. Helpful for determining whether we | |
91 | * may need FDI resources for a given DP output or not. | |
92 | */ | |
93 | static bool is_pch_edp(struct intel_dp *intel_dp) | |
94 | { | |
95 | return intel_dp->is_pch_edp; | |
96 | } | |
97 | ||
ea5b213a CW |
98 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
99 | { | |
4ef69c7a | 100 | return container_of(encoder, struct intel_dp, base.base); |
ea5b213a | 101 | } |
a4fc5ed6 | 102 | |
df0e9248 CW |
103 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
104 | { | |
105 | return container_of(intel_attached_encoder(connector), | |
106 | struct intel_dp, base); | |
107 | } | |
108 | ||
814948ad JB |
109 | /** |
110 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? | |
111 | * @encoder: DRM encoder | |
112 | * | |
113 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed | |
114 | * by intel_display.c. | |
115 | */ | |
116 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) | |
117 | { | |
118 | struct intel_dp *intel_dp; | |
119 | ||
120 | if (!encoder) | |
121 | return false; | |
122 | ||
123 | intel_dp = enc_to_intel_dp(encoder); | |
124 | ||
125 | return is_pch_edp(intel_dp); | |
126 | } | |
127 | ||
33a34e4e JB |
128 | static void intel_dp_start_link_train(struct intel_dp *intel_dp); |
129 | static void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
ea5b213a | 130 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
a4fc5ed6 | 131 | |
32f9d658 | 132 | void |
0206e353 | 133 | intel_edp_link_config(struct intel_encoder *intel_encoder, |
ea5b213a | 134 | int *lane_num, int *link_bw) |
32f9d658 | 135 | { |
ea5b213a | 136 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
32f9d658 | 137 | |
ea5b213a CW |
138 | *lane_num = intel_dp->lane_count; |
139 | if (intel_dp->link_bw == DP_LINK_BW_1_62) | |
32f9d658 | 140 | *link_bw = 162000; |
ea5b213a | 141 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
32f9d658 ZW |
142 | *link_bw = 270000; |
143 | } | |
144 | ||
a4fc5ed6 | 145 | static int |
ea5b213a | 146 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
a4fc5ed6 | 147 | { |
a4fc5ed6 KP |
148 | int max_lane_count = 4; |
149 | ||
7183dc29 JB |
150 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
151 | max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; | |
a4fc5ed6 KP |
152 | switch (max_lane_count) { |
153 | case 1: case 2: case 4: | |
154 | break; | |
155 | default: | |
156 | max_lane_count = 4; | |
157 | } | |
158 | } | |
159 | return max_lane_count; | |
160 | } | |
161 | ||
162 | static int | |
ea5b213a | 163 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 164 | { |
7183dc29 | 165 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
166 | |
167 | switch (max_link_bw) { | |
168 | case DP_LINK_BW_1_62: | |
169 | case DP_LINK_BW_2_7: | |
170 | break; | |
171 | default: | |
172 | max_link_bw = DP_LINK_BW_1_62; | |
173 | break; | |
174 | } | |
175 | return max_link_bw; | |
176 | } | |
177 | ||
178 | static int | |
179 | intel_dp_link_clock(uint8_t link_bw) | |
180 | { | |
181 | if (link_bw == DP_LINK_BW_2_7) | |
182 | return 270000; | |
183 | else | |
184 | return 162000; | |
185 | } | |
186 | ||
cd9dde44 AJ |
187 | /* |
188 | * The units on the numbers in the next two are... bizarre. Examples will | |
189 | * make it clearer; this one parallels an example in the eDP spec. | |
190 | * | |
191 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
192 | * | |
193 | * 270000 * 1 * 8 / 10 == 216000 | |
194 | * | |
195 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
196 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
197 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
198 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
199 | * | |
200 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
201 | * get the result in decakilobits instead of kilobits. | |
202 | */ | |
203 | ||
a4fc5ed6 | 204 | static int |
cd9dde44 | 205 | intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock) |
a4fc5ed6 | 206 | { |
89c61432 JB |
207 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
208 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
209 | int bpp = 24; | |
885a5fb5 | 210 | |
89c61432 JB |
211 | if (intel_crtc) |
212 | bpp = intel_crtc->bpp; | |
213 | ||
cd9dde44 | 214 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
215 | } |
216 | ||
fe27d53e DA |
217 | static int |
218 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
219 | { | |
220 | return (max_link_clock * max_lanes * 8) / 10; | |
221 | } | |
222 | ||
a4fc5ed6 KP |
223 | static int |
224 | intel_dp_mode_valid(struct drm_connector *connector, | |
225 | struct drm_display_mode *mode) | |
226 | { | |
df0e9248 | 227 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
ea5b213a CW |
228 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
229 | int max_lanes = intel_dp_max_lane_count(intel_dp); | |
a4fc5ed6 | 230 | |
d15456de KP |
231 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
232 | if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay) | |
7de56f43 ZY |
233 | return MODE_PANEL; |
234 | ||
d15456de | 235 | if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay) |
7de56f43 ZY |
236 | return MODE_PANEL; |
237 | } | |
238 | ||
dc22ee6f AJ |
239 | if (intel_dp_link_required(intel_dp, mode->clock) |
240 | > intel_dp_max_data_rate(max_link_clock, max_lanes)) | |
a4fc5ed6 KP |
241 | return MODE_CLOCK_HIGH; |
242 | ||
243 | if (mode->clock < 10000) | |
244 | return MODE_CLOCK_LOW; | |
245 | ||
246 | return MODE_OK; | |
247 | } | |
248 | ||
249 | static uint32_t | |
250 | pack_aux(uint8_t *src, int src_bytes) | |
251 | { | |
252 | int i; | |
253 | uint32_t v = 0; | |
254 | ||
255 | if (src_bytes > 4) | |
256 | src_bytes = 4; | |
257 | for (i = 0; i < src_bytes; i++) | |
258 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
259 | return v; | |
260 | } | |
261 | ||
262 | static void | |
263 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
264 | { | |
265 | int i; | |
266 | if (dst_bytes > 4) | |
267 | dst_bytes = 4; | |
268 | for (i = 0; i < dst_bytes; i++) | |
269 | dst[i] = src >> ((3-i) * 8); | |
270 | } | |
271 | ||
fb0f8fbf KP |
272 | /* hrawclock is 1/4 the FSB frequency */ |
273 | static int | |
274 | intel_hrawclk(struct drm_device *dev) | |
275 | { | |
276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
277 | uint32_t clkcfg; | |
278 | ||
279 | clkcfg = I915_READ(CLKCFG); | |
280 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
281 | case CLKCFG_FSB_400: | |
282 | return 100; | |
283 | case CLKCFG_FSB_533: | |
284 | return 133; | |
285 | case CLKCFG_FSB_667: | |
286 | return 166; | |
287 | case CLKCFG_FSB_800: | |
288 | return 200; | |
289 | case CLKCFG_FSB_1067: | |
290 | return 266; | |
291 | case CLKCFG_FSB_1333: | |
292 | return 333; | |
293 | /* these two are just a guess; one of them might be right */ | |
294 | case CLKCFG_FSB_1600: | |
295 | case CLKCFG_FSB_1600_ALT: | |
296 | return 400; | |
297 | default: | |
298 | return 133; | |
299 | } | |
300 | } | |
301 | ||
ebf33b18 KP |
302 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
303 | { | |
304 | struct drm_device *dev = intel_dp->base.base.dev; | |
305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
306 | ||
307 | return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; | |
308 | } | |
309 | ||
310 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) | |
311 | { | |
312 | struct drm_device *dev = intel_dp->base.base.dev; | |
313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
314 | ||
315 | return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; | |
316 | } | |
317 | ||
9b984dae KP |
318 | static void |
319 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
320 | { | |
321 | struct drm_device *dev = intel_dp->base.base.dev; | |
322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ebf33b18 | 323 | |
9b984dae KP |
324 | if (!is_edp(intel_dp)) |
325 | return; | |
ebf33b18 | 326 | if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
327 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
328 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
ebf33b18 | 329 | I915_READ(PCH_PP_STATUS), |
9b984dae KP |
330 | I915_READ(PCH_PP_CONTROL)); |
331 | } | |
332 | } | |
333 | ||
a4fc5ed6 | 334 | static int |
ea5b213a | 335 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
336 | uint8_t *send, int send_bytes, |
337 | uint8_t *recv, int recv_size) | |
338 | { | |
ea5b213a | 339 | uint32_t output_reg = intel_dp->output_reg; |
4ef69c7a | 340 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 KP |
341 | struct drm_i915_private *dev_priv = dev->dev_private; |
342 | uint32_t ch_ctl = output_reg + 0x10; | |
343 | uint32_t ch_data = ch_ctl + 4; | |
344 | int i; | |
345 | int recv_bytes; | |
a4fc5ed6 | 346 | uint32_t status; |
fb0f8fbf | 347 | uint32_t aux_clock_divider; |
e3421a18 | 348 | int try, precharge; |
a4fc5ed6 | 349 | |
9b984dae | 350 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 | 351 | /* The clock divider is based off the hrawclk, |
fb0f8fbf KP |
352 | * and would like to run at 2MHz. So, take the |
353 | * hrawclk value and divide by 2 and use that | |
6176b8f9 JB |
354 | * |
355 | * Note that PCH attached eDP panels should use a 125MHz input | |
356 | * clock divider. | |
a4fc5ed6 | 357 | */ |
cfcb0fc9 | 358 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
e3421a18 ZW |
359 | if (IS_GEN6(dev)) |
360 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ | |
361 | else | |
362 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
363 | } else if (HAS_PCH_SPLIT(dev)) | |
f2b115e6 | 364 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
5eb08b69 ZW |
365 | else |
366 | aux_clock_divider = intel_hrawclk(dev) / 2; | |
367 | ||
e3421a18 ZW |
368 | if (IS_GEN6(dev)) |
369 | precharge = 3; | |
370 | else | |
371 | precharge = 5; | |
372 | ||
11bee43e JB |
373 | /* Try to wait for any previous AUX channel activity */ |
374 | for (try = 0; try < 3; try++) { | |
375 | status = I915_READ(ch_ctl); | |
376 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
377 | break; | |
378 | msleep(1); | |
379 | } | |
380 | ||
381 | if (try == 3) { | |
382 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
383 | I915_READ(ch_ctl)); | |
4f7f7b7e CW |
384 | return -EBUSY; |
385 | } | |
386 | ||
fb0f8fbf KP |
387 | /* Must try at least 3 times according to DP spec */ |
388 | for (try = 0; try < 5; try++) { | |
389 | /* Load the send data into the aux channel data registers */ | |
4f7f7b7e CW |
390 | for (i = 0; i < send_bytes; i += 4) |
391 | I915_WRITE(ch_data + i, | |
392 | pack_aux(send + i, send_bytes - i)); | |
0206e353 | 393 | |
fb0f8fbf | 394 | /* Send the command and wait for it to complete */ |
4f7f7b7e CW |
395 | I915_WRITE(ch_ctl, |
396 | DP_AUX_CH_CTL_SEND_BUSY | | |
397 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
398 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
399 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
400 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
401 | DP_AUX_CH_CTL_DONE | | |
402 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
403 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
fb0f8fbf | 404 | for (;;) { |
fb0f8fbf KP |
405 | status = I915_READ(ch_ctl); |
406 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
407 | break; | |
4f7f7b7e | 408 | udelay(100); |
fb0f8fbf | 409 | } |
0206e353 | 410 | |
fb0f8fbf | 411 | /* Clear done status and any errors */ |
4f7f7b7e CW |
412 | I915_WRITE(ch_ctl, |
413 | status | | |
414 | DP_AUX_CH_CTL_DONE | | |
415 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
416 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
417 | if (status & DP_AUX_CH_CTL_DONE) | |
a4fc5ed6 KP |
418 | break; |
419 | } | |
420 | ||
a4fc5ed6 | 421 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 422 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
a5b3da54 | 423 | return -EBUSY; |
a4fc5ed6 KP |
424 | } |
425 | ||
426 | /* Check for timeout or receive error. | |
427 | * Timeouts occur when the sink is not connected | |
428 | */ | |
a5b3da54 | 429 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 430 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
a5b3da54 KP |
431 | return -EIO; |
432 | } | |
1ae8c0a5 KP |
433 | |
434 | /* Timeouts occur when the device isn't connected, so they're | |
435 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 436 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 437 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
a5b3da54 | 438 | return -ETIMEDOUT; |
a4fc5ed6 KP |
439 | } |
440 | ||
441 | /* Unload any bytes sent back from the other side */ | |
442 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
443 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
444 | if (recv_bytes > recv_size) |
445 | recv_bytes = recv_size; | |
0206e353 | 446 | |
4f7f7b7e CW |
447 | for (i = 0; i < recv_bytes; i += 4) |
448 | unpack_aux(I915_READ(ch_data + i), | |
449 | recv + i, recv_bytes - i); | |
a4fc5ed6 KP |
450 | |
451 | return recv_bytes; | |
452 | } | |
453 | ||
454 | /* Write data to the aux channel in native mode */ | |
455 | static int | |
ea5b213a | 456 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
457 | uint16_t address, uint8_t *send, int send_bytes) |
458 | { | |
459 | int ret; | |
460 | uint8_t msg[20]; | |
461 | int msg_bytes; | |
462 | uint8_t ack; | |
463 | ||
9b984dae | 464 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
465 | if (send_bytes > 16) |
466 | return -1; | |
467 | msg[0] = AUX_NATIVE_WRITE << 4; | |
468 | msg[1] = address >> 8; | |
eebc863e | 469 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
470 | msg[3] = send_bytes - 1; |
471 | memcpy(&msg[4], send, send_bytes); | |
472 | msg_bytes = send_bytes + 4; | |
473 | for (;;) { | |
ea5b213a | 474 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
475 | if (ret < 0) |
476 | return ret; | |
477 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
478 | break; | |
479 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
480 | udelay(100); | |
481 | else | |
a5b3da54 | 482 | return -EIO; |
a4fc5ed6 KP |
483 | } |
484 | return send_bytes; | |
485 | } | |
486 | ||
487 | /* Write a single byte to the aux channel in native mode */ | |
488 | static int | |
ea5b213a | 489 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
490 | uint16_t address, uint8_t byte) |
491 | { | |
ea5b213a | 492 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
493 | } |
494 | ||
495 | /* read bytes from a native aux channel */ | |
496 | static int | |
ea5b213a | 497 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
498 | uint16_t address, uint8_t *recv, int recv_bytes) |
499 | { | |
500 | uint8_t msg[4]; | |
501 | int msg_bytes; | |
502 | uint8_t reply[20]; | |
503 | int reply_bytes; | |
504 | uint8_t ack; | |
505 | int ret; | |
506 | ||
9b984dae | 507 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
508 | msg[0] = AUX_NATIVE_READ << 4; |
509 | msg[1] = address >> 8; | |
510 | msg[2] = address & 0xff; | |
511 | msg[3] = recv_bytes - 1; | |
512 | ||
513 | msg_bytes = 4; | |
514 | reply_bytes = recv_bytes + 1; | |
515 | ||
516 | for (;;) { | |
ea5b213a | 517 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 518 | reply, reply_bytes); |
a5b3da54 KP |
519 | if (ret == 0) |
520 | return -EPROTO; | |
521 | if (ret < 0) | |
a4fc5ed6 KP |
522 | return ret; |
523 | ack = reply[0]; | |
524 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
525 | memcpy(recv, reply + 1, ret - 1); | |
526 | return ret - 1; | |
527 | } | |
528 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
529 | udelay(100); | |
530 | else | |
a5b3da54 | 531 | return -EIO; |
a4fc5ed6 KP |
532 | } |
533 | } | |
534 | ||
535 | static int | |
ab2c0672 DA |
536 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
537 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 538 | { |
ab2c0672 | 539 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
540 | struct intel_dp *intel_dp = container_of(adapter, |
541 | struct intel_dp, | |
542 | adapter); | |
ab2c0672 DA |
543 | uint16_t address = algo_data->address; |
544 | uint8_t msg[5]; | |
545 | uint8_t reply[2]; | |
8316f337 | 546 | unsigned retry; |
ab2c0672 DA |
547 | int msg_bytes; |
548 | int reply_bytes; | |
549 | int ret; | |
550 | ||
9b984dae | 551 | intel_dp_check_edp(intel_dp); |
ab2c0672 DA |
552 | /* Set up the command byte */ |
553 | if (mode & MODE_I2C_READ) | |
554 | msg[0] = AUX_I2C_READ << 4; | |
555 | else | |
556 | msg[0] = AUX_I2C_WRITE << 4; | |
557 | ||
558 | if (!(mode & MODE_I2C_STOP)) | |
559 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 560 | |
ab2c0672 DA |
561 | msg[1] = address >> 8; |
562 | msg[2] = address; | |
563 | ||
564 | switch (mode) { | |
565 | case MODE_I2C_WRITE: | |
566 | msg[3] = 0; | |
567 | msg[4] = write_byte; | |
568 | msg_bytes = 5; | |
569 | reply_bytes = 1; | |
570 | break; | |
571 | case MODE_I2C_READ: | |
572 | msg[3] = 0; | |
573 | msg_bytes = 4; | |
574 | reply_bytes = 2; | |
575 | break; | |
576 | default: | |
577 | msg_bytes = 3; | |
578 | reply_bytes = 1; | |
579 | break; | |
580 | } | |
581 | ||
8316f337 DF |
582 | for (retry = 0; retry < 5; retry++) { |
583 | ret = intel_dp_aux_ch(intel_dp, | |
584 | msg, msg_bytes, | |
585 | reply, reply_bytes); | |
ab2c0672 | 586 | if (ret < 0) { |
3ff99164 | 587 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
588 | return ret; |
589 | } | |
8316f337 DF |
590 | |
591 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { | |
592 | case AUX_NATIVE_REPLY_ACK: | |
593 | /* I2C-over-AUX Reply field is only valid | |
594 | * when paired with AUX ACK. | |
595 | */ | |
596 | break; | |
597 | case AUX_NATIVE_REPLY_NACK: | |
598 | DRM_DEBUG_KMS("aux_ch native nack\n"); | |
599 | return -EREMOTEIO; | |
600 | case AUX_NATIVE_REPLY_DEFER: | |
601 | udelay(100); | |
602 | continue; | |
603 | default: | |
604 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", | |
605 | reply[0]); | |
606 | return -EREMOTEIO; | |
607 | } | |
608 | ||
ab2c0672 DA |
609 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
610 | case AUX_I2C_REPLY_ACK: | |
611 | if (mode == MODE_I2C_READ) { | |
612 | *read_byte = reply[1]; | |
613 | } | |
614 | return reply_bytes - 1; | |
615 | case AUX_I2C_REPLY_NACK: | |
8316f337 | 616 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
ab2c0672 DA |
617 | return -EREMOTEIO; |
618 | case AUX_I2C_REPLY_DEFER: | |
8316f337 | 619 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
ab2c0672 DA |
620 | udelay(100); |
621 | break; | |
622 | default: | |
8316f337 | 623 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
ab2c0672 DA |
624 | return -EREMOTEIO; |
625 | } | |
626 | } | |
8316f337 DF |
627 | |
628 | DRM_ERROR("too many retries, giving up\n"); | |
629 | return -EREMOTEIO; | |
a4fc5ed6 KP |
630 | } |
631 | ||
0b5c541b | 632 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
bd943159 | 633 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
0b5c541b | 634 | |
a4fc5ed6 | 635 | static int |
ea5b213a | 636 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 637 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 638 | { |
0b5c541b KP |
639 | int ret; |
640 | ||
d54e9d28 | 641 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
642 | intel_dp->algo.running = false; |
643 | intel_dp->algo.address = 0; | |
644 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
645 | ||
0206e353 | 646 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
ea5b213a CW |
647 | intel_dp->adapter.owner = THIS_MODULE; |
648 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
0206e353 | 649 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
ea5b213a CW |
650 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
651 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
652 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
653 | ||
0b5c541b KP |
654 | ironlake_edp_panel_vdd_on(intel_dp); |
655 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); | |
bd943159 | 656 | ironlake_edp_panel_vdd_off(intel_dp, false); |
0b5c541b | 657 | return ret; |
a4fc5ed6 KP |
658 | } |
659 | ||
660 | static bool | |
661 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
662 | struct drm_display_mode *adjusted_mode) | |
663 | { | |
0d3a1bee | 664 | struct drm_device *dev = encoder->dev; |
ea5b213a | 665 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4fc5ed6 | 666 | int lane_count, clock; |
ea5b213a CW |
667 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
668 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; | |
a4fc5ed6 KP |
669 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
670 | ||
d15456de KP |
671 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
672 | intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode); | |
1d8e1c75 CW |
673 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, |
674 | mode, adjusted_mode); | |
0d3a1bee ZY |
675 | /* |
676 | * the mode->clock is used to calculate the Data&Link M/N | |
677 | * of the pipe. For the eDP the fixed clock should be used. | |
678 | */ | |
d15456de | 679 | mode->clock = intel_dp->panel_fixed_mode->clock; |
0d3a1bee ZY |
680 | } |
681 | ||
a4fc5ed6 KP |
682 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
683 | for (clock = 0; clock <= max_clock; clock++) { | |
fe27d53e | 684 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
a4fc5ed6 | 685 | |
cd9dde44 | 686 | if (intel_dp_link_required(intel_dp, mode->clock) |
885a5fb5 | 687 | <= link_avail) { |
ea5b213a CW |
688 | intel_dp->link_bw = bws[clock]; |
689 | intel_dp->lane_count = lane_count; | |
690 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
28c97730 ZY |
691 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
692 | "count %d clock %d\n", | |
ea5b213a | 693 | intel_dp->link_bw, intel_dp->lane_count, |
a4fc5ed6 KP |
694 | adjusted_mode->clock); |
695 | return true; | |
696 | } | |
697 | } | |
698 | } | |
fe27d53e | 699 | |
a4fc5ed6 KP |
700 | return false; |
701 | } | |
702 | ||
703 | struct intel_dp_m_n { | |
704 | uint32_t tu; | |
705 | uint32_t gmch_m; | |
706 | uint32_t gmch_n; | |
707 | uint32_t link_m; | |
708 | uint32_t link_n; | |
709 | }; | |
710 | ||
711 | static void | |
712 | intel_reduce_ratio(uint32_t *num, uint32_t *den) | |
713 | { | |
714 | while (*num > 0xffffff || *den > 0xffffff) { | |
715 | *num >>= 1; | |
716 | *den >>= 1; | |
717 | } | |
718 | } | |
719 | ||
720 | static void | |
36e83a18 | 721 | intel_dp_compute_m_n(int bpp, |
a4fc5ed6 KP |
722 | int nlanes, |
723 | int pixel_clock, | |
724 | int link_clock, | |
725 | struct intel_dp_m_n *m_n) | |
726 | { | |
727 | m_n->tu = 64; | |
36e83a18 | 728 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
a4fc5ed6 KP |
729 | m_n->gmch_n = link_clock * nlanes; |
730 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
731 | m_n->link_m = pixel_clock; | |
732 | m_n->link_n = link_clock; | |
733 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
734 | } | |
735 | ||
736 | void | |
737 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
738 | struct drm_display_mode *adjusted_mode) | |
739 | { | |
740 | struct drm_device *dev = crtc->dev; | |
741 | struct drm_mode_config *mode_config = &dev->mode_config; | |
55f78c43 | 742 | struct drm_encoder *encoder; |
a4fc5ed6 KP |
743 | struct drm_i915_private *dev_priv = dev->dev_private; |
744 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
858fa035 | 745 | int lane_count = 4; |
a4fc5ed6 | 746 | struct intel_dp_m_n m_n; |
9db4a9c7 | 747 | int pipe = intel_crtc->pipe; |
a4fc5ed6 KP |
748 | |
749 | /* | |
21d40d37 | 750 | * Find the lane count in the intel_encoder private |
a4fc5ed6 | 751 | */ |
55f78c43 | 752 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
ea5b213a | 753 | struct intel_dp *intel_dp; |
a4fc5ed6 | 754 | |
d8201ab6 | 755 | if (encoder->crtc != crtc) |
a4fc5ed6 KP |
756 | continue; |
757 | ||
ea5b213a CW |
758 | intel_dp = enc_to_intel_dp(encoder); |
759 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
760 | lane_count = intel_dp->lane_count; | |
51190667 JB |
761 | break; |
762 | } else if (is_edp(intel_dp)) { | |
763 | lane_count = dev_priv->edp.lanes; | |
a4fc5ed6 KP |
764 | break; |
765 | } | |
766 | } | |
767 | ||
768 | /* | |
769 | * Compute the GMCH and Link ratios. The '3' here is | |
770 | * the number of bytes_per_pixel post-LUT, which we always | |
771 | * set up for 8-bits of R/G/B, or 3 bytes total. | |
772 | */ | |
858fa035 | 773 | intel_dp_compute_m_n(intel_crtc->bpp, lane_count, |
a4fc5ed6 KP |
774 | mode->clock, adjusted_mode->clock, &m_n); |
775 | ||
c619eed4 | 776 | if (HAS_PCH_SPLIT(dev)) { |
9db4a9c7 JB |
777 | I915_WRITE(TRANSDATA_M1(pipe), |
778 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
779 | m_n.gmch_m); | |
780 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); | |
781 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); | |
782 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); | |
a4fc5ed6 | 783 | } else { |
9db4a9c7 JB |
784 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
785 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
786 | m_n.gmch_m); | |
787 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); | |
788 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); | |
789 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); | |
a4fc5ed6 KP |
790 | } |
791 | } | |
792 | ||
f01eca2e KP |
793 | static void ironlake_edp_pll_on(struct drm_encoder *encoder); |
794 | static void ironlake_edp_pll_off(struct drm_encoder *encoder); | |
795 | ||
a4fc5ed6 KP |
796 | static void |
797 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
798 | struct drm_display_mode *adjusted_mode) | |
799 | { | |
e3421a18 | 800 | struct drm_device *dev = encoder->dev; |
ea5b213a | 801 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4ef69c7a | 802 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
a4fc5ed6 KP |
803 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
804 | ||
f01eca2e KP |
805 | /* Turn on the eDP PLL if needed */ |
806 | if (is_edp(intel_dp)) { | |
807 | if (!is_pch_edp(intel_dp)) | |
808 | ironlake_edp_pll_on(encoder); | |
809 | else | |
810 | ironlake_edp_pll_off(encoder); | |
811 | } | |
812 | ||
e953fd7b CW |
813 | intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
814 | intel_dp->DP |= intel_dp->color_range; | |
9c9e7927 AJ |
815 | |
816 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
ea5b213a | 817 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
9c9e7927 | 818 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
ea5b213a | 819 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
a4fc5ed6 | 820 | |
cfcb0fc9 | 821 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
ea5b213a | 822 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3421a18 | 823 | else |
ea5b213a | 824 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
a4fc5ed6 | 825 | |
ea5b213a | 826 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 827 | case 1: |
ea5b213a | 828 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
829 | break; |
830 | case 2: | |
ea5b213a | 831 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
832 | break; |
833 | case 4: | |
ea5b213a | 834 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
835 | break; |
836 | } | |
e0dac65e WF |
837 | if (intel_dp->has_audio) { |
838 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", | |
839 | pipe_name(intel_crtc->pipe)); | |
ea5b213a | 840 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
e0dac65e WF |
841 | intel_write_eld(encoder, adjusted_mode); |
842 | } | |
a4fc5ed6 | 843 | |
ea5b213a CW |
844 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
845 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
846 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
a2cab1b2 | 847 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
a4fc5ed6 KP |
848 | |
849 | /* | |
9962c925 | 850 | * Check for DPCD version > 1.1 and enhanced framing support |
a4fc5ed6 | 851 | */ |
7183dc29 JB |
852 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
853 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { | |
ea5b213a CW |
854 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
855 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
a4fc5ed6 KP |
856 | } |
857 | ||
e3421a18 ZW |
858 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ |
859 | if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) | |
ea5b213a | 860 | intel_dp->DP |= DP_PIPEB_SELECT; |
32f9d658 | 861 | |
895692be | 862 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
32f9d658 | 863 | /* don't miss out required setting for eDP */ |
ea5b213a | 864 | intel_dp->DP |= DP_PLL_ENABLE; |
32f9d658 | 865 | if (adjusted_mode->clock < 200000) |
ea5b213a | 866 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
32f9d658 | 867 | else |
ea5b213a | 868 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
32f9d658 | 869 | } |
a4fc5ed6 KP |
870 | } |
871 | ||
bd943159 KP |
872 | static void ironlake_wait_panel_off(struct intel_dp *intel_dp) |
873 | { | |
874 | unsigned long off_time; | |
875 | unsigned long delay; | |
32ce697c | 876 | |
bd943159 | 877 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
32ce697c KP |
878 | |
879 | if (ironlake_edp_have_panel_power(intel_dp) || | |
880 | ironlake_edp_have_panel_vdd(intel_dp)) | |
881 | { | |
882 | DRM_DEBUG_KMS("Panel still on, no delay needed\n"); | |
883 | return; | |
884 | } | |
885 | ||
bd943159 KP |
886 | off_time = intel_dp->panel_off_jiffies + msecs_to_jiffies(intel_dp->panel_power_down_delay); |
887 | if (time_after(jiffies, off_time)) { | |
888 | DRM_DEBUG_KMS("Time already passed"); | |
889 | return; | |
890 | } | |
891 | delay = jiffies_to_msecs(off_time - jiffies); | |
892 | if (delay > intel_dp->panel_power_down_delay) | |
893 | delay = intel_dp->panel_power_down_delay; | |
894 | DRM_DEBUG_KMS("Waiting an additional %ld ms\n", delay); | |
895 | msleep(delay); | |
896 | } | |
897 | ||
5d613501 JB |
898 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
899 | { | |
900 | struct drm_device *dev = intel_dp->base.base.dev; | |
901 | struct drm_i915_private *dev_priv = dev->dev_private; | |
902 | u32 pp; | |
903 | ||
97af61f5 KP |
904 | if (!is_edp(intel_dp)) |
905 | return; | |
f01eca2e | 906 | DRM_DEBUG_KMS("Turn eDP VDD on\n"); |
5d613501 | 907 | |
bd943159 KP |
908 | WARN(intel_dp->want_panel_vdd, |
909 | "eDP VDD already requested on\n"); | |
910 | ||
911 | intel_dp->want_panel_vdd = true; | |
912 | if (ironlake_edp_have_panel_vdd(intel_dp)) { | |
913 | DRM_DEBUG_KMS("eDP VDD already on\n"); | |
914 | return; | |
915 | } | |
916 | ||
917 | ironlake_wait_panel_off(intel_dp); | |
5d613501 | 918 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
919 | pp &= ~PANEL_UNLOCK_MASK; |
920 | pp |= PANEL_UNLOCK_REGS; | |
5d613501 JB |
921 | pp |= EDP_FORCE_VDD; |
922 | I915_WRITE(PCH_PP_CONTROL, pp); | |
923 | POSTING_READ(PCH_PP_CONTROL); | |
f01eca2e KP |
924 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
925 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); | |
ebf33b18 KP |
926 | |
927 | /* | |
928 | * If the panel wasn't on, delay before accessing aux channel | |
929 | */ | |
930 | if (!ironlake_edp_have_panel_power(intel_dp)) { | |
bd943159 | 931 | DRM_DEBUG_KMS("eDP was not running\n"); |
f01eca2e | 932 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 933 | } |
5d613501 JB |
934 | } |
935 | ||
bd943159 | 936 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 JB |
937 | { |
938 | struct drm_device *dev = intel_dp->base.base.dev; | |
939 | struct drm_i915_private *dev_priv = dev->dev_private; | |
940 | u32 pp; | |
941 | ||
bd943159 KP |
942 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
943 | pp = I915_READ(PCH_PP_CONTROL); | |
944 | pp &= ~PANEL_UNLOCK_MASK; | |
945 | pp |= PANEL_UNLOCK_REGS; | |
946 | pp &= ~EDP_FORCE_VDD; | |
947 | I915_WRITE(PCH_PP_CONTROL, pp); | |
948 | POSTING_READ(PCH_PP_CONTROL); | |
949 | ||
950 | /* Make sure sequencer is idle before allowing subsequent activity */ | |
951 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", | |
952 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); | |
953 | intel_dp->panel_off_jiffies = jiffies; | |
954 | } | |
955 | } | |
5d613501 | 956 | |
bd943159 KP |
957 | static void ironlake_panel_vdd_work(struct work_struct *__work) |
958 | { | |
959 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
960 | struct intel_dp, panel_vdd_work); | |
961 | struct drm_device *dev = intel_dp->base.base.dev; | |
962 | ||
963 | mutex_lock(&dev->struct_mutex); | |
964 | ironlake_panel_vdd_off_sync(intel_dp); | |
965 | mutex_unlock(&dev->struct_mutex); | |
966 | } | |
967 | ||
968 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) | |
969 | { | |
97af61f5 KP |
970 | if (!is_edp(intel_dp)) |
971 | return; | |
5d613501 | 972 | |
bd943159 KP |
973 | DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); |
974 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); | |
975 | ||
976 | intel_dp->want_panel_vdd = false; | |
977 | ||
978 | if (sync) { | |
979 | ironlake_panel_vdd_off_sync(intel_dp); | |
980 | } else { | |
981 | /* | |
982 | * Queue the timer to fire a long | |
983 | * time from now (relative to the power down delay) | |
984 | * to keep the panel power up across a sequence of operations | |
985 | */ | |
986 | schedule_delayed_work(&intel_dp->panel_vdd_work, | |
987 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
988 | } | |
5d613501 JB |
989 | } |
990 | ||
7eaf5547 | 991 | /* Returns true if the panel was already on when called */ |
86a3073e | 992 | static void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 993 | { |
01cb9ea6 | 994 | struct drm_device *dev = intel_dp->base.base.dev; |
9934c132 | 995 | struct drm_i915_private *dev_priv = dev->dev_private; |
01cb9ea6 | 996 | u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE; |
9934c132 | 997 | |
97af61f5 | 998 | if (!is_edp(intel_dp)) |
bd943159 | 999 | return; |
ebf33b18 | 1000 | if (ironlake_edp_have_panel_power(intel_dp)) |
7d639f35 | 1001 | return; |
9934c132 | 1002 | |
bd943159 | 1003 | ironlake_wait_panel_off(intel_dp); |
9934c132 | 1004 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
1005 | pp &= ~PANEL_UNLOCK_MASK; |
1006 | pp |= PANEL_UNLOCK_REGS; | |
37c6c9b0 | 1007 | |
05ce1a49 KP |
1008 | if (IS_GEN5(dev)) { |
1009 | /* ILK workaround: disable reset around power sequence */ | |
1010 | pp &= ~PANEL_POWER_RESET; | |
1011 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1012 | POSTING_READ(PCH_PP_CONTROL); | |
1013 | } | |
37c6c9b0 | 1014 | |
1c0ae80a | 1015 | pp |= POWER_TARGET_ON; |
9934c132 | 1016 | I915_WRITE(PCH_PP_CONTROL, pp); |
01cb9ea6 | 1017 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 | 1018 | |
01cb9ea6 JB |
1019 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, |
1020 | 5000)) | |
913d8d11 CW |
1021 | DRM_ERROR("panel on wait timed out: 0x%08x\n", |
1022 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 1023 | |
05ce1a49 KP |
1024 | if (IS_GEN5(dev)) { |
1025 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
1026 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1027 | POSTING_READ(PCH_PP_CONTROL); | |
1028 | } | |
9934c132 JB |
1029 | } |
1030 | ||
f01eca2e | 1031 | static void ironlake_edp_panel_off(struct drm_encoder *encoder) |
9934c132 | 1032 | { |
f01eca2e KP |
1033 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1034 | struct drm_device *dev = encoder->dev; | |
9934c132 | 1035 | struct drm_i915_private *dev_priv = dev->dev_private; |
01cb9ea6 JB |
1036 | u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | |
1037 | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK; | |
9934c132 | 1038 | |
97af61f5 KP |
1039 | if (!is_edp(intel_dp)) |
1040 | return; | |
9934c132 | 1041 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
1042 | pp &= ~PANEL_UNLOCK_MASK; |
1043 | pp |= PANEL_UNLOCK_REGS; | |
37c6c9b0 | 1044 | |
05ce1a49 KP |
1045 | if (IS_GEN5(dev)) { |
1046 | /* ILK workaround: disable reset around power sequence */ | |
1047 | pp &= ~PANEL_POWER_RESET; | |
1048 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1049 | POSTING_READ(PCH_PP_CONTROL); | |
1050 | } | |
37c6c9b0 | 1051 | |
05ce1a49 | 1052 | intel_dp->panel_off_jiffies = jiffies; |
37c6c9b0 | 1053 | |
05ce1a49 KP |
1054 | if (IS_GEN5(dev)) { |
1055 | pp &= ~POWER_TARGET_ON; | |
1056 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1057 | POSTING_READ(PCH_PP_CONTROL); | |
1058 | pp &= ~POWER_TARGET_ON; | |
1059 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1060 | POSTING_READ(PCH_PP_CONTROL); | |
1061 | msleep(intel_dp->panel_power_cycle_delay); | |
9934c132 | 1062 | |
05ce1a49 KP |
1063 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000)) |
1064 | DRM_ERROR("panel off wait timed out: 0x%08x\n", | |
1065 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 1066 | |
05ce1a49 KP |
1067 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
1068 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1069 | POSTING_READ(PCH_PP_CONTROL); | |
1070 | } | |
9934c132 JB |
1071 | } |
1072 | ||
86a3073e | 1073 | static void ironlake_edp_backlight_on(struct intel_dp *intel_dp) |
32f9d658 | 1074 | { |
f01eca2e | 1075 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1076 | struct drm_i915_private *dev_priv = dev->dev_private; |
1077 | u32 pp; | |
1078 | ||
f01eca2e KP |
1079 | if (!is_edp(intel_dp)) |
1080 | return; | |
1081 | ||
28c97730 | 1082 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
1083 | /* |
1084 | * If we enable the backlight right away following a panel power | |
1085 | * on, we may see slight flicker as the panel syncs with the eDP | |
1086 | * link. So delay a bit to make sure the image is solid before | |
1087 | * allowing it to appear. | |
1088 | */ | |
f01eca2e | 1089 | msleep(intel_dp->backlight_on_delay); |
32f9d658 | 1090 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
1091 | pp &= ~PANEL_UNLOCK_MASK; |
1092 | pp |= PANEL_UNLOCK_REGS; | |
32f9d658 ZW |
1093 | pp |= EDP_BLC_ENABLE; |
1094 | I915_WRITE(PCH_PP_CONTROL, pp); | |
f01eca2e | 1095 | POSTING_READ(PCH_PP_CONTROL); |
32f9d658 ZW |
1096 | } |
1097 | ||
86a3073e | 1098 | static void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
32f9d658 | 1099 | { |
f01eca2e | 1100 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1101 | struct drm_i915_private *dev_priv = dev->dev_private; |
1102 | u32 pp; | |
1103 | ||
f01eca2e KP |
1104 | if (!is_edp(intel_dp)) |
1105 | return; | |
1106 | ||
28c97730 | 1107 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1108 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
1109 | pp &= ~PANEL_UNLOCK_MASK; |
1110 | pp |= PANEL_UNLOCK_REGS; | |
32f9d658 ZW |
1111 | pp &= ~EDP_BLC_ENABLE; |
1112 | I915_WRITE(PCH_PP_CONTROL, pp); | |
f01eca2e KP |
1113 | POSTING_READ(PCH_PP_CONTROL); |
1114 | msleep(intel_dp->backlight_off_delay); | |
32f9d658 | 1115 | } |
a4fc5ed6 | 1116 | |
d240f20f JB |
1117 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
1118 | { | |
1119 | struct drm_device *dev = encoder->dev; | |
1120 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1121 | u32 dpa_ctl; | |
1122 | ||
1123 | DRM_DEBUG_KMS("\n"); | |
1124 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 1125 | dpa_ctl |= DP_PLL_ENABLE; |
d240f20f | 1126 | I915_WRITE(DP_A, dpa_ctl); |
298b0b39 JB |
1127 | POSTING_READ(DP_A); |
1128 | udelay(200); | |
d240f20f JB |
1129 | } |
1130 | ||
1131 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) | |
1132 | { | |
1133 | struct drm_device *dev = encoder->dev; | |
1134 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1135 | u32 dpa_ctl; | |
1136 | ||
1137 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 1138 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 1139 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 1140 | POSTING_READ(DP_A); |
d240f20f JB |
1141 | udelay(200); |
1142 | } | |
1143 | ||
c7ad3810 JB |
1144 | /* If the sink supports it, try to set the power state appropriately */ |
1145 | static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) | |
1146 | { | |
1147 | int ret, i; | |
1148 | ||
1149 | /* Should have a valid DPCD by this point */ | |
1150 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
1151 | return; | |
1152 | ||
1153 | if (mode != DRM_MODE_DPMS_ON) { | |
1154 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, | |
1155 | DP_SET_POWER_D3); | |
1156 | if (ret != 1) | |
1157 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
1158 | } else { | |
1159 | /* | |
1160 | * When turning on, we need to retry for 1ms to give the sink | |
1161 | * time to wake up. | |
1162 | */ | |
1163 | for (i = 0; i < 3; i++) { | |
1164 | ret = intel_dp_aux_native_write_1(intel_dp, | |
1165 | DP_SET_POWER, | |
1166 | DP_SET_POWER_D0); | |
1167 | if (ret == 1) | |
1168 | break; | |
1169 | msleep(1); | |
1170 | } | |
1171 | } | |
1172 | } | |
1173 | ||
d240f20f JB |
1174 | static void intel_dp_prepare(struct drm_encoder *encoder) |
1175 | { | |
1176 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
d240f20f | 1177 | |
c7ad3810 | 1178 | /* Wake up the sink first */ |
f58ff854 | 1179 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1180 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
bd943159 | 1181 | ironlake_edp_panel_vdd_off(intel_dp, false); |
c7ad3810 | 1182 | |
f01eca2e KP |
1183 | /* Make sure the panel is off before trying to |
1184 | * change the mode | |
1185 | */ | |
1186 | ironlake_edp_backlight_off(intel_dp); | |
736085bc | 1187 | intel_dp_link_down(intel_dp); |
f01eca2e | 1188 | ironlake_edp_panel_off(encoder); |
d240f20f JB |
1189 | } |
1190 | ||
1191 | static void intel_dp_commit(struct drm_encoder *encoder) | |
1192 | { | |
1193 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
d4270e57 JB |
1194 | struct drm_device *dev = encoder->dev; |
1195 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); | |
5d613501 | 1196 | |
97af61f5 | 1197 | ironlake_edp_panel_vdd_on(intel_dp); |
f01eca2e | 1198 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 1199 | intel_dp_start_link_train(intel_dp); |
97af61f5 | 1200 | ironlake_edp_panel_on(intel_dp); |
bd943159 | 1201 | ironlake_edp_panel_vdd_off(intel_dp, true); |
33a34e4e JB |
1202 | |
1203 | intel_dp_complete_link_train(intel_dp); | |
f01eca2e | 1204 | ironlake_edp_backlight_on(intel_dp); |
d2b996ac KP |
1205 | |
1206 | intel_dp->dpms_mode = DRM_MODE_DPMS_ON; | |
d4270e57 JB |
1207 | |
1208 | if (HAS_PCH_CPT(dev)) | |
1209 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
d240f20f JB |
1210 | } |
1211 | ||
a4fc5ed6 KP |
1212 | static void |
1213 | intel_dp_dpms(struct drm_encoder *encoder, int mode) | |
1214 | { | |
ea5b213a | 1215 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
55f78c43 | 1216 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 | 1217 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1218 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
a4fc5ed6 KP |
1219 | |
1220 | if (mode != DRM_MODE_DPMS_ON) { | |
245e2708 | 1221 | ironlake_edp_panel_vdd_on(intel_dp); |
01cb9ea6 | 1222 | if (is_edp(intel_dp)) |
f01eca2e | 1223 | ironlake_edp_backlight_off(intel_dp); |
c7ad3810 | 1224 | intel_dp_sink_dpms(intel_dp, mode); |
736085bc | 1225 | intel_dp_link_down(intel_dp); |
f01eca2e | 1226 | ironlake_edp_panel_off(encoder); |
01cb9ea6 | 1227 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) |
d240f20f | 1228 | ironlake_edp_pll_off(encoder); |
bd943159 | 1229 | ironlake_edp_panel_vdd_off(intel_dp, false); |
a4fc5ed6 | 1230 | } else { |
97af61f5 | 1231 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1232 | intel_dp_sink_dpms(intel_dp, mode); |
32f9d658 | 1233 | if (!(dp_reg & DP_PORT_EN)) { |
01cb9ea6 | 1234 | intel_dp_start_link_train(intel_dp); |
97af61f5 | 1235 | ironlake_edp_panel_on(intel_dp); |
bd943159 | 1236 | ironlake_edp_panel_vdd_off(intel_dp, true); |
33a34e4e | 1237 | intel_dp_complete_link_train(intel_dp); |
f01eca2e | 1238 | ironlake_edp_backlight_on(intel_dp); |
bee7eb2d | 1239 | } else |
bd943159 KP |
1240 | ironlake_edp_panel_vdd_off(intel_dp, false); |
1241 | ironlake_edp_backlight_on(intel_dp); | |
a4fc5ed6 | 1242 | } |
d2b996ac | 1243 | intel_dp->dpms_mode = mode; |
a4fc5ed6 KP |
1244 | } |
1245 | ||
1246 | /* | |
df0c237d JB |
1247 | * Native read with retry for link status and receiver capability reads for |
1248 | * cases where the sink may still be asleep. | |
a4fc5ed6 KP |
1249 | */ |
1250 | static bool | |
df0c237d JB |
1251 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
1252 | uint8_t *recv, int recv_bytes) | |
a4fc5ed6 | 1253 | { |
61da5fab JB |
1254 | int ret, i; |
1255 | ||
df0c237d JB |
1256 | /* |
1257 | * Sinks are *supposed* to come up within 1ms from an off state, | |
1258 | * but we're also supposed to retry 3 times per the spec. | |
1259 | */ | |
61da5fab | 1260 | for (i = 0; i < 3; i++) { |
df0c237d JB |
1261 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
1262 | recv_bytes); | |
1263 | if (ret == recv_bytes) | |
61da5fab JB |
1264 | return true; |
1265 | msleep(1); | |
1266 | } | |
a4fc5ed6 | 1267 | |
61da5fab | 1268 | return false; |
a4fc5ed6 KP |
1269 | } |
1270 | ||
1271 | /* | |
1272 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
1273 | * link status information | |
1274 | */ | |
1275 | static bool | |
33a34e4e | 1276 | intel_dp_get_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1277 | { |
df0c237d JB |
1278 | return intel_dp_aux_native_read_retry(intel_dp, |
1279 | DP_LANE0_1_STATUS, | |
1280 | intel_dp->link_status, | |
1281 | DP_LINK_STATUS_SIZE); | |
a4fc5ed6 KP |
1282 | } |
1283 | ||
1284 | static uint8_t | |
1285 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1286 | int r) | |
1287 | { | |
1288 | return link_status[r - DP_LANE0_1_STATUS]; | |
1289 | } | |
1290 | ||
a4fc5ed6 KP |
1291 | static uint8_t |
1292 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1293 | int lane) | |
1294 | { | |
1295 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
1296 | int s = ((lane & 1) ? | |
1297 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
1298 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
1299 | uint8_t l = intel_dp_link_status(link_status, i); | |
1300 | ||
1301 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
1302 | } | |
1303 | ||
1304 | static uint8_t | |
1305 | intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1306 | int lane) | |
1307 | { | |
1308 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
1309 | int s = ((lane & 1) ? | |
1310 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
1311 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
1312 | uint8_t l = intel_dp_link_status(link_status, i); | |
1313 | ||
1314 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
1315 | } | |
1316 | ||
1317 | ||
1318 | #if 0 | |
1319 | static char *voltage_names[] = { | |
1320 | "0.4V", "0.6V", "0.8V", "1.2V" | |
1321 | }; | |
1322 | static char *pre_emph_names[] = { | |
1323 | "0dB", "3.5dB", "6dB", "9.5dB" | |
1324 | }; | |
1325 | static char *link_train_names[] = { | |
1326 | "pattern 1", "pattern 2", "idle", "off" | |
1327 | }; | |
1328 | #endif | |
1329 | ||
1330 | /* | |
1331 | * These are source-specific values; current Intel hardware supports | |
1332 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1333 | */ | |
1334 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 | |
1335 | ||
1336 | static uint8_t | |
1337 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) | |
1338 | { | |
1339 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1340 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1341 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1342 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1343 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1344 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1345 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1346 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1347 | default: | |
1348 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1349 | } | |
1350 | } | |
1351 | ||
1352 | static void | |
33a34e4e | 1353 | intel_get_adjust_train(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1354 | { |
1355 | uint8_t v = 0; | |
1356 | uint8_t p = 0; | |
1357 | int lane; | |
1358 | ||
33a34e4e JB |
1359 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1360 | uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane); | |
1361 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1362 | |
1363 | if (this_v > v) | |
1364 | v = this_v; | |
1365 | if (this_p > p) | |
1366 | p = this_p; | |
1367 | } | |
1368 | ||
1369 | if (v >= I830_DP_VOLTAGE_MAX) | |
1370 | v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; | |
1371 | ||
1372 | if (p >= intel_dp_pre_emphasis_max(v)) | |
1373 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
1374 | ||
1375 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 1376 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
1377 | } |
1378 | ||
1379 | static uint32_t | |
3cf2efb1 | 1380 | intel_dp_signal_levels(uint8_t train_set, int lane_count) |
a4fc5ed6 | 1381 | { |
3cf2efb1 | 1382 | uint32_t signal_levels = 0; |
a4fc5ed6 | 1383 | |
3cf2efb1 | 1384 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
1385 | case DP_TRAIN_VOLTAGE_SWING_400: |
1386 | default: | |
1387 | signal_levels |= DP_VOLTAGE_0_4; | |
1388 | break; | |
1389 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1390 | signal_levels |= DP_VOLTAGE_0_6; | |
1391 | break; | |
1392 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1393 | signal_levels |= DP_VOLTAGE_0_8; | |
1394 | break; | |
1395 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1396 | signal_levels |= DP_VOLTAGE_1_2; | |
1397 | break; | |
1398 | } | |
3cf2efb1 | 1399 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
1400 | case DP_TRAIN_PRE_EMPHASIS_0: |
1401 | default: | |
1402 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1403 | break; | |
1404 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1405 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1406 | break; | |
1407 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1408 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1409 | break; | |
1410 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1411 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1412 | break; | |
1413 | } | |
1414 | return signal_levels; | |
1415 | } | |
1416 | ||
e3421a18 ZW |
1417 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1418 | static uint32_t | |
1419 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1420 | { | |
3c5a62b5 YL |
1421 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1422 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1423 | switch (signal_levels) { | |
e3421a18 | 1424 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1425 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
1426 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
1427 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1428 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 1429 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
1430 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
1431 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 1432 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
1433 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
1434 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 1435 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1436 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
1437 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 1438 | default: |
3c5a62b5 YL |
1439 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
1440 | "0x%x\n", signal_levels); | |
1441 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
1442 | } |
1443 | } | |
1444 | ||
a4fc5ed6 KP |
1445 | static uint8_t |
1446 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1447 | int lane) | |
1448 | { | |
1449 | int i = DP_LANE0_1_STATUS + (lane >> 1); | |
1450 | int s = (lane & 1) * 4; | |
1451 | uint8_t l = intel_dp_link_status(link_status, i); | |
1452 | ||
1453 | return (l >> s) & 0xf; | |
1454 | } | |
1455 | ||
1456 | /* Check for clock recovery is done on all channels */ | |
1457 | static bool | |
1458 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1459 | { | |
1460 | int lane; | |
1461 | uint8_t lane_status; | |
1462 | ||
1463 | for (lane = 0; lane < lane_count; lane++) { | |
1464 | lane_status = intel_get_lane_status(link_status, lane); | |
1465 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
1466 | return false; | |
1467 | } | |
1468 | return true; | |
1469 | } | |
1470 | ||
1471 | /* Check to see if channel eq is done on all channels */ | |
1472 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ | |
1473 | DP_LANE_CHANNEL_EQ_DONE|\ | |
1474 | DP_LANE_SYMBOL_LOCKED) | |
1475 | static bool | |
33a34e4e | 1476 | intel_channel_eq_ok(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1477 | { |
1478 | uint8_t lane_align; | |
1479 | uint8_t lane_status; | |
1480 | int lane; | |
1481 | ||
33a34e4e | 1482 | lane_align = intel_dp_link_status(intel_dp->link_status, |
a4fc5ed6 KP |
1483 | DP_LANE_ALIGN_STATUS_UPDATED); |
1484 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
1485 | return false; | |
33a34e4e JB |
1486 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1487 | lane_status = intel_get_lane_status(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1488 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
1489 | return false; | |
1490 | } | |
1491 | return true; | |
1492 | } | |
1493 | ||
1494 | static bool | |
ea5b213a | 1495 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 | 1496 | uint32_t dp_reg_value, |
58e10eb9 | 1497 | uint8_t dp_train_pat) |
a4fc5ed6 | 1498 | { |
4ef69c7a | 1499 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1500 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1501 | int ret; |
1502 | ||
ea5b213a CW |
1503 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1504 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1505 | |
ea5b213a | 1506 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1507 | DP_TRAINING_PATTERN_SET, |
1508 | dp_train_pat); | |
1509 | ||
ea5b213a | 1510 | ret = intel_dp_aux_native_write(intel_dp, |
58e10eb9 CW |
1511 | DP_TRAINING_LANE0_SET, |
1512 | intel_dp->train_set, 4); | |
a4fc5ed6 KP |
1513 | if (ret != 4) |
1514 | return false; | |
1515 | ||
1516 | return true; | |
1517 | } | |
1518 | ||
33a34e4e | 1519 | /* Enable corresponding port and start training pattern 1 */ |
a4fc5ed6 | 1520 | static void |
33a34e4e | 1521 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1522 | { |
4ef69c7a | 1523 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1524 | struct drm_i915_private *dev_priv = dev->dev_private; |
58e10eb9 | 1525 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); |
a4fc5ed6 KP |
1526 | int i; |
1527 | uint8_t voltage; | |
1528 | bool clock_recovery = false; | |
a4fc5ed6 | 1529 | int tries; |
e3421a18 | 1530 | u32 reg; |
ea5b213a | 1531 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1532 | |
e8519464 AJ |
1533 | /* |
1534 | * On CPT we have to enable the port in training pattern 1, which | |
1535 | * will happen below in intel_dp_set_link_train. Otherwise, enable | |
1536 | * the port and wait for it to become active. | |
1537 | */ | |
1538 | if (!HAS_PCH_CPT(dev)) { | |
1539 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
1540 | POSTING_READ(intel_dp->output_reg); | |
1541 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1542 | } | |
a4fc5ed6 | 1543 | |
3cf2efb1 CW |
1544 | /* Write the link configuration data */ |
1545 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, | |
1546 | intel_dp->link_configuration, | |
1547 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
1548 | |
1549 | DP |= DP_PORT_EN; | |
cfcb0fc9 | 1550 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1551 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1552 | else | |
1553 | DP &= ~DP_LINK_TRAIN_MASK; | |
33a34e4e | 1554 | memset(intel_dp->train_set, 0, 4); |
a4fc5ed6 KP |
1555 | voltage = 0xff; |
1556 | tries = 0; | |
1557 | clock_recovery = false; | |
1558 | for (;;) { | |
33a34e4e | 1559 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 | 1560 | uint32_t signal_levels; |
cfcb0fc9 | 1561 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
33a34e4e | 1562 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1563 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1564 | } else { | |
3cf2efb1 | 1565 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1566 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1567 | } | |
a4fc5ed6 | 1568 | |
cfcb0fc9 | 1569 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1570 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
1571 | else | |
1572 | reg = DP | DP_LINK_TRAIN_PAT_1; | |
1573 | ||
ea5b213a | 1574 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1575 | DP_TRAINING_PATTERN_1 | |
1576 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 | 1577 | break; |
a4fc5ed6 KP |
1578 | /* Set training pattern 1 */ |
1579 | ||
3cf2efb1 CW |
1580 | udelay(100); |
1581 | if (!intel_dp_get_link_status(intel_dp)) | |
a4fc5ed6 | 1582 | break; |
a4fc5ed6 | 1583 | |
3cf2efb1 CW |
1584 | if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { |
1585 | clock_recovery = true; | |
1586 | break; | |
1587 | } | |
1588 | ||
1589 | /* Check to see if we've tried the max voltage */ | |
1590 | for (i = 0; i < intel_dp->lane_count; i++) | |
1591 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 1592 | break; |
3cf2efb1 CW |
1593 | if (i == intel_dp->lane_count) |
1594 | break; | |
a4fc5ed6 | 1595 | |
3cf2efb1 CW |
1596 | /* Check to see if we've tried the same voltage 5 times */ |
1597 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { | |
1598 | ++tries; | |
1599 | if (tries == 5) | |
a4fc5ed6 | 1600 | break; |
3cf2efb1 CW |
1601 | } else |
1602 | tries = 0; | |
1603 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 1604 | |
3cf2efb1 CW |
1605 | /* Compute new intel_dp->train_set as requested by target */ |
1606 | intel_get_adjust_train(intel_dp); | |
a4fc5ed6 KP |
1607 | } |
1608 | ||
33a34e4e JB |
1609 | intel_dp->DP = DP; |
1610 | } | |
1611 | ||
1612 | static void | |
1613 | intel_dp_complete_link_train(struct intel_dp *intel_dp) | |
1614 | { | |
4ef69c7a | 1615 | struct drm_device *dev = intel_dp->base.base.dev; |
33a34e4e JB |
1616 | struct drm_i915_private *dev_priv = dev->dev_private; |
1617 | bool channel_eq = false; | |
37f80975 | 1618 | int tries, cr_tries; |
33a34e4e JB |
1619 | u32 reg; |
1620 | uint32_t DP = intel_dp->DP; | |
1621 | ||
a4fc5ed6 KP |
1622 | /* channel equalization */ |
1623 | tries = 0; | |
37f80975 | 1624 | cr_tries = 0; |
a4fc5ed6 KP |
1625 | channel_eq = false; |
1626 | for (;;) { | |
33a34e4e | 1627 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 ZW |
1628 | uint32_t signal_levels; |
1629 | ||
37f80975 JB |
1630 | if (cr_tries > 5) { |
1631 | DRM_ERROR("failed to train DP, aborting\n"); | |
1632 | intel_dp_link_down(intel_dp); | |
1633 | break; | |
1634 | } | |
1635 | ||
cfcb0fc9 | 1636 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
33a34e4e | 1637 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1638 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1639 | } else { | |
3cf2efb1 | 1640 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1641 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1642 | } | |
1643 | ||
cfcb0fc9 | 1644 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1645 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
1646 | else | |
1647 | reg = DP | DP_LINK_TRAIN_PAT_2; | |
a4fc5ed6 KP |
1648 | |
1649 | /* channel eq pattern */ | |
ea5b213a | 1650 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1651 | DP_TRAINING_PATTERN_2 | |
1652 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 KP |
1653 | break; |
1654 | ||
3cf2efb1 CW |
1655 | udelay(400); |
1656 | if (!intel_dp_get_link_status(intel_dp)) | |
a4fc5ed6 | 1657 | break; |
a4fc5ed6 | 1658 | |
37f80975 JB |
1659 | /* Make sure clock is still ok */ |
1660 | if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { | |
1661 | intel_dp_start_link_train(intel_dp); | |
1662 | cr_tries++; | |
1663 | continue; | |
1664 | } | |
1665 | ||
3cf2efb1 CW |
1666 | if (intel_channel_eq_ok(intel_dp)) { |
1667 | channel_eq = true; | |
1668 | break; | |
1669 | } | |
a4fc5ed6 | 1670 | |
37f80975 JB |
1671 | /* Try 5 times, then try clock recovery if that fails */ |
1672 | if (tries > 5) { | |
1673 | intel_dp_link_down(intel_dp); | |
1674 | intel_dp_start_link_train(intel_dp); | |
1675 | tries = 0; | |
1676 | cr_tries++; | |
1677 | continue; | |
1678 | } | |
a4fc5ed6 | 1679 | |
3cf2efb1 CW |
1680 | /* Compute new intel_dp->train_set as requested by target */ |
1681 | intel_get_adjust_train(intel_dp); | |
1682 | ++tries; | |
869184a6 | 1683 | } |
3cf2efb1 | 1684 | |
cfcb0fc9 | 1685 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1686 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
1687 | else | |
1688 | reg = DP | DP_LINK_TRAIN_OFF; | |
1689 | ||
ea5b213a CW |
1690 | I915_WRITE(intel_dp->output_reg, reg); |
1691 | POSTING_READ(intel_dp->output_reg); | |
1692 | intel_dp_aux_native_write_1(intel_dp, | |
a4fc5ed6 KP |
1693 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
1694 | } | |
1695 | ||
1696 | static void | |
ea5b213a | 1697 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 1698 | { |
4ef69c7a | 1699 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1700 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1701 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1702 | |
1b39d6f3 CW |
1703 | if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) |
1704 | return; | |
1705 | ||
28c97730 | 1706 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1707 | |
cfcb0fc9 | 1708 | if (is_edp(intel_dp)) { |
32f9d658 | 1709 | DP &= ~DP_PLL_ENABLE; |
ea5b213a CW |
1710 | I915_WRITE(intel_dp->output_reg, DP); |
1711 | POSTING_READ(intel_dp->output_reg); | |
32f9d658 ZW |
1712 | udelay(100); |
1713 | } | |
1714 | ||
cfcb0fc9 | 1715 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) { |
e3421a18 | 1716 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 1717 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
1718 | } else { |
1719 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 1720 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 1721 | } |
fe255d00 | 1722 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 1723 | |
fe255d00 | 1724 | msleep(17); |
5eb08b69 | 1725 | |
cfcb0fc9 | 1726 | if (is_edp(intel_dp)) |
32f9d658 | 1727 | DP |= DP_LINK_TRAIN_OFF; |
5bddd17f | 1728 | |
1b39d6f3 CW |
1729 | if (!HAS_PCH_CPT(dev) && |
1730 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { | |
31acbcc4 CW |
1731 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
1732 | ||
5bddd17f EA |
1733 | /* Hardware workaround: leaving our transcoder select |
1734 | * set to transcoder B while it's off will prevent the | |
1735 | * corresponding HDMI output on transcoder A. | |
1736 | * | |
1737 | * Combine this with another hardware workaround: | |
1738 | * transcoder select bit can only be cleared while the | |
1739 | * port is enabled. | |
1740 | */ | |
1741 | DP &= ~DP_PIPEB_SELECT; | |
1742 | I915_WRITE(intel_dp->output_reg, DP); | |
1743 | ||
1744 | /* Changes to enable or select take place the vblank | |
1745 | * after being written. | |
1746 | */ | |
31acbcc4 CW |
1747 | if (crtc == NULL) { |
1748 | /* We can arrive here never having been attached | |
1749 | * to a CRTC, for instance, due to inheriting | |
1750 | * random state from the BIOS. | |
1751 | * | |
1752 | * If the pipe is not running, play safe and | |
1753 | * wait for the clocks to stabilise before | |
1754 | * continuing. | |
1755 | */ | |
1756 | POSTING_READ(intel_dp->output_reg); | |
1757 | msleep(50); | |
1758 | } else | |
1759 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
5bddd17f EA |
1760 | } |
1761 | ||
ea5b213a CW |
1762 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
1763 | POSTING_READ(intel_dp->output_reg); | |
f01eca2e | 1764 | msleep(intel_dp->panel_power_down_delay); |
a4fc5ed6 KP |
1765 | } |
1766 | ||
26d61aad KP |
1767 | static bool |
1768 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 1769 | { |
92fd8fd1 | 1770 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
0206e353 | 1771 | sizeof(intel_dp->dpcd)) && |
92fd8fd1 | 1772 | (intel_dp->dpcd[DP_DPCD_REV] != 0)) { |
26d61aad | 1773 | return true; |
92fd8fd1 KP |
1774 | } |
1775 | ||
26d61aad | 1776 | return false; |
92fd8fd1 KP |
1777 | } |
1778 | ||
a4fc5ed6 KP |
1779 | /* |
1780 | * According to DP spec | |
1781 | * 5.1.2: | |
1782 | * 1. Read DPCD | |
1783 | * 2. Configure link according to Receiver Capabilities | |
1784 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
1785 | * 4. Check link status on receipt of hot-plug interrupt | |
1786 | */ | |
1787 | ||
1788 | static void | |
ea5b213a | 1789 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1790 | { |
d2b996ac KP |
1791 | if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON) |
1792 | return; | |
59cd09e1 | 1793 | |
4ef69c7a | 1794 | if (!intel_dp->base.base.crtc) |
a4fc5ed6 KP |
1795 | return; |
1796 | ||
92fd8fd1 | 1797 | /* Try to read receiver status if the link appears to be up */ |
33a34e4e | 1798 | if (!intel_dp_get_link_status(intel_dp)) { |
ea5b213a | 1799 | intel_dp_link_down(intel_dp); |
a4fc5ed6 KP |
1800 | return; |
1801 | } | |
1802 | ||
92fd8fd1 | 1803 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 1804 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
1805 | intel_dp_link_down(intel_dp); |
1806 | return; | |
1807 | } | |
1808 | ||
33a34e4e | 1809 | if (!intel_channel_eq_ok(intel_dp)) { |
92fd8fd1 KP |
1810 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
1811 | drm_get_encoder_name(&intel_dp->base.base)); | |
33a34e4e JB |
1812 | intel_dp_start_link_train(intel_dp); |
1813 | intel_dp_complete_link_train(intel_dp); | |
1814 | } | |
a4fc5ed6 | 1815 | } |
a4fc5ed6 | 1816 | |
71ba9000 | 1817 | static enum drm_connector_status |
26d61aad | 1818 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 1819 | { |
26d61aad KP |
1820 | if (intel_dp_get_dpcd(intel_dp)) |
1821 | return connector_status_connected; | |
1822 | return connector_status_disconnected; | |
71ba9000 AJ |
1823 | } |
1824 | ||
5eb08b69 | 1825 | static enum drm_connector_status |
a9756bb5 | 1826 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 1827 | { |
5eb08b69 ZW |
1828 | enum drm_connector_status status; |
1829 | ||
fe16d949 CW |
1830 | /* Can't disconnect eDP, but you can close the lid... */ |
1831 | if (is_edp(intel_dp)) { | |
1832 | status = intel_panel_detect(intel_dp->base.base.dev); | |
1833 | if (status == connector_status_unknown) | |
1834 | status = connector_status_connected; | |
1835 | return status; | |
1836 | } | |
01cb9ea6 | 1837 | |
26d61aad | 1838 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
1839 | } |
1840 | ||
a4fc5ed6 | 1841 | static enum drm_connector_status |
a9756bb5 | 1842 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 1843 | { |
4ef69c7a | 1844 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1845 | struct drm_i915_private *dev_priv = dev->dev_private; |
a9756bb5 | 1846 | uint32_t temp, bit; |
5eb08b69 | 1847 | |
ea5b213a | 1848 | switch (intel_dp->output_reg) { |
a4fc5ed6 KP |
1849 | case DP_B: |
1850 | bit = DPB_HOTPLUG_INT_STATUS; | |
1851 | break; | |
1852 | case DP_C: | |
1853 | bit = DPC_HOTPLUG_INT_STATUS; | |
1854 | break; | |
1855 | case DP_D: | |
1856 | bit = DPD_HOTPLUG_INT_STATUS; | |
1857 | break; | |
1858 | default: | |
1859 | return connector_status_unknown; | |
1860 | } | |
1861 | ||
1862 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
1863 | ||
1864 | if ((temp & bit) == 0) | |
1865 | return connector_status_disconnected; | |
1866 | ||
26d61aad | 1867 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
1868 | } |
1869 | ||
8c241fef KP |
1870 | static struct edid * |
1871 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
1872 | { | |
1873 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1874 | struct edid *edid; | |
1875 | ||
1876 | ironlake_edp_panel_vdd_on(intel_dp); | |
1877 | edid = drm_get_edid(connector, adapter); | |
bd943159 | 1878 | ironlake_edp_panel_vdd_off(intel_dp, false); |
8c241fef KP |
1879 | return edid; |
1880 | } | |
1881 | ||
1882 | static int | |
1883 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) | |
1884 | { | |
1885 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1886 | int ret; | |
1887 | ||
1888 | ironlake_edp_panel_vdd_on(intel_dp); | |
1889 | ret = intel_ddc_get_modes(connector, adapter); | |
bd943159 | 1890 | ironlake_edp_panel_vdd_off(intel_dp, false); |
8c241fef KP |
1891 | return ret; |
1892 | } | |
1893 | ||
1894 | ||
a9756bb5 ZW |
1895 | /** |
1896 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. | |
1897 | * | |
1898 | * \return true if DP port is connected. | |
1899 | * \return false if DP port is disconnected. | |
1900 | */ | |
1901 | static enum drm_connector_status | |
1902 | intel_dp_detect(struct drm_connector *connector, bool force) | |
1903 | { | |
1904 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1905 | struct drm_device *dev = intel_dp->base.base.dev; | |
1906 | enum drm_connector_status status; | |
1907 | struct edid *edid = NULL; | |
1908 | ||
1909 | intel_dp->has_audio = false; | |
1910 | ||
1911 | if (HAS_PCH_SPLIT(dev)) | |
1912 | status = ironlake_dp_detect(intel_dp); | |
1913 | else | |
1914 | status = g4x_dp_detect(intel_dp); | |
1b9be9d0 | 1915 | |
ac66ae83 AJ |
1916 | DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", |
1917 | intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], | |
1918 | intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], | |
1919 | intel_dp->dpcd[6], intel_dp->dpcd[7]); | |
1b9be9d0 | 1920 | |
a9756bb5 ZW |
1921 | if (status != connector_status_connected) |
1922 | return status; | |
1923 | ||
f684960e CW |
1924 | if (intel_dp->force_audio) { |
1925 | intel_dp->has_audio = intel_dp->force_audio > 0; | |
1926 | } else { | |
8c241fef | 1927 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
f684960e CW |
1928 | if (edid) { |
1929 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
1930 | connector->display_info.raw_edid = NULL; | |
1931 | kfree(edid); | |
1932 | } | |
a9756bb5 ZW |
1933 | } |
1934 | ||
1935 | return connector_status_connected; | |
a4fc5ed6 KP |
1936 | } |
1937 | ||
1938 | static int intel_dp_get_modes(struct drm_connector *connector) | |
1939 | { | |
df0e9248 | 1940 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4ef69c7a | 1941 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1942 | struct drm_i915_private *dev_priv = dev->dev_private; |
1943 | int ret; | |
a4fc5ed6 KP |
1944 | |
1945 | /* We should parse the EDID data and find out if it has an audio sink | |
1946 | */ | |
1947 | ||
8c241fef | 1948 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
b9efc480 | 1949 | if (ret) { |
d15456de | 1950 | if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) { |
b9efc480 ZY |
1951 | struct drm_display_mode *newmode; |
1952 | list_for_each_entry(newmode, &connector->probed_modes, | |
1953 | head) { | |
d15456de KP |
1954 | if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) { |
1955 | intel_dp->panel_fixed_mode = | |
b9efc480 ZY |
1956 | drm_mode_duplicate(dev, newmode); |
1957 | break; | |
1958 | } | |
1959 | } | |
1960 | } | |
32f9d658 | 1961 | return ret; |
b9efc480 | 1962 | } |
32f9d658 ZW |
1963 | |
1964 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ | |
4d926461 | 1965 | if (is_edp(intel_dp)) { |
47f0eb22 | 1966 | /* initialize panel mode from VBT if available for eDP */ |
d15456de KP |
1967 | if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) { |
1968 | intel_dp->panel_fixed_mode = | |
47f0eb22 | 1969 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
d15456de KP |
1970 | if (intel_dp->panel_fixed_mode) { |
1971 | intel_dp->panel_fixed_mode->type |= | |
47f0eb22 KP |
1972 | DRM_MODE_TYPE_PREFERRED; |
1973 | } | |
1974 | } | |
d15456de | 1975 | if (intel_dp->panel_fixed_mode) { |
32f9d658 | 1976 | struct drm_display_mode *mode; |
d15456de | 1977 | mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode); |
32f9d658 ZW |
1978 | drm_mode_probed_add(connector, mode); |
1979 | return 1; | |
1980 | } | |
1981 | } | |
1982 | return 0; | |
a4fc5ed6 KP |
1983 | } |
1984 | ||
1aad7ac0 CW |
1985 | static bool |
1986 | intel_dp_detect_audio(struct drm_connector *connector) | |
1987 | { | |
1988 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1989 | struct edid *edid; | |
1990 | bool has_audio = false; | |
1991 | ||
8c241fef | 1992 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
1aad7ac0 CW |
1993 | if (edid) { |
1994 | has_audio = drm_detect_monitor_audio(edid); | |
1995 | ||
1996 | connector->display_info.raw_edid = NULL; | |
1997 | kfree(edid); | |
1998 | } | |
1999 | ||
2000 | return has_audio; | |
2001 | } | |
2002 | ||
f684960e CW |
2003 | static int |
2004 | intel_dp_set_property(struct drm_connector *connector, | |
2005 | struct drm_property *property, | |
2006 | uint64_t val) | |
2007 | { | |
e953fd7b | 2008 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
f684960e CW |
2009 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
2010 | int ret; | |
2011 | ||
2012 | ret = drm_connector_property_set_value(connector, property, val); | |
2013 | if (ret) | |
2014 | return ret; | |
2015 | ||
3f43c48d | 2016 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
2017 | int i = val; |
2018 | bool has_audio; | |
2019 | ||
2020 | if (i == intel_dp->force_audio) | |
f684960e CW |
2021 | return 0; |
2022 | ||
1aad7ac0 | 2023 | intel_dp->force_audio = i; |
f684960e | 2024 | |
1aad7ac0 CW |
2025 | if (i == 0) |
2026 | has_audio = intel_dp_detect_audio(connector); | |
2027 | else | |
2028 | has_audio = i > 0; | |
2029 | ||
2030 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
2031 | return 0; |
2032 | ||
1aad7ac0 | 2033 | intel_dp->has_audio = has_audio; |
f684960e CW |
2034 | goto done; |
2035 | } | |
2036 | ||
e953fd7b CW |
2037 | if (property == dev_priv->broadcast_rgb_property) { |
2038 | if (val == !!intel_dp->color_range) | |
2039 | return 0; | |
2040 | ||
2041 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; | |
2042 | goto done; | |
2043 | } | |
2044 | ||
f684960e CW |
2045 | return -EINVAL; |
2046 | ||
2047 | done: | |
2048 | if (intel_dp->base.base.crtc) { | |
2049 | struct drm_crtc *crtc = intel_dp->base.base.crtc; | |
2050 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
2051 | crtc->x, crtc->y, | |
2052 | crtc->fb); | |
2053 | } | |
2054 | ||
2055 | return 0; | |
2056 | } | |
2057 | ||
a4fc5ed6 | 2058 | static void |
0206e353 | 2059 | intel_dp_destroy(struct drm_connector *connector) |
a4fc5ed6 | 2060 | { |
aaa6fd2a MG |
2061 | struct drm_device *dev = connector->dev; |
2062 | ||
2063 | if (intel_dpd_is_edp(dev)) | |
2064 | intel_panel_destroy_backlight(dev); | |
2065 | ||
a4fc5ed6 KP |
2066 | drm_sysfs_connector_remove(connector); |
2067 | drm_connector_cleanup(connector); | |
55f78c43 | 2068 | kfree(connector); |
a4fc5ed6 KP |
2069 | } |
2070 | ||
24d05927 DV |
2071 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
2072 | { | |
2073 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
2074 | ||
2075 | i2c_del_adapter(&intel_dp->adapter); | |
2076 | drm_encoder_cleanup(encoder); | |
bd943159 KP |
2077 | if (is_edp(intel_dp)) { |
2078 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
2079 | ironlake_panel_vdd_off_sync(intel_dp); | |
2080 | } | |
24d05927 DV |
2081 | kfree(intel_dp); |
2082 | } | |
2083 | ||
a4fc5ed6 KP |
2084 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
2085 | .dpms = intel_dp_dpms, | |
2086 | .mode_fixup = intel_dp_mode_fixup, | |
d240f20f | 2087 | .prepare = intel_dp_prepare, |
a4fc5ed6 | 2088 | .mode_set = intel_dp_mode_set, |
d240f20f | 2089 | .commit = intel_dp_commit, |
a4fc5ed6 KP |
2090 | }; |
2091 | ||
2092 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
2093 | .dpms = drm_helper_connector_dpms, | |
a4fc5ed6 KP |
2094 | .detect = intel_dp_detect, |
2095 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 2096 | .set_property = intel_dp_set_property, |
a4fc5ed6 KP |
2097 | .destroy = intel_dp_destroy, |
2098 | }; | |
2099 | ||
2100 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
2101 | .get_modes = intel_dp_get_modes, | |
2102 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 2103 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
2104 | }; |
2105 | ||
a4fc5ed6 | 2106 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 2107 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
2108 | }; |
2109 | ||
995b6762 | 2110 | static void |
21d40d37 | 2111 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 2112 | { |
ea5b213a | 2113 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
c8110e52 | 2114 | |
885a5014 | 2115 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 2116 | } |
6207937d | 2117 | |
e3421a18 ZW |
2118 | /* Return which DP Port should be selected for Transcoder DP control */ |
2119 | int | |
0206e353 | 2120 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
e3421a18 ZW |
2121 | { |
2122 | struct drm_device *dev = crtc->dev; | |
2123 | struct drm_mode_config *mode_config = &dev->mode_config; | |
2124 | struct drm_encoder *encoder; | |
e3421a18 ZW |
2125 | |
2126 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a CW |
2127 | struct intel_dp *intel_dp; |
2128 | ||
d8201ab6 | 2129 | if (encoder->crtc != crtc) |
e3421a18 ZW |
2130 | continue; |
2131 | ||
ea5b213a CW |
2132 | intel_dp = enc_to_intel_dp(encoder); |
2133 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) | |
2134 | return intel_dp->output_reg; | |
e3421a18 | 2135 | } |
ea5b213a | 2136 | |
e3421a18 ZW |
2137 | return -1; |
2138 | } | |
2139 | ||
36e83a18 | 2140 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 2141 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
2142 | { |
2143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2144 | struct child_device_config *p_child; | |
2145 | int i; | |
2146 | ||
2147 | if (!dev_priv->child_dev_num) | |
2148 | return false; | |
2149 | ||
2150 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
2151 | p_child = dev_priv->child_dev + i; | |
2152 | ||
2153 | if (p_child->dvo_port == PORT_IDPD && | |
2154 | p_child->device_type == DEVICE_TYPE_eDP) | |
2155 | return true; | |
2156 | } | |
2157 | return false; | |
2158 | } | |
2159 | ||
f684960e CW |
2160 | static void |
2161 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
2162 | { | |
3f43c48d | 2163 | intel_attach_force_audio_property(connector); |
e953fd7b | 2164 | intel_attach_broadcast_rgb_property(connector); |
f684960e CW |
2165 | } |
2166 | ||
a4fc5ed6 KP |
2167 | void |
2168 | intel_dp_init(struct drm_device *dev, int output_reg) | |
2169 | { | |
2170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2171 | struct drm_connector *connector; | |
ea5b213a | 2172 | struct intel_dp *intel_dp; |
21d40d37 | 2173 | struct intel_encoder *intel_encoder; |
55f78c43 | 2174 | struct intel_connector *intel_connector; |
5eb08b69 | 2175 | const char *name = NULL; |
b329530c | 2176 | int type; |
a4fc5ed6 | 2177 | |
ea5b213a CW |
2178 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
2179 | if (!intel_dp) | |
a4fc5ed6 KP |
2180 | return; |
2181 | ||
3d3dc149 | 2182 | intel_dp->output_reg = output_reg; |
d2b996ac | 2183 | intel_dp->dpms_mode = -1; |
3d3dc149 | 2184 | |
55f78c43 ZW |
2185 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
2186 | if (!intel_connector) { | |
ea5b213a | 2187 | kfree(intel_dp); |
55f78c43 ZW |
2188 | return; |
2189 | } | |
ea5b213a | 2190 | intel_encoder = &intel_dp->base; |
55f78c43 | 2191 | |
ea5b213a | 2192 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
b329530c | 2193 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 2194 | intel_dp->is_pch_edp = true; |
b329530c | 2195 | |
cfcb0fc9 | 2196 | if (output_reg == DP_A || is_pch_edp(intel_dp)) { |
b329530c AJ |
2197 | type = DRM_MODE_CONNECTOR_eDP; |
2198 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
2199 | } else { | |
2200 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
2201 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
2202 | } | |
2203 | ||
55f78c43 | 2204 | connector = &intel_connector->base; |
b329530c | 2205 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
2206 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
2207 | ||
eb1f8e4f DA |
2208 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
2209 | ||
652af9d7 | 2210 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
21d40d37 | 2211 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
652af9d7 | 2212 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
21d40d37 | 2213 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
652af9d7 | 2214 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
21d40d37 | 2215 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
f8aed700 | 2216 | |
bd943159 | 2217 | if (is_edp(intel_dp)) { |
21d40d37 | 2218 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
bd943159 KP |
2219 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
2220 | ironlake_panel_vdd_work); | |
2221 | } | |
6251ec0a | 2222 | |
27f8227b | 2223 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
a4fc5ed6 KP |
2224 | connector->interlace_allowed = true; |
2225 | connector->doublescan_allowed = 0; | |
2226 | ||
4ef69c7a | 2227 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
a4fc5ed6 | 2228 | DRM_MODE_ENCODER_TMDS); |
4ef69c7a | 2229 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
a4fc5ed6 | 2230 | |
df0e9248 | 2231 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
2232 | drm_sysfs_connector_add(connector); |
2233 | ||
2234 | /* Set up the DDC bus. */ | |
5eb08b69 | 2235 | switch (output_reg) { |
32f9d658 ZW |
2236 | case DP_A: |
2237 | name = "DPDDC-A"; | |
2238 | break; | |
5eb08b69 ZW |
2239 | case DP_B: |
2240 | case PCH_DP_B: | |
b01f2c3a JB |
2241 | dev_priv->hotplug_supported_mask |= |
2242 | HDMIB_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2243 | name = "DPDDC-B"; |
2244 | break; | |
2245 | case DP_C: | |
2246 | case PCH_DP_C: | |
b01f2c3a JB |
2247 | dev_priv->hotplug_supported_mask |= |
2248 | HDMIC_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2249 | name = "DPDDC-C"; |
2250 | break; | |
2251 | case DP_D: | |
2252 | case PCH_DP_D: | |
b01f2c3a JB |
2253 | dev_priv->hotplug_supported_mask |= |
2254 | HDMID_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2255 | name = "DPDDC-D"; |
2256 | break; | |
2257 | } | |
2258 | ||
89667383 JB |
2259 | /* Cache some DPCD data in the eDP case */ |
2260 | if (is_edp(intel_dp)) { | |
59f3e272 | 2261 | bool ret; |
f01eca2e KP |
2262 | struct edp_power_seq cur, vbt; |
2263 | u32 pp_on, pp_off, pp_div; | |
5d613501 JB |
2264 | |
2265 | pp_on = I915_READ(PCH_PP_ON_DELAYS); | |
f01eca2e | 2266 | pp_off = I915_READ(PCH_PP_OFF_DELAYS); |
5d613501 | 2267 | pp_div = I915_READ(PCH_PP_DIVISOR); |
89667383 | 2268 | |
f01eca2e KP |
2269 | /* Pull timing values out of registers */ |
2270 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
2271 | PANEL_POWER_UP_DELAY_SHIFT; | |
2272 | ||
2273 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
2274 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
2275 | ||
2276 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
2277 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
2278 | ||
2279 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
2280 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
2281 | ||
2282 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
2283 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
2284 | ||
2285 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2286 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
2287 | ||
2288 | vbt = dev_priv->edp.pps; | |
2289 | ||
2290 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2291 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
2292 | ||
2293 | #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10) | |
2294 | ||
2295 | intel_dp->panel_power_up_delay = get_delay(t1_t3); | |
2296 | intel_dp->backlight_on_delay = get_delay(t8); | |
2297 | intel_dp->backlight_off_delay = get_delay(t9); | |
2298 | intel_dp->panel_power_down_delay = get_delay(t10); | |
2299 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
2300 | ||
2301 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", | |
2302 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
2303 | intel_dp->panel_power_cycle_delay); | |
2304 | ||
2305 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
2306 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
5d613501 | 2307 | |
bd943159 | 2308 | intel_dp->panel_off_jiffies = jiffies - intel_dp->panel_power_down_delay; |
5d613501 JB |
2309 | |
2310 | ironlake_edp_panel_vdd_on(intel_dp); | |
59f3e272 | 2311 | ret = intel_dp_get_dpcd(intel_dp); |
bd943159 | 2312 | ironlake_edp_panel_vdd_off(intel_dp, false); |
59f3e272 | 2313 | if (ret) { |
7183dc29 JB |
2314 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
2315 | dev_priv->no_aux_handshake = | |
2316 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
89667383 JB |
2317 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
2318 | } else { | |
3d3dc149 | 2319 | /* if this fails, presume the device is a ghost */ |
48898b03 | 2320 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
3d3dc149 | 2321 | intel_dp_encoder_destroy(&intel_dp->base.base); |
48898b03 | 2322 | intel_dp_destroy(&intel_connector->base); |
3d3dc149 | 2323 | return; |
89667383 | 2324 | } |
89667383 JB |
2325 | } |
2326 | ||
552fb0b7 KP |
2327 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
2328 | ||
21d40d37 | 2329 | intel_encoder->hot_plug = intel_dp_hot_plug; |
a4fc5ed6 | 2330 | |
4d926461 | 2331 | if (is_edp(intel_dp)) { |
aaa6fd2a MG |
2332 | dev_priv->int_edp_connector = connector; |
2333 | intel_panel_setup_backlight(dev); | |
32f9d658 ZW |
2334 | } |
2335 | ||
f684960e CW |
2336 | intel_dp_add_properties(intel_dp, connector); |
2337 | ||
a4fc5ed6 KP |
2338 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
2339 | * 0xd. Failure to do so will result in spurious interrupts being | |
2340 | * generated on the port when a cable is not attached. | |
2341 | */ | |
2342 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
2343 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
2344 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2345 | } | |
2346 | } |