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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
611032bf | 31 | #include <linux/types.h> |
01527b31 CT |
32 | #include <linux/notifier.h> |
33 | #include <linux/reboot.h> | |
611032bf | 34 | #include <asm/byteorder.h> |
760285e7 | 35 | #include <drm/drmP.h> |
c6f95f27 | 36 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
37 | #include <drm/drm_crtc.h> |
38 | #include <drm/drm_crtc_helper.h> | |
39 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 40 | #include "intel_drv.h" |
760285e7 | 41 | #include <drm/i915_drm.h> |
a4fc5ed6 | 42 | #include "i915_drv.h" |
a4fc5ed6 | 43 | |
a4fc5ed6 KP |
44 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
45 | ||
559be30c TP |
46 | /* Compliance test status bits */ |
47 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 | |
48 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
49 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
50 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
51 | ||
9dd4ffdf | 52 | struct dp_link_dpll { |
840b32b7 | 53 | int clock; |
9dd4ffdf CML |
54 | struct dpll dpll; |
55 | }; | |
56 | ||
57 | static const struct dp_link_dpll gen4_dpll[] = { | |
840b32b7 | 58 | { 162000, |
9dd4ffdf | 59 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
840b32b7 | 60 | { 270000, |
9dd4ffdf CML |
61 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
62 | }; | |
63 | ||
64 | static const struct dp_link_dpll pch_dpll[] = { | |
840b32b7 | 65 | { 162000, |
9dd4ffdf | 66 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
840b32b7 | 67 | { 270000, |
9dd4ffdf CML |
68 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
69 | }; | |
70 | ||
65ce4bf5 | 71 | static const struct dp_link_dpll vlv_dpll[] = { |
840b32b7 | 72 | { 162000, |
58f6e632 | 73 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
840b32b7 | 74 | { 270000, |
65ce4bf5 CML |
75 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
76 | }; | |
77 | ||
ef9348c8 CML |
78 | /* |
79 | * CHV supports eDP 1.4 that have more link rates. | |
80 | * Below only provides the fixed rate but exclude variable rate. | |
81 | */ | |
82 | static const struct dp_link_dpll chv_dpll[] = { | |
83 | /* | |
84 | * CHV requires to program fractional division for m2. | |
85 | * m2 is stored in fixed point format using formula below | |
86 | * (m2_int << 22) | m2_fraction | |
87 | */ | |
840b32b7 | 88 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
ef9348c8 | 89 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
840b32b7 | 90 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 | 91 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
840b32b7 | 92 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 CML |
93 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
94 | }; | |
637a9c63 | 95 | |
64987fc5 SJ |
96 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
97 | 324000, 432000, 540000 }; | |
637a9c63 | 98 | static const int skl_rates[] = { 162000, 216000, 270000, |
f4896f15 VS |
99 | 324000, 432000, 540000 }; |
100 | static const int default_rates[] = { 162000, 270000, 540000 }; | |
ef9348c8 | 101 | |
cfcb0fc9 JB |
102 | /** |
103 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
104 | * @intel_dp: DP struct | |
105 | * | |
106 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
107 | * will return true, and false otherwise. | |
108 | */ | |
109 | static bool is_edp(struct intel_dp *intel_dp) | |
110 | { | |
da63a9f2 PZ |
111 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
112 | ||
113 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
114 | } |
115 | ||
68b4d824 | 116 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 117 | { |
68b4d824 ID |
118 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
119 | ||
120 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
121 | } |
122 | ||
df0e9248 CW |
123 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
124 | { | |
fa90ecef | 125 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
126 | } |
127 | ||
ea5b213a | 128 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
1e0560e0 | 129 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 130 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
093e3f13 | 131 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
a8c3344e VS |
132 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
133 | enum pipe pipe); | |
f21a2198 | 134 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
a4fc5ed6 | 135 | |
68f357cb JN |
136 | static int intel_dp_num_rates(u8 link_bw_code) |
137 | { | |
138 | switch (link_bw_code) { | |
139 | default: | |
140 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", | |
141 | link_bw_code); | |
142 | case DP_LINK_BW_1_62: | |
143 | return 1; | |
144 | case DP_LINK_BW_2_7: | |
145 | return 2; | |
146 | case DP_LINK_BW_5_4: | |
147 | return 3; | |
148 | } | |
149 | } | |
150 | ||
151 | /* update sink rates from dpcd */ | |
152 | static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) | |
153 | { | |
154 | int i, num_rates; | |
155 | ||
156 | num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]); | |
157 | ||
158 | for (i = 0; i < num_rates; i++) | |
159 | intel_dp->sink_rates[i] = default_rates[i]; | |
160 | ||
161 | intel_dp->num_sink_rates = num_rates; | |
162 | } | |
163 | ||
a079d108 | 164 | static int intel_dp_max_sink_rate(struct intel_dp *intel_dp) |
a4fc5ed6 | 165 | { |
a079d108 | 166 | return intel_dp->sink_rates[intel_dp->num_sink_rates - 1]; |
a4fc5ed6 KP |
167 | } |
168 | ||
eeb6324d PZ |
169 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
170 | { | |
171 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
eeb6324d PZ |
172 | u8 source_max, sink_max; |
173 | ||
ccb1a831 | 174 | source_max = intel_dig_port->max_lanes; |
f482984a | 175 | sink_max = intel_dp->max_sink_lane_count; |
eeb6324d PZ |
176 | |
177 | return min(source_max, sink_max); | |
178 | } | |
179 | ||
22a2c8e0 | 180 | int |
c898261c | 181 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 182 | { |
fd81c44e DP |
183 | /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ |
184 | return DIV_ROUND_UP(pixel_clock * bpp, 8); | |
a4fc5ed6 KP |
185 | } |
186 | ||
22a2c8e0 | 187 | int |
fe27d53e DA |
188 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
189 | { | |
fd81c44e DP |
190 | /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the |
191 | * link rate that is generally expressed in Gbps. Since, 8 bits of data | |
192 | * is transmitted every LS_Clk per lane, there is no need to account for | |
193 | * the channel encoding that is done in the PHY layer here. | |
194 | */ | |
195 | ||
196 | return max_link_clock * max_lanes; | |
fe27d53e DA |
197 | } |
198 | ||
70ec0645 MK |
199 | static int |
200 | intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) | |
201 | { | |
202 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
203 | struct intel_encoder *encoder = &intel_dig_port->base; | |
204 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
205 | int max_dotclk = dev_priv->max_dotclk_freq; | |
206 | int ds_max_dotclk; | |
207 | ||
208 | int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
209 | ||
210 | if (type != DP_DS_PORT_TYPE_VGA) | |
211 | return max_dotclk; | |
212 | ||
213 | ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, | |
214 | intel_dp->downstream_ports); | |
215 | ||
216 | if (ds_max_dotclk != 0) | |
217 | max_dotclk = min(max_dotclk, ds_max_dotclk); | |
218 | ||
219 | return max_dotclk; | |
220 | } | |
221 | ||
55cfc580 JN |
222 | static void |
223 | intel_dp_set_source_rates(struct intel_dp *intel_dp) | |
40dba341 NM |
224 | { |
225 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
226 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
55cfc580 | 227 | const int *source_rates; |
40dba341 NM |
228 | int size; |
229 | ||
55cfc580 JN |
230 | /* This should only be done once */ |
231 | WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); | |
232 | ||
cc3f90f0 | 233 | if (IS_GEN9_LP(dev_priv)) { |
55cfc580 | 234 | source_rates = bxt_rates; |
40dba341 | 235 | size = ARRAY_SIZE(bxt_rates); |
b976dc53 | 236 | } else if (IS_GEN9_BC(dev_priv)) { |
55cfc580 | 237 | source_rates = skl_rates; |
40dba341 NM |
238 | size = ARRAY_SIZE(skl_rates); |
239 | } else { | |
55cfc580 | 240 | source_rates = default_rates; |
40dba341 NM |
241 | size = ARRAY_SIZE(default_rates); |
242 | } | |
243 | ||
244 | /* This depends on the fact that 5.4 is last value in the array */ | |
245 | if (!intel_dp_source_supports_hbr2(intel_dp)) | |
246 | size--; | |
247 | ||
55cfc580 JN |
248 | intel_dp->source_rates = source_rates; |
249 | intel_dp->num_source_rates = size; | |
40dba341 NM |
250 | } |
251 | ||
252 | static int intersect_rates(const int *source_rates, int source_len, | |
253 | const int *sink_rates, int sink_len, | |
254 | int *common_rates) | |
255 | { | |
256 | int i = 0, j = 0, k = 0; | |
257 | ||
258 | while (i < source_len && j < sink_len) { | |
259 | if (source_rates[i] == sink_rates[j]) { | |
260 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) | |
261 | return k; | |
262 | common_rates[k] = source_rates[i]; | |
263 | ++k; | |
264 | ++i; | |
265 | ++j; | |
266 | } else if (source_rates[i] < sink_rates[j]) { | |
267 | ++i; | |
268 | } else { | |
269 | ++j; | |
270 | } | |
271 | } | |
272 | return k; | |
273 | } | |
274 | ||
8001b754 JN |
275 | /* return index of rate in rates array, or -1 if not found */ |
276 | static int intel_dp_rate_index(const int *rates, int len, int rate) | |
277 | { | |
278 | int i; | |
279 | ||
280 | for (i = 0; i < len; i++) | |
281 | if (rate == rates[i]) | |
282 | return i; | |
283 | ||
284 | return -1; | |
285 | } | |
286 | ||
975ee5fc | 287 | static void intel_dp_set_common_rates(struct intel_dp *intel_dp) |
40dba341 | 288 | { |
975ee5fc | 289 | WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates); |
40dba341 | 290 | |
975ee5fc JN |
291 | intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, |
292 | intel_dp->num_source_rates, | |
293 | intel_dp->sink_rates, | |
294 | intel_dp->num_sink_rates, | |
295 | intel_dp->common_rates); | |
296 | ||
297 | /* Paranoia, there should always be something in common. */ | |
298 | if (WARN_ON(intel_dp->num_common_rates == 0)) { | |
299 | intel_dp->common_rates[0] = default_rates[0]; | |
300 | intel_dp->num_common_rates = 1; | |
301 | } | |
302 | } | |
303 | ||
304 | /* get length of common rates potentially limited by max_rate */ | |
305 | static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp, | |
306 | int max_rate) | |
307 | { | |
308 | const int *common_rates = intel_dp->common_rates; | |
309 | int i, common_len = intel_dp->num_common_rates; | |
68f357cb JN |
310 | |
311 | /* Limit results by potentially reduced max rate */ | |
312 | for (i = 0; i < common_len; i++) { | |
313 | if (common_rates[common_len - i - 1] <= max_rate) | |
314 | return common_len - i; | |
315 | } | |
40dba341 | 316 | |
68f357cb | 317 | return 0; |
40dba341 NM |
318 | } |
319 | ||
fdb14d33 MN |
320 | int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, |
321 | int link_rate, uint8_t lane_count) | |
322 | { | |
b1810a74 | 323 | int index; |
fdb14d33 | 324 | |
b1810a74 JN |
325 | index = intel_dp_rate_index(intel_dp->common_rates, |
326 | intel_dp->num_common_rates, | |
327 | link_rate); | |
328 | if (index > 0) { | |
329 | intel_dp->max_sink_link_rate = intel_dp->common_rates[index - 1]; | |
fdb14d33 MN |
330 | intel_dp->max_sink_lane_count = lane_count; |
331 | } else if (lane_count > 1) { | |
a079d108 | 332 | intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp); |
fdb14d33 MN |
333 | intel_dp->max_sink_lane_count = lane_count >> 1; |
334 | } else { | |
335 | DRM_ERROR("Link Training Unsuccessful\n"); | |
336 | return -1; | |
337 | } | |
338 | ||
339 | return 0; | |
340 | } | |
341 | ||
c19de8eb | 342 | static enum drm_mode_status |
a4fc5ed6 KP |
343 | intel_dp_mode_valid(struct drm_connector *connector, |
344 | struct drm_display_mode *mode) | |
345 | { | |
df0e9248 | 346 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
347 | struct intel_connector *intel_connector = to_intel_connector(connector); |
348 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
349 | int target_clock = mode->clock; |
350 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
70ec0645 MK |
351 | int max_dotclk; |
352 | ||
353 | max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); | |
a4fc5ed6 | 354 | |
dd06f90e JN |
355 | if (is_edp(intel_dp) && fixed_mode) { |
356 | if (mode->hdisplay > fixed_mode->hdisplay) | |
7de56f43 ZY |
357 | return MODE_PANEL; |
358 | ||
dd06f90e | 359 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 360 | return MODE_PANEL; |
03afc4a2 DV |
361 | |
362 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
363 | } |
364 | ||
50fec21a | 365 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
eeb6324d | 366 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 DV |
367 | |
368 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
369 | mode_rate = intel_dp_link_required(target_clock, 18); | |
370 | ||
799487f5 | 371 | if (mode_rate > max_rate || target_clock > max_dotclk) |
c4867936 | 372 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
373 | |
374 | if (mode->clock < 10000) | |
375 | return MODE_CLOCK_LOW; | |
376 | ||
0af78a2b DV |
377 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
378 | return MODE_H_ILLEGAL; | |
379 | ||
a4fc5ed6 KP |
380 | return MODE_OK; |
381 | } | |
382 | ||
a4f1289e | 383 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
a4fc5ed6 KP |
384 | { |
385 | int i; | |
386 | uint32_t v = 0; | |
387 | ||
388 | if (src_bytes > 4) | |
389 | src_bytes = 4; | |
390 | for (i = 0; i < src_bytes; i++) | |
391 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
392 | return v; | |
393 | } | |
394 | ||
c2af70e2 | 395 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
a4fc5ed6 KP |
396 | { |
397 | int i; | |
398 | if (dst_bytes > 4) | |
399 | dst_bytes = 4; | |
400 | for (i = 0; i < dst_bytes; i++) | |
401 | dst[i] = src >> ((3-i) * 8); | |
402 | } | |
403 | ||
bf13e81b JN |
404 | static void |
405 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
36b5f425 | 406 | struct intel_dp *intel_dp); |
bf13e81b JN |
407 | static void |
408 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
5d5ab2d2 VS |
409 | struct intel_dp *intel_dp, |
410 | bool force_disable_vdd); | |
335f752b ID |
411 | static void |
412 | intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp); | |
bf13e81b | 413 | |
773538e8 VS |
414 | static void pps_lock(struct intel_dp *intel_dp) |
415 | { | |
416 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
417 | struct intel_encoder *encoder = &intel_dig_port->base; | |
418 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 419 | struct drm_i915_private *dev_priv = to_i915(dev); |
773538e8 VS |
420 | |
421 | /* | |
422 | * See vlv_power_sequencer_reset() why we need | |
423 | * a power domain reference here. | |
424 | */ | |
5432fcaf | 425 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
773538e8 VS |
426 | |
427 | mutex_lock(&dev_priv->pps_mutex); | |
428 | } | |
429 | ||
430 | static void pps_unlock(struct intel_dp *intel_dp) | |
431 | { | |
432 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
433 | struct intel_encoder *encoder = &intel_dig_port->base; | |
434 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 435 | struct drm_i915_private *dev_priv = to_i915(dev); |
773538e8 VS |
436 | |
437 | mutex_unlock(&dev_priv->pps_mutex); | |
438 | ||
5432fcaf | 439 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
773538e8 VS |
440 | } |
441 | ||
961a0db0 VS |
442 | static void |
443 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) | |
444 | { | |
445 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
30ad9814 | 446 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
961a0db0 | 447 | enum pipe pipe = intel_dp->pps_pipe; |
0047eedc VS |
448 | bool pll_enabled, release_cl_override = false; |
449 | enum dpio_phy phy = DPIO_PHY(pipe); | |
450 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); | |
961a0db0 VS |
451 | uint32_t DP; |
452 | ||
453 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, | |
454 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", | |
455 | pipe_name(pipe), port_name(intel_dig_port->port))) | |
456 | return; | |
457 | ||
458 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", | |
459 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
460 | ||
461 | /* Preserve the BIOS-computed detected bit. This is | |
462 | * supposed to be read-only. | |
463 | */ | |
464 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
465 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
466 | DP |= DP_PORT_WIDTH(1); | |
467 | DP |= DP_LINK_TRAIN_PAT_1; | |
468 | ||
920a14b2 | 469 | if (IS_CHERRYVIEW(dev_priv)) |
961a0db0 VS |
470 | DP |= DP_PIPE_SELECT_CHV(pipe); |
471 | else if (pipe == PIPE_B) | |
472 | DP |= DP_PIPEB_SELECT; | |
473 | ||
d288f65f VS |
474 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
475 | ||
476 | /* | |
477 | * The DPLL for the pipe must be enabled for this to work. | |
478 | * So enable temporarily it if it's not already enabled. | |
479 | */ | |
0047eedc | 480 | if (!pll_enabled) { |
920a14b2 | 481 | release_cl_override = IS_CHERRYVIEW(dev_priv) && |
0047eedc VS |
482 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
483 | ||
30ad9814 | 484 | if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ? |
3f36b937 TU |
485 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
486 | DRM_ERROR("Failed to force on pll for pipe %c!\n", | |
487 | pipe_name(pipe)); | |
488 | return; | |
489 | } | |
0047eedc | 490 | } |
d288f65f | 491 | |
961a0db0 VS |
492 | /* |
493 | * Similar magic as in intel_dp_enable_port(). | |
494 | * We _must_ do this port enable + disable trick | |
495 | * to make this power seqeuencer lock onto the port. | |
496 | * Otherwise even VDD force bit won't work. | |
497 | */ | |
498 | I915_WRITE(intel_dp->output_reg, DP); | |
499 | POSTING_READ(intel_dp->output_reg); | |
500 | ||
501 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); | |
502 | POSTING_READ(intel_dp->output_reg); | |
503 | ||
504 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); | |
505 | POSTING_READ(intel_dp->output_reg); | |
d288f65f | 506 | |
0047eedc | 507 | if (!pll_enabled) { |
30ad9814 | 508 | vlv_force_pll_off(dev_priv, pipe); |
0047eedc VS |
509 | |
510 | if (release_cl_override) | |
511 | chv_phy_powergate_ch(dev_priv, phy, ch, false); | |
512 | } | |
961a0db0 VS |
513 | } |
514 | ||
9f2bdb00 VS |
515 | static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv) |
516 | { | |
517 | struct intel_encoder *encoder; | |
518 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); | |
519 | ||
520 | /* | |
521 | * We don't have power sequencer currently. | |
522 | * Pick one that's not used by other ports. | |
523 | */ | |
524 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
525 | struct intel_dp *intel_dp; | |
526 | ||
527 | if (encoder->type != INTEL_OUTPUT_DP && | |
528 | encoder->type != INTEL_OUTPUT_EDP) | |
529 | continue; | |
530 | ||
531 | intel_dp = enc_to_intel_dp(&encoder->base); | |
532 | ||
533 | if (encoder->type == INTEL_OUTPUT_EDP) { | |
534 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE && | |
535 | intel_dp->active_pipe != intel_dp->pps_pipe); | |
536 | ||
537 | if (intel_dp->pps_pipe != INVALID_PIPE) | |
538 | pipes &= ~(1 << intel_dp->pps_pipe); | |
539 | } else { | |
540 | WARN_ON(intel_dp->pps_pipe != INVALID_PIPE); | |
541 | ||
542 | if (intel_dp->active_pipe != INVALID_PIPE) | |
543 | pipes &= ~(1 << intel_dp->active_pipe); | |
544 | } | |
545 | } | |
546 | ||
547 | if (pipes == 0) | |
548 | return INVALID_PIPE; | |
549 | ||
550 | return ffs(pipes) - 1; | |
551 | } | |
552 | ||
bf13e81b JN |
553 | static enum pipe |
554 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
555 | { | |
556 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bf13e81b | 557 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 558 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8c3344e | 559 | enum pipe pipe; |
bf13e81b | 560 | |
e39b999a | 561 | lockdep_assert_held(&dev_priv->pps_mutex); |
bf13e81b | 562 | |
a8c3344e VS |
563 | /* We should never land here with regular DP ports */ |
564 | WARN_ON(!is_edp(intel_dp)); | |
565 | ||
9f2bdb00 VS |
566 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE && |
567 | intel_dp->active_pipe != intel_dp->pps_pipe); | |
568 | ||
a4a5d2f8 VS |
569 | if (intel_dp->pps_pipe != INVALID_PIPE) |
570 | return intel_dp->pps_pipe; | |
571 | ||
9f2bdb00 | 572 | pipe = vlv_find_free_pps(dev_priv); |
a4a5d2f8 VS |
573 | |
574 | /* | |
575 | * Didn't find one. This should not happen since there | |
576 | * are two power sequencers and up to two eDP ports. | |
577 | */ | |
9f2bdb00 | 578 | if (WARN_ON(pipe == INVALID_PIPE)) |
a8c3344e | 579 | pipe = PIPE_A; |
a4a5d2f8 | 580 | |
a8c3344e VS |
581 | vlv_steal_power_sequencer(dev, pipe); |
582 | intel_dp->pps_pipe = pipe; | |
a4a5d2f8 VS |
583 | |
584 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", | |
585 | pipe_name(intel_dp->pps_pipe), | |
586 | port_name(intel_dig_port->port)); | |
587 | ||
588 | /* init power sequencer on this pipe and port */ | |
36b5f425 | 589 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
5d5ab2d2 | 590 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true); |
a4a5d2f8 | 591 | |
961a0db0 VS |
592 | /* |
593 | * Even vdd force doesn't work until we've made | |
594 | * the power sequencer lock in on the port. | |
595 | */ | |
596 | vlv_power_sequencer_kick(intel_dp); | |
a4a5d2f8 VS |
597 | |
598 | return intel_dp->pps_pipe; | |
599 | } | |
600 | ||
78597996 ID |
601 | static int |
602 | bxt_power_sequencer_idx(struct intel_dp *intel_dp) | |
603 | { | |
604 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
605 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 606 | struct drm_i915_private *dev_priv = to_i915(dev); |
78597996 ID |
607 | |
608 | lockdep_assert_held(&dev_priv->pps_mutex); | |
609 | ||
610 | /* We should never land here with regular DP ports */ | |
611 | WARN_ON(!is_edp(intel_dp)); | |
612 | ||
613 | /* | |
614 | * TODO: BXT has 2 PPS instances. The correct port->PPS instance | |
615 | * mapping needs to be retrieved from VBT, for now just hard-code to | |
616 | * use instance #0 always. | |
617 | */ | |
618 | if (!intel_dp->pps_reset) | |
619 | return 0; | |
620 | ||
621 | intel_dp->pps_reset = false; | |
622 | ||
623 | /* | |
624 | * Only the HW needs to be reprogrammed, the SW state is fixed and | |
625 | * has been setup during connector init. | |
626 | */ | |
5d5ab2d2 | 627 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false); |
78597996 ID |
628 | |
629 | return 0; | |
630 | } | |
631 | ||
6491ab27 VS |
632 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
633 | enum pipe pipe); | |
634 | ||
635 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, | |
636 | enum pipe pipe) | |
637 | { | |
44cb734c | 638 | return I915_READ(PP_STATUS(pipe)) & PP_ON; |
6491ab27 VS |
639 | } |
640 | ||
641 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, | |
642 | enum pipe pipe) | |
643 | { | |
44cb734c | 644 | return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
6491ab27 VS |
645 | } |
646 | ||
647 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, | |
648 | enum pipe pipe) | |
649 | { | |
650 | return true; | |
651 | } | |
bf13e81b | 652 | |
a4a5d2f8 | 653 | static enum pipe |
6491ab27 VS |
654 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
655 | enum port port, | |
656 | vlv_pipe_check pipe_check) | |
a4a5d2f8 VS |
657 | { |
658 | enum pipe pipe; | |
bf13e81b | 659 | |
bf13e81b | 660 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
44cb734c | 661 | u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & |
bf13e81b | 662 | PANEL_PORT_SELECT_MASK; |
a4a5d2f8 VS |
663 | |
664 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) | |
665 | continue; | |
666 | ||
6491ab27 VS |
667 | if (!pipe_check(dev_priv, pipe)) |
668 | continue; | |
669 | ||
a4a5d2f8 | 670 | return pipe; |
bf13e81b JN |
671 | } |
672 | ||
a4a5d2f8 VS |
673 | return INVALID_PIPE; |
674 | } | |
675 | ||
676 | static void | |
677 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) | |
678 | { | |
679 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
680 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 681 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
682 | enum port port = intel_dig_port->port; |
683 | ||
684 | lockdep_assert_held(&dev_priv->pps_mutex); | |
685 | ||
686 | /* try to find a pipe with this port selected */ | |
6491ab27 VS |
687 | /* first pick one where the panel is on */ |
688 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
689 | vlv_pipe_has_pp_on); | |
690 | /* didn't find one? pick one where vdd is on */ | |
691 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
692 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
693 | vlv_pipe_has_vdd_on); | |
694 | /* didn't find one? pick one with just the correct port */ | |
695 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
696 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
697 | vlv_pipe_any); | |
a4a5d2f8 VS |
698 | |
699 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ | |
700 | if (intel_dp->pps_pipe == INVALID_PIPE) { | |
701 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", | |
702 | port_name(port)); | |
703 | return; | |
bf13e81b JN |
704 | } |
705 | ||
a4a5d2f8 VS |
706 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
707 | port_name(port), pipe_name(intel_dp->pps_pipe)); | |
708 | ||
36b5f425 | 709 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
5d5ab2d2 | 710 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false); |
bf13e81b JN |
711 | } |
712 | ||
78597996 | 713 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) |
773538e8 | 714 | { |
91c8a326 | 715 | struct drm_device *dev = &dev_priv->drm; |
773538e8 VS |
716 | struct intel_encoder *encoder; |
717 | ||
920a14b2 | 718 | if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 719 | !IS_GEN9_LP(dev_priv))) |
773538e8 VS |
720 | return; |
721 | ||
722 | /* | |
723 | * We can't grab pps_mutex here due to deadlock with power_domain | |
724 | * mutex when power_domain functions are called while holding pps_mutex. | |
725 | * That also means that in order to use pps_pipe the code needs to | |
726 | * hold both a power domain reference and pps_mutex, and the power domain | |
727 | * reference get/put must be done while _not_ holding pps_mutex. | |
728 | * pps_{lock,unlock}() do these steps in the correct order, so one | |
729 | * should use them always. | |
730 | */ | |
731 | ||
19c8054c | 732 | for_each_intel_encoder(dev, encoder) { |
773538e8 VS |
733 | struct intel_dp *intel_dp; |
734 | ||
9f2bdb00 VS |
735 | if (encoder->type != INTEL_OUTPUT_DP && |
736 | encoder->type != INTEL_OUTPUT_EDP) | |
773538e8 VS |
737 | continue; |
738 | ||
739 | intel_dp = enc_to_intel_dp(&encoder->base); | |
9f2bdb00 VS |
740 | |
741 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); | |
742 | ||
743 | if (encoder->type != INTEL_OUTPUT_EDP) | |
744 | continue; | |
745 | ||
cc3f90f0 | 746 | if (IS_GEN9_LP(dev_priv)) |
78597996 ID |
747 | intel_dp->pps_reset = true; |
748 | else | |
749 | intel_dp->pps_pipe = INVALID_PIPE; | |
773538e8 | 750 | } |
bf13e81b JN |
751 | } |
752 | ||
8e8232d5 ID |
753 | struct pps_registers { |
754 | i915_reg_t pp_ctrl; | |
755 | i915_reg_t pp_stat; | |
756 | i915_reg_t pp_on; | |
757 | i915_reg_t pp_off; | |
758 | i915_reg_t pp_div; | |
759 | }; | |
760 | ||
761 | static void intel_pps_get_registers(struct drm_i915_private *dev_priv, | |
762 | struct intel_dp *intel_dp, | |
763 | struct pps_registers *regs) | |
764 | { | |
44cb734c ID |
765 | int pps_idx = 0; |
766 | ||
8e8232d5 ID |
767 | memset(regs, 0, sizeof(*regs)); |
768 | ||
cc3f90f0 | 769 | if (IS_GEN9_LP(dev_priv)) |
44cb734c ID |
770 | pps_idx = bxt_power_sequencer_idx(intel_dp); |
771 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
772 | pps_idx = vlv_power_sequencer_pipe(intel_dp); | |
8e8232d5 | 773 | |
44cb734c ID |
774 | regs->pp_ctrl = PP_CONTROL(pps_idx); |
775 | regs->pp_stat = PP_STATUS(pps_idx); | |
776 | regs->pp_on = PP_ON_DELAYS(pps_idx); | |
777 | regs->pp_off = PP_OFF_DELAYS(pps_idx); | |
cc3f90f0 | 778 | if (!IS_GEN9_LP(dev_priv)) |
44cb734c | 779 | regs->pp_div = PP_DIVISOR(pps_idx); |
8e8232d5 ID |
780 | } |
781 | ||
f0f59a00 VS |
782 | static i915_reg_t |
783 | _pp_ctrl_reg(struct intel_dp *intel_dp) | |
bf13e81b | 784 | { |
8e8232d5 | 785 | struct pps_registers regs; |
bf13e81b | 786 | |
8e8232d5 ID |
787 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
788 | ®s); | |
789 | ||
790 | return regs.pp_ctrl; | |
bf13e81b JN |
791 | } |
792 | ||
f0f59a00 VS |
793 | static i915_reg_t |
794 | _pp_stat_reg(struct intel_dp *intel_dp) | |
bf13e81b | 795 | { |
8e8232d5 | 796 | struct pps_registers regs; |
bf13e81b | 797 | |
8e8232d5 ID |
798 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
799 | ®s); | |
800 | ||
801 | return regs.pp_stat; | |
bf13e81b JN |
802 | } |
803 | ||
01527b31 CT |
804 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
805 | This function only applicable when panel PM state is not to be tracked */ | |
806 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, | |
807 | void *unused) | |
808 | { | |
809 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), | |
810 | edp_notifier); | |
811 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 812 | struct drm_i915_private *dev_priv = to_i915(dev); |
01527b31 CT |
813 | |
814 | if (!is_edp(intel_dp) || code != SYS_RESTART) | |
815 | return 0; | |
816 | ||
773538e8 | 817 | pps_lock(intel_dp); |
e39b999a | 818 | |
920a14b2 | 819 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e39b999a | 820 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
f0f59a00 | 821 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
649636ef | 822 | u32 pp_div; |
e39b999a | 823 | |
44cb734c ID |
824 | pp_ctrl_reg = PP_CONTROL(pipe); |
825 | pp_div_reg = PP_DIVISOR(pipe); | |
01527b31 CT |
826 | pp_div = I915_READ(pp_div_reg); |
827 | pp_div &= PP_REFERENCE_DIVIDER_MASK; | |
828 | ||
829 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ | |
830 | I915_WRITE(pp_div_reg, pp_div | 0x1F); | |
831 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); | |
832 | msleep(intel_dp->panel_power_cycle_delay); | |
833 | } | |
834 | ||
773538e8 | 835 | pps_unlock(intel_dp); |
e39b999a | 836 | |
01527b31 CT |
837 | return 0; |
838 | } | |
839 | ||
4be73780 | 840 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 841 | { |
30add22d | 842 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 843 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 844 | |
e39b999a VS |
845 | lockdep_assert_held(&dev_priv->pps_mutex); |
846 | ||
920a14b2 | 847 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
848 | intel_dp->pps_pipe == INVALID_PIPE) |
849 | return false; | |
850 | ||
bf13e81b | 851 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
852 | } |
853 | ||
4be73780 | 854 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 855 | { |
30add22d | 856 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 857 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 858 | |
e39b999a VS |
859 | lockdep_assert_held(&dev_priv->pps_mutex); |
860 | ||
920a14b2 | 861 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
862 | intel_dp->pps_pipe == INVALID_PIPE) |
863 | return false; | |
864 | ||
773538e8 | 865 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
ebf33b18 KP |
866 | } |
867 | ||
9b984dae KP |
868 | static void |
869 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
870 | { | |
30add22d | 871 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 872 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 873 | |
9b984dae KP |
874 | if (!is_edp(intel_dp)) |
875 | return; | |
453c5420 | 876 | |
4be73780 | 877 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
878 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
879 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
880 | I915_READ(_pp_stat_reg(intel_dp)), |
881 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
882 | } |
883 | } | |
884 | ||
9ee32fea DV |
885 | static uint32_t |
886 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
887 | { | |
888 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
889 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 890 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 891 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
892 | uint32_t status; |
893 | bool done; | |
894 | ||
ef04f00d | 895 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 896 | if (has_aux_irq) |
b18ac466 | 897 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 898 | msecs_to_jiffies_timeout(10)); |
9ee32fea | 899 | else |
713a6b66 | 900 | done = wait_for(C, 10) == 0; |
9ee32fea DV |
901 | if (!done) |
902 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
903 | has_aux_irq); | |
904 | #undef C | |
905 | ||
906 | return status; | |
907 | } | |
908 | ||
6ffb1be7 | 909 | static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 910 | { |
174edf1f | 911 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
e7dc33f3 | 912 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
9ee32fea | 913 | |
a457f54b VS |
914 | if (index) |
915 | return 0; | |
916 | ||
ec5b01dd DL |
917 | /* |
918 | * The clock divider is based off the hrawclk, and would like to run at | |
a457f54b | 919 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
a4fc5ed6 | 920 | */ |
a457f54b | 921 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
ec5b01dd DL |
922 | } |
923 | ||
924 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
925 | { | |
926 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 927 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd DL |
928 | |
929 | if (index) | |
930 | return 0; | |
931 | ||
a457f54b VS |
932 | /* |
933 | * The clock divider is based off the cdclk or PCH rawclk, and would | |
934 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and | |
935 | * divide by 2000 and use that | |
936 | */ | |
e7dc33f3 | 937 | if (intel_dig_port->port == PORT_A) |
49cd97a3 | 938 | return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000); |
e7dc33f3 VS |
939 | else |
940 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); | |
ec5b01dd DL |
941 | } |
942 | ||
943 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
944 | { | |
945 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 946 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd | 947 | |
a457f54b | 948 | if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { |
2c55c336 | 949 | /* Workaround for non-ULT HSW */ |
bc86625a CW |
950 | switch (index) { |
951 | case 0: return 63; | |
952 | case 1: return 72; | |
953 | default: return 0; | |
954 | } | |
2c55c336 | 955 | } |
a457f54b VS |
956 | |
957 | return ilk_get_aux_clock_divider(intel_dp, index); | |
b84a1cf8 RV |
958 | } |
959 | ||
b6b5e383 DL |
960 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
961 | { | |
962 | /* | |
963 | * SKL doesn't need us to program the AUX clock divider (Hardware will | |
964 | * derive the clock from CDCLK automatically). We still implement the | |
965 | * get_aux_clock_divider vfunc to plug-in into the existing code. | |
966 | */ | |
967 | return index ? 0 : 1; | |
968 | } | |
969 | ||
6ffb1be7 VS |
970 | static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
971 | bool has_aux_irq, | |
972 | int send_bytes, | |
973 | uint32_t aux_clock_divider) | |
5ed12a19 DL |
974 | { |
975 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
8652744b TU |
976 | struct drm_i915_private *dev_priv = |
977 | to_i915(intel_dig_port->base.base.dev); | |
5ed12a19 DL |
978 | uint32_t precharge, timeout; |
979 | ||
8652744b | 980 | if (IS_GEN6(dev_priv)) |
5ed12a19 DL |
981 | precharge = 3; |
982 | else | |
983 | precharge = 5; | |
984 | ||
8652744b | 985 | if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A) |
5ed12a19 DL |
986 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
987 | else | |
988 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
989 | ||
990 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 991 | DP_AUX_CH_CTL_DONE | |
5ed12a19 | 992 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
788d4433 | 993 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 994 | timeout | |
788d4433 | 995 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
996 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
997 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 998 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
999 | } |
1000 | ||
b9ca5fad DL |
1001 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
1002 | bool has_aux_irq, | |
1003 | int send_bytes, | |
1004 | uint32_t unused) | |
1005 | { | |
1006 | return DP_AUX_CH_CTL_SEND_BUSY | | |
1007 | DP_AUX_CH_CTL_DONE | | |
1008 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | | |
1009 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
1010 | DP_AUX_CH_CTL_TIME_OUT_1600us | | |
1011 | DP_AUX_CH_CTL_RECEIVE_ERROR | | |
1012 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
d4dcbdce | 1013 | DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | |
b9ca5fad DL |
1014 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
1015 | } | |
1016 | ||
b84a1cf8 RV |
1017 | static int |
1018 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
bd9f74a5 | 1019 | const uint8_t *send, int send_bytes, |
b84a1cf8 RV |
1020 | uint8_t *recv, int recv_size) |
1021 | { | |
1022 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
0031fb96 TU |
1023 | struct drm_i915_private *dev_priv = |
1024 | to_i915(intel_dig_port->base.base.dev); | |
f0f59a00 | 1025 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
bc86625a | 1026 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
1027 | int i, ret, recv_bytes; |
1028 | uint32_t status; | |
5ed12a19 | 1029 | int try, clock = 0; |
0031fb96 | 1030 | bool has_aux_irq = HAS_AUX_IRQ(dev_priv); |
884f19e9 JN |
1031 | bool vdd; |
1032 | ||
773538e8 | 1033 | pps_lock(intel_dp); |
e39b999a | 1034 | |
72c3500a VS |
1035 | /* |
1036 | * We will be called with VDD already enabled for dpcd/edid/oui reads. | |
1037 | * In such cases we want to leave VDD enabled and it's up to upper layers | |
1038 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off | |
1039 | * ourselves. | |
1040 | */ | |
1e0560e0 | 1041 | vdd = edp_panel_vdd_on(intel_dp); |
b84a1cf8 RV |
1042 | |
1043 | /* dp aux is extremely sensitive to irq latency, hence request the | |
1044 | * lowest possible wakeup latency and so prevent the cpu from going into | |
1045 | * deep sleep states. | |
1046 | */ | |
1047 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
1048 | ||
1049 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 1050 | |
11bee43e JB |
1051 | /* Try to wait for any previous AUX channel activity */ |
1052 | for (try = 0; try < 3; try++) { | |
ef04f00d | 1053 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
1054 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
1055 | break; | |
1056 | msleep(1); | |
1057 | } | |
1058 | ||
1059 | if (try == 3) { | |
02196c77 MK |
1060 | static u32 last_status = -1; |
1061 | const u32 status = I915_READ(ch_ctl); | |
1062 | ||
1063 | if (status != last_status) { | |
1064 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
1065 | status); | |
1066 | last_status = status; | |
1067 | } | |
1068 | ||
9ee32fea DV |
1069 | ret = -EBUSY; |
1070 | goto out; | |
4f7f7b7e CW |
1071 | } |
1072 | ||
46a5ae9f PZ |
1073 | /* Only 5 data registers! */ |
1074 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
1075 | ret = -E2BIG; | |
1076 | goto out; | |
1077 | } | |
1078 | ||
ec5b01dd | 1079 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
153b1100 DL |
1080 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
1081 | has_aux_irq, | |
1082 | send_bytes, | |
1083 | aux_clock_divider); | |
5ed12a19 | 1084 | |
bc86625a CW |
1085 | /* Must try at least 3 times according to DP spec */ |
1086 | for (try = 0; try < 5; try++) { | |
1087 | /* Load the send data into the aux channel data registers */ | |
1088 | for (i = 0; i < send_bytes; i += 4) | |
330e20ec | 1089 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
a4f1289e RV |
1090 | intel_dp_pack_aux(send + i, |
1091 | send_bytes - i)); | |
bc86625a CW |
1092 | |
1093 | /* Send the command and wait for it to complete */ | |
5ed12a19 | 1094 | I915_WRITE(ch_ctl, send_ctl); |
bc86625a CW |
1095 | |
1096 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
1097 | ||
1098 | /* Clear done status and any errors */ | |
1099 | I915_WRITE(ch_ctl, | |
1100 | status | | |
1101 | DP_AUX_CH_CTL_DONE | | |
1102 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
1103 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
1104 | ||
74ebf294 | 1105 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
bc86625a | 1106 | continue; |
74ebf294 TP |
1107 | |
1108 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 | |
1109 | * 400us delay required for errors and timeouts | |
1110 | * Timeout errors from the HW already meet this | |
1111 | * requirement so skip to next iteration | |
1112 | */ | |
1113 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { | |
1114 | usleep_range(400, 500); | |
bc86625a | 1115 | continue; |
74ebf294 | 1116 | } |
bc86625a | 1117 | if (status & DP_AUX_CH_CTL_DONE) |
e058c945 | 1118 | goto done; |
bc86625a | 1119 | } |
a4fc5ed6 KP |
1120 | } |
1121 | ||
a4fc5ed6 | 1122 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 1123 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
1124 | ret = -EBUSY; |
1125 | goto out; | |
a4fc5ed6 KP |
1126 | } |
1127 | ||
e058c945 | 1128 | done: |
a4fc5ed6 KP |
1129 | /* Check for timeout or receive error. |
1130 | * Timeouts occur when the sink is not connected | |
1131 | */ | |
a5b3da54 | 1132 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 1133 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
1134 | ret = -EIO; |
1135 | goto out; | |
a5b3da54 | 1136 | } |
1ae8c0a5 KP |
1137 | |
1138 | /* Timeouts occur when the device isn't connected, so they're | |
1139 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 1140 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
a5570fe5 | 1141 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
1142 | ret = -ETIMEDOUT; |
1143 | goto out; | |
a4fc5ed6 KP |
1144 | } |
1145 | ||
1146 | /* Unload any bytes sent back from the other side */ | |
1147 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
1148 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
14e01889 RV |
1149 | |
1150 | /* | |
1151 | * By BSpec: "Message sizes of 0 or >20 are not allowed." | |
1152 | * We have no idea of what happened so we return -EBUSY so | |
1153 | * drm layer takes care for the necessary retries. | |
1154 | */ | |
1155 | if (recv_bytes == 0 || recv_bytes > 20) { | |
1156 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", | |
1157 | recv_bytes); | |
1158 | /* | |
1159 | * FIXME: This patch was created on top of a series that | |
1160 | * organize the retries at drm level. There EBUSY should | |
1161 | * also take care for 1ms wait before retrying. | |
1162 | * That aux retries re-org is still needed and after that is | |
1163 | * merged we remove this sleep from here. | |
1164 | */ | |
1165 | usleep_range(1000, 1500); | |
1166 | ret = -EBUSY; | |
1167 | goto out; | |
1168 | } | |
1169 | ||
a4fc5ed6 KP |
1170 | if (recv_bytes > recv_size) |
1171 | recv_bytes = recv_size; | |
0206e353 | 1172 | |
4f7f7b7e | 1173 | for (i = 0; i < recv_bytes; i += 4) |
330e20ec | 1174 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
a4f1289e | 1175 | recv + i, recv_bytes - i); |
a4fc5ed6 | 1176 | |
9ee32fea DV |
1177 | ret = recv_bytes; |
1178 | out: | |
1179 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
1180 | ||
884f19e9 JN |
1181 | if (vdd) |
1182 | edp_panel_vdd_off(intel_dp, false); | |
1183 | ||
773538e8 | 1184 | pps_unlock(intel_dp); |
e39b999a | 1185 | |
9ee32fea | 1186 | return ret; |
a4fc5ed6 KP |
1187 | } |
1188 | ||
a6c8aff0 JN |
1189 | #define BARE_ADDRESS_SIZE 3 |
1190 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
9d1a1031 JN |
1191 | static ssize_t |
1192 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 1193 | { |
9d1a1031 JN |
1194 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
1195 | uint8_t txbuf[20], rxbuf[20]; | |
1196 | size_t txsize, rxsize; | |
a4fc5ed6 | 1197 | int ret; |
a4fc5ed6 | 1198 | |
d2d9cbbd VS |
1199 | txbuf[0] = (msg->request << 4) | |
1200 | ((msg->address >> 16) & 0xf); | |
1201 | txbuf[1] = (msg->address >> 8) & 0xff; | |
9d1a1031 JN |
1202 | txbuf[2] = msg->address & 0xff; |
1203 | txbuf[3] = msg->size - 1; | |
46a5ae9f | 1204 | |
9d1a1031 JN |
1205 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
1206 | case DP_AUX_NATIVE_WRITE: | |
1207 | case DP_AUX_I2C_WRITE: | |
c1e74122 | 1208 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
a6c8aff0 | 1209 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
a1ddefd8 | 1210 | rxsize = 2; /* 0 or 1 data bytes */ |
f51a44b9 | 1211 | |
9d1a1031 JN |
1212 | if (WARN_ON(txsize > 20)) |
1213 | return -E2BIG; | |
a4fc5ed6 | 1214 | |
dd788090 VS |
1215 | WARN_ON(!msg->buffer != !msg->size); |
1216 | ||
d81a67cc ID |
1217 | if (msg->buffer) |
1218 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); | |
a4fc5ed6 | 1219 | |
9d1a1031 JN |
1220 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1221 | if (ret > 0) { | |
1222 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 1223 | |
a1ddefd8 JN |
1224 | if (ret > 1) { |
1225 | /* Number of bytes written in a short write. */ | |
1226 | ret = clamp_t(int, rxbuf[1], 0, msg->size); | |
1227 | } else { | |
1228 | /* Return payload size. */ | |
1229 | ret = msg->size; | |
1230 | } | |
9d1a1031 JN |
1231 | } |
1232 | break; | |
46a5ae9f | 1233 | |
9d1a1031 JN |
1234 | case DP_AUX_NATIVE_READ: |
1235 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 1236 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 1237 | rxsize = msg->size + 1; |
a4fc5ed6 | 1238 | |
9d1a1031 JN |
1239 | if (WARN_ON(rxsize > 20)) |
1240 | return -E2BIG; | |
a4fc5ed6 | 1241 | |
9d1a1031 JN |
1242 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1243 | if (ret > 0) { | |
1244 | msg->reply = rxbuf[0] >> 4; | |
1245 | /* | |
1246 | * Assume happy day, and copy the data. The caller is | |
1247 | * expected to check msg->reply before touching it. | |
1248 | * | |
1249 | * Return payload size. | |
1250 | */ | |
1251 | ret--; | |
1252 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 1253 | } |
9d1a1031 JN |
1254 | break; |
1255 | ||
1256 | default: | |
1257 | ret = -EINVAL; | |
1258 | break; | |
a4fc5ed6 | 1259 | } |
f51a44b9 | 1260 | |
9d1a1031 | 1261 | return ret; |
a4fc5ed6 KP |
1262 | } |
1263 | ||
8f7ce038 VS |
1264 | static enum port intel_aux_port(struct drm_i915_private *dev_priv, |
1265 | enum port port) | |
1266 | { | |
1267 | const struct ddi_vbt_port_info *info = | |
1268 | &dev_priv->vbt.ddi_port_info[port]; | |
1269 | enum port aux_port; | |
1270 | ||
1271 | if (!info->alternate_aux_channel) { | |
1272 | DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n", | |
1273 | port_name(port), port_name(port)); | |
1274 | return port; | |
1275 | } | |
1276 | ||
1277 | switch (info->alternate_aux_channel) { | |
1278 | case DP_AUX_A: | |
1279 | aux_port = PORT_A; | |
1280 | break; | |
1281 | case DP_AUX_B: | |
1282 | aux_port = PORT_B; | |
1283 | break; | |
1284 | case DP_AUX_C: | |
1285 | aux_port = PORT_C; | |
1286 | break; | |
1287 | case DP_AUX_D: | |
1288 | aux_port = PORT_D; | |
1289 | break; | |
1290 | default: | |
1291 | MISSING_CASE(info->alternate_aux_channel); | |
1292 | aux_port = PORT_A; | |
1293 | break; | |
1294 | } | |
1295 | ||
1296 | DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n", | |
1297 | port_name(aux_port), port_name(port)); | |
1298 | ||
1299 | return aux_port; | |
1300 | } | |
1301 | ||
f0f59a00 | 1302 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1303 | enum port port) |
da00bdcf VS |
1304 | { |
1305 | switch (port) { | |
1306 | case PORT_B: | |
1307 | case PORT_C: | |
1308 | case PORT_D: | |
1309 | return DP_AUX_CH_CTL(port); | |
1310 | default: | |
1311 | MISSING_CASE(port); | |
1312 | return DP_AUX_CH_CTL(PORT_B); | |
1313 | } | |
1314 | } | |
1315 | ||
f0f59a00 | 1316 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1317 | enum port port, int index) |
330e20ec VS |
1318 | { |
1319 | switch (port) { | |
1320 | case PORT_B: | |
1321 | case PORT_C: | |
1322 | case PORT_D: | |
1323 | return DP_AUX_CH_DATA(port, index); | |
1324 | default: | |
1325 | MISSING_CASE(port); | |
1326 | return DP_AUX_CH_DATA(PORT_B, index); | |
1327 | } | |
1328 | } | |
1329 | ||
f0f59a00 | 1330 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1331 | enum port port) |
da00bdcf VS |
1332 | { |
1333 | switch (port) { | |
1334 | case PORT_A: | |
1335 | return DP_AUX_CH_CTL(port); | |
1336 | case PORT_B: | |
1337 | case PORT_C: | |
1338 | case PORT_D: | |
1339 | return PCH_DP_AUX_CH_CTL(port); | |
1340 | default: | |
1341 | MISSING_CASE(port); | |
1342 | return DP_AUX_CH_CTL(PORT_A); | |
1343 | } | |
1344 | } | |
1345 | ||
f0f59a00 | 1346 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1347 | enum port port, int index) |
330e20ec VS |
1348 | { |
1349 | switch (port) { | |
1350 | case PORT_A: | |
1351 | return DP_AUX_CH_DATA(port, index); | |
1352 | case PORT_B: | |
1353 | case PORT_C: | |
1354 | case PORT_D: | |
1355 | return PCH_DP_AUX_CH_DATA(port, index); | |
1356 | default: | |
1357 | MISSING_CASE(port); | |
1358 | return DP_AUX_CH_DATA(PORT_A, index); | |
1359 | } | |
1360 | } | |
1361 | ||
f0f59a00 | 1362 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1363 | enum port port) |
da00bdcf | 1364 | { |
da00bdcf VS |
1365 | switch (port) { |
1366 | case PORT_A: | |
1367 | case PORT_B: | |
1368 | case PORT_C: | |
1369 | case PORT_D: | |
1370 | return DP_AUX_CH_CTL(port); | |
1371 | default: | |
1372 | MISSING_CASE(port); | |
1373 | return DP_AUX_CH_CTL(PORT_A); | |
1374 | } | |
1375 | } | |
1376 | ||
f0f59a00 | 1377 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1378 | enum port port, int index) |
330e20ec | 1379 | { |
330e20ec VS |
1380 | switch (port) { |
1381 | case PORT_A: | |
1382 | case PORT_B: | |
1383 | case PORT_C: | |
1384 | case PORT_D: | |
1385 | return DP_AUX_CH_DATA(port, index); | |
1386 | default: | |
1387 | MISSING_CASE(port); | |
1388 | return DP_AUX_CH_DATA(PORT_A, index); | |
1389 | } | |
1390 | } | |
1391 | ||
f0f59a00 | 1392 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1393 | enum port port) |
330e20ec VS |
1394 | { |
1395 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1396 | return skl_aux_ctl_reg(dev_priv, port); | |
1397 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1398 | return ilk_aux_ctl_reg(dev_priv, port); | |
1399 | else | |
1400 | return g4x_aux_ctl_reg(dev_priv, port); | |
1401 | } | |
1402 | ||
f0f59a00 | 1403 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1404 | enum port port, int index) |
330e20ec VS |
1405 | { |
1406 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1407 | return skl_aux_data_reg(dev_priv, port, index); | |
1408 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1409 | return ilk_aux_data_reg(dev_priv, port, index); | |
1410 | else | |
1411 | return g4x_aux_data_reg(dev_priv, port, index); | |
1412 | } | |
1413 | ||
1414 | static void intel_aux_reg_init(struct intel_dp *intel_dp) | |
1415 | { | |
1416 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); | |
8f7ce038 VS |
1417 | enum port port = intel_aux_port(dev_priv, |
1418 | dp_to_dig_port(intel_dp)->port); | |
330e20ec VS |
1419 | int i; |
1420 | ||
1421 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); | |
1422 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) | |
1423 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); | |
1424 | } | |
1425 | ||
9d1a1031 | 1426 | static void |
a121f4e5 VS |
1427 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
1428 | { | |
a121f4e5 VS |
1429 | kfree(intel_dp->aux.name); |
1430 | } | |
1431 | ||
7a418e34 | 1432 | static void |
b6339585 | 1433 | intel_dp_aux_init(struct intel_dp *intel_dp) |
9d1a1031 | 1434 | { |
33ad6626 JN |
1435 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1436 | enum port port = intel_dig_port->port; | |
ab2c0672 | 1437 | |
330e20ec | 1438 | intel_aux_reg_init(intel_dp); |
7a418e34 | 1439 | drm_dp_aux_init(&intel_dp->aux); |
8316f337 | 1440 | |
7a418e34 | 1441 | /* Failure to allocate our preferred name is not critical */ |
a121f4e5 | 1442 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
9d1a1031 | 1443 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
a4fc5ed6 KP |
1444 | } |
1445 | ||
e588fa18 | 1446 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
ed63baaf | 1447 | { |
e588fa18 | 1448 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
577c5430 | 1449 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
e588fa18 | 1450 | |
577c5430 NM |
1451 | if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || |
1452 | IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9)) | |
ed63baaf TS |
1453 | return true; |
1454 | else | |
1455 | return false; | |
1456 | } | |
1457 | ||
c6bb3538 DV |
1458 | static void |
1459 | intel_dp_set_clock(struct intel_encoder *encoder, | |
840b32b7 | 1460 | struct intel_crtc_state *pipe_config) |
c6bb3538 DV |
1461 | { |
1462 | struct drm_device *dev = encoder->base.dev; | |
6e266956 | 1463 | struct drm_i915_private *dev_priv = to_i915(dev); |
9dd4ffdf CML |
1464 | const struct dp_link_dpll *divisor = NULL; |
1465 | int i, count = 0; | |
c6bb3538 | 1466 | |
9beb5fea | 1467 | if (IS_G4X(dev_priv)) { |
9dd4ffdf CML |
1468 | divisor = gen4_dpll; |
1469 | count = ARRAY_SIZE(gen4_dpll); | |
6e266956 | 1470 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
9dd4ffdf CML |
1471 | divisor = pch_dpll; |
1472 | count = ARRAY_SIZE(pch_dpll); | |
920a14b2 | 1473 | } else if (IS_CHERRYVIEW(dev_priv)) { |
ef9348c8 CML |
1474 | divisor = chv_dpll; |
1475 | count = ARRAY_SIZE(chv_dpll); | |
11a914c2 | 1476 | } else if (IS_VALLEYVIEW(dev_priv)) { |
65ce4bf5 CML |
1477 | divisor = vlv_dpll; |
1478 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 1479 | } |
9dd4ffdf CML |
1480 | |
1481 | if (divisor && count) { | |
1482 | for (i = 0; i < count; i++) { | |
840b32b7 | 1483 | if (pipe_config->port_clock == divisor[i].clock) { |
9dd4ffdf CML |
1484 | pipe_config->dpll = divisor[i].dpll; |
1485 | pipe_config->clock_set = true; | |
1486 | break; | |
1487 | } | |
1488 | } | |
c6bb3538 DV |
1489 | } |
1490 | } | |
1491 | ||
0336400e VS |
1492 | static void snprintf_int_array(char *str, size_t len, |
1493 | const int *array, int nelem) | |
1494 | { | |
1495 | int i; | |
1496 | ||
1497 | str[0] = '\0'; | |
1498 | ||
1499 | for (i = 0; i < nelem; i++) { | |
b2f505be | 1500 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
0336400e VS |
1501 | if (r >= len) |
1502 | return; | |
1503 | str += r; | |
1504 | len -= r; | |
1505 | } | |
1506 | } | |
1507 | ||
1508 | static void intel_dp_print_rates(struct intel_dp *intel_dp) | |
1509 | { | |
0336400e VS |
1510 | char str[128]; /* FIXME: too big for stack? */ |
1511 | ||
1512 | if ((drm_debug & DRM_UT_KMS) == 0) | |
1513 | return; | |
1514 | ||
55cfc580 JN |
1515 | snprintf_int_array(str, sizeof(str), |
1516 | intel_dp->source_rates, intel_dp->num_source_rates); | |
0336400e VS |
1517 | DRM_DEBUG_KMS("source rates: %s\n", str); |
1518 | ||
68f357cb JN |
1519 | snprintf_int_array(str, sizeof(str), |
1520 | intel_dp->sink_rates, intel_dp->num_sink_rates); | |
0336400e VS |
1521 | DRM_DEBUG_KMS("sink rates: %s\n", str); |
1522 | ||
975ee5fc JN |
1523 | snprintf_int_array(str, sizeof(str), |
1524 | intel_dp->common_rates, intel_dp->num_common_rates); | |
94ca719e | 1525 | DRM_DEBUG_KMS("common rates: %s\n", str); |
0336400e VS |
1526 | } |
1527 | ||
489375c8 | 1528 | bool |
7b3fc170 | 1529 | __intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc) |
0e390a33 | 1530 | { |
7b3fc170 ID |
1531 | u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI : |
1532 | DP_SINK_OUI; | |
0e390a33 | 1533 | |
7b3fc170 ID |
1534 | return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) == |
1535 | sizeof(*desc); | |
0e390a33 MK |
1536 | } |
1537 | ||
12a47a42 | 1538 | bool intel_dp_read_desc(struct intel_dp *intel_dp) |
1a2724fa | 1539 | { |
7b3fc170 ID |
1540 | struct intel_dp_desc *desc = &intel_dp->desc; |
1541 | bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & | |
1542 | DP_OUI_SUPPORT; | |
1543 | int dev_id_len; | |
1a2724fa | 1544 | |
7b3fc170 ID |
1545 | if (!__intel_dp_read_desc(intel_dp, desc)) |
1546 | return false; | |
1a2724fa | 1547 | |
7b3fc170 ID |
1548 | dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id)); |
1549 | DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n", | |
1550 | drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink", | |
1551 | (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)", | |
1552 | dev_id_len, desc->device_id, | |
1553 | desc->hw_rev >> 4, desc->hw_rev & 0xf, | |
1554 | desc->sw_major_rev, desc->sw_minor_rev); | |
1a2724fa | 1555 | |
7b3fc170 | 1556 | return true; |
1a2724fa MK |
1557 | } |
1558 | ||
50fec21a VS |
1559 | int |
1560 | intel_dp_max_link_rate(struct intel_dp *intel_dp) | |
1561 | { | |
50fec21a VS |
1562 | int len; |
1563 | ||
975ee5fc JN |
1564 | len = intel_dp_common_len_rate_limit(intel_dp, |
1565 | intel_dp->max_sink_link_rate); | |
50fec21a VS |
1566 | if (WARN_ON(len <= 0)) |
1567 | return 162000; | |
1568 | ||
975ee5fc | 1569 | return intel_dp->common_rates[len - 1]; |
50fec21a VS |
1570 | } |
1571 | ||
ed4e9c1d VS |
1572 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1573 | { | |
8001b754 JN |
1574 | int i = intel_dp_rate_index(intel_dp->sink_rates, |
1575 | intel_dp->num_sink_rates, rate); | |
b5c72b20 JN |
1576 | |
1577 | if (WARN_ON(i < 0)) | |
1578 | i = 0; | |
1579 | ||
1580 | return i; | |
ed4e9c1d VS |
1581 | } |
1582 | ||
94223d04 ACO |
1583 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1584 | uint8_t *link_bw, uint8_t *rate_select) | |
04a60f9f | 1585 | { |
68f357cb JN |
1586 | /* eDP 1.4 rate select method. */ |
1587 | if (intel_dp->use_rate_select) { | |
04a60f9f VS |
1588 | *link_bw = 0; |
1589 | *rate_select = | |
1590 | intel_dp_rate_select(intel_dp, port_clock); | |
1591 | } else { | |
1592 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); | |
1593 | *rate_select = 0; | |
1594 | } | |
1595 | } | |
1596 | ||
f580bea9 JN |
1597 | static int intel_dp_compute_bpp(struct intel_dp *intel_dp, |
1598 | struct intel_crtc_state *pipe_config) | |
f9bb705e MK |
1599 | { |
1600 | int bpp, bpc; | |
1601 | ||
1602 | bpp = pipe_config->pipe_bpp; | |
1603 | bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports); | |
1604 | ||
1605 | if (bpc > 0) | |
1606 | bpp = min(bpp, 3*bpc); | |
1607 | ||
611032bf MN |
1608 | /* For DP Compliance we override the computed bpp for the pipe */ |
1609 | if (intel_dp->compliance.test_data.bpc != 0) { | |
1610 | pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc; | |
1611 | pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3; | |
1612 | DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", | |
1613 | pipe_config->pipe_bpp); | |
1614 | } | |
f9bb705e MK |
1615 | return bpp; |
1616 | } | |
1617 | ||
00c09d70 | 1618 | bool |
5bfe2ac0 | 1619 | intel_dp_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
1620 | struct intel_crtc_state *pipe_config, |
1621 | struct drm_connector_state *conn_state) | |
a4fc5ed6 | 1622 | { |
dd11bc10 | 1623 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2d112de7 | 1624 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
5bfe2ac0 | 1625 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1626 | enum port port = dp_to_dig_port(intel_dp)->port; |
84556d58 | 1627 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
dd06f90e | 1628 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
a4fc5ed6 | 1629 | int lane_count, clock; |
56071a20 | 1630 | int min_lane_count = 1; |
eeb6324d | 1631 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
06ea66b6 | 1632 | /* Conveniently, the link BW constants become indices with a shift...*/ |
56071a20 | 1633 | int min_clock = 0; |
a8f3ef61 | 1634 | int max_clock; |
da15f7cb | 1635 | int link_rate_index; |
083f9560 | 1636 | int bpp, mode_rate; |
ff9a6750 | 1637 | int link_avail, link_clock; |
94ca719e | 1638 | int common_len; |
04a60f9f | 1639 | uint8_t link_bw, rate_select; |
a8f3ef61 | 1640 | |
975ee5fc JN |
1641 | common_len = intel_dp_common_len_rate_limit(intel_dp, |
1642 | intel_dp->max_sink_link_rate); | |
a8f3ef61 SJ |
1643 | |
1644 | /* No common link rates between source and sink */ | |
94ca719e | 1645 | WARN_ON(common_len <= 0); |
a8f3ef61 | 1646 | |
94ca719e | 1647 | max_clock = common_len - 1; |
a4fc5ed6 | 1648 | |
4f8036a2 | 1649 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) |
5bfe2ac0 DV |
1650 | pipe_config->has_pch_encoder = true; |
1651 | ||
f769cd24 | 1652 | pipe_config->has_drrs = false; |
9fcb1704 | 1653 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
a4fc5ed6 | 1654 | |
dd06f90e JN |
1655 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
1656 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
1657 | adjusted_mode); | |
a1b2278e | 1658 | |
dd11bc10 | 1659 | if (INTEL_GEN(dev_priv) >= 9) { |
a1b2278e | 1660 | int ret; |
e435d6e5 | 1661 | ret = skl_update_scaler_crtc(pipe_config); |
a1b2278e CK |
1662 | if (ret) |
1663 | return ret; | |
1664 | } | |
1665 | ||
49cff963 | 1666 | if (HAS_GMCH_DISPLAY(dev_priv)) |
2dd24552 JB |
1667 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
1668 | intel_connector->panel.fitting_mode); | |
1669 | else | |
b074cec8 JB |
1670 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
1671 | intel_connector->panel.fitting_mode); | |
0d3a1bee ZY |
1672 | } |
1673 | ||
cb1793ce | 1674 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
1675 | return false; |
1676 | ||
da15f7cb MN |
1677 | /* Use values requested by Compliance Test Request */ |
1678 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { | |
b1810a74 JN |
1679 | link_rate_index = intel_dp_rate_index(intel_dp->common_rates, |
1680 | intel_dp->num_common_rates, | |
1681 | intel_dp->compliance.test_link_rate); | |
da15f7cb MN |
1682 | if (link_rate_index >= 0) |
1683 | min_clock = max_clock = link_rate_index; | |
1684 | min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count; | |
1685 | } | |
083f9560 | 1686 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
a8f3ef61 | 1687 | "max bw %d pixel clock %iKHz\n", |
975ee5fc | 1688 | max_lane_count, intel_dp->common_rates[max_clock], |
241bfc38 | 1689 | adjusted_mode->crtc_clock); |
083f9560 | 1690 | |
36008365 DV |
1691 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1692 | * bpc in between. */ | |
f9bb705e | 1693 | bpp = intel_dp_compute_bpp(intel_dp, pipe_config); |
56071a20 | 1694 | if (is_edp(intel_dp)) { |
22ce5628 TS |
1695 | |
1696 | /* Get bpp from vbt only for panels that dont have bpp in edid */ | |
1697 | if (intel_connector->base.display_info.bpc == 0 && | |
6aa23e65 | 1698 | (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { |
56071a20 | 1699 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
6aa23e65 JN |
1700 | dev_priv->vbt.edp.bpp); |
1701 | bpp = dev_priv->vbt.edp.bpp; | |
56071a20 JN |
1702 | } |
1703 | ||
344c5bbc JN |
1704 | /* |
1705 | * Use the maximum clock and number of lanes the eDP panel | |
1706 | * advertizes being capable of. The panels are generally | |
1707 | * designed to support only a single clock and lane | |
1708 | * configuration, and typically these values correspond to the | |
1709 | * native resolution of the panel. | |
1710 | */ | |
1711 | min_lane_count = max_lane_count; | |
1712 | min_clock = max_clock; | |
7984211e | 1713 | } |
657445fe | 1714 | |
36008365 | 1715 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
1716 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1717 | bpp); | |
36008365 | 1718 | |
c6930992 | 1719 | for (clock = min_clock; clock <= max_clock; clock++) { |
a8f3ef61 SJ |
1720 | for (lane_count = min_lane_count; |
1721 | lane_count <= max_lane_count; | |
1722 | lane_count <<= 1) { | |
1723 | ||
975ee5fc | 1724 | link_clock = intel_dp->common_rates[clock]; |
36008365 DV |
1725 | link_avail = intel_dp_max_data_rate(link_clock, |
1726 | lane_count); | |
1727 | ||
1728 | if (mode_rate <= link_avail) { | |
1729 | goto found; | |
1730 | } | |
1731 | } | |
1732 | } | |
1733 | } | |
c4867936 | 1734 | |
36008365 | 1735 | return false; |
3685a8f3 | 1736 | |
36008365 | 1737 | found: |
55bc60db VS |
1738 | if (intel_dp->color_range_auto) { |
1739 | /* | |
1740 | * See: | |
1741 | * CEA-861-E - 5.1 Default Encoding Parameters | |
1742 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
1743 | */ | |
0f2a2a75 | 1744 | pipe_config->limited_color_range = |
c8127cf0 VS |
1745 | bpp != 18 && |
1746 | drm_default_rgb_quant_range(adjusted_mode) == | |
1747 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
0f2a2a75 VS |
1748 | } else { |
1749 | pipe_config->limited_color_range = | |
1750 | intel_dp->limited_color_range; | |
55bc60db VS |
1751 | } |
1752 | ||
90a6b7b0 | 1753 | pipe_config->lane_count = lane_count; |
a8f3ef61 | 1754 | |
657445fe | 1755 | pipe_config->pipe_bpp = bpp; |
975ee5fc | 1756 | pipe_config->port_clock = intel_dp->common_rates[clock]; |
a4fc5ed6 | 1757 | |
04a60f9f VS |
1758 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
1759 | &link_bw, &rate_select); | |
1760 | ||
1761 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", | |
1762 | link_bw, rate_select, pipe_config->lane_count, | |
ff9a6750 | 1763 | pipe_config->port_clock, bpp); |
36008365 DV |
1764 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1765 | mode_rate, link_avail); | |
a4fc5ed6 | 1766 | |
03afc4a2 | 1767 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
1768 | adjusted_mode->crtc_clock, |
1769 | pipe_config->port_clock, | |
03afc4a2 | 1770 | &pipe_config->dp_m_n); |
9d1a455b | 1771 | |
439d7ac0 | 1772 | if (intel_connector->panel.downclock_mode != NULL && |
96178eeb | 1773 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
f769cd24 | 1774 | pipe_config->has_drrs = true; |
439d7ac0 PB |
1775 | intel_link_compute_m_n(bpp, lane_count, |
1776 | intel_connector->panel.downclock_mode->clock, | |
1777 | pipe_config->port_clock, | |
1778 | &pipe_config->dp_m2_n2); | |
1779 | } | |
1780 | ||
14d41b3b VS |
1781 | /* |
1782 | * DPLL0 VCO may need to be adjusted to get the correct | |
1783 | * clock for eDP. This will affect cdclk as well. | |
1784 | */ | |
b976dc53 | 1785 | if (is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) { |
14d41b3b VS |
1786 | int vco; |
1787 | ||
1788 | switch (pipe_config->port_clock / 2) { | |
1789 | case 108000: | |
1790 | case 216000: | |
63911d72 | 1791 | vco = 8640000; |
14d41b3b VS |
1792 | break; |
1793 | default: | |
63911d72 | 1794 | vco = 8100000; |
14d41b3b VS |
1795 | break; |
1796 | } | |
1797 | ||
bb0f4aab | 1798 | to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco; |
14d41b3b VS |
1799 | } |
1800 | ||
4f8036a2 | 1801 | if (!HAS_DDI(dev_priv)) |
840b32b7 | 1802 | intel_dp_set_clock(encoder, pipe_config); |
c6bb3538 | 1803 | |
03afc4a2 | 1804 | return true; |
a4fc5ed6 KP |
1805 | } |
1806 | ||
901c2daf | 1807 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
dfa10480 ACO |
1808 | int link_rate, uint8_t lane_count, |
1809 | bool link_mst) | |
901c2daf | 1810 | { |
dfa10480 ACO |
1811 | intel_dp->link_rate = link_rate; |
1812 | intel_dp->lane_count = lane_count; | |
1813 | intel_dp->link_mst = link_mst; | |
901c2daf VS |
1814 | } |
1815 | ||
85cb48a1 ML |
1816 | static void intel_dp_prepare(struct intel_encoder *encoder, |
1817 | struct intel_crtc_state *pipe_config) | |
a4fc5ed6 | 1818 | { |
b934223d | 1819 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1820 | struct drm_i915_private *dev_priv = to_i915(dev); |
b934223d | 1821 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1822 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d | 1823 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
85cb48a1 | 1824 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
a4fc5ed6 | 1825 | |
dfa10480 ACO |
1826 | intel_dp_set_link_params(intel_dp, pipe_config->port_clock, |
1827 | pipe_config->lane_count, | |
1828 | intel_crtc_has_type(pipe_config, | |
1829 | INTEL_OUTPUT_DP_MST)); | |
901c2daf | 1830 | |
417e822d | 1831 | /* |
1a2eb460 | 1832 | * There are four kinds of DP registers: |
417e822d KP |
1833 | * |
1834 | * IBX PCH | |
1a2eb460 KP |
1835 | * SNB CPU |
1836 | * IVB CPU | |
417e822d KP |
1837 | * CPT PCH |
1838 | * | |
1839 | * IBX PCH and CPU are the same for almost everything, | |
1840 | * except that the CPU DP PLL is configured in this | |
1841 | * register | |
1842 | * | |
1843 | * CPT PCH is quite different, having many bits moved | |
1844 | * to the TRANS_DP_CTL register instead. That | |
1845 | * configuration happens (oddly) in ironlake_pch_enable | |
1846 | */ | |
9c9e7927 | 1847 | |
417e822d KP |
1848 | /* Preserve the BIOS-computed detected bit. This is |
1849 | * supposed to be read-only. | |
1850 | */ | |
1851 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 1852 | |
417e822d | 1853 | /* Handle DP bits in common between all three register formats */ |
417e822d | 1854 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
85cb48a1 | 1855 | intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); |
a4fc5ed6 | 1856 | |
417e822d | 1857 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 1858 | |
5db94019 | 1859 | if (IS_GEN7(dev_priv) && port == PORT_A) { |
1a2eb460 KP |
1860 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1861 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1862 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1863 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1864 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
1865 | ||
6aba5b6c | 1866 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
1867 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1868 | ||
7c62a164 | 1869 | intel_dp->DP |= crtc->pipe << 29; |
6e266956 | 1870 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
e3ef4479 VS |
1871 | u32 trans_dp; |
1872 | ||
39e5fa88 | 1873 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3ef4479 VS |
1874 | |
1875 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
1876 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
1877 | trans_dp |= TRANS_DP_ENH_FRAMING; | |
1878 | else | |
1879 | trans_dp &= ~TRANS_DP_ENH_FRAMING; | |
1880 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); | |
39e5fa88 | 1881 | } else { |
c99f53f7 | 1882 | if (IS_G4X(dev_priv) && pipe_config->limited_color_range) |
0f2a2a75 | 1883 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
417e822d KP |
1884 | |
1885 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
1886 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1887 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1888 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1889 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
1890 | ||
6aba5b6c | 1891 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
1892 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1893 | ||
920a14b2 | 1894 | if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 1895 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
39e5fa88 VS |
1896 | else if (crtc->pipe == PIPE_B) |
1897 | intel_dp->DP |= DP_PIPEB_SELECT; | |
32f9d658 | 1898 | } |
a4fc5ed6 KP |
1899 | } |
1900 | ||
ffd6749d PZ |
1901 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1902 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 1903 | |
1a5ef5b7 PZ |
1904 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1905 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 1906 | |
ffd6749d PZ |
1907 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1908 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 1909 | |
de9c1b6b ID |
1910 | static void intel_pps_verify_state(struct drm_i915_private *dev_priv, |
1911 | struct intel_dp *intel_dp); | |
1912 | ||
4be73780 | 1913 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
1914 | u32 mask, |
1915 | u32 value) | |
bd943159 | 1916 | { |
30add22d | 1917 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 1918 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1919 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
453c5420 | 1920 | |
e39b999a VS |
1921 | lockdep_assert_held(&dev_priv->pps_mutex); |
1922 | ||
de9c1b6b ID |
1923 | intel_pps_verify_state(dev_priv, intel_dp); |
1924 | ||
bf13e81b JN |
1925 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1926 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 1927 | |
99ea7127 | 1928 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
1929 | mask, value, |
1930 | I915_READ(pp_stat_reg), | |
1931 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1932 | |
9036ff06 CW |
1933 | if (intel_wait_for_register(dev_priv, |
1934 | pp_stat_reg, mask, value, | |
1935 | 5000)) | |
99ea7127 | 1936 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
1937 | I915_READ(pp_stat_reg), |
1938 | I915_READ(pp_ctrl_reg)); | |
54c136d4 CW |
1939 | |
1940 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 1941 | } |
32ce697c | 1942 | |
4be73780 | 1943 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
1944 | { |
1945 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 1946 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
1947 | } |
1948 | ||
4be73780 | 1949 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
1950 | { |
1951 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 1952 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
1953 | } |
1954 | ||
4be73780 | 1955 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 | 1956 | { |
d28d4731 AK |
1957 | ktime_t panel_power_on_time; |
1958 | s64 panel_power_off_duration; | |
1959 | ||
99ea7127 | 1960 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
dce56b3c | 1961 | |
d28d4731 AK |
1962 | /* take the difference of currrent time and panel power off time |
1963 | * and then make panel wait for t11_t12 if needed. */ | |
1964 | panel_power_on_time = ktime_get_boottime(); | |
1965 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); | |
1966 | ||
dce56b3c PZ |
1967 | /* When we disable the VDD override bit last we have to do the manual |
1968 | * wait. */ | |
d28d4731 AK |
1969 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
1970 | wait_remaining_ms_from_jiffies(jiffies, | |
1971 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); | |
dce56b3c | 1972 | |
4be73780 | 1973 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
1974 | } |
1975 | ||
4be73780 | 1976 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
1977 | { |
1978 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
1979 | intel_dp->backlight_on_delay); | |
1980 | } | |
1981 | ||
4be73780 | 1982 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
1983 | { |
1984 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
1985 | intel_dp->backlight_off_delay); | |
1986 | } | |
99ea7127 | 1987 | |
832dd3c1 KP |
1988 | /* Read the current pp_control value, unlocking the register if it |
1989 | * is locked | |
1990 | */ | |
1991 | ||
453c5420 | 1992 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 1993 | { |
453c5420 | 1994 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 1995 | struct drm_i915_private *dev_priv = to_i915(dev); |
453c5420 | 1996 | u32 control; |
832dd3c1 | 1997 | |
e39b999a VS |
1998 | lockdep_assert_held(&dev_priv->pps_mutex); |
1999 | ||
bf13e81b | 2000 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
8090ba8c ID |
2001 | if (WARN_ON(!HAS_DDI(dev_priv) && |
2002 | (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { | |
b0a08bec VK |
2003 | control &= ~PANEL_UNLOCK_MASK; |
2004 | control |= PANEL_UNLOCK_REGS; | |
2005 | } | |
832dd3c1 | 2006 | return control; |
bd943159 KP |
2007 | } |
2008 | ||
951468f3 VS |
2009 | /* |
2010 | * Must be paired with edp_panel_vdd_off(). | |
2011 | * Must hold pps_mutex around the whole on/off sequence. | |
2012 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2013 | */ | |
1e0560e0 | 2014 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 2015 | { |
30add22d | 2016 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4e6e1a54 | 2017 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
fac5e23e | 2018 | struct drm_i915_private *dev_priv = to_i915(dev); |
5d613501 | 2019 | u32 pp; |
f0f59a00 | 2020 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 2021 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 2022 | |
e39b999a VS |
2023 | lockdep_assert_held(&dev_priv->pps_mutex); |
2024 | ||
97af61f5 | 2025 | if (!is_edp(intel_dp)) |
adddaaf4 | 2026 | return false; |
bd943159 | 2027 | |
2c623c11 | 2028 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
bd943159 | 2029 | intel_dp->want_panel_vdd = true; |
99ea7127 | 2030 | |
4be73780 | 2031 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 2032 | return need_to_disable; |
b0665d57 | 2033 | |
5432fcaf | 2034 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
e9cb81a2 | 2035 | |
3936fcf4 VS |
2036 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
2037 | port_name(intel_dig_port->port)); | |
bd943159 | 2038 | |
4be73780 DV |
2039 | if (!edp_have_panel_power(intel_dp)) |
2040 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 2041 | |
453c5420 | 2042 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 2043 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 2044 | |
bf13e81b JN |
2045 | pp_stat_reg = _pp_stat_reg(intel_dp); |
2046 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
2047 | |
2048 | I915_WRITE(pp_ctrl_reg, pp); | |
2049 | POSTING_READ(pp_ctrl_reg); | |
2050 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
2051 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
2052 | /* |
2053 | * If the panel wasn't on, delay before accessing aux channel | |
2054 | */ | |
4be73780 | 2055 | if (!edp_have_panel_power(intel_dp)) { |
3936fcf4 VS |
2056 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
2057 | port_name(intel_dig_port->port)); | |
f01eca2e | 2058 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 2059 | } |
adddaaf4 JN |
2060 | |
2061 | return need_to_disable; | |
2062 | } | |
2063 | ||
951468f3 VS |
2064 | /* |
2065 | * Must be paired with intel_edp_panel_vdd_off() or | |
2066 | * intel_edp_panel_off(). | |
2067 | * Nested calls to these functions are not allowed since | |
2068 | * we drop the lock. Caller must use some higher level | |
2069 | * locking to prevent nested calls from other threads. | |
2070 | */ | |
b80d6c78 | 2071 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 | 2072 | { |
c695b6b6 | 2073 | bool vdd; |
adddaaf4 | 2074 | |
c695b6b6 VS |
2075 | if (!is_edp(intel_dp)) |
2076 | return; | |
2077 | ||
773538e8 | 2078 | pps_lock(intel_dp); |
c695b6b6 | 2079 | vdd = edp_panel_vdd_on(intel_dp); |
773538e8 | 2080 | pps_unlock(intel_dp); |
c695b6b6 | 2081 | |
e2c719b7 | 2082 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
3936fcf4 | 2083 | port_name(dp_to_dig_port(intel_dp)->port)); |
5d613501 JB |
2084 | } |
2085 | ||
4be73780 | 2086 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 2087 | { |
30add22d | 2088 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2089 | struct drm_i915_private *dev_priv = to_i915(dev); |
be2c9196 VS |
2090 | struct intel_digital_port *intel_dig_port = |
2091 | dp_to_dig_port(intel_dp); | |
5d613501 | 2092 | u32 pp; |
f0f59a00 | 2093 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
5d613501 | 2094 | |
e39b999a | 2095 | lockdep_assert_held(&dev_priv->pps_mutex); |
a0e99e68 | 2096 | |
15e899a0 | 2097 | WARN_ON(intel_dp->want_panel_vdd); |
4e6e1a54 | 2098 | |
15e899a0 | 2099 | if (!edp_have_panel_vdd(intel_dp)) |
be2c9196 | 2100 | return; |
b0665d57 | 2101 | |
3936fcf4 VS |
2102 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
2103 | port_name(intel_dig_port->port)); | |
bd943159 | 2104 | |
be2c9196 VS |
2105 | pp = ironlake_get_pp_control(intel_dp); |
2106 | pp &= ~EDP_FORCE_VDD; | |
453c5420 | 2107 | |
be2c9196 VS |
2108 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2109 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
99ea7127 | 2110 | |
be2c9196 VS |
2111 | I915_WRITE(pp_ctrl_reg, pp); |
2112 | POSTING_READ(pp_ctrl_reg); | |
90791a5c | 2113 | |
be2c9196 VS |
2114 | /* Make sure sequencer is idle before allowing subsequent activity */ |
2115 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
2116 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
e9cb81a2 | 2117 | |
5a162e22 | 2118 | if ((pp & PANEL_POWER_ON) == 0) |
d28d4731 | 2119 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
e9cb81a2 | 2120 | |
5432fcaf | 2121 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
bd943159 | 2122 | } |
5d613501 | 2123 | |
4be73780 | 2124 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
2125 | { |
2126 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
2127 | struct intel_dp, panel_vdd_work); | |
bd943159 | 2128 | |
773538e8 | 2129 | pps_lock(intel_dp); |
15e899a0 VS |
2130 | if (!intel_dp->want_panel_vdd) |
2131 | edp_panel_vdd_off_sync(intel_dp); | |
773538e8 | 2132 | pps_unlock(intel_dp); |
bd943159 KP |
2133 | } |
2134 | ||
aba86890 ID |
2135 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
2136 | { | |
2137 | unsigned long delay; | |
2138 | ||
2139 | /* | |
2140 | * Queue the timer to fire a long time from now (relative to the power | |
2141 | * down delay) to keep the panel power up across a sequence of | |
2142 | * operations. | |
2143 | */ | |
2144 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); | |
2145 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); | |
2146 | } | |
2147 | ||
951468f3 VS |
2148 | /* |
2149 | * Must be paired with edp_panel_vdd_on(). | |
2150 | * Must hold pps_mutex around the whole on/off sequence. | |
2151 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2152 | */ | |
4be73780 | 2153 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 2154 | { |
fac5e23e | 2155 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
e39b999a VS |
2156 | |
2157 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2158 | ||
97af61f5 KP |
2159 | if (!is_edp(intel_dp)) |
2160 | return; | |
5d613501 | 2161 | |
e2c719b7 | 2162 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
3936fcf4 | 2163 | port_name(dp_to_dig_port(intel_dp)->port)); |
f2e8b18a | 2164 | |
bd943159 KP |
2165 | intel_dp->want_panel_vdd = false; |
2166 | ||
aba86890 | 2167 | if (sync) |
4be73780 | 2168 | edp_panel_vdd_off_sync(intel_dp); |
aba86890 ID |
2169 | else |
2170 | edp_panel_vdd_schedule_off(intel_dp); | |
5d613501 JB |
2171 | } |
2172 | ||
9f0fb5be | 2173 | static void edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 2174 | { |
30add22d | 2175 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2176 | struct drm_i915_private *dev_priv = to_i915(dev); |
99ea7127 | 2177 | u32 pp; |
f0f59a00 | 2178 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2179 | |
9f0fb5be VS |
2180 | lockdep_assert_held(&dev_priv->pps_mutex); |
2181 | ||
97af61f5 | 2182 | if (!is_edp(intel_dp)) |
bd943159 | 2183 | return; |
99ea7127 | 2184 | |
3936fcf4 VS |
2185 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
2186 | port_name(dp_to_dig_port(intel_dp)->port)); | |
e39b999a | 2187 | |
e7a89ace VS |
2188 | if (WARN(edp_have_panel_power(intel_dp), |
2189 | "eDP port %c panel power already on\n", | |
2190 | port_name(dp_to_dig_port(intel_dp)->port))) | |
9f0fb5be | 2191 | return; |
9934c132 | 2192 | |
4be73780 | 2193 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 2194 | |
bf13e81b | 2195 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2196 | pp = ironlake_get_pp_control(intel_dp); |
5db94019 | 2197 | if (IS_GEN5(dev_priv)) { |
05ce1a49 KP |
2198 | /* ILK workaround: disable reset around power sequence */ |
2199 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
2200 | I915_WRITE(pp_ctrl_reg, pp); |
2201 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2202 | } |
37c6c9b0 | 2203 | |
5a162e22 | 2204 | pp |= PANEL_POWER_ON; |
5db94019 | 2205 | if (!IS_GEN5(dev_priv)) |
99ea7127 KP |
2206 | pp |= PANEL_POWER_RESET; |
2207 | ||
453c5420 JB |
2208 | I915_WRITE(pp_ctrl_reg, pp); |
2209 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2210 | |
4be73780 | 2211 | wait_panel_on(intel_dp); |
dce56b3c | 2212 | intel_dp->last_power_on = jiffies; |
9934c132 | 2213 | |
5db94019 | 2214 | if (IS_GEN5(dev_priv)) { |
05ce1a49 | 2215 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
bf13e81b JN |
2216 | I915_WRITE(pp_ctrl_reg, pp); |
2217 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2218 | } |
9f0fb5be | 2219 | } |
e39b999a | 2220 | |
9f0fb5be VS |
2221 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
2222 | { | |
2223 | if (!is_edp(intel_dp)) | |
2224 | return; | |
2225 | ||
2226 | pps_lock(intel_dp); | |
2227 | edp_panel_on(intel_dp); | |
773538e8 | 2228 | pps_unlock(intel_dp); |
9934c132 JB |
2229 | } |
2230 | ||
9f0fb5be VS |
2231 | |
2232 | static void edp_panel_off(struct intel_dp *intel_dp) | |
9934c132 | 2233 | { |
30add22d | 2234 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2235 | struct drm_i915_private *dev_priv = to_i915(dev); |
99ea7127 | 2236 | u32 pp; |
f0f59a00 | 2237 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2238 | |
9f0fb5be VS |
2239 | lockdep_assert_held(&dev_priv->pps_mutex); |
2240 | ||
97af61f5 KP |
2241 | if (!is_edp(intel_dp)) |
2242 | return; | |
37c6c9b0 | 2243 | |
3936fcf4 VS |
2244 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2245 | port_name(dp_to_dig_port(intel_dp)->port)); | |
37c6c9b0 | 2246 | |
3936fcf4 VS |
2247 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2248 | port_name(dp_to_dig_port(intel_dp)->port)); | |
24f3e092 | 2249 | |
453c5420 | 2250 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
2251 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2252 | * panels get very unhappy and cease to work. */ | |
5a162e22 | 2253 | pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
b3064154 | 2254 | EDP_BLC_ENABLE); |
453c5420 | 2255 | |
bf13e81b | 2256 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2257 | |
849e39f5 PZ |
2258 | intel_dp->want_panel_vdd = false; |
2259 | ||
453c5420 JB |
2260 | I915_WRITE(pp_ctrl_reg, pp); |
2261 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2262 | |
d28d4731 | 2263 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
4be73780 | 2264 | wait_panel_off(intel_dp); |
849e39f5 PZ |
2265 | |
2266 | /* We got a reference when we enabled the VDD. */ | |
5432fcaf | 2267 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
9f0fb5be | 2268 | } |
e39b999a | 2269 | |
9f0fb5be VS |
2270 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2271 | { | |
2272 | if (!is_edp(intel_dp)) | |
2273 | return; | |
e39b999a | 2274 | |
9f0fb5be VS |
2275 | pps_lock(intel_dp); |
2276 | edp_panel_off(intel_dp); | |
773538e8 | 2277 | pps_unlock(intel_dp); |
9934c132 JB |
2278 | } |
2279 | ||
1250d107 JN |
2280 | /* Enable backlight in the panel power control. */ |
2281 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) | |
32f9d658 | 2282 | { |
da63a9f2 PZ |
2283 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2284 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 2285 | struct drm_i915_private *dev_priv = to_i915(dev); |
32f9d658 | 2286 | u32 pp; |
f0f59a00 | 2287 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2288 | |
01cb9ea6 JB |
2289 | /* |
2290 | * If we enable the backlight right away following a panel power | |
2291 | * on, we may see slight flicker as the panel syncs with the eDP | |
2292 | * link. So delay a bit to make sure the image is solid before | |
2293 | * allowing it to appear. | |
2294 | */ | |
4be73780 | 2295 | wait_backlight_on(intel_dp); |
e39b999a | 2296 | |
773538e8 | 2297 | pps_lock(intel_dp); |
e39b999a | 2298 | |
453c5420 | 2299 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2300 | pp |= EDP_BLC_ENABLE; |
453c5420 | 2301 | |
bf13e81b | 2302 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2303 | |
2304 | I915_WRITE(pp_ctrl_reg, pp); | |
2305 | POSTING_READ(pp_ctrl_reg); | |
e39b999a | 2306 | |
773538e8 | 2307 | pps_unlock(intel_dp); |
32f9d658 ZW |
2308 | } |
2309 | ||
1250d107 JN |
2310 | /* Enable backlight PWM and backlight PP control. */ |
2311 | void intel_edp_backlight_on(struct intel_dp *intel_dp) | |
2312 | { | |
2313 | if (!is_edp(intel_dp)) | |
2314 | return; | |
2315 | ||
2316 | DRM_DEBUG_KMS("\n"); | |
2317 | ||
2318 | intel_panel_enable_backlight(intel_dp->attached_connector); | |
2319 | _intel_edp_backlight_on(intel_dp); | |
2320 | } | |
2321 | ||
2322 | /* Disable backlight in the panel power control. */ | |
2323 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) | |
32f9d658 | 2324 | { |
30add22d | 2325 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2326 | struct drm_i915_private *dev_priv = to_i915(dev); |
32f9d658 | 2327 | u32 pp; |
f0f59a00 | 2328 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2329 | |
f01eca2e KP |
2330 | if (!is_edp(intel_dp)) |
2331 | return; | |
2332 | ||
773538e8 | 2333 | pps_lock(intel_dp); |
e39b999a | 2334 | |
453c5420 | 2335 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2336 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 2337 | |
bf13e81b | 2338 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2339 | |
2340 | I915_WRITE(pp_ctrl_reg, pp); | |
2341 | POSTING_READ(pp_ctrl_reg); | |
f7d2323c | 2342 | |
773538e8 | 2343 | pps_unlock(intel_dp); |
e39b999a VS |
2344 | |
2345 | intel_dp->last_backlight_off = jiffies; | |
f7d2323c | 2346 | edp_wait_backlight_off(intel_dp); |
1250d107 | 2347 | } |
f7d2323c | 2348 | |
1250d107 JN |
2349 | /* Disable backlight PP control and backlight PWM. */ |
2350 | void intel_edp_backlight_off(struct intel_dp *intel_dp) | |
2351 | { | |
2352 | if (!is_edp(intel_dp)) | |
2353 | return; | |
2354 | ||
2355 | DRM_DEBUG_KMS("\n"); | |
f7d2323c | 2356 | |
1250d107 | 2357 | _intel_edp_backlight_off(intel_dp); |
f7d2323c | 2358 | intel_panel_disable_backlight(intel_dp->attached_connector); |
32f9d658 | 2359 | } |
a4fc5ed6 | 2360 | |
73580fb7 JN |
2361 | /* |
2362 | * Hook for controlling the panel power control backlight through the bl_power | |
2363 | * sysfs attribute. Take care to handle multiple calls. | |
2364 | */ | |
2365 | static void intel_edp_backlight_power(struct intel_connector *connector, | |
2366 | bool enable) | |
2367 | { | |
2368 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); | |
e39b999a VS |
2369 | bool is_enabled; |
2370 | ||
773538e8 | 2371 | pps_lock(intel_dp); |
e39b999a | 2372 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
773538e8 | 2373 | pps_unlock(intel_dp); |
73580fb7 JN |
2374 | |
2375 | if (is_enabled == enable) | |
2376 | return; | |
2377 | ||
23ba9373 JN |
2378 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2379 | enable ? "enable" : "disable"); | |
73580fb7 JN |
2380 | |
2381 | if (enable) | |
2382 | _intel_edp_backlight_on(intel_dp); | |
2383 | else | |
2384 | _intel_edp_backlight_off(intel_dp); | |
2385 | } | |
2386 | ||
64e1077a VS |
2387 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
2388 | { | |
2389 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2390 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
2391 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; | |
2392 | ||
2393 | I915_STATE_WARN(cur_state != state, | |
2394 | "DP port %c state assertion failure (expected %s, current %s)\n", | |
2395 | port_name(dig_port->port), | |
87ad3212 | 2396 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2397 | } |
2398 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) | |
2399 | ||
2400 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) | |
2401 | { | |
2402 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; | |
2403 | ||
2404 | I915_STATE_WARN(cur_state != state, | |
2405 | "eDP PLL state assertion failure (expected %s, current %s)\n", | |
87ad3212 | 2406 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2407 | } |
2408 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) | |
2409 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) | |
2410 | ||
85cb48a1 ML |
2411 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp, |
2412 | struct intel_crtc_state *pipe_config) | |
d240f20f | 2413 | { |
85cb48a1 | 2414 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
64e1077a | 2415 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d240f20f | 2416 | |
64e1077a VS |
2417 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2418 | assert_dp_port_disabled(intel_dp); | |
2419 | assert_edp_pll_disabled(dev_priv); | |
2bd2ad64 | 2420 | |
abfce949 | 2421 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
85cb48a1 | 2422 | pipe_config->port_clock); |
abfce949 VS |
2423 | |
2424 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; | |
2425 | ||
85cb48a1 | 2426 | if (pipe_config->port_clock == 162000) |
abfce949 VS |
2427 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
2428 | else | |
2429 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
2430 | ||
2431 | I915_WRITE(DP_A, intel_dp->DP); | |
2432 | POSTING_READ(DP_A); | |
2433 | udelay(500); | |
2434 | ||
6b23f3e8 VS |
2435 | /* |
2436 | * [DevILK] Work around required when enabling DP PLL | |
2437 | * while a pipe is enabled going to FDI: | |
2438 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI | |
2439 | * 2. Program DP PLL enable | |
2440 | */ | |
2441 | if (IS_GEN5(dev_priv)) | |
0f0f74bc | 2442 | intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); |
6b23f3e8 | 2443 | |
0767935e | 2444 | intel_dp->DP |= DP_PLL_ENABLE; |
6fec7662 | 2445 | |
0767935e | 2446 | I915_WRITE(DP_A, intel_dp->DP); |
298b0b39 JB |
2447 | POSTING_READ(DP_A); |
2448 | udelay(200); | |
d240f20f JB |
2449 | } |
2450 | ||
2bd2ad64 | 2451 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 2452 | { |
da63a9f2 | 2453 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
64e1077a VS |
2454 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2455 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
d240f20f | 2456 | |
64e1077a VS |
2457 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2458 | assert_dp_port_disabled(intel_dp); | |
2459 | assert_edp_pll_enabled(dev_priv); | |
2bd2ad64 | 2460 | |
abfce949 VS |
2461 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
2462 | ||
6fec7662 | 2463 | intel_dp->DP &= ~DP_PLL_ENABLE; |
0767935e | 2464 | |
6fec7662 | 2465 | I915_WRITE(DP_A, intel_dp->DP); |
1af5fa1b | 2466 | POSTING_READ(DP_A); |
d240f20f JB |
2467 | udelay(200); |
2468 | } | |
2469 | ||
c7ad3810 | 2470 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 2471 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
2472 | { |
2473 | int ret, i; | |
2474 | ||
2475 | /* Should have a valid DPCD by this point */ | |
2476 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
2477 | return; | |
2478 | ||
2479 | if (mode != DRM_MODE_DPMS_ON) { | |
9d1a1031 JN |
2480 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2481 | DP_SET_POWER_D3); | |
c7ad3810 | 2482 | } else { |
357c0ae9 ID |
2483 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
2484 | ||
c7ad3810 JB |
2485 | /* |
2486 | * When turning on, we need to retry for 1ms to give the sink | |
2487 | * time to wake up. | |
2488 | */ | |
2489 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
2490 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2491 | DP_SET_POWER_D0); | |
c7ad3810 JB |
2492 | if (ret == 1) |
2493 | break; | |
2494 | msleep(1); | |
2495 | } | |
357c0ae9 ID |
2496 | |
2497 | if (ret == 1 && lspcon->active) | |
2498 | lspcon_wait_pcon_mode(lspcon); | |
c7ad3810 | 2499 | } |
f9cac721 JN |
2500 | |
2501 | if (ret != 1) | |
2502 | DRM_DEBUG_KMS("failed to %s sink power state\n", | |
2503 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); | |
c7ad3810 JB |
2504 | } |
2505 | ||
19d8fe15 DV |
2506 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2507 | enum pipe *pipe) | |
d240f20f | 2508 | { |
19d8fe15 | 2509 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 2510 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 | 2511 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2512 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d129bea | 2513 | u32 tmp; |
6fa9a5ec | 2514 | bool ret; |
6d129bea | 2515 | |
79f255a0 ACO |
2516 | if (!intel_display_power_get_if_enabled(dev_priv, |
2517 | encoder->power_domain)) | |
6d129bea ID |
2518 | return false; |
2519 | ||
6fa9a5ec ID |
2520 | ret = false; |
2521 | ||
6d129bea | 2522 | tmp = I915_READ(intel_dp->output_reg); |
19d8fe15 DV |
2523 | |
2524 | if (!(tmp & DP_PORT_EN)) | |
6fa9a5ec | 2525 | goto out; |
19d8fe15 | 2526 | |
5db94019 | 2527 | if (IS_GEN7(dev_priv) && port == PORT_A) { |
19d8fe15 | 2528 | *pipe = PORT_TO_PIPE_CPT(tmp); |
6e266956 | 2529 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
adc289d7 | 2530 | enum pipe p; |
19d8fe15 | 2531 | |
adc289d7 VS |
2532 | for_each_pipe(dev_priv, p) { |
2533 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); | |
2534 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { | |
2535 | *pipe = p; | |
6fa9a5ec ID |
2536 | ret = true; |
2537 | ||
2538 | goto out; | |
19d8fe15 DV |
2539 | } |
2540 | } | |
19d8fe15 | 2541 | |
4a0833ec | 2542 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
f0f59a00 | 2543 | i915_mmio_reg_offset(intel_dp->output_reg)); |
920a14b2 | 2544 | } else if (IS_CHERRYVIEW(dev_priv)) { |
39e5fa88 VS |
2545 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
2546 | } else { | |
2547 | *pipe = PORT_TO_PIPE(tmp); | |
4a0833ec | 2548 | } |
d240f20f | 2549 | |
6fa9a5ec ID |
2550 | ret = true; |
2551 | ||
2552 | out: | |
79f255a0 | 2553 | intel_display_power_put(dev_priv, encoder->power_domain); |
6fa9a5ec ID |
2554 | |
2555 | return ret; | |
19d8fe15 | 2556 | } |
d240f20f | 2557 | |
045ac3b5 | 2558 | static void intel_dp_get_config(struct intel_encoder *encoder, |
5cec258b | 2559 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
2560 | { |
2561 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 2562 | u32 tmp, flags = 0; |
63000ef6 | 2563 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2564 | struct drm_i915_private *dev_priv = to_i915(dev); |
63000ef6 XZ |
2565 | enum port port = dp_to_dig_port(intel_dp)->port; |
2566 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
045ac3b5 | 2567 | |
9ed109a7 | 2568 | tmp = I915_READ(intel_dp->output_reg); |
9fcb1704 JN |
2569 | |
2570 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; | |
9ed109a7 | 2571 | |
6e266956 | 2572 | if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
b81e34c2 VS |
2573 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2574 | ||
2575 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
63000ef6 XZ |
2576 | flags |= DRM_MODE_FLAG_PHSYNC; |
2577 | else | |
2578 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2579 | |
b81e34c2 | 2580 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
63000ef6 XZ |
2581 | flags |= DRM_MODE_FLAG_PVSYNC; |
2582 | else | |
2583 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2584 | } else { | |
39e5fa88 | 2585 | if (tmp & DP_SYNC_HS_HIGH) |
63000ef6 XZ |
2586 | flags |= DRM_MODE_FLAG_PHSYNC; |
2587 | else | |
2588 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2589 | |
39e5fa88 | 2590 | if (tmp & DP_SYNC_VS_HIGH) |
63000ef6 XZ |
2591 | flags |= DRM_MODE_FLAG_PVSYNC; |
2592 | else | |
2593 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2594 | } | |
045ac3b5 | 2595 | |
2d112de7 | 2596 | pipe_config->base.adjusted_mode.flags |= flags; |
f1f644dc | 2597 | |
c99f53f7 | 2598 | if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) |
8c875fca VS |
2599 | pipe_config->limited_color_range = true; |
2600 | ||
90a6b7b0 VS |
2601 | pipe_config->lane_count = |
2602 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; | |
2603 | ||
eb14cb74 VS |
2604 | intel_dp_get_m_n(crtc, pipe_config); |
2605 | ||
18442d08 | 2606 | if (port == PORT_A) { |
b377e0df | 2607 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
f1f644dc JB |
2608 | pipe_config->port_clock = 162000; |
2609 | else | |
2610 | pipe_config->port_clock = 270000; | |
2611 | } | |
18442d08 | 2612 | |
e3b247da VS |
2613 | pipe_config->base.adjusted_mode.crtc_clock = |
2614 | intel_dotclock_calculate(pipe_config->port_clock, | |
2615 | &pipe_config->dp_m_n); | |
7f16e5c1 | 2616 | |
6aa23e65 JN |
2617 | if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
2618 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { | |
c6cd2ee2 JN |
2619 | /* |
2620 | * This is a big fat ugly hack. | |
2621 | * | |
2622 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2623 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2624 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2625 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2626 | * max, not what it tells us to use. | |
2627 | * | |
2628 | * Note: This will still be broken if the eDP panel is not lit | |
2629 | * up by the BIOS, and thus we can't get the mode at module | |
2630 | * load. | |
2631 | */ | |
2632 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
2633 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
2634 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
c6cd2ee2 | 2635 | } |
045ac3b5 JB |
2636 | } |
2637 | ||
fd6bbda9 ML |
2638 | static void intel_disable_dp(struct intel_encoder *encoder, |
2639 | struct intel_crtc_state *old_crtc_state, | |
2640 | struct drm_connector_state *old_conn_state) | |
d240f20f | 2641 | { |
e8cb4558 | 2642 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
85cb48a1 | 2643 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
495a5bb8 | 2644 | |
85cb48a1 | 2645 | if (old_crtc_state->has_audio) |
495a5bb8 | 2646 | intel_audio_codec_disable(encoder); |
6cb49835 | 2647 | |
85cb48a1 | 2648 | if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv)) |
b32c6f48 RV |
2649 | intel_psr_disable(intel_dp); |
2650 | ||
6cb49835 DV |
2651 | /* Make sure the panel is off before trying to change the mode. But also |
2652 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 2653 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 2654 | intel_edp_backlight_off(intel_dp); |
fdbc3b1f | 2655 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 2656 | intel_edp_panel_off(intel_dp); |
3739850b | 2657 | |
08aff3fe | 2658 | /* disable the port before the pipe on g4x */ |
85cb48a1 | 2659 | if (INTEL_GEN(dev_priv) < 5) |
3739850b | 2660 | intel_dp_link_down(intel_dp); |
d240f20f JB |
2661 | } |
2662 | ||
fd6bbda9 ML |
2663 | static void ilk_post_disable_dp(struct intel_encoder *encoder, |
2664 | struct intel_crtc_state *old_crtc_state, | |
2665 | struct drm_connector_state *old_conn_state) | |
d240f20f | 2666 | { |
2bd2ad64 | 2667 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2668 | enum port port = dp_to_dig_port(intel_dp)->port; |
2bd2ad64 | 2669 | |
49277c31 | 2670 | intel_dp_link_down(intel_dp); |
abfce949 VS |
2671 | |
2672 | /* Only ilk+ has port A */ | |
08aff3fe VS |
2673 | if (port == PORT_A) |
2674 | ironlake_edp_pll_off(intel_dp); | |
49277c31 VS |
2675 | } |
2676 | ||
fd6bbda9 ML |
2677 | static void vlv_post_disable_dp(struct intel_encoder *encoder, |
2678 | struct intel_crtc_state *old_crtc_state, | |
2679 | struct drm_connector_state *old_conn_state) | |
49277c31 VS |
2680 | { |
2681 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2682 | ||
2683 | intel_dp_link_down(intel_dp); | |
2bd2ad64 DV |
2684 | } |
2685 | ||
fd6bbda9 ML |
2686 | static void chv_post_disable_dp(struct intel_encoder *encoder, |
2687 | struct intel_crtc_state *old_crtc_state, | |
2688 | struct drm_connector_state *old_conn_state) | |
a8f327fb VS |
2689 | { |
2690 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2691 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2692 | struct drm_i915_private *dev_priv = to_i915(dev); |
97fd4d5c | 2693 | |
a8f327fb VS |
2694 | intel_dp_link_down(intel_dp); |
2695 | ||
2696 | mutex_lock(&dev_priv->sb_lock); | |
2697 | ||
2698 | /* Assert data lane reset */ | |
2699 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 2700 | |
a580516d | 2701 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
2702 | } |
2703 | ||
7b13b58a VS |
2704 | static void |
2705 | _intel_dp_set_link_train(struct intel_dp *intel_dp, | |
2706 | uint32_t *DP, | |
2707 | uint8_t dp_train_pat) | |
2708 | { | |
2709 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2710 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 2711 | struct drm_i915_private *dev_priv = to_i915(dev); |
7b13b58a VS |
2712 | enum port port = intel_dig_port->port; |
2713 | ||
8b0878a0 PD |
2714 | if (dp_train_pat & DP_TRAINING_PATTERN_MASK) |
2715 | DRM_DEBUG_KMS("Using DP training pattern TPS%d\n", | |
2716 | dp_train_pat & DP_TRAINING_PATTERN_MASK); | |
2717 | ||
4f8036a2 | 2718 | if (HAS_DDI(dev_priv)) { |
7b13b58a VS |
2719 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
2720 | ||
2721 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2722 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2723 | else | |
2724 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2725 | ||
2726 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2727 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2728 | case DP_TRAINING_PATTERN_DISABLE: | |
2729 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; | |
2730 | ||
2731 | break; | |
2732 | case DP_TRAINING_PATTERN_1: | |
2733 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2734 | break; | |
2735 | case DP_TRAINING_PATTERN_2: | |
2736 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2737 | break; | |
2738 | case DP_TRAINING_PATTERN_3: | |
2739 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2740 | break; | |
2741 | } | |
2742 | I915_WRITE(DP_TP_CTL(port), temp); | |
2743 | ||
5db94019 | 2744 | } else if ((IS_GEN7(dev_priv) && port == PORT_A) || |
6e266956 | 2745 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
7b13b58a VS |
2746 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2747 | ||
2748 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2749 | case DP_TRAINING_PATTERN_DISABLE: | |
2750 | *DP |= DP_LINK_TRAIN_OFF_CPT; | |
2751 | break; | |
2752 | case DP_TRAINING_PATTERN_1: | |
2753 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; | |
2754 | break; | |
2755 | case DP_TRAINING_PATTERN_2: | |
2756 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2757 | break; | |
2758 | case DP_TRAINING_PATTERN_3: | |
8b0878a0 | 2759 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
7b13b58a VS |
2760 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2761 | break; | |
2762 | } | |
2763 | ||
2764 | } else { | |
920a14b2 | 2765 | if (IS_CHERRYVIEW(dev_priv)) |
7b13b58a VS |
2766 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
2767 | else | |
2768 | *DP &= ~DP_LINK_TRAIN_MASK; | |
2769 | ||
2770 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2771 | case DP_TRAINING_PATTERN_DISABLE: | |
2772 | *DP |= DP_LINK_TRAIN_OFF; | |
2773 | break; | |
2774 | case DP_TRAINING_PATTERN_1: | |
2775 | *DP |= DP_LINK_TRAIN_PAT_1; | |
2776 | break; | |
2777 | case DP_TRAINING_PATTERN_2: | |
2778 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2779 | break; | |
2780 | case DP_TRAINING_PATTERN_3: | |
920a14b2 | 2781 | if (IS_CHERRYVIEW(dev_priv)) { |
7b13b58a VS |
2782 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
2783 | } else { | |
8b0878a0 | 2784 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
7b13b58a VS |
2785 | *DP |= DP_LINK_TRAIN_PAT_2; |
2786 | } | |
2787 | break; | |
2788 | } | |
2789 | } | |
2790 | } | |
2791 | ||
85cb48a1 ML |
2792 | static void intel_dp_enable_port(struct intel_dp *intel_dp, |
2793 | struct intel_crtc_state *old_crtc_state) | |
7b13b58a VS |
2794 | { |
2795 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 2796 | struct drm_i915_private *dev_priv = to_i915(dev); |
7b13b58a | 2797 | |
7b13b58a | 2798 | /* enable with pattern 1 (as per spec) */ |
7b13b58a | 2799 | |
8b0878a0 | 2800 | intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1); |
7b713f50 VS |
2801 | |
2802 | /* | |
2803 | * Magic for VLV/CHV. We _must_ first set up the register | |
2804 | * without actually enabling the port, and then do another | |
2805 | * write to enable the port. Otherwise link training will | |
2806 | * fail when the power sequencer is freshly used for this port. | |
2807 | */ | |
2808 | intel_dp->DP |= DP_PORT_EN; | |
85cb48a1 | 2809 | if (old_crtc_state->has_audio) |
6fec7662 | 2810 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
7b713f50 VS |
2811 | |
2812 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2813 | POSTING_READ(intel_dp->output_reg); | |
580d3811 VS |
2814 | } |
2815 | ||
85cb48a1 | 2816 | static void intel_enable_dp(struct intel_encoder *encoder, |
bbf35e9d ML |
2817 | struct intel_crtc_state *pipe_config, |
2818 | struct drm_connector_state *conn_state) | |
d240f20f | 2819 | { |
e8cb4558 DV |
2820 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2821 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2822 | struct drm_i915_private *dev_priv = to_i915(dev); |
c1dec79a | 2823 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
e8cb4558 | 2824 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
d6fbdd15 | 2825 | enum pipe pipe = crtc->pipe; |
5d613501 | 2826 | |
0c33d8d7 DV |
2827 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2828 | return; | |
5d613501 | 2829 | |
093e3f13 VS |
2830 | pps_lock(intel_dp); |
2831 | ||
920a14b2 | 2832 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
093e3f13 VS |
2833 | vlv_init_panel_power_sequencer(intel_dp); |
2834 | ||
85cb48a1 | 2835 | intel_dp_enable_port(intel_dp, pipe_config); |
093e3f13 VS |
2836 | |
2837 | edp_panel_vdd_on(intel_dp); | |
2838 | edp_panel_on(intel_dp); | |
2839 | edp_panel_vdd_off(intel_dp, true); | |
2840 | ||
2841 | pps_unlock(intel_dp); | |
2842 | ||
920a14b2 | 2843 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e0fce78f VS |
2844 | unsigned int lane_mask = 0x0; |
2845 | ||
920a14b2 | 2846 | if (IS_CHERRYVIEW(dev_priv)) |
85cb48a1 | 2847 | lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); |
e0fce78f | 2848 | |
9b6de0a1 VS |
2849 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2850 | lane_mask); | |
e0fce78f | 2851 | } |
61234fa5 | 2852 | |
f01eca2e | 2853 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 2854 | intel_dp_start_link_train(intel_dp); |
3ab9c637 | 2855 | intel_dp_stop_link_train(intel_dp); |
c1dec79a | 2856 | |
85cb48a1 | 2857 | if (pipe_config->has_audio) { |
c1dec79a | 2858 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
d6fbdd15 | 2859 | pipe_name(pipe)); |
bbf35e9d | 2860 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
c1dec79a | 2861 | } |
ab1f90f9 | 2862 | } |
89b667f8 | 2863 | |
fd6bbda9 ML |
2864 | static void g4x_enable_dp(struct intel_encoder *encoder, |
2865 | struct intel_crtc_state *pipe_config, | |
2866 | struct drm_connector_state *conn_state) | |
ecff4f3b | 2867 | { |
828f5c6e JN |
2868 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2869 | ||
bbf35e9d | 2870 | intel_enable_dp(encoder, pipe_config, conn_state); |
4be73780 | 2871 | intel_edp_backlight_on(intel_dp); |
ab1f90f9 | 2872 | } |
89b667f8 | 2873 | |
fd6bbda9 ML |
2874 | static void vlv_enable_dp(struct intel_encoder *encoder, |
2875 | struct intel_crtc_state *pipe_config, | |
2876 | struct drm_connector_state *conn_state) | |
ab1f90f9 | 2877 | { |
828f5c6e JN |
2878 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2879 | ||
4be73780 | 2880 | intel_edp_backlight_on(intel_dp); |
b32c6f48 | 2881 | intel_psr_enable(intel_dp); |
d240f20f JB |
2882 | } |
2883 | ||
fd6bbda9 ML |
2884 | static void g4x_pre_enable_dp(struct intel_encoder *encoder, |
2885 | struct intel_crtc_state *pipe_config, | |
2886 | struct drm_connector_state *conn_state) | |
ab1f90f9 JN |
2887 | { |
2888 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
d6fbdd15 | 2889 | enum port port = dp_to_dig_port(intel_dp)->port; |
ab1f90f9 | 2890 | |
85cb48a1 | 2891 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 2892 | |
d41f1efb | 2893 | /* Only ilk+ has port A */ |
abfce949 | 2894 | if (port == PORT_A) |
85cb48a1 | 2895 | ironlake_edp_pll_on(intel_dp, pipe_config); |
ab1f90f9 JN |
2896 | } |
2897 | ||
83b84597 VS |
2898 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2899 | { | |
2900 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
fac5e23e | 2901 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
83b84597 | 2902 | enum pipe pipe = intel_dp->pps_pipe; |
44cb734c | 2903 | i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); |
83b84597 | 2904 | |
9f2bdb00 VS |
2905 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); |
2906 | ||
d158694f VS |
2907 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2908 | return; | |
2909 | ||
83b84597 VS |
2910 | edp_panel_vdd_off_sync(intel_dp); |
2911 | ||
2912 | /* | |
2913 | * VLV seems to get confused when multiple power seqeuencers | |
2914 | * have the same port selected (even if only one has power/vdd | |
2915 | * enabled). The failure manifests as vlv_wait_port_ready() failing | |
2916 | * CHV on the other hand doesn't seem to mind having the same port | |
2917 | * selected in multiple power seqeuencers, but let's clear the | |
2918 | * port select always when logically disconnecting a power sequencer | |
2919 | * from a port. | |
2920 | */ | |
2921 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", | |
2922 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
2923 | I915_WRITE(pp_on_reg, 0); | |
2924 | POSTING_READ(pp_on_reg); | |
2925 | ||
2926 | intel_dp->pps_pipe = INVALID_PIPE; | |
2927 | } | |
2928 | ||
a4a5d2f8 VS |
2929 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2930 | enum pipe pipe) | |
2931 | { | |
fac5e23e | 2932 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
2933 | struct intel_encoder *encoder; |
2934 | ||
2935 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2936 | ||
19c8054c | 2937 | for_each_intel_encoder(dev, encoder) { |
a4a5d2f8 | 2938 | struct intel_dp *intel_dp; |
773538e8 | 2939 | enum port port; |
a4a5d2f8 | 2940 | |
9f2bdb00 VS |
2941 | if (encoder->type != INTEL_OUTPUT_DP && |
2942 | encoder->type != INTEL_OUTPUT_EDP) | |
a4a5d2f8 VS |
2943 | continue; |
2944 | ||
2945 | intel_dp = enc_to_intel_dp(&encoder->base); | |
773538e8 | 2946 | port = dp_to_dig_port(intel_dp)->port; |
a4a5d2f8 | 2947 | |
9f2bdb00 VS |
2948 | WARN(intel_dp->active_pipe == pipe, |
2949 | "stealing pipe %c power sequencer from active (e)DP port %c\n", | |
2950 | pipe_name(pipe), port_name(port)); | |
2951 | ||
a4a5d2f8 VS |
2952 | if (intel_dp->pps_pipe != pipe) |
2953 | continue; | |
2954 | ||
2955 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", | |
773538e8 | 2956 | pipe_name(pipe), port_name(port)); |
a4a5d2f8 VS |
2957 | |
2958 | /* make sure vdd is off before we steal it */ | |
83b84597 | 2959 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2960 | } |
2961 | } | |
2962 | ||
2963 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) | |
2964 | { | |
2965 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2966 | struct intel_encoder *encoder = &intel_dig_port->base; | |
2967 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2968 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 | 2969 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
a4a5d2f8 VS |
2970 | |
2971 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2972 | ||
9f2bdb00 | 2973 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); |
093e3f13 | 2974 | |
9f2bdb00 VS |
2975 | if (intel_dp->pps_pipe != INVALID_PIPE && |
2976 | intel_dp->pps_pipe != crtc->pipe) { | |
2977 | /* | |
2978 | * If another power sequencer was being used on this | |
2979 | * port previously make sure to turn off vdd there while | |
2980 | * we still have control of it. | |
2981 | */ | |
83b84597 | 2982 | vlv_detach_power_sequencer(intel_dp); |
9f2bdb00 | 2983 | } |
a4a5d2f8 VS |
2984 | |
2985 | /* | |
2986 | * We may be stealing the power | |
2987 | * sequencer from another port. | |
2988 | */ | |
2989 | vlv_steal_power_sequencer(dev, crtc->pipe); | |
2990 | ||
9f2bdb00 VS |
2991 | intel_dp->active_pipe = crtc->pipe; |
2992 | ||
2993 | if (!is_edp(intel_dp)) | |
2994 | return; | |
2995 | ||
a4a5d2f8 VS |
2996 | /* now it's all ours */ |
2997 | intel_dp->pps_pipe = crtc->pipe; | |
2998 | ||
2999 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", | |
3000 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); | |
3001 | ||
3002 | /* init power sequencer on this pipe and port */ | |
36b5f425 | 3003 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
5d5ab2d2 | 3004 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true); |
a4a5d2f8 VS |
3005 | } |
3006 | ||
fd6bbda9 ML |
3007 | static void vlv_pre_enable_dp(struct intel_encoder *encoder, |
3008 | struct intel_crtc_state *pipe_config, | |
3009 | struct drm_connector_state *conn_state) | |
a4fc5ed6 | 3010 | { |
5f68c275 | 3011 | vlv_phy_pre_encoder_enable(encoder); |
ab1f90f9 | 3012 | |
bbf35e9d | 3013 | intel_enable_dp(encoder, pipe_config, conn_state); |
89b667f8 JB |
3014 | } |
3015 | ||
fd6bbda9 ML |
3016 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder, |
3017 | struct intel_crtc_state *pipe_config, | |
3018 | struct drm_connector_state *conn_state) | |
89b667f8 | 3019 | { |
85cb48a1 | 3020 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 3021 | |
6da2e616 | 3022 | vlv_phy_pre_pll_enable(encoder); |
a4fc5ed6 KP |
3023 | } |
3024 | ||
fd6bbda9 ML |
3025 | static void chv_pre_enable_dp(struct intel_encoder *encoder, |
3026 | struct intel_crtc_state *pipe_config, | |
3027 | struct drm_connector_state *conn_state) | |
e4a1d846 | 3028 | { |
e7d2a717 | 3029 | chv_phy_pre_encoder_enable(encoder); |
e4a1d846 | 3030 | |
bbf35e9d | 3031 | intel_enable_dp(encoder, pipe_config, conn_state); |
b0b33846 VS |
3032 | |
3033 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 3034 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
3035 | } |
3036 | ||
fd6bbda9 ML |
3037 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder, |
3038 | struct intel_crtc_state *pipe_config, | |
3039 | struct drm_connector_state *conn_state) | |
9197c88b | 3040 | { |
85cb48a1 | 3041 | intel_dp_prepare(encoder, pipe_config); |
625695f8 | 3042 | |
419b1b7a | 3043 | chv_phy_pre_pll_enable(encoder); |
9197c88b VS |
3044 | } |
3045 | ||
fd6bbda9 ML |
3046 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder, |
3047 | struct intel_crtc_state *pipe_config, | |
3048 | struct drm_connector_state *conn_state) | |
d6db995f | 3049 | { |
204970b5 | 3050 | chv_phy_post_pll_disable(encoder); |
d6db995f VS |
3051 | } |
3052 | ||
a4fc5ed6 KP |
3053 | /* |
3054 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
3055 | * link status information | |
3056 | */ | |
94223d04 | 3057 | bool |
93f62dad | 3058 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 3059 | { |
9f085ebb L |
3060 | return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, |
3061 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
3062 | } |
3063 | ||
97da2ef4 NV |
3064 | static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp) |
3065 | { | |
3066 | uint8_t psr_caps = 0; | |
3067 | ||
3068 | drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps); | |
3069 | return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED; | |
3070 | } | |
3071 | ||
3072 | static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) | |
3073 | { | |
3074 | uint8_t dprx = 0; | |
3075 | ||
3076 | drm_dp_dpcd_readb(&intel_dp->aux, | |
3077 | DP_DPRX_FEATURE_ENUMERATION_LIST, | |
3078 | &dprx); | |
3079 | return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; | |
3080 | } | |
3081 | ||
a76f73dc | 3082 | static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) |
340c93c0 NV |
3083 | { |
3084 | uint8_t alpm_caps = 0; | |
3085 | ||
3086 | drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &alpm_caps); | |
3087 | return alpm_caps & DP_ALPM_CAP; | |
3088 | } | |
3089 | ||
1100244e | 3090 | /* These are source-specific values. */ |
94223d04 | 3091 | uint8_t |
1a2eb460 | 3092 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 3093 | { |
dd11bc10 | 3094 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
bc7d38a4 | 3095 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 3096 | |
cc3f90f0 | 3097 | if (IS_GEN9_LP(dev_priv)) |
9314726b | 3098 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
dd11bc10 | 3099 | else if (INTEL_GEN(dev_priv) >= 9) { |
ffe5111e VS |
3100 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3101 | return intel_ddi_dp_voltage_max(encoder); | |
920a14b2 | 3102 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
bd60018a | 3103 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
5db94019 | 3104 | else if (IS_GEN7(dev_priv) && port == PORT_A) |
bd60018a | 3105 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
6e266956 | 3106 | else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) |
bd60018a | 3107 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
1a2eb460 | 3108 | else |
bd60018a | 3109 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
1a2eb460 KP |
3110 | } |
3111 | ||
94223d04 | 3112 | uint8_t |
1a2eb460 KP |
3113 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
3114 | { | |
8652744b | 3115 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
bc7d38a4 | 3116 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 3117 | |
8652744b | 3118 | if (INTEL_GEN(dev_priv) >= 9) { |
5a9d1f1a DL |
3119 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3120 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: | |
3121 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3122 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3123 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3124 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3125 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
7ad14a29 SJ |
3126 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3127 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
5a9d1f1a DL |
3128 | default: |
3129 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
3130 | } | |
8652744b | 3131 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
d6c0d722 | 3132 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3133 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3134 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3135 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3136 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3137 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3138 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3139 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
d6c0d722 | 3140 | default: |
bd60018a | 3141 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
d6c0d722 | 3142 | } |
8652744b | 3143 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e2fa6fba | 3144 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3145 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3146 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3147 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3148 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3149 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3150 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3151 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
e2fa6fba | 3152 | default: |
bd60018a | 3153 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
e2fa6fba | 3154 | } |
8652744b | 3155 | } else if (IS_GEN7(dev_priv) && port == PORT_A) { |
1a2eb460 | 3156 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3157 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3158 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3159 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3160 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3161 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
1a2eb460 | 3162 | default: |
bd60018a | 3163 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 KP |
3164 | } |
3165 | } else { | |
3166 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
3167 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3168 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3169 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3170 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3171 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3172 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3173 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
1a2eb460 | 3174 | default: |
bd60018a | 3175 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 | 3176 | } |
a4fc5ed6 KP |
3177 | } |
3178 | } | |
3179 | ||
5829975c | 3180 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
e2fa6fba | 3181 | { |
53d98725 | 3182 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
e2fa6fba P |
3183 | unsigned long demph_reg_value, preemph_reg_value, |
3184 | uniqtranscale_reg_value; | |
3185 | uint8_t train_set = intel_dp->train_set[0]; | |
e2fa6fba P |
3186 | |
3187 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3188 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e2fa6fba P |
3189 | preemph_reg_value = 0x0004000; |
3190 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3191 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3192 | demph_reg_value = 0x2B405555; |
3193 | uniqtranscale_reg_value = 0x552AB83A; | |
3194 | break; | |
bd60018a | 3195 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3196 | demph_reg_value = 0x2B404040; |
3197 | uniqtranscale_reg_value = 0x5548B83A; | |
3198 | break; | |
bd60018a | 3199 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3200 | demph_reg_value = 0x2B245555; |
3201 | uniqtranscale_reg_value = 0x5560B83A; | |
3202 | break; | |
bd60018a | 3203 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e2fa6fba P |
3204 | demph_reg_value = 0x2B405555; |
3205 | uniqtranscale_reg_value = 0x5598DA3A; | |
3206 | break; | |
3207 | default: | |
3208 | return 0; | |
3209 | } | |
3210 | break; | |
bd60018a | 3211 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e2fa6fba P |
3212 | preemph_reg_value = 0x0002000; |
3213 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3214 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3215 | demph_reg_value = 0x2B404040; |
3216 | uniqtranscale_reg_value = 0x5552B83A; | |
3217 | break; | |
bd60018a | 3218 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3219 | demph_reg_value = 0x2B404848; |
3220 | uniqtranscale_reg_value = 0x5580B83A; | |
3221 | break; | |
bd60018a | 3222 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3223 | demph_reg_value = 0x2B404040; |
3224 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3225 | break; | |
3226 | default: | |
3227 | return 0; | |
3228 | } | |
3229 | break; | |
bd60018a | 3230 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e2fa6fba P |
3231 | preemph_reg_value = 0x0000000; |
3232 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3233 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3234 | demph_reg_value = 0x2B305555; |
3235 | uniqtranscale_reg_value = 0x5570B83A; | |
3236 | break; | |
bd60018a | 3237 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3238 | demph_reg_value = 0x2B2B4040; |
3239 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3240 | break; | |
3241 | default: | |
3242 | return 0; | |
3243 | } | |
3244 | break; | |
bd60018a | 3245 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e2fa6fba P |
3246 | preemph_reg_value = 0x0006000; |
3247 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3248 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3249 | demph_reg_value = 0x1B405555; |
3250 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3251 | break; | |
3252 | default: | |
3253 | return 0; | |
3254 | } | |
3255 | break; | |
3256 | default: | |
3257 | return 0; | |
3258 | } | |
3259 | ||
53d98725 ACO |
3260 | vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, |
3261 | uniqtranscale_reg_value, 0); | |
e2fa6fba P |
3262 | |
3263 | return 0; | |
3264 | } | |
3265 | ||
5829975c | 3266 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
e4a1d846 | 3267 | { |
b7fa22d8 ACO |
3268 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3269 | u32 deemph_reg_value, margin_reg_value; | |
3270 | bool uniq_trans_scale = false; | |
e4a1d846 | 3271 | uint8_t train_set = intel_dp->train_set[0]; |
e4a1d846 CML |
3272 | |
3273 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3274 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e4a1d846 | 3275 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3276 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3277 | deemph_reg_value = 128; |
3278 | margin_reg_value = 52; | |
3279 | break; | |
bd60018a | 3280 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3281 | deemph_reg_value = 128; |
3282 | margin_reg_value = 77; | |
3283 | break; | |
bd60018a | 3284 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3285 | deemph_reg_value = 128; |
3286 | margin_reg_value = 102; | |
3287 | break; | |
bd60018a | 3288 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e4a1d846 CML |
3289 | deemph_reg_value = 128; |
3290 | margin_reg_value = 154; | |
b7fa22d8 | 3291 | uniq_trans_scale = true; |
e4a1d846 CML |
3292 | break; |
3293 | default: | |
3294 | return 0; | |
3295 | } | |
3296 | break; | |
bd60018a | 3297 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e4a1d846 | 3298 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3299 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3300 | deemph_reg_value = 85; |
3301 | margin_reg_value = 78; | |
3302 | break; | |
bd60018a | 3303 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3304 | deemph_reg_value = 85; |
3305 | margin_reg_value = 116; | |
3306 | break; | |
bd60018a | 3307 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3308 | deemph_reg_value = 85; |
3309 | margin_reg_value = 154; | |
3310 | break; | |
3311 | default: | |
3312 | return 0; | |
3313 | } | |
3314 | break; | |
bd60018a | 3315 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e4a1d846 | 3316 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3317 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3318 | deemph_reg_value = 64; |
3319 | margin_reg_value = 104; | |
3320 | break; | |
bd60018a | 3321 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3322 | deemph_reg_value = 64; |
3323 | margin_reg_value = 154; | |
3324 | break; | |
3325 | default: | |
3326 | return 0; | |
3327 | } | |
3328 | break; | |
bd60018a | 3329 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e4a1d846 | 3330 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3331 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3332 | deemph_reg_value = 43; |
3333 | margin_reg_value = 154; | |
3334 | break; | |
3335 | default: | |
3336 | return 0; | |
3337 | } | |
3338 | break; | |
3339 | default: | |
3340 | return 0; | |
3341 | } | |
3342 | ||
b7fa22d8 ACO |
3343 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
3344 | margin_reg_value, uniq_trans_scale); | |
e4a1d846 CML |
3345 | |
3346 | return 0; | |
3347 | } | |
3348 | ||
a4fc5ed6 | 3349 | static uint32_t |
5829975c | 3350 | gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 3351 | { |
3cf2efb1 | 3352 | uint32_t signal_levels = 0; |
a4fc5ed6 | 3353 | |
3cf2efb1 | 3354 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3355 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
a4fc5ed6 KP |
3356 | default: |
3357 | signal_levels |= DP_VOLTAGE_0_4; | |
3358 | break; | |
bd60018a | 3359 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
a4fc5ed6 KP |
3360 | signal_levels |= DP_VOLTAGE_0_6; |
3361 | break; | |
bd60018a | 3362 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
a4fc5ed6 KP |
3363 | signal_levels |= DP_VOLTAGE_0_8; |
3364 | break; | |
bd60018a | 3365 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
a4fc5ed6 KP |
3366 | signal_levels |= DP_VOLTAGE_1_2; |
3367 | break; | |
3368 | } | |
3cf2efb1 | 3369 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
bd60018a | 3370 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
a4fc5ed6 KP |
3371 | default: |
3372 | signal_levels |= DP_PRE_EMPHASIS_0; | |
3373 | break; | |
bd60018a | 3374 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
a4fc5ed6 KP |
3375 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3376 | break; | |
bd60018a | 3377 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
a4fc5ed6 KP |
3378 | signal_levels |= DP_PRE_EMPHASIS_6; |
3379 | break; | |
bd60018a | 3380 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
a4fc5ed6 KP |
3381 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3382 | break; | |
3383 | } | |
3384 | return signal_levels; | |
3385 | } | |
3386 | ||
e3421a18 ZW |
3387 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3388 | static uint32_t | |
5829975c | 3389 | gen6_edp_signal_levels(uint8_t train_set) |
e3421a18 | 3390 | { |
3c5a62b5 YL |
3391 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3392 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3393 | switch (signal_levels) { | |
bd60018a SJ |
3394 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3395 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3396 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
bd60018a | 3397 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3c5a62b5 | 3398 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
bd60018a SJ |
3399 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3400 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
3c5a62b5 | 3401 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
bd60018a SJ |
3402 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3403 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
3c5a62b5 | 3404 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
bd60018a SJ |
3405 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3406 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3407 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
e3421a18 | 3408 | default: |
3c5a62b5 YL |
3409 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3410 | "0x%x\n", signal_levels); | |
3411 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
3412 | } |
3413 | } | |
3414 | ||
1a2eb460 KP |
3415 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3416 | static uint32_t | |
5829975c | 3417 | gen7_edp_signal_levels(uint8_t train_set) |
1a2eb460 KP |
3418 | { |
3419 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
3420 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3421 | switch (signal_levels) { | |
bd60018a | 3422 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3423 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
bd60018a | 3424 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 | 3425 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
bd60018a | 3426 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
1a2eb460 KP |
3427 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3428 | ||
bd60018a | 3429 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3430 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
bd60018a | 3431 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3432 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3433 | ||
bd60018a | 3434 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3435 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
bd60018a | 3436 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3437 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3438 | ||
3439 | default: | |
3440 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
3441 | "0x%x\n", signal_levels); | |
3442 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
3443 | } | |
3444 | } | |
3445 | ||
94223d04 | 3446 | void |
f4eb692e | 3447 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
f0a3424e PZ |
3448 | { |
3449 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 3450 | enum port port = intel_dig_port->port; |
f0a3424e | 3451 | struct drm_device *dev = intel_dig_port->base.base.dev; |
b905a915 | 3452 | struct drm_i915_private *dev_priv = to_i915(dev); |
f8896f5d | 3453 | uint32_t signal_levels, mask = 0; |
f0a3424e PZ |
3454 | uint8_t train_set = intel_dp->train_set[0]; |
3455 | ||
4f8036a2 | 3456 | if (HAS_DDI(dev_priv)) { |
f8896f5d DW |
3457 | signal_levels = ddi_signal_levels(intel_dp); |
3458 | ||
254e0931 | 3459 | if (IS_GEN9_LP(dev_priv)) |
f8896f5d DW |
3460 | signal_levels = 0; |
3461 | else | |
3462 | mask = DDI_BUF_EMP_MASK; | |
920a14b2 | 3463 | } else if (IS_CHERRYVIEW(dev_priv)) { |
5829975c | 3464 | signal_levels = chv_signal_levels(intel_dp); |
11a914c2 | 3465 | } else if (IS_VALLEYVIEW(dev_priv)) { |
5829975c | 3466 | signal_levels = vlv_signal_levels(intel_dp); |
5db94019 | 3467 | } else if (IS_GEN7(dev_priv) && port == PORT_A) { |
5829975c | 3468 | signal_levels = gen7_edp_signal_levels(train_set); |
f0a3424e | 3469 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
5db94019 | 3470 | } else if (IS_GEN6(dev_priv) && port == PORT_A) { |
5829975c | 3471 | signal_levels = gen6_edp_signal_levels(train_set); |
f0a3424e PZ |
3472 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3473 | } else { | |
5829975c | 3474 | signal_levels = gen4_signal_levels(train_set); |
f0a3424e PZ |
3475 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3476 | } | |
3477 | ||
96fb9f9b VK |
3478 | if (mask) |
3479 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
3480 | ||
3481 | DRM_DEBUG_KMS("Using vswing level %d\n", | |
3482 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); | |
3483 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", | |
3484 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
3485 | DP_TRAIN_PRE_EMPHASIS_SHIFT); | |
f0a3424e | 3486 | |
f4eb692e | 3487 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
b905a915 ACO |
3488 | |
3489 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
3490 | POSTING_READ(intel_dp->output_reg); | |
f0a3424e PZ |
3491 | } |
3492 | ||
94223d04 | 3493 | void |
e9c176d5 ACO |
3494 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
3495 | uint8_t dp_train_pat) | |
a4fc5ed6 | 3496 | { |
174edf1f | 3497 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
90a6b7b0 VS |
3498 | struct drm_i915_private *dev_priv = |
3499 | to_i915(intel_dig_port->base.base.dev); | |
a4fc5ed6 | 3500 | |
f4eb692e | 3501 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
47ea7542 | 3502 | |
f4eb692e | 3503 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
ea5b213a | 3504 | POSTING_READ(intel_dp->output_reg); |
e9c176d5 ACO |
3505 | } |
3506 | ||
94223d04 | 3507 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3ab9c637 ID |
3508 | { |
3509 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3510 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 3511 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ab9c637 ID |
3512 | enum port port = intel_dig_port->port; |
3513 | uint32_t val; | |
3514 | ||
4f8036a2 | 3515 | if (!HAS_DDI(dev_priv)) |
3ab9c637 ID |
3516 | return; |
3517 | ||
3518 | val = I915_READ(DP_TP_CTL(port)); | |
3519 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
3520 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
3521 | I915_WRITE(DP_TP_CTL(port), val); | |
3522 | ||
3523 | /* | |
3524 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
3525 | * we need to set idle transmission mode is to work around a HW issue | |
3526 | * where we enable the pipe while not in idle link-training mode. | |
3527 | * In this case there is requirement to wait for a minimum number of | |
3528 | * idle patterns to be sent. | |
3529 | */ | |
3530 | if (port == PORT_A) | |
3531 | return; | |
3532 | ||
a767017f CW |
3533 | if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port), |
3534 | DP_TP_STATUS_IDLE_DONE, | |
3535 | DP_TP_STATUS_IDLE_DONE, | |
3536 | 1)) | |
3ab9c637 ID |
3537 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
3538 | } | |
3539 | ||
a4fc5ed6 | 3540 | static void |
ea5b213a | 3541 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 3542 | { |
da63a9f2 | 3543 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1612c8bd | 3544 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
bc7d38a4 | 3545 | enum port port = intel_dig_port->port; |
da63a9f2 | 3546 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 3547 | struct drm_i915_private *dev_priv = to_i915(dev); |
ea5b213a | 3548 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 3549 | |
4f8036a2 | 3550 | if (WARN_ON(HAS_DDI(dev_priv))) |
c19b0669 PZ |
3551 | return; |
3552 | ||
0c33d8d7 | 3553 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
3554 | return; |
3555 | ||
28c97730 | 3556 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 3557 | |
5db94019 | 3558 | if ((IS_GEN7(dev_priv) && port == PORT_A) || |
6e266956 | 3559 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
e3421a18 | 3560 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1612c8bd | 3561 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
e3421a18 | 3562 | } else { |
920a14b2 | 3563 | if (IS_CHERRYVIEW(dev_priv)) |
aad3d14d VS |
3564 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
3565 | else | |
3566 | DP &= ~DP_LINK_TRAIN_MASK; | |
1612c8bd | 3567 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
e3421a18 | 3568 | } |
1612c8bd | 3569 | I915_WRITE(intel_dp->output_reg, DP); |
fe255d00 | 3570 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 3571 | |
1612c8bd VS |
3572 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3573 | I915_WRITE(intel_dp->output_reg, DP); | |
3574 | POSTING_READ(intel_dp->output_reg); | |
3575 | ||
3576 | /* | |
3577 | * HW workaround for IBX, we need to move the port | |
3578 | * to transcoder A after disabling it to allow the | |
3579 | * matching HDMI port to be enabled on transcoder A. | |
3580 | */ | |
6e266956 | 3581 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { |
0c241d5b VS |
3582 | /* |
3583 | * We get CPU/PCH FIFO underruns on the other pipe when | |
3584 | * doing the workaround. Sweep them under the rug. | |
3585 | */ | |
3586 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3587 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3588 | ||
1612c8bd VS |
3589 | /* always enable with pattern 1 (as per spec) */ |
3590 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); | |
3591 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; | |
3592 | I915_WRITE(intel_dp->output_reg, DP); | |
3593 | POSTING_READ(intel_dp->output_reg); | |
3594 | ||
3595 | DP &= ~DP_PORT_EN; | |
5bddd17f | 3596 | I915_WRITE(intel_dp->output_reg, DP); |
0ca09685 | 3597 | POSTING_READ(intel_dp->output_reg); |
0c241d5b | 3598 | |
0f0f74bc | 3599 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
3600 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
3601 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
5bddd17f EA |
3602 | } |
3603 | ||
f01eca2e | 3604 | msleep(intel_dp->panel_power_down_delay); |
6fec7662 VS |
3605 | |
3606 | intel_dp->DP = DP; | |
9f2bdb00 VS |
3607 | |
3608 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
3609 | pps_lock(intel_dp); | |
3610 | intel_dp->active_pipe = INVALID_PIPE; | |
3611 | pps_unlock(intel_dp); | |
3612 | } | |
a4fc5ed6 KP |
3613 | } |
3614 | ||
24e807e7 | 3615 | bool |
fe5a66f9 | 3616 | intel_dp_read_dpcd(struct intel_dp *intel_dp) |
92fd8fd1 | 3617 | { |
9f085ebb L |
3618 | if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3619 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 3620 | return false; /* aux transfer failed */ |
92fd8fd1 | 3621 | |
a8e98153 | 3622 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
577c7a50 | 3623 | |
fe5a66f9 VS |
3624 | return intel_dp->dpcd[DP_DPCD_REV] != 0; |
3625 | } | |
edb39244 | 3626 | |
fe5a66f9 VS |
3627 | static bool |
3628 | intel_edp_init_dpcd(struct intel_dp *intel_dp) | |
3629 | { | |
3630 | struct drm_i915_private *dev_priv = | |
3631 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
30d9aa42 | 3632 | |
fe5a66f9 VS |
3633 | /* this function is meant to be called only once */ |
3634 | WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); | |
30d9aa42 | 3635 | |
fe5a66f9 | 3636 | if (!intel_dp_read_dpcd(intel_dp)) |
30d9aa42 SS |
3637 | return false; |
3638 | ||
12a47a42 ID |
3639 | intel_dp_read_desc(intel_dp); |
3640 | ||
fe5a66f9 VS |
3641 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
3642 | dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
3643 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
474d1ec4 | 3644 | |
fe5a66f9 VS |
3645 | /* Check if the panel supports PSR */ |
3646 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, | |
3647 | intel_dp->psr_dpcd, | |
3648 | sizeof(intel_dp->psr_dpcd)); | |
3649 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { | |
3650 | dev_priv->psr.sink_support = true; | |
3651 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); | |
3652 | } | |
86ee27b5 | 3653 | |
fe5a66f9 VS |
3654 | if (INTEL_GEN(dev_priv) >= 9 && |
3655 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { | |
3656 | uint8_t frame_sync_cap; | |
3657 | ||
3658 | dev_priv->psr.sink_support = true; | |
3659 | drm_dp_dpcd_read(&intel_dp->aux, | |
3660 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, | |
3661 | &frame_sync_cap, 1); | |
3662 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; | |
3663 | /* PSR2 needs frame sync as well */ | |
3664 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; | |
3665 | DRM_DEBUG_KMS("PSR2 %s on sink", | |
3666 | dev_priv->psr.psr2_support ? "supported" : "not supported"); | |
97da2ef4 NV |
3667 | |
3668 | if (dev_priv->psr.psr2_support) { | |
3669 | dev_priv->psr.y_cord_support = | |
3670 | intel_dp_get_y_cord_status(intel_dp); | |
3671 | dev_priv->psr.colorimetry_support = | |
3672 | intel_dp_get_colorimetry_status(intel_dp); | |
340c93c0 NV |
3673 | dev_priv->psr.alpm = |
3674 | intel_dp_get_alpm_status(intel_dp); | |
97da2ef4 NV |
3675 | } |
3676 | ||
50003939 JN |
3677 | } |
3678 | ||
fe5a66f9 VS |
3679 | /* Read the eDP Display control capabilities registers */ |
3680 | if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && | |
3681 | drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, | |
f7170e2e DC |
3682 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == |
3683 | sizeof(intel_dp->edp_dpcd)) | |
fe5a66f9 VS |
3684 | DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), |
3685 | intel_dp->edp_dpcd); | |
06ea66b6 | 3686 | |
fc0f8e25 | 3687 | /* Intermediate frequency support */ |
fe5a66f9 | 3688 | if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */ |
94ca719e | 3689 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
ea2d8a42 VS |
3690 | int i; |
3691 | ||
9f085ebb L |
3692 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, |
3693 | sink_rates, sizeof(sink_rates)); | |
ea2d8a42 | 3694 | |
94ca719e VS |
3695 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
3696 | int val = le16_to_cpu(sink_rates[i]); | |
ea2d8a42 VS |
3697 | |
3698 | if (val == 0) | |
3699 | break; | |
3700 | ||
fd81c44e DP |
3701 | /* Value read multiplied by 200kHz gives the per-lane |
3702 | * link rate in kHz. The source rates are, however, | |
3703 | * stored in terms of LS_Clk kHz. The full conversion | |
3704 | * back to symbols is | |
3705 | * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) | |
3706 | */ | |
af77b974 | 3707 | intel_dp->sink_rates[i] = (val * 200) / 10; |
ea2d8a42 | 3708 | } |
94ca719e | 3709 | intel_dp->num_sink_rates = i; |
fc0f8e25 | 3710 | } |
0336400e | 3711 | |
68f357cb JN |
3712 | if (intel_dp->num_sink_rates) |
3713 | intel_dp->use_rate_select = true; | |
3714 | else | |
3715 | intel_dp_set_sink_rates(intel_dp); | |
3716 | ||
975ee5fc JN |
3717 | intel_dp_set_common_rates(intel_dp); |
3718 | ||
fe5a66f9 VS |
3719 | return true; |
3720 | } | |
3721 | ||
3722 | ||
3723 | static bool | |
3724 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
3725 | { | |
3726 | if (!intel_dp_read_dpcd(intel_dp)) | |
3727 | return false; | |
3728 | ||
68f357cb | 3729 | /* Don't clobber cached eDP rates. */ |
975ee5fc | 3730 | if (!is_edp(intel_dp)) { |
68f357cb | 3731 | intel_dp_set_sink_rates(intel_dp); |
975ee5fc JN |
3732 | intel_dp_set_common_rates(intel_dp); |
3733 | } | |
68f357cb | 3734 | |
fe5a66f9 VS |
3735 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT, |
3736 | &intel_dp->sink_count, 1) < 0) | |
3737 | return false; | |
3738 | ||
3739 | /* | |
3740 | * Sink count can change between short pulse hpd hence | |
3741 | * a member variable in intel_dp will track any changes | |
3742 | * between short pulse interrupts. | |
3743 | */ | |
3744 | intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count); | |
3745 | ||
3746 | /* | |
3747 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that | |
3748 | * a dongle is present but no display. Unless we require to know | |
3749 | * if a dongle is present or not, we don't need to update | |
3750 | * downstream port information. So, an early return here saves | |
3751 | * time from performing other operations which are not required. | |
3752 | */ | |
3753 | if (!is_edp(intel_dp) && !intel_dp->sink_count) | |
3754 | return false; | |
0336400e | 3755 | |
c726ad01 | 3756 | if (!drm_dp_is_branch(intel_dp->dpcd)) |
edb39244 AJ |
3757 | return true; /* native DP sink */ |
3758 | ||
3759 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
3760 | return true; /* no per-port downstream info */ | |
3761 | ||
9f085ebb L |
3762 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3763 | intel_dp->downstream_ports, | |
3764 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
3765 | return false; /* downstream port status fetch failed */ |
3766 | ||
3767 | return true; | |
92fd8fd1 KP |
3768 | } |
3769 | ||
0e32b39c | 3770 | static bool |
c4e3170a | 3771 | intel_dp_can_mst(struct intel_dp *intel_dp) |
0e32b39c DA |
3772 | { |
3773 | u8 buf[1]; | |
3774 | ||
7cc96139 NS |
3775 | if (!i915.enable_dp_mst) |
3776 | return false; | |
3777 | ||
0e32b39c DA |
3778 | if (!intel_dp->can_mst) |
3779 | return false; | |
3780 | ||
3781 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) | |
3782 | return false; | |
3783 | ||
c4e3170a VS |
3784 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1) |
3785 | return false; | |
0e32b39c | 3786 | |
c4e3170a VS |
3787 | return buf[0] & DP_MST_CAP; |
3788 | } | |
3789 | ||
3790 | static void | |
3791 | intel_dp_configure_mst(struct intel_dp *intel_dp) | |
3792 | { | |
3793 | if (!i915.enable_dp_mst) | |
3794 | return; | |
3795 | ||
3796 | if (!intel_dp->can_mst) | |
3797 | return; | |
3798 | ||
3799 | intel_dp->is_mst = intel_dp_can_mst(intel_dp); | |
3800 | ||
3801 | if (intel_dp->is_mst) | |
3802 | DRM_DEBUG_KMS("Sink is MST capable\n"); | |
3803 | else | |
3804 | DRM_DEBUG_KMS("Sink is not MST capable\n"); | |
3805 | ||
3806 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
3807 | intel_dp->is_mst); | |
0e32b39c DA |
3808 | } |
3809 | ||
e5a1cab5 | 3810 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
d2e216d0 | 3811 | { |
082dcc7c | 3812 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
0f0f74bc | 3813 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c | 3814 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
ad9dc91b | 3815 | u8 buf; |
e5a1cab5 | 3816 | int ret = 0; |
c6297843 RV |
3817 | int count = 0; |
3818 | int attempts = 10; | |
d2e216d0 | 3819 | |
082dcc7c RV |
3820 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
3821 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); | |
e5a1cab5 RV |
3822 | ret = -EIO; |
3823 | goto out; | |
4373f0f2 PZ |
3824 | } |
3825 | ||
082dcc7c | 3826 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
e5a1cab5 | 3827 | buf & ~DP_TEST_SINK_START) < 0) { |
082dcc7c | 3828 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
e5a1cab5 RV |
3829 | ret = -EIO; |
3830 | goto out; | |
3831 | } | |
d2e216d0 | 3832 | |
c6297843 | 3833 | do { |
0f0f74bc | 3834 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
c6297843 RV |
3835 | |
3836 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
3837 | DP_TEST_SINK_MISC, &buf) < 0) { | |
3838 | ret = -EIO; | |
3839 | goto out; | |
3840 | } | |
3841 | count = buf & DP_TEST_COUNT_MASK; | |
3842 | } while (--attempts && count); | |
3843 | ||
3844 | if (attempts == 0) { | |
dc5a9037 | 3845 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
c6297843 RV |
3846 | ret = -ETIMEDOUT; |
3847 | } | |
3848 | ||
e5a1cab5 | 3849 | out: |
082dcc7c | 3850 | hsw_enable_ips(intel_crtc); |
e5a1cab5 | 3851 | return ret; |
082dcc7c RV |
3852 | } |
3853 | ||
3854 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) | |
3855 | { | |
3856 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
0f0f74bc | 3857 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c RV |
3858 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3859 | u8 buf; | |
e5a1cab5 RV |
3860 | int ret; |
3861 | ||
082dcc7c RV |
3862 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
3863 | return -EIO; | |
3864 | ||
3865 | if (!(buf & DP_TEST_CRC_SUPPORTED)) | |
3866 | return -ENOTTY; | |
3867 | ||
3868 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) | |
3869 | return -EIO; | |
3870 | ||
6d8175da RV |
3871 | if (buf & DP_TEST_SINK_START) { |
3872 | ret = intel_dp_sink_crc_stop(intel_dp); | |
3873 | if (ret) | |
3874 | return ret; | |
3875 | } | |
3876 | ||
082dcc7c | 3877 | hsw_disable_ips(intel_crtc); |
1dda5f93 | 3878 | |
9d1a1031 | 3879 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
082dcc7c RV |
3880 | buf | DP_TEST_SINK_START) < 0) { |
3881 | hsw_enable_ips(intel_crtc); | |
3882 | return -EIO; | |
4373f0f2 PZ |
3883 | } |
3884 | ||
0f0f74bc | 3885 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
082dcc7c RV |
3886 | return 0; |
3887 | } | |
3888 | ||
3889 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) | |
3890 | { | |
3891 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
0f0f74bc | 3892 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c RV |
3893 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3894 | u8 buf; | |
621d4c76 | 3895 | int count, ret; |
082dcc7c | 3896 | int attempts = 6; |
082dcc7c RV |
3897 | |
3898 | ret = intel_dp_sink_crc_start(intel_dp); | |
3899 | if (ret) | |
3900 | return ret; | |
3901 | ||
ad9dc91b | 3902 | do { |
0f0f74bc | 3903 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
621d4c76 | 3904 | |
1dda5f93 | 3905 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4373f0f2 PZ |
3906 | DP_TEST_SINK_MISC, &buf) < 0) { |
3907 | ret = -EIO; | |
afe0d67e | 3908 | goto stop; |
4373f0f2 | 3909 | } |
621d4c76 | 3910 | count = buf & DP_TEST_COUNT_MASK; |
aabc95dc | 3911 | |
7e38eeff | 3912 | } while (--attempts && count == 0); |
ad9dc91b RV |
3913 | |
3914 | if (attempts == 0) { | |
7e38eeff RV |
3915 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
3916 | ret = -ETIMEDOUT; | |
3917 | goto stop; | |
3918 | } | |
3919 | ||
3920 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { | |
3921 | ret = -EIO; | |
3922 | goto stop; | |
ad9dc91b | 3923 | } |
d2e216d0 | 3924 | |
afe0d67e | 3925 | stop: |
082dcc7c | 3926 | intel_dp_sink_crc_stop(intel_dp); |
4373f0f2 | 3927 | return ret; |
d2e216d0 RV |
3928 | } |
3929 | ||
a60f0e38 JB |
3930 | static bool |
3931 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3932 | { | |
9f085ebb | 3933 | return drm_dp_dpcd_read(&intel_dp->aux, |
9d1a1031 JN |
3934 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
3935 | sink_irq_vector, 1) == 1; | |
a60f0e38 JB |
3936 | } |
3937 | ||
0e32b39c DA |
3938 | static bool |
3939 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3940 | { | |
3941 | int ret; | |
3942 | ||
9f085ebb | 3943 | ret = drm_dp_dpcd_read(&intel_dp->aux, |
0e32b39c DA |
3944 | DP_SINK_COUNT_ESI, |
3945 | sink_irq_vector, 14); | |
3946 | if (ret != 14) | |
3947 | return false; | |
3948 | ||
3949 | return true; | |
3950 | } | |
3951 | ||
c5d5ab7a TP |
3952 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
3953 | { | |
da15f7cb MN |
3954 | int status = 0; |
3955 | int min_lane_count = 1; | |
da15f7cb MN |
3956 | int link_rate_index, test_link_rate; |
3957 | uint8_t test_lane_count, test_link_bw; | |
3958 | /* (DP CTS 1.2) | |
3959 | * 4.3.1.11 | |
3960 | */ | |
3961 | /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ | |
3962 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, | |
3963 | &test_lane_count); | |
3964 | ||
3965 | if (status <= 0) { | |
3966 | DRM_DEBUG_KMS("Lane count read failed\n"); | |
3967 | return DP_TEST_NAK; | |
3968 | } | |
3969 | test_lane_count &= DP_MAX_LANE_COUNT_MASK; | |
3970 | /* Validate the requested lane count */ | |
3971 | if (test_lane_count < min_lane_count || | |
3972 | test_lane_count > intel_dp->max_sink_lane_count) | |
3973 | return DP_TEST_NAK; | |
3974 | ||
3975 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, | |
3976 | &test_link_bw); | |
3977 | if (status <= 0) { | |
3978 | DRM_DEBUG_KMS("Link Rate read failed\n"); | |
3979 | return DP_TEST_NAK; | |
3980 | } | |
3981 | /* Validate the requested link rate */ | |
3982 | test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); | |
b1810a74 JN |
3983 | link_rate_index = intel_dp_rate_index(intel_dp->common_rates, |
3984 | intel_dp->num_common_rates, | |
3985 | test_link_rate); | |
da15f7cb MN |
3986 | if (link_rate_index < 0) |
3987 | return DP_TEST_NAK; | |
3988 | ||
3989 | intel_dp->compliance.test_lane_count = test_lane_count; | |
3990 | intel_dp->compliance.test_link_rate = test_link_rate; | |
3991 | ||
3992 | return DP_TEST_ACK; | |
c5d5ab7a TP |
3993 | } |
3994 | ||
3995 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) | |
3996 | { | |
611032bf MN |
3997 | uint8_t test_pattern; |
3998 | uint16_t test_misc; | |
3999 | __be16 h_width, v_height; | |
4000 | int status = 0; | |
4001 | ||
4002 | /* Read the TEST_PATTERN (DP CTS 3.1.5) */ | |
4003 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_PATTERN, | |
4004 | &test_pattern, 1); | |
4005 | if (status <= 0) { | |
4006 | DRM_DEBUG_KMS("Test pattern read failed\n"); | |
4007 | return DP_TEST_NAK; | |
4008 | } | |
4009 | if (test_pattern != DP_COLOR_RAMP) | |
4010 | return DP_TEST_NAK; | |
4011 | ||
4012 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, | |
4013 | &h_width, 2); | |
4014 | if (status <= 0) { | |
4015 | DRM_DEBUG_KMS("H Width read failed\n"); | |
4016 | return DP_TEST_NAK; | |
4017 | } | |
4018 | ||
4019 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, | |
4020 | &v_height, 2); | |
4021 | if (status <= 0) { | |
4022 | DRM_DEBUG_KMS("V Height read failed\n"); | |
4023 | return DP_TEST_NAK; | |
4024 | } | |
4025 | ||
4026 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_MISC0, | |
4027 | &test_misc, 1); | |
4028 | if (status <= 0) { | |
4029 | DRM_DEBUG_KMS("TEST MISC read failed\n"); | |
4030 | return DP_TEST_NAK; | |
4031 | } | |
4032 | if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB) | |
4033 | return DP_TEST_NAK; | |
4034 | if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA) | |
4035 | return DP_TEST_NAK; | |
4036 | switch (test_misc & DP_TEST_BIT_DEPTH_MASK) { | |
4037 | case DP_TEST_BIT_DEPTH_6: | |
4038 | intel_dp->compliance.test_data.bpc = 6; | |
4039 | break; | |
4040 | case DP_TEST_BIT_DEPTH_8: | |
4041 | intel_dp->compliance.test_data.bpc = 8; | |
4042 | break; | |
4043 | default: | |
4044 | return DP_TEST_NAK; | |
4045 | } | |
4046 | ||
4047 | intel_dp->compliance.test_data.video_pattern = test_pattern; | |
4048 | intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); | |
4049 | intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); | |
4050 | /* Set test active flag here so userspace doesn't interrupt things */ | |
4051 | intel_dp->compliance.test_active = 1; | |
4052 | ||
4053 | return DP_TEST_ACK; | |
c5d5ab7a TP |
4054 | } |
4055 | ||
4056 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) | |
a60f0e38 | 4057 | { |
b48a5ba9 | 4058 | uint8_t test_result = DP_TEST_ACK; |
559be30c TP |
4059 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4060 | struct drm_connector *connector = &intel_connector->base; | |
4061 | ||
4062 | if (intel_connector->detect_edid == NULL || | |
ac6f2e29 | 4063 | connector->edid_corrupt || |
559be30c TP |
4064 | intel_dp->aux.i2c_defer_count > 6) { |
4065 | /* Check EDID read for NACKs, DEFERs and corruption | |
4066 | * (DP CTS 1.2 Core r1.1) | |
4067 | * 4.2.2.4 : Failed EDID read, I2C_NAK | |
4068 | * 4.2.2.5 : Failed EDID read, I2C_DEFER | |
4069 | * 4.2.2.6 : EDID corruption detected | |
4070 | * Use failsafe mode for all cases | |
4071 | */ | |
4072 | if (intel_dp->aux.i2c_nack_count > 0 || | |
4073 | intel_dp->aux.i2c_defer_count > 0) | |
4074 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", | |
4075 | intel_dp->aux.i2c_nack_count, | |
4076 | intel_dp->aux.i2c_defer_count); | |
c1617abc | 4077 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; |
559be30c | 4078 | } else { |
f79b468e TS |
4079 | struct edid *block = intel_connector->detect_edid; |
4080 | ||
4081 | /* We have to write the checksum | |
4082 | * of the last block read | |
4083 | */ | |
4084 | block += intel_connector->detect_edid->extensions; | |
4085 | ||
559be30c TP |
4086 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
4087 | DP_TEST_EDID_CHECKSUM, | |
f79b468e | 4088 | &block->checksum, |
5a1cc655 | 4089 | 1)) |
559be30c TP |
4090 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
4091 | ||
4092 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; | |
b48a5ba9 | 4093 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; |
559be30c TP |
4094 | } |
4095 | ||
4096 | /* Set test active flag here so userspace doesn't interrupt things */ | |
c1617abc | 4097 | intel_dp->compliance.test_active = 1; |
559be30c | 4098 | |
c5d5ab7a TP |
4099 | return test_result; |
4100 | } | |
4101 | ||
4102 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) | |
a60f0e38 | 4103 | { |
c5d5ab7a TP |
4104 | uint8_t test_result = DP_TEST_NAK; |
4105 | return test_result; | |
4106 | } | |
4107 | ||
4108 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
4109 | { | |
4110 | uint8_t response = DP_TEST_NAK; | |
5ec63bbd JN |
4111 | uint8_t request = 0; |
4112 | int status; | |
c5d5ab7a | 4113 | |
5ec63bbd | 4114 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); |
c5d5ab7a TP |
4115 | if (status <= 0) { |
4116 | DRM_DEBUG_KMS("Could not read test request from sink\n"); | |
4117 | goto update_status; | |
4118 | } | |
4119 | ||
5ec63bbd | 4120 | switch (request) { |
c5d5ab7a TP |
4121 | case DP_TEST_LINK_TRAINING: |
4122 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); | |
c5d5ab7a TP |
4123 | response = intel_dp_autotest_link_training(intel_dp); |
4124 | break; | |
4125 | case DP_TEST_LINK_VIDEO_PATTERN: | |
4126 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); | |
c5d5ab7a TP |
4127 | response = intel_dp_autotest_video_pattern(intel_dp); |
4128 | break; | |
4129 | case DP_TEST_LINK_EDID_READ: | |
4130 | DRM_DEBUG_KMS("EDID test requested\n"); | |
c5d5ab7a TP |
4131 | response = intel_dp_autotest_edid(intel_dp); |
4132 | break; | |
4133 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
4134 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); | |
c5d5ab7a TP |
4135 | response = intel_dp_autotest_phy_pattern(intel_dp); |
4136 | break; | |
4137 | default: | |
5ec63bbd | 4138 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", request); |
c5d5ab7a TP |
4139 | break; |
4140 | } | |
4141 | ||
5ec63bbd JN |
4142 | if (response & DP_TEST_ACK) |
4143 | intel_dp->compliance.test_type = request; | |
4144 | ||
c5d5ab7a | 4145 | update_status: |
5ec63bbd | 4146 | status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); |
c5d5ab7a TP |
4147 | if (status <= 0) |
4148 | DRM_DEBUG_KMS("Could not write test response to sink\n"); | |
a60f0e38 JB |
4149 | } |
4150 | ||
0e32b39c DA |
4151 | static int |
4152 | intel_dp_check_mst_status(struct intel_dp *intel_dp) | |
4153 | { | |
4154 | bool bret; | |
4155 | ||
4156 | if (intel_dp->is_mst) { | |
4157 | u8 esi[16] = { 0 }; | |
4158 | int ret = 0; | |
4159 | int retry; | |
4160 | bool handled; | |
4161 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
4162 | go_again: | |
4163 | if (bret == true) { | |
4164 | ||
4165 | /* check link status - esi[10] = 0x200c */ | |
19e0b4ca | 4166 | if (intel_dp->active_mst_links && |
901c2daf | 4167 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
0e32b39c DA |
4168 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
4169 | intel_dp_start_link_train(intel_dp); | |
0e32b39c DA |
4170 | intel_dp_stop_link_train(intel_dp); |
4171 | } | |
4172 | ||
6f34cc39 | 4173 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
0e32b39c DA |
4174 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
4175 | ||
4176 | if (handled) { | |
4177 | for (retry = 0; retry < 3; retry++) { | |
4178 | int wret; | |
4179 | wret = drm_dp_dpcd_write(&intel_dp->aux, | |
4180 | DP_SINK_COUNT_ESI+1, | |
4181 | &esi[1], 3); | |
4182 | if (wret == 3) { | |
4183 | break; | |
4184 | } | |
4185 | } | |
4186 | ||
4187 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
4188 | if (bret == true) { | |
6f34cc39 | 4189 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
0e32b39c DA |
4190 | goto go_again; |
4191 | } | |
4192 | } else | |
4193 | ret = 0; | |
4194 | ||
4195 | return ret; | |
4196 | } else { | |
4197 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4198 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); | |
4199 | intel_dp->is_mst = false; | |
4200 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
4201 | /* send a hotplug event */ | |
4202 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); | |
4203 | } | |
4204 | } | |
4205 | return -EINVAL; | |
4206 | } | |
4207 | ||
bfd02b3c VS |
4208 | static void |
4209 | intel_dp_retrain_link(struct intel_dp *intel_dp) | |
4210 | { | |
4211 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; | |
4212 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
4213 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
4214 | ||
4215 | /* Suppress underruns caused by re-training */ | |
4216 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); | |
4217 | if (crtc->config->has_pch_encoder) | |
4218 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
4219 | intel_crtc_pch_transcoder(crtc), false); | |
4220 | ||
4221 | intel_dp_start_link_train(intel_dp); | |
4222 | intel_dp_stop_link_train(intel_dp); | |
4223 | ||
4224 | /* Keep underrun reporting disabled until things are stable */ | |
0f0f74bc | 4225 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
bfd02b3c VS |
4226 | |
4227 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); | |
4228 | if (crtc->config->has_pch_encoder) | |
4229 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
4230 | intel_crtc_pch_transcoder(crtc), true); | |
4231 | } | |
4232 | ||
5c9114d0 SS |
4233 | static void |
4234 | intel_dp_check_link_status(struct intel_dp *intel_dp) | |
4235 | { | |
4236 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; | |
4237 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
4238 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
4239 | ||
4240 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
4241 | ||
4242 | if (!intel_dp_get_link_status(intel_dp, link_status)) { | |
4243 | DRM_ERROR("Failed to get link status\n"); | |
4244 | return; | |
4245 | } | |
4246 | ||
4247 | if (!intel_encoder->base.crtc) | |
4248 | return; | |
4249 | ||
4250 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) | |
4251 | return; | |
4252 | ||
d4cb3fd9 | 4253 | /* FIXME: we need to synchronize this sort of stuff with hardware |
2dd85aeb DV |
4254 | * readout. Currently fast link training doesn't work on boot-up. */ |
4255 | if (!intel_dp->lane_count) | |
d4cb3fd9 MA |
4256 | return; |
4257 | ||
da15f7cb MN |
4258 | /* Retrain if Channel EQ or CR not ok */ |
4259 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { | |
5c9114d0 SS |
4260 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
4261 | intel_encoder->base.name); | |
bfd02b3c VS |
4262 | |
4263 | intel_dp_retrain_link(intel_dp); | |
5c9114d0 SS |
4264 | } |
4265 | } | |
4266 | ||
a4fc5ed6 KP |
4267 | /* |
4268 | * According to DP spec | |
4269 | * 5.1.2: | |
4270 | * 1. Read DPCD | |
4271 | * 2. Configure link according to Receiver Capabilities | |
4272 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
4273 | * 4. Check link status on receipt of hot-plug interrupt | |
39ff747b SS |
4274 | * |
4275 | * intel_dp_short_pulse - handles short pulse interrupts | |
4276 | * when full detection is not required. | |
4277 | * Returns %true if short pulse is handled and full detection | |
4278 | * is NOT required and %false otherwise. | |
a4fc5ed6 | 4279 | */ |
39ff747b | 4280 | static bool |
5c9114d0 | 4281 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
a4fc5ed6 | 4282 | { |
5b215bcf | 4283 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
da15f7cb | 4284 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
65fbb4e7 | 4285 | u8 sink_irq_vector = 0; |
39ff747b SS |
4286 | u8 old_sink_count = intel_dp->sink_count; |
4287 | bool ret; | |
5b215bcf | 4288 | |
4df6960e SS |
4289 | /* |
4290 | * Clearing compliance test variables to allow capturing | |
4291 | * of values for next automated test request. | |
4292 | */ | |
c1617abc | 4293 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
4df6960e | 4294 | |
39ff747b SS |
4295 | /* |
4296 | * Now read the DPCD to see if it's actually running | |
4297 | * If the current value of sink count doesn't match with | |
4298 | * the value that was stored earlier or dpcd read failed | |
4299 | * we need to do full detection | |
4300 | */ | |
4301 | ret = intel_dp_get_dpcd(intel_dp); | |
4302 | ||
4303 | if ((old_sink_count != intel_dp->sink_count) || !ret) { | |
4304 | /* No need to proceed if we are going to do full detect */ | |
4305 | return false; | |
59cd09e1 JB |
4306 | } |
4307 | ||
a60f0e38 JB |
4308 | /* Try to read the source of the interrupt */ |
4309 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
4310 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
4311 | sink_irq_vector != 0) { | |
a60f0e38 | 4312 | /* Clear interrupt source */ |
9d1a1031 JN |
4313 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4314 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4315 | sink_irq_vector); | |
a60f0e38 JB |
4316 | |
4317 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
da15f7cb | 4318 | intel_dp_handle_test_request(intel_dp); |
a60f0e38 JB |
4319 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4320 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4321 | } | |
4322 | ||
5c9114d0 SS |
4323 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
4324 | intel_dp_check_link_status(intel_dp); | |
4325 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
da15f7cb MN |
4326 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { |
4327 | DRM_DEBUG_KMS("Link Training Compliance Test requested\n"); | |
4328 | /* Send a Hotplug Uevent to userspace to start modeset */ | |
4329 | drm_kms_helper_hotplug_event(intel_encoder->base.dev); | |
4330 | } | |
39ff747b SS |
4331 | |
4332 | return true; | |
a4fc5ed6 | 4333 | } |
a4fc5ed6 | 4334 | |
caf9ab24 | 4335 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 4336 | static enum drm_connector_status |
26d61aad | 4337 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 4338 | { |
e393d0d6 | 4339 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
caf9ab24 | 4340 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
4341 | uint8_t type; |
4342 | ||
e393d0d6 ID |
4343 | if (lspcon->active) |
4344 | lspcon_resume(lspcon); | |
4345 | ||
caf9ab24 AJ |
4346 | if (!intel_dp_get_dpcd(intel_dp)) |
4347 | return connector_status_disconnected; | |
4348 | ||
1034ce70 SS |
4349 | if (is_edp(intel_dp)) |
4350 | return connector_status_connected; | |
4351 | ||
caf9ab24 | 4352 | /* if there's no downstream port, we're done */ |
c726ad01 | 4353 | if (!drm_dp_is_branch(dpcd)) |
26d61aad | 4354 | return connector_status_connected; |
caf9ab24 AJ |
4355 | |
4356 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
4357 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4358 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
9d1a1031 | 4359 | |
30d9aa42 SS |
4360 | return intel_dp->sink_count ? |
4361 | connector_status_connected : connector_status_disconnected; | |
caf9ab24 AJ |
4362 | } |
4363 | ||
c4e3170a VS |
4364 | if (intel_dp_can_mst(intel_dp)) |
4365 | return connector_status_connected; | |
4366 | ||
caf9ab24 | 4367 | /* If no HPD, poke DDC gently */ |
0b99836f | 4368 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 4369 | return connector_status_connected; |
caf9ab24 AJ |
4370 | |
4371 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
4372 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4373 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
4374 | if (type == DP_DS_PORT_TYPE_VGA || | |
4375 | type == DP_DS_PORT_TYPE_NON_EDID) | |
4376 | return connector_status_unknown; | |
4377 | } else { | |
4378 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
4379 | DP_DWN_STRM_PORT_TYPE_MASK; | |
4380 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
4381 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
4382 | return connector_status_unknown; | |
4383 | } | |
caf9ab24 AJ |
4384 | |
4385 | /* Anything else is out of spec, warn and ignore */ | |
4386 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 4387 | return connector_status_disconnected; |
71ba9000 AJ |
4388 | } |
4389 | ||
d410b56d CW |
4390 | static enum drm_connector_status |
4391 | edp_detect(struct intel_dp *intel_dp) | |
4392 | { | |
4393 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1650be74 | 4394 | struct drm_i915_private *dev_priv = to_i915(dev); |
d410b56d CW |
4395 | enum drm_connector_status status; |
4396 | ||
1650be74 | 4397 | status = intel_panel_detect(dev_priv); |
d410b56d CW |
4398 | if (status == connector_status_unknown) |
4399 | status = connector_status_connected; | |
4400 | ||
4401 | return status; | |
4402 | } | |
4403 | ||
b93433cc JN |
4404 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
4405 | struct intel_digital_port *port) | |
5eb08b69 | 4406 | { |
b93433cc | 4407 | u32 bit; |
01cb9ea6 | 4408 | |
0df53b77 JN |
4409 | switch (port->port) { |
4410 | case PORT_A: | |
4411 | return true; | |
4412 | case PORT_B: | |
4413 | bit = SDE_PORTB_HOTPLUG; | |
4414 | break; | |
4415 | case PORT_C: | |
4416 | bit = SDE_PORTC_HOTPLUG; | |
4417 | break; | |
4418 | case PORT_D: | |
4419 | bit = SDE_PORTD_HOTPLUG; | |
4420 | break; | |
4421 | default: | |
4422 | MISSING_CASE(port->port); | |
4423 | return false; | |
4424 | } | |
4425 | ||
4426 | return I915_READ(SDEISR) & bit; | |
4427 | } | |
4428 | ||
4429 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, | |
4430 | struct intel_digital_port *port) | |
4431 | { | |
4432 | u32 bit; | |
4433 | ||
4434 | switch (port->port) { | |
4435 | case PORT_A: | |
4436 | return true; | |
4437 | case PORT_B: | |
4438 | bit = SDE_PORTB_HOTPLUG_CPT; | |
4439 | break; | |
4440 | case PORT_C: | |
4441 | bit = SDE_PORTC_HOTPLUG_CPT; | |
4442 | break; | |
4443 | case PORT_D: | |
4444 | bit = SDE_PORTD_HOTPLUG_CPT; | |
4445 | break; | |
a78695d3 JN |
4446 | case PORT_E: |
4447 | bit = SDE_PORTE_HOTPLUG_SPT; | |
4448 | break; | |
0df53b77 JN |
4449 | default: |
4450 | MISSING_CASE(port->port); | |
4451 | return false; | |
b93433cc | 4452 | } |
1b469639 | 4453 | |
b93433cc | 4454 | return I915_READ(SDEISR) & bit; |
5eb08b69 ZW |
4455 | } |
4456 | ||
7e66bcf2 | 4457 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
1d245987 | 4458 | struct intel_digital_port *port) |
a4fc5ed6 | 4459 | { |
9642c81c | 4460 | u32 bit; |
5eb08b69 | 4461 | |
9642c81c JN |
4462 | switch (port->port) { |
4463 | case PORT_B: | |
4464 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; | |
4465 | break; | |
4466 | case PORT_C: | |
4467 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; | |
4468 | break; | |
4469 | case PORT_D: | |
4470 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | |
4471 | break; | |
4472 | default: | |
4473 | MISSING_CASE(port->port); | |
4474 | return false; | |
4475 | } | |
4476 | ||
4477 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
4478 | } | |
4479 | ||
0780cd36 VS |
4480 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
4481 | struct intel_digital_port *port) | |
9642c81c JN |
4482 | { |
4483 | u32 bit; | |
4484 | ||
4485 | switch (port->port) { | |
4486 | case PORT_B: | |
0780cd36 | 4487 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4488 | break; |
4489 | case PORT_C: | |
0780cd36 | 4490 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4491 | break; |
4492 | case PORT_D: | |
0780cd36 | 4493 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4494 | break; |
4495 | default: | |
4496 | MISSING_CASE(port->port); | |
4497 | return false; | |
a4fc5ed6 KP |
4498 | } |
4499 | ||
1d245987 | 4500 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
2a592bec DA |
4501 | } |
4502 | ||
e464bfde | 4503 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
e2ec35a5 | 4504 | struct intel_digital_port *intel_dig_port) |
e464bfde | 4505 | { |
e2ec35a5 SJ |
4506 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4507 | enum port port; | |
e464bfde JN |
4508 | u32 bit; |
4509 | ||
e2ec35a5 SJ |
4510 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
4511 | switch (port) { | |
e464bfde JN |
4512 | case PORT_A: |
4513 | bit = BXT_DE_PORT_HP_DDIA; | |
4514 | break; | |
4515 | case PORT_B: | |
4516 | bit = BXT_DE_PORT_HP_DDIB; | |
4517 | break; | |
4518 | case PORT_C: | |
4519 | bit = BXT_DE_PORT_HP_DDIC; | |
4520 | break; | |
4521 | default: | |
e2ec35a5 | 4522 | MISSING_CASE(port); |
e464bfde JN |
4523 | return false; |
4524 | } | |
4525 | ||
4526 | return I915_READ(GEN8_DE_PORT_ISR) & bit; | |
4527 | } | |
4528 | ||
7e66bcf2 JN |
4529 | /* |
4530 | * intel_digital_port_connected - is the specified port connected? | |
4531 | * @dev_priv: i915 private structure | |
4532 | * @port: the port to test | |
4533 | * | |
4534 | * Return %true if @port is connected, %false otherwise. | |
4535 | */ | |
390b4e00 ID |
4536 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
4537 | struct intel_digital_port *port) | |
7e66bcf2 | 4538 | { |
0df53b77 | 4539 | if (HAS_PCH_IBX(dev_priv)) |
7e66bcf2 | 4540 | return ibx_digital_port_connected(dev_priv, port); |
22824fac | 4541 | else if (HAS_PCH_SPLIT(dev_priv)) |
0df53b77 | 4542 | return cpt_digital_port_connected(dev_priv, port); |
cc3f90f0 | 4543 | else if (IS_GEN9_LP(dev_priv)) |
e464bfde | 4544 | return bxt_digital_port_connected(dev_priv, port); |
0780cd36 VS |
4545 | else if (IS_GM45(dev_priv)) |
4546 | return gm45_digital_port_connected(dev_priv, port); | |
7e66bcf2 JN |
4547 | else |
4548 | return g4x_digital_port_connected(dev_priv, port); | |
4549 | } | |
4550 | ||
8c241fef | 4551 | static struct edid * |
beb60608 | 4552 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 4553 | { |
beb60608 | 4554 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
d6f24d0f | 4555 | |
9cd300e0 JN |
4556 | /* use cached edid if we have one */ |
4557 | if (intel_connector->edid) { | |
9cd300e0 JN |
4558 | /* invalid edid */ |
4559 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
4560 | return NULL; |
4561 | ||
55e9edeb | 4562 | return drm_edid_duplicate(intel_connector->edid); |
beb60608 CW |
4563 | } else |
4564 | return drm_get_edid(&intel_connector->base, | |
4565 | &intel_dp->aux.ddc); | |
4566 | } | |
8c241fef | 4567 | |
beb60608 CW |
4568 | static void |
4569 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
4570 | { | |
4571 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
4572 | struct edid *edid; | |
8c241fef | 4573 | |
f21a2198 | 4574 | intel_dp_unset_edid(intel_dp); |
beb60608 CW |
4575 | edid = intel_dp_get_edid(intel_dp); |
4576 | intel_connector->detect_edid = edid; | |
4577 | ||
4578 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) | |
4579 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; | |
4580 | else | |
4581 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
8c241fef KP |
4582 | } |
4583 | ||
beb60608 CW |
4584 | static void |
4585 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 4586 | { |
beb60608 | 4587 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8c241fef | 4588 | |
beb60608 CW |
4589 | kfree(intel_connector->detect_edid); |
4590 | intel_connector->detect_edid = NULL; | |
9cd300e0 | 4591 | |
beb60608 CW |
4592 | intel_dp->has_audio = false; |
4593 | } | |
d6f24d0f | 4594 | |
5cb651a7 | 4595 | static enum drm_connector_status |
f21a2198 | 4596 | intel_dp_long_pulse(struct intel_connector *intel_connector) |
a9756bb5 | 4597 | { |
f21a2198 | 4598 | struct drm_connector *connector = &intel_connector->base; |
a9756bb5 | 4599 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
d63885da PZ |
4600 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4601 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 4602 | struct drm_device *dev = connector->dev; |
a9756bb5 | 4603 | enum drm_connector_status status; |
65fbb4e7 | 4604 | u8 sink_irq_vector = 0; |
a9756bb5 | 4605 | |
5432fcaf | 4606 | intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain); |
a9756bb5 | 4607 | |
d410b56d CW |
4608 | /* Can't disconnect eDP, but you can close the lid... */ |
4609 | if (is_edp(intel_dp)) | |
4610 | status = edp_detect(intel_dp); | |
c555a81d ACO |
4611 | else if (intel_digital_port_connected(to_i915(dev), |
4612 | dp_to_dig_port(intel_dp))) | |
4613 | status = intel_dp_detect_dpcd(intel_dp); | |
a9756bb5 | 4614 | else |
c555a81d ACO |
4615 | status = connector_status_disconnected; |
4616 | ||
5cb651a7 | 4617 | if (status == connector_status_disconnected) { |
c1617abc | 4618 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
4df6960e | 4619 | |
0e505a08 | 4620 | if (intel_dp->is_mst) { |
4621 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4622 | intel_dp->is_mst, | |
4623 | intel_dp->mst_mgr.mst_state); | |
4624 | intel_dp->is_mst = false; | |
4625 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4626 | intel_dp->is_mst); | |
4627 | } | |
4628 | ||
c8c8fb33 | 4629 | goto out; |
4df6960e | 4630 | } |
a9756bb5 | 4631 | |
f21a2198 | 4632 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
cca0502b | 4633 | intel_encoder->type = INTEL_OUTPUT_DP; |
f21a2198 | 4634 | |
fe5a66f9 VS |
4635 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
4636 | yesno(intel_dp_source_supports_hbr2(intel_dp)), | |
4637 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); | |
4638 | ||
d7e8ef02 MN |
4639 | if (intel_dp->reset_link_params) { |
4640 | /* Set the max lane count for sink */ | |
4641 | intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); | |
f482984a | 4642 | |
a079d108 JN |
4643 | /* Set the max link rate for sink */ |
4644 | intel_dp->max_sink_link_rate = intel_dp_max_sink_rate(intel_dp); | |
d7e8ef02 MN |
4645 | |
4646 | intel_dp->reset_link_params = false; | |
4647 | } | |
f482984a | 4648 | |
fe5a66f9 VS |
4649 | intel_dp_print_rates(intel_dp); |
4650 | ||
7b3fc170 | 4651 | intel_dp_read_desc(intel_dp); |
0e390a33 | 4652 | |
c4e3170a VS |
4653 | intel_dp_configure_mst(intel_dp); |
4654 | ||
4655 | if (intel_dp->is_mst) { | |
f21a2198 SS |
4656 | /* |
4657 | * If we are in MST mode then this connector | |
4658 | * won't appear connected or have anything | |
4659 | * with EDID on it | |
4660 | */ | |
0e32b39c DA |
4661 | status = connector_status_disconnected; |
4662 | goto out; | |
7d23e3c3 SS |
4663 | } else if (connector->status == connector_status_connected) { |
4664 | /* | |
4665 | * If display was connected already and is still connected | |
4666 | * check links status, there has been known issues of | |
4667 | * link loss triggerring long pulse!!!! | |
4668 | */ | |
4669 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); | |
4670 | intel_dp_check_link_status(intel_dp); | |
4671 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
4672 | goto out; | |
0e32b39c DA |
4673 | } |
4674 | ||
4df6960e SS |
4675 | /* |
4676 | * Clearing NACK and defer counts to get their exact values | |
4677 | * while reading EDID which are required by Compliance tests | |
4678 | * 4.2.2.4 and 4.2.2.5 | |
4679 | */ | |
4680 | intel_dp->aux.i2c_nack_count = 0; | |
4681 | intel_dp->aux.i2c_defer_count = 0; | |
4682 | ||
beb60608 | 4683 | intel_dp_set_edid(intel_dp); |
5cb651a7 VS |
4684 | if (is_edp(intel_dp) || intel_connector->detect_edid) |
4685 | status = connector_status_connected; | |
7d23e3c3 | 4686 | intel_dp->detect_done = true; |
c8c8fb33 | 4687 | |
09b1eb13 TP |
4688 | /* Try to read the source of the interrupt */ |
4689 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
4690 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
4691 | sink_irq_vector != 0) { | |
09b1eb13 TP |
4692 | /* Clear interrupt source */ |
4693 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
4694 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4695 | sink_irq_vector); | |
4696 | ||
4697 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
4698 | intel_dp_handle_test_request(intel_dp); | |
4699 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
4700 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4701 | } | |
4702 | ||
c8c8fb33 | 4703 | out: |
5cb651a7 | 4704 | if (status != connector_status_connected && !intel_dp->is_mst) |
f21a2198 | 4705 | intel_dp_unset_edid(intel_dp); |
7d23e3c3 | 4706 | |
5432fcaf | 4707 | intel_display_power_put(to_i915(dev), intel_dp->aux_power_domain); |
5cb651a7 | 4708 | return status; |
f21a2198 SS |
4709 | } |
4710 | ||
4711 | static enum drm_connector_status | |
4712 | intel_dp_detect(struct drm_connector *connector, bool force) | |
4713 | { | |
4714 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
5cb651a7 | 4715 | enum drm_connector_status status = connector->status; |
f21a2198 SS |
4716 | |
4717 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4718 | connector->base.id, connector->name); | |
4719 | ||
7d23e3c3 SS |
4720 | /* If full detect is not performed yet, do a full detect */ |
4721 | if (!intel_dp->detect_done) | |
5cb651a7 | 4722 | status = intel_dp_long_pulse(intel_dp->attached_connector); |
7d23e3c3 SS |
4723 | |
4724 | intel_dp->detect_done = false; | |
f21a2198 | 4725 | |
5cb651a7 | 4726 | return status; |
a4fc5ed6 KP |
4727 | } |
4728 | ||
beb60608 CW |
4729 | static void |
4730 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 4731 | { |
df0e9248 | 4732 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
beb60608 | 4733 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
25f78f58 | 4734 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
a4fc5ed6 | 4735 | |
beb60608 CW |
4736 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4737 | connector->base.id, connector->name); | |
4738 | intel_dp_unset_edid(intel_dp); | |
a4fc5ed6 | 4739 | |
beb60608 CW |
4740 | if (connector->status != connector_status_connected) |
4741 | return; | |
671dedd2 | 4742 | |
5432fcaf | 4743 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
beb60608 CW |
4744 | |
4745 | intel_dp_set_edid(intel_dp); | |
4746 | ||
5432fcaf | 4747 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
beb60608 CW |
4748 | |
4749 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
cca0502b | 4750 | intel_encoder->type = INTEL_OUTPUT_DP; |
beb60608 CW |
4751 | } |
4752 | ||
4753 | static int intel_dp_get_modes(struct drm_connector *connector) | |
4754 | { | |
4755 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4756 | struct edid *edid; | |
4757 | ||
4758 | edid = intel_connector->detect_edid; | |
4759 | if (edid) { | |
4760 | int ret = intel_connector_update_modes(connector, edid); | |
4761 | if (ret) | |
4762 | return ret; | |
4763 | } | |
32f9d658 | 4764 | |
f8779fda | 4765 | /* if eDP has no EDID, fall back to fixed mode */ |
beb60608 CW |
4766 | if (is_edp(intel_attached_dp(connector)) && |
4767 | intel_connector->panel.fixed_mode) { | |
f8779fda | 4768 | struct drm_display_mode *mode; |
beb60608 CW |
4769 | |
4770 | mode = drm_mode_duplicate(connector->dev, | |
dd06f90e | 4771 | intel_connector->panel.fixed_mode); |
f8779fda | 4772 | if (mode) { |
32f9d658 ZW |
4773 | drm_mode_probed_add(connector, mode); |
4774 | return 1; | |
4775 | } | |
4776 | } | |
beb60608 | 4777 | |
32f9d658 | 4778 | return 0; |
a4fc5ed6 KP |
4779 | } |
4780 | ||
1aad7ac0 CW |
4781 | static bool |
4782 | intel_dp_detect_audio(struct drm_connector *connector) | |
4783 | { | |
1aad7ac0 | 4784 | bool has_audio = false; |
beb60608 | 4785 | struct edid *edid; |
1aad7ac0 | 4786 | |
beb60608 CW |
4787 | edid = to_intel_connector(connector)->detect_edid; |
4788 | if (edid) | |
1aad7ac0 | 4789 | has_audio = drm_detect_monitor_audio(edid); |
671dedd2 | 4790 | |
1aad7ac0 CW |
4791 | return has_audio; |
4792 | } | |
4793 | ||
f684960e CW |
4794 | static int |
4795 | intel_dp_set_property(struct drm_connector *connector, | |
4796 | struct drm_property *property, | |
4797 | uint64_t val) | |
4798 | { | |
fac5e23e | 4799 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
53b41837 | 4800 | struct intel_connector *intel_connector = to_intel_connector(connector); |
da63a9f2 PZ |
4801 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
4802 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
f684960e CW |
4803 | int ret; |
4804 | ||
662595df | 4805 | ret = drm_object_property_set_value(&connector->base, property, val); |
f684960e CW |
4806 | if (ret) |
4807 | return ret; | |
4808 | ||
3f43c48d | 4809 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
4810 | int i = val; |
4811 | bool has_audio; | |
4812 | ||
4813 | if (i == intel_dp->force_audio) | |
f684960e CW |
4814 | return 0; |
4815 | ||
1aad7ac0 | 4816 | intel_dp->force_audio = i; |
f684960e | 4817 | |
c3e5f67b | 4818 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
4819 | has_audio = intel_dp_detect_audio(connector); |
4820 | else | |
c3e5f67b | 4821 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
4822 | |
4823 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
4824 | return 0; |
4825 | ||
1aad7ac0 | 4826 | intel_dp->has_audio = has_audio; |
f684960e CW |
4827 | goto done; |
4828 | } | |
4829 | ||
e953fd7b | 4830 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 | 4831 | bool old_auto = intel_dp->color_range_auto; |
0f2a2a75 | 4832 | bool old_range = intel_dp->limited_color_range; |
ae4edb80 | 4833 | |
55bc60db VS |
4834 | switch (val) { |
4835 | case INTEL_BROADCAST_RGB_AUTO: | |
4836 | intel_dp->color_range_auto = true; | |
4837 | break; | |
4838 | case INTEL_BROADCAST_RGB_FULL: | |
4839 | intel_dp->color_range_auto = false; | |
0f2a2a75 | 4840 | intel_dp->limited_color_range = false; |
55bc60db VS |
4841 | break; |
4842 | case INTEL_BROADCAST_RGB_LIMITED: | |
4843 | intel_dp->color_range_auto = false; | |
0f2a2a75 | 4844 | intel_dp->limited_color_range = true; |
55bc60db VS |
4845 | break; |
4846 | default: | |
4847 | return -EINVAL; | |
4848 | } | |
ae4edb80 DV |
4849 | |
4850 | if (old_auto == intel_dp->color_range_auto && | |
0f2a2a75 | 4851 | old_range == intel_dp->limited_color_range) |
ae4edb80 DV |
4852 | return 0; |
4853 | ||
e953fd7b CW |
4854 | goto done; |
4855 | } | |
4856 | ||
53b41837 YN |
4857 | if (is_edp(intel_dp) && |
4858 | property == connector->dev->mode_config.scaling_mode_property) { | |
4859 | if (val == DRM_MODE_SCALE_NONE) { | |
4860 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
4861 | return -EINVAL; | |
4862 | } | |
234126c6 VS |
4863 | if (HAS_GMCH_DISPLAY(dev_priv) && |
4864 | val == DRM_MODE_SCALE_CENTER) { | |
4865 | DRM_DEBUG_KMS("centering not supported\n"); | |
4866 | return -EINVAL; | |
4867 | } | |
53b41837 YN |
4868 | |
4869 | if (intel_connector->panel.fitting_mode == val) { | |
4870 | /* the eDP scaling property is not changed */ | |
4871 | return 0; | |
4872 | } | |
4873 | intel_connector->panel.fitting_mode = val; | |
4874 | ||
4875 | goto done; | |
4876 | } | |
4877 | ||
f684960e CW |
4878 | return -EINVAL; |
4879 | ||
4880 | done: | |
c0c36b94 CW |
4881 | if (intel_encoder->base.crtc) |
4882 | intel_crtc_restore_mode(intel_encoder->base.crtc); | |
f684960e CW |
4883 | |
4884 | return 0; | |
4885 | } | |
4886 | ||
7a418e34 CW |
4887 | static int |
4888 | intel_dp_connector_register(struct drm_connector *connector) | |
4889 | { | |
4890 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1ebaa0b9 CW |
4891 | int ret; |
4892 | ||
4893 | ret = intel_connector_register(connector); | |
4894 | if (ret) | |
4895 | return ret; | |
7a418e34 CW |
4896 | |
4897 | i915_debugfs_connector_add(connector); | |
4898 | ||
4899 | DRM_DEBUG_KMS("registering %s bus for %s\n", | |
4900 | intel_dp->aux.name, connector->kdev->kobj.name); | |
4901 | ||
4902 | intel_dp->aux.dev = connector->kdev; | |
4903 | return drm_dp_aux_register(&intel_dp->aux); | |
4904 | } | |
4905 | ||
c191eca1 CW |
4906 | static void |
4907 | intel_dp_connector_unregister(struct drm_connector *connector) | |
4908 | { | |
4909 | drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); | |
4910 | intel_connector_unregister(connector); | |
4911 | } | |
4912 | ||
a4fc5ed6 | 4913 | static void |
73845adf | 4914 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 4915 | { |
1d508706 | 4916 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 4917 | |
10e972d3 | 4918 | kfree(intel_connector->detect_edid); |
beb60608 | 4919 | |
9cd300e0 JN |
4920 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4921 | kfree(intel_connector->edid); | |
4922 | ||
acd8db10 PZ |
4923 | /* Can't call is_edp() since the encoder may have been destroyed |
4924 | * already. */ | |
4925 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
1d508706 | 4926 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 4927 | |
a4fc5ed6 | 4928 | drm_connector_cleanup(connector); |
55f78c43 | 4929 | kfree(connector); |
a4fc5ed6 KP |
4930 | } |
4931 | ||
00c09d70 | 4932 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 4933 | { |
da63a9f2 PZ |
4934 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4935 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
24d05927 | 4936 | |
0e32b39c | 4937 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
bd943159 KP |
4938 | if (is_edp(intel_dp)) { |
4939 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
951468f3 VS |
4940 | /* |
4941 | * vdd might still be enabled do to the delayed vdd off. | |
4942 | * Make sure vdd is actually turned off here. | |
4943 | */ | |
773538e8 | 4944 | pps_lock(intel_dp); |
4be73780 | 4945 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 VS |
4946 | pps_unlock(intel_dp); |
4947 | ||
01527b31 CT |
4948 | if (intel_dp->edp_notifier.notifier_call) { |
4949 | unregister_reboot_notifier(&intel_dp->edp_notifier); | |
4950 | intel_dp->edp_notifier.notifier_call = NULL; | |
4951 | } | |
bd943159 | 4952 | } |
99681886 CW |
4953 | |
4954 | intel_dp_aux_fini(intel_dp); | |
4955 | ||
c8bd0e49 | 4956 | drm_encoder_cleanup(encoder); |
da63a9f2 | 4957 | kfree(intel_dig_port); |
24d05927 DV |
4958 | } |
4959 | ||
bf93ba67 | 4960 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
07f9cd0b ID |
4961 | { |
4962 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
4963 | ||
4964 | if (!is_edp(intel_dp)) | |
4965 | return; | |
4966 | ||
951468f3 VS |
4967 | /* |
4968 | * vdd might still be enabled do to the delayed vdd off. | |
4969 | * Make sure vdd is actually turned off here. | |
4970 | */ | |
afa4e53a | 4971 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
773538e8 | 4972 | pps_lock(intel_dp); |
07f9cd0b | 4973 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 | 4974 | pps_unlock(intel_dp); |
07f9cd0b ID |
4975 | } |
4976 | ||
49e6bc51 VS |
4977 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
4978 | { | |
4979 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4980 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 4981 | struct drm_i915_private *dev_priv = to_i915(dev); |
49e6bc51 VS |
4982 | |
4983 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4984 | ||
4985 | if (!edp_have_panel_vdd(intel_dp)) | |
4986 | return; | |
4987 | ||
4988 | /* | |
4989 | * The VDD bit needs a power domain reference, so if the bit is | |
4990 | * already enabled when we boot or resume, grab this reference and | |
4991 | * schedule a vdd off, so we don't hold on to the reference | |
4992 | * indefinitely. | |
4993 | */ | |
4994 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); | |
5432fcaf | 4995 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
49e6bc51 VS |
4996 | |
4997 | edp_panel_vdd_schedule_off(intel_dp); | |
4998 | } | |
4999 | ||
9f2bdb00 VS |
5000 | static enum pipe vlv_active_pipe(struct intel_dp *intel_dp) |
5001 | { | |
5002 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); | |
5003 | ||
5004 | if ((intel_dp->DP & DP_PORT_EN) == 0) | |
5005 | return INVALID_PIPE; | |
5006 | ||
5007 | if (IS_CHERRYVIEW(dev_priv)) | |
5008 | return DP_PORT_TO_PIPE_CHV(intel_dp->DP); | |
5009 | else | |
5010 | return PORT_TO_PIPE(intel_dp->DP); | |
5011 | } | |
5012 | ||
bf93ba67 | 5013 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
6d93c0c4 | 5014 | { |
64989ca4 | 5015 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
dd75f6dd ID |
5016 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
5017 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); | |
64989ca4 VS |
5018 | |
5019 | if (!HAS_DDI(dev_priv)) | |
5020 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
49e6bc51 | 5021 | |
dd75f6dd | 5022 | if (lspcon->active) |
910530c0 SS |
5023 | lspcon_resume(lspcon); |
5024 | ||
d7e8ef02 MN |
5025 | intel_dp->reset_link_params = true; |
5026 | ||
49e6bc51 VS |
5027 | pps_lock(intel_dp); |
5028 | ||
9f2bdb00 VS |
5029 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
5030 | intel_dp->active_pipe = vlv_active_pipe(intel_dp); | |
5031 | ||
5032 | if (is_edp(intel_dp)) { | |
5033 | /* Reinit the power sequencer, in case BIOS did something with it. */ | |
5034 | intel_dp_pps_init(encoder->dev, intel_dp); | |
5035 | intel_edp_panel_vdd_sanitize(intel_dp); | |
5036 | } | |
49e6bc51 VS |
5037 | |
5038 | pps_unlock(intel_dp); | |
6d93c0c4 ID |
5039 | } |
5040 | ||
a4fc5ed6 | 5041 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
4d688a2a | 5042 | .dpms = drm_atomic_helper_connector_dpms, |
a4fc5ed6 | 5043 | .detect = intel_dp_detect, |
beb60608 | 5044 | .force = intel_dp_force, |
a4fc5ed6 | 5045 | .fill_modes = drm_helper_probe_single_connector_modes, |
f684960e | 5046 | .set_property = intel_dp_set_property, |
2545e4a6 | 5047 | .atomic_get_property = intel_connector_atomic_get_property, |
7a418e34 | 5048 | .late_register = intel_dp_connector_register, |
c191eca1 | 5049 | .early_unregister = intel_dp_connector_unregister, |
73845adf | 5050 | .destroy = intel_dp_connector_destroy, |
c6f95f27 | 5051 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 5052 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
a4fc5ed6 KP |
5053 | }; |
5054 | ||
5055 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
5056 | .get_modes = intel_dp_get_modes, | |
5057 | .mode_valid = intel_dp_mode_valid, | |
a4fc5ed6 KP |
5058 | }; |
5059 | ||
a4fc5ed6 | 5060 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
6d93c0c4 | 5061 | .reset = intel_dp_encoder_reset, |
24d05927 | 5062 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
5063 | }; |
5064 | ||
b2c5c181 | 5065 | enum irqreturn |
13cf5504 DA |
5066 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
5067 | { | |
5068 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
0e32b39c | 5069 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 5070 | struct drm_i915_private *dev_priv = to_i915(dev); |
b2c5c181 | 5071 | enum irqreturn ret = IRQ_NONE; |
1c767b33 | 5072 | |
2540058f TI |
5073 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
5074 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) | |
cca0502b | 5075 | intel_dig_port->base.type = INTEL_OUTPUT_DP; |
13cf5504 | 5076 | |
7a7f84cc VS |
5077 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
5078 | /* | |
5079 | * vdd off can generate a long pulse on eDP which | |
5080 | * would require vdd on to handle it, and thus we | |
5081 | * would end up in an endless cycle of | |
5082 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." | |
5083 | */ | |
5084 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", | |
5085 | port_name(intel_dig_port->port)); | |
a8b3d52f | 5086 | return IRQ_HANDLED; |
7a7f84cc VS |
5087 | } |
5088 | ||
26fbb774 VS |
5089 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
5090 | port_name(intel_dig_port->port), | |
0e32b39c | 5091 | long_hpd ? "long" : "short"); |
13cf5504 | 5092 | |
27d4efc5 | 5093 | if (long_hpd) { |
d7e8ef02 | 5094 | intel_dp->reset_link_params = true; |
27d4efc5 VS |
5095 | intel_dp->detect_done = false; |
5096 | return IRQ_NONE; | |
5097 | } | |
5098 | ||
5432fcaf | 5099 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
1c767b33 | 5100 | |
27d4efc5 VS |
5101 | if (intel_dp->is_mst) { |
5102 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { | |
5103 | /* | |
5104 | * If we were in MST mode, and device is not | |
5105 | * there, get out of MST mode | |
5106 | */ | |
5107 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
5108 | intel_dp->is_mst, intel_dp->mst_mgr.mst_state); | |
5109 | intel_dp->is_mst = false; | |
5110 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
5111 | intel_dp->is_mst); | |
5112 | intel_dp->detect_done = false; | |
5113 | goto put_power; | |
0e32b39c | 5114 | } |
27d4efc5 | 5115 | } |
0e32b39c | 5116 | |
27d4efc5 VS |
5117 | if (!intel_dp->is_mst) { |
5118 | if (!intel_dp_short_pulse(intel_dp)) { | |
5119 | intel_dp->detect_done = false; | |
5120 | goto put_power; | |
39ff747b | 5121 | } |
0e32b39c | 5122 | } |
b2c5c181 DV |
5123 | |
5124 | ret = IRQ_HANDLED; | |
5125 | ||
1c767b33 | 5126 | put_power: |
5432fcaf | 5127 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
1c767b33 ID |
5128 | |
5129 | return ret; | |
13cf5504 DA |
5130 | } |
5131 | ||
477ec328 | 5132 | /* check the VBT to see whether the eDP is on another port */ |
dd11bc10 | 5133 | bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port) |
36e83a18 | 5134 | { |
53ce81a7 VS |
5135 | /* |
5136 | * eDP not supported on g4x. so bail out early just | |
5137 | * for a bit extra safety in case the VBT is bonkers. | |
5138 | */ | |
dd11bc10 | 5139 | if (INTEL_GEN(dev_priv) < 5) |
53ce81a7 VS |
5140 | return false; |
5141 | ||
a98d9c1d | 5142 | if (INTEL_GEN(dev_priv) < 9 && port == PORT_A) |
3b32a35b VS |
5143 | return true; |
5144 | ||
951d9efe | 5145 | return intel_bios_is_port_edp(dev_priv, port); |
36e83a18 ZY |
5146 | } |
5147 | ||
0e32b39c | 5148 | void |
f684960e CW |
5149 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
5150 | { | |
53b41837 YN |
5151 | struct intel_connector *intel_connector = to_intel_connector(connector); |
5152 | ||
3f43c48d | 5153 | intel_attach_force_audio_property(connector); |
e953fd7b | 5154 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 5155 | intel_dp->color_range_auto = true; |
53b41837 YN |
5156 | |
5157 | if (is_edp(intel_dp)) { | |
5158 | drm_mode_create_scaling_mode_property(connector->dev); | |
6de6d846 RC |
5159 | drm_object_attach_property( |
5160 | &connector->base, | |
53b41837 | 5161 | connector->dev->mode_config.scaling_mode_property, |
8e740cd1 YN |
5162 | DRM_MODE_SCALE_ASPECT); |
5163 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
53b41837 | 5164 | } |
f684960e CW |
5165 | } |
5166 | ||
dada1a9f ID |
5167 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
5168 | { | |
d28d4731 | 5169 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
dada1a9f ID |
5170 | intel_dp->last_power_on = jiffies; |
5171 | intel_dp->last_backlight_off = jiffies; | |
5172 | } | |
5173 | ||
67a54566 | 5174 | static void |
54648618 ID |
5175 | intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, |
5176 | struct intel_dp *intel_dp, struct edp_power_seq *seq) | |
67a54566 | 5177 | { |
b0a08bec | 5178 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
8e8232d5 | 5179 | struct pps_registers regs; |
453c5420 | 5180 | |
8e8232d5 | 5181 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
67a54566 DV |
5182 | |
5183 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
5184 | * the very first thing. */ | |
b0a08bec | 5185 | pp_ctl = ironlake_get_pp_control(intel_dp); |
67a54566 | 5186 | |
8e8232d5 ID |
5187 | pp_on = I915_READ(regs.pp_on); |
5188 | pp_off = I915_READ(regs.pp_off); | |
cc3f90f0 | 5189 | if (!IS_GEN9_LP(dev_priv)) { |
8e8232d5 ID |
5190 | I915_WRITE(regs.pp_ctrl, pp_ctl); |
5191 | pp_div = I915_READ(regs.pp_div); | |
b0a08bec | 5192 | } |
67a54566 DV |
5193 | |
5194 | /* Pull timing values out of registers */ | |
54648618 ID |
5195 | seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
5196 | PANEL_POWER_UP_DELAY_SHIFT; | |
67a54566 | 5197 | |
54648618 ID |
5198 | seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
5199 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
67a54566 | 5200 | |
54648618 ID |
5201 | seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
5202 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
67a54566 | 5203 | |
54648618 ID |
5204 | seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
5205 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
67a54566 | 5206 | |
cc3f90f0 | 5207 | if (IS_GEN9_LP(dev_priv)) { |
b0a08bec VK |
5208 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
5209 | BXT_POWER_CYCLE_DELAY_SHIFT; | |
5210 | if (tmp > 0) | |
54648618 | 5211 | seq->t11_t12 = (tmp - 1) * 1000; |
b0a08bec | 5212 | else |
54648618 | 5213 | seq->t11_t12 = 0; |
b0a08bec | 5214 | } else { |
54648618 | 5215 | seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
67a54566 | 5216 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
b0a08bec | 5217 | } |
54648618 ID |
5218 | } |
5219 | ||
de9c1b6b ID |
5220 | static void |
5221 | intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) | |
5222 | { | |
5223 | DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
5224 | state_name, | |
5225 | seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); | |
5226 | } | |
5227 | ||
5228 | static void | |
5229 | intel_pps_verify_state(struct drm_i915_private *dev_priv, | |
5230 | struct intel_dp *intel_dp) | |
5231 | { | |
5232 | struct edp_power_seq hw; | |
5233 | struct edp_power_seq *sw = &intel_dp->pps_delays; | |
5234 | ||
5235 | intel_pps_readout_hw_state(dev_priv, intel_dp, &hw); | |
5236 | ||
5237 | if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || | |
5238 | hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { | |
5239 | DRM_ERROR("PPS state mismatch\n"); | |
5240 | intel_pps_dump_state("sw", sw); | |
5241 | intel_pps_dump_state("hw", &hw); | |
5242 | } | |
5243 | } | |
5244 | ||
54648618 ID |
5245 | static void |
5246 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
5247 | struct intel_dp *intel_dp) | |
5248 | { | |
fac5e23e | 5249 | struct drm_i915_private *dev_priv = to_i915(dev); |
54648618 ID |
5250 | struct edp_power_seq cur, vbt, spec, |
5251 | *final = &intel_dp->pps_delays; | |
5252 | ||
5253 | lockdep_assert_held(&dev_priv->pps_mutex); | |
5254 | ||
5255 | /* already initialized? */ | |
5256 | if (final->t11_t12 != 0) | |
5257 | return; | |
5258 | ||
5259 | intel_pps_readout_hw_state(dev_priv, intel_dp, &cur); | |
67a54566 | 5260 | |
de9c1b6b | 5261 | intel_pps_dump_state("cur", &cur); |
67a54566 | 5262 | |
6aa23e65 | 5263 | vbt = dev_priv->vbt.edp.pps; |
67a54566 DV |
5264 | |
5265 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
5266 | * our hw here, which are all in 100usec. */ | |
5267 | spec.t1_t3 = 210 * 10; | |
5268 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
5269 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
5270 | spec.t10 = 500 * 10; | |
5271 | /* This one is special and actually in units of 100ms, but zero | |
5272 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
5273 | * table multiplies it with 1000 to make it in units of 100usec, | |
5274 | * too. */ | |
5275 | spec.t11_t12 = (510 + 100) * 10; | |
5276 | ||
de9c1b6b | 5277 | intel_pps_dump_state("vbt", &vbt); |
67a54566 DV |
5278 | |
5279 | /* Use the max of the register settings and vbt. If both are | |
5280 | * unset, fall back to the spec limits. */ | |
36b5f425 | 5281 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
67a54566 DV |
5282 | spec.field : \ |
5283 | max(cur.field, vbt.field)) | |
5284 | assign_final(t1_t3); | |
5285 | assign_final(t8); | |
5286 | assign_final(t9); | |
5287 | assign_final(t10); | |
5288 | assign_final(t11_t12); | |
5289 | #undef assign_final | |
5290 | ||
36b5f425 | 5291 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
67a54566 DV |
5292 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
5293 | intel_dp->backlight_on_delay = get_delay(t8); | |
5294 | intel_dp->backlight_off_delay = get_delay(t9); | |
5295 | intel_dp->panel_power_down_delay = get_delay(t10); | |
5296 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
5297 | #undef get_delay | |
5298 | ||
f30d26e4 JN |
5299 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
5300 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
5301 | intel_dp->panel_power_cycle_delay); | |
5302 | ||
5303 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
5304 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
de9c1b6b ID |
5305 | |
5306 | /* | |
5307 | * We override the HW backlight delays to 1 because we do manual waits | |
5308 | * on them. For T8, even BSpec recommends doing it. For T9, if we | |
5309 | * don't do this, we'll end up waiting for the backlight off delay | |
5310 | * twice: once when we do the manual sleep, and once when we disable | |
5311 | * the panel and wait for the PP_STATUS bit to become zero. | |
5312 | */ | |
5313 | final->t8 = 1; | |
5314 | final->t9 = 1; | |
f30d26e4 JN |
5315 | } |
5316 | ||
5317 | static void | |
5318 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
5d5ab2d2 VS |
5319 | struct intel_dp *intel_dp, |
5320 | bool force_disable_vdd) | |
f30d26e4 | 5321 | { |
fac5e23e | 5322 | struct drm_i915_private *dev_priv = to_i915(dev); |
453c5420 | 5323 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
e7dc33f3 | 5324 | int div = dev_priv->rawclk_freq / 1000; |
8e8232d5 | 5325 | struct pps_registers regs; |
ad933b56 | 5326 | enum port port = dp_to_dig_port(intel_dp)->port; |
36b5f425 | 5327 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
453c5420 | 5328 | |
e39b999a | 5329 | lockdep_assert_held(&dev_priv->pps_mutex); |
453c5420 | 5330 | |
8e8232d5 | 5331 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
453c5420 | 5332 | |
5d5ab2d2 VS |
5333 | /* |
5334 | * On some VLV machines the BIOS can leave the VDD | |
5335 | * enabled even on power seqeuencers which aren't | |
5336 | * hooked up to any port. This would mess up the | |
5337 | * power domain tracking the first time we pick | |
5338 | * one of these power sequencers for use since | |
5339 | * edp_panel_vdd_on() would notice that the VDD was | |
5340 | * already on and therefore wouldn't grab the power | |
5341 | * domain reference. Disable VDD first to avoid this. | |
5342 | * This also avoids spuriously turning the VDD on as | |
5343 | * soon as the new power seqeuencer gets initialized. | |
5344 | */ | |
5345 | if (force_disable_vdd) { | |
5346 | u32 pp = ironlake_get_pp_control(intel_dp); | |
5347 | ||
5348 | WARN(pp & PANEL_POWER_ON, "Panel power already on\n"); | |
5349 | ||
5350 | if (pp & EDP_FORCE_VDD) | |
5351 | DRM_DEBUG_KMS("VDD already on, disabling first\n"); | |
5352 | ||
5353 | pp &= ~EDP_FORCE_VDD; | |
5354 | ||
5355 | I915_WRITE(regs.pp_ctrl, pp); | |
5356 | } | |
5357 | ||
f30d26e4 | 5358 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
de9c1b6b ID |
5359 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
5360 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 5361 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
5362 | /* Compute the divisor for the pp clock, simply match the Bspec |
5363 | * formula. */ | |
cc3f90f0 | 5364 | if (IS_GEN9_LP(dev_priv)) { |
8e8232d5 | 5365 | pp_div = I915_READ(regs.pp_ctrl); |
b0a08bec VK |
5366 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
5367 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) | |
5368 | << BXT_POWER_CYCLE_DELAY_SHIFT); | |
5369 | } else { | |
5370 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; | |
5371 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) | |
5372 | << PANEL_POWER_CYCLE_DELAY_SHIFT); | |
5373 | } | |
67a54566 DV |
5374 | |
5375 | /* Haswell doesn't have any port selection bits for the panel | |
5376 | * power sequencer any more. */ | |
920a14b2 | 5377 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
ad933b56 | 5378 | port_sel = PANEL_PORT_SELECT_VLV(port); |
6e266956 | 5379 | } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
ad933b56 | 5380 | if (port == PORT_A) |
a24c144c | 5381 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 5382 | else |
a24c144c | 5383 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
5384 | } |
5385 | ||
453c5420 JB |
5386 | pp_on |= port_sel; |
5387 | ||
8e8232d5 ID |
5388 | I915_WRITE(regs.pp_on, pp_on); |
5389 | I915_WRITE(regs.pp_off, pp_off); | |
cc3f90f0 | 5390 | if (IS_GEN9_LP(dev_priv)) |
8e8232d5 | 5391 | I915_WRITE(regs.pp_ctrl, pp_div); |
b0a08bec | 5392 | else |
8e8232d5 | 5393 | I915_WRITE(regs.pp_div, pp_div); |
67a54566 | 5394 | |
67a54566 | 5395 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
8e8232d5 ID |
5396 | I915_READ(regs.pp_on), |
5397 | I915_READ(regs.pp_off), | |
cc3f90f0 | 5398 | IS_GEN9_LP(dev_priv) ? |
8e8232d5 ID |
5399 | (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : |
5400 | I915_READ(regs.pp_div)); | |
f684960e CW |
5401 | } |
5402 | ||
335f752b ID |
5403 | static void intel_dp_pps_init(struct drm_device *dev, |
5404 | struct intel_dp *intel_dp) | |
5405 | { | |
920a14b2 TU |
5406 | struct drm_i915_private *dev_priv = to_i915(dev); |
5407 | ||
5408 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
335f752b ID |
5409 | vlv_initial_power_sequencer_setup(intel_dp); |
5410 | } else { | |
5411 | intel_dp_init_panel_power_sequencer(dev, intel_dp); | |
5d5ab2d2 | 5412 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false); |
335f752b ID |
5413 | } |
5414 | } | |
5415 | ||
b33a2815 VK |
5416 | /** |
5417 | * intel_dp_set_drrs_state - program registers for RR switch to take effect | |
5423adf1 | 5418 | * @dev_priv: i915 device |
e896402c | 5419 | * @crtc_state: a pointer to the active intel_crtc_state |
b33a2815 VK |
5420 | * @refresh_rate: RR to be programmed |
5421 | * | |
5422 | * This function gets called when refresh rate (RR) has to be changed from | |
5423 | * one frequency to another. Switches can be between high and low RR | |
5424 | * supported by the panel or to any other RR based on media playback (in | |
5425 | * this case, RR value needs to be passed from user space). | |
5426 | * | |
5427 | * The caller of this function needs to take a lock on dev_priv->drrs. | |
5428 | */ | |
85cb48a1 ML |
5429 | static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, |
5430 | struct intel_crtc_state *crtc_state, | |
5431 | int refresh_rate) | |
439d7ac0 | 5432 | { |
439d7ac0 | 5433 | struct intel_encoder *encoder; |
96178eeb VK |
5434 | struct intel_digital_port *dig_port = NULL; |
5435 | struct intel_dp *intel_dp = dev_priv->drrs.dp; | |
85cb48a1 | 5436 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
96178eeb | 5437 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
439d7ac0 PB |
5438 | |
5439 | if (refresh_rate <= 0) { | |
5440 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); | |
5441 | return; | |
5442 | } | |
5443 | ||
96178eeb VK |
5444 | if (intel_dp == NULL) { |
5445 | DRM_DEBUG_KMS("DRRS not supported.\n"); | |
439d7ac0 PB |
5446 | return; |
5447 | } | |
5448 | ||
1fcc9d1c | 5449 | /* |
e4d59f6b RV |
5450 | * FIXME: This needs proper synchronization with psr state for some |
5451 | * platforms that cannot have PSR and DRRS enabled at the same time. | |
1fcc9d1c | 5452 | */ |
439d7ac0 | 5453 | |
96178eeb VK |
5454 | dig_port = dp_to_dig_port(intel_dp); |
5455 | encoder = &dig_port->base; | |
723f9aab | 5456 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
439d7ac0 PB |
5457 | |
5458 | if (!intel_crtc) { | |
5459 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); | |
5460 | return; | |
5461 | } | |
5462 | ||
96178eeb | 5463 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
439d7ac0 PB |
5464 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5465 | return; | |
5466 | } | |
5467 | ||
96178eeb VK |
5468 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5469 | refresh_rate) | |
439d7ac0 PB |
5470 | index = DRRS_LOW_RR; |
5471 | ||
96178eeb | 5472 | if (index == dev_priv->drrs.refresh_rate_type) { |
439d7ac0 PB |
5473 | DRM_DEBUG_KMS( |
5474 | "DRRS requested for previously set RR...ignoring\n"); | |
5475 | return; | |
5476 | } | |
5477 | ||
85cb48a1 | 5478 | if (!crtc_state->base.active) { |
439d7ac0 PB |
5479 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
5480 | return; | |
5481 | } | |
5482 | ||
85cb48a1 | 5483 | if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { |
a4c30b1d VK |
5484 | switch (index) { |
5485 | case DRRS_HIGH_RR: | |
5486 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
5487 | break; | |
5488 | case DRRS_LOW_RR: | |
5489 | intel_dp_set_m_n(intel_crtc, M2_N2); | |
5490 | break; | |
5491 | case DRRS_MAX_RR: | |
5492 | default: | |
5493 | DRM_ERROR("Unsupported refreshrate type\n"); | |
5494 | } | |
85cb48a1 ML |
5495 | } else if (INTEL_GEN(dev_priv) > 6) { |
5496 | i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); | |
649636ef | 5497 | u32 val; |
a4c30b1d | 5498 | |
649636ef | 5499 | val = I915_READ(reg); |
439d7ac0 | 5500 | if (index > DRRS_HIGH_RR) { |
85cb48a1 | 5501 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
5502 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5503 | else | |
5504 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 5505 | } else { |
85cb48a1 | 5506 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
5507 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5508 | else | |
5509 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 PB |
5510 | } |
5511 | I915_WRITE(reg, val); | |
5512 | } | |
5513 | ||
4e9ac947 VK |
5514 | dev_priv->drrs.refresh_rate_type = index; |
5515 | ||
5516 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); | |
5517 | } | |
5518 | ||
b33a2815 VK |
5519 | /** |
5520 | * intel_edp_drrs_enable - init drrs struct if supported | |
5521 | * @intel_dp: DP struct | |
5423adf1 | 5522 | * @crtc_state: A pointer to the active crtc state. |
b33a2815 VK |
5523 | * |
5524 | * Initializes frontbuffer_bits and drrs.dp | |
5525 | */ | |
85cb48a1 ML |
5526 | void intel_edp_drrs_enable(struct intel_dp *intel_dp, |
5527 | struct intel_crtc_state *crtc_state) | |
c395578e VK |
5528 | { |
5529 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 5530 | struct drm_i915_private *dev_priv = to_i915(dev); |
c395578e | 5531 | |
85cb48a1 | 5532 | if (!crtc_state->has_drrs) { |
c395578e VK |
5533 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
5534 | return; | |
5535 | } | |
5536 | ||
5537 | mutex_lock(&dev_priv->drrs.mutex); | |
5538 | if (WARN_ON(dev_priv->drrs.dp)) { | |
5539 | DRM_ERROR("DRRS already enabled\n"); | |
5540 | goto unlock; | |
5541 | } | |
5542 | ||
5543 | dev_priv->drrs.busy_frontbuffer_bits = 0; | |
5544 | ||
5545 | dev_priv->drrs.dp = intel_dp; | |
5546 | ||
5547 | unlock: | |
5548 | mutex_unlock(&dev_priv->drrs.mutex); | |
5549 | } | |
5550 | ||
b33a2815 VK |
5551 | /** |
5552 | * intel_edp_drrs_disable - Disable DRRS | |
5553 | * @intel_dp: DP struct | |
5423adf1 | 5554 | * @old_crtc_state: Pointer to old crtc_state. |
b33a2815 VK |
5555 | * |
5556 | */ | |
85cb48a1 ML |
5557 | void intel_edp_drrs_disable(struct intel_dp *intel_dp, |
5558 | struct intel_crtc_state *old_crtc_state) | |
c395578e VK |
5559 | { |
5560 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 5561 | struct drm_i915_private *dev_priv = to_i915(dev); |
c395578e | 5562 | |
85cb48a1 | 5563 | if (!old_crtc_state->has_drrs) |
c395578e VK |
5564 | return; |
5565 | ||
5566 | mutex_lock(&dev_priv->drrs.mutex); | |
5567 | if (!dev_priv->drrs.dp) { | |
5568 | mutex_unlock(&dev_priv->drrs.mutex); | |
5569 | return; | |
5570 | } | |
5571 | ||
5572 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) | |
85cb48a1 ML |
5573 | intel_dp_set_drrs_state(dev_priv, old_crtc_state, |
5574 | intel_dp->attached_connector->panel.fixed_mode->vrefresh); | |
c395578e VK |
5575 | |
5576 | dev_priv->drrs.dp = NULL; | |
5577 | mutex_unlock(&dev_priv->drrs.mutex); | |
5578 | ||
5579 | cancel_delayed_work_sync(&dev_priv->drrs.work); | |
5580 | } | |
5581 | ||
4e9ac947 VK |
5582 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5583 | { | |
5584 | struct drm_i915_private *dev_priv = | |
5585 | container_of(work, typeof(*dev_priv), drrs.work.work); | |
5586 | struct intel_dp *intel_dp; | |
5587 | ||
5588 | mutex_lock(&dev_priv->drrs.mutex); | |
5589 | ||
5590 | intel_dp = dev_priv->drrs.dp; | |
5591 | ||
5592 | if (!intel_dp) | |
5593 | goto unlock; | |
5594 | ||
439d7ac0 | 5595 | /* |
4e9ac947 VK |
5596 | * The delayed work can race with an invalidate hence we need to |
5597 | * recheck. | |
439d7ac0 PB |
5598 | */ |
5599 | ||
4e9ac947 VK |
5600 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5601 | goto unlock; | |
439d7ac0 | 5602 | |
85cb48a1 ML |
5603 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { |
5604 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; | |
5605 | ||
5606 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, | |
5607 | intel_dp->attached_connector->panel.downclock_mode->vrefresh); | |
5608 | } | |
439d7ac0 | 5609 | |
4e9ac947 | 5610 | unlock: |
4e9ac947 | 5611 | mutex_unlock(&dev_priv->drrs.mutex); |
439d7ac0 PB |
5612 | } |
5613 | ||
b33a2815 | 5614 | /** |
0ddfd203 | 5615 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5748b6a1 | 5616 | * @dev_priv: i915 device |
b33a2815 VK |
5617 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5618 | * | |
0ddfd203 R |
5619 | * This function gets called everytime rendering on the given planes start. |
5620 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). | |
b33a2815 VK |
5621 | * |
5622 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5623 | */ | |
5748b6a1 CW |
5624 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
5625 | unsigned int frontbuffer_bits) | |
a93fad0f | 5626 | { |
a93fad0f VK |
5627 | struct drm_crtc *crtc; |
5628 | enum pipe pipe; | |
5629 | ||
9da7d693 | 5630 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5631 | return; |
5632 | ||
88f933a8 | 5633 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5634 | |
a93fad0f | 5635 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5636 | if (!dev_priv->drrs.dp) { |
5637 | mutex_unlock(&dev_priv->drrs.mutex); | |
5638 | return; | |
5639 | } | |
5640 | ||
a93fad0f VK |
5641 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5642 | pipe = to_intel_crtc(crtc)->pipe; | |
5643 | ||
c1d038c6 DV |
5644 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5645 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; | |
5646 | ||
0ddfd203 | 5647 | /* invalidate means busy screen hence upclock */ |
c1d038c6 | 5648 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
5649 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
5650 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
a93fad0f | 5651 | |
a93fad0f VK |
5652 | mutex_unlock(&dev_priv->drrs.mutex); |
5653 | } | |
5654 | ||
b33a2815 | 5655 | /** |
0ddfd203 | 5656 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5748b6a1 | 5657 | * @dev_priv: i915 device |
b33a2815 VK |
5658 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5659 | * | |
0ddfd203 R |
5660 | * This function gets called every time rendering on the given planes has |
5661 | * completed or flip on a crtc is completed. So DRRS should be upclocked | |
5662 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, | |
5663 | * if no other planes are dirty. | |
b33a2815 VK |
5664 | * |
5665 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5666 | */ | |
5748b6a1 CW |
5667 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, |
5668 | unsigned int frontbuffer_bits) | |
a93fad0f | 5669 | { |
a93fad0f VK |
5670 | struct drm_crtc *crtc; |
5671 | enum pipe pipe; | |
5672 | ||
9da7d693 | 5673 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5674 | return; |
5675 | ||
88f933a8 | 5676 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5677 | |
a93fad0f | 5678 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5679 | if (!dev_priv->drrs.dp) { |
5680 | mutex_unlock(&dev_priv->drrs.mutex); | |
5681 | return; | |
5682 | } | |
5683 | ||
a93fad0f VK |
5684 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5685 | pipe = to_intel_crtc(crtc)->pipe; | |
c1d038c6 DV |
5686 | |
5687 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
a93fad0f VK |
5688 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5689 | ||
0ddfd203 | 5690 | /* flush means busy screen hence upclock */ |
c1d038c6 | 5691 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
5692 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
5693 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
0ddfd203 R |
5694 | |
5695 | /* | |
5696 | * flush also means no more activity hence schedule downclock, if all | |
5697 | * other fbs are quiescent too | |
5698 | */ | |
5699 | if (!dev_priv->drrs.busy_frontbuffer_bits) | |
a93fad0f VK |
5700 | schedule_delayed_work(&dev_priv->drrs.work, |
5701 | msecs_to_jiffies(1000)); | |
5702 | mutex_unlock(&dev_priv->drrs.mutex); | |
5703 | } | |
5704 | ||
b33a2815 VK |
5705 | /** |
5706 | * DOC: Display Refresh Rate Switching (DRRS) | |
5707 | * | |
5708 | * Display Refresh Rate Switching (DRRS) is a power conservation feature | |
5709 | * which enables swtching between low and high refresh rates, | |
5710 | * dynamically, based on the usage scenario. This feature is applicable | |
5711 | * for internal panels. | |
5712 | * | |
5713 | * Indication that the panel supports DRRS is given by the panel EDID, which | |
5714 | * would list multiple refresh rates for one resolution. | |
5715 | * | |
5716 | * DRRS is of 2 types - static and seamless. | |
5717 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset | |
5718 | * (may appear as a blink on screen) and is used in dock-undock scenario. | |
5719 | * Seamless DRRS involves changing RR without any visual effect to the user | |
5720 | * and can be used during normal system usage. This is done by programming | |
5721 | * certain registers. | |
5722 | * | |
5723 | * Support for static/seamless DRRS may be indicated in the VBT based on | |
5724 | * inputs from the panel spec. | |
5725 | * | |
5726 | * DRRS saves power by switching to low RR based on usage scenarios. | |
5727 | * | |
2e7a5701 DV |
5728 | * The implementation is based on frontbuffer tracking implementation. When |
5729 | * there is a disturbance on the screen triggered by user activity or a periodic | |
5730 | * system activity, DRRS is disabled (RR is changed to high RR). When there is | |
5731 | * no movement on screen, after a timeout of 1 second, a switch to low RR is | |
5732 | * made. | |
5733 | * | |
5734 | * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() | |
5735 | * and intel_edp_drrs_flush() are called. | |
b33a2815 VK |
5736 | * |
5737 | * DRRS can be further extended to support other internal panels and also | |
5738 | * the scenario of video playback wherein RR is set based on the rate | |
5739 | * requested by userspace. | |
5740 | */ | |
5741 | ||
5742 | /** | |
5743 | * intel_dp_drrs_init - Init basic DRRS work and mutex. | |
5744 | * @intel_connector: eDP connector | |
5745 | * @fixed_mode: preferred mode of panel | |
5746 | * | |
5747 | * This function is called only once at driver load to initialize basic | |
5748 | * DRRS stuff. | |
5749 | * | |
5750 | * Returns: | |
5751 | * Downclock mode if panel supports it, else return NULL. | |
5752 | * DRRS support is determined by the presence of downclock mode (apart | |
5753 | * from VBT setting). | |
5754 | */ | |
4f9db5b5 | 5755 | static struct drm_display_mode * |
96178eeb VK |
5756 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5757 | struct drm_display_mode *fixed_mode) | |
4f9db5b5 PB |
5758 | { |
5759 | struct drm_connector *connector = &intel_connector->base; | |
96178eeb | 5760 | struct drm_device *dev = connector->dev; |
fac5e23e | 5761 | struct drm_i915_private *dev_priv = to_i915(dev); |
4f9db5b5 PB |
5762 | struct drm_display_mode *downclock_mode = NULL; |
5763 | ||
9da7d693 DV |
5764 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5765 | mutex_init(&dev_priv->drrs.mutex); | |
5766 | ||
dd11bc10 | 5767 | if (INTEL_GEN(dev_priv) <= 6) { |
4f9db5b5 PB |
5768 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
5769 | return NULL; | |
5770 | } | |
5771 | ||
5772 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
4079b8d1 | 5773 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
4f9db5b5 PB |
5774 | return NULL; |
5775 | } | |
5776 | ||
5777 | downclock_mode = intel_find_panel_downclock | |
a318b4c4 | 5778 | (dev_priv, fixed_mode, connector); |
4f9db5b5 PB |
5779 | |
5780 | if (!downclock_mode) { | |
a1d26342 | 5781 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
4f9db5b5 PB |
5782 | return NULL; |
5783 | } | |
5784 | ||
96178eeb | 5785 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
4f9db5b5 | 5786 | |
96178eeb | 5787 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
4079b8d1 | 5788 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
4f9db5b5 PB |
5789 | return downclock_mode; |
5790 | } | |
5791 | ||
ed92f0b2 | 5792 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 5793 | struct intel_connector *intel_connector) |
ed92f0b2 PZ |
5794 | { |
5795 | struct drm_connector *connector = &intel_connector->base; | |
5796 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
63635217 PZ |
5797 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5798 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 5799 | struct drm_i915_private *dev_priv = to_i915(dev); |
ed92f0b2 | 5800 | struct drm_display_mode *fixed_mode = NULL; |
4f9db5b5 | 5801 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 PZ |
5802 | bool has_dpcd; |
5803 | struct drm_display_mode *scan; | |
5804 | struct edid *edid; | |
6517d273 | 5805 | enum pipe pipe = INVALID_PIPE; |
ed92f0b2 PZ |
5806 | |
5807 | if (!is_edp(intel_dp)) | |
5808 | return true; | |
5809 | ||
97a824e1 ID |
5810 | /* |
5811 | * On IBX/CPT we may get here with LVDS already registered. Since the | |
5812 | * driver uses the only internal power sequencer available for both | |
5813 | * eDP and LVDS bail out early in this case to prevent interfering | |
5814 | * with an already powered-on LVDS power sequencer. | |
5815 | */ | |
5816 | if (intel_get_lvds_encoder(dev)) { | |
5817 | WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); | |
5818 | DRM_INFO("LVDS was detected, not registering eDP\n"); | |
5819 | ||
5820 | return false; | |
5821 | } | |
5822 | ||
49e6bc51 | 5823 | pps_lock(intel_dp); |
b4d06ede ID |
5824 | |
5825 | intel_dp_init_panel_power_timestamps(intel_dp); | |
335f752b | 5826 | intel_dp_pps_init(dev, intel_dp); |
49e6bc51 | 5827 | intel_edp_panel_vdd_sanitize(intel_dp); |
b4d06ede | 5828 | |
49e6bc51 | 5829 | pps_unlock(intel_dp); |
63635217 | 5830 | |
ed92f0b2 | 5831 | /* Cache DPCD and EDID for edp. */ |
fe5a66f9 | 5832 | has_dpcd = intel_edp_init_dpcd(intel_dp); |
ed92f0b2 | 5833 | |
fe5a66f9 | 5834 | if (!has_dpcd) { |
ed92f0b2 PZ |
5835 | /* if this fails, presume the device is a ghost */ |
5836 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
b4d06ede | 5837 | goto out_vdd_off; |
ed92f0b2 PZ |
5838 | } |
5839 | ||
060c8778 | 5840 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 5841 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
5842 | if (edid) { |
5843 | if (drm_add_edid_modes(connector, edid)) { | |
5844 | drm_mode_connector_update_edid_property(connector, | |
5845 | edid); | |
5846 | drm_edid_to_eld(connector, edid); | |
5847 | } else { | |
5848 | kfree(edid); | |
5849 | edid = ERR_PTR(-EINVAL); | |
5850 | } | |
5851 | } else { | |
5852 | edid = ERR_PTR(-ENOENT); | |
5853 | } | |
5854 | intel_connector->edid = edid; | |
5855 | ||
5856 | /* prefer fixed mode from EDID if available */ | |
5857 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
5858 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
5859 | fixed_mode = drm_mode_duplicate(dev, scan); | |
4f9db5b5 | 5860 | downclock_mode = intel_dp_drrs_init( |
4f9db5b5 | 5861 | intel_connector, fixed_mode); |
ed92f0b2 PZ |
5862 | break; |
5863 | } | |
5864 | } | |
5865 | ||
5866 | /* fallback to VBT if available for eDP */ | |
5867 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
5868 | fixed_mode = drm_mode_duplicate(dev, | |
5869 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
df457245 | 5870 | if (fixed_mode) { |
ed92f0b2 | 5871 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
df457245 VS |
5872 | connector->display_info.width_mm = fixed_mode->width_mm; |
5873 | connector->display_info.height_mm = fixed_mode->height_mm; | |
5874 | } | |
ed92f0b2 | 5875 | } |
060c8778 | 5876 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 5877 | |
920a14b2 | 5878 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
01527b31 CT |
5879 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
5880 | register_reboot_notifier(&intel_dp->edp_notifier); | |
6517d273 VS |
5881 | |
5882 | /* | |
5883 | * Figure out the current pipe for the initial backlight setup. | |
5884 | * If the current pipe isn't valid, try the PPS pipe, and if that | |
5885 | * fails just assume pipe A. | |
5886 | */ | |
9f2bdb00 | 5887 | pipe = vlv_active_pipe(intel_dp); |
6517d273 VS |
5888 | |
5889 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5890 | pipe = intel_dp->pps_pipe; | |
5891 | ||
5892 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5893 | pipe = PIPE_A; | |
5894 | ||
5895 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", | |
5896 | pipe_name(pipe)); | |
01527b31 CT |
5897 | } |
5898 | ||
4f9db5b5 | 5899 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5507faeb | 5900 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
6517d273 | 5901 | intel_panel_setup_backlight(connector, pipe); |
ed92f0b2 PZ |
5902 | |
5903 | return true; | |
b4d06ede ID |
5904 | |
5905 | out_vdd_off: | |
5906 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
5907 | /* | |
5908 | * vdd might still be enabled do to the delayed vdd off. | |
5909 | * Make sure vdd is actually turned off here. | |
5910 | */ | |
5911 | pps_lock(intel_dp); | |
5912 | edp_panel_vdd_off_sync(intel_dp); | |
5913 | pps_unlock(intel_dp); | |
5914 | ||
5915 | return false; | |
ed92f0b2 PZ |
5916 | } |
5917 | ||
5432fcaf | 5918 | /* Set up the hotplug pin and aux power domain. */ |
b71953a1 ACO |
5919 | static void |
5920 | intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port) | |
5921 | { | |
5922 | struct intel_encoder *encoder = &intel_dig_port->base; | |
5432fcaf | 5923 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
b71953a1 | 5924 | |
b71953a1 ACO |
5925 | switch (intel_dig_port->port) { |
5926 | case PORT_A: | |
5927 | encoder->hpd_pin = HPD_PORT_A; | |
5432fcaf | 5928 | intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A; |
b71953a1 ACO |
5929 | break; |
5930 | case PORT_B: | |
5931 | encoder->hpd_pin = HPD_PORT_B; | |
5432fcaf | 5932 | intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B; |
b71953a1 ACO |
5933 | break; |
5934 | case PORT_C: | |
5935 | encoder->hpd_pin = HPD_PORT_C; | |
5432fcaf | 5936 | intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C; |
b71953a1 ACO |
5937 | break; |
5938 | case PORT_D: | |
5939 | encoder->hpd_pin = HPD_PORT_D; | |
5432fcaf | 5940 | intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D; |
b71953a1 ACO |
5941 | break; |
5942 | case PORT_E: | |
5943 | encoder->hpd_pin = HPD_PORT_E; | |
5432fcaf ACO |
5944 | |
5945 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5946 | intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D; | |
b71953a1 ACO |
5947 | break; |
5948 | default: | |
5949 | MISSING_CASE(intel_dig_port->port); | |
5950 | } | |
5951 | } | |
5952 | ||
16c25533 | 5953 | bool |
f0fec3f2 PZ |
5954 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5955 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 5956 | { |
f0fec3f2 PZ |
5957 | struct drm_connector *connector = &intel_connector->base; |
5958 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
5959 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
5960 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 5961 | struct drm_i915_private *dev_priv = to_i915(dev); |
174edf1f | 5962 | enum port port = intel_dig_port->port; |
7a418e34 | 5963 | int type; |
a4fc5ed6 | 5964 | |
ccb1a831 VS |
5965 | if (WARN(intel_dig_port->max_lanes < 1, |
5966 | "Not enough lanes (%d) for DP on port %c\n", | |
5967 | intel_dig_port->max_lanes, port_name(port))) | |
5968 | return false; | |
5969 | ||
55cfc580 JN |
5970 | intel_dp_set_source_rates(intel_dp); |
5971 | ||
d7e8ef02 | 5972 | intel_dp->reset_link_params = true; |
a4a5d2f8 | 5973 | intel_dp->pps_pipe = INVALID_PIPE; |
9f2bdb00 | 5974 | intel_dp->active_pipe = INVALID_PIPE; |
a4a5d2f8 | 5975 | |
ec5b01dd | 5976 | /* intel_dp vfuncs */ |
dd11bc10 | 5977 | if (INTEL_GEN(dev_priv) >= 9) |
b6b5e383 | 5978 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
8652744b | 5979 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ec5b01dd | 5980 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
6e266956 | 5981 | else if (HAS_PCH_SPLIT(dev_priv)) |
ec5b01dd DL |
5982 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
5983 | else | |
6ffb1be7 | 5984 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; |
ec5b01dd | 5985 | |
dd11bc10 | 5986 | if (INTEL_GEN(dev_priv) >= 9) |
b9ca5fad DL |
5987 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
5988 | else | |
6ffb1be7 | 5989 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; |
153b1100 | 5990 | |
4f8036a2 | 5991 | if (HAS_DDI(dev_priv)) |
ad64217b ACO |
5992 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; |
5993 | ||
0767935e DV |
5994 | /* Preserve the current hw state. */ |
5995 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 5996 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 5997 | |
dd11bc10 | 5998 | if (intel_dp_is_edp(dev_priv, port)) |
b329530c | 5999 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
6000 | else |
6001 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 6002 | |
9f2bdb00 VS |
6003 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6004 | intel_dp->active_pipe = vlv_active_pipe(intel_dp); | |
6005 | ||
f7d24902 ID |
6006 | /* |
6007 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
6008 | * for DP the encoder type can be set by the caller to | |
6009 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
6010 | */ | |
6011 | if (type == DRM_MODE_CONNECTOR_eDP) | |
6012 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
6013 | ||
c17ed5b5 | 6014 | /* eDP only on port B and/or C on vlv/chv */ |
920a14b2 | 6015 | if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 6016 | is_edp(intel_dp) && port != PORT_B && port != PORT_C)) |
c17ed5b5 VS |
6017 | return false; |
6018 | ||
e7281eab ID |
6019 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
6020 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
6021 | port_name(port)); | |
6022 | ||
b329530c | 6023 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
6024 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
6025 | ||
a4fc5ed6 KP |
6026 | connector->interlace_allowed = true; |
6027 | connector->doublescan_allowed = 0; | |
6028 | ||
5432fcaf ACO |
6029 | intel_dp_init_connector_port_info(intel_dig_port); |
6030 | ||
b6339585 | 6031 | intel_dp_aux_init(intel_dp); |
7a418e34 | 6032 | |
f0fec3f2 | 6033 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 6034 | edp_panel_vdd_work); |
a4fc5ed6 | 6035 | |
df0e9248 | 6036 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 | 6037 | |
4f8036a2 | 6038 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
6039 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
6040 | else | |
6041 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
6042 | ||
0e32b39c | 6043 | /* init MST on ports that can support it */ |
56b857a5 | 6044 | if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) && |
0c9b3715 JN |
6045 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
6046 | intel_dp_mst_encoder_init(intel_dig_port, | |
6047 | intel_connector->base.base.id); | |
0e32b39c | 6048 | |
36b5f425 | 6049 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
a121f4e5 VS |
6050 | intel_dp_aux_fini(intel_dp); |
6051 | intel_dp_mst_encoder_cleanup(intel_dig_port); | |
6052 | goto fail; | |
b2f246a8 | 6053 | } |
32f9d658 | 6054 | |
f684960e CW |
6055 | intel_dp_add_properties(intel_dp, connector); |
6056 | ||
a4fc5ed6 KP |
6057 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
6058 | * 0xd. Failure to do so will result in spurious interrupts being | |
6059 | * generated on the port when a cable is not attached. | |
6060 | */ | |
50a0bc90 | 6061 | if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { |
a4fc5ed6 KP |
6062 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
6063 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
6064 | } | |
16c25533 PZ |
6065 | |
6066 | return true; | |
a121f4e5 VS |
6067 | |
6068 | fail: | |
a121f4e5 VS |
6069 | drm_connector_cleanup(connector); |
6070 | ||
6071 | return false; | |
a4fc5ed6 | 6072 | } |
f0fec3f2 | 6073 | |
c39055b0 | 6074 | bool intel_dp_init(struct drm_i915_private *dev_priv, |
457c52d8 CW |
6075 | i915_reg_t output_reg, |
6076 | enum port port) | |
f0fec3f2 PZ |
6077 | { |
6078 | struct intel_digital_port *intel_dig_port; | |
6079 | struct intel_encoder *intel_encoder; | |
6080 | struct drm_encoder *encoder; | |
6081 | struct intel_connector *intel_connector; | |
6082 | ||
b14c5679 | 6083 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 | 6084 | if (!intel_dig_port) |
457c52d8 | 6085 | return false; |
f0fec3f2 | 6086 | |
08d9bc92 | 6087 | intel_connector = intel_connector_alloc(); |
11aee0f6 SM |
6088 | if (!intel_connector) |
6089 | goto err_connector_alloc; | |
f0fec3f2 PZ |
6090 | |
6091 | intel_encoder = &intel_dig_port->base; | |
6092 | encoder = &intel_encoder->base; | |
6093 | ||
c39055b0 ACO |
6094 | if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
6095 | &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
6096 | "DP %c", port_name(port))) | |
893da0c9 | 6097 | goto err_encoder_init; |
f0fec3f2 | 6098 | |
5bfe2ac0 | 6099 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 6100 | intel_encoder->disable = intel_disable_dp; |
00c09d70 | 6101 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 6102 | intel_encoder->get_config = intel_dp_get_config; |
07f9cd0b | 6103 | intel_encoder->suspend = intel_dp_encoder_suspend; |
920a14b2 | 6104 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 6105 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
e4a1d846 CML |
6106 | intel_encoder->pre_enable = chv_pre_enable_dp; |
6107 | intel_encoder->enable = vlv_enable_dp; | |
580d3811 | 6108 | intel_encoder->post_disable = chv_post_disable_dp; |
d6db995f | 6109 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
11a914c2 | 6110 | } else if (IS_VALLEYVIEW(dev_priv)) { |
ecff4f3b | 6111 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
6112 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
6113 | intel_encoder->enable = vlv_enable_dp; | |
49277c31 | 6114 | intel_encoder->post_disable = vlv_post_disable_dp; |
ab1f90f9 | 6115 | } else { |
ecff4f3b JN |
6116 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
6117 | intel_encoder->enable = g4x_enable_dp; | |
dd11bc10 | 6118 | if (INTEL_GEN(dev_priv) >= 5) |
08aff3fe | 6119 | intel_encoder->post_disable = ilk_post_disable_dp; |
ab1f90f9 | 6120 | } |
f0fec3f2 | 6121 | |
174edf1f | 6122 | intel_dig_port->port = port; |
f0fec3f2 | 6123 | intel_dig_port->dp.output_reg = output_reg; |
ccb1a831 | 6124 | intel_dig_port->max_lanes = 4; |
f0fec3f2 | 6125 | |
cca0502b | 6126 | intel_encoder->type = INTEL_OUTPUT_DP; |
79f255a0 | 6127 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
920a14b2 | 6128 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 VS |
6129 | if (port == PORT_D) |
6130 | intel_encoder->crtc_mask = 1 << 2; | |
6131 | else | |
6132 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
6133 | } else { | |
6134 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
6135 | } | |
bc079e8b | 6136 | intel_encoder->cloneable = 0; |
03cdc1d4 | 6137 | intel_encoder->port = port; |
f0fec3f2 | 6138 | |
13cf5504 | 6139 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
5fcece80 | 6140 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
13cf5504 | 6141 | |
11aee0f6 SM |
6142 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
6143 | goto err_init_connector; | |
6144 | ||
457c52d8 | 6145 | return true; |
11aee0f6 SM |
6146 | |
6147 | err_init_connector: | |
6148 | drm_encoder_cleanup(encoder); | |
893da0c9 | 6149 | err_encoder_init: |
11aee0f6 SM |
6150 | kfree(intel_connector); |
6151 | err_connector_alloc: | |
6152 | kfree(intel_dig_port); | |
457c52d8 | 6153 | return false; |
f0fec3f2 | 6154 | } |
0e32b39c DA |
6155 | |
6156 | void intel_dp_mst_suspend(struct drm_device *dev) | |
6157 | { | |
fac5e23e | 6158 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
6159 | int i; |
6160 | ||
6161 | /* disable MST */ | |
6162 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 6163 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 VS |
6164 | |
6165 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) | |
0e32b39c DA |
6166 | continue; |
6167 | ||
5aa56969 VS |
6168 | if (intel_dig_port->dp.is_mst) |
6169 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); | |
0e32b39c DA |
6170 | } |
6171 | } | |
6172 | ||
6173 | void intel_dp_mst_resume(struct drm_device *dev) | |
6174 | { | |
fac5e23e | 6175 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
6176 | int i; |
6177 | ||
6178 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 6179 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 | 6180 | int ret; |
0e32b39c | 6181 | |
5aa56969 VS |
6182 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) |
6183 | continue; | |
0e32b39c | 6184 | |
5aa56969 VS |
6185 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
6186 | if (ret) | |
6187 | intel_dp_check_mst_status(&intel_dig_port->dp); | |
0e32b39c DA |
6188 | } |
6189 | } |