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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
a4fc5ed6 KP |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "drm_crtc_helper.h" | |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
ab2c0672 | 37 | #include "drm_dp_helper.h" |
a4fc5ed6 | 38 | |
ae266c98 | 39 | |
a4fc5ed6 KP |
40 | #define DP_LINK_STATUS_SIZE 6 |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) | |
42 | ||
43 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
44 | ||
ea5b213a CW |
45 | #define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP) |
46 | #define IS_PCH_eDP(i) ((i)->is_pch_edp) | |
32f9d658 | 47 | |
ea5b213a CW |
48 | struct intel_dp { |
49 | struct intel_encoder base; | |
a4fc5ed6 KP |
50 | uint32_t output_reg; |
51 | uint32_t DP; | |
52 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
a4fc5ed6 | 53 | bool has_audio; |
c8110e52 | 54 | int dpms_mode; |
a4fc5ed6 KP |
55 | uint8_t link_bw; |
56 | uint8_t lane_count; | |
57 | uint8_t dpcd[4]; | |
a4fc5ed6 KP |
58 | struct i2c_adapter adapter; |
59 | struct i2c_algo_dp_aux_data algo; | |
f0917379 | 60 | bool is_pch_edp; |
a4fc5ed6 KP |
61 | }; |
62 | ||
ea5b213a CW |
63 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
64 | { | |
65 | return container_of(enc_to_intel_encoder(encoder), struct intel_dp, base); | |
66 | } | |
a4fc5ed6 | 67 | |
ea5b213a CW |
68 | static void intel_dp_link_train(struct intel_dp *intel_dp); |
69 | static void intel_dp_link_down(struct intel_dp *intel_dp); | |
a4fc5ed6 | 70 | |
32f9d658 | 71 | void |
21d40d37 | 72 | intel_edp_link_config (struct intel_encoder *intel_encoder, |
ea5b213a | 73 | int *lane_num, int *link_bw) |
32f9d658 | 74 | { |
ea5b213a | 75 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
32f9d658 | 76 | |
ea5b213a CW |
77 | *lane_num = intel_dp->lane_count; |
78 | if (intel_dp->link_bw == DP_LINK_BW_1_62) | |
32f9d658 | 79 | *link_bw = 162000; |
ea5b213a | 80 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
32f9d658 ZW |
81 | *link_bw = 270000; |
82 | } | |
83 | ||
a4fc5ed6 | 84 | static int |
ea5b213a | 85 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
a4fc5ed6 | 86 | { |
a4fc5ed6 KP |
87 | int max_lane_count = 4; |
88 | ||
ea5b213a CW |
89 | if (intel_dp->dpcd[0] >= 0x11) { |
90 | max_lane_count = intel_dp->dpcd[2] & 0x1f; | |
a4fc5ed6 KP |
91 | switch (max_lane_count) { |
92 | case 1: case 2: case 4: | |
93 | break; | |
94 | default: | |
95 | max_lane_count = 4; | |
96 | } | |
97 | } | |
98 | return max_lane_count; | |
99 | } | |
100 | ||
101 | static int | |
ea5b213a | 102 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 103 | { |
ea5b213a | 104 | int max_link_bw = intel_dp->dpcd[1]; |
a4fc5ed6 KP |
105 | |
106 | switch (max_link_bw) { | |
107 | case DP_LINK_BW_1_62: | |
108 | case DP_LINK_BW_2_7: | |
109 | break; | |
110 | default: | |
111 | max_link_bw = DP_LINK_BW_1_62; | |
112 | break; | |
113 | } | |
114 | return max_link_bw; | |
115 | } | |
116 | ||
117 | static int | |
118 | intel_dp_link_clock(uint8_t link_bw) | |
119 | { | |
120 | if (link_bw == DP_LINK_BW_2_7) | |
121 | return 270000; | |
122 | else | |
123 | return 162000; | |
124 | } | |
125 | ||
126 | /* I think this is a fiction */ | |
127 | static int | |
ea5b213a | 128 | intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) |
a4fc5ed6 | 129 | { |
885a5fb5 ZW |
130 | struct drm_i915_private *dev_priv = dev->dev_private; |
131 | ||
ea5b213a | 132 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) |
885a5fb5 ZW |
133 | return (pixel_clock * dev_priv->edp_bpp) / 8; |
134 | else | |
135 | return pixel_clock * 3; | |
a4fc5ed6 KP |
136 | } |
137 | ||
fe27d53e DA |
138 | static int |
139 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
140 | { | |
141 | return (max_link_clock * max_lanes * 8) / 10; | |
142 | } | |
143 | ||
a4fc5ed6 KP |
144 | static int |
145 | intel_dp_mode_valid(struct drm_connector *connector, | |
146 | struct drm_display_mode *mode) | |
147 | { | |
55f78c43 | 148 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
ea5b213a | 149 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
7de56f43 ZY |
150 | struct drm_device *dev = connector->dev; |
151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a CW |
152 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
153 | int max_lanes = intel_dp_max_lane_count(intel_dp); | |
a4fc5ed6 | 154 | |
ea5b213a | 155 | if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && |
7de56f43 ZY |
156 | dev_priv->panel_fixed_mode) { |
157 | if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) | |
158 | return MODE_PANEL; | |
159 | ||
160 | if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay) | |
161 | return MODE_PANEL; | |
162 | } | |
163 | ||
fe27d53e DA |
164 | /* only refuse the mode on non eDP since we have seen some wierd eDP panels |
165 | which are outside spec tolerances but somehow work by magic */ | |
ea5b213a CW |
166 | if (!IS_eDP(intel_dp) && |
167 | (intel_dp_link_required(connector->dev, intel_dp, mode->clock) | |
fe27d53e | 168 | > intel_dp_max_data_rate(max_link_clock, max_lanes))) |
a4fc5ed6 KP |
169 | return MODE_CLOCK_HIGH; |
170 | ||
171 | if (mode->clock < 10000) | |
172 | return MODE_CLOCK_LOW; | |
173 | ||
174 | return MODE_OK; | |
175 | } | |
176 | ||
177 | static uint32_t | |
178 | pack_aux(uint8_t *src, int src_bytes) | |
179 | { | |
180 | int i; | |
181 | uint32_t v = 0; | |
182 | ||
183 | if (src_bytes > 4) | |
184 | src_bytes = 4; | |
185 | for (i = 0; i < src_bytes; i++) | |
186 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
187 | return v; | |
188 | } | |
189 | ||
190 | static void | |
191 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
192 | { | |
193 | int i; | |
194 | if (dst_bytes > 4) | |
195 | dst_bytes = 4; | |
196 | for (i = 0; i < dst_bytes; i++) | |
197 | dst[i] = src >> ((3-i) * 8); | |
198 | } | |
199 | ||
fb0f8fbf KP |
200 | /* hrawclock is 1/4 the FSB frequency */ |
201 | static int | |
202 | intel_hrawclk(struct drm_device *dev) | |
203 | { | |
204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
205 | uint32_t clkcfg; | |
206 | ||
207 | clkcfg = I915_READ(CLKCFG); | |
208 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
209 | case CLKCFG_FSB_400: | |
210 | return 100; | |
211 | case CLKCFG_FSB_533: | |
212 | return 133; | |
213 | case CLKCFG_FSB_667: | |
214 | return 166; | |
215 | case CLKCFG_FSB_800: | |
216 | return 200; | |
217 | case CLKCFG_FSB_1067: | |
218 | return 266; | |
219 | case CLKCFG_FSB_1333: | |
220 | return 333; | |
221 | /* these two are just a guess; one of them might be right */ | |
222 | case CLKCFG_FSB_1600: | |
223 | case CLKCFG_FSB_1600_ALT: | |
224 | return 400; | |
225 | default: | |
226 | return 133; | |
227 | } | |
228 | } | |
229 | ||
a4fc5ed6 | 230 | static int |
ea5b213a | 231 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
232 | uint8_t *send, int send_bytes, |
233 | uint8_t *recv, int recv_size) | |
234 | { | |
ea5b213a CW |
235 | uint32_t output_reg = intel_dp->output_reg; |
236 | struct drm_device *dev = intel_dp->base.enc.dev; | |
a4fc5ed6 KP |
237 | struct drm_i915_private *dev_priv = dev->dev_private; |
238 | uint32_t ch_ctl = output_reg + 0x10; | |
239 | uint32_t ch_data = ch_ctl + 4; | |
240 | int i; | |
241 | int recv_bytes; | |
a4fc5ed6 | 242 | uint32_t status; |
fb0f8fbf | 243 | uint32_t aux_clock_divider; |
e3421a18 | 244 | int try, precharge; |
a4fc5ed6 KP |
245 | |
246 | /* The clock divider is based off the hrawclk, | |
fb0f8fbf KP |
247 | * and would like to run at 2MHz. So, take the |
248 | * hrawclk value and divide by 2 and use that | |
6176b8f9 JB |
249 | * |
250 | * Note that PCH attached eDP panels should use a 125MHz input | |
251 | * clock divider. | |
a4fc5ed6 | 252 | */ |
6176b8f9 | 253 | if (IS_eDP(intel_dp) && !IS_PCH_eDP(intel_dp)) { |
e3421a18 ZW |
254 | if (IS_GEN6(dev)) |
255 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ | |
256 | else | |
257 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
258 | } else if (HAS_PCH_SPLIT(dev)) | |
f2b115e6 | 259 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
5eb08b69 ZW |
260 | else |
261 | aux_clock_divider = intel_hrawclk(dev) / 2; | |
262 | ||
e3421a18 ZW |
263 | if (IS_GEN6(dev)) |
264 | precharge = 3; | |
265 | else | |
266 | precharge = 5; | |
267 | ||
4f7f7b7e CW |
268 | if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { |
269 | DRM_ERROR("dp_aux_ch not started status 0x%08x\n", | |
270 | I915_READ(ch_ctl)); | |
271 | return -EBUSY; | |
272 | } | |
273 | ||
fb0f8fbf KP |
274 | /* Must try at least 3 times according to DP spec */ |
275 | for (try = 0; try < 5; try++) { | |
276 | /* Load the send data into the aux channel data registers */ | |
4f7f7b7e CW |
277 | for (i = 0; i < send_bytes; i += 4) |
278 | I915_WRITE(ch_data + i, | |
279 | pack_aux(send + i, send_bytes - i)); | |
fb0f8fbf KP |
280 | |
281 | /* Send the command and wait for it to complete */ | |
4f7f7b7e CW |
282 | I915_WRITE(ch_ctl, |
283 | DP_AUX_CH_CTL_SEND_BUSY | | |
284 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
285 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
286 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
287 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
288 | DP_AUX_CH_CTL_DONE | | |
289 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
290 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
fb0f8fbf | 291 | for (;;) { |
fb0f8fbf KP |
292 | status = I915_READ(ch_ctl); |
293 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
294 | break; | |
4f7f7b7e | 295 | udelay(100); |
fb0f8fbf KP |
296 | } |
297 | ||
298 | /* Clear done status and any errors */ | |
4f7f7b7e CW |
299 | I915_WRITE(ch_ctl, |
300 | status | | |
301 | DP_AUX_CH_CTL_DONE | | |
302 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
303 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
304 | if (status & DP_AUX_CH_CTL_DONE) | |
a4fc5ed6 KP |
305 | break; |
306 | } | |
307 | ||
a4fc5ed6 | 308 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 309 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
a5b3da54 | 310 | return -EBUSY; |
a4fc5ed6 KP |
311 | } |
312 | ||
313 | /* Check for timeout or receive error. | |
314 | * Timeouts occur when the sink is not connected | |
315 | */ | |
a5b3da54 | 316 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 317 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
a5b3da54 KP |
318 | return -EIO; |
319 | } | |
1ae8c0a5 KP |
320 | |
321 | /* Timeouts occur when the device isn't connected, so they're | |
322 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 323 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 324 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
a5b3da54 | 325 | return -ETIMEDOUT; |
a4fc5ed6 KP |
326 | } |
327 | ||
328 | /* Unload any bytes sent back from the other side */ | |
329 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
330 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
331 | if (recv_bytes > recv_size) |
332 | recv_bytes = recv_size; | |
333 | ||
4f7f7b7e CW |
334 | for (i = 0; i < recv_bytes; i += 4) |
335 | unpack_aux(I915_READ(ch_data + i), | |
336 | recv + i, recv_bytes - i); | |
a4fc5ed6 KP |
337 | |
338 | return recv_bytes; | |
339 | } | |
340 | ||
341 | /* Write data to the aux channel in native mode */ | |
342 | static int | |
ea5b213a | 343 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
344 | uint16_t address, uint8_t *send, int send_bytes) |
345 | { | |
346 | int ret; | |
347 | uint8_t msg[20]; | |
348 | int msg_bytes; | |
349 | uint8_t ack; | |
350 | ||
351 | if (send_bytes > 16) | |
352 | return -1; | |
353 | msg[0] = AUX_NATIVE_WRITE << 4; | |
354 | msg[1] = address >> 8; | |
eebc863e | 355 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
356 | msg[3] = send_bytes - 1; |
357 | memcpy(&msg[4], send, send_bytes); | |
358 | msg_bytes = send_bytes + 4; | |
359 | for (;;) { | |
ea5b213a | 360 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
361 | if (ret < 0) |
362 | return ret; | |
363 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
364 | break; | |
365 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
366 | udelay(100); | |
367 | else | |
a5b3da54 | 368 | return -EIO; |
a4fc5ed6 KP |
369 | } |
370 | return send_bytes; | |
371 | } | |
372 | ||
373 | /* Write a single byte to the aux channel in native mode */ | |
374 | static int | |
ea5b213a | 375 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
376 | uint16_t address, uint8_t byte) |
377 | { | |
ea5b213a | 378 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
379 | } |
380 | ||
381 | /* read bytes from a native aux channel */ | |
382 | static int | |
ea5b213a | 383 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
384 | uint16_t address, uint8_t *recv, int recv_bytes) |
385 | { | |
386 | uint8_t msg[4]; | |
387 | int msg_bytes; | |
388 | uint8_t reply[20]; | |
389 | int reply_bytes; | |
390 | uint8_t ack; | |
391 | int ret; | |
392 | ||
393 | msg[0] = AUX_NATIVE_READ << 4; | |
394 | msg[1] = address >> 8; | |
395 | msg[2] = address & 0xff; | |
396 | msg[3] = recv_bytes - 1; | |
397 | ||
398 | msg_bytes = 4; | |
399 | reply_bytes = recv_bytes + 1; | |
400 | ||
401 | for (;;) { | |
ea5b213a | 402 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 403 | reply, reply_bytes); |
a5b3da54 KP |
404 | if (ret == 0) |
405 | return -EPROTO; | |
406 | if (ret < 0) | |
a4fc5ed6 KP |
407 | return ret; |
408 | ack = reply[0]; | |
409 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
410 | memcpy(recv, reply + 1, ret - 1); | |
411 | return ret - 1; | |
412 | } | |
413 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
414 | udelay(100); | |
415 | else | |
a5b3da54 | 416 | return -EIO; |
a4fc5ed6 KP |
417 | } |
418 | } | |
419 | ||
420 | static int | |
ab2c0672 DA |
421 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
422 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 423 | { |
ab2c0672 | 424 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
425 | struct intel_dp *intel_dp = container_of(adapter, |
426 | struct intel_dp, | |
427 | adapter); | |
ab2c0672 DA |
428 | uint16_t address = algo_data->address; |
429 | uint8_t msg[5]; | |
430 | uint8_t reply[2]; | |
431 | int msg_bytes; | |
432 | int reply_bytes; | |
433 | int ret; | |
434 | ||
435 | /* Set up the command byte */ | |
436 | if (mode & MODE_I2C_READ) | |
437 | msg[0] = AUX_I2C_READ << 4; | |
438 | else | |
439 | msg[0] = AUX_I2C_WRITE << 4; | |
440 | ||
441 | if (!(mode & MODE_I2C_STOP)) | |
442 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 443 | |
ab2c0672 DA |
444 | msg[1] = address >> 8; |
445 | msg[2] = address; | |
446 | ||
447 | switch (mode) { | |
448 | case MODE_I2C_WRITE: | |
449 | msg[3] = 0; | |
450 | msg[4] = write_byte; | |
451 | msg_bytes = 5; | |
452 | reply_bytes = 1; | |
453 | break; | |
454 | case MODE_I2C_READ: | |
455 | msg[3] = 0; | |
456 | msg_bytes = 4; | |
457 | reply_bytes = 2; | |
458 | break; | |
459 | default: | |
460 | msg_bytes = 3; | |
461 | reply_bytes = 1; | |
462 | break; | |
463 | } | |
464 | ||
465 | for (;;) { | |
ea5b213a | 466 | ret = intel_dp_aux_ch(intel_dp, |
ab2c0672 DA |
467 | msg, msg_bytes, |
468 | reply, reply_bytes); | |
469 | if (ret < 0) { | |
3ff99164 | 470 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
471 | return ret; |
472 | } | |
473 | switch (reply[0] & AUX_I2C_REPLY_MASK) { | |
474 | case AUX_I2C_REPLY_ACK: | |
475 | if (mode == MODE_I2C_READ) { | |
476 | *read_byte = reply[1]; | |
477 | } | |
478 | return reply_bytes - 1; | |
479 | case AUX_I2C_REPLY_NACK: | |
3ff99164 | 480 | DRM_DEBUG_KMS("aux_ch nack\n"); |
ab2c0672 DA |
481 | return -EREMOTEIO; |
482 | case AUX_I2C_REPLY_DEFER: | |
3ff99164 | 483 | DRM_DEBUG_KMS("aux_ch defer\n"); |
ab2c0672 DA |
484 | udelay(100); |
485 | break; | |
486 | default: | |
487 | DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]); | |
488 | return -EREMOTEIO; | |
489 | } | |
490 | } | |
a4fc5ed6 KP |
491 | } |
492 | ||
493 | static int | |
ea5b213a | 494 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 495 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 496 | { |
d54e9d28 | 497 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
498 | intel_dp->algo.running = false; |
499 | intel_dp->algo.address = 0; | |
500 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
501 | ||
502 | memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); | |
503 | intel_dp->adapter.owner = THIS_MODULE; | |
504 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
505 | strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); | |
506 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; | |
507 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
508 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
509 | ||
510 | return i2c_dp_aux_add_bus(&intel_dp->adapter); | |
a4fc5ed6 KP |
511 | } |
512 | ||
513 | static bool | |
514 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
515 | struct drm_display_mode *adjusted_mode) | |
516 | { | |
0d3a1bee ZY |
517 | struct drm_device *dev = encoder->dev; |
518 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 519 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4fc5ed6 | 520 | int lane_count, clock; |
ea5b213a CW |
521 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
522 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; | |
a4fc5ed6 KP |
523 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
524 | ||
ea5b213a | 525 | if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && |
0d3a1bee | 526 | dev_priv->panel_fixed_mode) { |
1d8e1c75 CW |
527 | intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); |
528 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, | |
529 | mode, adjusted_mode); | |
0d3a1bee ZY |
530 | /* |
531 | * the mode->clock is used to calculate the Data&Link M/N | |
532 | * of the pipe. For the eDP the fixed clock should be used. | |
533 | */ | |
534 | mode->clock = dev_priv->panel_fixed_mode->clock; | |
535 | } | |
536 | ||
a4fc5ed6 KP |
537 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
538 | for (clock = 0; clock <= max_clock; clock++) { | |
fe27d53e | 539 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
a4fc5ed6 | 540 | |
ea5b213a | 541 | if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) |
885a5fb5 | 542 | <= link_avail) { |
ea5b213a CW |
543 | intel_dp->link_bw = bws[clock]; |
544 | intel_dp->lane_count = lane_count; | |
545 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
28c97730 ZY |
546 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
547 | "count %d clock %d\n", | |
ea5b213a | 548 | intel_dp->link_bw, intel_dp->lane_count, |
a4fc5ed6 KP |
549 | adjusted_mode->clock); |
550 | return true; | |
551 | } | |
552 | } | |
553 | } | |
fe27d53e | 554 | |
ea5b213a | 555 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { |
fe27d53e | 556 | /* okay we failed just pick the highest */ |
ea5b213a CW |
557 | intel_dp->lane_count = max_lane_count; |
558 | intel_dp->link_bw = bws[max_clock]; | |
559 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
fe27d53e DA |
560 | DRM_DEBUG_KMS("Force picking display port link bw %02x lane " |
561 | "count %d clock %d\n", | |
ea5b213a | 562 | intel_dp->link_bw, intel_dp->lane_count, |
fe27d53e | 563 | adjusted_mode->clock); |
1d8e1c75 | 564 | |
fe27d53e DA |
565 | return true; |
566 | } | |
1d8e1c75 | 567 | |
a4fc5ed6 KP |
568 | return false; |
569 | } | |
570 | ||
571 | struct intel_dp_m_n { | |
572 | uint32_t tu; | |
573 | uint32_t gmch_m; | |
574 | uint32_t gmch_n; | |
575 | uint32_t link_m; | |
576 | uint32_t link_n; | |
577 | }; | |
578 | ||
579 | static void | |
580 | intel_reduce_ratio(uint32_t *num, uint32_t *den) | |
581 | { | |
582 | while (*num > 0xffffff || *den > 0xffffff) { | |
583 | *num >>= 1; | |
584 | *den >>= 1; | |
585 | } | |
586 | } | |
587 | ||
588 | static void | |
36e83a18 | 589 | intel_dp_compute_m_n(int bpp, |
a4fc5ed6 KP |
590 | int nlanes, |
591 | int pixel_clock, | |
592 | int link_clock, | |
593 | struct intel_dp_m_n *m_n) | |
594 | { | |
595 | m_n->tu = 64; | |
36e83a18 | 596 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
a4fc5ed6 KP |
597 | m_n->gmch_n = link_clock * nlanes; |
598 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
599 | m_n->link_m = pixel_clock; | |
600 | m_n->link_n = link_clock; | |
601 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
602 | } | |
603 | ||
36e83a18 ZY |
604 | bool intel_pch_has_edp(struct drm_crtc *crtc) |
605 | { | |
606 | struct drm_device *dev = crtc->dev; | |
607 | struct drm_mode_config *mode_config = &dev->mode_config; | |
608 | struct drm_encoder *encoder; | |
609 | ||
610 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a | 611 | struct intel_dp *intel_dp; |
36e83a18 | 612 | |
ea5b213a | 613 | if (encoder->crtc != crtc) |
36e83a18 ZY |
614 | continue; |
615 | ||
ea5b213a CW |
616 | intel_dp = enc_to_intel_dp(encoder); |
617 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) | |
618 | return intel_dp->is_pch_edp; | |
36e83a18 ZY |
619 | } |
620 | return false; | |
621 | } | |
622 | ||
a4fc5ed6 KP |
623 | void |
624 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
625 | struct drm_display_mode *adjusted_mode) | |
626 | { | |
627 | struct drm_device *dev = crtc->dev; | |
628 | struct drm_mode_config *mode_config = &dev->mode_config; | |
55f78c43 | 629 | struct drm_encoder *encoder; |
a4fc5ed6 KP |
630 | struct drm_i915_private *dev_priv = dev->dev_private; |
631 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
36e83a18 | 632 | int lane_count = 4, bpp = 24; |
a4fc5ed6 KP |
633 | struct intel_dp_m_n m_n; |
634 | ||
635 | /* | |
21d40d37 | 636 | * Find the lane count in the intel_encoder private |
a4fc5ed6 | 637 | */ |
55f78c43 | 638 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
ea5b213a | 639 | struct intel_dp *intel_dp; |
a4fc5ed6 | 640 | |
d8201ab6 | 641 | if (encoder->crtc != crtc) |
a4fc5ed6 KP |
642 | continue; |
643 | ||
ea5b213a CW |
644 | intel_dp = enc_to_intel_dp(encoder); |
645 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
646 | lane_count = intel_dp->lane_count; | |
647 | if (IS_PCH_eDP(intel_dp)) | |
36e83a18 | 648 | bpp = dev_priv->edp_bpp; |
a4fc5ed6 KP |
649 | break; |
650 | } | |
651 | } | |
652 | ||
653 | /* | |
654 | * Compute the GMCH and Link ratios. The '3' here is | |
655 | * the number of bytes_per_pixel post-LUT, which we always | |
656 | * set up for 8-bits of R/G/B, or 3 bytes total. | |
657 | */ | |
36e83a18 | 658 | intel_dp_compute_m_n(bpp, lane_count, |
a4fc5ed6 KP |
659 | mode->clock, adjusted_mode->clock, &m_n); |
660 | ||
c619eed4 | 661 | if (HAS_PCH_SPLIT(dev)) { |
5eb08b69 ZW |
662 | if (intel_crtc->pipe == 0) { |
663 | I915_WRITE(TRANSA_DATA_M1, | |
664 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
665 | m_n.gmch_m); | |
666 | I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n); | |
667 | I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m); | |
668 | I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n); | |
669 | } else { | |
670 | I915_WRITE(TRANSB_DATA_M1, | |
671 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
672 | m_n.gmch_m); | |
673 | I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n); | |
674 | I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m); | |
675 | I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n); | |
676 | } | |
a4fc5ed6 | 677 | } else { |
5eb08b69 ZW |
678 | if (intel_crtc->pipe == 0) { |
679 | I915_WRITE(PIPEA_GMCH_DATA_M, | |
680 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
681 | m_n.gmch_m); | |
682 | I915_WRITE(PIPEA_GMCH_DATA_N, | |
683 | m_n.gmch_n); | |
684 | I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m); | |
685 | I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n); | |
686 | } else { | |
687 | I915_WRITE(PIPEB_GMCH_DATA_M, | |
688 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
689 | m_n.gmch_m); | |
690 | I915_WRITE(PIPEB_GMCH_DATA_N, | |
691 | m_n.gmch_n); | |
692 | I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m); | |
693 | I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n); | |
694 | } | |
a4fc5ed6 KP |
695 | } |
696 | } | |
697 | ||
698 | static void | |
699 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
700 | struct drm_display_mode *adjusted_mode) | |
701 | { | |
e3421a18 | 702 | struct drm_device *dev = encoder->dev; |
ea5b213a CW |
703 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
704 | struct drm_crtc *crtc = intel_dp->base.enc.crtc; | |
a4fc5ed6 KP |
705 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
706 | ||
ea5b213a | 707 | intel_dp->DP = (DP_VOLTAGE_0_4 | |
9c9e7927 AJ |
708 | DP_PRE_EMPHASIS_0); |
709 | ||
710 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
ea5b213a | 711 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
9c9e7927 | 712 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
ea5b213a | 713 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
a4fc5ed6 | 714 | |
ea5b213a CW |
715 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
716 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
e3421a18 | 717 | else |
ea5b213a | 718 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
a4fc5ed6 | 719 | |
ea5b213a | 720 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 721 | case 1: |
ea5b213a | 722 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
723 | break; |
724 | case 2: | |
ea5b213a | 725 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
726 | break; |
727 | case 4: | |
ea5b213a | 728 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
729 | break; |
730 | } | |
ea5b213a CW |
731 | if (intel_dp->has_audio) |
732 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; | |
a4fc5ed6 | 733 | |
ea5b213a CW |
734 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
735 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
736 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
a4fc5ed6 KP |
737 | |
738 | /* | |
9962c925 | 739 | * Check for DPCD version > 1.1 and enhanced framing support |
a4fc5ed6 | 740 | */ |
ea5b213a CW |
741 | if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) { |
742 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; | |
743 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
a4fc5ed6 KP |
744 | } |
745 | ||
e3421a18 ZW |
746 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ |
747 | if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) | |
ea5b213a | 748 | intel_dp->DP |= DP_PIPEB_SELECT; |
32f9d658 | 749 | |
ea5b213a | 750 | if (IS_eDP(intel_dp)) { |
32f9d658 | 751 | /* don't miss out required setting for eDP */ |
ea5b213a | 752 | intel_dp->DP |= DP_PLL_ENABLE; |
32f9d658 | 753 | if (adjusted_mode->clock < 200000) |
ea5b213a | 754 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
32f9d658 | 755 | else |
ea5b213a | 756 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
32f9d658 | 757 | } |
a4fc5ed6 KP |
758 | } |
759 | ||
7eaf5547 JB |
760 | /* Returns true if the panel was already on when called */ |
761 | static bool ironlake_edp_panel_on (struct drm_device *dev) | |
9934c132 JB |
762 | { |
763 | struct drm_i915_private *dev_priv = dev->dev_private; | |
913d8d11 | 764 | u32 pp; |
9934c132 | 765 | |
913d8d11 | 766 | if (I915_READ(PCH_PP_STATUS) & PP_ON) |
7eaf5547 | 767 | return true; |
9934c132 JB |
768 | |
769 | pp = I915_READ(PCH_PP_CONTROL); | |
37c6c9b0 JB |
770 | |
771 | /* ILK workaround: disable reset around power sequence */ | |
772 | pp &= ~PANEL_POWER_RESET; | |
773 | I915_WRITE(PCH_PP_CONTROL, pp); | |
774 | POSTING_READ(PCH_PP_CONTROL); | |
775 | ||
9934c132 JB |
776 | pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; |
777 | I915_WRITE(PCH_PP_CONTROL, pp); | |
9934c132 | 778 | |
481b6af3 | 779 | if (wait_for(I915_READ(PCH_PP_STATUS) & PP_ON, 5000)) |
913d8d11 CW |
780 | DRM_ERROR("panel on wait timed out: 0x%08x\n", |
781 | I915_READ(PCH_PP_STATUS)); | |
9934c132 JB |
782 | |
783 | pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD); | |
37c6c9b0 | 784 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 785 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 786 | POSTING_READ(PCH_PP_CONTROL); |
7eaf5547 JB |
787 | |
788 | return false; | |
9934c132 JB |
789 | } |
790 | ||
791 | static void ironlake_edp_panel_off (struct drm_device *dev) | |
792 | { | |
793 | struct drm_i915_private *dev_priv = dev->dev_private; | |
913d8d11 | 794 | u32 pp; |
9934c132 JB |
795 | |
796 | pp = I915_READ(PCH_PP_CONTROL); | |
37c6c9b0 JB |
797 | |
798 | /* ILK workaround: disable reset around power sequence */ | |
799 | pp &= ~PANEL_POWER_RESET; | |
800 | I915_WRITE(PCH_PP_CONTROL, pp); | |
801 | POSTING_READ(PCH_PP_CONTROL); | |
802 | ||
9934c132 JB |
803 | pp &= ~POWER_TARGET_ON; |
804 | I915_WRITE(PCH_PP_CONTROL, pp); | |
9934c132 | 805 | |
481b6af3 | 806 | if (wait_for((I915_READ(PCH_PP_STATUS) & PP_ON) == 0, 5000)) |
913d8d11 CW |
807 | DRM_ERROR("panel off wait timed out: 0x%08x\n", |
808 | I915_READ(PCH_PP_STATUS)); | |
9934c132 JB |
809 | |
810 | /* Make sure VDD is enabled so DP AUX will work */ | |
37c6c9b0 | 811 | pp |= EDP_FORCE_VDD | PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 812 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 813 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 JB |
814 | } |
815 | ||
b2094bba JB |
816 | static void ironlake_edp_panel_vdd_on(struct drm_device *dev) |
817 | { | |
818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
819 | u32 pp; | |
820 | ||
821 | pp = I915_READ(PCH_PP_CONTROL); | |
822 | pp |= EDP_FORCE_VDD; | |
823 | I915_WRITE(PCH_PP_CONTROL, pp); | |
824 | POSTING_READ(PCH_PP_CONTROL); | |
825 | } | |
826 | ||
827 | static void ironlake_edp_panel_vdd_off(struct drm_device *dev) | |
828 | { | |
829 | struct drm_i915_private *dev_priv = dev->dev_private; | |
830 | u32 pp; | |
831 | ||
832 | pp = I915_READ(PCH_PP_CONTROL); | |
833 | pp &= ~EDP_FORCE_VDD; | |
834 | I915_WRITE(PCH_PP_CONTROL, pp); | |
835 | POSTING_READ(PCH_PP_CONTROL); | |
836 | } | |
837 | ||
f2b115e6 | 838 | static void ironlake_edp_backlight_on (struct drm_device *dev) |
32f9d658 ZW |
839 | { |
840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
841 | u32 pp; | |
842 | ||
28c97730 | 843 | DRM_DEBUG_KMS("\n"); |
32f9d658 ZW |
844 | pp = I915_READ(PCH_PP_CONTROL); |
845 | pp |= EDP_BLC_ENABLE; | |
846 | I915_WRITE(PCH_PP_CONTROL, pp); | |
847 | } | |
848 | ||
f2b115e6 | 849 | static void ironlake_edp_backlight_off (struct drm_device *dev) |
32f9d658 ZW |
850 | { |
851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
852 | u32 pp; | |
853 | ||
28c97730 | 854 | DRM_DEBUG_KMS("\n"); |
32f9d658 ZW |
855 | pp = I915_READ(PCH_PP_CONTROL); |
856 | pp &= ~EDP_BLC_ENABLE; | |
857 | I915_WRITE(PCH_PP_CONTROL, pp); | |
858 | } | |
a4fc5ed6 | 859 | |
d240f20f JB |
860 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
861 | { | |
862 | struct drm_device *dev = encoder->dev; | |
863 | struct drm_i915_private *dev_priv = dev->dev_private; | |
864 | u32 dpa_ctl; | |
865 | ||
866 | DRM_DEBUG_KMS("\n"); | |
867 | dpa_ctl = I915_READ(DP_A); | |
868 | dpa_ctl &= ~DP_PLL_ENABLE; | |
869 | I915_WRITE(DP_A, dpa_ctl); | |
870 | } | |
871 | ||
872 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) | |
873 | { | |
874 | struct drm_device *dev = encoder->dev; | |
875 | struct drm_i915_private *dev_priv = dev->dev_private; | |
876 | u32 dpa_ctl; | |
877 | ||
878 | dpa_ctl = I915_READ(DP_A); | |
879 | dpa_ctl |= DP_PLL_ENABLE; | |
880 | I915_WRITE(DP_A, dpa_ctl); | |
881 | udelay(200); | |
882 | } | |
883 | ||
884 | static void intel_dp_prepare(struct drm_encoder *encoder) | |
885 | { | |
886 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
887 | struct drm_device *dev = encoder->dev; | |
888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
889 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); | |
890 | ||
7eaf5547 | 891 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { |
d240f20f | 892 | ironlake_edp_backlight_off(dev); |
b2094bba | 893 | ironlake_edp_panel_vdd_on(dev); |
d240f20f JB |
894 | ironlake_edp_pll_on(encoder); |
895 | } | |
896 | if (dp_reg & DP_PORT_EN) | |
897 | intel_dp_link_down(intel_dp); | |
898 | } | |
899 | ||
900 | static void intel_dp_commit(struct drm_encoder *encoder) | |
901 | { | |
902 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
903 | struct drm_device *dev = encoder->dev; | |
904 | struct drm_i915_private *dev_priv = dev->dev_private; | |
905 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); | |
906 | ||
907 | if (!(dp_reg & DP_PORT_EN)) { | |
908 | intel_dp_link_train(intel_dp); | |
909 | } | |
b2094bba JB |
910 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { |
911 | ironlake_edp_panel_on(dev); | |
d240f20f | 912 | ironlake_edp_backlight_on(dev); |
b2094bba | 913 | } |
d240f20f JB |
914 | } |
915 | ||
a4fc5ed6 KP |
916 | static void |
917 | intel_dp_dpms(struct drm_encoder *encoder, int mode) | |
918 | { | |
ea5b213a | 919 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
55f78c43 | 920 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 | 921 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 922 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
a4fc5ed6 KP |
923 | |
924 | if (mode != DRM_MODE_DPMS_ON) { | |
7643a7fa JB |
925 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { |
926 | ironlake_edp_backlight_off(dev); | |
927 | ironlake_edp_panel_off(dev); | |
32f9d658 | 928 | } |
7643a7fa JB |
929 | if (dp_reg & DP_PORT_EN) |
930 | intel_dp_link_down(intel_dp); | |
d240f20f JB |
931 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) |
932 | ironlake_edp_pll_off(encoder); | |
a4fc5ed6 | 933 | } else { |
32f9d658 | 934 | if (!(dp_reg & DP_PORT_EN)) { |
7643a7fa | 935 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) |
9934c132 | 936 | ironlake_edp_panel_on(dev); |
7643a7fa JB |
937 | intel_dp_link_train(intel_dp); |
938 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) | |
f2b115e6 | 939 | ironlake_edp_backlight_on(dev); |
32f9d658 | 940 | } |
a4fc5ed6 | 941 | } |
ea5b213a | 942 | intel_dp->dpms_mode = mode; |
a4fc5ed6 KP |
943 | } |
944 | ||
945 | /* | |
946 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
947 | * link status information | |
948 | */ | |
949 | static bool | |
ea5b213a | 950 | intel_dp_get_link_status(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
951 | uint8_t link_status[DP_LINK_STATUS_SIZE]) |
952 | { | |
953 | int ret; | |
954 | ||
ea5b213a | 955 | ret = intel_dp_aux_native_read(intel_dp, |
a4fc5ed6 KP |
956 | DP_LANE0_1_STATUS, |
957 | link_status, DP_LINK_STATUS_SIZE); | |
958 | if (ret != DP_LINK_STATUS_SIZE) | |
959 | return false; | |
960 | return true; | |
961 | } | |
962 | ||
963 | static uint8_t | |
964 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
965 | int r) | |
966 | { | |
967 | return link_status[r - DP_LANE0_1_STATUS]; | |
968 | } | |
969 | ||
a4fc5ed6 KP |
970 | static uint8_t |
971 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
972 | int lane) | |
973 | { | |
974 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
975 | int s = ((lane & 1) ? | |
976 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
977 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
978 | uint8_t l = intel_dp_link_status(link_status, i); | |
979 | ||
980 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
981 | } | |
982 | ||
983 | static uint8_t | |
984 | intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
985 | int lane) | |
986 | { | |
987 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
988 | int s = ((lane & 1) ? | |
989 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
990 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
991 | uint8_t l = intel_dp_link_status(link_status, i); | |
992 | ||
993 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
994 | } | |
995 | ||
996 | ||
997 | #if 0 | |
998 | static char *voltage_names[] = { | |
999 | "0.4V", "0.6V", "0.8V", "1.2V" | |
1000 | }; | |
1001 | static char *pre_emph_names[] = { | |
1002 | "0dB", "3.5dB", "6dB", "9.5dB" | |
1003 | }; | |
1004 | static char *link_train_names[] = { | |
1005 | "pattern 1", "pattern 2", "idle", "off" | |
1006 | }; | |
1007 | #endif | |
1008 | ||
1009 | /* | |
1010 | * These are source-specific values; current Intel hardware supports | |
1011 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1012 | */ | |
1013 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 | |
1014 | ||
1015 | static uint8_t | |
1016 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) | |
1017 | { | |
1018 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1019 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1020 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1021 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1022 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1023 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1024 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1025 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1026 | default: | |
1027 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1028 | } | |
1029 | } | |
1030 | ||
1031 | static void | |
ea5b213a | 1032 | intel_get_adjust_train(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
1033 | uint8_t link_status[DP_LINK_STATUS_SIZE], |
1034 | int lane_count, | |
1035 | uint8_t train_set[4]) | |
1036 | { | |
1037 | uint8_t v = 0; | |
1038 | uint8_t p = 0; | |
1039 | int lane; | |
1040 | ||
1041 | for (lane = 0; lane < lane_count; lane++) { | |
1042 | uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane); | |
1043 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane); | |
1044 | ||
1045 | if (this_v > v) | |
1046 | v = this_v; | |
1047 | if (this_p > p) | |
1048 | p = this_p; | |
1049 | } | |
1050 | ||
1051 | if (v >= I830_DP_VOLTAGE_MAX) | |
1052 | v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; | |
1053 | ||
1054 | if (p >= intel_dp_pre_emphasis_max(v)) | |
1055 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
1056 | ||
1057 | for (lane = 0; lane < 4; lane++) | |
1058 | train_set[lane] = v | p; | |
1059 | } | |
1060 | ||
1061 | static uint32_t | |
1062 | intel_dp_signal_levels(uint8_t train_set, int lane_count) | |
1063 | { | |
1064 | uint32_t signal_levels = 0; | |
1065 | ||
1066 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1067 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1068 | default: | |
1069 | signal_levels |= DP_VOLTAGE_0_4; | |
1070 | break; | |
1071 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1072 | signal_levels |= DP_VOLTAGE_0_6; | |
1073 | break; | |
1074 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1075 | signal_levels |= DP_VOLTAGE_0_8; | |
1076 | break; | |
1077 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1078 | signal_levels |= DP_VOLTAGE_1_2; | |
1079 | break; | |
1080 | } | |
1081 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
1082 | case DP_TRAIN_PRE_EMPHASIS_0: | |
1083 | default: | |
1084 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1085 | break; | |
1086 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1087 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1088 | break; | |
1089 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1090 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1091 | break; | |
1092 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1093 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1094 | break; | |
1095 | } | |
1096 | return signal_levels; | |
1097 | } | |
1098 | ||
e3421a18 ZW |
1099 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1100 | static uint32_t | |
1101 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1102 | { | |
1103 | switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) { | |
1104 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
1105 | return EDP_LINK_TRAIN_400MV_0DB_SNB_B; | |
1106 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
1107 | return EDP_LINK_TRAIN_400MV_6DB_SNB_B; | |
1108 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1109 | return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B; | |
1110 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | |
1111 | return EDP_LINK_TRAIN_800MV_0DB_SNB_B; | |
1112 | default: | |
1113 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n"); | |
1114 | return EDP_LINK_TRAIN_400MV_0DB_SNB_B; | |
1115 | } | |
1116 | } | |
1117 | ||
a4fc5ed6 KP |
1118 | static uint8_t |
1119 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1120 | int lane) | |
1121 | { | |
1122 | int i = DP_LANE0_1_STATUS + (lane >> 1); | |
1123 | int s = (lane & 1) * 4; | |
1124 | uint8_t l = intel_dp_link_status(link_status, i); | |
1125 | ||
1126 | return (l >> s) & 0xf; | |
1127 | } | |
1128 | ||
1129 | /* Check for clock recovery is done on all channels */ | |
1130 | static bool | |
1131 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1132 | { | |
1133 | int lane; | |
1134 | uint8_t lane_status; | |
1135 | ||
1136 | for (lane = 0; lane < lane_count; lane++) { | |
1137 | lane_status = intel_get_lane_status(link_status, lane); | |
1138 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
1139 | return false; | |
1140 | } | |
1141 | return true; | |
1142 | } | |
1143 | ||
1144 | /* Check to see if channel eq is done on all channels */ | |
1145 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ | |
1146 | DP_LANE_CHANNEL_EQ_DONE|\ | |
1147 | DP_LANE_SYMBOL_LOCKED) | |
1148 | static bool | |
1149 | intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1150 | { | |
1151 | uint8_t lane_align; | |
1152 | uint8_t lane_status; | |
1153 | int lane; | |
1154 | ||
1155 | lane_align = intel_dp_link_status(link_status, | |
1156 | DP_LANE_ALIGN_STATUS_UPDATED); | |
1157 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
1158 | return false; | |
1159 | for (lane = 0; lane < lane_count; lane++) { | |
1160 | lane_status = intel_get_lane_status(link_status, lane); | |
1161 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) | |
1162 | return false; | |
1163 | } | |
1164 | return true; | |
1165 | } | |
1166 | ||
1167 | static bool | |
ea5b213a | 1168 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
1169 | uint32_t dp_reg_value, |
1170 | uint8_t dp_train_pat, | |
1171 | uint8_t train_set[4], | |
1172 | bool first) | |
1173 | { | |
ea5b213a | 1174 | struct drm_device *dev = intel_dp->base.enc.dev; |
a4fc5ed6 | 1175 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d0498a2 | 1176 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.enc.crtc); |
a4fc5ed6 KP |
1177 | int ret; |
1178 | ||
ea5b213a CW |
1179 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1180 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1181 | if (first) |
9d0498a2 | 1182 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
a4fc5ed6 | 1183 | |
ea5b213a | 1184 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1185 | DP_TRAINING_PATTERN_SET, |
1186 | dp_train_pat); | |
1187 | ||
ea5b213a | 1188 | ret = intel_dp_aux_native_write(intel_dp, |
a4fc5ed6 KP |
1189 | DP_TRAINING_LANE0_SET, train_set, 4); |
1190 | if (ret != 4) | |
1191 | return false; | |
1192 | ||
1193 | return true; | |
1194 | } | |
1195 | ||
1196 | static void | |
ea5b213a | 1197 | intel_dp_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1198 | { |
ea5b213a | 1199 | struct drm_device *dev = intel_dp->base.enc.dev; |
a4fc5ed6 | 1200 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1201 | uint8_t train_set[4]; |
1202 | uint8_t link_status[DP_LINK_STATUS_SIZE]; | |
1203 | int i; | |
1204 | uint8_t voltage; | |
1205 | bool clock_recovery = false; | |
1206 | bool channel_eq = false; | |
1207 | bool first = true; | |
1208 | int tries; | |
e3421a18 | 1209 | u32 reg; |
ea5b213a | 1210 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 KP |
1211 | |
1212 | /* Write the link configuration data */ | |
ea5b213a CW |
1213 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, |
1214 | intel_dp->link_configuration, | |
1215 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
1216 | |
1217 | DP |= DP_PORT_EN; | |
ea5b213a | 1218 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
e3421a18 ZW |
1219 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1220 | else | |
1221 | DP &= ~DP_LINK_TRAIN_MASK; | |
a4fc5ed6 KP |
1222 | memset(train_set, 0, 4); |
1223 | voltage = 0xff; | |
1224 | tries = 0; | |
1225 | clock_recovery = false; | |
1226 | for (;;) { | |
1227 | /* Use train_set[0] to set the voltage and pre emphasis values */ | |
e3421a18 | 1228 | uint32_t signal_levels; |
ea5b213a | 1229 | if (IS_GEN6(dev) && IS_eDP(intel_dp)) { |
e3421a18 ZW |
1230 | signal_levels = intel_gen6_edp_signal_levels(train_set[0]); |
1231 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; | |
1232 | } else { | |
ea5b213a | 1233 | signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1234 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1235 | } | |
a4fc5ed6 | 1236 | |
ea5b213a | 1237 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
e3421a18 ZW |
1238 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
1239 | else | |
1240 | reg = DP | DP_LINK_TRAIN_PAT_1; | |
1241 | ||
ea5b213a | 1242 | if (!intel_dp_set_link_train(intel_dp, reg, |
a4fc5ed6 KP |
1243 | DP_TRAINING_PATTERN_1, train_set, first)) |
1244 | break; | |
1245 | first = false; | |
1246 | /* Set training pattern 1 */ | |
1247 | ||
1248 | udelay(100); | |
ea5b213a | 1249 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
a4fc5ed6 KP |
1250 | break; |
1251 | ||
ea5b213a | 1252 | if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
a4fc5ed6 KP |
1253 | clock_recovery = true; |
1254 | break; | |
1255 | } | |
1256 | ||
1257 | /* Check to see if we've tried the max voltage */ | |
ea5b213a | 1258 | for (i = 0; i < intel_dp->lane_count; i++) |
a4fc5ed6 KP |
1259 | if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
1260 | break; | |
ea5b213a | 1261 | if (i == intel_dp->lane_count) |
a4fc5ed6 KP |
1262 | break; |
1263 | ||
1264 | /* Check to see if we've tried the same voltage 5 times */ | |
1265 | if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { | |
1266 | ++tries; | |
1267 | if (tries == 5) | |
1268 | break; | |
1269 | } else | |
1270 | tries = 0; | |
1271 | voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
1272 | ||
1273 | /* Compute new train_set as requested by target */ | |
ea5b213a | 1274 | intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set); |
a4fc5ed6 KP |
1275 | } |
1276 | ||
1277 | /* channel equalization */ | |
1278 | tries = 0; | |
1279 | channel_eq = false; | |
1280 | for (;;) { | |
1281 | /* Use train_set[0] to set the voltage and pre emphasis values */ | |
e3421a18 ZW |
1282 | uint32_t signal_levels; |
1283 | ||
ea5b213a | 1284 | if (IS_GEN6(dev) && IS_eDP(intel_dp)) { |
e3421a18 ZW |
1285 | signal_levels = intel_gen6_edp_signal_levels(train_set[0]); |
1286 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; | |
1287 | } else { | |
ea5b213a | 1288 | signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1289 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1290 | } | |
1291 | ||
ea5b213a | 1292 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
e3421a18 ZW |
1293 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
1294 | else | |
1295 | reg = DP | DP_LINK_TRAIN_PAT_2; | |
a4fc5ed6 KP |
1296 | |
1297 | /* channel eq pattern */ | |
ea5b213a | 1298 | if (!intel_dp_set_link_train(intel_dp, reg, |
a4fc5ed6 KP |
1299 | DP_TRAINING_PATTERN_2, train_set, |
1300 | false)) | |
1301 | break; | |
1302 | ||
1303 | udelay(400); | |
ea5b213a | 1304 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
a4fc5ed6 KP |
1305 | break; |
1306 | ||
ea5b213a | 1307 | if (intel_channel_eq_ok(link_status, intel_dp->lane_count)) { |
a4fc5ed6 KP |
1308 | channel_eq = true; |
1309 | break; | |
1310 | } | |
1311 | ||
1312 | /* Try 5 times */ | |
1313 | if (tries > 5) | |
1314 | break; | |
1315 | ||
1316 | /* Compute new train_set as requested by target */ | |
ea5b213a | 1317 | intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set); |
a4fc5ed6 KP |
1318 | ++tries; |
1319 | } | |
1320 | ||
ea5b213a | 1321 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
e3421a18 ZW |
1322 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
1323 | else | |
1324 | reg = DP | DP_LINK_TRAIN_OFF; | |
1325 | ||
ea5b213a CW |
1326 | I915_WRITE(intel_dp->output_reg, reg); |
1327 | POSTING_READ(intel_dp->output_reg); | |
1328 | intel_dp_aux_native_write_1(intel_dp, | |
a4fc5ed6 KP |
1329 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
1330 | } | |
1331 | ||
1332 | static void | |
ea5b213a | 1333 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 1334 | { |
ea5b213a | 1335 | struct drm_device *dev = intel_dp->base.enc.dev; |
a4fc5ed6 | 1336 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1337 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1338 | |
28c97730 | 1339 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1340 | |
ea5b213a | 1341 | if (IS_eDP(intel_dp)) { |
32f9d658 | 1342 | DP &= ~DP_PLL_ENABLE; |
ea5b213a CW |
1343 | I915_WRITE(intel_dp->output_reg, DP); |
1344 | POSTING_READ(intel_dp->output_reg); | |
32f9d658 ZW |
1345 | udelay(100); |
1346 | } | |
1347 | ||
ea5b213a | 1348 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) { |
e3421a18 | 1349 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a CW |
1350 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
1351 | POSTING_READ(intel_dp->output_reg); | |
e3421a18 ZW |
1352 | } else { |
1353 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a CW |
1354 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
1355 | POSTING_READ(intel_dp->output_reg); | |
e3421a18 | 1356 | } |
5eb08b69 ZW |
1357 | |
1358 | udelay(17000); | |
1359 | ||
ea5b213a | 1360 | if (IS_eDP(intel_dp)) |
32f9d658 | 1361 | DP |= DP_LINK_TRAIN_OFF; |
ea5b213a CW |
1362 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
1363 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 KP |
1364 | } |
1365 | ||
a4fc5ed6 KP |
1366 | /* |
1367 | * According to DP spec | |
1368 | * 5.1.2: | |
1369 | * 1. Read DPCD | |
1370 | * 2. Configure link according to Receiver Capabilities | |
1371 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
1372 | * 4. Check link status on receipt of hot-plug interrupt | |
1373 | */ | |
1374 | ||
1375 | static void | |
ea5b213a | 1376 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1377 | { |
a4fc5ed6 KP |
1378 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
1379 | ||
ea5b213a | 1380 | if (!intel_dp->base.enc.crtc) |
a4fc5ed6 KP |
1381 | return; |
1382 | ||
ea5b213a CW |
1383 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
1384 | intel_dp_link_down(intel_dp); | |
a4fc5ed6 KP |
1385 | return; |
1386 | } | |
1387 | ||
ea5b213a CW |
1388 | if (!intel_channel_eq_ok(link_status, intel_dp->lane_count)) |
1389 | intel_dp_link_train(intel_dp); | |
a4fc5ed6 | 1390 | } |
a4fc5ed6 | 1391 | |
5eb08b69 | 1392 | static enum drm_connector_status |
f2b115e6 | 1393 | ironlake_dp_detect(struct drm_connector *connector) |
5eb08b69 | 1394 | { |
55f78c43 | 1395 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
ea5b213a | 1396 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
5eb08b69 ZW |
1397 | enum drm_connector_status status; |
1398 | ||
7eaf5547 JB |
1399 | /* Panel needs power for AUX to work */ |
1400 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) | |
b2094bba | 1401 | ironlake_edp_panel_vdd_on(connector->dev); |
5eb08b69 | 1402 | status = connector_status_disconnected; |
ea5b213a CW |
1403 | if (intel_dp_aux_native_read(intel_dp, |
1404 | 0x000, intel_dp->dpcd, | |
1405 | sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) | |
5eb08b69 | 1406 | { |
ea5b213a | 1407 | if (intel_dp->dpcd[0] != 0) |
5eb08b69 ZW |
1408 | status = connector_status_connected; |
1409 | } | |
ea5b213a CW |
1410 | DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0], |
1411 | intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]); | |
b2094bba JB |
1412 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) |
1413 | ironlake_edp_panel_vdd_off(connector->dev); | |
5eb08b69 ZW |
1414 | return status; |
1415 | } | |
1416 | ||
a4fc5ed6 KP |
1417 | /** |
1418 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. | |
1419 | * | |
1420 | * \return true if DP port is connected. | |
1421 | * \return false if DP port is disconnected. | |
1422 | */ | |
1423 | static enum drm_connector_status | |
1424 | intel_dp_detect(struct drm_connector *connector) | |
1425 | { | |
55f78c43 | 1426 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
ea5b213a CW |
1427 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1428 | struct drm_device *dev = intel_dp->base.enc.dev; | |
a4fc5ed6 | 1429 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1430 | uint32_t temp, bit; |
1431 | enum drm_connector_status status; | |
1432 | ||
ea5b213a | 1433 | intel_dp->has_audio = false; |
a4fc5ed6 | 1434 | |
c619eed4 | 1435 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1436 | return ironlake_dp_detect(connector); |
5eb08b69 | 1437 | |
ea5b213a | 1438 | switch (intel_dp->output_reg) { |
a4fc5ed6 KP |
1439 | case DP_B: |
1440 | bit = DPB_HOTPLUG_INT_STATUS; | |
1441 | break; | |
1442 | case DP_C: | |
1443 | bit = DPC_HOTPLUG_INT_STATUS; | |
1444 | break; | |
1445 | case DP_D: | |
1446 | bit = DPD_HOTPLUG_INT_STATUS; | |
1447 | break; | |
1448 | default: | |
1449 | return connector_status_unknown; | |
1450 | } | |
1451 | ||
1452 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
1453 | ||
1454 | if ((temp & bit) == 0) | |
1455 | return connector_status_disconnected; | |
1456 | ||
1457 | status = connector_status_disconnected; | |
ea5b213a CW |
1458 | if (intel_dp_aux_native_read(intel_dp, |
1459 | 0x000, intel_dp->dpcd, | |
1460 | sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) | |
a4fc5ed6 | 1461 | { |
ea5b213a | 1462 | if (intel_dp->dpcd[0] != 0) |
a4fc5ed6 KP |
1463 | status = connector_status_connected; |
1464 | } | |
1465 | return status; | |
1466 | } | |
1467 | ||
1468 | static int intel_dp_get_modes(struct drm_connector *connector) | |
1469 | { | |
55f78c43 | 1470 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
ea5b213a CW |
1471 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1472 | struct drm_device *dev = intel_dp->base.enc.dev; | |
32f9d658 ZW |
1473 | struct drm_i915_private *dev_priv = dev->dev_private; |
1474 | int ret; | |
a4fc5ed6 KP |
1475 | |
1476 | /* We should parse the EDID data and find out if it has an audio sink | |
1477 | */ | |
1478 | ||
ea5b213a | 1479 | ret = intel_ddc_get_modes(connector, intel_dp->base.ddc_bus); |
b9efc480 | 1480 | if (ret) { |
ea5b213a | 1481 | if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && |
b9efc480 ZY |
1482 | !dev_priv->panel_fixed_mode) { |
1483 | struct drm_display_mode *newmode; | |
1484 | list_for_each_entry(newmode, &connector->probed_modes, | |
1485 | head) { | |
1486 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
1487 | dev_priv->panel_fixed_mode = | |
1488 | drm_mode_duplicate(dev, newmode); | |
1489 | break; | |
1490 | } | |
1491 | } | |
1492 | } | |
1493 | ||
32f9d658 | 1494 | return ret; |
b9efc480 | 1495 | } |
32f9d658 ZW |
1496 | |
1497 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ | |
ea5b213a | 1498 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { |
32f9d658 ZW |
1499 | if (dev_priv->panel_fixed_mode != NULL) { |
1500 | struct drm_display_mode *mode; | |
1501 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); | |
1502 | drm_mode_probed_add(connector, mode); | |
1503 | return 1; | |
1504 | } | |
1505 | } | |
1506 | return 0; | |
a4fc5ed6 KP |
1507 | } |
1508 | ||
1509 | static void | |
1510 | intel_dp_destroy (struct drm_connector *connector) | |
1511 | { | |
a4fc5ed6 KP |
1512 | drm_sysfs_connector_remove(connector); |
1513 | drm_connector_cleanup(connector); | |
55f78c43 | 1514 | kfree(connector); |
a4fc5ed6 KP |
1515 | } |
1516 | ||
24d05927 DV |
1517 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
1518 | { | |
1519 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1520 | ||
1521 | i2c_del_adapter(&intel_dp->adapter); | |
1522 | drm_encoder_cleanup(encoder); | |
1523 | kfree(intel_dp); | |
1524 | } | |
1525 | ||
a4fc5ed6 KP |
1526 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
1527 | .dpms = intel_dp_dpms, | |
1528 | .mode_fixup = intel_dp_mode_fixup, | |
d240f20f | 1529 | .prepare = intel_dp_prepare, |
a4fc5ed6 | 1530 | .mode_set = intel_dp_mode_set, |
d240f20f | 1531 | .commit = intel_dp_commit, |
a4fc5ed6 KP |
1532 | }; |
1533 | ||
1534 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
1535 | .dpms = drm_helper_connector_dpms, | |
a4fc5ed6 KP |
1536 | .detect = intel_dp_detect, |
1537 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1538 | .destroy = intel_dp_destroy, | |
1539 | }; | |
1540 | ||
1541 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
1542 | .get_modes = intel_dp_get_modes, | |
1543 | .mode_valid = intel_dp_mode_valid, | |
55f78c43 | 1544 | .best_encoder = intel_attached_encoder, |
a4fc5ed6 KP |
1545 | }; |
1546 | ||
a4fc5ed6 | 1547 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 1548 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
1549 | }; |
1550 | ||
995b6762 | 1551 | static void |
21d40d37 | 1552 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 1553 | { |
ea5b213a | 1554 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
c8110e52 | 1555 | |
ea5b213a CW |
1556 | if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON) |
1557 | intel_dp_check_link_status(intel_dp); | |
c8110e52 | 1558 | } |
6207937d | 1559 | |
e3421a18 ZW |
1560 | /* Return which DP Port should be selected for Transcoder DP control */ |
1561 | int | |
1562 | intel_trans_dp_port_sel (struct drm_crtc *crtc) | |
1563 | { | |
1564 | struct drm_device *dev = crtc->dev; | |
1565 | struct drm_mode_config *mode_config = &dev->mode_config; | |
1566 | struct drm_encoder *encoder; | |
e3421a18 ZW |
1567 | |
1568 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a CW |
1569 | struct intel_dp *intel_dp; |
1570 | ||
d8201ab6 | 1571 | if (encoder->crtc != crtc) |
e3421a18 ZW |
1572 | continue; |
1573 | ||
ea5b213a CW |
1574 | intel_dp = enc_to_intel_dp(encoder); |
1575 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) | |
1576 | return intel_dp->output_reg; | |
e3421a18 | 1577 | } |
ea5b213a | 1578 | |
e3421a18 ZW |
1579 | return -1; |
1580 | } | |
1581 | ||
36e83a18 | 1582 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 1583 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
1584 | { |
1585 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1586 | struct child_device_config *p_child; | |
1587 | int i; | |
1588 | ||
1589 | if (!dev_priv->child_dev_num) | |
1590 | return false; | |
1591 | ||
1592 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
1593 | p_child = dev_priv->child_dev + i; | |
1594 | ||
1595 | if (p_child->dvo_port == PORT_IDPD && | |
1596 | p_child->device_type == DEVICE_TYPE_eDP) | |
1597 | return true; | |
1598 | } | |
1599 | return false; | |
1600 | } | |
1601 | ||
a4fc5ed6 KP |
1602 | void |
1603 | intel_dp_init(struct drm_device *dev, int output_reg) | |
1604 | { | |
1605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1606 | struct drm_connector *connector; | |
ea5b213a | 1607 | struct intel_dp *intel_dp; |
21d40d37 | 1608 | struct intel_encoder *intel_encoder; |
55f78c43 | 1609 | struct intel_connector *intel_connector; |
5eb08b69 | 1610 | const char *name = NULL; |
b329530c | 1611 | int type; |
a4fc5ed6 | 1612 | |
ea5b213a CW |
1613 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
1614 | if (!intel_dp) | |
a4fc5ed6 KP |
1615 | return; |
1616 | ||
55f78c43 ZW |
1617 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
1618 | if (!intel_connector) { | |
ea5b213a | 1619 | kfree(intel_dp); |
55f78c43 ZW |
1620 | return; |
1621 | } | |
ea5b213a | 1622 | intel_encoder = &intel_dp->base; |
55f78c43 | 1623 | |
ea5b213a | 1624 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
b329530c | 1625 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 1626 | intel_dp->is_pch_edp = true; |
b329530c | 1627 | |
ea5b213a | 1628 | if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) { |
b329530c AJ |
1629 | type = DRM_MODE_CONNECTOR_eDP; |
1630 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
1631 | } else { | |
1632 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
1633 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
1634 | } | |
1635 | ||
55f78c43 | 1636 | connector = &intel_connector->base; |
b329530c | 1637 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
1638 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
1639 | ||
eb1f8e4f DA |
1640 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
1641 | ||
652af9d7 | 1642 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
21d40d37 | 1643 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
652af9d7 | 1644 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
21d40d37 | 1645 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
652af9d7 | 1646 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
21d40d37 | 1647 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
f8aed700 | 1648 | |
ea5b213a | 1649 | if (IS_eDP(intel_dp)) |
21d40d37 | 1650 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
6251ec0a | 1651 | |
21d40d37 | 1652 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
a4fc5ed6 KP |
1653 | connector->interlace_allowed = true; |
1654 | connector->doublescan_allowed = 0; | |
1655 | ||
ea5b213a CW |
1656 | intel_dp->output_reg = output_reg; |
1657 | intel_dp->has_audio = false; | |
1658 | intel_dp->dpms_mode = DRM_MODE_DPMS_ON; | |
a4fc5ed6 | 1659 | |
21d40d37 | 1660 | drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs, |
a4fc5ed6 | 1661 | DRM_MODE_ENCODER_TMDS); |
21d40d37 | 1662 | drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs); |
a4fc5ed6 | 1663 | |
55f78c43 | 1664 | drm_mode_connector_attach_encoder(&intel_connector->base, |
21d40d37 | 1665 | &intel_encoder->enc); |
a4fc5ed6 KP |
1666 | drm_sysfs_connector_add(connector); |
1667 | ||
1668 | /* Set up the DDC bus. */ | |
5eb08b69 | 1669 | switch (output_reg) { |
32f9d658 ZW |
1670 | case DP_A: |
1671 | name = "DPDDC-A"; | |
1672 | break; | |
5eb08b69 ZW |
1673 | case DP_B: |
1674 | case PCH_DP_B: | |
b01f2c3a JB |
1675 | dev_priv->hotplug_supported_mask |= |
1676 | HDMIB_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1677 | name = "DPDDC-B"; |
1678 | break; | |
1679 | case DP_C: | |
1680 | case PCH_DP_C: | |
b01f2c3a JB |
1681 | dev_priv->hotplug_supported_mask |= |
1682 | HDMIC_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1683 | name = "DPDDC-C"; |
1684 | break; | |
1685 | case DP_D: | |
1686 | case PCH_DP_D: | |
b01f2c3a JB |
1687 | dev_priv->hotplug_supported_mask |= |
1688 | HDMID_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1689 | name = "DPDDC-D"; |
1690 | break; | |
1691 | } | |
1692 | ||
ea5b213a | 1693 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
32f9d658 | 1694 | |
ea5b213a | 1695 | intel_encoder->ddc_bus = &intel_dp->adapter; |
21d40d37 | 1696 | intel_encoder->hot_plug = intel_dp_hot_plug; |
a4fc5ed6 | 1697 | |
ea5b213a | 1698 | if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) { |
32f9d658 ZW |
1699 | /* initialize panel mode from VBT if available for eDP */ |
1700 | if (dev_priv->lfp_lvds_vbt_mode) { | |
1701 | dev_priv->panel_fixed_mode = | |
1702 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); | |
1703 | if (dev_priv->panel_fixed_mode) { | |
1704 | dev_priv->panel_fixed_mode->type |= | |
1705 | DRM_MODE_TYPE_PREFERRED; | |
1706 | } | |
1707 | } | |
1708 | } | |
1709 | ||
a4fc5ed6 KP |
1710 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
1711 | * 0xd. Failure to do so will result in spurious interrupts being | |
1712 | * generated on the port when a cable is not attached. | |
1713 | */ | |
1714 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1715 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1716 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1717 | } | |
1718 | } |