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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
a4fc5ed6 KP |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "drm_crtc_helper.h" | |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
ab2c0672 | 37 | #include "drm_dp_helper.h" |
a4fc5ed6 | 38 | |
ae266c98 | 39 | |
a4fc5ed6 KP |
40 | #define DP_LINK_STATUS_SIZE 6 |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) | |
42 | ||
43 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
44 | ||
ea5b213a CW |
45 | #define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP) |
46 | #define IS_PCH_eDP(i) ((i)->is_pch_edp) | |
32f9d658 | 47 | |
ea5b213a CW |
48 | struct intel_dp { |
49 | struct intel_encoder base; | |
a4fc5ed6 KP |
50 | uint32_t output_reg; |
51 | uint32_t DP; | |
52 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
a4fc5ed6 | 53 | bool has_audio; |
c8110e52 | 54 | int dpms_mode; |
a4fc5ed6 KP |
55 | uint8_t link_bw; |
56 | uint8_t lane_count; | |
57 | uint8_t dpcd[4]; | |
a4fc5ed6 KP |
58 | struct i2c_adapter adapter; |
59 | struct i2c_algo_dp_aux_data algo; | |
f0917379 | 60 | bool is_pch_edp; |
a4fc5ed6 KP |
61 | }; |
62 | ||
ea5b213a CW |
63 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
64 | { | |
65 | return container_of(enc_to_intel_encoder(encoder), struct intel_dp, base); | |
66 | } | |
a4fc5ed6 | 67 | |
ea5b213a CW |
68 | static void intel_dp_link_train(struct intel_dp *intel_dp); |
69 | static void intel_dp_link_down(struct intel_dp *intel_dp); | |
a4fc5ed6 | 70 | |
32f9d658 | 71 | void |
21d40d37 | 72 | intel_edp_link_config (struct intel_encoder *intel_encoder, |
ea5b213a | 73 | int *lane_num, int *link_bw) |
32f9d658 | 74 | { |
ea5b213a | 75 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
32f9d658 | 76 | |
ea5b213a CW |
77 | *lane_num = intel_dp->lane_count; |
78 | if (intel_dp->link_bw == DP_LINK_BW_1_62) | |
32f9d658 | 79 | *link_bw = 162000; |
ea5b213a | 80 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
32f9d658 ZW |
81 | *link_bw = 270000; |
82 | } | |
83 | ||
a4fc5ed6 | 84 | static int |
ea5b213a | 85 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
a4fc5ed6 | 86 | { |
a4fc5ed6 KP |
87 | int max_lane_count = 4; |
88 | ||
ea5b213a CW |
89 | if (intel_dp->dpcd[0] >= 0x11) { |
90 | max_lane_count = intel_dp->dpcd[2] & 0x1f; | |
a4fc5ed6 KP |
91 | switch (max_lane_count) { |
92 | case 1: case 2: case 4: | |
93 | break; | |
94 | default: | |
95 | max_lane_count = 4; | |
96 | } | |
97 | } | |
98 | return max_lane_count; | |
99 | } | |
100 | ||
101 | static int | |
ea5b213a | 102 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 103 | { |
ea5b213a | 104 | int max_link_bw = intel_dp->dpcd[1]; |
a4fc5ed6 KP |
105 | |
106 | switch (max_link_bw) { | |
107 | case DP_LINK_BW_1_62: | |
108 | case DP_LINK_BW_2_7: | |
109 | break; | |
110 | default: | |
111 | max_link_bw = DP_LINK_BW_1_62; | |
112 | break; | |
113 | } | |
114 | return max_link_bw; | |
115 | } | |
116 | ||
117 | static int | |
118 | intel_dp_link_clock(uint8_t link_bw) | |
119 | { | |
120 | if (link_bw == DP_LINK_BW_2_7) | |
121 | return 270000; | |
122 | else | |
123 | return 162000; | |
124 | } | |
125 | ||
126 | /* I think this is a fiction */ | |
127 | static int | |
ea5b213a | 128 | intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) |
a4fc5ed6 | 129 | { |
885a5fb5 ZW |
130 | struct drm_i915_private *dev_priv = dev->dev_private; |
131 | ||
ea5b213a | 132 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) |
885a5fb5 ZW |
133 | return (pixel_clock * dev_priv->edp_bpp) / 8; |
134 | else | |
135 | return pixel_clock * 3; | |
a4fc5ed6 KP |
136 | } |
137 | ||
fe27d53e DA |
138 | static int |
139 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
140 | { | |
141 | return (max_link_clock * max_lanes * 8) / 10; | |
142 | } | |
143 | ||
a4fc5ed6 KP |
144 | static int |
145 | intel_dp_mode_valid(struct drm_connector *connector, | |
146 | struct drm_display_mode *mode) | |
147 | { | |
55f78c43 | 148 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
ea5b213a | 149 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
7de56f43 ZY |
150 | struct drm_device *dev = connector->dev; |
151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a CW |
152 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
153 | int max_lanes = intel_dp_max_lane_count(intel_dp); | |
a4fc5ed6 | 154 | |
ea5b213a | 155 | if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && |
7de56f43 ZY |
156 | dev_priv->panel_fixed_mode) { |
157 | if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) | |
158 | return MODE_PANEL; | |
159 | ||
160 | if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay) | |
161 | return MODE_PANEL; | |
162 | } | |
163 | ||
fe27d53e DA |
164 | /* only refuse the mode on non eDP since we have seen some wierd eDP panels |
165 | which are outside spec tolerances but somehow work by magic */ | |
ea5b213a CW |
166 | if (!IS_eDP(intel_dp) && |
167 | (intel_dp_link_required(connector->dev, intel_dp, mode->clock) | |
fe27d53e | 168 | > intel_dp_max_data_rate(max_link_clock, max_lanes))) |
a4fc5ed6 KP |
169 | return MODE_CLOCK_HIGH; |
170 | ||
171 | if (mode->clock < 10000) | |
172 | return MODE_CLOCK_LOW; | |
173 | ||
174 | return MODE_OK; | |
175 | } | |
176 | ||
177 | static uint32_t | |
178 | pack_aux(uint8_t *src, int src_bytes) | |
179 | { | |
180 | int i; | |
181 | uint32_t v = 0; | |
182 | ||
183 | if (src_bytes > 4) | |
184 | src_bytes = 4; | |
185 | for (i = 0; i < src_bytes; i++) | |
186 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
187 | return v; | |
188 | } | |
189 | ||
190 | static void | |
191 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
192 | { | |
193 | int i; | |
194 | if (dst_bytes > 4) | |
195 | dst_bytes = 4; | |
196 | for (i = 0; i < dst_bytes; i++) | |
197 | dst[i] = src >> ((3-i) * 8); | |
198 | } | |
199 | ||
fb0f8fbf KP |
200 | /* hrawclock is 1/4 the FSB frequency */ |
201 | static int | |
202 | intel_hrawclk(struct drm_device *dev) | |
203 | { | |
204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
205 | uint32_t clkcfg; | |
206 | ||
207 | clkcfg = I915_READ(CLKCFG); | |
208 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
209 | case CLKCFG_FSB_400: | |
210 | return 100; | |
211 | case CLKCFG_FSB_533: | |
212 | return 133; | |
213 | case CLKCFG_FSB_667: | |
214 | return 166; | |
215 | case CLKCFG_FSB_800: | |
216 | return 200; | |
217 | case CLKCFG_FSB_1067: | |
218 | return 266; | |
219 | case CLKCFG_FSB_1333: | |
220 | return 333; | |
221 | /* these two are just a guess; one of them might be right */ | |
222 | case CLKCFG_FSB_1600: | |
223 | case CLKCFG_FSB_1600_ALT: | |
224 | return 400; | |
225 | default: | |
226 | return 133; | |
227 | } | |
228 | } | |
229 | ||
a4fc5ed6 | 230 | static int |
ea5b213a | 231 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
232 | uint8_t *send, int send_bytes, |
233 | uint8_t *recv, int recv_size) | |
234 | { | |
ea5b213a CW |
235 | uint32_t output_reg = intel_dp->output_reg; |
236 | struct drm_device *dev = intel_dp->base.enc.dev; | |
a4fc5ed6 KP |
237 | struct drm_i915_private *dev_priv = dev->dev_private; |
238 | uint32_t ch_ctl = output_reg + 0x10; | |
239 | uint32_t ch_data = ch_ctl + 4; | |
240 | int i; | |
241 | int recv_bytes; | |
242 | uint32_t ctl; | |
243 | uint32_t status; | |
fb0f8fbf | 244 | uint32_t aux_clock_divider; |
e3421a18 | 245 | int try, precharge; |
a4fc5ed6 KP |
246 | |
247 | /* The clock divider is based off the hrawclk, | |
fb0f8fbf KP |
248 | * and would like to run at 2MHz. So, take the |
249 | * hrawclk value and divide by 2 and use that | |
a4fc5ed6 | 250 | */ |
ea5b213a | 251 | if (IS_eDP(intel_dp)) { |
e3421a18 ZW |
252 | if (IS_GEN6(dev)) |
253 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ | |
254 | else | |
255 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
256 | } else if (HAS_PCH_SPLIT(dev)) | |
f2b115e6 | 257 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
5eb08b69 ZW |
258 | else |
259 | aux_clock_divider = intel_hrawclk(dev) / 2; | |
260 | ||
e3421a18 ZW |
261 | if (IS_GEN6(dev)) |
262 | precharge = 3; | |
263 | else | |
264 | precharge = 5; | |
265 | ||
fb0f8fbf KP |
266 | /* Must try at least 3 times according to DP spec */ |
267 | for (try = 0; try < 5; try++) { | |
268 | /* Load the send data into the aux channel data registers */ | |
269 | for (i = 0; i < send_bytes; i += 4) { | |
a419aef8 | 270 | uint32_t d = pack_aux(send + i, send_bytes - i); |
fb0f8fbf KP |
271 | |
272 | I915_WRITE(ch_data + i, d); | |
273 | } | |
274 | ||
275 | ctl = (DP_AUX_CH_CTL_SEND_BUSY | | |
276 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
277 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
e3421a18 | 278 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
fb0f8fbf KP |
279 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | |
280 | DP_AUX_CH_CTL_DONE | | |
281 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
282 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
283 | ||
284 | /* Send the command and wait for it to complete */ | |
285 | I915_WRITE(ch_ctl, ctl); | |
286 | (void) I915_READ(ch_ctl); | |
287 | for (;;) { | |
288 | udelay(100); | |
289 | status = I915_READ(ch_ctl); | |
290 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
291 | break; | |
292 | } | |
293 | ||
294 | /* Clear done status and any errors */ | |
eebc863e | 295 | I915_WRITE(ch_ctl, (status | |
fb0f8fbf KP |
296 | DP_AUX_CH_CTL_DONE | |
297 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
298 | DP_AUX_CH_CTL_RECEIVE_ERROR)); | |
299 | (void) I915_READ(ch_ctl); | |
300 | if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0) | |
a4fc5ed6 KP |
301 | break; |
302 | } | |
303 | ||
a4fc5ed6 | 304 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 305 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
a5b3da54 | 306 | return -EBUSY; |
a4fc5ed6 KP |
307 | } |
308 | ||
309 | /* Check for timeout or receive error. | |
310 | * Timeouts occur when the sink is not connected | |
311 | */ | |
a5b3da54 | 312 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 313 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
a5b3da54 KP |
314 | return -EIO; |
315 | } | |
1ae8c0a5 KP |
316 | |
317 | /* Timeouts occur when the device isn't connected, so they're | |
318 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 319 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 320 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
a5b3da54 | 321 | return -ETIMEDOUT; |
a4fc5ed6 KP |
322 | } |
323 | ||
324 | /* Unload any bytes sent back from the other side */ | |
325 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
326 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
327 | ||
328 | if (recv_bytes > recv_size) | |
329 | recv_bytes = recv_size; | |
330 | ||
331 | for (i = 0; i < recv_bytes; i += 4) { | |
332 | uint32_t d = I915_READ(ch_data + i); | |
333 | ||
334 | unpack_aux(d, recv + i, recv_bytes - i); | |
335 | } | |
336 | ||
337 | return recv_bytes; | |
338 | } | |
339 | ||
340 | /* Write data to the aux channel in native mode */ | |
341 | static int | |
ea5b213a | 342 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
343 | uint16_t address, uint8_t *send, int send_bytes) |
344 | { | |
345 | int ret; | |
346 | uint8_t msg[20]; | |
347 | int msg_bytes; | |
348 | uint8_t ack; | |
349 | ||
350 | if (send_bytes > 16) | |
351 | return -1; | |
352 | msg[0] = AUX_NATIVE_WRITE << 4; | |
353 | msg[1] = address >> 8; | |
eebc863e | 354 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
355 | msg[3] = send_bytes - 1; |
356 | memcpy(&msg[4], send, send_bytes); | |
357 | msg_bytes = send_bytes + 4; | |
358 | for (;;) { | |
ea5b213a | 359 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
360 | if (ret < 0) |
361 | return ret; | |
362 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
363 | break; | |
364 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
365 | udelay(100); | |
366 | else | |
a5b3da54 | 367 | return -EIO; |
a4fc5ed6 KP |
368 | } |
369 | return send_bytes; | |
370 | } | |
371 | ||
372 | /* Write a single byte to the aux channel in native mode */ | |
373 | static int | |
ea5b213a | 374 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
375 | uint16_t address, uint8_t byte) |
376 | { | |
ea5b213a | 377 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
378 | } |
379 | ||
380 | /* read bytes from a native aux channel */ | |
381 | static int | |
ea5b213a | 382 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
383 | uint16_t address, uint8_t *recv, int recv_bytes) |
384 | { | |
385 | uint8_t msg[4]; | |
386 | int msg_bytes; | |
387 | uint8_t reply[20]; | |
388 | int reply_bytes; | |
389 | uint8_t ack; | |
390 | int ret; | |
391 | ||
392 | msg[0] = AUX_NATIVE_READ << 4; | |
393 | msg[1] = address >> 8; | |
394 | msg[2] = address & 0xff; | |
395 | msg[3] = recv_bytes - 1; | |
396 | ||
397 | msg_bytes = 4; | |
398 | reply_bytes = recv_bytes + 1; | |
399 | ||
400 | for (;;) { | |
ea5b213a | 401 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 402 | reply, reply_bytes); |
a5b3da54 KP |
403 | if (ret == 0) |
404 | return -EPROTO; | |
405 | if (ret < 0) | |
a4fc5ed6 KP |
406 | return ret; |
407 | ack = reply[0]; | |
408 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
409 | memcpy(recv, reply + 1, ret - 1); | |
410 | return ret - 1; | |
411 | } | |
412 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
413 | udelay(100); | |
414 | else | |
a5b3da54 | 415 | return -EIO; |
a4fc5ed6 KP |
416 | } |
417 | } | |
418 | ||
419 | static int | |
ab2c0672 DA |
420 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
421 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 422 | { |
ab2c0672 | 423 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
424 | struct intel_dp *intel_dp = container_of(adapter, |
425 | struct intel_dp, | |
426 | adapter); | |
ab2c0672 DA |
427 | uint16_t address = algo_data->address; |
428 | uint8_t msg[5]; | |
429 | uint8_t reply[2]; | |
430 | int msg_bytes; | |
431 | int reply_bytes; | |
432 | int ret; | |
433 | ||
434 | /* Set up the command byte */ | |
435 | if (mode & MODE_I2C_READ) | |
436 | msg[0] = AUX_I2C_READ << 4; | |
437 | else | |
438 | msg[0] = AUX_I2C_WRITE << 4; | |
439 | ||
440 | if (!(mode & MODE_I2C_STOP)) | |
441 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 442 | |
ab2c0672 DA |
443 | msg[1] = address >> 8; |
444 | msg[2] = address; | |
445 | ||
446 | switch (mode) { | |
447 | case MODE_I2C_WRITE: | |
448 | msg[3] = 0; | |
449 | msg[4] = write_byte; | |
450 | msg_bytes = 5; | |
451 | reply_bytes = 1; | |
452 | break; | |
453 | case MODE_I2C_READ: | |
454 | msg[3] = 0; | |
455 | msg_bytes = 4; | |
456 | reply_bytes = 2; | |
457 | break; | |
458 | default: | |
459 | msg_bytes = 3; | |
460 | reply_bytes = 1; | |
461 | break; | |
462 | } | |
463 | ||
464 | for (;;) { | |
ea5b213a | 465 | ret = intel_dp_aux_ch(intel_dp, |
ab2c0672 DA |
466 | msg, msg_bytes, |
467 | reply, reply_bytes); | |
468 | if (ret < 0) { | |
3ff99164 | 469 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
470 | return ret; |
471 | } | |
472 | switch (reply[0] & AUX_I2C_REPLY_MASK) { | |
473 | case AUX_I2C_REPLY_ACK: | |
474 | if (mode == MODE_I2C_READ) { | |
475 | *read_byte = reply[1]; | |
476 | } | |
477 | return reply_bytes - 1; | |
478 | case AUX_I2C_REPLY_NACK: | |
3ff99164 | 479 | DRM_DEBUG_KMS("aux_ch nack\n"); |
ab2c0672 DA |
480 | return -EREMOTEIO; |
481 | case AUX_I2C_REPLY_DEFER: | |
3ff99164 | 482 | DRM_DEBUG_KMS("aux_ch defer\n"); |
ab2c0672 DA |
483 | udelay(100); |
484 | break; | |
485 | default: | |
486 | DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]); | |
487 | return -EREMOTEIO; | |
488 | } | |
489 | } | |
a4fc5ed6 KP |
490 | } |
491 | ||
492 | static int | |
ea5b213a | 493 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 494 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 495 | { |
d54e9d28 | 496 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
497 | intel_dp->algo.running = false; |
498 | intel_dp->algo.address = 0; | |
499 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
500 | ||
501 | memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); | |
502 | intel_dp->adapter.owner = THIS_MODULE; | |
503 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
504 | strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); | |
505 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; | |
506 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
507 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
508 | ||
509 | return i2c_dp_aux_add_bus(&intel_dp->adapter); | |
a4fc5ed6 KP |
510 | } |
511 | ||
512 | static bool | |
513 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
514 | struct drm_display_mode *adjusted_mode) | |
515 | { | |
0d3a1bee ZY |
516 | struct drm_device *dev = encoder->dev; |
517 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 518 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4fc5ed6 | 519 | int lane_count, clock; |
ea5b213a CW |
520 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
521 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; | |
a4fc5ed6 KP |
522 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
523 | ||
ea5b213a | 524 | if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && |
0d3a1bee | 525 | dev_priv->panel_fixed_mode) { |
1d8e1c75 CW |
526 | intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); |
527 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, | |
528 | mode, adjusted_mode); | |
0d3a1bee ZY |
529 | /* |
530 | * the mode->clock is used to calculate the Data&Link M/N | |
531 | * of the pipe. For the eDP the fixed clock should be used. | |
532 | */ | |
533 | mode->clock = dev_priv->panel_fixed_mode->clock; | |
534 | } | |
535 | ||
a4fc5ed6 KP |
536 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
537 | for (clock = 0; clock <= max_clock; clock++) { | |
fe27d53e | 538 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
a4fc5ed6 | 539 | |
ea5b213a | 540 | if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) |
885a5fb5 | 541 | <= link_avail) { |
ea5b213a CW |
542 | intel_dp->link_bw = bws[clock]; |
543 | intel_dp->lane_count = lane_count; | |
544 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
28c97730 ZY |
545 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
546 | "count %d clock %d\n", | |
ea5b213a | 547 | intel_dp->link_bw, intel_dp->lane_count, |
a4fc5ed6 KP |
548 | adjusted_mode->clock); |
549 | return true; | |
550 | } | |
551 | } | |
552 | } | |
fe27d53e | 553 | |
ea5b213a | 554 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { |
fe27d53e | 555 | /* okay we failed just pick the highest */ |
ea5b213a CW |
556 | intel_dp->lane_count = max_lane_count; |
557 | intel_dp->link_bw = bws[max_clock]; | |
558 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
fe27d53e DA |
559 | DRM_DEBUG_KMS("Force picking display port link bw %02x lane " |
560 | "count %d clock %d\n", | |
ea5b213a | 561 | intel_dp->link_bw, intel_dp->lane_count, |
fe27d53e | 562 | adjusted_mode->clock); |
1d8e1c75 | 563 | |
fe27d53e DA |
564 | return true; |
565 | } | |
1d8e1c75 | 566 | |
a4fc5ed6 KP |
567 | return false; |
568 | } | |
569 | ||
570 | struct intel_dp_m_n { | |
571 | uint32_t tu; | |
572 | uint32_t gmch_m; | |
573 | uint32_t gmch_n; | |
574 | uint32_t link_m; | |
575 | uint32_t link_n; | |
576 | }; | |
577 | ||
578 | static void | |
579 | intel_reduce_ratio(uint32_t *num, uint32_t *den) | |
580 | { | |
581 | while (*num > 0xffffff || *den > 0xffffff) { | |
582 | *num >>= 1; | |
583 | *den >>= 1; | |
584 | } | |
585 | } | |
586 | ||
587 | static void | |
36e83a18 | 588 | intel_dp_compute_m_n(int bpp, |
a4fc5ed6 KP |
589 | int nlanes, |
590 | int pixel_clock, | |
591 | int link_clock, | |
592 | struct intel_dp_m_n *m_n) | |
593 | { | |
594 | m_n->tu = 64; | |
36e83a18 | 595 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
a4fc5ed6 KP |
596 | m_n->gmch_n = link_clock * nlanes; |
597 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
598 | m_n->link_m = pixel_clock; | |
599 | m_n->link_n = link_clock; | |
600 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
601 | } | |
602 | ||
36e83a18 ZY |
603 | bool intel_pch_has_edp(struct drm_crtc *crtc) |
604 | { | |
605 | struct drm_device *dev = crtc->dev; | |
606 | struct drm_mode_config *mode_config = &dev->mode_config; | |
607 | struct drm_encoder *encoder; | |
608 | ||
609 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a | 610 | struct intel_dp *intel_dp; |
36e83a18 | 611 | |
ea5b213a | 612 | if (encoder->crtc != crtc) |
36e83a18 ZY |
613 | continue; |
614 | ||
ea5b213a CW |
615 | intel_dp = enc_to_intel_dp(encoder); |
616 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) | |
617 | return intel_dp->is_pch_edp; | |
36e83a18 ZY |
618 | } |
619 | return false; | |
620 | } | |
621 | ||
a4fc5ed6 KP |
622 | void |
623 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
624 | struct drm_display_mode *adjusted_mode) | |
625 | { | |
626 | struct drm_device *dev = crtc->dev; | |
627 | struct drm_mode_config *mode_config = &dev->mode_config; | |
55f78c43 | 628 | struct drm_encoder *encoder; |
a4fc5ed6 KP |
629 | struct drm_i915_private *dev_priv = dev->dev_private; |
630 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
36e83a18 | 631 | int lane_count = 4, bpp = 24; |
a4fc5ed6 KP |
632 | struct intel_dp_m_n m_n; |
633 | ||
634 | /* | |
21d40d37 | 635 | * Find the lane count in the intel_encoder private |
a4fc5ed6 | 636 | */ |
55f78c43 | 637 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
ea5b213a | 638 | struct intel_dp *intel_dp; |
a4fc5ed6 | 639 | |
d8201ab6 | 640 | if (encoder->crtc != crtc) |
a4fc5ed6 KP |
641 | continue; |
642 | ||
ea5b213a CW |
643 | intel_dp = enc_to_intel_dp(encoder); |
644 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
645 | lane_count = intel_dp->lane_count; | |
646 | if (IS_PCH_eDP(intel_dp)) | |
36e83a18 | 647 | bpp = dev_priv->edp_bpp; |
a4fc5ed6 KP |
648 | break; |
649 | } | |
650 | } | |
651 | ||
652 | /* | |
653 | * Compute the GMCH and Link ratios. The '3' here is | |
654 | * the number of bytes_per_pixel post-LUT, which we always | |
655 | * set up for 8-bits of R/G/B, or 3 bytes total. | |
656 | */ | |
36e83a18 | 657 | intel_dp_compute_m_n(bpp, lane_count, |
a4fc5ed6 KP |
658 | mode->clock, adjusted_mode->clock, &m_n); |
659 | ||
c619eed4 | 660 | if (HAS_PCH_SPLIT(dev)) { |
5eb08b69 ZW |
661 | if (intel_crtc->pipe == 0) { |
662 | I915_WRITE(TRANSA_DATA_M1, | |
663 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
664 | m_n.gmch_m); | |
665 | I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n); | |
666 | I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m); | |
667 | I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n); | |
668 | } else { | |
669 | I915_WRITE(TRANSB_DATA_M1, | |
670 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
671 | m_n.gmch_m); | |
672 | I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n); | |
673 | I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m); | |
674 | I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n); | |
675 | } | |
a4fc5ed6 | 676 | } else { |
5eb08b69 ZW |
677 | if (intel_crtc->pipe == 0) { |
678 | I915_WRITE(PIPEA_GMCH_DATA_M, | |
679 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
680 | m_n.gmch_m); | |
681 | I915_WRITE(PIPEA_GMCH_DATA_N, | |
682 | m_n.gmch_n); | |
683 | I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m); | |
684 | I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n); | |
685 | } else { | |
686 | I915_WRITE(PIPEB_GMCH_DATA_M, | |
687 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
688 | m_n.gmch_m); | |
689 | I915_WRITE(PIPEB_GMCH_DATA_N, | |
690 | m_n.gmch_n); | |
691 | I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m); | |
692 | I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n); | |
693 | } | |
a4fc5ed6 KP |
694 | } |
695 | } | |
696 | ||
697 | static void | |
698 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
699 | struct drm_display_mode *adjusted_mode) | |
700 | { | |
e3421a18 | 701 | struct drm_device *dev = encoder->dev; |
ea5b213a CW |
702 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
703 | struct drm_crtc *crtc = intel_dp->base.enc.crtc; | |
a4fc5ed6 KP |
704 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
705 | ||
ea5b213a | 706 | intel_dp->DP = (DP_VOLTAGE_0_4 | |
9c9e7927 AJ |
707 | DP_PRE_EMPHASIS_0); |
708 | ||
709 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
ea5b213a | 710 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
9c9e7927 | 711 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
ea5b213a | 712 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
a4fc5ed6 | 713 | |
ea5b213a CW |
714 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
715 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
e3421a18 | 716 | else |
ea5b213a | 717 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
a4fc5ed6 | 718 | |
ea5b213a | 719 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 720 | case 1: |
ea5b213a | 721 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
722 | break; |
723 | case 2: | |
ea5b213a | 724 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
725 | break; |
726 | case 4: | |
ea5b213a | 727 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
728 | break; |
729 | } | |
ea5b213a CW |
730 | if (intel_dp->has_audio) |
731 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; | |
a4fc5ed6 | 732 | |
ea5b213a CW |
733 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
734 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
735 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
a4fc5ed6 KP |
736 | |
737 | /* | |
9962c925 | 738 | * Check for DPCD version > 1.1 and enhanced framing support |
a4fc5ed6 | 739 | */ |
ea5b213a CW |
740 | if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) { |
741 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; | |
742 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
a4fc5ed6 KP |
743 | } |
744 | ||
e3421a18 ZW |
745 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ |
746 | if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) | |
ea5b213a | 747 | intel_dp->DP |= DP_PIPEB_SELECT; |
32f9d658 | 748 | |
ea5b213a | 749 | if (IS_eDP(intel_dp)) { |
32f9d658 | 750 | /* don't miss out required setting for eDP */ |
ea5b213a | 751 | intel_dp->DP |= DP_PLL_ENABLE; |
32f9d658 | 752 | if (adjusted_mode->clock < 200000) |
ea5b213a | 753 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
32f9d658 | 754 | else |
ea5b213a | 755 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
32f9d658 | 756 | } |
a4fc5ed6 KP |
757 | } |
758 | ||
9934c132 JB |
759 | static void ironlake_edp_panel_on (struct drm_device *dev) |
760 | { | |
761 | struct drm_i915_private *dev_priv = dev->dev_private; | |
913d8d11 | 762 | u32 pp; |
9934c132 | 763 | |
913d8d11 | 764 | if (I915_READ(PCH_PP_STATUS) & PP_ON) |
9934c132 JB |
765 | return; |
766 | ||
767 | pp = I915_READ(PCH_PP_CONTROL); | |
37c6c9b0 JB |
768 | |
769 | /* ILK workaround: disable reset around power sequence */ | |
770 | pp &= ~PANEL_POWER_RESET; | |
771 | I915_WRITE(PCH_PP_CONTROL, pp); | |
772 | POSTING_READ(PCH_PP_CONTROL); | |
773 | ||
9934c132 JB |
774 | pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; |
775 | I915_WRITE(PCH_PP_CONTROL, pp); | |
9934c132 | 776 | |
913d8d11 CW |
777 | if (wait_for(I915_READ(PCH_PP_STATUS) & PP_ON, 5000, 10)) |
778 | DRM_ERROR("panel on wait timed out: 0x%08x\n", | |
779 | I915_READ(PCH_PP_STATUS)); | |
9934c132 JB |
780 | |
781 | pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD); | |
37c6c9b0 | 782 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 783 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 784 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 JB |
785 | } |
786 | ||
787 | static void ironlake_edp_panel_off (struct drm_device *dev) | |
788 | { | |
789 | struct drm_i915_private *dev_priv = dev->dev_private; | |
913d8d11 | 790 | u32 pp; |
9934c132 JB |
791 | |
792 | pp = I915_READ(PCH_PP_CONTROL); | |
37c6c9b0 JB |
793 | |
794 | /* ILK workaround: disable reset around power sequence */ | |
795 | pp &= ~PANEL_POWER_RESET; | |
796 | I915_WRITE(PCH_PP_CONTROL, pp); | |
797 | POSTING_READ(PCH_PP_CONTROL); | |
798 | ||
9934c132 JB |
799 | pp &= ~POWER_TARGET_ON; |
800 | I915_WRITE(PCH_PP_CONTROL, pp); | |
9934c132 | 801 | |
913d8d11 CW |
802 | if (wait_for((I915_READ(PCH_PP_STATUS) & PP_ON) == 0, 5000, 10)) |
803 | DRM_ERROR("panel off wait timed out: 0x%08x\n", | |
804 | I915_READ(PCH_PP_STATUS)); | |
9934c132 JB |
805 | |
806 | /* Make sure VDD is enabled so DP AUX will work */ | |
37c6c9b0 | 807 | pp |= EDP_FORCE_VDD | PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 808 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 809 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 JB |
810 | } |
811 | ||
f2b115e6 | 812 | static void ironlake_edp_backlight_on (struct drm_device *dev) |
32f9d658 ZW |
813 | { |
814 | struct drm_i915_private *dev_priv = dev->dev_private; | |
815 | u32 pp; | |
816 | ||
28c97730 | 817 | DRM_DEBUG_KMS("\n"); |
32f9d658 ZW |
818 | pp = I915_READ(PCH_PP_CONTROL); |
819 | pp |= EDP_BLC_ENABLE; | |
820 | I915_WRITE(PCH_PP_CONTROL, pp); | |
821 | } | |
822 | ||
f2b115e6 | 823 | static void ironlake_edp_backlight_off (struct drm_device *dev) |
32f9d658 ZW |
824 | { |
825 | struct drm_i915_private *dev_priv = dev->dev_private; | |
826 | u32 pp; | |
827 | ||
28c97730 | 828 | DRM_DEBUG_KMS("\n"); |
32f9d658 ZW |
829 | pp = I915_READ(PCH_PP_CONTROL); |
830 | pp &= ~EDP_BLC_ENABLE; | |
831 | I915_WRITE(PCH_PP_CONTROL, pp); | |
832 | } | |
a4fc5ed6 | 833 | |
d240f20f JB |
834 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
835 | { | |
836 | struct drm_device *dev = encoder->dev; | |
837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
838 | u32 dpa_ctl; | |
839 | ||
840 | DRM_DEBUG_KMS("\n"); | |
841 | dpa_ctl = I915_READ(DP_A); | |
842 | dpa_ctl &= ~DP_PLL_ENABLE; | |
843 | I915_WRITE(DP_A, dpa_ctl); | |
844 | } | |
845 | ||
846 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) | |
847 | { | |
848 | struct drm_device *dev = encoder->dev; | |
849 | struct drm_i915_private *dev_priv = dev->dev_private; | |
850 | u32 dpa_ctl; | |
851 | ||
852 | dpa_ctl = I915_READ(DP_A); | |
853 | dpa_ctl |= DP_PLL_ENABLE; | |
854 | I915_WRITE(DP_A, dpa_ctl); | |
855 | udelay(200); | |
856 | } | |
857 | ||
858 | static void intel_dp_prepare(struct drm_encoder *encoder) | |
859 | { | |
860 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
861 | struct drm_device *dev = encoder->dev; | |
862 | struct drm_i915_private *dev_priv = dev->dev_private; | |
863 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); | |
864 | ||
865 | if (IS_eDP(intel_dp)) { | |
866 | ironlake_edp_backlight_off(dev); | |
867 | ironlake_edp_panel_on(dev); | |
868 | ironlake_edp_pll_on(encoder); | |
869 | } | |
870 | if (dp_reg & DP_PORT_EN) | |
871 | intel_dp_link_down(intel_dp); | |
872 | } | |
873 | ||
874 | static void intel_dp_commit(struct drm_encoder *encoder) | |
875 | { | |
876 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
877 | struct drm_device *dev = encoder->dev; | |
878 | struct drm_i915_private *dev_priv = dev->dev_private; | |
879 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); | |
880 | ||
881 | if (!(dp_reg & DP_PORT_EN)) { | |
882 | intel_dp_link_train(intel_dp); | |
883 | } | |
884 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) | |
885 | ironlake_edp_backlight_on(dev); | |
886 | } | |
887 | ||
a4fc5ed6 KP |
888 | static void |
889 | intel_dp_dpms(struct drm_encoder *encoder, int mode) | |
890 | { | |
ea5b213a | 891 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
55f78c43 | 892 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 | 893 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 894 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
a4fc5ed6 KP |
895 | |
896 | if (mode != DRM_MODE_DPMS_ON) { | |
7643a7fa JB |
897 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { |
898 | ironlake_edp_backlight_off(dev); | |
899 | ironlake_edp_panel_off(dev); | |
32f9d658 | 900 | } |
7643a7fa JB |
901 | if (dp_reg & DP_PORT_EN) |
902 | intel_dp_link_down(intel_dp); | |
d240f20f JB |
903 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) |
904 | ironlake_edp_pll_off(encoder); | |
a4fc5ed6 | 905 | } else { |
32f9d658 | 906 | if (!(dp_reg & DP_PORT_EN)) { |
7643a7fa | 907 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) |
9934c132 | 908 | ironlake_edp_panel_on(dev); |
7643a7fa JB |
909 | intel_dp_link_train(intel_dp); |
910 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) | |
f2b115e6 | 911 | ironlake_edp_backlight_on(dev); |
32f9d658 | 912 | } |
a4fc5ed6 | 913 | } |
ea5b213a | 914 | intel_dp->dpms_mode = mode; |
a4fc5ed6 KP |
915 | } |
916 | ||
917 | /* | |
918 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
919 | * link status information | |
920 | */ | |
921 | static bool | |
ea5b213a | 922 | intel_dp_get_link_status(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
923 | uint8_t link_status[DP_LINK_STATUS_SIZE]) |
924 | { | |
925 | int ret; | |
926 | ||
ea5b213a | 927 | ret = intel_dp_aux_native_read(intel_dp, |
a4fc5ed6 KP |
928 | DP_LANE0_1_STATUS, |
929 | link_status, DP_LINK_STATUS_SIZE); | |
930 | if (ret != DP_LINK_STATUS_SIZE) | |
931 | return false; | |
932 | return true; | |
933 | } | |
934 | ||
935 | static uint8_t | |
936 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
937 | int r) | |
938 | { | |
939 | return link_status[r - DP_LANE0_1_STATUS]; | |
940 | } | |
941 | ||
a4fc5ed6 KP |
942 | static uint8_t |
943 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
944 | int lane) | |
945 | { | |
946 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
947 | int s = ((lane & 1) ? | |
948 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
949 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
950 | uint8_t l = intel_dp_link_status(link_status, i); | |
951 | ||
952 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
953 | } | |
954 | ||
955 | static uint8_t | |
956 | intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
957 | int lane) | |
958 | { | |
959 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
960 | int s = ((lane & 1) ? | |
961 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
962 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
963 | uint8_t l = intel_dp_link_status(link_status, i); | |
964 | ||
965 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
966 | } | |
967 | ||
968 | ||
969 | #if 0 | |
970 | static char *voltage_names[] = { | |
971 | "0.4V", "0.6V", "0.8V", "1.2V" | |
972 | }; | |
973 | static char *pre_emph_names[] = { | |
974 | "0dB", "3.5dB", "6dB", "9.5dB" | |
975 | }; | |
976 | static char *link_train_names[] = { | |
977 | "pattern 1", "pattern 2", "idle", "off" | |
978 | }; | |
979 | #endif | |
980 | ||
981 | /* | |
982 | * These are source-specific values; current Intel hardware supports | |
983 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
984 | */ | |
985 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 | |
986 | ||
987 | static uint8_t | |
988 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) | |
989 | { | |
990 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
991 | case DP_TRAIN_VOLTAGE_SWING_400: | |
992 | return DP_TRAIN_PRE_EMPHASIS_6; | |
993 | case DP_TRAIN_VOLTAGE_SWING_600: | |
994 | return DP_TRAIN_PRE_EMPHASIS_6; | |
995 | case DP_TRAIN_VOLTAGE_SWING_800: | |
996 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
997 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
998 | default: | |
999 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1000 | } | |
1001 | } | |
1002 | ||
1003 | static void | |
ea5b213a | 1004 | intel_get_adjust_train(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
1005 | uint8_t link_status[DP_LINK_STATUS_SIZE], |
1006 | int lane_count, | |
1007 | uint8_t train_set[4]) | |
1008 | { | |
1009 | uint8_t v = 0; | |
1010 | uint8_t p = 0; | |
1011 | int lane; | |
1012 | ||
1013 | for (lane = 0; lane < lane_count; lane++) { | |
1014 | uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane); | |
1015 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane); | |
1016 | ||
1017 | if (this_v > v) | |
1018 | v = this_v; | |
1019 | if (this_p > p) | |
1020 | p = this_p; | |
1021 | } | |
1022 | ||
1023 | if (v >= I830_DP_VOLTAGE_MAX) | |
1024 | v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; | |
1025 | ||
1026 | if (p >= intel_dp_pre_emphasis_max(v)) | |
1027 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
1028 | ||
1029 | for (lane = 0; lane < 4; lane++) | |
1030 | train_set[lane] = v | p; | |
1031 | } | |
1032 | ||
1033 | static uint32_t | |
1034 | intel_dp_signal_levels(uint8_t train_set, int lane_count) | |
1035 | { | |
1036 | uint32_t signal_levels = 0; | |
1037 | ||
1038 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1039 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1040 | default: | |
1041 | signal_levels |= DP_VOLTAGE_0_4; | |
1042 | break; | |
1043 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1044 | signal_levels |= DP_VOLTAGE_0_6; | |
1045 | break; | |
1046 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1047 | signal_levels |= DP_VOLTAGE_0_8; | |
1048 | break; | |
1049 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1050 | signal_levels |= DP_VOLTAGE_1_2; | |
1051 | break; | |
1052 | } | |
1053 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
1054 | case DP_TRAIN_PRE_EMPHASIS_0: | |
1055 | default: | |
1056 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1057 | break; | |
1058 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1059 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1060 | break; | |
1061 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1062 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1063 | break; | |
1064 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1065 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1066 | break; | |
1067 | } | |
1068 | return signal_levels; | |
1069 | } | |
1070 | ||
e3421a18 ZW |
1071 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1072 | static uint32_t | |
1073 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1074 | { | |
1075 | switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) { | |
1076 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
1077 | return EDP_LINK_TRAIN_400MV_0DB_SNB_B; | |
1078 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
1079 | return EDP_LINK_TRAIN_400MV_6DB_SNB_B; | |
1080 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1081 | return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B; | |
1082 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | |
1083 | return EDP_LINK_TRAIN_800MV_0DB_SNB_B; | |
1084 | default: | |
1085 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n"); | |
1086 | return EDP_LINK_TRAIN_400MV_0DB_SNB_B; | |
1087 | } | |
1088 | } | |
1089 | ||
a4fc5ed6 KP |
1090 | static uint8_t |
1091 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1092 | int lane) | |
1093 | { | |
1094 | int i = DP_LANE0_1_STATUS + (lane >> 1); | |
1095 | int s = (lane & 1) * 4; | |
1096 | uint8_t l = intel_dp_link_status(link_status, i); | |
1097 | ||
1098 | return (l >> s) & 0xf; | |
1099 | } | |
1100 | ||
1101 | /* Check for clock recovery is done on all channels */ | |
1102 | static bool | |
1103 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1104 | { | |
1105 | int lane; | |
1106 | uint8_t lane_status; | |
1107 | ||
1108 | for (lane = 0; lane < lane_count; lane++) { | |
1109 | lane_status = intel_get_lane_status(link_status, lane); | |
1110 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
1111 | return false; | |
1112 | } | |
1113 | return true; | |
1114 | } | |
1115 | ||
1116 | /* Check to see if channel eq is done on all channels */ | |
1117 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ | |
1118 | DP_LANE_CHANNEL_EQ_DONE|\ | |
1119 | DP_LANE_SYMBOL_LOCKED) | |
1120 | static bool | |
1121 | intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1122 | { | |
1123 | uint8_t lane_align; | |
1124 | uint8_t lane_status; | |
1125 | int lane; | |
1126 | ||
1127 | lane_align = intel_dp_link_status(link_status, | |
1128 | DP_LANE_ALIGN_STATUS_UPDATED); | |
1129 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
1130 | return false; | |
1131 | for (lane = 0; lane < lane_count; lane++) { | |
1132 | lane_status = intel_get_lane_status(link_status, lane); | |
1133 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) | |
1134 | return false; | |
1135 | } | |
1136 | return true; | |
1137 | } | |
1138 | ||
1139 | static bool | |
ea5b213a | 1140 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
1141 | uint32_t dp_reg_value, |
1142 | uint8_t dp_train_pat, | |
1143 | uint8_t train_set[4], | |
1144 | bool first) | |
1145 | { | |
ea5b213a | 1146 | struct drm_device *dev = intel_dp->base.enc.dev; |
a4fc5ed6 | 1147 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d0498a2 | 1148 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.enc.crtc); |
a4fc5ed6 KP |
1149 | int ret; |
1150 | ||
ea5b213a CW |
1151 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1152 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1153 | if (first) |
9d0498a2 | 1154 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
a4fc5ed6 | 1155 | |
ea5b213a | 1156 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1157 | DP_TRAINING_PATTERN_SET, |
1158 | dp_train_pat); | |
1159 | ||
ea5b213a | 1160 | ret = intel_dp_aux_native_write(intel_dp, |
a4fc5ed6 KP |
1161 | DP_TRAINING_LANE0_SET, train_set, 4); |
1162 | if (ret != 4) | |
1163 | return false; | |
1164 | ||
1165 | return true; | |
1166 | } | |
1167 | ||
1168 | static void | |
ea5b213a | 1169 | intel_dp_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1170 | { |
ea5b213a | 1171 | struct drm_device *dev = intel_dp->base.enc.dev; |
a4fc5ed6 | 1172 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1173 | uint8_t train_set[4]; |
1174 | uint8_t link_status[DP_LINK_STATUS_SIZE]; | |
1175 | int i; | |
1176 | uint8_t voltage; | |
1177 | bool clock_recovery = false; | |
1178 | bool channel_eq = false; | |
1179 | bool first = true; | |
1180 | int tries; | |
e3421a18 | 1181 | u32 reg; |
ea5b213a | 1182 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 KP |
1183 | |
1184 | /* Write the link configuration data */ | |
ea5b213a CW |
1185 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, |
1186 | intel_dp->link_configuration, | |
1187 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
1188 | |
1189 | DP |= DP_PORT_EN; | |
ea5b213a | 1190 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
e3421a18 ZW |
1191 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1192 | else | |
1193 | DP &= ~DP_LINK_TRAIN_MASK; | |
a4fc5ed6 KP |
1194 | memset(train_set, 0, 4); |
1195 | voltage = 0xff; | |
1196 | tries = 0; | |
1197 | clock_recovery = false; | |
1198 | for (;;) { | |
1199 | /* Use train_set[0] to set the voltage and pre emphasis values */ | |
e3421a18 | 1200 | uint32_t signal_levels; |
ea5b213a | 1201 | if (IS_GEN6(dev) && IS_eDP(intel_dp)) { |
e3421a18 ZW |
1202 | signal_levels = intel_gen6_edp_signal_levels(train_set[0]); |
1203 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; | |
1204 | } else { | |
ea5b213a | 1205 | signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1206 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1207 | } | |
a4fc5ed6 | 1208 | |
ea5b213a | 1209 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
e3421a18 ZW |
1210 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
1211 | else | |
1212 | reg = DP | DP_LINK_TRAIN_PAT_1; | |
1213 | ||
ea5b213a | 1214 | if (!intel_dp_set_link_train(intel_dp, reg, |
a4fc5ed6 KP |
1215 | DP_TRAINING_PATTERN_1, train_set, first)) |
1216 | break; | |
1217 | first = false; | |
1218 | /* Set training pattern 1 */ | |
1219 | ||
1220 | udelay(100); | |
ea5b213a | 1221 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
a4fc5ed6 KP |
1222 | break; |
1223 | ||
ea5b213a | 1224 | if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
a4fc5ed6 KP |
1225 | clock_recovery = true; |
1226 | break; | |
1227 | } | |
1228 | ||
1229 | /* Check to see if we've tried the max voltage */ | |
ea5b213a | 1230 | for (i = 0; i < intel_dp->lane_count; i++) |
a4fc5ed6 KP |
1231 | if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
1232 | break; | |
ea5b213a | 1233 | if (i == intel_dp->lane_count) |
a4fc5ed6 KP |
1234 | break; |
1235 | ||
1236 | /* Check to see if we've tried the same voltage 5 times */ | |
1237 | if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { | |
1238 | ++tries; | |
1239 | if (tries == 5) | |
1240 | break; | |
1241 | } else | |
1242 | tries = 0; | |
1243 | voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
1244 | ||
1245 | /* Compute new train_set as requested by target */ | |
ea5b213a | 1246 | intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set); |
a4fc5ed6 KP |
1247 | } |
1248 | ||
1249 | /* channel equalization */ | |
1250 | tries = 0; | |
1251 | channel_eq = false; | |
1252 | for (;;) { | |
1253 | /* Use train_set[0] to set the voltage and pre emphasis values */ | |
e3421a18 ZW |
1254 | uint32_t signal_levels; |
1255 | ||
ea5b213a | 1256 | if (IS_GEN6(dev) && IS_eDP(intel_dp)) { |
e3421a18 ZW |
1257 | signal_levels = intel_gen6_edp_signal_levels(train_set[0]); |
1258 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; | |
1259 | } else { | |
ea5b213a | 1260 | signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1261 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1262 | } | |
1263 | ||
ea5b213a | 1264 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
e3421a18 ZW |
1265 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
1266 | else | |
1267 | reg = DP | DP_LINK_TRAIN_PAT_2; | |
a4fc5ed6 KP |
1268 | |
1269 | /* channel eq pattern */ | |
ea5b213a | 1270 | if (!intel_dp_set_link_train(intel_dp, reg, |
a4fc5ed6 KP |
1271 | DP_TRAINING_PATTERN_2, train_set, |
1272 | false)) | |
1273 | break; | |
1274 | ||
1275 | udelay(400); | |
ea5b213a | 1276 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
a4fc5ed6 KP |
1277 | break; |
1278 | ||
ea5b213a | 1279 | if (intel_channel_eq_ok(link_status, intel_dp->lane_count)) { |
a4fc5ed6 KP |
1280 | channel_eq = true; |
1281 | break; | |
1282 | } | |
1283 | ||
1284 | /* Try 5 times */ | |
1285 | if (tries > 5) | |
1286 | break; | |
1287 | ||
1288 | /* Compute new train_set as requested by target */ | |
ea5b213a | 1289 | intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set); |
a4fc5ed6 KP |
1290 | ++tries; |
1291 | } | |
1292 | ||
ea5b213a | 1293 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
e3421a18 ZW |
1294 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
1295 | else | |
1296 | reg = DP | DP_LINK_TRAIN_OFF; | |
1297 | ||
ea5b213a CW |
1298 | I915_WRITE(intel_dp->output_reg, reg); |
1299 | POSTING_READ(intel_dp->output_reg); | |
1300 | intel_dp_aux_native_write_1(intel_dp, | |
a4fc5ed6 KP |
1301 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
1302 | } | |
1303 | ||
1304 | static void | |
ea5b213a | 1305 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 1306 | { |
ea5b213a | 1307 | struct drm_device *dev = intel_dp->base.enc.dev; |
a4fc5ed6 | 1308 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1309 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1310 | |
28c97730 | 1311 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1312 | |
ea5b213a | 1313 | if (IS_eDP(intel_dp)) { |
32f9d658 | 1314 | DP &= ~DP_PLL_ENABLE; |
ea5b213a CW |
1315 | I915_WRITE(intel_dp->output_reg, DP); |
1316 | POSTING_READ(intel_dp->output_reg); | |
32f9d658 ZW |
1317 | udelay(100); |
1318 | } | |
1319 | ||
ea5b213a | 1320 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) { |
e3421a18 | 1321 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a CW |
1322 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
1323 | POSTING_READ(intel_dp->output_reg); | |
e3421a18 ZW |
1324 | } else { |
1325 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a CW |
1326 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
1327 | POSTING_READ(intel_dp->output_reg); | |
e3421a18 | 1328 | } |
5eb08b69 ZW |
1329 | |
1330 | udelay(17000); | |
1331 | ||
ea5b213a | 1332 | if (IS_eDP(intel_dp)) |
32f9d658 | 1333 | DP |= DP_LINK_TRAIN_OFF; |
ea5b213a CW |
1334 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
1335 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 KP |
1336 | } |
1337 | ||
a4fc5ed6 KP |
1338 | /* |
1339 | * According to DP spec | |
1340 | * 5.1.2: | |
1341 | * 1. Read DPCD | |
1342 | * 2. Configure link according to Receiver Capabilities | |
1343 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
1344 | * 4. Check link status on receipt of hot-plug interrupt | |
1345 | */ | |
1346 | ||
1347 | static void | |
ea5b213a | 1348 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1349 | { |
a4fc5ed6 KP |
1350 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
1351 | ||
ea5b213a | 1352 | if (!intel_dp->base.enc.crtc) |
a4fc5ed6 KP |
1353 | return; |
1354 | ||
ea5b213a CW |
1355 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
1356 | intel_dp_link_down(intel_dp); | |
a4fc5ed6 KP |
1357 | return; |
1358 | } | |
1359 | ||
ea5b213a CW |
1360 | if (!intel_channel_eq_ok(link_status, intel_dp->lane_count)) |
1361 | intel_dp_link_train(intel_dp); | |
a4fc5ed6 | 1362 | } |
a4fc5ed6 | 1363 | |
5eb08b69 | 1364 | static enum drm_connector_status |
f2b115e6 | 1365 | ironlake_dp_detect(struct drm_connector *connector) |
5eb08b69 | 1366 | { |
55f78c43 | 1367 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
ea5b213a | 1368 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
5eb08b69 ZW |
1369 | enum drm_connector_status status; |
1370 | ||
1371 | status = connector_status_disconnected; | |
ea5b213a CW |
1372 | if (intel_dp_aux_native_read(intel_dp, |
1373 | 0x000, intel_dp->dpcd, | |
1374 | sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) | |
5eb08b69 | 1375 | { |
ea5b213a | 1376 | if (intel_dp->dpcd[0] != 0) |
5eb08b69 ZW |
1377 | status = connector_status_connected; |
1378 | } | |
ea5b213a CW |
1379 | DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0], |
1380 | intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]); | |
5eb08b69 ZW |
1381 | return status; |
1382 | } | |
1383 | ||
a4fc5ed6 KP |
1384 | /** |
1385 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. | |
1386 | * | |
1387 | * \return true if DP port is connected. | |
1388 | * \return false if DP port is disconnected. | |
1389 | */ | |
1390 | static enum drm_connector_status | |
1391 | intel_dp_detect(struct drm_connector *connector) | |
1392 | { | |
55f78c43 | 1393 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
ea5b213a CW |
1394 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1395 | struct drm_device *dev = intel_dp->base.enc.dev; | |
a4fc5ed6 | 1396 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1397 | uint32_t temp, bit; |
1398 | enum drm_connector_status status; | |
1399 | ||
ea5b213a | 1400 | intel_dp->has_audio = false; |
a4fc5ed6 | 1401 | |
c619eed4 | 1402 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1403 | return ironlake_dp_detect(connector); |
5eb08b69 | 1404 | |
ea5b213a | 1405 | switch (intel_dp->output_reg) { |
a4fc5ed6 KP |
1406 | case DP_B: |
1407 | bit = DPB_HOTPLUG_INT_STATUS; | |
1408 | break; | |
1409 | case DP_C: | |
1410 | bit = DPC_HOTPLUG_INT_STATUS; | |
1411 | break; | |
1412 | case DP_D: | |
1413 | bit = DPD_HOTPLUG_INT_STATUS; | |
1414 | break; | |
1415 | default: | |
1416 | return connector_status_unknown; | |
1417 | } | |
1418 | ||
1419 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
1420 | ||
1421 | if ((temp & bit) == 0) | |
1422 | return connector_status_disconnected; | |
1423 | ||
1424 | status = connector_status_disconnected; | |
ea5b213a CW |
1425 | if (intel_dp_aux_native_read(intel_dp, |
1426 | 0x000, intel_dp->dpcd, | |
1427 | sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) | |
a4fc5ed6 | 1428 | { |
ea5b213a | 1429 | if (intel_dp->dpcd[0] != 0) |
a4fc5ed6 KP |
1430 | status = connector_status_connected; |
1431 | } | |
1432 | return status; | |
1433 | } | |
1434 | ||
1435 | static int intel_dp_get_modes(struct drm_connector *connector) | |
1436 | { | |
55f78c43 | 1437 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
ea5b213a CW |
1438 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1439 | struct drm_device *dev = intel_dp->base.enc.dev; | |
32f9d658 ZW |
1440 | struct drm_i915_private *dev_priv = dev->dev_private; |
1441 | int ret; | |
a4fc5ed6 KP |
1442 | |
1443 | /* We should parse the EDID data and find out if it has an audio sink | |
1444 | */ | |
1445 | ||
ea5b213a | 1446 | ret = intel_ddc_get_modes(connector, intel_dp->base.ddc_bus); |
b9efc480 | 1447 | if (ret) { |
ea5b213a | 1448 | if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && |
b9efc480 ZY |
1449 | !dev_priv->panel_fixed_mode) { |
1450 | struct drm_display_mode *newmode; | |
1451 | list_for_each_entry(newmode, &connector->probed_modes, | |
1452 | head) { | |
1453 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
1454 | dev_priv->panel_fixed_mode = | |
1455 | drm_mode_duplicate(dev, newmode); | |
1456 | break; | |
1457 | } | |
1458 | } | |
1459 | } | |
1460 | ||
32f9d658 | 1461 | return ret; |
b9efc480 | 1462 | } |
32f9d658 ZW |
1463 | |
1464 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ | |
ea5b213a | 1465 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { |
32f9d658 ZW |
1466 | if (dev_priv->panel_fixed_mode != NULL) { |
1467 | struct drm_display_mode *mode; | |
1468 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); | |
1469 | drm_mode_probed_add(connector, mode); | |
1470 | return 1; | |
1471 | } | |
1472 | } | |
1473 | return 0; | |
a4fc5ed6 KP |
1474 | } |
1475 | ||
1476 | static void | |
1477 | intel_dp_destroy (struct drm_connector *connector) | |
1478 | { | |
a4fc5ed6 KP |
1479 | drm_sysfs_connector_remove(connector); |
1480 | drm_connector_cleanup(connector); | |
55f78c43 | 1481 | kfree(connector); |
a4fc5ed6 KP |
1482 | } |
1483 | ||
1484 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { | |
1485 | .dpms = intel_dp_dpms, | |
1486 | .mode_fixup = intel_dp_mode_fixup, | |
d240f20f | 1487 | .prepare = intel_dp_prepare, |
a4fc5ed6 | 1488 | .mode_set = intel_dp_mode_set, |
d240f20f | 1489 | .commit = intel_dp_commit, |
a4fc5ed6 KP |
1490 | }; |
1491 | ||
1492 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
1493 | .dpms = drm_helper_connector_dpms, | |
a4fc5ed6 KP |
1494 | .detect = intel_dp_detect, |
1495 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1496 | .destroy = intel_dp_destroy, | |
1497 | }; | |
1498 | ||
1499 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
1500 | .get_modes = intel_dp_get_modes, | |
1501 | .mode_valid = intel_dp_mode_valid, | |
55f78c43 | 1502 | .best_encoder = intel_attached_encoder, |
a4fc5ed6 KP |
1503 | }; |
1504 | ||
a4fc5ed6 | 1505 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
ea5b213a | 1506 | .destroy = intel_encoder_destroy, |
a4fc5ed6 KP |
1507 | }; |
1508 | ||
c8110e52 | 1509 | void |
21d40d37 | 1510 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 1511 | { |
ea5b213a | 1512 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
c8110e52 | 1513 | |
ea5b213a CW |
1514 | if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON) |
1515 | intel_dp_check_link_status(intel_dp); | |
c8110e52 | 1516 | } |
6207937d | 1517 | |
e3421a18 ZW |
1518 | /* Return which DP Port should be selected for Transcoder DP control */ |
1519 | int | |
1520 | intel_trans_dp_port_sel (struct drm_crtc *crtc) | |
1521 | { | |
1522 | struct drm_device *dev = crtc->dev; | |
1523 | struct drm_mode_config *mode_config = &dev->mode_config; | |
1524 | struct drm_encoder *encoder; | |
e3421a18 ZW |
1525 | |
1526 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a CW |
1527 | struct intel_dp *intel_dp; |
1528 | ||
d8201ab6 | 1529 | if (encoder->crtc != crtc) |
e3421a18 ZW |
1530 | continue; |
1531 | ||
ea5b213a CW |
1532 | intel_dp = enc_to_intel_dp(encoder); |
1533 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) | |
1534 | return intel_dp->output_reg; | |
e3421a18 | 1535 | } |
ea5b213a | 1536 | |
e3421a18 ZW |
1537 | return -1; |
1538 | } | |
1539 | ||
36e83a18 | 1540 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 1541 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
1542 | { |
1543 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1544 | struct child_device_config *p_child; | |
1545 | int i; | |
1546 | ||
1547 | if (!dev_priv->child_dev_num) | |
1548 | return false; | |
1549 | ||
1550 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
1551 | p_child = dev_priv->child_dev + i; | |
1552 | ||
1553 | if (p_child->dvo_port == PORT_IDPD && | |
1554 | p_child->device_type == DEVICE_TYPE_eDP) | |
1555 | return true; | |
1556 | } | |
1557 | return false; | |
1558 | } | |
1559 | ||
a4fc5ed6 KP |
1560 | void |
1561 | intel_dp_init(struct drm_device *dev, int output_reg) | |
1562 | { | |
1563 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1564 | struct drm_connector *connector; | |
ea5b213a | 1565 | struct intel_dp *intel_dp; |
21d40d37 | 1566 | struct intel_encoder *intel_encoder; |
55f78c43 | 1567 | struct intel_connector *intel_connector; |
5eb08b69 | 1568 | const char *name = NULL; |
b329530c | 1569 | int type; |
a4fc5ed6 | 1570 | |
ea5b213a CW |
1571 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
1572 | if (!intel_dp) | |
a4fc5ed6 KP |
1573 | return; |
1574 | ||
55f78c43 ZW |
1575 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
1576 | if (!intel_connector) { | |
ea5b213a | 1577 | kfree(intel_dp); |
55f78c43 ZW |
1578 | return; |
1579 | } | |
ea5b213a | 1580 | intel_encoder = &intel_dp->base; |
55f78c43 | 1581 | |
ea5b213a | 1582 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
b329530c | 1583 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 1584 | intel_dp->is_pch_edp = true; |
b329530c | 1585 | |
ea5b213a | 1586 | if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) { |
b329530c AJ |
1587 | type = DRM_MODE_CONNECTOR_eDP; |
1588 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
1589 | } else { | |
1590 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
1591 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
1592 | } | |
1593 | ||
55f78c43 | 1594 | connector = &intel_connector->base; |
b329530c | 1595 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
1596 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
1597 | ||
eb1f8e4f DA |
1598 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
1599 | ||
652af9d7 | 1600 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
21d40d37 | 1601 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
652af9d7 | 1602 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
21d40d37 | 1603 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
652af9d7 | 1604 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
21d40d37 | 1605 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
f8aed700 | 1606 | |
ea5b213a | 1607 | if (IS_eDP(intel_dp)) |
21d40d37 | 1608 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
6251ec0a | 1609 | |
21d40d37 | 1610 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
a4fc5ed6 KP |
1611 | connector->interlace_allowed = true; |
1612 | connector->doublescan_allowed = 0; | |
1613 | ||
ea5b213a CW |
1614 | intel_dp->output_reg = output_reg; |
1615 | intel_dp->has_audio = false; | |
1616 | intel_dp->dpms_mode = DRM_MODE_DPMS_ON; | |
a4fc5ed6 | 1617 | |
21d40d37 | 1618 | drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs, |
a4fc5ed6 | 1619 | DRM_MODE_ENCODER_TMDS); |
21d40d37 | 1620 | drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs); |
a4fc5ed6 | 1621 | |
55f78c43 | 1622 | drm_mode_connector_attach_encoder(&intel_connector->base, |
21d40d37 | 1623 | &intel_encoder->enc); |
a4fc5ed6 KP |
1624 | drm_sysfs_connector_add(connector); |
1625 | ||
1626 | /* Set up the DDC bus. */ | |
5eb08b69 | 1627 | switch (output_reg) { |
32f9d658 ZW |
1628 | case DP_A: |
1629 | name = "DPDDC-A"; | |
1630 | break; | |
5eb08b69 ZW |
1631 | case DP_B: |
1632 | case PCH_DP_B: | |
b01f2c3a JB |
1633 | dev_priv->hotplug_supported_mask |= |
1634 | HDMIB_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1635 | name = "DPDDC-B"; |
1636 | break; | |
1637 | case DP_C: | |
1638 | case PCH_DP_C: | |
b01f2c3a JB |
1639 | dev_priv->hotplug_supported_mask |= |
1640 | HDMIC_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1641 | name = "DPDDC-C"; |
1642 | break; | |
1643 | case DP_D: | |
1644 | case PCH_DP_D: | |
b01f2c3a JB |
1645 | dev_priv->hotplug_supported_mask |= |
1646 | HDMID_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1647 | name = "DPDDC-D"; |
1648 | break; | |
1649 | } | |
1650 | ||
ea5b213a | 1651 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
32f9d658 | 1652 | |
ea5b213a | 1653 | intel_encoder->ddc_bus = &intel_dp->adapter; |
21d40d37 | 1654 | intel_encoder->hot_plug = intel_dp_hot_plug; |
a4fc5ed6 | 1655 | |
ea5b213a | 1656 | if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) { |
32f9d658 ZW |
1657 | /* initialize panel mode from VBT if available for eDP */ |
1658 | if (dev_priv->lfp_lvds_vbt_mode) { | |
1659 | dev_priv->panel_fixed_mode = | |
1660 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); | |
1661 | if (dev_priv->panel_fixed_mode) { | |
1662 | dev_priv->panel_fixed_mode->type |= | |
1663 | DRM_MODE_TYPE_PREFERRED; | |
1664 | } | |
1665 | } | |
1666 | } | |
1667 | ||
a4fc5ed6 KP |
1668 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
1669 | * 0xd. Failure to do so will result in spurious interrupts being | |
1670 | * generated on the port when a cable is not attached. | |
1671 | */ | |
1672 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1673 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1674 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1675 | } | |
1676 | } |