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drm/i915: set the correct eDP aux channel clock divider on DDI
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
50 return intel_dp->base.type == INTEL_OUTPUT_EDP;
51}
52
53/**
54 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
55 * @intel_dp: DP struct
56 *
57 * Returns true if the given DP struct corresponds to a PCH DP port attached
58 * to an eDP panel, false otherwise. Helpful for determining whether we
59 * may need FDI resources for a given DP output or not.
60 */
61static bool is_pch_edp(struct intel_dp *intel_dp)
62{
63 return intel_dp->is_pch_edp;
64}
65
1c95822a
AJ		 66/**
67 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
68 * @intel_dp: DP struct
69 *
70 * Returns true if the given DP struct corresponds to a CPU eDP port.
71 */
72static bool is_cpu_edp(struct intel_dp *intel_dp)
73{
74 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
75}
76
df0e9248
CW		 77static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
78{
79 return container_of(intel_attached_encoder(connector),
80 struct intel_dp, base);
81}
82
814948ad
JB		 83/**
84 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
85 * @encoder: DRM encoder
86 *
87 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
88 * by intel_display.c.
89 */
90bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
91{
92 struct intel_dp *intel_dp;
93
94 if (!encoder)
95 return false;
96
97 intel_dp = enc_to_intel_dp(encoder);
98
99 return is_pch_edp(intel_dp);
100}
101
ea5b213a 102static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 103
32f9d658 104void
0206e353 105intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 106 int *lane_num, int *link_bw)
32f9d658 107{
ea5b213a 108 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 109
ea5b213a 110 *lane_num = intel_dp->lane_count;
3b5c662e 111 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
32f9d658
ZW		 112}
113
94bf2ced
DV		 114int
115intel_edp_target_clock(struct intel_encoder *intel_encoder,
116 struct drm_display_mode *mode)
117{
118 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
dd06f90e 119 struct intel_connector *intel_connector = intel_dp->attached_connector;
94bf2ced 120
dd06f90e
JN		 121 if (intel_connector->panel.fixed_mode)
122 return intel_connector->panel.fixed_mode->clock;
94bf2ced
DV		 123 else
124 return mode->clock;
125}
126
a4fc5ed6 127static int
ea5b213a 128intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 129{
7183dc29 130 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 131
132 switch (max_link_bw) {
133 case DP_LINK_BW_1_62:
134 case DP_LINK_BW_2_7:
135 break;
136 default:
137 max_link_bw = DP_LINK_BW_1_62;
138 break;
139 }
140 return max_link_bw;
141}
142
143static int
144intel_dp_link_clock(uint8_t link_bw)
145{
146 if (link_bw == DP_LINK_BW_2_7)
147 return 270000;
148 else
149 return 162000;
150}
151
cd9dde44
AJ		 152/*
153 * The units on the numbers in the next two are... bizarre. Examples will
154 * make it clearer; this one parallels an example in the eDP spec.
155 *
156 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
157 *
158 * 270000 * 1 * 8 / 10 == 216000
159 *
160 * The actual data capacity of that configuration is 2.16Gbit/s, so the
161 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
162 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
163 * 119000. At 18bpp that's 2142000 kilobits per second.
164 *
165 * Thus the strange-looking division by 10 in intel_dp_link_required, to
166 * get the result in decakilobits instead of kilobits.
167 */
168
a4fc5ed6 169static int
c898261c 170intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 171{
cd9dde44 172 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 173}
174
fe27d53e
DA		 175static int
176intel_dp_max_data_rate(int max_link_clock, int max_lanes)
177{
178 return (max_link_clock * max_lanes * 8) / 10;
179}
180
c4867936
DV		 181static bool
182intel_dp_adjust_dithering(struct intel_dp *intel_dp,
183 struct drm_display_mode *mode,
cb1793ce 184 bool adjust_mode)
c4867936
DV		 185{
186 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
397fe157 187 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
c4867936
DV		 188 int max_rate, mode_rate;
189
190 mode_rate = intel_dp_link_required(mode->clock, 24);
191 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
192
193 if (mode_rate > max_rate) {
194 mode_rate = intel_dp_link_required(mode->clock, 18);
195 if (mode_rate > max_rate)
196 return false;
197
cb1793ce
DV		 198 if (adjust_mode)
199 mode->private_flags
c4867936
DV		 200 |= INTEL_MODE_DP_FORCE_6BPC;
201
202 return true;
203 }
204
205 return true;
206}
207
a4fc5ed6
KP		 208static int
209intel_dp_mode_valid(struct drm_connector *connector,
210 struct drm_display_mode *mode)
211{
df0e9248 212 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 213 struct intel_connector *intel_connector = to_intel_connector(connector);
214 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
a4fc5ed6 215
dd06f90e
JN		 216 if (is_edp(intel_dp) && fixed_mode) {
217 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 218 return MODE_PANEL;
219
dd06f90e 220 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43
ZY		 221 return MODE_PANEL;
222 }
223
cb1793ce 224 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 225 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 226
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
229
0af78a2b
DV		 230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
232
a4fc5ed6
KP		 233 return MODE_OK;
234}
235
236static uint32_t
237pack_aux(uint8_t *src, int src_bytes)
238{
239 int i;
240 uint32_t v = 0;
241
242 if (src_bytes > 4)
243 src_bytes = 4;
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
246 return v;
247}
248
249static void
250unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
251{
252 int i;
253 if (dst_bytes > 4)
254 dst_bytes = 4;
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
257}
258
fb0f8fbf
KP		 259/* hrawclock is 1/4 the FSB frequency */
260static int
261intel_hrawclk(struct drm_device *dev)
262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 uint32_t clkcfg;
265
9473c8f4
VP		 266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
268 return 200;
269
fb0f8fbf
KP		 270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
272 case CLKCFG_FSB_400:
273 return 100;
274 case CLKCFG_FSB_533:
275 return 133;
276 case CLKCFG_FSB_667:
277 return 166;
278 case CLKCFG_FSB_800:
279 return 200;
280 case CLKCFG_FSB_1067:
281 return 266;
282 case CLKCFG_FSB_1333:
283 return 333;
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
287 return 400;
288 default:
289 return 133;
290 }
291}
292
ebf33b18
KP		 293static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
294{
295 struct drm_device *dev = intel_dp->base.base.dev;
296 struct drm_i915_private *dev_priv = dev->dev_private;
297
298 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
299}
300
301static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
302{
303 struct drm_device *dev = intel_dp->base.base.dev;
304 struct drm_i915_private *dev_priv = dev->dev_private;
305
306 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
307}
308
9b984dae
KP		 309static void
310intel_dp_check_edp(struct intel_dp *intel_dp)
311{
312 struct drm_device *dev = intel_dp->base.base.dev;
313 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 314
9b984dae
KP		 315 if (!is_edp(intel_dp))
316 return;
ebf33b18 317 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 318 WARN(1, "eDP powered off while attempting aux channel communication.\n");
319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 320 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 321 I915_READ(PCH_PP_CONTROL));
322 }
323}
324
a4fc5ed6 325static int
ea5b213a 326intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 327 uint8_t *send, int send_bytes,
328 uint8_t *recv, int recv_size)
329{
ea5b213a 330 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 331 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 332 struct drm_i915_private *dev_priv = dev->dev_private;
333 uint32_t ch_ctl = output_reg + 0x10;
334 uint32_t ch_data = ch_ctl + 4;
335 int i;
336 int recv_bytes;
a4fc5ed6 337 uint32_t status;
fb0f8fbf 338 uint32_t aux_clock_divider;
6b4e0a93 339 int try, precharge;
a4fc5ed6 340
750eb99e
PZ		 341 if (IS_HASWELL(dev)) {
342 switch (intel_dp->port) {
343 case PORT_A:
344 ch_ctl = DPA_AUX_CH_CTL;
345 ch_data = DPA_AUX_CH_DATA1;
346 break;
347 case PORT_B:
348 ch_ctl = PCH_DPB_AUX_CH_CTL;
349 ch_data = PCH_DPB_AUX_CH_DATA1;
350 break;
351 case PORT_C:
352 ch_ctl = PCH_DPC_AUX_CH_CTL;
353 ch_data = PCH_DPC_AUX_CH_DATA1;
354 break;
355 case PORT_D:
356 ch_ctl = PCH_DPD_AUX_CH_CTL;
357 ch_data = PCH_DPD_AUX_CH_DATA1;
358 break;
359 default:
360 BUG();
361 }
362 }
363
9b984dae 364 intel_dp_check_edp(intel_dp);
a4fc5ed6 365 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 366 * and would like to run at 2MHz. So, take the
367 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 368 *
369 * Note that PCH attached eDP panels should use a 125MHz input
370 * clock divider.
a4fc5ed6 371 */
1c95822a 372 if (is_cpu_edp(intel_dp)) {
b8fc2f6a
PZ		 373 if (IS_HASWELL(dev))
374 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
375 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 376 aux_clock_divider = 100;
377 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 378 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 379 else
380 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
381 } else if (HAS_PCH_SPLIT(dev))
6b3ec1c9 382 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
5eb08b69
ZW		 383 else
384 aux_clock_divider = intel_hrawclk(dev) / 2;
385
6b4e0a93
DV		 386 if (IS_GEN6(dev))
387 precharge = 3;
388 else
389 precharge = 5;
390
11bee43e
JB		 391 /* Try to wait for any previous AUX channel activity */
392 for (try = 0; try < 3; try++) {
393 status = I915_READ(ch_ctl);
394 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
395 break;
396 msleep(1);
397 }
398
399 if (try == 3) {
400 WARN(1, "dp_aux_ch not started status 0x%08x\n",
401 I915_READ(ch_ctl));
4f7f7b7e
CW		 402 return -EBUSY;
403 }
404
fb0f8fbf
KP		 405 /* Must try at least 3 times according to DP spec */
406 for (try = 0; try < 5; try++) {
407 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 408 for (i = 0; i < send_bytes; i += 4)
409 I915_WRITE(ch_data + i,
410 pack_aux(send + i, send_bytes - i));
0206e353 411
fb0f8fbf 412 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 413 I915_WRITE(ch_ctl,
414 DP_AUX_CH_CTL_SEND_BUSY |
415 DP_AUX_CH_CTL_TIME_OUT_400us |
416 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
417 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
418 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
419 DP_AUX_CH_CTL_DONE |
420 DP_AUX_CH_CTL_TIME_OUT_ERROR |
421 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 422 for (;;) {
fb0f8fbf
KP		 423 status = I915_READ(ch_ctl);
424 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
425 break;
4f7f7b7e 426 udelay(100);
fb0f8fbf 427 }
0206e353 428
fb0f8fbf 429 /* Clear done status and any errors */
4f7f7b7e
CW		 430 I915_WRITE(ch_ctl,
431 status |
432 DP_AUX_CH_CTL_DONE |
433 DP_AUX_CH_CTL_TIME_OUT_ERROR |
434 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 435
436 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
437 DP_AUX_CH_CTL_RECEIVE_ERROR))
438 continue;
4f7f7b7e 439 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 440 break;
441 }
442
a4fc5ed6 443 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 444 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 445 return -EBUSY;
a4fc5ed6
KP		 446 }
447
448 /* Check for timeout or receive error.
449 * Timeouts occur when the sink is not connected
450 */
a5b3da54 451 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 452 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 453 return -EIO;
454 }
1ae8c0a5
KP		 455
456 /* Timeouts occur when the device isn't connected, so they're
457 * "normal" -- don't fill the kernel log with these */
a5b3da54 458 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 459 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 460 return -ETIMEDOUT;
a4fc5ed6
KP		 461 }
462
463 /* Unload any bytes sent back from the other side */
464 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
465 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 466 if (recv_bytes > recv_size)
467 recv_bytes = recv_size;
0206e353 468
4f7f7b7e
CW		 469 for (i = 0; i < recv_bytes; i += 4)
470 unpack_aux(I915_READ(ch_data + i),
471 recv + i, recv_bytes - i);
a4fc5ed6
KP		 472
473 return recv_bytes;
474}
475
476/* Write data to the aux channel in native mode */
477static int
ea5b213a 478intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 479 uint16_t address, uint8_t *send, int send_bytes)
480{
481 int ret;
482 uint8_t msg[20];
483 int msg_bytes;
484 uint8_t ack;
485
9b984dae 486 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 487 if (send_bytes > 16)
488 return -1;
489 msg[0] = AUX_NATIVE_WRITE << 4;
490 msg[1] = address >> 8;
eebc863e 491 msg[2] = address & 0xff;
a4fc5ed6
KP		 492 msg[3] = send_bytes - 1;
493 memcpy(&msg[4], send, send_bytes);
494 msg_bytes = send_bytes + 4;
495 for (;;) {
ea5b213a 496 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 497 if (ret < 0)
498 return ret;
499 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
500 break;
501 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
502 udelay(100);
503 else
a5b3da54 504 return -EIO;
a4fc5ed6
KP		 505 }
506 return send_bytes;
507}
508
509/* Write a single byte to the aux channel in native mode */
510static int
ea5b213a 511intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 512 uint16_t address, uint8_t byte)
513{
ea5b213a 514 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 515}
516
517/* read bytes from a native aux channel */
518static int
ea5b213a 519intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 520 uint16_t address, uint8_t *recv, int recv_bytes)
521{
522 uint8_t msg[4];
523 int msg_bytes;
524 uint8_t reply[20];
525 int reply_bytes;
526 uint8_t ack;
527 int ret;
528
9b984dae 529 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 530 msg[0] = AUX_NATIVE_READ << 4;
531 msg[1] = address >> 8;
532 msg[2] = address & 0xff;
533 msg[3] = recv_bytes - 1;
534
535 msg_bytes = 4;
536 reply_bytes = recv_bytes + 1;
537
538 for (;;) {
ea5b213a 539 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 540 reply, reply_bytes);
a5b3da54
KP		 541 if (ret == 0)
542 return -EPROTO;
543 if (ret < 0)
a4fc5ed6
KP		 544 return ret;
545 ack = reply[0];
546 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
547 memcpy(recv, reply + 1, ret - 1);
548 return ret - 1;
549 }
550 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
551 udelay(100);
552 else
a5b3da54 553 return -EIO;
a4fc5ed6
KP		 554 }
555}
556
557static int
ab2c0672
DA		 558intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
559 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 560{
ab2c0672 561 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 562 struct intel_dp *intel_dp = container_of(adapter,
563 struct intel_dp,
564 adapter);
ab2c0672
DA		 565 uint16_t address = algo_data->address;
566 uint8_t msg[5];
567 uint8_t reply[2];
8316f337 568 unsigned retry;
ab2c0672
DA		 569 int msg_bytes;
570 int reply_bytes;
571 int ret;
572
9b984dae 573 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 574 /* Set up the command byte */
575 if (mode & MODE_I2C_READ)
576 msg[0] = AUX_I2C_READ << 4;
577 else
578 msg[0] = AUX_I2C_WRITE << 4;
579
580 if (!(mode & MODE_I2C_STOP))
581 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 582
ab2c0672
DA		 583 msg[1] = address >> 8;
584 msg[2] = address;
585
586 switch (mode) {
587 case MODE_I2C_WRITE:
588 msg[3] = 0;
589 msg[4] = write_byte;
590 msg_bytes = 5;
591 reply_bytes = 1;
592 break;
593 case MODE_I2C_READ:
594 msg[3] = 0;
595 msg_bytes = 4;
596 reply_bytes = 2;
597 break;
598 default:
599 msg_bytes = 3;
600 reply_bytes = 1;
601 break;
602 }
603
8316f337
DF		 604 for (retry = 0; retry < 5; retry++) {
605 ret = intel_dp_aux_ch(intel_dp,
606 msg, msg_bytes,
607 reply, reply_bytes);
ab2c0672 608 if (ret < 0) {
3ff99164 609 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 610 return ret;
611 }
8316f337
DF		 612
613 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
614 case AUX_NATIVE_REPLY_ACK:
615 /* I2C-over-AUX Reply field is only valid
616 * when paired with AUX ACK.
617 */
618 break;
619 case AUX_NATIVE_REPLY_NACK:
620 DRM_DEBUG_KMS("aux_ch native nack\n");
621 return -EREMOTEIO;
622 case AUX_NATIVE_REPLY_DEFER:
623 udelay(100);
624 continue;
625 default:
626 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
627 reply[0]);
628 return -EREMOTEIO;
629 }
630
ab2c0672
DA		 631 switch (reply[0] & AUX_I2C_REPLY_MASK) {
632 case AUX_I2C_REPLY_ACK:
633 if (mode == MODE_I2C_READ) {
634 *read_byte = reply[1];
635 }
636 return reply_bytes - 1;
637 case AUX_I2C_REPLY_NACK:
8316f337 638 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 639 return -EREMOTEIO;
640 case AUX_I2C_REPLY_DEFER:
8316f337 641 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 642 udelay(100);
643 break;
644 default:
8316f337 645 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 646 return -EREMOTEIO;
647 }
648 }
8316f337
DF		 649
650 DRM_ERROR("too many retries, giving up\n");
651 return -EREMOTEIO;
a4fc5ed6
KP		 652}
653
0b5c541b 654static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
bd943159 655static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0b5c541b 656
a4fc5ed6 657static int
ea5b213a 658intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 659 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 660{
0b5c541b
KP		 661 int ret;
662
d54e9d28 663 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 664 intel_dp->algo.running = false;
665 intel_dp->algo.address = 0;
666 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
667
0206e353 668 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 669 intel_dp->adapter.owner = THIS_MODULE;
670 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 671 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 672 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
673 intel_dp->adapter.algo_data = &intel_dp->algo;
674 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
675
0b5c541b
KP		 676 ironlake_edp_panel_vdd_on(intel_dp);
677 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 678 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 679 return ret;
a4fc5ed6
KP		 680}
681
682static bool
e811f5ae
LP		 683intel_dp_mode_fixup(struct drm_encoder *encoder,
684 const struct drm_display_mode *mode,
a4fc5ed6
KP		 685 struct drm_display_mode *adjusted_mode)
686{
0d3a1bee 687 struct drm_device *dev = encoder->dev;
ea5b213a 688 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
dd06f90e 689 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 690 int lane_count, clock;
397fe157 691 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 692 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 693 int bpp, mode_rate;
a4fc5ed6
KP		 694 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
695
dd06f90e
JN		 696 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
697 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
698 adjusted_mode);
1d8e1c75
CW		 699 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
700 mode, adjusted_mode);
0d3a1bee
ZY		 701 }
702
cb1793ce 703 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 704 return false;
705
083f9560
DV		 706 DRM_DEBUG_KMS("DP link computation with max lane count %i "
707 "max bw %02x pixel clock %iKHz\n",
71244653 708 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 709
cb1793ce 710 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 711 return false;
712
713 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 714 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 715
2514bc51
JB		 716 for (clock = 0; clock <= max_clock; clock++) {
717 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
fe27d53e 718 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 719
083f9560 720 if (mode_rate <= link_avail) {
ea5b213a
CW		 721 intel_dp->link_bw = bws[clock];
722 intel_dp->lane_count = lane_count;
723 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 724 DRM_DEBUG_KMS("DP link bw %02x lane "
725 "count %d clock %d bpp %d\n",
ea5b213a 726 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 727 adjusted_mode->clock, bpp);
728 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
729 mode_rate, link_avail);
a4fc5ed6
KP		 730 return true;
731 }
732 }
733 }
fe27d53e 734
a4fc5ed6
KP		 735 return false;
736}
737
738struct intel_dp_m_n {
739 uint32_t tu;
740 uint32_t gmch_m;
741 uint32_t gmch_n;
742 uint32_t link_m;
743 uint32_t link_n;
744};
745
746static void
747intel_reduce_ratio(uint32_t *num, uint32_t *den)
748{
749 while (*num > 0xffffff || *den > 0xffffff) {
750 *num >>= 1;
751 *den >>= 1;
752 }
753}
754
755static void
36e83a18 756intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 757 int nlanes,
758 int pixel_clock,
759 int link_clock,
760 struct intel_dp_m_n *m_n)
761{
762 m_n->tu = 64;
36e83a18 763 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 764 m_n->gmch_n = link_clock * nlanes;
765 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
766 m_n->link_m = pixel_clock;
767 m_n->link_n = link_clock;
768 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
769}
770
771void
772intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
773 struct drm_display_mode *adjusted_mode)
774{
775 struct drm_device *dev = crtc->dev;
6c2b7c12 776 struct intel_encoder *encoder;
a4fc5ed6
KP		 777 struct drm_i915_private *dev_priv = dev->dev_private;
778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 779 int lane_count = 4;
a4fc5ed6 780 struct intel_dp_m_n m_n;
9db4a9c7 781 int pipe = intel_crtc->pipe;
afe2fcf5 782 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
a4fc5ed6
KP		 783
784 /*
21d40d37 785 * Find the lane count in the intel_encoder private
a4fc5ed6 786 */
6c2b7c12
DV		 787 for_each_encoder_on_crtc(dev, crtc, encoder) {
788 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 789
9a10f401
KP		 790 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
791 intel_dp->base.type == INTEL_OUTPUT_EDP)
792 {
ea5b213a 793 lane_count = intel_dp->lane_count;
51190667 794 break;
a4fc5ed6
KP		 795 }
796 }
797
798 /*
799 * Compute the GMCH and Link ratios. The '3' here is
800 * the number of bytes_per_pixel post-LUT, which we always
801 * set up for 8-bits of R/G/B, or 3 bytes total.
802 */
858fa035 803 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 804 mode->clock, adjusted_mode->clock, &m_n);
805
1eb8dfec 806 if (IS_HASWELL(dev)) {
afe2fcf5
PZ		 807 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
808 TU_SIZE(m_n.tu) | m_n.gmch_m);
809 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
810 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
811 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
1eb8dfec 812 } else if (HAS_PCH_SPLIT(dev)) {
7346bfa0 813 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 814 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
815 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
816 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 817 } else if (IS_VALLEYVIEW(dev)) {
818 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
819 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
820 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
821 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 822 } else {
9db4a9c7 823 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
7346bfa0 824 TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 825 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
826 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
827 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 828 }
829}
830
247d89f6
PZ		 831void intel_dp_init_link_config(struct intel_dp *intel_dp)
832{
833 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
834 intel_dp->link_configuration[0] = intel_dp->link_bw;
835 intel_dp->link_configuration[1] = intel_dp->lane_count;
836 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
837 /*
838 * Check for DPCD version > 1.1 and enhanced framing support
839 */
840 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
841 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
842 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
843 }
844}
845
a4fc5ed6
KP		 846static void
847intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
848 struct drm_display_mode *adjusted_mode)
849{
e3421a18 850 struct drm_device *dev = encoder->dev;
417e822d 851 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 852 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 853 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
855
417e822d 856 /*
1a2eb460 857 * There are four kinds of DP registers:
417e822d
KP		 858 *
859 * IBX PCH
1a2eb460
KP		 860 * SNB CPU
861 * IVB CPU
417e822d
KP		 862 * CPT PCH
863 *
864 * IBX PCH and CPU are the same for almost everything,
865 * except that the CPU DP PLL is configured in this
866 * register
867 *
868 * CPT PCH is quite different, having many bits moved
869 * to the TRANS_DP_CTL register instead. That
870 * configuration happens (oddly) in ironlake_pch_enable
871 */
9c9e7927 872
417e822d
KP		 873 /* Preserve the BIOS-computed detected bit. This is
874 * supposed to be read-only.
875 */
876 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 877
417e822d 878 /* Handle DP bits in common between all three register formats */
417e822d 879 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 880
ea5b213a 881 switch (intel_dp->lane_count) {
a4fc5ed6 882 case 1:
ea5b213a 883 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 884 break;
885 case 2:
ea5b213a 886 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 887 break;
888 case 4:
ea5b213a 889 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 890 break;
891 }
e0dac65e
WF		 892 if (intel_dp->has_audio) {
893 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
894 pipe_name(intel_crtc->pipe));
ea5b213a 895 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 896 intel_write_eld(encoder, adjusted_mode);
897 }
247d89f6
PZ		 898
899 intel_dp_init_link_config(intel_dp);
a4fc5ed6 900
417e822d 901 /* Split out the IBX/CPU vs CPT settings */
32f9d658 902
19c03924 903 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 904 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
905 intel_dp->DP |= DP_SYNC_HS_HIGH;
906 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
907 intel_dp->DP |= DP_SYNC_VS_HIGH;
908 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
909
910 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
911 intel_dp->DP |= DP_ENHANCED_FRAMING;
912
913 intel_dp->DP |= intel_crtc->pipe << 29;
914
915 /* don't miss out required setting for eDP */
1a2eb460
KP		 916 if (adjusted_mode->clock < 200000)
917 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
918 else
919 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
920 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 921 intel_dp->DP |= intel_dp->color_range;
922
923 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
924 intel_dp->DP |= DP_SYNC_HS_HIGH;
925 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
926 intel_dp->DP |= DP_SYNC_VS_HIGH;
927 intel_dp->DP |= DP_LINK_TRAIN_OFF;
928
929 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
930 intel_dp->DP |= DP_ENHANCED_FRAMING;
931
932 if (intel_crtc->pipe == 1)
933 intel_dp->DP |= DP_PIPEB_SELECT;
934
935 if (is_cpu_edp(intel_dp)) {
936 /* don't miss out required setting for eDP */
417e822d
KP		 937 if (adjusted_mode->clock < 200000)
938 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
939 else
940 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
941 }
942 } else {
943 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 944 }
a4fc5ed6
KP		 945}
946
99ea7127
KP		 947#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
948#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
949
950#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
951#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
952
953#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
954#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
955
956static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
957 u32 mask,
958 u32 value)
bd943159 959{
99ea7127
KP		 960 struct drm_device *dev = intel_dp->base.base.dev;
961 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 962
99ea7127
KP		 963 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
964 mask, value,
965 I915_READ(PCH_PP_STATUS),
966 I915_READ(PCH_PP_CONTROL));
32ce697c 967
99ea7127
KP		 968 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
969 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
970 I915_READ(PCH_PP_STATUS),
971 I915_READ(PCH_PP_CONTROL));
32ce697c 972 }
99ea7127 973}
32ce697c 974
99ea7127
KP		 975static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
976{
977 DRM_DEBUG_KMS("Wait for panel power on\n");
978 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 979}
980
99ea7127
KP		 981static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
982{
983 DRM_DEBUG_KMS("Wait for panel power off time\n");
984 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
985}
986
987static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
988{
989 DRM_DEBUG_KMS("Wait for panel power cycle\n");
990 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
991}
992
993
832dd3c1
KP		 994/* Read the current pp_control value, unlocking the register if it
995 * is locked
996 */
997
998static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
999{
1000 u32 control = I915_READ(PCH_PP_CONTROL);
1001
1002 control &= ~PANEL_UNLOCK_MASK;
1003 control |= PANEL_UNLOCK_REGS;
1004 return control;
bd943159
KP		 1005}
1006
5d613501
JB		 1007static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1008{
1009 struct drm_device *dev = intel_dp->base.base.dev;
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 u32 pp;
1012
97af61f5
KP		 1013 if (!is_edp(intel_dp))
1014 return;
f01eca2e 1015 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1016
bd943159
KP		 1017 WARN(intel_dp->want_panel_vdd,
1018 "eDP VDD already requested on\n");
1019
1020 intel_dp->want_panel_vdd = true;
99ea7127 1021
bd943159
KP		 1022 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1023 DRM_DEBUG_KMS("eDP VDD already on\n");
1024 return;
1025 }
1026
99ea7127
KP		 1027 if (!ironlake_edp_have_panel_power(intel_dp))
1028 ironlake_wait_panel_power_cycle(intel_dp);
1029
832dd3c1 1030 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1031 pp |= EDP_FORCE_VDD;
1032 I915_WRITE(PCH_PP_CONTROL, pp);
1033 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1034 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1035 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1036
1037 /*
1038 * If the panel wasn't on, delay before accessing aux channel
1039 */
1040 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1041 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1042 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1043 }
5d613501
JB		 1044}
1045
bd943159 1046static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1047{
1048 struct drm_device *dev = intel_dp->base.base.dev;
1049 struct drm_i915_private *dev_priv = dev->dev_private;
1050 u32 pp;
1051
bd943159 1052 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1053 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1054 pp &= ~EDP_FORCE_VDD;
1055 I915_WRITE(PCH_PP_CONTROL, pp);
1056 POSTING_READ(PCH_PP_CONTROL);
1057
1058 /* Make sure sequencer is idle before allowing subsequent activity */
1059 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1060 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1061
1062 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1063 }
1064}
5d613501 1065
bd943159
KP		 1066static void ironlake_panel_vdd_work(struct work_struct *__work)
1067{
1068 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1069 struct intel_dp, panel_vdd_work);
1070 struct drm_device *dev = intel_dp->base.base.dev;
1071
627f7675 1072 mutex_lock(&dev->mode_config.mutex);
bd943159 1073 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1074 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1075}
1076
1077static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1078{
97af61f5
KP		 1079 if (!is_edp(intel_dp))
1080 return;
5d613501 1081
bd943159
KP		 1082 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1083 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1084
bd943159
KP		 1085 intel_dp->want_panel_vdd = false;
1086
1087 if (sync) {
1088 ironlake_panel_vdd_off_sync(intel_dp);
1089 } else {
1090 /*
1091 * Queue the timer to fire a long
1092 * time from now (relative to the power down delay)
1093 * to keep the panel power up across a sequence of operations
1094 */
1095 schedule_delayed_work(&intel_dp->panel_vdd_work,
1096 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1097 }
5d613501
JB		 1098}
1099
86a3073e 1100static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1101{
01cb9ea6 1102 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1103 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1104 u32 pp;
9934c132 1105
97af61f5 1106 if (!is_edp(intel_dp))
bd943159 1107 return;
99ea7127
KP		 1108
1109 DRM_DEBUG_KMS("Turn eDP power on\n");
1110
1111 if (ironlake_edp_have_panel_power(intel_dp)) {
1112 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1113 return;
99ea7127 1114 }
9934c132 1115
99ea7127 1116 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1117
99ea7127 1118 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1119 if (IS_GEN5(dev)) {
1120 /* ILK workaround: disable reset around power sequence */
1121 pp &= ~PANEL_POWER_RESET;
1122 I915_WRITE(PCH_PP_CONTROL, pp);
1123 POSTING_READ(PCH_PP_CONTROL);
1124 }
37c6c9b0 1125
1c0ae80a 1126 pp |= POWER_TARGET_ON;
99ea7127
KP		 1127 if (!IS_GEN5(dev))
1128 pp |= PANEL_POWER_RESET;
1129
9934c132 1130 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1131 POSTING_READ(PCH_PP_CONTROL);
9934c132 1132
99ea7127 1133 ironlake_wait_panel_on(intel_dp);
9934c132 1134
05ce1a49
KP		 1135 if (IS_GEN5(dev)) {
1136 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1137 I915_WRITE(PCH_PP_CONTROL, pp);
1138 POSTING_READ(PCH_PP_CONTROL);
1139 }
9934c132
JB		 1140}
1141
99ea7127 1142static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1143{
99ea7127 1144 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1145 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1146 u32 pp;
9934c132 1147
97af61f5
KP		 1148 if (!is_edp(intel_dp))
1149 return;
37c6c9b0 1150
99ea7127 1151 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1152
6cb49835 1153 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1154
99ea7127 1155 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1156 /* We need to switch off panel power _and_ force vdd, for otherwise some
1157 * panels get very unhappy and cease to work. */
1158 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1159 I915_WRITE(PCH_PP_CONTROL, pp);
1160 POSTING_READ(PCH_PP_CONTROL);
9934c132 1161
35a38556
DV		 1162 intel_dp->want_panel_vdd = false;
1163
99ea7127 1164 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1165}
1166
86a3073e 1167static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1168{
f01eca2e 1169 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658 1170 struct drm_i915_private *dev_priv = dev->dev_private;
035aa3de 1171 int pipe = to_intel_crtc(intel_dp->base.base.crtc)->pipe;
32f9d658
ZW		 1172 u32 pp;
1173
f01eca2e
KP		 1174 if (!is_edp(intel_dp))
1175 return;
1176
28c97730 1177 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1178 /*
1179 * If we enable the backlight right away following a panel power
1180 * on, we may see slight flicker as the panel syncs with the eDP
1181 * link. So delay a bit to make sure the image is solid before
1182 * allowing it to appear.
1183 */
f01eca2e 1184 msleep(intel_dp->backlight_on_delay);
832dd3c1 1185 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1186 pp |= EDP_BLC_ENABLE;
1187 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1188 POSTING_READ(PCH_PP_CONTROL);
035aa3de
DV		 1189
1190 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1191}
1192
86a3073e 1193static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1194{
f01eca2e 1195 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1196 struct drm_i915_private *dev_priv = dev->dev_private;
1197 u32 pp;
1198
f01eca2e
KP		 1199 if (!is_edp(intel_dp))
1200 return;
1201
035aa3de
DV		 1202 intel_panel_disable_backlight(dev);
1203
28c97730 1204 DRM_DEBUG_KMS("\n");
832dd3c1 1205 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1206 pp &= ~EDP_BLC_ENABLE;
1207 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1208 POSTING_READ(PCH_PP_CONTROL);
1209 msleep(intel_dp->backlight_off_delay);
32f9d658 1210}
a4fc5ed6 1211
2bd2ad64 1212static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1213{
2bd2ad64
DV		 1214 struct drm_device *dev = intel_dp->base.base.dev;
1215 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1216 struct drm_i915_private *dev_priv = dev->dev_private;
1217 u32 dpa_ctl;
1218
2bd2ad64
DV		 1219 assert_pipe_disabled(dev_priv,
1220 to_intel_crtc(crtc)->pipe);
1221
d240f20f
JB		 1222 DRM_DEBUG_KMS("\n");
1223 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1224 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1225 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1226
1227 /* We don't adjust intel_dp->DP while tearing down the link, to
1228 * facilitate link retraining (e.g. after hotplug). Hence clear all
1229 * enable bits here to ensure that we don't enable too much. */
1230 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1231 intel_dp->DP |= DP_PLL_ENABLE;
1232 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1233 POSTING_READ(DP_A);
1234 udelay(200);
d240f20f
JB		 1235}
1236
2bd2ad64 1237static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1238{
2bd2ad64
DV		 1239 struct drm_device *dev = intel_dp->base.base.dev;
1240 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1241 struct drm_i915_private *dev_priv = dev->dev_private;
1242 u32 dpa_ctl;
1243
2bd2ad64
DV		 1244 assert_pipe_disabled(dev_priv,
1245 to_intel_crtc(crtc)->pipe);
1246
d240f20f 1247 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1248 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1249 "dp pll off, should be on\n");
1250 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1251
1252 /* We can't rely on the value tracked for the DP register in
1253 * intel_dp->DP because link_down must not change that (otherwise link
1254 * re-training will fail. */
298b0b39 1255 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1256 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1257 POSTING_READ(DP_A);
d240f20f
JB		 1258 udelay(200);
1259}
1260
c7ad3810 1261/* If the sink supports it, try to set the power state appropriately */
c19b0669 1262void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1263{
1264 int ret, i;
1265
1266 /* Should have a valid DPCD by this point */
1267 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1268 return;
1269
1270 if (mode != DRM_MODE_DPMS_ON) {
1271 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1272 DP_SET_POWER_D3);
1273 if (ret != 1)
1274 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1275 } else {
1276 /*
1277 * When turning on, we need to retry for 1ms to give the sink
1278 * time to wake up.
1279 */
1280 for (i = 0; i < 3; i++) {
1281 ret = intel_dp_aux_native_write_1(intel_dp,
1282 DP_SET_POWER,
1283 DP_SET_POWER_D0);
1284 if (ret == 1)
1285 break;
1286 msleep(1);
1287 }
1288 }
1289}
1290
19d8fe15
DV		 1291static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1292 enum pipe *pipe)
d240f20f 1293{
19d8fe15
DV		 1294 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1295 struct drm_device *dev = encoder->base.dev;
1296 struct drm_i915_private *dev_priv = dev->dev_private;
1297 u32 tmp = I915_READ(intel_dp->output_reg);
1298
1299 if (!(tmp & DP_PORT_EN))
1300 return false;
1301
1302 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1303 *pipe = PORT_TO_PIPE_CPT(tmp);
1304 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1305 *pipe = PORT_TO_PIPE(tmp);
1306 } else {
1307 u32 trans_sel;
1308 u32 trans_dp;
1309 int i;
1310
1311 switch (intel_dp->output_reg) {
1312 case PCH_DP_B:
1313 trans_sel = TRANS_DP_PORT_SEL_B;
1314 break;
1315 case PCH_DP_C:
1316 trans_sel = TRANS_DP_PORT_SEL_C;
1317 break;
1318 case PCH_DP_D:
1319 trans_sel = TRANS_DP_PORT_SEL_D;
1320 break;
1321 default:
1322 return true;
1323 }
1324
1325 for_each_pipe(i) {
1326 trans_dp = I915_READ(TRANS_DP_CTL(i));
1327 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1328 *pipe = i;
1329 return true;
1330 }
1331 }
1332 }
1333
1334 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
d240f20f 1335
19d8fe15
DV		 1336 return true;
1337}
1338
e8cb4558 1339static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1340{
e8cb4558 1341 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1342
1343 /* Make sure the panel is off before trying to change the mode. But also
1344 * ensure that we have vdd while we switch off the panel. */
1345 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1346 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1347 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1348 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1349
1350 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1351 if (!is_cpu_edp(intel_dp))
1352 intel_dp_link_down(intel_dp);
d240f20f
JB		 1353}
1354
2bd2ad64
DV		 1355static void intel_post_disable_dp(struct intel_encoder *encoder)
1356{
1357 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1358
3739850b
DV		 1359 if (is_cpu_edp(intel_dp)) {
1360 intel_dp_link_down(intel_dp);
2bd2ad64 1361 ironlake_edp_pll_off(intel_dp);
3739850b 1362 }
2bd2ad64
DV		 1363}
1364
e8cb4558 1365static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1366{
e8cb4558
DV		 1367 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1368 struct drm_device *dev = encoder->base.dev;
1369 struct drm_i915_private *dev_priv = dev->dev_private;
1370 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1371
0c33d8d7
DV		 1372 if (WARN_ON(dp_reg & DP_PORT_EN))
1373 return;
1374
97af61f5 1375 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1376 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
0c33d8d7
DV		 1377 intel_dp_start_link_train(intel_dp);
1378 ironlake_edp_panel_on(intel_dp);
1379 ironlake_edp_panel_vdd_off(intel_dp, true);
1380 intel_dp_complete_link_train(intel_dp);
f01eca2e 1381 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1382}
1383
2bd2ad64 1384static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1385{
2bd2ad64 1386 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0a91ca29 1387
2bd2ad64
DV		 1388 if (is_cpu_edp(intel_dp))
1389 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1390}
1391
1392/*
df0c237d
JB		 1393 * Native read with retry for link status and receiver capability reads for
1394 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1395 */
1396static bool
df0c237d
JB		 1397intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1398 uint8_t *recv, int recv_bytes)
a4fc5ed6 1399{
61da5fab
JB		 1400 int ret, i;
1401
df0c237d
JB		 1402 /*
1403 * Sinks are *supposed* to come up within 1ms from an off state,
1404 * but we're also supposed to retry 3 times per the spec.
1405 */
61da5fab 1406 for (i = 0; i < 3; i++) {
df0c237d
JB		 1407 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1408 recv_bytes);
1409 if (ret == recv_bytes)
61da5fab
JB		 1410 return true;
1411 msleep(1);
1412 }
a4fc5ed6 1413
61da5fab 1414 return false;
a4fc5ed6
KP		 1415}
1416
1417/*
1418 * Fetch AUX CH registers 0x202 - 0x207 which contain
1419 * link status information
1420 */
1421static bool
93f62dad 1422intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1423{
df0c237d
JB		 1424 return intel_dp_aux_native_read_retry(intel_dp,
1425 DP_LANE0_1_STATUS,
93f62dad 1426 link_status,
df0c237d 1427 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1428}
1429
a4fc5ed6
KP		 1430#if 0
1431static char *voltage_names[] = {
1432 "0.4V", "0.6V", "0.8V", "1.2V"
1433};
1434static char *pre_emph_names[] = {
1435 "0dB", "3.5dB", "6dB", "9.5dB"
1436};
1437static char *link_train_names[] = {
1438 "pattern 1", "pattern 2", "idle", "off"
1439};
1440#endif
1441
1442/*
1443 * These are source-specific values; current Intel hardware supports
1444 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1445 */
a4fc5ed6
KP		 1446
1447static uint8_t
1a2eb460 1448intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1449{
1a2eb460
KP		 1450 struct drm_device *dev = intel_dp->base.base.dev;
1451
1452 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1453 return DP_TRAIN_VOLTAGE_SWING_800;
1454 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1455 return DP_TRAIN_VOLTAGE_SWING_1200;
1456 else
1457 return DP_TRAIN_VOLTAGE_SWING_800;
1458}
1459
1460static uint8_t
1461intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1462{
1463 struct drm_device *dev = intel_dp->base.base.dev;
1464
d6c0d722
PZ		 1465 if (IS_HASWELL(dev)) {
1466 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1467 case DP_TRAIN_VOLTAGE_SWING_400:
1468 return DP_TRAIN_PRE_EMPHASIS_9_5;
1469 case DP_TRAIN_VOLTAGE_SWING_600:
1470 return DP_TRAIN_PRE_EMPHASIS_6;
1471 case DP_TRAIN_VOLTAGE_SWING_800:
1472 return DP_TRAIN_PRE_EMPHASIS_3_5;
1473 case DP_TRAIN_VOLTAGE_SWING_1200:
1474 default:
1475 return DP_TRAIN_PRE_EMPHASIS_0;
1476 }
1477 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1478 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1479 case DP_TRAIN_VOLTAGE_SWING_400:
1480 return DP_TRAIN_PRE_EMPHASIS_6;
1481 case DP_TRAIN_VOLTAGE_SWING_600:
1482 case DP_TRAIN_VOLTAGE_SWING_800:
1483 return DP_TRAIN_PRE_EMPHASIS_3_5;
1484 default:
1485 return DP_TRAIN_PRE_EMPHASIS_0;
1486 }
1487 } else {
1488 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1489 case DP_TRAIN_VOLTAGE_SWING_400:
1490 return DP_TRAIN_PRE_EMPHASIS_6;
1491 case DP_TRAIN_VOLTAGE_SWING_600:
1492 return DP_TRAIN_PRE_EMPHASIS_6;
1493 case DP_TRAIN_VOLTAGE_SWING_800:
1494 return DP_TRAIN_PRE_EMPHASIS_3_5;
1495 case DP_TRAIN_VOLTAGE_SWING_1200:
1496 default:
1497 return DP_TRAIN_PRE_EMPHASIS_0;
1498 }
a4fc5ed6
KP		 1499 }
1500}
1501
1502static void
93f62dad 1503intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1504{
1505 uint8_t v = 0;
1506 uint8_t p = 0;
1507 int lane;
1a2eb460
KP		 1508 uint8_t voltage_max;
1509 uint8_t preemph_max;
a4fc5ed6 1510
33a34e4e 1511 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1512 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1513 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1514
1515 if (this_v > v)
1516 v = this_v;
1517 if (this_p > p)
1518 p = this_p;
1519 }
1520
1a2eb460 1521 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1522 if (v >= voltage_max)
1523 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1524
1a2eb460
KP		 1525 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1526 if (p >= preemph_max)
1527 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1528
1529 for (lane = 0; lane < 4; lane++)
33a34e4e 1530 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1531}
1532
1533static uint32_t
93f62dad 1534intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1535{
3cf2efb1 1536 uint32_t signal_levels = 0;
a4fc5ed6 1537
3cf2efb1 1538 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1539 case DP_TRAIN_VOLTAGE_SWING_400:
1540 default:
1541 signal_levels |= DP_VOLTAGE_0_4;
1542 break;
1543 case DP_TRAIN_VOLTAGE_SWING_600:
1544 signal_levels |= DP_VOLTAGE_0_6;
1545 break;
1546 case DP_TRAIN_VOLTAGE_SWING_800:
1547 signal_levels |= DP_VOLTAGE_0_8;
1548 break;
1549 case DP_TRAIN_VOLTAGE_SWING_1200:
1550 signal_levels |= DP_VOLTAGE_1_2;
1551 break;
1552 }
3cf2efb1 1553 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1554 case DP_TRAIN_PRE_EMPHASIS_0:
1555 default:
1556 signal_levels |= DP_PRE_EMPHASIS_0;
1557 break;
1558 case DP_TRAIN_PRE_EMPHASIS_3_5:
1559 signal_levels |= DP_PRE_EMPHASIS_3_5;
1560 break;
1561 case DP_TRAIN_PRE_EMPHASIS_6:
1562 signal_levels |= DP_PRE_EMPHASIS_6;
1563 break;
1564 case DP_TRAIN_PRE_EMPHASIS_9_5:
1565 signal_levels |= DP_PRE_EMPHASIS_9_5;
1566 break;
1567 }
1568 return signal_levels;
1569}
1570
e3421a18
ZW		 1571/* Gen6's DP voltage swing and pre-emphasis control */
1572static uint32_t
1573intel_gen6_edp_signal_levels(uint8_t train_set)
1574{
3c5a62b5
YL		 1575 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1576 DP_TRAIN_PRE_EMPHASIS_MASK);
1577 switch (signal_levels) {
e3421a18 1578 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1579 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1580 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1581 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1582 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1583 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1584 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1585 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1586 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1587 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1588 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1589 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1590 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1591 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1592 default:
3c5a62b5
YL		 1593 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1594 "0x%x\n", signal_levels);
1595 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1596 }
1597}
1598
1a2eb460
KP		 1599/* Gen7's DP voltage swing and pre-emphasis control */
1600static uint32_t
1601intel_gen7_edp_signal_levels(uint8_t train_set)
1602{
1603 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1604 DP_TRAIN_PRE_EMPHASIS_MASK);
1605 switch (signal_levels) {
1606 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1607 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1608 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1609 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1610 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1611 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1612
1613 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1614 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1615 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1616 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1617
1618 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1619 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1620 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1621 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1622
1623 default:
1624 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1625 "0x%x\n", signal_levels);
1626 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1627 }
1628}
1629
d6c0d722
PZ		 1630/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1631static uint32_t
1632intel_dp_signal_levels_hsw(uint8_t train_set)
1633{
1634 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1635 DP_TRAIN_PRE_EMPHASIS_MASK);
1636 switch (signal_levels) {
1637 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1638 return DDI_BUF_EMP_400MV_0DB_HSW;
1639 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1640 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1641 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1642 return DDI_BUF_EMP_400MV_6DB_HSW;
1643 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1644 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1645
1646 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1647 return DDI_BUF_EMP_600MV_0DB_HSW;
1648 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1649 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1650 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1651 return DDI_BUF_EMP_600MV_6DB_HSW;
1652
1653 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1654 return DDI_BUF_EMP_800MV_0DB_HSW;
1655 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1656 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1657 default:
1658 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1659 "0x%x\n", signal_levels);
1660 return DDI_BUF_EMP_400MV_0DB_HSW;
1661 }
1662}
1663
a4fc5ed6 1664static bool
ea5b213a 1665intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1666 uint32_t dp_reg_value,
58e10eb9 1667 uint8_t dp_train_pat)
a4fc5ed6 1668{
4ef69c7a 1669 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1670 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1671 int ret;
d6c0d722 1672 uint32_t temp;
a4fc5ed6 1673
d6c0d722
PZ		 1674 if (IS_HASWELL(dev)) {
1675 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1676
1677 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1678 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1679 else
1680 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1681
1682 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1683 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1684 case DP_TRAINING_PATTERN_DISABLE:
1685 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1686 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1687
1688 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1689 DP_TP_STATUS_IDLE_DONE), 1))
1690 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1691
1692 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1693 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1694
1695 break;
1696 case DP_TRAINING_PATTERN_1:
1697 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1698 break;
1699 case DP_TRAINING_PATTERN_2:
1700 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1701 break;
1702 case DP_TRAINING_PATTERN_3:
1703 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1704 break;
1705 }
1706 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1707
1708 } else if (HAS_PCH_CPT(dev) &&
1709 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1710 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1711
1712 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1713 case DP_TRAINING_PATTERN_DISABLE:
1714 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1715 break;
1716 case DP_TRAINING_PATTERN_1:
1717 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1718 break;
1719 case DP_TRAINING_PATTERN_2:
1720 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1721 break;
1722 case DP_TRAINING_PATTERN_3:
1723 DRM_ERROR("DP training pattern 3 not supported\n");
1724 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1725 break;
1726 }
1727
1728 } else {
1729 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1730
1731 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1732 case DP_TRAINING_PATTERN_DISABLE:
1733 dp_reg_value |= DP_LINK_TRAIN_OFF;
1734 break;
1735 case DP_TRAINING_PATTERN_1:
1736 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1737 break;
1738 case DP_TRAINING_PATTERN_2:
1739 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1740 break;
1741 case DP_TRAINING_PATTERN_3:
1742 DRM_ERROR("DP training pattern 3 not supported\n");
1743 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1744 break;
1745 }
1746 }
1747
ea5b213a
CW		 1748 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1749 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1750
ea5b213a 1751 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1752 DP_TRAINING_PATTERN_SET,
1753 dp_train_pat);
1754
47ea7542
PZ		 1755 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1756 DP_TRAINING_PATTERN_DISABLE) {
1757 ret = intel_dp_aux_native_write(intel_dp,
1758 DP_TRAINING_LANE0_SET,
1759 intel_dp->train_set,
1760 intel_dp->lane_count);
1761 if (ret != intel_dp->lane_count)
1762 return false;
1763 }
a4fc5ed6
KP		 1764
1765 return true;
1766}
1767
33a34e4e 1768/* Enable corresponding port and start training pattern 1 */
c19b0669 1769void
33a34e4e 1770intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1771{
c19b0669
PZ		 1772 struct drm_encoder *encoder = &intel_dp->base.base;
1773 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1774 int i;
1775 uint8_t voltage;
1776 bool clock_recovery = false;
cdb0e95b 1777 int voltage_tries, loop_tries;
ea5b213a 1778 uint32_t DP = intel_dp->DP;
a4fc5ed6 1779
c19b0669
PZ		 1780 if (IS_HASWELL(dev))
1781 intel_ddi_prepare_link_retrain(encoder);
1782
3cf2efb1
CW		 1783 /* Write the link configuration data */
1784 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1785 intel_dp->link_configuration,
1786 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1787
1788 DP |= DP_PORT_EN;
1a2eb460 1789
33a34e4e 1790 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1791 voltage = 0xff;
cdb0e95b
KP		 1792 voltage_tries = 0;
1793 loop_tries = 0;
a4fc5ed6
KP		 1794 clock_recovery = false;
1795 for (;;) {
33a34e4e 1796 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1797 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1798 uint32_t signal_levels;
417e822d 1799
d6c0d722
PZ		 1800 if (IS_HASWELL(dev)) {
1801 signal_levels = intel_dp_signal_levels_hsw(
1802 intel_dp->train_set[0]);
1803 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1804 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1805 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1806 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1807 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1808 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1809 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1810 } else {
93f62dad 1811 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1812 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1813 }
d6c0d722
PZ		 1814 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1815 signal_levels);
a4fc5ed6 1816
a7c9655f 1817 /* Set training pattern 1 */
47ea7542 1818 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1819 DP_TRAINING_PATTERN_1 |
1820 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1821 break;
a4fc5ed6 1822
a7c9655f 1823 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 1824 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1825 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1826 break;
93f62dad 1827 }
a4fc5ed6 1828
01916270 1829 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 1830 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1831 clock_recovery = true;
1832 break;
1833 }
1834
1835 /* Check to see if we've tried the max voltage */
1836 for (i = 0; i < intel_dp->lane_count; i++)
1837 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1838 break;
0d710688 1839 if (i == intel_dp->lane_count && voltage_tries == 5) {
24773670 1840 if (++loop_tries == 5) {
cdb0e95b
KP		 1841 DRM_DEBUG_KMS("too many full retries, give up\n");
1842 break;
1843 }
1844 memset(intel_dp->train_set, 0, 4);
1845 voltage_tries = 0;
1846 continue;
1847 }
a4fc5ed6 1848
3cf2efb1 1849 /* Check to see if we've tried the same voltage 5 times */
24773670
CW		 1850 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
1851 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
cdb0e95b 1852 voltage_tries = 0;
24773670
CW		 1853 } else
1854 ++voltage_tries;
a4fc5ed6 1855
3cf2efb1 1856 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1857 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1858 }
1859
33a34e4e
JB		 1860 intel_dp->DP = DP;
1861}
1862
c19b0669 1863void
33a34e4e
JB		 1864intel_dp_complete_link_train(struct intel_dp *intel_dp)
1865{
4ef69c7a 1866 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e 1867 bool channel_eq = false;
37f80975 1868 int tries, cr_tries;
33a34e4e
JB		 1869 uint32_t DP = intel_dp->DP;
1870
a4fc5ed6
KP		 1871 /* channel equalization */
1872 tries = 0;
37f80975 1873 cr_tries = 0;
a4fc5ed6
KP		 1874 channel_eq = false;
1875 for (;;) {
33a34e4e 1876 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1877 uint32_t signal_levels;
93f62dad 1878 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1879
37f80975
JB		 1880 if (cr_tries > 5) {
1881 DRM_ERROR("failed to train DP, aborting\n");
1882 intel_dp_link_down(intel_dp);
1883 break;
1884 }
1885
d6c0d722
PZ		 1886 if (IS_HASWELL(dev)) {
1887 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1888 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1889 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1890 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1891 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1892 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1893 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1894 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1895 } else {
93f62dad 1896 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1897 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1898 }
1899
a4fc5ed6 1900 /* channel eq pattern */
47ea7542 1901 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1902 DP_TRAINING_PATTERN_2 |
1903 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1904 break;
1905
a7c9655f 1906 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 1907 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1908 break;
a4fc5ed6 1909
37f80975 1910 /* Make sure clock is still ok */
01916270 1911 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1912 intel_dp_start_link_train(intel_dp);
1913 cr_tries++;
1914 continue;
1915 }
1916
1ffdff13 1917 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 1918 channel_eq = true;
1919 break;
1920 }
a4fc5ed6 1921
37f80975
JB		 1922 /* Try 5 times, then try clock recovery if that fails */
1923 if (tries > 5) {
1924 intel_dp_link_down(intel_dp);
1925 intel_dp_start_link_train(intel_dp);
1926 tries = 0;
1927 cr_tries++;
1928 continue;
1929 }
a4fc5ed6 1930
3cf2efb1 1931 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1932 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1933 ++tries;
869184a6 1934 }
3cf2efb1 1935
d6c0d722
PZ		 1936 if (channel_eq)
1937 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1938
47ea7542 1939 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 1940}
1941
1942static void
ea5b213a 1943intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1944{
4ef69c7a 1945 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1946 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1947 uint32_t DP = intel_dp->DP;
a4fc5ed6 1948
c19b0669
PZ		 1949 /*
1950 * DDI code has a strict mode set sequence and we should try to respect
1951 * it, otherwise we might hang the machine in many different ways. So we
1952 * really should be disabling the port only on a complete crtc_disable
1953 * sequence. This function is just called under two conditions on DDI
1954 * code:
1955 * - Link train failed while doing crtc_enable, and on this case we
1956 * really should respect the mode set sequence and wait for a
1957 * crtc_disable.
1958 * - Someone turned the monitor off and intel_dp_check_link_status
1959 * called us. We don't need to disable the whole port on this case, so
1960 * when someone turns the monitor on again,
1961 * intel_ddi_prepare_link_retrain will take care of redoing the link
1962 * train.
1963 */
1964 if (IS_HASWELL(dev))
1965 return;
1966
0c33d8d7 1967 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 1968 return;
1969
28c97730 1970 DRM_DEBUG_KMS("\n");
32f9d658 1971
1a2eb460 1972 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1973 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1974 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1975 } else {
1976 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1977 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1978 }
fe255d00 1979 POSTING_READ(intel_dp->output_reg);
5eb08b69 1980
fe255d00 1981 msleep(17);
5eb08b69 1982
493a7081 1983 if (HAS_PCH_IBX(dev) &&
1b39d6f3 1984 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 1985 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1986
5bddd17f
EA		 1987 /* Hardware workaround: leaving our transcoder select
1988 * set to transcoder B while it's off will prevent the
1989 * corresponding HDMI output on transcoder A.
1990 *
1991 * Combine this with another hardware workaround:
1992 * transcoder select bit can only be cleared while the
1993 * port is enabled.
1994 */
1995 DP &= ~DP_PIPEB_SELECT;
1996 I915_WRITE(intel_dp->output_reg, DP);
1997
1998 /* Changes to enable or select take place the vblank
1999 * after being written.
2000 */
31acbcc4
CW		 2001 if (crtc == NULL) {
2002 /* We can arrive here never having been attached
2003 * to a CRTC, for instance, due to inheriting
2004 * random state from the BIOS.
2005 *
2006 * If the pipe is not running, play safe and
2007 * wait for the clocks to stabilise before
2008 * continuing.
2009 */
2010 POSTING_READ(intel_dp->output_reg);
2011 msleep(50);
2012 } else
2013 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 2014 }
2015
832afda6 2016 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2017 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2018 POSTING_READ(intel_dp->output_reg);
f01eca2e 2019 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2020}
2021
26d61aad
KP		 2022static bool
2023intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2024{
92fd8fd1 2025 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
b091cd92
AJ		 2026 sizeof(intel_dp->dpcd)) == 0)
2027 return false; /* aux transfer failed */
92fd8fd1 2028
b091cd92
AJ		 2029 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2030 return false; /* DPCD not present */
2031
2032 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2033 DP_DWN_STRM_PORT_PRESENT))
2034 return true; /* native DP sink */
2035
2036 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2037 return true; /* no per-port downstream info */
2038
2039 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2040 intel_dp->downstream_ports,
2041 DP_MAX_DOWNSTREAM_PORTS) == 0)
2042 return false; /* downstream port status fetch failed */
2043
2044 return true;
92fd8fd1
KP		 2045}
2046
0d198328
AJ		 2047static void
2048intel_dp_probe_oui(struct intel_dp *intel_dp)
2049{
2050 u8 buf[3];
2051
2052 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2053 return;
2054
351cfc34
DV		 2055 ironlake_edp_panel_vdd_on(intel_dp);
2056
0d198328
AJ		 2057 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2058 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2059 buf[0], buf[1], buf[2]);
2060
2061 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2062 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2063 buf[0], buf[1], buf[2]);
351cfc34
DV		 2064
2065 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2066}
2067
a60f0e38
JB		 2068static bool
2069intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2070{
2071 int ret;
2072
2073 ret = intel_dp_aux_native_read_retry(intel_dp,
2074 DP_DEVICE_SERVICE_IRQ_VECTOR,
2075 sink_irq_vector, 1);
2076 if (!ret)
2077 return false;
2078
2079 return true;
2080}
2081
2082static void
2083intel_dp_handle_test_request(struct intel_dp *intel_dp)
2084{
2085 /* NAK by default */
9324cf7f 2086 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2087}
2088
a4fc5ed6
KP		 2089/*
2090 * According to DP spec
2091 * 5.1.2:
2092 * 1. Read DPCD
2093 * 2. Configure link according to Receiver Capabilities
2094 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2095 * 4. Check link status on receipt of hot-plug interrupt
2096 */
2097
2098static void
ea5b213a 2099intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2100{
a60f0e38 2101 u8 sink_irq_vector;
93f62dad 2102 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2103
24e804ba 2104 if (!intel_dp->base.connectors_active)
d2b996ac 2105 return;
59cd09e1 2106
24e804ba 2107 if (WARN_ON(!intel_dp->base.base.crtc))
a4fc5ed6
KP		 2108 return;
2109
92fd8fd1 2110 /* Try to read receiver status if the link appears to be up */
93f62dad 2111 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2112 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2113 return;
2114 }
2115
92fd8fd1 2116 /* Now read the DPCD to see if it's actually running */
26d61aad 2117 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2118 intel_dp_link_down(intel_dp);
2119 return;
2120 }
2121
a60f0e38
JB		 2122 /* Try to read the source of the interrupt */
2123 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2124 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2125 /* Clear interrupt source */
2126 intel_dp_aux_native_write_1(intel_dp,
2127 DP_DEVICE_SERVICE_IRQ_VECTOR,
2128 sink_irq_vector);
2129
2130 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2131 intel_dp_handle_test_request(intel_dp);
2132 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2133 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2134 }
2135
1ffdff13 2136 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1
KP		 2137 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2138 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2139 intel_dp_start_link_train(intel_dp);
2140 intel_dp_complete_link_train(intel_dp);
2141 }
a4fc5ed6 2142}
a4fc5ed6 2143
07d3dc18 2144/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2145static enum drm_connector_status
26d61aad 2146intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2147{
07d3dc18
AJ		 2148 uint8_t *dpcd = intel_dp->dpcd;
2149 bool hpd;
2150 uint8_t type;
2151
2152 if (!intel_dp_get_dpcd(intel_dp))
2153 return connector_status_disconnected;
2154
2155 /* if there's no downstream port, we're done */
2156 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2157 return connector_status_connected;
2158
2159 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2160 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2161 if (hpd) {
da131a46 2162 uint8_t reg;
07d3dc18 2163 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
da131a46 2164 &reg, 1))
07d3dc18 2165 return connector_status_unknown;
da131a46
AJ		 2166 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2167 : connector_status_disconnected;
07d3dc18
AJ		 2168 }
2169
2170 /* If no HPD, poke DDC gently */
2171 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2172 return connector_status_connected;
07d3dc18
AJ		 2173
2174 /* Well we tried, say unknown for unreliable port types */
2175 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2176 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2177 return connector_status_unknown;
2178
2179 /* Anything else is out of spec, warn and ignore */
2180 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2181 return connector_status_disconnected;
71ba9000
AJ		 2182}
2183
5eb08b69 2184static enum drm_connector_status
a9756bb5 2185ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2186{
5eb08b69
ZW		 2187 enum drm_connector_status status;
2188
fe16d949
CW		 2189 /* Can't disconnect eDP, but you can close the lid... */
2190 if (is_edp(intel_dp)) {
2191 status = intel_panel_detect(intel_dp->base.base.dev);
2192 if (status == connector_status_unknown)
2193 status = connector_status_connected;
2194 return status;
2195 }
01cb9ea6 2196
26d61aad 2197 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2198}
2199
a4fc5ed6 2200static enum drm_connector_status
a9756bb5 2201g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2202{
4ef69c7a 2203 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2204 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2205 uint32_t bit;
5eb08b69 2206
ea5b213a 2207 switch (intel_dp->output_reg) {
a4fc5ed6 2208 case DP_B:
10f76a38 2209 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2210 break;
2211 case DP_C:
10f76a38 2212 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2213 break;
2214 case DP_D:
10f76a38 2215 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2216 break;
2217 default:
2218 return connector_status_unknown;
2219 }
2220
10f76a38 2221 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2222 return connector_status_disconnected;
2223
26d61aad 2224 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2225}
2226
8c241fef
KP		 2227static struct edid *
2228intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2229{
9cd300e0 2230 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2231
9cd300e0
JN		 2232 /* use cached edid if we have one */
2233 if (intel_connector->edid) {
2234 struct edid *edid;
2235 int size;
2236
2237 /* invalid edid */
2238 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2239 return NULL;
2240
9cd300e0 2241 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2242 edid = kmalloc(size, GFP_KERNEL);
2243 if (!edid)
2244 return NULL;
2245
9cd300e0 2246 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2247 return edid;
2248 }
8c241fef 2249
9cd300e0 2250 return drm_get_edid(connector, adapter);
8c241fef
KP		 2251}
2252
2253static int
2254intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2255{
9cd300e0 2256 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2257
9cd300e0
JN		 2258 /* use cached edid if we have one */
2259 if (intel_connector->edid) {
2260 /* invalid edid */
2261 if (IS_ERR(intel_connector->edid))
2262 return 0;
2263
2264 return intel_connector_update_modes(connector,
2265 intel_connector->edid);
d6f24d0f
JB		 2266 }
2267
9cd300e0 2268 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2269}
2270
2271
a9756bb5
ZW		 2272/**
2273 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2274 *
2275 * \return true if DP port is connected.
2276 * \return false if DP port is disconnected.
2277 */
2278static enum drm_connector_status
2279intel_dp_detect(struct drm_connector *connector, bool force)
2280{
2281 struct intel_dp *intel_dp = intel_attached_dp(connector);
2282 struct drm_device *dev = intel_dp->base.base.dev;
2283 enum drm_connector_status status;
2284 struct edid *edid = NULL;
2285
2286 intel_dp->has_audio = false;
2287
2288 if (HAS_PCH_SPLIT(dev))
2289 status = ironlake_dp_detect(intel_dp);
2290 else
2291 status = g4x_dp_detect(intel_dp);
1b9be9d0 2292
ac66ae83
AJ		 2293 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2294 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2295 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2296 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 2297
a9756bb5
ZW		 2298 if (status != connector_status_connected)
2299 return status;
2300
0d198328
AJ		 2301 intel_dp_probe_oui(intel_dp);
2302
c3e5f67b
DV		 2303 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2304 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2305 } else {
8c241fef 2306 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2307 if (edid) {
2308 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2309 kfree(edid);
2310 }
a9756bb5
ZW		 2311 }
2312
2313 return connector_status_connected;
a4fc5ed6
KP		 2314}
2315
2316static int intel_dp_get_modes(struct drm_connector *connector)
2317{
df0e9248 2318 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2319 struct intel_connector *intel_connector = to_intel_connector(connector);
4ef69c7a 2320 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658 2321 int ret;
a4fc5ed6
KP		 2322
2323 /* We should parse the EDID data and find out if it has an audio sink
2324 */
2325
8c241fef 2326 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2327 if (ret)
32f9d658
ZW		 2328 return ret;
2329
f8779fda 2330 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2331 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2332 struct drm_display_mode *mode;
dd06f90e
JN		 2333 mode = drm_mode_duplicate(dev,
2334 intel_connector->panel.fixed_mode);
f8779fda 2335 if (mode) {
32f9d658
ZW		 2336 drm_mode_probed_add(connector, mode);
2337 return 1;
2338 }
2339 }
2340 return 0;
a4fc5ed6
KP		 2341}
2342
1aad7ac0
CW		 2343static bool
2344intel_dp_detect_audio(struct drm_connector *connector)
2345{
2346 struct intel_dp *intel_dp = intel_attached_dp(connector);
2347 struct edid *edid;
2348 bool has_audio = false;
2349
8c241fef 2350 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2351 if (edid) {
2352 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2353 kfree(edid);
2354 }
2355
2356 return has_audio;
2357}
2358
f684960e
CW		 2359static int
2360intel_dp_set_property(struct drm_connector *connector,
2361 struct drm_property *property,
2362 uint64_t val)
2363{
e953fd7b 2364 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2365 struct intel_dp *intel_dp = intel_attached_dp(connector);
2366 int ret;
2367
2368 ret = drm_connector_property_set_value(connector, property, val);
2369 if (ret)
2370 return ret;
2371
3f43c48d 2372 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2373 int i = val;
2374 bool has_audio;
2375
2376 if (i == intel_dp->force_audio)
f684960e
CW		 2377 return 0;
2378
1aad7ac0 2379 intel_dp->force_audio = i;
f684960e 2380
c3e5f67b 2381 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2382 has_audio = intel_dp_detect_audio(connector);
2383 else
c3e5f67b 2384 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2385
2386 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2387 return 0;
2388
1aad7ac0 2389 intel_dp->has_audio = has_audio;
f684960e
CW		 2390 goto done;
2391 }
2392
e953fd7b
CW		 2393 if (property == dev_priv->broadcast_rgb_property) {
2394 if (val == !!intel_dp->color_range)
2395 return 0;
2396
2397 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2398 goto done;
2399 }
2400
f684960e
CW		 2401 return -EINVAL;
2402
2403done:
2404 if (intel_dp->base.base.crtc) {
2405 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a6778b3c
DV		 2406 intel_set_mode(crtc, &crtc->mode,
2407 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2408 }
2409
2410 return 0;
2411}
2412
a4fc5ed6 2413static void
0206e353 2414intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2415{
aaa6fd2a 2416 struct drm_device *dev = connector->dev;
be3cd5e3 2417 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2418 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2419
9cd300e0
JN		 2420 if (!IS_ERR_OR_NULL(intel_connector->edid))
2421 kfree(intel_connector->edid);
2422
1d508706 2423 if (is_edp(intel_dp)) {
aaa6fd2a 2424 intel_panel_destroy_backlight(dev);
1d508706
JN		 2425 intel_panel_fini(&intel_connector->panel);
2426 }
aaa6fd2a 2427
a4fc5ed6
KP		 2428 drm_sysfs_connector_remove(connector);
2429 drm_connector_cleanup(connector);
55f78c43 2430 kfree(connector);
a4fc5ed6
KP		 2431}
2432
24d05927
DV		 2433static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2434{
2435 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2436
2437 i2c_del_adapter(&intel_dp->adapter);
2438 drm_encoder_cleanup(encoder);
bd943159
KP		 2439 if (is_edp(intel_dp)) {
2440 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2441 ironlake_panel_vdd_off_sync(intel_dp);
2442 }
24d05927
DV		 2443 kfree(intel_dp);
2444}
2445
a4fc5ed6 2446static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2447 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2448 .mode_set = intel_dp_mode_set,
1f703855 2449 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2450};
2451
a7902ac5
PZ		 2452static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw = {
2453 .mode_fixup = intel_dp_mode_fixup,
2454 .mode_set = intel_ddi_mode_set,
2455 .disable = intel_encoder_noop,
2456};
2457
a4fc5ed6 2458static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2459 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2460 .detect = intel_dp_detect,
2461 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2462 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2463 .destroy = intel_dp_destroy,
2464};
2465
2466static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2467 .get_modes = intel_dp_get_modes,
2468 .mode_valid = intel_dp_mode_valid,
df0e9248 2469 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2470};
2471
a4fc5ed6 2472static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2473 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2474};
2475
995b6762 2476static void
21d40d37 2477intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2478{
ea5b213a 2479 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2480
885a5014 2481 intel_dp_check_link_status(intel_dp);
c8110e52 2482}
6207937d 2483
e3421a18
ZW		 2484/* Return which DP Port should be selected for Transcoder DP control */
2485int
0206e353 2486intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2487{
2488 struct drm_device *dev = crtc->dev;
6c2b7c12 2489 struct intel_encoder *encoder;
e3421a18 2490
6c2b7c12
DV		 2491 for_each_encoder_on_crtc(dev, crtc, encoder) {
2492 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
e3421a18 2493
417e822d
KP		 2494 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2495 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2496 return intel_dp->output_reg;
e3421a18 2497 }
ea5b213a 2498
e3421a18
ZW		 2499 return -1;
2500}
2501
36e83a18 2502/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2503bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2504{
2505 struct drm_i915_private *dev_priv = dev->dev_private;
2506 struct child_device_config *p_child;
2507 int i;
2508
2509 if (!dev_priv->child_dev_num)
2510 return false;
2511
2512 for (i = 0; i < dev_priv->child_dev_num; i++) {
2513 p_child = dev_priv->child_dev + i;
2514
2515 if (p_child->dvo_port == PORT_IDPD &&
2516 p_child->device_type == DEVICE_TYPE_eDP)
2517 return true;
2518 }
2519 return false;
2520}
2521
f684960e
CW		 2522static void
2523intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2524{
3f43c48d 2525 intel_attach_force_audio_property(connector);
e953fd7b 2526 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2527}
2528
67a54566
DV		 2529static void
2530intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2531 struct intel_dp *intel_dp)
2532{
2533 struct drm_i915_private *dev_priv = dev->dev_private;
2534 struct edp_power_seq cur, vbt, spec, final;
2535 u32 pp_on, pp_off, pp_div, pp;
2536
2537 /* Workaround: Need to write PP_CONTROL with the unlock key as
2538 * the very first thing. */
2539 pp = ironlake_get_pp_control(dev_priv);
2540 I915_WRITE(PCH_PP_CONTROL, pp);
2541
2542 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2543 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2544 pp_div = I915_READ(PCH_PP_DIVISOR);
2545
2546 /* Pull timing values out of registers */
2547 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2548 PANEL_POWER_UP_DELAY_SHIFT;
2549
2550 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2551 PANEL_LIGHT_ON_DELAY_SHIFT;
2552
2553 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2554 PANEL_LIGHT_OFF_DELAY_SHIFT;
2555
2556 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2557 PANEL_POWER_DOWN_DELAY_SHIFT;
2558
2559 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2560 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2561
2562 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2563 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2564
2565 vbt = dev_priv->edp.pps;
2566
2567 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2568 * our hw here, which are all in 100usec. */
2569 spec.t1_t3 = 210 * 10;
2570 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2571 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2572 spec.t10 = 500 * 10;
2573 /* This one is special and actually in units of 100ms, but zero
2574 * based in the hw (so we need to add 100 ms). But the sw vbt
2575 * table multiplies it with 1000 to make it in units of 100usec,
2576 * too. */
2577 spec.t11_t12 = (510 + 100) * 10;
2578
2579 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2580 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2581
2582 /* Use the max of the register settings and vbt. If both are
2583 * unset, fall back to the spec limits. */
2584#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2585 spec.field : \
2586 max(cur.field, vbt.field))
2587 assign_final(t1_t3);
2588 assign_final(t8);
2589 assign_final(t9);
2590 assign_final(t10);
2591 assign_final(t11_t12);
2592#undef assign_final
2593
2594#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2595 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2596 intel_dp->backlight_on_delay = get_delay(t8);
2597 intel_dp->backlight_off_delay = get_delay(t9);
2598 intel_dp->panel_power_down_delay = get_delay(t10);
2599 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2600#undef get_delay
2601
2602 /* And finally store the new values in the power sequencer. */
2603 pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2604 (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2605 pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2606 (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2607 /* Compute the divisor for the pp clock, simply match the Bspec
2608 * formula. */
2609 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2610 << PP_REFERENCE_DIVIDER_SHIFT;
2611 pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
2612 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2613
2614 /* Haswell doesn't have any port selection bits for the panel
2615 * power sequencer any more. */
2616 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2617 if (is_cpu_edp(intel_dp))
2618 pp_on |= PANEL_POWER_PORT_DP_A;
2619 else
2620 pp_on |= PANEL_POWER_PORT_DP_D;
2621 }
2622
2623 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2624 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2625 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2626
2627
2628 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2629 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2630 intel_dp->panel_power_cycle_delay);
2631
2632 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2633 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2634
2635 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2636 I915_READ(PCH_PP_ON_DELAYS),
2637 I915_READ(PCH_PP_OFF_DELAYS),
2638 I915_READ(PCH_PP_DIVISOR));
2639}
2640
a4fc5ed6 2641void
ab9d7c30 2642intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
a4fc5ed6
KP		 2643{
2644 struct drm_i915_private *dev_priv = dev->dev_private;
2645 struct drm_connector *connector;
ea5b213a 2646 struct intel_dp *intel_dp;
21d40d37 2647 struct intel_encoder *intel_encoder;
55f78c43 2648 struct intel_connector *intel_connector;
f8779fda 2649 struct drm_display_mode *fixed_mode = NULL;
5eb08b69 2650 const char *name = NULL;
b329530c 2651 int type;
a4fc5ed6 2652
ea5b213a
CW		 2653 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2654 if (!intel_dp)
a4fc5ed6
KP		 2655 return;
2656
3d3dc149 2657 intel_dp->output_reg = output_reg;
ab9d7c30 2658 intel_dp->port = port;
0767935e
DV		 2659 /* Preserve the current hw state. */
2660 intel_dp->DP = I915_READ(intel_dp->output_reg);
3d3dc149 2661
55f78c43
ZW		 2662 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2663 if (!intel_connector) {
ea5b213a 2664 kfree(intel_dp);
55f78c43
ZW		 2665 return;
2666 }
ea5b213a 2667 intel_encoder = &intel_dp->base;
dd06f90e 2668 intel_dp->attached_connector = intel_connector;
55f78c43 2669
ea5b213a 2670 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2671 if (intel_dpd_is_edp(dev))
ea5b213a 2672 intel_dp->is_pch_edp = true;
b329530c 2673
19c03924
GB		 2674 /*
2675 * FIXME : We need to initialize built-in panels before external panels.
2676 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2677 */
2678 if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2679 type = DRM_MODE_CONNECTOR_eDP;
2680 intel_encoder->type = INTEL_OUTPUT_EDP;
2681 } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2682 type = DRM_MODE_CONNECTOR_eDP;
2683 intel_encoder->type = INTEL_OUTPUT_EDP;
2684 } else {
2685 type = DRM_MODE_CONNECTOR_DisplayPort;
2686 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2687 }
2688
55f78c43 2689 connector = &intel_connector->base;
b329530c 2690 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2691 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2692
eb1f8e4f
DA		 2693 connector->polled = DRM_CONNECTOR_POLL_HPD;
2694
66a9278e 2695 intel_encoder->cloneable = false;
f8aed700 2696
66a9278e
DV		 2697 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2698 ironlake_panel_vdd_work);
6251ec0a 2699
27f8227b 2700 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2701
a4fc5ed6
KP		 2702 connector->interlace_allowed = true;
2703 connector->doublescan_allowed = 0;
2704
4ef69c7a 2705 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2706 DRM_MODE_ENCODER_TMDS);
a7902ac5
PZ		 2707
2708 if (IS_HASWELL(dev))
2709 drm_encoder_helper_add(&intel_encoder->base,
2710 &intel_dp_helper_funcs_hsw);
2711 else
2712 drm_encoder_helper_add(&intel_encoder->base,
2713 &intel_dp_helper_funcs);
a4fc5ed6 2714
df0e9248 2715 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2716 drm_sysfs_connector_add(connector);
2717
a7902ac5
PZ		 2718 if (IS_HASWELL(dev)) {
2719 intel_encoder->enable = intel_enable_ddi;
2720 intel_encoder->pre_enable = intel_ddi_pre_enable;
2721 intel_encoder->disable = intel_disable_ddi;
2722 intel_encoder->post_disable = intel_ddi_post_disable;
2723 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2724 } else {
2725 intel_encoder->enable = intel_enable_dp;
2726 intel_encoder->pre_enable = intel_pre_enable_dp;
2727 intel_encoder->disable = intel_disable_dp;
2728 intel_encoder->post_disable = intel_post_disable_dp;
2729 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2730 }
19d8fe15 2731 intel_connector->get_hw_state = intel_connector_get_hw_state;
e8cb4558 2732
a4fc5ed6 2733 /* Set up the DDC bus. */
ab9d7c30
PZ		 2734 switch (port) {
2735 case PORT_A:
2736 name = "DPDDC-A";
2737 break;
2738 case PORT_B:
2739 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2740 name = "DPDDC-B";
2741 break;
2742 case PORT_C:
2743 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2744 name = "DPDDC-C";
2745 break;
2746 case PORT_D:
2747 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2748 name = "DPDDC-D";
2749 break;
2750 default:
2751 WARN(1, "Invalid port %c\n", port_name(port));
2752 break;
5eb08b69
ZW		 2753 }
2754
67a54566
DV		 2755 if (is_edp(intel_dp))
2756 intel_dp_init_panel_power_sequencer(dev, intel_dp);
c1f05264
DA		 2757
2758 intel_dp_i2c_init(intel_dp, intel_connector, name);
2759
67a54566 2760 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 2761 if (is_edp(intel_dp)) {
2762 bool ret;
f8779fda 2763 struct drm_display_mode *scan;
c1f05264 2764 struct edid *edid;
5d613501
JB		 2765
2766 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2767 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2768 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2769
59f3e272 2770 if (ret) {
7183dc29
JB		 2771 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2772 dev_priv->no_aux_handshake =
2773 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2774 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2775 } else {
3d3dc149 2776 /* if this fails, presume the device is a ghost */
48898b03 2777 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2778 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2779 intel_dp_destroy(&intel_connector->base);
3d3dc149 2780 return;
89667383 2781 }
89667383 2782
d6f24d0f
JB		 2783 ironlake_edp_panel_vdd_on(intel_dp);
2784 edid = drm_get_edid(connector, &intel_dp->adapter);
2785 if (edid) {
9cd300e0
JN		 2786 if (drm_add_edid_modes(connector, edid)) {
2787 drm_mode_connector_update_edid_property(connector, edid);
2788 drm_edid_to_eld(connector, edid);
2789 } else {
2790 kfree(edid);
2791 edid = ERR_PTR(-EINVAL);
2792 }
2793 } else {
2794 edid = ERR_PTR(-ENOENT);
d6f24d0f 2795 }
9cd300e0 2796 intel_connector->edid = edid;
f8779fda
JN		 2797
2798 /* prefer fixed mode from EDID if available */
2799 list_for_each_entry(scan, &connector->probed_modes, head) {
2800 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2801 fixed_mode = drm_mode_duplicate(dev, scan);
2802 break;
2803 }
2804 }
2805
2806 /* fallback to VBT if available for eDP */
2807 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2808 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2809 if (fixed_mode)
2810 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2811 }
f8779fda 2812
d6f24d0f
JB		 2813 ironlake_edp_panel_vdd_off(intel_dp, false);
2814 }
552fb0b7 2815
21d40d37 2816 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2817
1d508706 2818 if (is_edp(intel_dp)) {
dd06f90e 2819 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 2820 intel_panel_setup_backlight(connector);
1d508706 2821 }
32f9d658 2822
f684960e
CW		 2823 intel_dp_add_properties(intel_dp, connector);
2824
a4fc5ed6
KP		 2825 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2826 * 0xd. Failure to do so will result in spurious interrupts being
2827 * generated on the port when a cable is not attached.
2828 */
2829 if (IS_G4X(dev) && !IS_GM45(dev)) {
2830 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2831 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2832 }
2833}
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