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drm/i915/bdw: Let the memory controller do all the swizzling
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
293static enum pipe
294vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
298 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum port port = intel_dig_port->port;
301 enum pipe pipe;
302
303 /* modeset should have pipe */
304 if (crtc)
305 return to_intel_crtc(crtc)->pipe;
306
307 /* init time, try to find a pipe with this port selected */
308 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
309 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
310 PANEL_PORT_SELECT_MASK;
ad933b56 311 if (port_sel == PANEL_PORT_SELECT_VLV(port))
bf13e81b
JN		 312 return pipe;
313 }
314
315 /* shrug */
316 return PIPE_A;
317}
318
319static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
322
323 if (HAS_PCH_SPLIT(dev))
324 return PCH_PP_CONTROL;
325 else
326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
327}
328
329static u32 _pp_stat_reg(struct intel_dp *intel_dp)
330{
331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
332
333 if (HAS_PCH_SPLIT(dev))
334 return PCH_PP_STATUS;
335 else
336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
337}
338
01527b31
CT		 339/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
340 This function only applicable when panel PM state is not to be tracked */
341static int edp_notify_handler(struct notifier_block *this, unsigned long code,
342 void *unused)
343{
344 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
345 edp_notifier);
346 struct drm_device *dev = intel_dp_to_dev(intel_dp);
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 u32 pp_div;
349 u32 pp_ctrl_reg, pp_div_reg;
350 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
351
352 if (!is_edp(intel_dp) || code != SYS_RESTART)
353 return 0;
354
355 if (IS_VALLEYVIEW(dev)) {
356 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
357 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
358 pp_div = I915_READ(pp_div_reg);
359 pp_div &= PP_REFERENCE_DIVIDER_MASK;
360
361 /* 0x1F write to PP_DIV_REG sets max cycle delay */
362 I915_WRITE(pp_div_reg, pp_div | 0x1F);
363 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
364 msleep(intel_dp->panel_power_cycle_delay);
365 }
366
367 return 0;
368}
369
4be73780 370static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 371{
30add22d 372 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 373 struct drm_i915_private *dev_priv = dev->dev_private;
374
bf13e81b 375 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 376}
377
4be73780 378static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 379{
30add22d 380 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 381 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 382 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
383 struct intel_encoder *intel_encoder = &intel_dig_port->base;
384 enum intel_display_power_domain power_domain;
ebf33b18 385
bb4932c4
ID		 386 power_domain = intel_display_port_power_domain(intel_encoder);
387 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 388 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 389}
390
9b984dae
KP		 391static void
392intel_dp_check_edp(struct intel_dp *intel_dp)
393{
30add22d 394 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 395 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 396
9b984dae
KP		 397 if (!is_edp(intel_dp))
398 return;
453c5420 399
4be73780 400 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 401 WARN(1, "eDP powered off while attempting aux channel communication.\n");
402 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 403 I915_READ(_pp_stat_reg(intel_dp)),
404 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 405 }
406}
407
9ee32fea
DV		 408static uint32_t
409intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
410{
411 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
412 struct drm_device *dev = intel_dig_port->base.base.dev;
413 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 414 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 415 uint32_t status;
416 bool done;
417
ef04f00d 418#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 419 if (has_aux_irq)
b18ac466 420 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 421 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 422 else
423 done = wait_for_atomic(C, 10) == 0;
424 if (!done)
425 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
426 has_aux_irq);
427#undef C
428
429 return status;
430}
431
ec5b01dd 432static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 433{
174edf1f
PZ		 434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
435 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 436
ec5b01dd
DL		 437 /*
438 * The clock divider is based off the hrawclk, and would like to run at
439 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 440 */
ec5b01dd
DL		 441 return index ? 0 : intel_hrawclk(dev) / 2;
442}
443
444static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
445{
446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
447 struct drm_device *dev = intel_dig_port->base.base.dev;
448
449 if (index)
450 return 0;
451
452 if (intel_dig_port->port == PORT_A) {
453 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 454 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 455 else
b84a1cf8 456 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 457 } else {
458 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
459 }
460}
461
462static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
463{
464 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
465 struct drm_device *dev = intel_dig_port->base.base.dev;
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 if (intel_dig_port->port == PORT_A) {
469 if (index)
470 return 0;
471 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 472 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
473 /* Workaround for non-ULT HSW */
bc86625a
CW		 474 switch (index) {
475 case 0: return 63;
476 case 1: return 72;
477 default: return 0;
478 }
ec5b01dd 479 } else {
bc86625a 480 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 481 }
b84a1cf8
RV		 482}
483
ec5b01dd
DL		 484static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
485{
486 return index ? 0 : 100;
487}
488
5ed12a19
DL		 489static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
490 bool has_aux_irq,
491 int send_bytes,
492 uint32_t aux_clock_divider)
493{
494 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
495 struct drm_device *dev = intel_dig_port->base.base.dev;
496 uint32_t precharge, timeout;
497
498 if (IS_GEN6(dev))
499 precharge = 3;
500 else
501 precharge = 5;
502
503 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
504 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
505 else
506 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
507
508 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 509 DP_AUX_CH_CTL_DONE |
5ed12a19 510 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 511 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 512 timeout |
788d4433 513 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 514 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
515 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 516 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 517}
518
b84a1cf8
RV		 519static int
520intel_dp_aux_ch(struct intel_dp *intel_dp,
521 uint8_t *send, int send_bytes,
522 uint8_t *recv, int recv_size)
523{
524 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
525 struct drm_device *dev = intel_dig_port->base.base.dev;
526 struct drm_i915_private *dev_priv = dev->dev_private;
527 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
528 uint32_t ch_data = ch_ctl + 4;
bc86625a 529 uint32_t aux_clock_divider;
b84a1cf8
RV		 530 int i, ret, recv_bytes;
531 uint32_t status;
5ed12a19 532 int try, clock = 0;
4e6b788c 533 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 534 bool vdd;
535
72c3500a
VS		 536 /*
537 * We will be called with VDD already enabled for dpcd/edid/oui reads.
538 * In such cases we want to leave VDD enabled and it's up to upper layers
539 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
540 * ourselves.
541 */
1e0560e0 542 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 543
544 /* dp aux is extremely sensitive to irq latency, hence request the
545 * lowest possible wakeup latency and so prevent the cpu from going into
546 * deep sleep states.
547 */
548 pm_qos_update_request(&dev_priv->pm_qos, 0);
549
550 intel_dp_check_edp(intel_dp);
5eb08b69 551
c67a470b
PZ		 552 intel_aux_display_runtime_get(dev_priv);
553
11bee43e
JB		 554 /* Try to wait for any previous AUX channel activity */
555 for (try = 0; try < 3; try++) {
ef04f00d 556 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 557 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
558 break;
559 msleep(1);
560 }
561
562 if (try == 3) {
563 WARN(1, "dp_aux_ch not started status 0x%08x\n",
564 I915_READ(ch_ctl));
9ee32fea
DV		 565 ret = -EBUSY;
566 goto out;
4f7f7b7e
CW		 567 }
568
46a5ae9f
PZ		 569 /* Only 5 data registers! */
570 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
571 ret = -E2BIG;
572 goto out;
573 }
574
ec5b01dd 575 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 576 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
577 has_aux_irq,
578 send_bytes,
579 aux_clock_divider);
5ed12a19 580
bc86625a
CW		 581 /* Must try at least 3 times according to DP spec */
582 for (try = 0; try < 5; try++) {
583 /* Load the send data into the aux channel data registers */
584 for (i = 0; i < send_bytes; i += 4)
585 I915_WRITE(ch_data + i,
586 pack_aux(send + i, send_bytes - i));
587
588 /* Send the command and wait for it to complete */
5ed12a19 589 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 590
591 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
592
593 /* Clear done status and any errors */
594 I915_WRITE(ch_ctl,
595 status |
596 DP_AUX_CH_CTL_DONE |
597 DP_AUX_CH_CTL_TIME_OUT_ERROR |
598 DP_AUX_CH_CTL_RECEIVE_ERROR);
599
600 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
601 DP_AUX_CH_CTL_RECEIVE_ERROR))
602 continue;
603 if (status & DP_AUX_CH_CTL_DONE)
604 break;
605 }
4f7f7b7e 606 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 607 break;
608 }
609
a4fc5ed6 610 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 611 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 612 ret = -EBUSY;
613 goto out;
a4fc5ed6
KP		 614 }
615
616 /* Check for timeout or receive error.
617 * Timeouts occur when the sink is not connected
618 */
a5b3da54 619 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 620 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 621 ret = -EIO;
622 goto out;
a5b3da54 623 }
1ae8c0a5
KP		 624
625 /* Timeouts occur when the device isn't connected, so they're
626 * "normal" -- don't fill the kernel log with these */
a5b3da54 627 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 628 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 629 ret = -ETIMEDOUT;
630 goto out;
a4fc5ed6
KP		 631 }
632
633 /* Unload any bytes sent back from the other side */
634 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
635 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 636 if (recv_bytes > recv_size)
637 recv_bytes = recv_size;
0206e353 638
4f7f7b7e
CW		 639 for (i = 0; i < recv_bytes; i += 4)
640 unpack_aux(I915_READ(ch_data + i),
641 recv + i, recv_bytes - i);
a4fc5ed6 642
9ee32fea
DV		 643 ret = recv_bytes;
644out:
645 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 646 intel_aux_display_runtime_put(dev_priv);
9ee32fea 647
884f19e9
JN		 648 if (vdd)
649 edp_panel_vdd_off(intel_dp, false);
650
9ee32fea 651 return ret;
a4fc5ed6
KP		 652}
653
a6c8aff0
JN		 654#define BARE_ADDRESS_SIZE 3
655#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 656static ssize_t
657intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 658{
9d1a1031
JN		 659 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
660 uint8_t txbuf[20], rxbuf[20];
661 size_t txsize, rxsize;
a4fc5ed6 662 int ret;
a4fc5ed6 663
9d1a1031
JN		 664 txbuf[0] = msg->request << 4;
665 txbuf[1] = msg->address >> 8;
666 txbuf[2] = msg->address & 0xff;
667 txbuf[3] = msg->size - 1;
46a5ae9f 668
9d1a1031
JN		 669 switch (msg->request & ~DP_AUX_I2C_MOT) {
670 case DP_AUX_NATIVE_WRITE:
671 case DP_AUX_I2C_WRITE:
a6c8aff0 672 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 673 rxsize = 1;
f51a44b9 674
9d1a1031
JN		 675 if (WARN_ON(txsize > 20))
676 return -E2BIG;
a4fc5ed6 677
9d1a1031 678 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 679
9d1a1031
JN		 680 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
681 if (ret > 0) {
682 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 683
9d1a1031
JN		 684 /* Return payload size. */
685 ret = msg->size;
686 }
687 break;
46a5ae9f 688
9d1a1031
JN		 689 case DP_AUX_NATIVE_READ:
690 case DP_AUX_I2C_READ:
a6c8aff0 691 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 692 rxsize = msg->size + 1;
a4fc5ed6 693
9d1a1031
JN		 694 if (WARN_ON(rxsize > 20))
695 return -E2BIG;
a4fc5ed6 696
9d1a1031
JN		 697 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
698 if (ret > 0) {
699 msg->reply = rxbuf[0] >> 4;
700 /*
701 * Assume happy day, and copy the data. The caller is
702 * expected to check msg->reply before touching it.
703 *
704 * Return payload size.
705 */
706 ret--;
707 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 708 }
9d1a1031
JN		 709 break;
710
711 default:
712 ret = -EINVAL;
713 break;
a4fc5ed6 714 }
f51a44b9 715
9d1a1031 716 return ret;
a4fc5ed6
KP		 717}
718
9d1a1031
JN		 719static void
720intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
721{
722 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 723 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
724 enum port port = intel_dig_port->port;
0b99836f 725 const char *name = NULL;
ab2c0672
DA		 726 int ret;
727
33ad6626
JN		 728 switch (port) {
729 case PORT_A:
730 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 731 name = "DPDDC-A";
ab2c0672 732 break;
33ad6626
JN		 733 case PORT_B:
734 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 735 name = "DPDDC-B";
ab2c0672 736 break;
33ad6626
JN		 737 case PORT_C:
738 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 739 name = "DPDDC-C";
ab2c0672 740 break;
33ad6626
JN		 741 case PORT_D:
742 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 743 name = "DPDDC-D";
33ad6626
JN		 744 break;
745 default:
746 BUG();
ab2c0672
DA		 747 }
748
33ad6626
JN		 749 if (!HAS_DDI(dev))
750 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 751
0b99836f 752 intel_dp->aux.name = name;
9d1a1031
JN		 753 intel_dp->aux.dev = dev->dev;
754 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 755
0b99836f
JN		 756 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
757 connector->base.kdev->kobj.name);
8316f337 758
4f71d0cb 759 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 760 if (ret < 0) {
4f71d0cb 761 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 762 name, ret);
763 return;
ab2c0672 764 }
8a5e6aeb 765
0b99836f
JN		 766 ret = sysfs_create_link(&connector->base.kdev->kobj,
767 &intel_dp->aux.ddc.dev.kobj,
768 intel_dp->aux.ddc.dev.kobj.name);
769 if (ret < 0) {
770 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 771 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 772 }
a4fc5ed6
KP		 773}
774
80f65de3
ID		 775static void
776intel_dp_connector_unregister(struct intel_connector *intel_connector)
777{
778 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
779
0e32b39c
DA		 780 if (!intel_connector->mst_port)
781 sysfs_remove_link(&intel_connector->base.kdev->kobj,
782 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 783 intel_connector_unregister(intel_connector);
784}
785
0e50338c
DV		 786static void
787hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
788{
789 switch (link_bw) {
790 case DP_LINK_BW_1_62:
791 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
792 break;
793 case DP_LINK_BW_2_7:
794 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
795 break;
796 case DP_LINK_BW_5_4:
797 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
798 break;
799 }
800}
801
c6bb3538
DV		 802static void
803intel_dp_set_clock(struct intel_encoder *encoder,
804 struct intel_crtc_config *pipe_config, int link_bw)
805{
806 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 807 const struct dp_link_dpll *divisor = NULL;
808 int i, count = 0;
c6bb3538
DV		 809
810 if (IS_G4X(dev)) {
9dd4ffdf
CML		 811 divisor = gen4_dpll;
812 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 813 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 814 divisor = pch_dpll;
815 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 816 } else if (IS_CHERRYVIEW(dev)) {
817 divisor = chv_dpll;
818 count = ARRAY_SIZE(chv_dpll);
c6bb3538 819 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 820 divisor = vlv_dpll;
821 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 822 }
9dd4ffdf
CML		 823
824 if (divisor && count) {
825 for (i = 0; i < count; i++) {
826 if (link_bw == divisor[i].link_bw) {
827 pipe_config->dpll = divisor[i].dpll;
828 pipe_config->clock_set = true;
829 break;
830 }
831 }
c6bb3538
DV		 832 }
833}
834
00c09d70 835bool
5bfe2ac0
DV		 836intel_dp_compute_config(struct intel_encoder *encoder,
837 struct intel_crtc_config *pipe_config)
a4fc5ed6 838{
5bfe2ac0 839 struct drm_device *dev = encoder->base.dev;
36008365 840 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 841 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 842 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 843 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 844 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 845 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 846 int lane_count, clock;
56071a20 847 int min_lane_count = 1;
eeb6324d 848 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 849 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 850 int min_clock = 0;
06ea66b6 851 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 852 int bpp, mode_rate;
06ea66b6 853 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 854 int link_avail, link_clock;
a4fc5ed6 855
bc7d38a4 856 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 857 pipe_config->has_pch_encoder = true;
858
03afc4a2 859 pipe_config->has_dp_encoder = true;
f769cd24 860 pipe_config->has_drrs = false;
9ed109a7 861 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 862
dd06f90e
JN		 863 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
864 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
865 adjusted_mode);
2dd24552
JB		 866 if (!HAS_PCH_SPLIT(dev))
867 intel_gmch_panel_fitting(intel_crtc, pipe_config,
868 intel_connector->panel.fitting_mode);
869 else
b074cec8
JB		 870 intel_pch_panel_fitting(intel_crtc, pipe_config,
871 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 872 }
873
cb1793ce 874 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 875 return false;
876
083f9560
DV		 877 DRM_DEBUG_KMS("DP link computation with max lane count %i "
878 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 879 max_lane_count, bws[max_clock],
880 adjusted_mode->crtc_clock);
083f9560 881
36008365
DV		 882 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
883 * bpc in between. */
3e7ca985 884 bpp = pipe_config->pipe_bpp;
56071a20
JN		 885 if (is_edp(intel_dp)) {
886 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
887 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
888 dev_priv->vbt.edp_bpp);
889 bpp = dev_priv->vbt.edp_bpp;
890 }
891
f4cdbc21
JN		 892 if (IS_BROADWELL(dev)) {
893 /* Yes, it's an ugly hack. */
894 min_lane_count = max_lane_count;
895 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
896 min_lane_count);
897 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 898 min_lane_count = min(dev_priv->vbt.edp_lanes,
899 max_lane_count);
900 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
901 min_lane_count);
902 }
903
904 if (dev_priv->vbt.edp_rate) {
905 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
906 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
907 bws[min_clock]);
908 }
7984211e 909 }
657445fe 910
36008365 911 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 912 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
913 bpp);
36008365 914
c6930992
DA		 915 for (clock = min_clock; clock <= max_clock; clock++) {
916 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 917 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
918 link_avail = intel_dp_max_data_rate(link_clock,
919 lane_count);
920
921 if (mode_rate <= link_avail) {
922 goto found;
923 }
924 }
925 }
926 }
c4867936 927
36008365 928 return false;
3685a8f3 929
36008365 930found:
55bc60db
VS		 931 if (intel_dp->color_range_auto) {
932 /*
933 * See:
934 * CEA-861-E - 5.1 Default Encoding Parameters
935 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
936 */
18316c8c 937 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 938 intel_dp->color_range = DP_COLOR_RANGE_16_235;
939 else
940 intel_dp->color_range = 0;
941 }
942
3685a8f3 943 if (intel_dp->color_range)
50f3b016 944 pipe_config->limited_color_range = true;
a4fc5ed6 945
36008365
DV		 946 intel_dp->link_bw = bws[clock];
947 intel_dp->lane_count = lane_count;
657445fe 948 pipe_config->pipe_bpp = bpp;
ff9a6750 949 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 950
36008365
DV		 951 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
952 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 953 pipe_config->port_clock, bpp);
36008365
DV		 954 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
955 mode_rate, link_avail);
a4fc5ed6 956
03afc4a2 957 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 958 adjusted_mode->crtc_clock,
959 pipe_config->port_clock,
03afc4a2 960 &pipe_config->dp_m_n);
9d1a455b 961
439d7ac0
PB		 962 if (intel_connector->panel.downclock_mode != NULL &&
963 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 964 pipe_config->has_drrs = true;
439d7ac0
PB		 965 intel_link_compute_m_n(bpp, lane_count,
966 intel_connector->panel.downclock_mode->clock,
967 pipe_config->port_clock,
968 &pipe_config->dp_m2_n2);
969 }
970
ea155f32 971 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 972 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
973 else
974 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 975
03afc4a2 976 return true;
a4fc5ed6
KP		 977}
978
7c62a164 979static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 980{
7c62a164
DV		 981 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
982 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
983 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 984 struct drm_i915_private *dev_priv = dev->dev_private;
985 u32 dpa_ctl;
986
ff9a6750 987 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 988 dpa_ctl = I915_READ(DP_A);
989 dpa_ctl &= ~DP_PLL_FREQ_MASK;
990
ff9a6750 991 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 992 /* For a long time we've carried around a ILK-DevA w/a for the
993 * 160MHz clock. If we're really unlucky, it's still required.
994 */
995 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 996 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 997 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 998 } else {
999 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1000 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1001 }
1ce17038 1002
ea9b6006
DV		 1003 I915_WRITE(DP_A, dpa_ctl);
1004
1005 POSTING_READ(DP_A);
1006 udelay(500);
1007}
1008
8ac33ed3 1009static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1010{
b934223d 1011 struct drm_device *dev = encoder->base.dev;
417e822d 1012 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1013 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1014 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1015 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1016 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1017
417e822d 1018 /*
1a2eb460 1019 * There are four kinds of DP registers:
417e822d
KP		 1020 *
1021 * IBX PCH
1a2eb460
KP		 1022 * SNB CPU
1023 * IVB CPU
417e822d
KP		 1024 * CPT PCH
1025 *
1026 * IBX PCH and CPU are the same for almost everything,
1027 * except that the CPU DP PLL is configured in this
1028 * register
1029 *
1030 * CPT PCH is quite different, having many bits moved
1031 * to the TRANS_DP_CTL register instead. That
1032 * configuration happens (oddly) in ironlake_pch_enable
1033 */
9c9e7927 1034
417e822d
KP		 1035 /* Preserve the BIOS-computed detected bit. This is
1036 * supposed to be read-only.
1037 */
1038 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1039
417e822d 1040 /* Handle DP bits in common between all three register formats */
417e822d 1041 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1042 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1043
9ed109a7 1044 if (crtc->config.has_audio) {
e0dac65e 1045 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1046 pipe_name(crtc->pipe));
ea5b213a 1047 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1048 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1049 }
247d89f6 1050
417e822d 1051 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1052
bc7d38a4 1053 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1054 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1055 intel_dp->DP |= DP_SYNC_HS_HIGH;
1056 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1057 intel_dp->DP |= DP_SYNC_VS_HIGH;
1058 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1059
6aba5b6c 1060 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1061 intel_dp->DP |= DP_ENHANCED_FRAMING;
1062
7c62a164 1063 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1064 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1065 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1066 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1067
1068 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1069 intel_dp->DP |= DP_SYNC_HS_HIGH;
1070 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1071 intel_dp->DP |= DP_SYNC_VS_HIGH;
1072 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1073
6aba5b6c 1074 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1075 intel_dp->DP |= DP_ENHANCED_FRAMING;
1076
44f37d1f
CML		 1077 if (!IS_CHERRYVIEW(dev)) {
1078 if (crtc->pipe == 1)
1079 intel_dp->DP |= DP_PIPEB_SELECT;
1080 } else {
1081 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1082 }
417e822d
KP		 1083 } else {
1084 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1085 }
a4fc5ed6
KP		 1086}
1087
ffd6749d
PZ		 1088#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1089#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1090
1a5ef5b7
PZ		 1091#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1092#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1093
ffd6749d
PZ		 1094#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1095#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1096
4be73780 1097static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1098 u32 mask,
1099 u32 value)
bd943159 1100{
30add22d 1101 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1102 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1103 u32 pp_stat_reg, pp_ctrl_reg;
1104
bf13e81b
JN		 1105 pp_stat_reg = _pp_stat_reg(intel_dp);
1106 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1107
99ea7127 1108 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1109 mask, value,
1110 I915_READ(pp_stat_reg),
1111 I915_READ(pp_ctrl_reg));
32ce697c 1112
453c5420 1113 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1114 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1115 I915_READ(pp_stat_reg),
1116 I915_READ(pp_ctrl_reg));
32ce697c 1117 }
54c136d4
CW		 1118
1119 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1120}
32ce697c 1121
4be73780 1122static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1123{
1124 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1125 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1126}
1127
4be73780 1128static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1129{
1130 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1131 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1132}
1133
4be73780 1134static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1135{
1136 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1137
1138 /* When we disable the VDD override bit last we have to do the manual
1139 * wait. */
1140 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1141 intel_dp->panel_power_cycle_delay);
1142
4be73780 1143 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1144}
1145
4be73780 1146static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1147{
1148 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1149 intel_dp->backlight_on_delay);
1150}
1151
4be73780 1152static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1153{
1154 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1155 intel_dp->backlight_off_delay);
1156}
99ea7127 1157
832dd3c1
KP		 1158/* Read the current pp_control value, unlocking the register if it
1159 * is locked
1160 */
1161
453c5420 1162static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1163{
453c5420
JB		 1164 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1166 u32 control;
832dd3c1 1167
bf13e81b 1168 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1169 control &= ~PANEL_UNLOCK_MASK;
1170 control |= PANEL_UNLOCK_REGS;
1171 return control;
bd943159
KP		 1172}
1173
1e0560e0 1174static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1175{
30add22d 1176 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1177 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1178 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1179 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1180 enum intel_display_power_domain power_domain;
5d613501 1181 u32 pp;
453c5420 1182 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1183 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1184
97af61f5 1185 if (!is_edp(intel_dp))
adddaaf4 1186 return false;
bd943159
KP		 1187
1188 intel_dp->want_panel_vdd = true;
99ea7127 1189
4be73780 1190 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1191 return need_to_disable;
b0665d57 1192
4e6e1a54
ID		 1193 power_domain = intel_display_port_power_domain(intel_encoder);
1194 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1195
b0665d57 1196 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1197
4be73780
DV		 1198 if (!edp_have_panel_power(intel_dp))
1199 wait_panel_power_cycle(intel_dp);
99ea7127 1200
453c5420 1201 pp = ironlake_get_pp_control(intel_dp);
5d613501 1202 pp |= EDP_FORCE_VDD;
ebf33b18 1203
bf13e81b
JN		 1204 pp_stat_reg = _pp_stat_reg(intel_dp);
1205 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1206
1207 I915_WRITE(pp_ctrl_reg, pp);
1208 POSTING_READ(pp_ctrl_reg);
1209 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1210 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1211 /*
1212 * If the panel wasn't on, delay before accessing aux channel
1213 */
4be73780 1214 if (!edp_have_panel_power(intel_dp)) {
bd943159 1215 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1216 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1217 }
adddaaf4
JN		 1218
1219 return need_to_disable;
1220}
1221
b80d6c78 1222void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1223{
c695b6b6 1224 bool vdd;
adddaaf4 1225
c695b6b6
VS		 1226 if (!is_edp(intel_dp))
1227 return;
1228
1229 vdd = edp_panel_vdd_on(intel_dp);
1230
1231 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1232}
1233
4be73780 1234static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1235{
30add22d 1236 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1237 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1238 struct intel_digital_port *intel_dig_port =
1239 dp_to_dig_port(intel_dp);
1240 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1241 enum intel_display_power_domain power_domain;
5d613501 1242 u32 pp;
453c5420 1243 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1244
51fd371b 1245 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
a0e99e68 1246
15e899a0
VS		 1247 WARN_ON(intel_dp->want_panel_vdd);
1248
1249 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1250 return;
4e6e1a54 1251
be2c9196 1252 DRM_DEBUG_KMS("Turning eDP VDD off\n");
b0665d57 1253
be2c9196
VS		 1254 pp = ironlake_get_pp_control(intel_dp);
1255 pp &= ~EDP_FORCE_VDD;
bd943159 1256
be2c9196
VS		 1257 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1258 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420 1259
be2c9196
VS		 1260 I915_WRITE(pp_ctrl_reg, pp);
1261 POSTING_READ(pp_ctrl_reg);
99ea7127 1262
be2c9196
VS		 1263 /* Make sure sequencer is idle before allowing subsequent activity */
1264 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1265 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c 1266
be2c9196
VS		 1267 if ((pp & POWER_TARGET_ON) == 0)
1268 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1269
be2c9196
VS		 1270 power_domain = intel_display_port_power_domain(intel_encoder);
1271 intel_display_power_put(dev_priv, power_domain);
bd943159 1272}
5d613501 1273
4be73780 1274static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1275{
1276 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1277 struct intel_dp, panel_vdd_work);
30add22d 1278 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1279
51fd371b 1280 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
15e899a0
VS		 1281 if (!intel_dp->want_panel_vdd)
1282 edp_panel_vdd_off_sync(intel_dp);
51fd371b 1283 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159
KP		 1284}
1285
aba86890
ID		 1286static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1287{
1288 unsigned long delay;
1289
1290 /*
1291 * Queue the timer to fire a long time from now (relative to the power
1292 * down delay) to keep the panel power up across a sequence of
1293 * operations.
1294 */
1295 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1296 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1297}
1298
4be73780 1299static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1300{
97af61f5
KP		 1301 if (!is_edp(intel_dp))
1302 return;
5d613501 1303
bd943159 1304 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1305
bd943159
KP		 1306 intel_dp->want_panel_vdd = false;
1307
aba86890 1308 if (sync)
4be73780 1309 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1310 else
1311 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1312}
1313
1e0560e0
VS		 1314static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1315{
1316 edp_panel_vdd_off(intel_dp, sync);
1317}
1318
4be73780 1319void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1320{
30add22d 1321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1322 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1323 u32 pp;
453c5420 1324 u32 pp_ctrl_reg;
9934c132 1325
97af61f5 1326 if (!is_edp(intel_dp))
bd943159 1327 return;
99ea7127
KP		 1328
1329 DRM_DEBUG_KMS("Turn eDP power on\n");
1330
4be73780 1331 if (edp_have_panel_power(intel_dp)) {
99ea7127 1332 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1333 return;
99ea7127 1334 }
9934c132 1335
4be73780 1336 wait_panel_power_cycle(intel_dp);
37c6c9b0 1337
bf13e81b 1338 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1339 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1340 if (IS_GEN5(dev)) {
1341 /* ILK workaround: disable reset around power sequence */
1342 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1343 I915_WRITE(pp_ctrl_reg, pp);
1344 POSTING_READ(pp_ctrl_reg);
05ce1a49 1345 }
37c6c9b0 1346
1c0ae80a 1347 pp |= POWER_TARGET_ON;
99ea7127
KP		 1348 if (!IS_GEN5(dev))
1349 pp |= PANEL_POWER_RESET;
1350
453c5420
JB		 1351 I915_WRITE(pp_ctrl_reg, pp);
1352 POSTING_READ(pp_ctrl_reg);
9934c132 1353
4be73780 1354 wait_panel_on(intel_dp);
dce56b3c 1355 intel_dp->last_power_on = jiffies;
9934c132 1356
05ce1a49
KP		 1357 if (IS_GEN5(dev)) {
1358 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1359 I915_WRITE(pp_ctrl_reg, pp);
1360 POSTING_READ(pp_ctrl_reg);
05ce1a49 1361 }
9934c132
JB		 1362}
1363
4be73780 1364void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1365{
4e6e1a54
ID		 1366 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1367 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1368 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1369 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1370 enum intel_display_power_domain power_domain;
99ea7127 1371 u32 pp;
453c5420 1372 u32 pp_ctrl_reg;
9934c132 1373
97af61f5
KP		 1374 if (!is_edp(intel_dp))
1375 return;
37c6c9b0 1376
99ea7127 1377 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1378
24f3e092
JN		 1379 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1380
453c5420 1381 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1382 /* We need to switch off panel power _and_ force vdd, for otherwise some
1383 * panels get very unhappy and cease to work. */
b3064154
PJ		 1384 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1385 EDP_BLC_ENABLE);
453c5420 1386
bf13e81b 1387 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1388
849e39f5
PZ		 1389 intel_dp->want_panel_vdd = false;
1390
453c5420
JB		 1391 I915_WRITE(pp_ctrl_reg, pp);
1392 POSTING_READ(pp_ctrl_reg);
9934c132 1393
dce56b3c 1394 intel_dp->last_power_cycle = jiffies;
4be73780 1395 wait_panel_off(intel_dp);
849e39f5
PZ		 1396
1397 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1398 power_domain = intel_display_port_power_domain(intel_encoder);
1399 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1400}
1401
1250d107
JN		 1402/* Enable backlight in the panel power control. */
1403static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1404{
da63a9f2
PZ		 1405 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1406 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1407 struct drm_i915_private *dev_priv = dev->dev_private;
1408 u32 pp;
453c5420 1409 u32 pp_ctrl_reg;
32f9d658 1410
01cb9ea6
JB		 1411 /*
1412 * If we enable the backlight right away following a panel power
1413 * on, we may see slight flicker as the panel syncs with the eDP
1414 * link. So delay a bit to make sure the image is solid before
1415 * allowing it to appear.
1416 */
4be73780 1417 wait_backlight_on(intel_dp);
453c5420 1418 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1419 pp |= EDP_BLC_ENABLE;
453c5420 1420
bf13e81b 1421 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1422
1423 I915_WRITE(pp_ctrl_reg, pp);
1424 POSTING_READ(pp_ctrl_reg);
32f9d658
ZW		 1425}
1426
1250d107
JN		 1427/* Enable backlight PWM and backlight PP control. */
1428void intel_edp_backlight_on(struct intel_dp *intel_dp)
1429{
1430 if (!is_edp(intel_dp))
1431 return;
1432
1433 DRM_DEBUG_KMS("\n");
1434
1435 intel_panel_enable_backlight(intel_dp->attached_connector);
1436 _intel_edp_backlight_on(intel_dp);
1437}
1438
1439/* Disable backlight in the panel power control. */
1440static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1441{
30add22d 1442 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1443 struct drm_i915_private *dev_priv = dev->dev_private;
1444 u32 pp;
453c5420 1445 u32 pp_ctrl_reg;
32f9d658 1446
453c5420 1447 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1448 pp &= ~EDP_BLC_ENABLE;
453c5420 1449
bf13e81b 1450 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1451
1452 I915_WRITE(pp_ctrl_reg, pp);
1453 POSTING_READ(pp_ctrl_reg);
dce56b3c 1454 intel_dp->last_backlight_off = jiffies;
f7d2323c
JB		 1455
1456 edp_wait_backlight_off(intel_dp);
1250d107
JN		 1457}
1458
1459/* Disable backlight PP control and backlight PWM. */
1460void intel_edp_backlight_off(struct intel_dp *intel_dp)
1461{
1462 if (!is_edp(intel_dp))
1463 return;
1464
1465 DRM_DEBUG_KMS("\n");
f7d2323c 1466
1250d107 1467 _intel_edp_backlight_off(intel_dp);
f7d2323c 1468 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1469}
a4fc5ed6 1470
73580fb7
JN		 1471/*
1472 * Hook for controlling the panel power control backlight through the bl_power
1473 * sysfs attribute. Take care to handle multiple calls.
1474 */
1475static void intel_edp_backlight_power(struct intel_connector *connector,
1476 bool enable)
1477{
1478 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1479 bool is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1480
1481 if (is_enabled == enable)
1482 return;
1483
1484 DRM_DEBUG_KMS("\n");
1485
1486 if (enable)
1487 _intel_edp_backlight_on(intel_dp);
1488 else
1489 _intel_edp_backlight_off(intel_dp);
1490}
1491
2bd2ad64 1492static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1493{
da63a9f2
PZ		 1494 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1495 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1496 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1497 struct drm_i915_private *dev_priv = dev->dev_private;
1498 u32 dpa_ctl;
1499
2bd2ad64
DV		 1500 assert_pipe_disabled(dev_priv,
1501 to_intel_crtc(crtc)->pipe);
1502
d240f20f
JB		 1503 DRM_DEBUG_KMS("\n");
1504 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1505 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1506 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1507
1508 /* We don't adjust intel_dp->DP while tearing down the link, to
1509 * facilitate link retraining (e.g. after hotplug). Hence clear all
1510 * enable bits here to ensure that we don't enable too much. */
1511 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1512 intel_dp->DP |= DP_PLL_ENABLE;
1513 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1514 POSTING_READ(DP_A);
1515 udelay(200);
d240f20f
JB		 1516}
1517
2bd2ad64 1518static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1519{
da63a9f2
PZ		 1520 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1521 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1522 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1523 struct drm_i915_private *dev_priv = dev->dev_private;
1524 u32 dpa_ctl;
1525
2bd2ad64
DV		 1526 assert_pipe_disabled(dev_priv,
1527 to_intel_crtc(crtc)->pipe);
1528
d240f20f 1529 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1530 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1531 "dp pll off, should be on\n");
1532 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1533
1534 /* We can't rely on the value tracked for the DP register in
1535 * intel_dp->DP because link_down must not change that (otherwise link
1536 * re-training will fail. */
298b0b39 1537 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1538 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1539 POSTING_READ(DP_A);
d240f20f
JB		 1540 udelay(200);
1541}
1542
c7ad3810 1543/* If the sink supports it, try to set the power state appropriately */
c19b0669 1544void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1545{
1546 int ret, i;
1547
1548 /* Should have a valid DPCD by this point */
1549 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1550 return;
1551
1552 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1553 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1554 DP_SET_POWER_D3);
c7ad3810
JB		 1555 if (ret != 1)
1556 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1557 } else {
1558 /*
1559 * When turning on, we need to retry for 1ms to give the sink
1560 * time to wake up.
1561 */
1562 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1563 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1564 DP_SET_POWER_D0);
c7ad3810
JB		 1565 if (ret == 1)
1566 break;
1567 msleep(1);
1568 }
1569 }
1570}
1571
19d8fe15
DV		 1572static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1573 enum pipe *pipe)
d240f20f 1574{
19d8fe15 1575 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1576 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1577 struct drm_device *dev = encoder->base.dev;
1578 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1579 enum intel_display_power_domain power_domain;
1580 u32 tmp;
1581
1582 power_domain = intel_display_port_power_domain(encoder);
1583 if (!intel_display_power_enabled(dev_priv, power_domain))
1584 return false;
1585
1586 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1587
1588 if (!(tmp & DP_PORT_EN))
1589 return false;
1590
bc7d38a4 1591 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1592 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1593 } else if (IS_CHERRYVIEW(dev)) {
1594 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1595 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1596 *pipe = PORT_TO_PIPE(tmp);
1597 } else {
1598 u32 trans_sel;
1599 u32 trans_dp;
1600 int i;
1601
1602 switch (intel_dp->output_reg) {
1603 case PCH_DP_B:
1604 trans_sel = TRANS_DP_PORT_SEL_B;
1605 break;
1606 case PCH_DP_C:
1607 trans_sel = TRANS_DP_PORT_SEL_C;
1608 break;
1609 case PCH_DP_D:
1610 trans_sel = TRANS_DP_PORT_SEL_D;
1611 break;
1612 default:
1613 return true;
1614 }
1615
055e393f 1616 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1617 trans_dp = I915_READ(TRANS_DP_CTL(i));
1618 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1619 *pipe = i;
1620 return true;
1621 }
1622 }
19d8fe15 1623
4a0833ec
DV		 1624 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1625 intel_dp->output_reg);
1626 }
d240f20f 1627
19d8fe15
DV		 1628 return true;
1629}
d240f20f 1630
045ac3b5
JB		 1631static void intel_dp_get_config(struct intel_encoder *encoder,
1632 struct intel_crtc_config *pipe_config)
1633{
1634 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1635 u32 tmp, flags = 0;
63000ef6
XZ		 1636 struct drm_device *dev = encoder->base.dev;
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1638 enum port port = dp_to_dig_port(intel_dp)->port;
1639 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1640 int dotclock;
045ac3b5 1641
9ed109a7
DV		 1642 tmp = I915_READ(intel_dp->output_reg);
1643 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1644 pipe_config->has_audio = true;
1645
63000ef6 1646 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1647 if (tmp & DP_SYNC_HS_HIGH)
1648 flags |= DRM_MODE_FLAG_PHSYNC;
1649 else
1650 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1651
63000ef6
XZ		 1652 if (tmp & DP_SYNC_VS_HIGH)
1653 flags |= DRM_MODE_FLAG_PVSYNC;
1654 else
1655 flags |= DRM_MODE_FLAG_NVSYNC;
1656 } else {
1657 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1658 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1659 flags |= DRM_MODE_FLAG_PHSYNC;
1660 else
1661 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1662
63000ef6
XZ		 1663 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1664 flags |= DRM_MODE_FLAG_PVSYNC;
1665 else
1666 flags |= DRM_MODE_FLAG_NVSYNC;
1667 }
045ac3b5
JB		 1668
1669 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1670
eb14cb74
VS		 1671 pipe_config->has_dp_encoder = true;
1672
1673 intel_dp_get_m_n(crtc, pipe_config);
1674
18442d08 1675 if (port == PORT_A) {
f1f644dc
JB		 1676 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1677 pipe_config->port_clock = 162000;
1678 else
1679 pipe_config->port_clock = 270000;
1680 }
18442d08
VS		 1681
1682 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1683 &pipe_config->dp_m_n);
1684
1685 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1686 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1687
241bfc38 1688 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1689
c6cd2ee2
JN		 1690 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1691 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1692 /*
1693 * This is a big fat ugly hack.
1694 *
1695 * Some machines in UEFI boot mode provide us a VBT that has 18
1696 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1697 * unknown we fail to light up. Yet the same BIOS boots up with
1698 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1699 * max, not what it tells us to use.
1700 *
1701 * Note: This will still be broken if the eDP panel is not lit
1702 * up by the BIOS, and thus we can't get the mode at module
1703 * load.
1704 */
1705 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1706 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1707 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1708 }
045ac3b5
JB		 1709}
1710
34eb7579 1711static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1712{
34eb7579 1713 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1714}
1715
2b28bb1b
RV		 1716static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1717{
1718 struct drm_i915_private *dev_priv = dev->dev_private;
1719
18b5992c 1720 if (!HAS_PSR(dev))
2b28bb1b
RV		 1721 return false;
1722
18b5992c 1723 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1724}
1725
1726static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1727 struct edp_vsc_psr *vsc_psr)
1728{
1729 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1730 struct drm_device *dev = dig_port->base.base.dev;
1731 struct drm_i915_private *dev_priv = dev->dev_private;
1732 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1733 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1734 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1735 uint32_t *data = (uint32_t *) vsc_psr;
1736 unsigned int i;
1737
1738 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1739 the video DIP being updated before program video DIP data buffer
1740 registers for DIP being updated. */
1741 I915_WRITE(ctl_reg, 0);
1742 POSTING_READ(ctl_reg);
1743
1744 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1745 if (i < sizeof(struct edp_vsc_psr))
1746 I915_WRITE(data_reg + i, *data++);
1747 else
1748 I915_WRITE(data_reg + i, 0);
1749 }
1750
1751 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1752 POSTING_READ(ctl_reg);
1753}
1754
1755static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1756{
1757 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1758 struct drm_i915_private *dev_priv = dev->dev_private;
1759 struct edp_vsc_psr psr_vsc;
1760
2b28bb1b
RV		 1761 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1762 memset(&psr_vsc, 0, sizeof(psr_vsc));
1763 psr_vsc.sdp_header.HB0 = 0;
1764 psr_vsc.sdp_header.HB1 = 0x7;
1765 psr_vsc.sdp_header.HB2 = 0x2;
1766 psr_vsc.sdp_header.HB3 = 0x8;
1767 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1768
1769 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1770 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1771 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1772}
1773
1774static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1775{
0e0ae652
RV		 1776 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1777 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 1778 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1779 uint32_t aux_clock_divider;
2b28bb1b
RV		 1780 int precharge = 0x3;
1781 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 1782 bool only_standby = false;
2b28bb1b 1783
ec5b01dd
DL		 1784 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1785
0e0ae652
RV		 1786 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1787 only_standby = true;
1788
2b28bb1b 1789 /* Enable PSR in sink */
0e0ae652 1790 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 1791 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1792 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1793 else
9d1a1031
JN		 1794 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1795 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1796
1797 /* Setup AUX registers */
18b5992c
BW		 1798 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1799 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1800 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1801 DP_AUX_CH_CTL_TIME_OUT_400us |
1802 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1803 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1804 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1805}
1806
1807static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1808{
0e0ae652
RV		 1809 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1810 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 1811 struct drm_i915_private *dev_priv = dev->dev_private;
1812 uint32_t max_sleep_time = 0x1f;
1813 uint32_t idle_frames = 1;
1814 uint32_t val = 0x0;
ed8546ac 1815 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 1816 bool only_standby = false;
1817
1818 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1819 only_standby = true;
2b28bb1b 1820
0e0ae652 1821 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 1822 val |= EDP_PSR_LINK_STANDBY;
1823 val |= EDP_PSR_TP2_TP3_TIME_0us;
1824 val |= EDP_PSR_TP1_TIME_0us;
1825 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 1826 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 1827 } else
1828 val |= EDP_PSR_LINK_DISABLE;
1829
18b5992c 1830 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1831 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1832 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1833 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1834 EDP_PSR_ENABLE);
1835}
1836
3f51e471
RV		 1837static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1838{
1839 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1840 struct drm_device *dev = dig_port->base.base.dev;
1841 struct drm_i915_private *dev_priv = dev->dev_private;
1842 struct drm_crtc *crtc = dig_port->base.base.crtc;
1843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 1844
f0355c4a 1845 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 1846 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1847 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1848
a031d709
RV		 1849 dev_priv->psr.source_ok = false;
1850
9ca15301 1851 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 1852 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1853 return false;
1854 }
1855
d330a953 1856 if (!i915.enable_psr) {
105b7c11 1857 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1858 return false;
1859 }
1860
4c8c7000
RV		 1861 /* Below limitations aren't valid for Broadwell */
1862 if (IS_BROADWELL(dev))
1863 goto out;
1864
3f51e471
RV		 1865 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1866 S3D_ENABLE) {
1867 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1868 return false;
1869 }
1870
ca73b4f0 1871 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1872 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1873 return false;
1874 }
1875
4c8c7000 1876 out:
a031d709 1877 dev_priv->psr.source_ok = true;
3f51e471
RV		 1878 return true;
1879}
1880
3d739d92 1881static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 1882{
7c8f8a70
RV		 1883 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1884 struct drm_device *dev = intel_dig_port->base.base.dev;
1885 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 1886
3638379c
DV		 1887 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1888 WARN_ON(dev_priv->psr.active);
f0355c4a 1889 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 1890
2b28bb1b
RV		 1891 /* Enable PSR on the panel */
1892 intel_edp_psr_enable_sink(intel_dp);
1893
1894 /* Enable PSR on the host */
1895 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 1896
7c8f8a70 1897 dev_priv->psr.active = true;
2b28bb1b
RV		 1898}
1899
3d739d92
RV		 1900void intel_edp_psr_enable(struct intel_dp *intel_dp)
1901{
1902 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 1903 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 1904
4704c573
RV		 1905 if (!HAS_PSR(dev)) {
1906 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1907 return;
1908 }
1909
34eb7579
RV		 1910 if (!is_edp_psr(intel_dp)) {
1911 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1912 return;
1913 }
1914
f0355c4a 1915 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 1916 if (dev_priv->psr.enabled) {
1917 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 1918 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 1919 return;
1920 }
1921
9ca15301
DV		 1922 dev_priv->psr.busy_frontbuffer_bits = 0;
1923
16487254
RV		 1924 /* Setup PSR once */
1925 intel_edp_psr_setup(intel_dp);
1926
7c8f8a70 1927 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 1928 dev_priv->psr.enabled = intel_dp;
f0355c4a 1929 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1930}
1931
2b28bb1b
RV		 1932void intel_edp_psr_disable(struct intel_dp *intel_dp)
1933{
1934 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1935 struct drm_i915_private *dev_priv = dev->dev_private;
1936
f0355c4a
DV		 1937 mutex_lock(&dev_priv->psr.lock);
1938 if (!dev_priv->psr.enabled) {
1939 mutex_unlock(&dev_priv->psr.lock);
1940 return;
1941 }
1942
3638379c
DV		 1943 if (dev_priv->psr.active) {
1944 I915_WRITE(EDP_PSR_CTL(dev),
1945 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1946
1947 /* Wait till PSR is idle */
1948 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1949 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1950 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 1951
3638379c
DV		 1952 dev_priv->psr.active = false;
1953 } else {
1954 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1955 }
7c8f8a70 1956
2807cf69 1957 dev_priv->psr.enabled = NULL;
f0355c4a 1958 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 1959
1960 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 1961}
1962
f02a326e 1963static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 1964{
1965 struct drm_i915_private *dev_priv =
1966 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 1967 struct intel_dp *intel_dp = dev_priv->psr.enabled;
1968
f0355c4a
DV		 1969 mutex_lock(&dev_priv->psr.lock);
1970 intel_dp = dev_priv->psr.enabled;
1971
2807cf69 1972 if (!intel_dp)
f0355c4a 1973 goto unlock;
2807cf69 1974
9ca15301
DV		 1975 /*
1976 * The delayed work can race with an invalidate hence we need to
1977 * recheck. Since psr_flush first clears this and then reschedules we
1978 * won't ever miss a flush when bailing out here.
1979 */
1980 if (dev_priv->psr.busy_frontbuffer_bits)
1981 goto unlock;
1982
1983 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 1984unlock:
1985 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1986}
1987
9ca15301 1988static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 1989{
1990 struct drm_i915_private *dev_priv = dev->dev_private;
1991
3638379c
DV		 1992 if (dev_priv->psr.active) {
1993 u32 val = I915_READ(EDP_PSR_CTL(dev));
1994
1995 WARN_ON(!(val & EDP_PSR_ENABLE));
1996
1997 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
1998
1999 dev_priv->psr.active = false;
2000 }
7c8f8a70 2001
9ca15301
DV		 2002}
2003
2004void intel_edp_psr_invalidate(struct drm_device *dev,
2005 unsigned frontbuffer_bits)
2006{
2007 struct drm_i915_private *dev_priv = dev->dev_private;
2008 struct drm_crtc *crtc;
2009 enum pipe pipe;
2010
9ca15301
DV		 2011 mutex_lock(&dev_priv->psr.lock);
2012 if (!dev_priv->psr.enabled) {
2013 mutex_unlock(&dev_priv->psr.lock);
2014 return;
2015 }
2016
2017 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2018 pipe = to_intel_crtc(crtc)->pipe;
2019
2020 intel_edp_psr_do_exit(dev);
2021
2022 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2023
2024 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2025 mutex_unlock(&dev_priv->psr.lock);
2026}
2027
2028void intel_edp_psr_flush(struct drm_device *dev,
2029 unsigned frontbuffer_bits)
2030{
2031 struct drm_i915_private *dev_priv = dev->dev_private;
2032 struct drm_crtc *crtc;
2033 enum pipe pipe;
2034
9ca15301
DV		 2035 mutex_lock(&dev_priv->psr.lock);
2036 if (!dev_priv->psr.enabled) {
2037 mutex_unlock(&dev_priv->psr.lock);
2038 return;
2039 }
2040
2041 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2042 pipe = to_intel_crtc(crtc)->pipe;
2043 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2044
2045 /*
2046 * On Haswell sprite plane updates don't result in a psr invalidating
2047 * signal in the hardware. Which means we need to manually fake this in
2048 * software for all flushes, not just when we've seen a preceding
2049 * invalidation through frontbuffer rendering.
2050 */
2051 if (IS_HASWELL(dev) &&
2052 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2053 intel_edp_psr_do_exit(dev);
2054
2055 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2056 schedule_delayed_work(&dev_priv->psr.work,
2057 msecs_to_jiffies(100));
f0355c4a 2058 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2059}
2060
2061void intel_edp_psr_init(struct drm_device *dev)
2062{
2063 struct drm_i915_private *dev_priv = dev->dev_private;
2064
7c8f8a70 2065 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2066 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2067}
2068
e8cb4558 2069static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2070{
e8cb4558 2071 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 2072 enum port port = dp_to_dig_port(intel_dp)->port;
2073 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2074
2075 /* Make sure the panel is off before trying to change the mode. But also
2076 * ensure that we have vdd while we switch off the panel. */
24f3e092 2077 intel_edp_panel_vdd_on(intel_dp);
4be73780 2078 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2079 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2080 intel_edp_panel_off(intel_dp);
3739850b
DV		 2081
2082 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 2083 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 2084 intel_dp_link_down(intel_dp);
d240f20f
JB		 2085}
2086
49277c31 2087static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2088{
2bd2ad64 2089 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2090 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2091
49277c31
VS		 2092 if (port != PORT_A)
2093 return;
2094
2095 intel_dp_link_down(intel_dp);
2096 ironlake_edp_pll_off(intel_dp);
2097}
2098
2099static void vlv_post_disable_dp(struct intel_encoder *encoder)
2100{
2101 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2102
2103 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2104}
2105
580d3811
VS		 2106static void chv_post_disable_dp(struct intel_encoder *encoder)
2107{
2108 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2109 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2110 struct drm_device *dev = encoder->base.dev;
2111 struct drm_i915_private *dev_priv = dev->dev_private;
2112 struct intel_crtc *intel_crtc =
2113 to_intel_crtc(encoder->base.crtc);
2114 enum dpio_channel ch = vlv_dport_to_channel(dport);
2115 enum pipe pipe = intel_crtc->pipe;
2116 u32 val;
2117
2118 intel_dp_link_down(intel_dp);
2119
2120 mutex_lock(&dev_priv->dpio_lock);
2121
2122 /* Propagate soft reset to data lane reset */
97fd4d5c 2123 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2124 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2125 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2126
97fd4d5c
VS		 2127 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2128 val |= CHV_PCS_REQ_SOFTRESET_EN;
2129 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2130
2131 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2132 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2133 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2134
2135 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2136 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2137 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2138
2139 mutex_unlock(&dev_priv->dpio_lock);
2140}
2141
e8cb4558 2142static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2143{
e8cb4558
DV		 2144 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2145 struct drm_device *dev = encoder->base.dev;
2146 struct drm_i915_private *dev_priv = dev->dev_private;
2147 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2148
0c33d8d7
DV		 2149 if (WARN_ON(dp_reg & DP_PORT_EN))
2150 return;
5d613501 2151
24f3e092 2152 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 2153 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2154 intel_dp_start_link_train(intel_dp);
4be73780 2155 intel_edp_panel_on(intel_dp);
1e0560e0 2156 intel_edp_panel_vdd_off(intel_dp, true);
33a34e4e 2157 intel_dp_complete_link_train(intel_dp);
3ab9c637 2158 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2159}
89b667f8 2160
ecff4f3b
JN		 2161static void g4x_enable_dp(struct intel_encoder *encoder)
2162{
828f5c6e
JN		 2163 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2164
ecff4f3b 2165 intel_enable_dp(encoder);
4be73780 2166 intel_edp_backlight_on(intel_dp);
ab1f90f9 2167}
89b667f8 2168
ab1f90f9
JN		 2169static void vlv_enable_dp(struct intel_encoder *encoder)
2170{
828f5c6e
JN		 2171 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2172
4be73780 2173 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2174}
2175
ecff4f3b 2176static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2177{
2178 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2179 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2180
8ac33ed3
DV		 2181 intel_dp_prepare(encoder);
2182
d41f1efb
DV		 2183 /* Only ilk+ has port A */
2184 if (dport->port == PORT_A) {
2185 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2186 ironlake_edp_pll_on(intel_dp);
d41f1efb 2187 }
ab1f90f9
JN		 2188}
2189
2190static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2191{
2bd2ad64 2192 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2193 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2194 struct drm_device *dev = encoder->base.dev;
89b667f8 2195 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2196 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2197 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 2198 int pipe = intel_crtc->pipe;
bf13e81b 2199 struct edp_power_seq power_seq;
ab1f90f9 2200 u32 val;
a4fc5ed6 2201
ab1f90f9 2202 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2203
ab3c759a 2204 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2205 val = 0;
2206 if (pipe)
2207 val |= (1<<21);
2208 else
2209 val &= ~(1<<21);
2210 val |= 0x001000c4;
ab3c759a
CML		 2211 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2212 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2213 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2214
ab1f90f9
JN		 2215 mutex_unlock(&dev_priv->dpio_lock);
2216
2cac613b
ID		 2217 if (is_edp(intel_dp)) {
2218 /* init power sequencer on this pipe and port */
2219 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2220 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2221 &power_seq);
2222 }
bf13e81b 2223
ab1f90f9
JN		 2224 intel_enable_dp(encoder);
2225
e4607fcf 2226 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2227}
2228
ecff4f3b 2229static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2230{
2231 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2232 struct drm_device *dev = encoder->base.dev;
2233 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2234 struct intel_crtc *intel_crtc =
2235 to_intel_crtc(encoder->base.crtc);
e4607fcf 2236 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2237 int pipe = intel_crtc->pipe;
89b667f8 2238
8ac33ed3
DV		 2239 intel_dp_prepare(encoder);
2240
89b667f8 2241 /* Program Tx lane resets to default */
0980a60f 2242 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2243 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2244 DPIO_PCS_TX_LANE2_RESET |
2245 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2246 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2247 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2248 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2249 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2250 DPIO_PCS_CLK_SOFT_RESET);
2251
2252 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2253 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2254 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2255 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2256 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2257}
2258
e4a1d846
CML		 2259static void chv_pre_enable_dp(struct intel_encoder *encoder)
2260{
2261 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2262 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2263 struct drm_device *dev = encoder->base.dev;
2264 struct drm_i915_private *dev_priv = dev->dev_private;
2265 struct edp_power_seq power_seq;
2266 struct intel_crtc *intel_crtc =
2267 to_intel_crtc(encoder->base.crtc);
2268 enum dpio_channel ch = vlv_dport_to_channel(dport);
2269 int pipe = intel_crtc->pipe;
2270 int data, i;
949c1d43 2271 u32 val;
e4a1d846 2272
e4a1d846 2273 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2274
2275 /* Deassert soft data lane reset*/
97fd4d5c 2276 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2277 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2278 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2279
2280 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2281 val |= CHV_PCS_REQ_SOFTRESET_EN;
2282 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2283
2284 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2285 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2286 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2287
97fd4d5c 2288 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2289 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2290 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2291
2292 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2293 for (i = 0; i < 4; i++) {
2294 /* Set the latency optimal bit */
2295 data = (i == 1) ? 0x0 : 0x6;
2296 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2297 data << DPIO_FRC_LATENCY_SHFIT);
2298
2299 /* Set the upar bit */
2300 data = (i == 1) ? 0x0 : 0x1;
2301 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2302 data << DPIO_UPAR_SHIFT);
2303 }
2304
2305 /* Data lane stagger programming */
2306 /* FIXME: Fix up value only after power analysis */
2307
2308 mutex_unlock(&dev_priv->dpio_lock);
2309
2310 if (is_edp(intel_dp)) {
2311 /* init power sequencer on this pipe and port */
2312 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2313 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2314 &power_seq);
2315 }
2316
2317 intel_enable_dp(encoder);
2318
2319 vlv_wait_port_ready(dev_priv, dport);
2320}
2321
9197c88b
VS		 2322static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2323{
2324 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2325 struct drm_device *dev = encoder->base.dev;
2326 struct drm_i915_private *dev_priv = dev->dev_private;
2327 struct intel_crtc *intel_crtc =
2328 to_intel_crtc(encoder->base.crtc);
2329 enum dpio_channel ch = vlv_dport_to_channel(dport);
2330 enum pipe pipe = intel_crtc->pipe;
2331 u32 val;
2332
625695f8
VS		 2333 intel_dp_prepare(encoder);
2334
9197c88b
VS		 2335 mutex_lock(&dev_priv->dpio_lock);
2336
b9e5ac3c
VS		 2337 /* program left/right clock distribution */
2338 if (pipe != PIPE_B) {
2339 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2340 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2341 if (ch == DPIO_CH0)
2342 val |= CHV_BUFLEFTENA1_FORCE;
2343 if (ch == DPIO_CH1)
2344 val |= CHV_BUFRIGHTENA1_FORCE;
2345 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2346 } else {
2347 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2348 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2349 if (ch == DPIO_CH0)
2350 val |= CHV_BUFLEFTENA2_FORCE;
2351 if (ch == DPIO_CH1)
2352 val |= CHV_BUFRIGHTENA2_FORCE;
2353 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2354 }
2355
9197c88b
VS		 2356 /* program clock channel usage */
2357 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2358 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2359 if (pipe != PIPE_B)
2360 val &= ~CHV_PCS_USEDCLKCHANNEL;
2361 else
2362 val |= CHV_PCS_USEDCLKCHANNEL;
2363 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2364
2365 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2366 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2367 if (pipe != PIPE_B)
2368 val &= ~CHV_PCS_USEDCLKCHANNEL;
2369 else
2370 val |= CHV_PCS_USEDCLKCHANNEL;
2371 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2372
2373 /*
2374 * This a a bit weird since generally CL
2375 * matches the pipe, but here we need to
2376 * pick the CL based on the port.
2377 */
2378 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2379 if (pipe != PIPE_B)
2380 val &= ~CHV_CMN_USEDCLKCHANNEL;
2381 else
2382 val |= CHV_CMN_USEDCLKCHANNEL;
2383 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2384
2385 mutex_unlock(&dev_priv->dpio_lock);
2386}
2387
a4fc5ed6 2388/*
df0c237d
JB		 2389 * Native read with retry for link status and receiver capability reads for
2390 * cases where the sink may still be asleep.
9d1a1031
JN		 2391 *
2392 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2393 * supposed to retry 3 times per the spec.
a4fc5ed6 2394 */
9d1a1031
JN		 2395static ssize_t
2396intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2397 void *buffer, size_t size)
a4fc5ed6 2398{
9d1a1031
JN		 2399 ssize_t ret;
2400 int i;
61da5fab 2401
61da5fab 2402 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2403 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2404 if (ret == size)
2405 return ret;
61da5fab
JB		 2406 msleep(1);
2407 }
a4fc5ed6 2408
9d1a1031 2409 return ret;
a4fc5ed6
KP		 2410}
2411
2412/*
2413 * Fetch AUX CH registers 0x202 - 0x207 which contain
2414 * link status information
2415 */
2416static bool
93f62dad 2417intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2418{
9d1a1031
JN		 2419 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2420 DP_LANE0_1_STATUS,
2421 link_status,
2422 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2423}
2424
1100244e 2425/* These are source-specific values. */
a4fc5ed6 2426static uint8_t
1a2eb460 2427intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2428{
30add22d 2429 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2430 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2431
9576c27f 2432 if (IS_VALLEYVIEW(dev))
e2fa6fba 2433 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2434 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2435 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2436 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2437 return DP_TRAIN_VOLTAGE_SWING_1200;
2438 else
2439 return DP_TRAIN_VOLTAGE_SWING_800;
2440}
2441
2442static uint8_t
2443intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2444{
30add22d 2445 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2446 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2447
9576c27f 2448 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722
PZ		 2449 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2450 case DP_TRAIN_VOLTAGE_SWING_400:
2451 return DP_TRAIN_PRE_EMPHASIS_9_5;
2452 case DP_TRAIN_VOLTAGE_SWING_600:
2453 return DP_TRAIN_PRE_EMPHASIS_6;
2454 case DP_TRAIN_VOLTAGE_SWING_800:
2455 return DP_TRAIN_PRE_EMPHASIS_3_5;
2456 case DP_TRAIN_VOLTAGE_SWING_1200:
2457 default:
2458 return DP_TRAIN_PRE_EMPHASIS_0;
2459 }
e2fa6fba
P		 2460 } else if (IS_VALLEYVIEW(dev)) {
2461 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2462 case DP_TRAIN_VOLTAGE_SWING_400:
2463 return DP_TRAIN_PRE_EMPHASIS_9_5;
2464 case DP_TRAIN_VOLTAGE_SWING_600:
2465 return DP_TRAIN_PRE_EMPHASIS_6;
2466 case DP_TRAIN_VOLTAGE_SWING_800:
2467 return DP_TRAIN_PRE_EMPHASIS_3_5;
2468 case DP_TRAIN_VOLTAGE_SWING_1200:
2469 default:
2470 return DP_TRAIN_PRE_EMPHASIS_0;
2471 }
bc7d38a4 2472 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2473 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2474 case DP_TRAIN_VOLTAGE_SWING_400:
2475 return DP_TRAIN_PRE_EMPHASIS_6;
2476 case DP_TRAIN_VOLTAGE_SWING_600:
2477 case DP_TRAIN_VOLTAGE_SWING_800:
2478 return DP_TRAIN_PRE_EMPHASIS_3_5;
2479 default:
2480 return DP_TRAIN_PRE_EMPHASIS_0;
2481 }
2482 } else {
2483 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2484 case DP_TRAIN_VOLTAGE_SWING_400:
2485 return DP_TRAIN_PRE_EMPHASIS_6;
2486 case DP_TRAIN_VOLTAGE_SWING_600:
2487 return DP_TRAIN_PRE_EMPHASIS_6;
2488 case DP_TRAIN_VOLTAGE_SWING_800:
2489 return DP_TRAIN_PRE_EMPHASIS_3_5;
2490 case DP_TRAIN_VOLTAGE_SWING_1200:
2491 default:
2492 return DP_TRAIN_PRE_EMPHASIS_0;
2493 }
a4fc5ed6
KP		 2494 }
2495}
2496
e2fa6fba
P		 2497static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2498{
2499 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2500 struct drm_i915_private *dev_priv = dev->dev_private;
2501 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2502 struct intel_crtc *intel_crtc =
2503 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2504 unsigned long demph_reg_value, preemph_reg_value,
2505 uniqtranscale_reg_value;
2506 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2507 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2508 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2509
2510 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2511 case DP_TRAIN_PRE_EMPHASIS_0:
2512 preemph_reg_value = 0x0004000;
2513 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2514 case DP_TRAIN_VOLTAGE_SWING_400:
2515 demph_reg_value = 0x2B405555;
2516 uniqtranscale_reg_value = 0x552AB83A;
2517 break;
2518 case DP_TRAIN_VOLTAGE_SWING_600:
2519 demph_reg_value = 0x2B404040;
2520 uniqtranscale_reg_value = 0x5548B83A;
2521 break;
2522 case DP_TRAIN_VOLTAGE_SWING_800:
2523 demph_reg_value = 0x2B245555;
2524 uniqtranscale_reg_value = 0x5560B83A;
2525 break;
2526 case DP_TRAIN_VOLTAGE_SWING_1200:
2527 demph_reg_value = 0x2B405555;
2528 uniqtranscale_reg_value = 0x5598DA3A;
2529 break;
2530 default:
2531 return 0;
2532 }
2533 break;
2534 case DP_TRAIN_PRE_EMPHASIS_3_5:
2535 preemph_reg_value = 0x0002000;
2536 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2537 case DP_TRAIN_VOLTAGE_SWING_400:
2538 demph_reg_value = 0x2B404040;
2539 uniqtranscale_reg_value = 0x5552B83A;
2540 break;
2541 case DP_TRAIN_VOLTAGE_SWING_600:
2542 demph_reg_value = 0x2B404848;
2543 uniqtranscale_reg_value = 0x5580B83A;
2544 break;
2545 case DP_TRAIN_VOLTAGE_SWING_800:
2546 demph_reg_value = 0x2B404040;
2547 uniqtranscale_reg_value = 0x55ADDA3A;
2548 break;
2549 default:
2550 return 0;
2551 }
2552 break;
2553 case DP_TRAIN_PRE_EMPHASIS_6:
2554 preemph_reg_value = 0x0000000;
2555 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2556 case DP_TRAIN_VOLTAGE_SWING_400:
2557 demph_reg_value = 0x2B305555;
2558 uniqtranscale_reg_value = 0x5570B83A;
2559 break;
2560 case DP_TRAIN_VOLTAGE_SWING_600:
2561 demph_reg_value = 0x2B2B4040;
2562 uniqtranscale_reg_value = 0x55ADDA3A;
2563 break;
2564 default:
2565 return 0;
2566 }
2567 break;
2568 case DP_TRAIN_PRE_EMPHASIS_9_5:
2569 preemph_reg_value = 0x0006000;
2570 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2571 case DP_TRAIN_VOLTAGE_SWING_400:
2572 demph_reg_value = 0x1B405555;
2573 uniqtranscale_reg_value = 0x55ADDA3A;
2574 break;
2575 default:
2576 return 0;
2577 }
2578 break;
2579 default:
2580 return 0;
2581 }
2582
0980a60f 2583 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2584 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2585 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2586 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2587 uniqtranscale_reg_value);
ab3c759a
CML		 2588 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2589 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2590 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2591 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2592 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2593
2594 return 0;
2595}
2596
e4a1d846
CML		 2597static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2598{
2599 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2600 struct drm_i915_private *dev_priv = dev->dev_private;
2601 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2602 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2603 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2604 uint8_t train_set = intel_dp->train_set[0];
2605 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2606 enum pipe pipe = intel_crtc->pipe;
2607 int i;
e4a1d846
CML		 2608
2609 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2610 case DP_TRAIN_PRE_EMPHASIS_0:
2611 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2612 case DP_TRAIN_VOLTAGE_SWING_400:
2613 deemph_reg_value = 128;
2614 margin_reg_value = 52;
2615 break;
2616 case DP_TRAIN_VOLTAGE_SWING_600:
2617 deemph_reg_value = 128;
2618 margin_reg_value = 77;
2619 break;
2620 case DP_TRAIN_VOLTAGE_SWING_800:
2621 deemph_reg_value = 128;
2622 margin_reg_value = 102;
2623 break;
2624 case DP_TRAIN_VOLTAGE_SWING_1200:
2625 deemph_reg_value = 128;
2626 margin_reg_value = 154;
2627 /* FIXME extra to set for 1200 */
2628 break;
2629 default:
2630 return 0;
2631 }
2632 break;
2633 case DP_TRAIN_PRE_EMPHASIS_3_5:
2634 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2635 case DP_TRAIN_VOLTAGE_SWING_400:
2636 deemph_reg_value = 85;
2637 margin_reg_value = 78;
2638 break;
2639 case DP_TRAIN_VOLTAGE_SWING_600:
2640 deemph_reg_value = 85;
2641 margin_reg_value = 116;
2642 break;
2643 case DP_TRAIN_VOLTAGE_SWING_800:
2644 deemph_reg_value = 85;
2645 margin_reg_value = 154;
2646 break;
2647 default:
2648 return 0;
2649 }
2650 break;
2651 case DP_TRAIN_PRE_EMPHASIS_6:
2652 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2653 case DP_TRAIN_VOLTAGE_SWING_400:
2654 deemph_reg_value = 64;
2655 margin_reg_value = 104;
2656 break;
2657 case DP_TRAIN_VOLTAGE_SWING_600:
2658 deemph_reg_value = 64;
2659 margin_reg_value = 154;
2660 break;
2661 default:
2662 return 0;
2663 }
2664 break;
2665 case DP_TRAIN_PRE_EMPHASIS_9_5:
2666 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2667 case DP_TRAIN_VOLTAGE_SWING_400:
2668 deemph_reg_value = 43;
2669 margin_reg_value = 154;
2670 break;
2671 default:
2672 return 0;
2673 }
2674 break;
2675 default:
2676 return 0;
2677 }
2678
2679 mutex_lock(&dev_priv->dpio_lock);
2680
2681 /* Clear calc init */
1966e59e
VS		 2682 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2683 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2684 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2685
2686 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2687 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2688 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2689
2690 /* Program swing deemph */
f72df8db
VS		 2691 for (i = 0; i < 4; i++) {
2692 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2693 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2694 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2695 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2696 }
e4a1d846
CML		 2697
2698 /* Program swing margin */
f72df8db
VS		 2699 for (i = 0; i < 4; i++) {
2700 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 2701 val &= ~DPIO_SWING_MARGIN000_MASK;
2702 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 2703 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2704 }
e4a1d846
CML		 2705
2706 /* Disable unique transition scale */
f72df8db
VS		 2707 for (i = 0; i < 4; i++) {
2708 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2709 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2710 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2711 }
e4a1d846
CML		 2712
2713 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2714 == DP_TRAIN_PRE_EMPHASIS_0) &&
2715 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2716 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2717
2718 /*
2719 * The document said it needs to set bit 27 for ch0 and bit 26
2720 * for ch1. Might be a typo in the doc.
2721 * For now, for this unique transition scale selection, set bit
2722 * 27 for ch0 and ch1.
2723 */
f72df8db
VS		 2724 for (i = 0; i < 4; i++) {
2725 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2726 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2727 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2728 }
e4a1d846 2729
f72df8db
VS		 2730 for (i = 0; i < 4; i++) {
2731 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2732 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2733 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2734 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2735 }
e4a1d846
CML		 2736 }
2737
2738 /* Start swing calculation */
1966e59e
VS		 2739 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2740 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2741 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2742
2743 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2744 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2745 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2746
2747 /* LRC Bypass */
2748 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2749 val |= DPIO_LRC_BYPASS;
2750 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2751
2752 mutex_unlock(&dev_priv->dpio_lock);
2753
2754 return 0;
2755}
2756
a4fc5ed6 2757static void
0301b3ac
JN		 2758intel_get_adjust_train(struct intel_dp *intel_dp,
2759 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2760{
2761 uint8_t v = 0;
2762 uint8_t p = 0;
2763 int lane;
1a2eb460
KP		 2764 uint8_t voltage_max;
2765 uint8_t preemph_max;
a4fc5ed6 2766
33a34e4e 2767 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2768 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2769 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2770
2771 if (this_v > v)
2772 v = this_v;
2773 if (this_p > p)
2774 p = this_p;
2775 }
2776
1a2eb460 2777 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2778 if (v >= voltage_max)
2779 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2780
1a2eb460
KP		 2781 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2782 if (p >= preemph_max)
2783 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2784
2785 for (lane = 0; lane < 4; lane++)
33a34e4e 2786 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2787}
2788
2789static uint32_t
f0a3424e 2790intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2791{
3cf2efb1 2792 uint32_t signal_levels = 0;
a4fc5ed6 2793
3cf2efb1 2794 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2795 case DP_TRAIN_VOLTAGE_SWING_400:
2796 default:
2797 signal_levels |= DP_VOLTAGE_0_4;
2798 break;
2799 case DP_TRAIN_VOLTAGE_SWING_600:
2800 signal_levels |= DP_VOLTAGE_0_6;
2801 break;
2802 case DP_TRAIN_VOLTAGE_SWING_800:
2803 signal_levels |= DP_VOLTAGE_0_8;
2804 break;
2805 case DP_TRAIN_VOLTAGE_SWING_1200:
2806 signal_levels |= DP_VOLTAGE_1_2;
2807 break;
2808 }
3cf2efb1 2809 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2810 case DP_TRAIN_PRE_EMPHASIS_0:
2811 default:
2812 signal_levels |= DP_PRE_EMPHASIS_0;
2813 break;
2814 case DP_TRAIN_PRE_EMPHASIS_3_5:
2815 signal_levels |= DP_PRE_EMPHASIS_3_5;
2816 break;
2817 case DP_TRAIN_PRE_EMPHASIS_6:
2818 signal_levels |= DP_PRE_EMPHASIS_6;
2819 break;
2820 case DP_TRAIN_PRE_EMPHASIS_9_5:
2821 signal_levels |= DP_PRE_EMPHASIS_9_5;
2822 break;
2823 }
2824 return signal_levels;
2825}
2826
e3421a18
ZW		 2827/* Gen6's DP voltage swing and pre-emphasis control */
2828static uint32_t
2829intel_gen6_edp_signal_levels(uint8_t train_set)
2830{
3c5a62b5
YL		 2831 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2832 DP_TRAIN_PRE_EMPHASIS_MASK);
2833 switch (signal_levels) {
e3421a18 2834 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2835 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2836 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2837 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2838 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2839 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2840 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2841 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2842 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2843 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2844 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2845 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2846 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2847 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2848 default:
3c5a62b5
YL		 2849 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2850 "0x%x\n", signal_levels);
2851 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2852 }
2853}
2854
1a2eb460
KP		 2855/* Gen7's DP voltage swing and pre-emphasis control */
2856static uint32_t
2857intel_gen7_edp_signal_levels(uint8_t train_set)
2858{
2859 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2860 DP_TRAIN_PRE_EMPHASIS_MASK);
2861 switch (signal_levels) {
2862 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2863 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2864 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2865 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2866 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2867 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2868
2869 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2870 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2871 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2872 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2873
2874 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2875 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2876 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2877 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2878
2879 default:
2880 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2881 "0x%x\n", signal_levels);
2882 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2883 }
2884}
2885
d6c0d722
PZ		 2886/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2887static uint32_t
f0a3424e 2888intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2889{
d6c0d722
PZ		 2890 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2891 DP_TRAIN_PRE_EMPHASIS_MASK);
2892 switch (signal_levels) {
2893 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2894 return DDI_BUF_EMP_400MV_0DB_HSW;
2895 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2896 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2897 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2898 return DDI_BUF_EMP_400MV_6DB_HSW;
2899 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2900 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2901
d6c0d722
PZ		 2902 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2903 return DDI_BUF_EMP_600MV_0DB_HSW;
2904 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2905 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2906 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2907 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2908
d6c0d722
PZ		 2909 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2910 return DDI_BUF_EMP_800MV_0DB_HSW;
2911 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2912 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2913 default:
2914 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2915 "0x%x\n", signal_levels);
2916 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2917 }
a4fc5ed6
KP		 2918}
2919
f0a3424e
PZ		 2920/* Properly updates "DP" with the correct signal levels. */
2921static void
2922intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2923{
2924 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2925 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2926 struct drm_device *dev = intel_dig_port->base.base.dev;
2927 uint32_t signal_levels, mask;
2928 uint8_t train_set = intel_dp->train_set[0];
2929
9576c27f 2930 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 2931 signal_levels = intel_hsw_signal_levels(train_set);
2932 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2933 } else if (IS_CHERRYVIEW(dev)) {
2934 signal_levels = intel_chv_signal_levels(intel_dp);
2935 mask = 0;
e2fa6fba
P		 2936 } else if (IS_VALLEYVIEW(dev)) {
2937 signal_levels = intel_vlv_signal_levels(intel_dp);
2938 mask = 0;
bc7d38a4 2939 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2940 signal_levels = intel_gen7_edp_signal_levels(train_set);
2941 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2942 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2943 signal_levels = intel_gen6_edp_signal_levels(train_set);
2944 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2945 } else {
2946 signal_levels = intel_gen4_signal_levels(train_set);
2947 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2948 }
2949
2950 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2951
2952 *DP = (*DP & ~mask) | signal_levels;
2953}
2954
a4fc5ed6 2955static bool
ea5b213a 2956intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2957 uint32_t *DP,
58e10eb9 2958 uint8_t dp_train_pat)
a4fc5ed6 2959{
174edf1f
PZ		 2960 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2961 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2962 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2963 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2964 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2965 int ret, len;
a4fc5ed6 2966
22b8bf17 2967 if (HAS_DDI(dev)) {
3ab9c637 2968 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2969
2970 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2971 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2972 else
2973 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2974
2975 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2976 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2977 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2978 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2979
2980 break;
2981 case DP_TRAINING_PATTERN_1:
2982 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2983 break;
2984 case DP_TRAINING_PATTERN_2:
2985 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2986 break;
2987 case DP_TRAINING_PATTERN_3:
2988 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2989 break;
2990 }
174edf1f 2991 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2992
bc7d38a4 2993 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2994 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2995
2996 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2997 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2998 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2999 break;
3000 case DP_TRAINING_PATTERN_1:
70aff66c 3001 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 3002 break;
3003 case DP_TRAINING_PATTERN_2:
70aff66c 3004 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 3005 break;
3006 case DP_TRAINING_PATTERN_3:
3007 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 3008 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 3009 break;
3010 }
3011
3012 } else {
aad3d14d
VS		 3013 if (IS_CHERRYVIEW(dev))
3014 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
3015 else
3016 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 3017
3018 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3019 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 3020 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 3021 break;
3022 case DP_TRAINING_PATTERN_1:
70aff66c 3023 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 3024 break;
3025 case DP_TRAINING_PATTERN_2:
70aff66c 3026 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 3027 break;
3028 case DP_TRAINING_PATTERN_3:
aad3d14d
VS		 3029 if (IS_CHERRYVIEW(dev)) {
3030 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
3031 } else {
3032 DRM_ERROR("DP training pattern 3 not supported\n");
3033 *DP |= DP_LINK_TRAIN_PAT_2;
3034 }
47ea7542
PZ		 3035 break;
3036 }
3037 }
3038
70aff66c 3039 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3040 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3041
2cdfe6c8
JN		 3042 buf[0] = dp_train_pat;
3043 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3044 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3045 /* don't write DP_TRAINING_LANEx_SET on disable */
3046 len = 1;
3047 } else {
3048 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3049 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3050 len = intel_dp->lane_count + 1;
47ea7542 3051 }
a4fc5ed6 3052
9d1a1031
JN		 3053 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3054 buf, len);
2cdfe6c8
JN		 3055
3056 return ret == len;
a4fc5ed6
KP		 3057}
3058
70aff66c
JN		 3059static bool
3060intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3061 uint8_t dp_train_pat)
3062{
953d22e8 3063 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3064 intel_dp_set_signal_levels(intel_dp, DP);
3065 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3066}
3067
3068static bool
3069intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3070 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3071{
3072 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3073 struct drm_device *dev = intel_dig_port->base.base.dev;
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075 int ret;
3076
3077 intel_get_adjust_train(intel_dp, link_status);
3078 intel_dp_set_signal_levels(intel_dp, DP);
3079
3080 I915_WRITE(intel_dp->output_reg, *DP);
3081 POSTING_READ(intel_dp->output_reg);
3082
9d1a1031
JN		 3083 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3084 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3085
3086 return ret == intel_dp->lane_count;
3087}
3088
3ab9c637
ID		 3089static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3090{
3091 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3092 struct drm_device *dev = intel_dig_port->base.base.dev;
3093 struct drm_i915_private *dev_priv = dev->dev_private;
3094 enum port port = intel_dig_port->port;
3095 uint32_t val;
3096
3097 if (!HAS_DDI(dev))
3098 return;
3099
3100 val = I915_READ(DP_TP_CTL(port));
3101 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3102 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3103 I915_WRITE(DP_TP_CTL(port), val);
3104
3105 /*
3106 * On PORT_A we can have only eDP in SST mode. There the only reason
3107 * we need to set idle transmission mode is to work around a HW issue
3108 * where we enable the pipe while not in idle link-training mode.
3109 * In this case there is requirement to wait for a minimum number of
3110 * idle patterns to be sent.
3111 */
3112 if (port == PORT_A)
3113 return;
3114
3115 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3116 1))
3117 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3118}
3119
33a34e4e 3120/* Enable corresponding port and start training pattern 1 */
c19b0669 3121void
33a34e4e 3122intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3123{
da63a9f2 3124 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3125 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3126 int i;
3127 uint8_t voltage;
cdb0e95b 3128 int voltage_tries, loop_tries;
ea5b213a 3129 uint32_t DP = intel_dp->DP;
6aba5b6c 3130 uint8_t link_config[2];
a4fc5ed6 3131
affa9354 3132 if (HAS_DDI(dev))
c19b0669
PZ		 3133 intel_ddi_prepare_link_retrain(encoder);
3134
3cf2efb1 3135 /* Write the link configuration data */
6aba5b6c
JN		 3136 link_config[0] = intel_dp->link_bw;
3137 link_config[1] = intel_dp->lane_count;
3138 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3139 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3140 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3141
3142 link_config[0] = 0;
3143 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3144 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3145
3146 DP |= DP_PORT_EN;
1a2eb460 3147
70aff66c
JN		 3148 /* clock recovery */
3149 if (!intel_dp_reset_link_train(intel_dp, &DP,
3150 DP_TRAINING_PATTERN_1 |
3151 DP_LINK_SCRAMBLING_DISABLE)) {
3152 DRM_ERROR("failed to enable link training\n");
3153 return;
3154 }
3155
a4fc5ed6 3156 voltage = 0xff;
cdb0e95b
KP		 3157 voltage_tries = 0;
3158 loop_tries = 0;
a4fc5ed6 3159 for (;;) {
70aff66c 3160 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3161
a7c9655f 3162 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3163 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3164 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3165 break;
93f62dad 3166 }
a4fc5ed6 3167
01916270 3168 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3169 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3170 break;
3171 }
3172
3173 /* Check to see if we've tried the max voltage */
3174 for (i = 0; i < intel_dp->lane_count; i++)
3175 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3176 break;
3b4f819d 3177 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3178 ++loop_tries;
3179 if (loop_tries == 5) {
3def84b3 3180 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3181 break;
3182 }
70aff66c
JN		 3183 intel_dp_reset_link_train(intel_dp, &DP,
3184 DP_TRAINING_PATTERN_1 |
3185 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3186 voltage_tries = 0;
3187 continue;
3188 }
a4fc5ed6 3189
3cf2efb1 3190 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3191 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3192 ++voltage_tries;
b06fbda3 3193 if (voltage_tries == 5) {
3def84b3 3194 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3195 break;
3196 }
3197 } else
3198 voltage_tries = 0;
3199 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3200
70aff66c
JN		 3201 /* Update training set as requested by target */
3202 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3203 DRM_ERROR("failed to update link training\n");
3204 break;
3205 }
a4fc5ed6
KP		 3206 }
3207
33a34e4e
JB		 3208 intel_dp->DP = DP;
3209}
3210
c19b0669 3211void
33a34e4e
JB		 3212intel_dp_complete_link_train(struct intel_dp *intel_dp)
3213{
33a34e4e 3214 bool channel_eq = false;
37f80975 3215 int tries, cr_tries;
33a34e4e 3216 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3217 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3218
3219 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3220 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3221 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3222
a4fc5ed6 3223 /* channel equalization */
70aff66c 3224 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3225 training_pattern |
70aff66c
JN		 3226 DP_LINK_SCRAMBLING_DISABLE)) {
3227 DRM_ERROR("failed to start channel equalization\n");
3228 return;
3229 }
3230
a4fc5ed6 3231 tries = 0;
37f80975 3232 cr_tries = 0;
a4fc5ed6
KP		 3233 channel_eq = false;
3234 for (;;) {
70aff66c 3235 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3236
37f80975
JB		 3237 if (cr_tries > 5) {
3238 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3239 break;
3240 }
3241
a7c9655f 3242 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3243 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3244 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3245 break;
70aff66c 3246 }
a4fc5ed6 3247
37f80975 3248 /* Make sure clock is still ok */
01916270 3249 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3250 intel_dp_start_link_train(intel_dp);
70aff66c 3251 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3252 training_pattern |
70aff66c 3253 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3254 cr_tries++;
3255 continue;
3256 }
3257
1ffdff13 3258 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3259 channel_eq = true;
3260 break;
3261 }
a4fc5ed6 3262
37f80975
JB		 3263 /* Try 5 times, then try clock recovery if that fails */
3264 if (tries > 5) {
3265 intel_dp_link_down(intel_dp);
3266 intel_dp_start_link_train(intel_dp);
70aff66c 3267 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3268 training_pattern |
70aff66c 3269 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3270 tries = 0;
3271 cr_tries++;
3272 continue;
3273 }
a4fc5ed6 3274
70aff66c
JN		 3275 /* Update training set as requested by target */
3276 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3277 DRM_ERROR("failed to update link training\n");
3278 break;
3279 }
3cf2efb1 3280 ++tries;
869184a6 3281 }
3cf2efb1 3282
3ab9c637
ID		 3283 intel_dp_set_idle_link_train(intel_dp);
3284
3285 intel_dp->DP = DP;
3286
d6c0d722 3287 if (channel_eq)
07f42258 3288 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3289
3ab9c637
ID		 3290}
3291
3292void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3293{
70aff66c 3294 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3295 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3296}
3297
3298static void
ea5b213a 3299intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3300{
da63a9f2 3301 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3302 enum port port = intel_dig_port->port;
da63a9f2 3303 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3304 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3305 struct intel_crtc *intel_crtc =
3306 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3307 uint32_t DP = intel_dp->DP;
a4fc5ed6 3308
bc76e320 3309 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3310 return;
3311
0c33d8d7 3312 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3313 return;
3314
28c97730 3315 DRM_DEBUG_KMS("\n");
32f9d658 3316
bc7d38a4 3317 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3318 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3319 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3320 } else {
aad3d14d
VS		 3321 if (IS_CHERRYVIEW(dev))
3322 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3323 else
3324 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3325 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3326 }
fe255d00 3327 POSTING_READ(intel_dp->output_reg);
5eb08b69 3328
493a7081 3329 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3330 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3331 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3332
5bddd17f
EA		 3333 /* Hardware workaround: leaving our transcoder select
3334 * set to transcoder B while it's off will prevent the
3335 * corresponding HDMI output on transcoder A.
3336 *
3337 * Combine this with another hardware workaround:
3338 * transcoder select bit can only be cleared while the
3339 * port is enabled.
3340 */
3341 DP &= ~DP_PIPEB_SELECT;
3342 I915_WRITE(intel_dp->output_reg, DP);
3343
3344 /* Changes to enable or select take place the vblank
3345 * after being written.
3346 */
ff50afe9
DV		 3347 if (WARN_ON(crtc == NULL)) {
3348 /* We should never try to disable a port without a crtc
3349 * attached. For paranoia keep the code around for a
3350 * bit. */
31acbcc4
CW		 3351 POSTING_READ(intel_dp->output_reg);
3352 msleep(50);
3353 } else
ab527efc 3354 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3355 }
3356
832afda6 3357 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3358 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3359 POSTING_READ(intel_dp->output_reg);
f01eca2e 3360 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3361}
3362
26d61aad
KP		 3363static bool
3364intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3365{
a031d709
RV		 3366 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3367 struct drm_device *dev = dig_port->base.base.dev;
3368 struct drm_i915_private *dev_priv = dev->dev_private;
3369
577c7a50
DL		 3370 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3371
9d1a1031
JN		 3372 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3373 sizeof(intel_dp->dpcd)) < 0)
edb39244 3374 return false; /* aux transfer failed */
92fd8fd1 3375
577c7a50
DL		 3376 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3377 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3378 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3379
edb39244
AJ		 3380 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3381 return false; /* DPCD not present */
3382
2293bb5c
SK		 3383 /* Check if the panel supports PSR */
3384 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3385 if (is_edp(intel_dp)) {
9d1a1031
JN		 3386 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3387 intel_dp->psr_dpcd,
3388 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3389 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3390 dev_priv->psr.sink_support = true;
50003939 3391 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3392 }
50003939
JN		 3393 }
3394
06ea66b6
TP		 3395 /* Training Pattern 3 support */
3396 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3397 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3398 intel_dp->use_tps3 = true;
3399 DRM_DEBUG_KMS("Displayport TPS3 supported");
3400 } else
3401 intel_dp->use_tps3 = false;
3402
edb39244
AJ		 3403 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3404 DP_DWN_STRM_PORT_PRESENT))
3405 return true; /* native DP sink */
3406
3407 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3408 return true; /* no per-port downstream info */
3409
9d1a1031
JN		 3410 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3411 intel_dp->downstream_ports,
3412 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3413 return false; /* downstream port status fetch failed */
3414
3415 return true;
92fd8fd1
KP		 3416}
3417
0d198328
AJ		 3418static void
3419intel_dp_probe_oui(struct intel_dp *intel_dp)
3420{
3421 u8 buf[3];
3422
3423 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3424 return;
3425
24f3e092 3426 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3427
9d1a1031 3428 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3429 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3430 buf[0], buf[1], buf[2]);
3431
9d1a1031 3432 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3433 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3434 buf[0], buf[1], buf[2]);
351cfc34 3435
1e0560e0 3436 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3437}
3438
0e32b39c
DA		 3439static bool
3440intel_dp_probe_mst(struct intel_dp *intel_dp)
3441{
3442 u8 buf[1];
3443
3444 if (!intel_dp->can_mst)
3445 return false;
3446
3447 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3448 return false;
3449
d337a341 3450 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3451 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3452 if (buf[0] & DP_MST_CAP) {
3453 DRM_DEBUG_KMS("Sink is MST capable\n");
3454 intel_dp->is_mst = true;
3455 } else {
3456 DRM_DEBUG_KMS("Sink is not MST capable\n");
3457 intel_dp->is_mst = false;
3458 }
3459 }
1e0560e0 3460 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3461
3462 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3463 return intel_dp->is_mst;
3464}
3465
d2e216d0
RV		 3466int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3467{
3468 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3469 struct drm_device *dev = intel_dig_port->base.base.dev;
3470 struct intel_crtc *intel_crtc =
3471 to_intel_crtc(intel_dig_port->base.base.crtc);
3472 u8 buf[1];
3473
9d1a1031 3474 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3475 return -EAGAIN;
3476
3477 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3478 return -ENOTTY;
3479
9d1a1031
JN		 3480 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3481 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3482 return -EAGAIN;
3483
3484 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3485 intel_wait_for_vblank(dev, intel_crtc->pipe);
3486 intel_wait_for_vblank(dev, intel_crtc->pipe);
3487
9d1a1031 3488 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3489 return -EAGAIN;
3490
9d1a1031 3491 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3492 return 0;
3493}
3494
a60f0e38
JB		 3495static bool
3496intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3497{
9d1a1031
JN		 3498 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3499 DP_DEVICE_SERVICE_IRQ_VECTOR,
3500 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3501}
3502
0e32b39c
DA		 3503static bool
3504intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3505{
3506 int ret;
3507
3508 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3509 DP_SINK_COUNT_ESI,
3510 sink_irq_vector, 14);
3511 if (ret != 14)
3512 return false;
3513
3514 return true;
3515}
3516
a60f0e38
JB		 3517static void
3518intel_dp_handle_test_request(struct intel_dp *intel_dp)
3519{
3520 /* NAK by default */
9d1a1031 3521 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3522}
3523
0e32b39c
DA		 3524static int
3525intel_dp_check_mst_status(struct intel_dp *intel_dp)
3526{
3527 bool bret;
3528
3529 if (intel_dp->is_mst) {
3530 u8 esi[16] = { 0 };
3531 int ret = 0;
3532 int retry;
3533 bool handled;
3534 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3535go_again:
3536 if (bret == true) {
3537
3538 /* check link status - esi[10] = 0x200c */
3539 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3540 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3541 intel_dp_start_link_train(intel_dp);
3542 intel_dp_complete_link_train(intel_dp);
3543 intel_dp_stop_link_train(intel_dp);
3544 }
3545
3546 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3547 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3548
3549 if (handled) {
3550 for (retry = 0; retry < 3; retry++) {
3551 int wret;
3552 wret = drm_dp_dpcd_write(&intel_dp->aux,
3553 DP_SINK_COUNT_ESI+1,
3554 &esi[1], 3);
3555 if (wret == 3) {
3556 break;
3557 }
3558 }
3559
3560 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3561 if (bret == true) {
3562 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3563 goto go_again;
3564 }
3565 } else
3566 ret = 0;
3567
3568 return ret;
3569 } else {
3570 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3571 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3572 intel_dp->is_mst = false;
3573 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3574 /* send a hotplug event */
3575 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3576 }
3577 }
3578 return -EINVAL;
3579}
3580
a4fc5ed6
KP		 3581/*
3582 * According to DP spec
3583 * 5.1.2:
3584 * 1. Read DPCD
3585 * 2. Configure link according to Receiver Capabilities
3586 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3587 * 4. Check link status on receipt of hot-plug interrupt
3588 */
00c09d70 3589void
ea5b213a 3590intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3591{
5b215bcf 3592 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3593 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3594 u8 sink_irq_vector;
93f62dad 3595 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3596
5b215bcf
DA		 3597 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3598
da63a9f2 3599 if (!intel_encoder->connectors_active)
d2b996ac 3600 return;
59cd09e1 3601
da63a9f2 3602 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3603 return;
3604
1a125d8a
ID		 3605 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3606 return;
3607
92fd8fd1 3608 /* Try to read receiver status if the link appears to be up */
93f62dad 3609 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3610 return;
3611 }
3612
92fd8fd1 3613 /* Now read the DPCD to see if it's actually running */
26d61aad 3614 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3615 return;
3616 }
3617
a60f0e38
JB		 3618 /* Try to read the source of the interrupt */
3619 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3620 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3621 /* Clear interrupt source */
9d1a1031
JN		 3622 drm_dp_dpcd_writeb(&intel_dp->aux,
3623 DP_DEVICE_SERVICE_IRQ_VECTOR,
3624 sink_irq_vector);
a60f0e38
JB		 3625
3626 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3627 intel_dp_handle_test_request(intel_dp);
3628 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3629 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3630 }
3631
1ffdff13 3632 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3633 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3634 intel_encoder->base.name);
33a34e4e
JB		 3635 intel_dp_start_link_train(intel_dp);
3636 intel_dp_complete_link_train(intel_dp);
3ab9c637 3637 intel_dp_stop_link_train(intel_dp);
33a34e4e 3638 }
a4fc5ed6 3639}
a4fc5ed6 3640
caf9ab24 3641/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3642static enum drm_connector_status
26d61aad 3643intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3644{
caf9ab24 3645 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3646 uint8_t type;
3647
3648 if (!intel_dp_get_dpcd(intel_dp))
3649 return connector_status_disconnected;
3650
3651 /* if there's no downstream port, we're done */
3652 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3653 return connector_status_connected;
caf9ab24
AJ		 3654
3655 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3656 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3657 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3658 uint8_t reg;
9d1a1031
JN		 3659
3660 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3661 &reg, 1) < 0)
caf9ab24 3662 return connector_status_unknown;
9d1a1031 3663
23235177
AJ		 3664 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3665 : connector_status_disconnected;
caf9ab24
AJ		 3666 }
3667
3668 /* If no HPD, poke DDC gently */
0b99836f 3669 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3670 return connector_status_connected;
caf9ab24
AJ		 3671
3672 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3673 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3674 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3675 if (type == DP_DS_PORT_TYPE_VGA ||
3676 type == DP_DS_PORT_TYPE_NON_EDID)
3677 return connector_status_unknown;
3678 } else {
3679 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3680 DP_DWN_STRM_PORT_TYPE_MASK;
3681 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3682 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3683 return connector_status_unknown;
3684 }
caf9ab24
AJ		 3685
3686 /* Anything else is out of spec, warn and ignore */
3687 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3688 return connector_status_disconnected;
71ba9000
AJ		 3689}
3690
5eb08b69 3691static enum drm_connector_status
a9756bb5 3692ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3693{
30add22d 3694 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3695 struct drm_i915_private *dev_priv = dev->dev_private;
3696 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3697 enum drm_connector_status status;
3698
fe16d949
CW		 3699 /* Can't disconnect eDP, but you can close the lid... */
3700 if (is_edp(intel_dp)) {
30add22d 3701 status = intel_panel_detect(dev);
fe16d949
CW		 3702 if (status == connector_status_unknown)
3703 status = connector_status_connected;
3704 return status;
3705 }
01cb9ea6 3706
1b469639
DL		 3707 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3708 return connector_status_disconnected;
3709
26d61aad 3710 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3711}
3712
a4fc5ed6 3713static enum drm_connector_status
a9756bb5 3714g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3715{
30add22d 3716 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3717 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3718 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3719 uint32_t bit;
5eb08b69 3720
35aad75f
JB		 3721 /* Can't disconnect eDP, but you can close the lid... */
3722 if (is_edp(intel_dp)) {
3723 enum drm_connector_status status;
3724
3725 status = intel_panel_detect(dev);
3726 if (status == connector_status_unknown)
3727 status = connector_status_connected;
3728 return status;
3729 }
3730
232a6ee9
TP		 3731 if (IS_VALLEYVIEW(dev)) {
3732 switch (intel_dig_port->port) {
3733 case PORT_B:
3734 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3735 break;
3736 case PORT_C:
3737 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3738 break;
3739 case PORT_D:
3740 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3741 break;
3742 default:
3743 return connector_status_unknown;
3744 }
3745 } else {
3746 switch (intel_dig_port->port) {
3747 case PORT_B:
3748 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3749 break;
3750 case PORT_C:
3751 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3752 break;
3753 case PORT_D:
3754 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3755 break;
3756 default:
3757 return connector_status_unknown;
3758 }
a4fc5ed6
KP		 3759 }
3760
10f76a38 3761 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3762 return connector_status_disconnected;
3763
26d61aad 3764 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3765}
3766
8c241fef
KP		 3767static struct edid *
3768intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3769{
9cd300e0 3770 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3771
9cd300e0
JN		 3772 /* use cached edid if we have one */
3773 if (intel_connector->edid) {
9cd300e0
JN		 3774 /* invalid edid */
3775 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3776 return NULL;
3777
55e9edeb 3778 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3779 }
8c241fef 3780
9cd300e0 3781 return drm_get_edid(connector, adapter);
8c241fef
KP		 3782}
3783
3784static int
3785intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3786{
9cd300e0 3787 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3788
9cd300e0
JN		 3789 /* use cached edid if we have one */
3790 if (intel_connector->edid) {
3791 /* invalid edid */
3792 if (IS_ERR(intel_connector->edid))
3793 return 0;
3794
3795 return intel_connector_update_modes(connector,
3796 intel_connector->edid);
d6f24d0f
JB		 3797 }
3798
9cd300e0 3799 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3800}
3801
a9756bb5
ZW		 3802static enum drm_connector_status
3803intel_dp_detect(struct drm_connector *connector, bool force)
3804{
3805 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3806 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3807 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3808 struct drm_device *dev = connector->dev;
c8c8fb33 3809 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3810 enum drm_connector_status status;
671dedd2 3811 enum intel_display_power_domain power_domain;
a9756bb5 3812 struct edid *edid = NULL;
0e32b39c 3813 bool ret;
a9756bb5 3814
671dedd2
ID		 3815 power_domain = intel_display_port_power_domain(intel_encoder);
3816 intel_display_power_get(dev_priv, power_domain);
3817
164c8598 3818 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 3819 connector->base.id, connector->name);
164c8598 3820
0e32b39c
DA		 3821 if (intel_dp->is_mst) {
3822 /* MST devices are disconnected from a monitor POV */
3823 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3824 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3825 status = connector_status_disconnected;
3826 goto out;
3827 }
3828
a9756bb5
ZW		 3829 intel_dp->has_audio = false;
3830
3831 if (HAS_PCH_SPLIT(dev))
3832 status = ironlake_dp_detect(intel_dp);
3833 else
3834 status = g4x_dp_detect(intel_dp);
1b9be9d0 3835
a9756bb5 3836 if (status != connector_status_connected)
c8c8fb33 3837 goto out;
a9756bb5 3838
0d198328
AJ		 3839 intel_dp_probe_oui(intel_dp);
3840
0e32b39c
DA		 3841 ret = intel_dp_probe_mst(intel_dp);
3842 if (ret) {
3843 /* if we are in MST mode then this connector
3844 won't appear connected or have anything with EDID on it */
3845 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3846 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3847 status = connector_status_disconnected;
3848 goto out;
3849 }
3850
c3e5f67b
DV		 3851 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3852 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3853 } else {
0b99836f 3854 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3855 if (edid) {
3856 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3857 kfree(edid);
3858 }
a9756bb5
ZW		 3859 }
3860
d63885da
PZ		 3861 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3862 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3863 status = connector_status_connected;
3864
3865out:
671dedd2 3866 intel_display_power_put(dev_priv, power_domain);
c8c8fb33 3867 return status;
a4fc5ed6
KP		 3868}
3869
3870static int intel_dp_get_modes(struct drm_connector *connector)
3871{
df0e9248 3872 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3873 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3874 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3875 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3876 struct drm_device *dev = connector->dev;
671dedd2
ID		 3877 struct drm_i915_private *dev_priv = dev->dev_private;
3878 enum intel_display_power_domain power_domain;
32f9d658 3879 int ret;
a4fc5ed6
KP		 3880
3881 /* We should parse the EDID data and find out if it has an audio sink
3882 */
3883
671dedd2
ID		 3884 power_domain = intel_display_port_power_domain(intel_encoder);
3885 intel_display_power_get(dev_priv, power_domain);
3886
0b99836f 3887 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3888 intel_display_power_put(dev_priv, power_domain);
f8779fda 3889 if (ret)
32f9d658
ZW		 3890 return ret;
3891
f8779fda 3892 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3893 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3894 struct drm_display_mode *mode;
dd06f90e
JN		 3895 mode = drm_mode_duplicate(dev,
3896 intel_connector->panel.fixed_mode);
f8779fda 3897 if (mode) {
32f9d658
ZW		 3898 drm_mode_probed_add(connector, mode);
3899 return 1;
3900 }
3901 }
3902 return 0;
a4fc5ed6
KP		 3903}
3904
1aad7ac0
CW		 3905static bool
3906intel_dp_detect_audio(struct drm_connector *connector)
3907{
3908 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3909 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3910 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3911 struct drm_device *dev = connector->dev;
3912 struct drm_i915_private *dev_priv = dev->dev_private;
3913 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3914 struct edid *edid;
3915 bool has_audio = false;
3916
671dedd2
ID		 3917 power_domain = intel_display_port_power_domain(intel_encoder);
3918 intel_display_power_get(dev_priv, power_domain);
3919
0b99836f 3920 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3921 if (edid) {
3922 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3923 kfree(edid);
3924 }
3925
671dedd2
ID		 3926 intel_display_power_put(dev_priv, power_domain);
3927
1aad7ac0
CW		 3928 return has_audio;
3929}
3930
f684960e
CW		 3931static int
3932intel_dp_set_property(struct drm_connector *connector,
3933 struct drm_property *property,
3934 uint64_t val)
3935{
e953fd7b 3936 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3937 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3938 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3939 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3940 int ret;
3941
662595df 3942 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3943 if (ret)
3944 return ret;
3945
3f43c48d 3946 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3947 int i = val;
3948 bool has_audio;
3949
3950 if (i == intel_dp->force_audio)
f684960e
CW		 3951 return 0;
3952
1aad7ac0 3953 intel_dp->force_audio = i;
f684960e 3954
c3e5f67b 3955 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3956 has_audio = intel_dp_detect_audio(connector);
3957 else
c3e5f67b 3958 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3959
3960 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3961 return 0;
3962
1aad7ac0 3963 intel_dp->has_audio = has_audio;
f684960e
CW		 3964 goto done;
3965 }
3966
e953fd7b 3967 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3968 bool old_auto = intel_dp->color_range_auto;
3969 uint32_t old_range = intel_dp->color_range;
3970
55bc60db
VS		 3971 switch (val) {
3972 case INTEL_BROADCAST_RGB_AUTO:
3973 intel_dp->color_range_auto = true;
3974 break;
3975 case INTEL_BROADCAST_RGB_FULL:
3976 intel_dp->color_range_auto = false;
3977 intel_dp->color_range = 0;
3978 break;
3979 case INTEL_BROADCAST_RGB_LIMITED:
3980 intel_dp->color_range_auto = false;
3981 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3982 break;
3983 default:
3984 return -EINVAL;
3985 }
ae4edb80
DV		 3986
3987 if (old_auto == intel_dp->color_range_auto &&
3988 old_range == intel_dp->color_range)
3989 return 0;
3990
e953fd7b
CW		 3991 goto done;
3992 }
3993
53b41837
YN		 3994 if (is_edp(intel_dp) &&
3995 property == connector->dev->mode_config.scaling_mode_property) {
3996 if (val == DRM_MODE_SCALE_NONE) {
3997 DRM_DEBUG_KMS("no scaling not supported\n");
3998 return -EINVAL;
3999 }
4000
4001 if (intel_connector->panel.fitting_mode == val) {
4002 /* the eDP scaling property is not changed */
4003 return 0;
4004 }
4005 intel_connector->panel.fitting_mode = val;
4006
4007 goto done;
4008 }
4009
f684960e
CW		 4010 return -EINVAL;
4011
4012done:
c0c36b94
CW		 4013 if (intel_encoder->base.crtc)
4014 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4015
4016 return 0;
4017}
4018
a4fc5ed6 4019static void
73845adf 4020intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4021{
1d508706 4022 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4023
9cd300e0
JN		 4024 if (!IS_ERR_OR_NULL(intel_connector->edid))
4025 kfree(intel_connector->edid);
4026
acd8db10
PZ		 4027 /* Can't call is_edp() since the encoder may have been destroyed
4028 * already. */
4029 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4030 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4031
a4fc5ed6 4032 drm_connector_cleanup(connector);
55f78c43 4033 kfree(connector);
a4fc5ed6
KP		 4034}
4035
00c09d70 4036void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4037{
da63a9f2
PZ		 4038 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4039 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 4040 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 4041
4f71d0cb 4042 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4043 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4044 drm_encoder_cleanup(encoder);
bd943159
KP		 4045 if (is_edp(intel_dp)) {
4046 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4047 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4048 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4049 drm_modeset_unlock(&dev->mode_config.connection_mutex);
01527b31
CT		 4050 if (intel_dp->edp_notifier.notifier_call) {
4051 unregister_reboot_notifier(&intel_dp->edp_notifier);
4052 intel_dp->edp_notifier.notifier_call = NULL;
4053 }
bd943159 4054 }
da63a9f2 4055 kfree(intel_dig_port);
24d05927
DV		 4056}
4057
07f9cd0b
ID		 4058static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4059{
4060 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4061
4062 if (!is_edp(intel_dp))
4063 return;
4064
4065 edp_panel_vdd_off_sync(intel_dp);
4066}
4067
6d93c0c4
ID		 4068static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4069{
4070 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4071}
4072
a4fc5ed6 4073static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4074 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 4075 .detect = intel_dp_detect,
4076 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4077 .set_property = intel_dp_set_property,
73845adf 4078 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4079};
4080
4081static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4082 .get_modes = intel_dp_get_modes,
4083 .mode_valid = intel_dp_mode_valid,
df0e9248 4084 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4085};
4086
a4fc5ed6 4087static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4088 .reset = intel_dp_encoder_reset,
24d05927 4089 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4090};
4091
0e32b39c 4092void
21d40d37 4093intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4094{
0e32b39c 4095 return;
c8110e52 4096}
6207937d 4097
13cf5504
DA		 4098bool
4099intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4100{
4101 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4102 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4103 struct drm_device *dev = intel_dig_port->base.base.dev;
4104 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4105 enum intel_display_power_domain power_domain;
4106 bool ret = true;
4107
0e32b39c
DA		 4108 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4109 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4110
26fbb774
VS		 4111 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4112 port_name(intel_dig_port->port),
0e32b39c 4113 long_hpd ? "long" : "short");
13cf5504 4114
1c767b33
ID		 4115 power_domain = intel_display_port_power_domain(intel_encoder);
4116 intel_display_power_get(dev_priv, power_domain);
4117
0e32b39c
DA		 4118 if (long_hpd) {
4119 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4120 goto mst_fail;
4121
4122 if (!intel_dp_get_dpcd(intel_dp)) {
4123 goto mst_fail;
4124 }
4125
4126 intel_dp_probe_oui(intel_dp);
4127
4128 if (!intel_dp_probe_mst(intel_dp))
4129 goto mst_fail;
4130
4131 } else {
4132 if (intel_dp->is_mst) {
1c767b33 4133 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4134 goto mst_fail;
4135 }
4136
4137 if (!intel_dp->is_mst) {
4138 /*
4139 * we'll check the link status via the normal hot plug path later -
4140 * but for short hpds we should check it now
4141 */
5b215bcf 4142 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4143 intel_dp_check_link_status(intel_dp);
5b215bcf 4144 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4145 }
4146 }
1c767b33
ID		 4147 ret = false;
4148 goto put_power;
0e32b39c
DA		 4149mst_fail:
4150 /* if we were in MST mode, and device is not there get out of MST mode */
4151 if (intel_dp->is_mst) {
4152 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4153 intel_dp->is_mst = false;
4154 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4155 }
1c767b33
ID		 4156put_power:
4157 intel_display_power_put(dev_priv, power_domain);
4158
4159 return ret;
13cf5504
DA		 4160}
4161
e3421a18
ZW		 4162/* Return which DP Port should be selected for Transcoder DP control */
4163int
0206e353 4164intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4165{
4166 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4167 struct intel_encoder *intel_encoder;
4168 struct intel_dp *intel_dp;
e3421a18 4169
fa90ecef
PZ		 4170 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4171 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4172
fa90ecef
PZ		 4173 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4174 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4175 return intel_dp->output_reg;
e3421a18 4176 }
ea5b213a 4177
e3421a18
ZW		 4178 return -1;
4179}
4180
36e83a18 4181/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4182bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4183{
4184 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4185 union child_device_config *p_child;
36e83a18 4186 int i;
5d8a7752
VS		 4187 static const short port_mapping[] = {
4188 [PORT_B] = PORT_IDPB,
4189 [PORT_C] = PORT_IDPC,
4190 [PORT_D] = PORT_IDPD,
4191 };
36e83a18 4192
3b32a35b
VS		 4193 if (port == PORT_A)
4194 return true;
4195
41aa3448 4196 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4197 return false;
4198
41aa3448
RV		 4199 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4200 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4201
5d8a7752 4202 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4203 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4204 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4205 return true;
4206 }
4207 return false;
4208}
4209
0e32b39c 4210void
f684960e
CW		 4211intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4212{
53b41837
YN		 4213 struct intel_connector *intel_connector = to_intel_connector(connector);
4214
3f43c48d 4215 intel_attach_force_audio_property(connector);
e953fd7b 4216 intel_attach_broadcast_rgb_property(connector);
55bc60db 4217 intel_dp->color_range_auto = true;
53b41837
YN		 4218
4219 if (is_edp(intel_dp)) {
4220 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4221 drm_object_attach_property(
4222 &connector->base,
53b41837 4223 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4224 DRM_MODE_SCALE_ASPECT);
4225 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4226 }
f684960e
CW		 4227}
4228
dada1a9f
ID		 4229static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4230{
4231 intel_dp->last_power_cycle = jiffies;
4232 intel_dp->last_power_on = jiffies;
4233 intel_dp->last_backlight_off = jiffies;
4234}
4235
67a54566
DV		 4236static void
4237intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4238 struct intel_dp *intel_dp,
4239 struct edp_power_seq *out)
67a54566
DV		 4240{
4241 struct drm_i915_private *dev_priv = dev->dev_private;
4242 struct edp_power_seq cur, vbt, spec, final;
4243 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4244 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 4245
4246 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4247 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4248 pp_on_reg = PCH_PP_ON_DELAYS;
4249 pp_off_reg = PCH_PP_OFF_DELAYS;
4250 pp_div_reg = PCH_PP_DIVISOR;
4251 } else {
bf13e81b
JN		 4252 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4253
4254 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4255 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4256 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4257 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4258 }
67a54566
DV		 4259
4260 /* Workaround: Need to write PP_CONTROL with the unlock key as
4261 * the very first thing. */
453c5420 4262 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4263 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4264
453c5420
JB		 4265 pp_on = I915_READ(pp_on_reg);
4266 pp_off = I915_READ(pp_off_reg);
4267 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4268
4269 /* Pull timing values out of registers */
4270 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4271 PANEL_POWER_UP_DELAY_SHIFT;
4272
4273 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4274 PANEL_LIGHT_ON_DELAY_SHIFT;
4275
4276 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4277 PANEL_LIGHT_OFF_DELAY_SHIFT;
4278
4279 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4280 PANEL_POWER_DOWN_DELAY_SHIFT;
4281
4282 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4283 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4284
4285 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4286 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4287
41aa3448 4288 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4289
4290 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4291 * our hw here, which are all in 100usec. */
4292 spec.t1_t3 = 210 * 10;
4293 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4294 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4295 spec.t10 = 500 * 10;
4296 /* This one is special and actually in units of 100ms, but zero
4297 * based in the hw (so we need to add 100 ms). But the sw vbt
4298 * table multiplies it with 1000 to make it in units of 100usec,
4299 * too. */
4300 spec.t11_t12 = (510 + 100) * 10;
4301
4302 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4303 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4304
4305 /* Use the max of the register settings and vbt. If both are
4306 * unset, fall back to the spec limits. */
4307#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4308 spec.field : \
4309 max(cur.field, vbt.field))
4310 assign_final(t1_t3);
4311 assign_final(t8);
4312 assign_final(t9);
4313 assign_final(t10);
4314 assign_final(t11_t12);
4315#undef assign_final
4316
4317#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4318 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4319 intel_dp->backlight_on_delay = get_delay(t8);
4320 intel_dp->backlight_off_delay = get_delay(t9);
4321 intel_dp->panel_power_down_delay = get_delay(t10);
4322 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4323#undef get_delay
4324
f30d26e4
JN		 4325 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4326 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4327 intel_dp->panel_power_cycle_delay);
4328
4329 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4330 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4331
4332 if (out)
4333 *out = final;
4334}
4335
4336static void
4337intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4338 struct intel_dp *intel_dp,
4339 struct edp_power_seq *seq)
4340{
4341 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4342 u32 pp_on, pp_off, pp_div, port_sel = 0;
4343 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4344 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4345 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420
JB		 4346
4347 if (HAS_PCH_SPLIT(dev)) {
4348 pp_on_reg = PCH_PP_ON_DELAYS;
4349 pp_off_reg = PCH_PP_OFF_DELAYS;
4350 pp_div_reg = PCH_PP_DIVISOR;
4351 } else {
bf13e81b
JN		 4352 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4353
4354 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4355 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4356 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4357 }
4358
b2f19d1a
PZ		 4359 /*
4360 * And finally store the new values in the power sequencer. The
4361 * backlight delays are set to 1 because we do manual waits on them. For
4362 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4363 * we'll end up waiting for the backlight off delay twice: once when we
4364 * do the manual sleep, and once when we disable the panel and wait for
4365 * the PP_STATUS bit to become zero.
4366 */
f30d26e4 4367 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4368 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4369 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4370 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4371 /* Compute the divisor for the pp clock, simply match the Bspec
4372 * formula. */
453c5420 4373 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4374 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4375 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4376
4377 /* Haswell doesn't have any port selection bits for the panel
4378 * power sequencer any more. */
bc7d38a4 4379 if (IS_VALLEYVIEW(dev)) {
ad933b56 4380 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4381 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4382 if (port == PORT_A)
a24c144c 4383 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4384 else
a24c144c 4385 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4386 }
4387
453c5420
JB		 4388 pp_on |= port_sel;
4389
4390 I915_WRITE(pp_on_reg, pp_on);
4391 I915_WRITE(pp_off_reg, pp_off);
4392 I915_WRITE(pp_div_reg, pp_div);
67a54566 4393
67a54566 4394 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4395 I915_READ(pp_on_reg),
4396 I915_READ(pp_off_reg),
4397 I915_READ(pp_div_reg));
f684960e
CW		 4398}
4399
439d7ac0
PB		 4400void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4401{
4402 struct drm_i915_private *dev_priv = dev->dev_private;
4403 struct intel_encoder *encoder;
4404 struct intel_dp *intel_dp = NULL;
4405 struct intel_crtc_config *config = NULL;
4406 struct intel_crtc *intel_crtc = NULL;
4407 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4408 u32 reg, val;
4409 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4410
4411 if (refresh_rate <= 0) {
4412 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4413 return;
4414 }
4415
4416 if (intel_connector == NULL) {
4417 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4418 return;
4419 }
4420
1fcc9d1c
DV		 4421 /*
4422 * FIXME: This needs proper synchronization with psr state. But really
4423 * hard to tell without seeing the user of this function of this code.
4424 * Check locking and ordering once that lands.
4425 */
439d7ac0
PB		 4426 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4427 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4428 return;
4429 }
4430
4431 encoder = intel_attached_encoder(&intel_connector->base);
4432 intel_dp = enc_to_intel_dp(&encoder->base);
4433 intel_crtc = encoder->new_crtc;
4434
4435 if (!intel_crtc) {
4436 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4437 return;
4438 }
4439
4440 config = &intel_crtc->config;
4441
4442 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4443 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4444 return;
4445 }
4446
4447 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4448 index = DRRS_LOW_RR;
4449
4450 if (index == intel_dp->drrs_state.refresh_rate_type) {
4451 DRM_DEBUG_KMS(
4452 "DRRS requested for previously set RR...ignoring\n");
4453 return;
4454 }
4455
4456 if (!intel_crtc->active) {
4457 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4458 return;
4459 }
4460
4461 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4462 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4463 val = I915_READ(reg);
4464 if (index > DRRS_HIGH_RR) {
4465 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4466 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4467 } else {
4468 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4469 }
4470 I915_WRITE(reg, val);
4471 }
4472
4473 /*
4474 * mutex taken to ensure that there is no race between differnt
4475 * drrs calls trying to update refresh rate. This scenario may occur
4476 * in future when idleness detection based DRRS in kernel and
4477 * possible calls from user space to set differnt RR are made.
4478 */
4479
4480 mutex_lock(&intel_dp->drrs_state.mutex);
4481
4482 intel_dp->drrs_state.refresh_rate_type = index;
4483
4484 mutex_unlock(&intel_dp->drrs_state.mutex);
4485
4486 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4487}
4488
4f9db5b5
PB		 4489static struct drm_display_mode *
4490intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4491 struct intel_connector *intel_connector,
4492 struct drm_display_mode *fixed_mode)
4493{
4494 struct drm_connector *connector = &intel_connector->base;
4495 struct intel_dp *intel_dp = &intel_dig_port->dp;
4496 struct drm_device *dev = intel_dig_port->base.base.dev;
4497 struct drm_i915_private *dev_priv = dev->dev_private;
4498 struct drm_display_mode *downclock_mode = NULL;
4499
4500 if (INTEL_INFO(dev)->gen <= 6) {
4501 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4502 return NULL;
4503 }
4504
4505 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4506 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4507 return NULL;
4508 }
4509
4510 downclock_mode = intel_find_panel_downclock
4511 (dev, fixed_mode, connector);
4512
4513 if (!downclock_mode) {
4079b8d1 4514 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4515 return NULL;
4516 }
4517
439d7ac0
PB		 4518 dev_priv->drrs.connector = intel_connector;
4519
4520 mutex_init(&intel_dp->drrs_state.mutex);
4521
4f9db5b5
PB		 4522 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4523
4524 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4525 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4526 return downclock_mode;
4527}
4528
aba86890
ID		 4529void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4530{
4531 struct drm_device *dev = intel_encoder->base.dev;
4532 struct drm_i915_private *dev_priv = dev->dev_private;
4533 struct intel_dp *intel_dp;
4534 enum intel_display_power_domain power_domain;
4535
4536 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4537 return;
4538
4539 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4540 if (!edp_have_panel_vdd(intel_dp))
4541 return;
4542 /*
4543 * The VDD bit needs a power domain reference, so if the bit is
4544 * already enabled when we boot or resume, grab this reference and
4545 * schedule a vdd off, so we don't hold on to the reference
4546 * indefinitely.
4547 */
4548 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4549 power_domain = intel_display_port_power_domain(intel_encoder);
4550 intel_display_power_get(dev_priv, power_domain);
4551
4552 edp_panel_vdd_schedule_off(intel_dp);
4553}
4554
ed92f0b2 4555static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4556 struct intel_connector *intel_connector,
4557 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4558{
4559 struct drm_connector *connector = &intel_connector->base;
4560 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4561 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4562 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4563 struct drm_i915_private *dev_priv = dev->dev_private;
4564 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4565 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4566 bool has_dpcd;
4567 struct drm_display_mode *scan;
4568 struct edid *edid;
4569
4f9db5b5
PB		 4570 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4571
ed92f0b2
PZ		 4572 if (!is_edp(intel_dp))
4573 return true;
4574
aba86890 4575 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 4576
ed92f0b2 4577 /* Cache DPCD and EDID for edp. */
24f3e092 4578 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4579 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 4580 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4581
4582 if (has_dpcd) {
4583 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4584 dev_priv->no_aux_handshake =
4585 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4586 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4587 } else {
4588 /* if this fails, presume the device is a ghost */
4589 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4590 return false;
4591 }
4592
4593 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4594 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4595
060c8778 4596 mutex_lock(&dev->mode_config.mutex);
0b99836f 4597 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4598 if (edid) {
4599 if (drm_add_edid_modes(connector, edid)) {
4600 drm_mode_connector_update_edid_property(connector,
4601 edid);
4602 drm_edid_to_eld(connector, edid);
4603 } else {
4604 kfree(edid);
4605 edid = ERR_PTR(-EINVAL);
4606 }
4607 } else {
4608 edid = ERR_PTR(-ENOENT);
4609 }
4610 intel_connector->edid = edid;
4611
4612 /* prefer fixed mode from EDID if available */
4613 list_for_each_entry(scan, &connector->probed_modes, head) {
4614 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4615 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4616 downclock_mode = intel_dp_drrs_init(
4617 intel_dig_port,
4618 intel_connector, fixed_mode);
ed92f0b2
PZ		 4619 break;
4620 }
4621 }
4622
4623 /* fallback to VBT if available for eDP */
4624 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4625 fixed_mode = drm_mode_duplicate(dev,
4626 dev_priv->vbt.lfp_lvds_vbt_mode);
4627 if (fixed_mode)
4628 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4629 }
060c8778 4630 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4631
01527b31
CT		 4632 if (IS_VALLEYVIEW(dev)) {
4633 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4634 register_reboot_notifier(&intel_dp->edp_notifier);
4635 }
4636
4f9db5b5 4637 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 4638 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 4639 intel_panel_setup_backlight(connector);
4640
4641 return true;
4642}
4643
16c25533 4644bool
f0fec3f2
PZ		 4645intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4646 struct intel_connector *intel_connector)
a4fc5ed6 4647{
f0fec3f2
PZ		 4648 struct drm_connector *connector = &intel_connector->base;
4649 struct intel_dp *intel_dp = &intel_dig_port->dp;
4650 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4651 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4652 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4653 enum port port = intel_dig_port->port;
0095e6dc 4654 struct edp_power_seq power_seq = { 0 };
0b99836f 4655 int type;
a4fc5ed6 4656
ec5b01dd
DL		 4657 /* intel_dp vfuncs */
4658 if (IS_VALLEYVIEW(dev))
4659 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4660 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4661 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4662 else if (HAS_PCH_SPLIT(dev))
4663 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4664 else
4665 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4666
153b1100
DL		 4667 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4668
0767935e
DV		 4669 /* Preserve the current hw state. */
4670 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4671 intel_dp->attached_connector = intel_connector;
3d3dc149 4672
3b32a35b 4673 if (intel_dp_is_edp(dev, port))
b329530c 4674 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4675 else
4676 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4677
f7d24902
ID		 4678 /*
4679 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4680 * for DP the encoder type can be set by the caller to
4681 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4682 */
4683 if (type == DRM_MODE_CONNECTOR_eDP)
4684 intel_encoder->type = INTEL_OUTPUT_EDP;
4685
e7281eab
ID		 4686 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4687 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4688 port_name(port));
4689
b329530c 4690 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4691 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4692
a4fc5ed6
KP		 4693 connector->interlace_allowed = true;
4694 connector->doublescan_allowed = 0;
4695
f0fec3f2 4696 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4697 edp_panel_vdd_work);
a4fc5ed6 4698
df0e9248 4699 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 4700 drm_connector_register(connector);
a4fc5ed6 4701
affa9354 4702 if (HAS_DDI(dev))
bcbc889b
PZ		 4703 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4704 else
4705 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4706 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4707
0b99836f 4708 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4709 switch (port) {
4710 case PORT_A:
1d843f9d 4711 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4712 break;
4713 case PORT_B:
1d843f9d 4714 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4715 break;
4716 case PORT_C:
1d843f9d 4717 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4718 break;
4719 case PORT_D:
1d843f9d 4720 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4721 break;
4722 default:
ad1c0b19 4723 BUG();
5eb08b69
ZW		 4724 }
4725
dada1a9f
ID		 4726 if (is_edp(intel_dp)) {
4727 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4728 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4729 }
0095e6dc 4730
9d1a1031 4731 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4732
0e32b39c
DA		 4733 /* init MST on ports that can support it */
4734 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4735 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4736 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4737 }
4738 }
4739
0095e6dc 4740 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4741 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4742 if (is_edp(intel_dp)) {
4743 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4744 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4745 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4746 drm_modeset_unlock(&dev->mode_config.connection_mutex);
15b1d171 4747 }
34ea3d38 4748 drm_connector_unregister(connector);
b2f246a8 4749 drm_connector_cleanup(connector);
16c25533 4750 return false;
b2f246a8 4751 }
32f9d658 4752
f684960e
CW		 4753 intel_dp_add_properties(intel_dp, connector);
4754
a4fc5ed6
KP		 4755 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4756 * 0xd. Failure to do so will result in spurious interrupts being
4757 * generated on the port when a cable is not attached.
4758 */
4759 if (IS_G4X(dev) && !IS_GM45(dev)) {
4760 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4761 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4762 }
16c25533
PZ		 4763
4764 return true;
a4fc5ed6 4765}
f0fec3f2
PZ		 4766
4767void
4768intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4769{
13cf5504 4770 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 4771 struct intel_digital_port *intel_dig_port;
4772 struct intel_encoder *intel_encoder;
4773 struct drm_encoder *encoder;
4774 struct intel_connector *intel_connector;
4775
b14c5679 4776 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4777 if (!intel_dig_port)
4778 return;
4779
b14c5679 4780 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4781 if (!intel_connector) {
4782 kfree(intel_dig_port);
4783 return;
4784 }
4785
4786 intel_encoder = &intel_dig_port->base;
4787 encoder = &intel_encoder->base;
4788
4789 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4790 DRM_MODE_ENCODER_TMDS);
4791
5bfe2ac0 4792 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4793 intel_encoder->disable = intel_disable_dp;
00c09d70 4794 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4795 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 4796 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 4797 if (IS_CHERRYVIEW(dev)) {
9197c88b 4798 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 4799 intel_encoder->pre_enable = chv_pre_enable_dp;
4800 intel_encoder->enable = vlv_enable_dp;
580d3811 4801 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4802 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4803 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4804 intel_encoder->pre_enable = vlv_pre_enable_dp;
4805 intel_encoder->enable = vlv_enable_dp;
49277c31 4806 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4807 } else {
ecff4f3b
JN		 4808 intel_encoder->pre_enable = g4x_pre_enable_dp;
4809 intel_encoder->enable = g4x_enable_dp;
49277c31 4810 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4811 }
f0fec3f2 4812
174edf1f 4813 intel_dig_port->port = port;
f0fec3f2
PZ		 4814 intel_dig_port->dp.output_reg = output_reg;
4815
00c09d70 4816 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4817 if (IS_CHERRYVIEW(dev)) {
4818 if (port == PORT_D)
4819 intel_encoder->crtc_mask = 1 << 2;
4820 else
4821 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4822 } else {
4823 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4824 }
bc079e8b 4825 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4826 intel_encoder->hot_plug = intel_dp_hot_plug;
4827
13cf5504
DA		 4828 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4829 dev_priv->hpd_irq_port[port] = intel_dig_port;
4830
15b1d171
PZ		 4831 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4832 drm_encoder_cleanup(encoder);
4833 kfree(intel_dig_port);
b2f246a8 4834 kfree(intel_connector);
15b1d171 4835 }
f0fec3f2 4836}
0e32b39c
DA		 4837
4838void intel_dp_mst_suspend(struct drm_device *dev)
4839{
4840 struct drm_i915_private *dev_priv = dev->dev_private;
4841 int i;
4842
4843 /* disable MST */
4844 for (i = 0; i < I915_MAX_PORTS; i++) {
4845 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4846 if (!intel_dig_port)
4847 continue;
4848
4849 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4850 if (!intel_dig_port->dp.can_mst)
4851 continue;
4852 if (intel_dig_port->dp.is_mst)
4853 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4854 }
4855 }
4856}
4857
4858void intel_dp_mst_resume(struct drm_device *dev)
4859{
4860 struct drm_i915_private *dev_priv = dev->dev_private;
4861 int i;
4862
4863 for (i = 0; i < I915_MAX_PORTS; i++) {
4864 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4865 if (!intel_dig_port)
4866 continue;
4867 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4868 int ret;
4869
4870 if (!intel_dig_port->dp.can_mst)
4871 continue;
4872
4873 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4874 if (ret != 0) {
4875 intel_dp_check_mst_status(&intel_dig_port->dp);
4876 }
4877 }
4878 }
4879}
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