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drm/i915: add encoder->pre_enable/post_disable
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
a4fc5ed6
KP		 31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
34#include "drm_crtc_helper.h"
d6f24d0f 35#include "drm_edid.h"
a4fc5ed6
KP		 36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
a4fc5ed6
KP		 39
40#define DP_LINK_STATUS_SIZE 6
41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
cfcb0fc9
JB		 43/**
44 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
45 * @intel_dp: DP struct
46 *
47 * If a CPU or PCH DP output is attached to an eDP panel, this function
48 * will return true, and false otherwise.
49 */
50static bool is_edp(struct intel_dp *intel_dp)
51{
52 return intel_dp->base.type == INTEL_OUTPUT_EDP;
53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
ea5b213a
CW		 79static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
80{
4ef69c7a 81 return container_of(encoder, struct intel_dp, base.base);
ea5b213a 82}
a4fc5ed6 83
df0e9248
CW		 84static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
85{
86 return container_of(intel_attached_encoder(connector),
87 struct intel_dp, base);
88}
89
814948ad
JB		 90/**
91 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
92 * @encoder: DRM encoder
93 *
94 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
95 * by intel_display.c.
96 */
97bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
98{
99 struct intel_dp *intel_dp;
100
101 if (!encoder)
102 return false;
103
104 intel_dp = enc_to_intel_dp(encoder);
105
106 return is_pch_edp(intel_dp);
107}
108
33a34e4e
JB		 109static void intel_dp_start_link_train(struct intel_dp *intel_dp);
110static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
ea5b213a 111static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 112
32f9d658 113void
0206e353 114intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 115 int *lane_num, int *link_bw)
32f9d658 116{
ea5b213a 117 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 118
ea5b213a
CW		 119 *lane_num = intel_dp->lane_count;
120 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 121 *link_bw = 162000;
ea5b213a 122 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 123 *link_bw = 270000;
124}
125
94bf2ced
DV		 126int
127intel_edp_target_clock(struct intel_encoder *intel_encoder,
128 struct drm_display_mode *mode)
129{
130 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
131
132 if (intel_dp->panel_fixed_mode)
133 return intel_dp->panel_fixed_mode->clock;
134 else
135 return mode->clock;
136}
137
a4fc5ed6 138static int
ea5b213a 139intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 140{
9a10f401
KP		 141 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
142 switch (max_lane_count) {
143 case 1: case 2: case 4:
144 break;
145 default:
146 max_lane_count = 4;
a4fc5ed6
KP		 147 }
148 return max_lane_count;
149}
150
151static int
ea5b213a 152intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 153{
7183dc29 154 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 155
156 switch (max_link_bw) {
157 case DP_LINK_BW_1_62:
158 case DP_LINK_BW_2_7:
159 break;
160 default:
161 max_link_bw = DP_LINK_BW_1_62;
162 break;
163 }
164 return max_link_bw;
165}
166
167static int
168intel_dp_link_clock(uint8_t link_bw)
169{
170 if (link_bw == DP_LINK_BW_2_7)
171 return 270000;
172 else
173 return 162000;
174}
175
cd9dde44
AJ		 176/*
177 * The units on the numbers in the next two are... bizarre. Examples will
178 * make it clearer; this one parallels an example in the eDP spec.
179 *
180 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
181 *
182 * 270000 * 1 * 8 / 10 == 216000
183 *
184 * The actual data capacity of that configuration is 2.16Gbit/s, so the
185 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
186 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
187 * 119000. At 18bpp that's 2142000 kilobits per second.
188 *
189 * Thus the strange-looking division by 10 in intel_dp_link_required, to
190 * get the result in decakilobits instead of kilobits.
191 */
192
a4fc5ed6 193static int
c898261c 194intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 195{
cd9dde44 196 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 197}
198
fe27d53e
DA		 199static int
200intel_dp_max_data_rate(int max_link_clock, int max_lanes)
201{
202 return (max_link_clock * max_lanes * 8) / 10;
203}
204
c4867936
DV		 205static bool
206intel_dp_adjust_dithering(struct intel_dp *intel_dp,
207 struct drm_display_mode *mode,
cb1793ce 208 bool adjust_mode)
c4867936
DV		 209{
210 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
211 int max_lanes = intel_dp_max_lane_count(intel_dp);
212 int max_rate, mode_rate;
213
214 mode_rate = intel_dp_link_required(mode->clock, 24);
215 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
216
217 if (mode_rate > max_rate) {
218 mode_rate = intel_dp_link_required(mode->clock, 18);
219 if (mode_rate > max_rate)
220 return false;
221
cb1793ce
DV		 222 if (adjust_mode)
223 mode->private_flags
c4867936
DV		 224 |= INTEL_MODE_DP_FORCE_6BPC;
225
226 return true;
227 }
228
229 return true;
230}
231
a4fc5ed6
KP		 232static int
233intel_dp_mode_valid(struct drm_connector *connector,
234 struct drm_display_mode *mode)
235{
df0e9248 236 struct intel_dp *intel_dp = intel_attached_dp(connector);
a4fc5ed6 237
d15456de
KP		 238 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
239 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
7de56f43
ZY		 240 return MODE_PANEL;
241
d15456de 242 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
7de56f43
ZY		 243 return MODE_PANEL;
244 }
245
cb1793ce 246 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 247 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 248
249 if (mode->clock < 10000)
250 return MODE_CLOCK_LOW;
251
0af78a2b
DV		 252 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
253 return MODE_H_ILLEGAL;
254
a4fc5ed6
KP		 255 return MODE_OK;
256}
257
258static uint32_t
259pack_aux(uint8_t *src, int src_bytes)
260{
261 int i;
262 uint32_t v = 0;
263
264 if (src_bytes > 4)
265 src_bytes = 4;
266 for (i = 0; i < src_bytes; i++)
267 v |= ((uint32_t) src[i]) << ((3-i) * 8);
268 return v;
269}
270
271static void
272unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
273{
274 int i;
275 if (dst_bytes > 4)
276 dst_bytes = 4;
277 for (i = 0; i < dst_bytes; i++)
278 dst[i] = src >> ((3-i) * 8);
279}
280
fb0f8fbf
KP		 281/* hrawclock is 1/4 the FSB frequency */
282static int
283intel_hrawclk(struct drm_device *dev)
284{
285 struct drm_i915_private *dev_priv = dev->dev_private;
286 uint32_t clkcfg;
287
288 clkcfg = I915_READ(CLKCFG);
289 switch (clkcfg & CLKCFG_FSB_MASK) {
290 case CLKCFG_FSB_400:
291 return 100;
292 case CLKCFG_FSB_533:
293 return 133;
294 case CLKCFG_FSB_667:
295 return 166;
296 case CLKCFG_FSB_800:
297 return 200;
298 case CLKCFG_FSB_1067:
299 return 266;
300 case CLKCFG_FSB_1333:
301 return 333;
302 /* these two are just a guess; one of them might be right */
303 case CLKCFG_FSB_1600:
304 case CLKCFG_FSB_1600_ALT:
305 return 400;
306 default:
307 return 133;
308 }
309}
310
ebf33b18
KP		 311static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
312{
313 struct drm_device *dev = intel_dp->base.base.dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315
316 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
317}
318
319static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp->base.base.dev;
322 struct drm_i915_private *dev_priv = dev->dev_private;
323
324 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
325}
326
9b984dae
KP		 327static void
328intel_dp_check_edp(struct intel_dp *intel_dp)
329{
330 struct drm_device *dev = intel_dp->base.base.dev;
331 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 332
9b984dae
KP		 333 if (!is_edp(intel_dp))
334 return;
ebf33b18 335 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 336 WARN(1, "eDP powered off while attempting aux channel communication.\n");
337 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 338 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 339 I915_READ(PCH_PP_CONTROL));
340 }
341}
342
a4fc5ed6 343static int
ea5b213a 344intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 345 uint8_t *send, int send_bytes,
346 uint8_t *recv, int recv_size)
347{
ea5b213a 348 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 349 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 350 struct drm_i915_private *dev_priv = dev->dev_private;
351 uint32_t ch_ctl = output_reg + 0x10;
352 uint32_t ch_data = ch_ctl + 4;
353 int i;
354 int recv_bytes;
a4fc5ed6 355 uint32_t status;
fb0f8fbf 356 uint32_t aux_clock_divider;
6b4e0a93 357 int try, precharge;
a4fc5ed6 358
9b984dae 359 intel_dp_check_edp(intel_dp);
a4fc5ed6 360 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 361 * and would like to run at 2MHz. So, take the
362 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 363 *
364 * Note that PCH attached eDP panels should use a 125MHz input
365 * clock divider.
a4fc5ed6 366 */
1c95822a 367 if (is_cpu_edp(intel_dp)) {
1a2eb460
KP		 368 if (IS_GEN6(dev) || IS_GEN7(dev))
369 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 370 else
371 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
372 } else if (HAS_PCH_SPLIT(dev))
6919132e 373 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 374 else
375 aux_clock_divider = intel_hrawclk(dev) / 2;
376
6b4e0a93
DV		 377 if (IS_GEN6(dev))
378 precharge = 3;
379 else
380 precharge = 5;
381
11bee43e
JB		 382 /* Try to wait for any previous AUX channel activity */
383 for (try = 0; try < 3; try++) {
384 status = I915_READ(ch_ctl);
385 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
386 break;
387 msleep(1);
388 }
389
390 if (try == 3) {
391 WARN(1, "dp_aux_ch not started status 0x%08x\n",
392 I915_READ(ch_ctl));
4f7f7b7e
CW		 393 return -EBUSY;
394 }
395
fb0f8fbf
KP		 396 /* Must try at least 3 times according to DP spec */
397 for (try = 0; try < 5; try++) {
398 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 399 for (i = 0; i < send_bytes; i += 4)
400 I915_WRITE(ch_data + i,
401 pack_aux(send + i, send_bytes - i));
0206e353 402
fb0f8fbf 403 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 404 I915_WRITE(ch_ctl,
405 DP_AUX_CH_CTL_SEND_BUSY |
406 DP_AUX_CH_CTL_TIME_OUT_400us |
407 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
408 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
409 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
410 DP_AUX_CH_CTL_DONE |
411 DP_AUX_CH_CTL_TIME_OUT_ERROR |
412 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 413 for (;;) {
fb0f8fbf
KP		 414 status = I915_READ(ch_ctl);
415 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
416 break;
4f7f7b7e 417 udelay(100);
fb0f8fbf 418 }
0206e353 419
fb0f8fbf 420 /* Clear done status and any errors */
4f7f7b7e
CW		 421 I915_WRITE(ch_ctl,
422 status |
423 DP_AUX_CH_CTL_DONE |
424 DP_AUX_CH_CTL_TIME_OUT_ERROR |
425 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 426
427 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
428 DP_AUX_CH_CTL_RECEIVE_ERROR))
429 continue;
4f7f7b7e 430 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 431 break;
432 }
433
a4fc5ed6 434 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 435 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 436 return -EBUSY;
a4fc5ed6
KP		 437 }
438
439 /* Check for timeout or receive error.
440 * Timeouts occur when the sink is not connected
441 */
a5b3da54 442 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 443 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 444 return -EIO;
445 }
1ae8c0a5
KP		 446
447 /* Timeouts occur when the device isn't connected, so they're
448 * "normal" -- don't fill the kernel log with these */
a5b3da54 449 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 450 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 451 return -ETIMEDOUT;
a4fc5ed6
KP		 452 }
453
454 /* Unload any bytes sent back from the other side */
455 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
456 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 457 if (recv_bytes > recv_size)
458 recv_bytes = recv_size;
0206e353 459
4f7f7b7e
CW		 460 for (i = 0; i < recv_bytes; i += 4)
461 unpack_aux(I915_READ(ch_data + i),
462 recv + i, recv_bytes - i);
a4fc5ed6
KP		 463
464 return recv_bytes;
465}
466
467/* Write data to the aux channel in native mode */
468static int
ea5b213a 469intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 470 uint16_t address, uint8_t *send, int send_bytes)
471{
472 int ret;
473 uint8_t msg[20];
474 int msg_bytes;
475 uint8_t ack;
476
9b984dae 477 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 478 if (send_bytes > 16)
479 return -1;
480 msg[0] = AUX_NATIVE_WRITE << 4;
481 msg[1] = address >> 8;
eebc863e 482 msg[2] = address & 0xff;
a4fc5ed6
KP		 483 msg[3] = send_bytes - 1;
484 memcpy(&msg[4], send, send_bytes);
485 msg_bytes = send_bytes + 4;
486 for (;;) {
ea5b213a 487 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 488 if (ret < 0)
489 return ret;
490 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
491 break;
492 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
493 udelay(100);
494 else
a5b3da54 495 return -EIO;
a4fc5ed6
KP		 496 }
497 return send_bytes;
498}
499
500/* Write a single byte to the aux channel in native mode */
501static int
ea5b213a 502intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 503 uint16_t address, uint8_t byte)
504{
ea5b213a 505 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 506}
507
508/* read bytes from a native aux channel */
509static int
ea5b213a 510intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 511 uint16_t address, uint8_t *recv, int recv_bytes)
512{
513 uint8_t msg[4];
514 int msg_bytes;
515 uint8_t reply[20];
516 int reply_bytes;
517 uint8_t ack;
518 int ret;
519
9b984dae 520 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 521 msg[0] = AUX_NATIVE_READ << 4;
522 msg[1] = address >> 8;
523 msg[2] = address & 0xff;
524 msg[3] = recv_bytes - 1;
525
526 msg_bytes = 4;
527 reply_bytes = recv_bytes + 1;
528
529 for (;;) {
ea5b213a 530 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 531 reply, reply_bytes);
a5b3da54
KP		 532 if (ret == 0)
533 return -EPROTO;
534 if (ret < 0)
a4fc5ed6
KP		 535 return ret;
536 ack = reply[0];
537 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
538 memcpy(recv, reply + 1, ret - 1);
539 return ret - 1;
540 }
541 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
542 udelay(100);
543 else
a5b3da54 544 return -EIO;
a4fc5ed6
KP		 545 }
546}
547
548static int
ab2c0672
DA		 549intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
550 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 551{
ab2c0672 552 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 553 struct intel_dp *intel_dp = container_of(adapter,
554 struct intel_dp,
555 adapter);
ab2c0672
DA		 556 uint16_t address = algo_data->address;
557 uint8_t msg[5];
558 uint8_t reply[2];
8316f337 559 unsigned retry;
ab2c0672
DA		 560 int msg_bytes;
561 int reply_bytes;
562 int ret;
563
9b984dae 564 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 565 /* Set up the command byte */
566 if (mode & MODE_I2C_READ)
567 msg[0] = AUX_I2C_READ << 4;
568 else
569 msg[0] = AUX_I2C_WRITE << 4;
570
571 if (!(mode & MODE_I2C_STOP))
572 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 573
ab2c0672
DA		 574 msg[1] = address >> 8;
575 msg[2] = address;
576
577 switch (mode) {
578 case MODE_I2C_WRITE:
579 msg[3] = 0;
580 msg[4] = write_byte;
581 msg_bytes = 5;
582 reply_bytes = 1;
583 break;
584 case MODE_I2C_READ:
585 msg[3] = 0;
586 msg_bytes = 4;
587 reply_bytes = 2;
588 break;
589 default:
590 msg_bytes = 3;
591 reply_bytes = 1;
592 break;
593 }
594
8316f337
DF		 595 for (retry = 0; retry < 5; retry++) {
596 ret = intel_dp_aux_ch(intel_dp,
597 msg, msg_bytes,
598 reply, reply_bytes);
ab2c0672 599 if (ret < 0) {
3ff99164 600 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 601 return ret;
602 }
8316f337
DF		 603
604 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
605 case AUX_NATIVE_REPLY_ACK:
606 /* I2C-over-AUX Reply field is only valid
607 * when paired with AUX ACK.
608 */
609 break;
610 case AUX_NATIVE_REPLY_NACK:
611 DRM_DEBUG_KMS("aux_ch native nack\n");
612 return -EREMOTEIO;
613 case AUX_NATIVE_REPLY_DEFER:
614 udelay(100);
615 continue;
616 default:
617 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
618 reply[0]);
619 return -EREMOTEIO;
620 }
621
ab2c0672
DA		 622 switch (reply[0] & AUX_I2C_REPLY_MASK) {
623 case AUX_I2C_REPLY_ACK:
624 if (mode == MODE_I2C_READ) {
625 *read_byte = reply[1];
626 }
627 return reply_bytes - 1;
628 case AUX_I2C_REPLY_NACK:
8316f337 629 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 630 return -EREMOTEIO;
631 case AUX_I2C_REPLY_DEFER:
8316f337 632 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 633 udelay(100);
634 break;
635 default:
8316f337 636 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 637 return -EREMOTEIO;
638 }
639 }
8316f337
DF		 640
641 DRM_ERROR("too many retries, giving up\n");
642 return -EREMOTEIO;
a4fc5ed6
KP		 643}
644
0b5c541b 645static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
bd943159 646static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0b5c541b 647
a4fc5ed6 648static int
ea5b213a 649intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 650 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 651{
0b5c541b
KP		 652 int ret;
653
d54e9d28 654 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 655 intel_dp->algo.running = false;
656 intel_dp->algo.address = 0;
657 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
658
0206e353 659 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 660 intel_dp->adapter.owner = THIS_MODULE;
661 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 662 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 663 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
664 intel_dp->adapter.algo_data = &intel_dp->algo;
665 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
666
0b5c541b
KP		 667 ironlake_edp_panel_vdd_on(intel_dp);
668 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 669 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 670 return ret;
a4fc5ed6
KP		 671}
672
673static bool
e811f5ae
LP		 674intel_dp_mode_fixup(struct drm_encoder *encoder,
675 const struct drm_display_mode *mode,
a4fc5ed6
KP		 676 struct drm_display_mode *adjusted_mode)
677{
0d3a1bee 678 struct drm_device *dev = encoder->dev;
ea5b213a 679 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 680 int lane_count, clock;
ea5b213a
CW		 681 int max_lane_count = intel_dp_max_lane_count(intel_dp);
682 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 683 int bpp, mode_rate;
a4fc5ed6
KP		 684 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
685
d15456de
KP		 686 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
687 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
1d8e1c75
CW		 688 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
689 mode, adjusted_mode);
0d3a1bee
ZY		 690 }
691
cb1793ce 692 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 693 return false;
694
083f9560
DV		 695 DRM_DEBUG_KMS("DP link computation with max lane count %i "
696 "max bw %02x pixel clock %iKHz\n",
71244653 697 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 698
cb1793ce 699 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 700 return false;
701
702 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 703 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 704
2514bc51
JB		 705 for (clock = 0; clock <= max_clock; clock++) {
706 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
fe27d53e 707 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 708
083f9560 709 if (mode_rate <= link_avail) {
ea5b213a
CW		 710 intel_dp->link_bw = bws[clock];
711 intel_dp->lane_count = lane_count;
712 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 713 DRM_DEBUG_KMS("DP link bw %02x lane "
714 "count %d clock %d bpp %d\n",
ea5b213a 715 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 716 adjusted_mode->clock, bpp);
717 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
718 mode_rate, link_avail);
a4fc5ed6
KP		 719 return true;
720 }
721 }
722 }
fe27d53e 723
a4fc5ed6
KP		 724 return false;
725}
726
727struct intel_dp_m_n {
728 uint32_t tu;
729 uint32_t gmch_m;
730 uint32_t gmch_n;
731 uint32_t link_m;
732 uint32_t link_n;
733};
734
735static void
736intel_reduce_ratio(uint32_t *num, uint32_t *den)
737{
738 while (*num > 0xffffff || *den > 0xffffff) {
739 *num >>= 1;
740 *den >>= 1;
741 }
742}
743
744static void
36e83a18 745intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 746 int nlanes,
747 int pixel_clock,
748 int link_clock,
749 struct intel_dp_m_n *m_n)
750{
751 m_n->tu = 64;
36e83a18 752 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 753 m_n->gmch_n = link_clock * nlanes;
754 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
755 m_n->link_m = pixel_clock;
756 m_n->link_n = link_clock;
757 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
758}
759
760void
761intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
762 struct drm_display_mode *adjusted_mode)
763{
764 struct drm_device *dev = crtc->dev;
6c2b7c12 765 struct intel_encoder *encoder;
a4fc5ed6
KP		 766 struct drm_i915_private *dev_priv = dev->dev_private;
767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 768 int lane_count = 4;
a4fc5ed6 769 struct intel_dp_m_n m_n;
9db4a9c7 770 int pipe = intel_crtc->pipe;
a4fc5ed6
KP		 771
772 /*
21d40d37 773 * Find the lane count in the intel_encoder private
a4fc5ed6 774 */
6c2b7c12
DV		 775 for_each_encoder_on_crtc(dev, crtc, encoder) {
776 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 777
9a10f401
KP		 778 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
779 intel_dp->base.type == INTEL_OUTPUT_EDP)
780 {
ea5b213a 781 lane_count = intel_dp->lane_count;
51190667 782 break;
a4fc5ed6
KP		 783 }
784 }
785
786 /*
787 * Compute the GMCH and Link ratios. The '3' here is
788 * the number of bytes_per_pixel post-LUT, which we always
789 * set up for 8-bits of R/G/B, or 3 bytes total.
790 */
858fa035 791 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 792 mode->clock, adjusted_mode->clock, &m_n);
793
c619eed4 794 if (HAS_PCH_SPLIT(dev)) {
9db4a9c7
JB		 795 I915_WRITE(TRANSDATA_M1(pipe),
796 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
797 m_n.gmch_m);
798 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
799 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
800 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
a4fc5ed6 801 } else {
9db4a9c7
JB		 802 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
803 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
804 m_n.gmch_m);
805 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
806 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
807 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 808 }
809}
810
f01eca2e
KP		 811static void ironlake_edp_pll_on(struct drm_encoder *encoder);
812static void ironlake_edp_pll_off(struct drm_encoder *encoder);
813
a4fc5ed6
KP		 814static void
815intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
816 struct drm_display_mode *adjusted_mode)
817{
e3421a18 818 struct drm_device *dev = encoder->dev;
417e822d 819 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 820 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 821 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
823
f01eca2e
KP		 824 /* Turn on the eDP PLL if needed */
825 if (is_edp(intel_dp)) {
826 if (!is_pch_edp(intel_dp))
827 ironlake_edp_pll_on(encoder);
828 else
829 ironlake_edp_pll_off(encoder);
830 }
831
417e822d 832 /*
1a2eb460 833 * There are four kinds of DP registers:
417e822d
KP		 834 *
835 * IBX PCH
1a2eb460
KP		 836 * SNB CPU
837 * IVB CPU
417e822d
KP		 838 * CPT PCH
839 *
840 * IBX PCH and CPU are the same for almost everything,
841 * except that the CPU DP PLL is configured in this
842 * register
843 *
844 * CPT PCH is quite different, having many bits moved
845 * to the TRANS_DP_CTL register instead. That
846 * configuration happens (oddly) in ironlake_pch_enable
847 */
9c9e7927 848
417e822d
KP		 849 /* Preserve the BIOS-computed detected bit. This is
850 * supposed to be read-only.
851 */
852 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 853
417e822d 854 /* Handle DP bits in common between all three register formats */
417e822d 855 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 856
ea5b213a 857 switch (intel_dp->lane_count) {
a4fc5ed6 858 case 1:
ea5b213a 859 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 860 break;
861 case 2:
ea5b213a 862 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 863 break;
864 case 4:
ea5b213a 865 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 866 break;
867 }
e0dac65e
WF		 868 if (intel_dp->has_audio) {
869 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
870 pipe_name(intel_crtc->pipe));
ea5b213a 871 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 872 intel_write_eld(encoder, adjusted_mode);
873 }
ea5b213a
CW		 874 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
875 intel_dp->link_configuration[0] = intel_dp->link_bw;
876 intel_dp->link_configuration[1] = intel_dp->lane_count;
a2cab1b2 877 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
a4fc5ed6 878 /*
9962c925 879 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 880 */
7183dc29
JB		 881 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
882 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
ea5b213a 883 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
a4fc5ed6
KP		 884 }
885
417e822d 886 /* Split out the IBX/CPU vs CPT settings */
32f9d658 887
1a2eb460
KP		 888 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
889 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
890 intel_dp->DP |= DP_SYNC_HS_HIGH;
891 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
892 intel_dp->DP |= DP_SYNC_VS_HIGH;
893 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
894
895 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
896 intel_dp->DP |= DP_ENHANCED_FRAMING;
897
898 intel_dp->DP |= intel_crtc->pipe << 29;
899
900 /* don't miss out required setting for eDP */
901 intel_dp->DP |= DP_PLL_ENABLE;
902 if (adjusted_mode->clock < 200000)
903 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
904 else
905 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
906 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 907 intel_dp->DP |= intel_dp->color_range;
908
909 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
910 intel_dp->DP |= DP_SYNC_HS_HIGH;
911 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
912 intel_dp->DP |= DP_SYNC_VS_HIGH;
913 intel_dp->DP |= DP_LINK_TRAIN_OFF;
914
915 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
916 intel_dp->DP |= DP_ENHANCED_FRAMING;
917
918 if (intel_crtc->pipe == 1)
919 intel_dp->DP |= DP_PIPEB_SELECT;
920
921 if (is_cpu_edp(intel_dp)) {
922 /* don't miss out required setting for eDP */
923 intel_dp->DP |= DP_PLL_ENABLE;
924 if (adjusted_mode->clock < 200000)
925 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
926 else
927 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
928 }
929 } else {
930 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 931 }
a4fc5ed6
KP		 932}
933
99ea7127
KP		 934#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
935#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
936
937#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
938#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
939
940#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
941#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
942
943static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
944 u32 mask,
945 u32 value)
bd943159 946{
99ea7127
KP		 947 struct drm_device *dev = intel_dp->base.base.dev;
948 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 949
99ea7127
KP		 950 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
951 mask, value,
952 I915_READ(PCH_PP_STATUS),
953 I915_READ(PCH_PP_CONTROL));
32ce697c 954
99ea7127
KP		 955 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
956 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
957 I915_READ(PCH_PP_STATUS),
958 I915_READ(PCH_PP_CONTROL));
32ce697c 959 }
99ea7127 960}
32ce697c 961
99ea7127
KP		 962static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
963{
964 DRM_DEBUG_KMS("Wait for panel power on\n");
965 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 966}
967
99ea7127
KP		 968static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
969{
970 DRM_DEBUG_KMS("Wait for panel power off time\n");
971 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
972}
973
974static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
975{
976 DRM_DEBUG_KMS("Wait for panel power cycle\n");
977 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
978}
979
980
832dd3c1
KP		 981/* Read the current pp_control value, unlocking the register if it
982 * is locked
983 */
984
985static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
986{
987 u32 control = I915_READ(PCH_PP_CONTROL);
988
989 control &= ~PANEL_UNLOCK_MASK;
990 control |= PANEL_UNLOCK_REGS;
991 return control;
bd943159
KP		 992}
993
5d613501
JB		 994static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
995{
996 struct drm_device *dev = intel_dp->base.base.dev;
997 struct drm_i915_private *dev_priv = dev->dev_private;
998 u32 pp;
999
97af61f5
KP		 1000 if (!is_edp(intel_dp))
1001 return;
f01eca2e 1002 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1003
bd943159
KP		 1004 WARN(intel_dp->want_panel_vdd,
1005 "eDP VDD already requested on\n");
1006
1007 intel_dp->want_panel_vdd = true;
99ea7127 1008
bd943159
KP		 1009 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1010 DRM_DEBUG_KMS("eDP VDD already on\n");
1011 return;
1012 }
1013
99ea7127
KP		 1014 if (!ironlake_edp_have_panel_power(intel_dp))
1015 ironlake_wait_panel_power_cycle(intel_dp);
1016
832dd3c1 1017 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1018 pp |= EDP_FORCE_VDD;
1019 I915_WRITE(PCH_PP_CONTROL, pp);
1020 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1021 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1022 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1023
1024 /*
1025 * If the panel wasn't on, delay before accessing aux channel
1026 */
1027 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1028 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1029 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1030 }
5d613501
JB		 1031}
1032
bd943159 1033static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1034{
1035 struct drm_device *dev = intel_dp->base.base.dev;
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037 u32 pp;
1038
bd943159 1039 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1040 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1041 pp &= ~EDP_FORCE_VDD;
1042 I915_WRITE(PCH_PP_CONTROL, pp);
1043 POSTING_READ(PCH_PP_CONTROL);
1044
1045 /* Make sure sequencer is idle before allowing subsequent activity */
1046 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1047 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1048
1049 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1050 }
1051}
5d613501 1052
bd943159
KP		 1053static void ironlake_panel_vdd_work(struct work_struct *__work)
1054{
1055 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1056 struct intel_dp, panel_vdd_work);
1057 struct drm_device *dev = intel_dp->base.base.dev;
1058
627f7675 1059 mutex_lock(&dev->mode_config.mutex);
bd943159 1060 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1061 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1062}
1063
1064static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1065{
97af61f5
KP		 1066 if (!is_edp(intel_dp))
1067 return;
5d613501 1068
bd943159
KP		 1069 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1070 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1071
bd943159
KP		 1072 intel_dp->want_panel_vdd = false;
1073
1074 if (sync) {
1075 ironlake_panel_vdd_off_sync(intel_dp);
1076 } else {
1077 /*
1078 * Queue the timer to fire a long
1079 * time from now (relative to the power down delay)
1080 * to keep the panel power up across a sequence of operations
1081 */
1082 schedule_delayed_work(&intel_dp->panel_vdd_work,
1083 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1084 }
5d613501
JB		 1085}
1086
86a3073e 1087static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1088{
01cb9ea6 1089 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1090 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1091 u32 pp;
9934c132 1092
97af61f5 1093 if (!is_edp(intel_dp))
bd943159 1094 return;
99ea7127
KP		 1095
1096 DRM_DEBUG_KMS("Turn eDP power on\n");
1097
1098 if (ironlake_edp_have_panel_power(intel_dp)) {
1099 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1100 return;
99ea7127 1101 }
9934c132 1102
99ea7127 1103 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1104
99ea7127 1105 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1106 if (IS_GEN5(dev)) {
1107 /* ILK workaround: disable reset around power sequence */
1108 pp &= ~PANEL_POWER_RESET;
1109 I915_WRITE(PCH_PP_CONTROL, pp);
1110 POSTING_READ(PCH_PP_CONTROL);
1111 }
37c6c9b0 1112
1c0ae80a 1113 pp |= POWER_TARGET_ON;
99ea7127
KP		 1114 if (!IS_GEN5(dev))
1115 pp |= PANEL_POWER_RESET;
1116
9934c132 1117 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1118 POSTING_READ(PCH_PP_CONTROL);
9934c132 1119
99ea7127 1120 ironlake_wait_panel_on(intel_dp);
9934c132 1121
05ce1a49
KP		 1122 if (IS_GEN5(dev)) {
1123 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1124 I915_WRITE(PCH_PP_CONTROL, pp);
1125 POSTING_READ(PCH_PP_CONTROL);
1126 }
9934c132
JB		 1127}
1128
99ea7127 1129static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1130{
99ea7127 1131 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1132 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1133 u32 pp;
9934c132 1134
97af61f5
KP		 1135 if (!is_edp(intel_dp))
1136 return;
37c6c9b0 1137
99ea7127 1138 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1139
6cb49835 1140 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1141
99ea7127 1142 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1143 /* We need to switch off panel power _and_ force vdd, for otherwise some
1144 * panels get very unhappy and cease to work. */
1145 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1146 I915_WRITE(PCH_PP_CONTROL, pp);
1147 POSTING_READ(PCH_PP_CONTROL);
9934c132 1148
35a38556
DV		 1149 intel_dp->want_panel_vdd = false;
1150
99ea7127 1151 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1152}
1153
86a3073e 1154static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1155{
f01eca2e 1156 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1157 struct drm_i915_private *dev_priv = dev->dev_private;
1158 u32 pp;
1159
f01eca2e
KP		 1160 if (!is_edp(intel_dp))
1161 return;
1162
28c97730 1163 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1164 /*
1165 * If we enable the backlight right away following a panel power
1166 * on, we may see slight flicker as the panel syncs with the eDP
1167 * link. So delay a bit to make sure the image is solid before
1168 * allowing it to appear.
1169 */
f01eca2e 1170 msleep(intel_dp->backlight_on_delay);
832dd3c1 1171 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1172 pp |= EDP_BLC_ENABLE;
1173 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1174 POSTING_READ(PCH_PP_CONTROL);
32f9d658
ZW		 1175}
1176
86a3073e 1177static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1178{
f01eca2e 1179 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1180 struct drm_i915_private *dev_priv = dev->dev_private;
1181 u32 pp;
1182
f01eca2e
KP		 1183 if (!is_edp(intel_dp))
1184 return;
1185
28c97730 1186 DRM_DEBUG_KMS("\n");
832dd3c1 1187 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1188 pp &= ~EDP_BLC_ENABLE;
1189 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1190 POSTING_READ(PCH_PP_CONTROL);
1191 msleep(intel_dp->backlight_off_delay);
32f9d658 1192}
a4fc5ed6 1193
d240f20f
JB		 1194static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1195{
1196 struct drm_device *dev = encoder->dev;
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1198 u32 dpa_ctl;
1199
1200 DRM_DEBUG_KMS("\n");
1201 dpa_ctl = I915_READ(DP_A);
298b0b39 1202 dpa_ctl |= DP_PLL_ENABLE;
d240f20f 1203 I915_WRITE(DP_A, dpa_ctl);
298b0b39
JB		 1204 POSTING_READ(DP_A);
1205 udelay(200);
d240f20f
JB		 1206}
1207
1208static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1209{
1210 struct drm_device *dev = encoder->dev;
1211 struct drm_i915_private *dev_priv = dev->dev_private;
1212 u32 dpa_ctl;
1213
1214 dpa_ctl = I915_READ(DP_A);
298b0b39 1215 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1216 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1217 POSTING_READ(DP_A);
d240f20f
JB		 1218 udelay(200);
1219}
1220
c7ad3810
JB		 1221/* If the sink supports it, try to set the power state appropriately */
1222static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1223{
1224 int ret, i;
1225
1226 /* Should have a valid DPCD by this point */
1227 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1228 return;
1229
1230 if (mode != DRM_MODE_DPMS_ON) {
1231 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1232 DP_SET_POWER_D3);
1233 if (ret != 1)
1234 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1235 } else {
1236 /*
1237 * When turning on, we need to retry for 1ms to give the sink
1238 * time to wake up.
1239 */
1240 for (i = 0; i < 3; i++) {
1241 ret = intel_dp_aux_native_write_1(intel_dp,
1242 DP_SET_POWER,
1243 DP_SET_POWER_D0);
1244 if (ret == 1)
1245 break;
1246 msleep(1);
1247 }
1248 }
1249}
1250
19d8fe15
DV		 1251static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1252 enum pipe *pipe)
d240f20f 1253{
19d8fe15
DV		 1254 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1255 struct drm_device *dev = encoder->base.dev;
1256 struct drm_i915_private *dev_priv = dev->dev_private;
1257 u32 tmp = I915_READ(intel_dp->output_reg);
1258
1259 if (!(tmp & DP_PORT_EN))
1260 return false;
1261
1262 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1263 *pipe = PORT_TO_PIPE_CPT(tmp);
1264 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1265 *pipe = PORT_TO_PIPE(tmp);
1266 } else {
1267 u32 trans_sel;
1268 u32 trans_dp;
1269 int i;
1270
1271 switch (intel_dp->output_reg) {
1272 case PCH_DP_B:
1273 trans_sel = TRANS_DP_PORT_SEL_B;
1274 break;
1275 case PCH_DP_C:
1276 trans_sel = TRANS_DP_PORT_SEL_C;
1277 break;
1278 case PCH_DP_D:
1279 trans_sel = TRANS_DP_PORT_SEL_D;
1280 break;
1281 default:
1282 return true;
1283 }
1284
1285 for_each_pipe(i) {
1286 trans_dp = I915_READ(TRANS_DP_CTL(i));
1287 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1288 *pipe = i;
1289 return true;
1290 }
1291 }
1292 }
1293
1294 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
d240f20f 1295
19d8fe15
DV		 1296 return true;
1297}
1298
e8cb4558 1299static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1300{
e8cb4558 1301 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1302
1303 /* Make sure the panel is off before trying to change the mode. But also
1304 * ensure that we have vdd while we switch off the panel. */
1305 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1306 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1307 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1308 ironlake_edp_panel_off(intel_dp);
21264c63 1309 intel_dp_link_down(intel_dp);
d240f20f
JB		 1310}
1311
e8cb4558 1312static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1313{
e8cb4558
DV		 1314 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1315 struct drm_device *dev = encoder->base.dev;
1316 struct drm_i915_private *dev_priv = dev->dev_private;
1317 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1318
97af61f5 1319 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1320 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
e8cb4558
DV		 1321 if (!(dp_reg & DP_PORT_EN)) {
1322 intel_dp_start_link_train(intel_dp);
1323 ironlake_edp_panel_on(intel_dp);
1324 ironlake_edp_panel_vdd_off(intel_dp, true);
1325 intel_dp_complete_link_train(intel_dp);
1326 } else
1327 ironlake_edp_panel_vdd_off(intel_dp, false);
f01eca2e 1328 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1329}
1330
a4fc5ed6 1331static void
e8cb4558 1332intel_dp_dpms(struct drm_connector *connector, int mode)
a4fc5ed6 1333{
e8cb4558
DV		 1334 struct intel_dp *intel_dp = intel_attached_dp(connector);
1335
1336 /* DP supports only 2 dpms states. */
1337 if (mode != DRM_MODE_DPMS_ON)
1338 mode = DRM_MODE_DPMS_OFF;
1339
1340 if (mode == connector->dpms)
1341 return;
1342
1343 connector->dpms = mode;
1344
1345 /* Only need to change hw state when actually enabled */
1346 if (!intel_dp->base.base.crtc) {
1347 intel_dp->base.connectors_active = false;
1348 return;
1349 }
a4fc5ed6
KP		 1350
1351 if (mode != DRM_MODE_DPMS_ON) {
e8cb4558 1352 intel_encoder_dpms(&intel_dp->base, mode);
21264c63
KP		 1353
1354 if (is_cpu_edp(intel_dp))
e8cb4558 1355 ironlake_edp_pll_off(&intel_dp->base.base);
a4fc5ed6 1356 } else {
21264c63 1357 if (is_cpu_edp(intel_dp))
e8cb4558 1358 ironlake_edp_pll_on(&intel_dp->base.base);
21264c63 1359
e8cb4558 1360 intel_encoder_dpms(&intel_dp->base, mode);
a4fc5ed6 1361 }
0a91ca29 1362
b980514c 1363 intel_modeset_check_state(connector->dev);
a4fc5ed6
KP		 1364}
1365
1366/*
df0c237d
JB		 1367 * Native read with retry for link status and receiver capability reads for
1368 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1369 */
1370static bool
df0c237d
JB		 1371intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1372 uint8_t *recv, int recv_bytes)
a4fc5ed6 1373{
61da5fab
JB		 1374 int ret, i;
1375
df0c237d
JB		 1376 /*
1377 * Sinks are *supposed* to come up within 1ms from an off state,
1378 * but we're also supposed to retry 3 times per the spec.
1379 */
61da5fab 1380 for (i = 0; i < 3; i++) {
df0c237d
JB		 1381 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1382 recv_bytes);
1383 if (ret == recv_bytes)
61da5fab
JB		 1384 return true;
1385 msleep(1);
1386 }
a4fc5ed6 1387
61da5fab 1388 return false;
a4fc5ed6
KP		 1389}
1390
1391/*
1392 * Fetch AUX CH registers 0x202 - 0x207 which contain
1393 * link status information
1394 */
1395static bool
93f62dad 1396intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1397{
df0c237d
JB		 1398 return intel_dp_aux_native_read_retry(intel_dp,
1399 DP_LANE0_1_STATUS,
93f62dad 1400 link_status,
df0c237d 1401 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1402}
1403
1404static uint8_t
1405intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1406 int r)
1407{
1408 return link_status[r - DP_LANE0_1_STATUS];
1409}
1410
a4fc5ed6 1411static uint8_t
93f62dad 1412intel_get_adjust_request_voltage(uint8_t adjust_request[2],
a4fc5ed6
KP		 1413 int lane)
1414{
a4fc5ed6
KP		 1415 int s = ((lane & 1) ?
1416 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1417 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
93f62dad 1418 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1419
1420 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1421}
1422
1423static uint8_t
93f62dad 1424intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
a4fc5ed6
KP		 1425 int lane)
1426{
a4fc5ed6
KP		 1427 int s = ((lane & 1) ?
1428 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1429 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
93f62dad 1430 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1431
1432 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1433}
1434
1435
1436#if 0
1437static char *voltage_names[] = {
1438 "0.4V", "0.6V", "0.8V", "1.2V"
1439};
1440static char *pre_emph_names[] = {
1441 "0dB", "3.5dB", "6dB", "9.5dB"
1442};
1443static char *link_train_names[] = {
1444 "pattern 1", "pattern 2", "idle", "off"
1445};
1446#endif
1447
1448/*
1449 * These are source-specific values; current Intel hardware supports
1450 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1451 */
a4fc5ed6
KP		 1452
1453static uint8_t
1a2eb460 1454intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1455{
1a2eb460
KP		 1456 struct drm_device *dev = intel_dp->base.base.dev;
1457
1458 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1459 return DP_TRAIN_VOLTAGE_SWING_800;
1460 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1461 return DP_TRAIN_VOLTAGE_SWING_1200;
1462 else
1463 return DP_TRAIN_VOLTAGE_SWING_800;
1464}
1465
1466static uint8_t
1467intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1468{
1469 struct drm_device *dev = intel_dp->base.base.dev;
1470
1471 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1472 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1473 case DP_TRAIN_VOLTAGE_SWING_400:
1474 return DP_TRAIN_PRE_EMPHASIS_6;
1475 case DP_TRAIN_VOLTAGE_SWING_600:
1476 case DP_TRAIN_VOLTAGE_SWING_800:
1477 return DP_TRAIN_PRE_EMPHASIS_3_5;
1478 default:
1479 return DP_TRAIN_PRE_EMPHASIS_0;
1480 }
1481 } else {
1482 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1483 case DP_TRAIN_VOLTAGE_SWING_400:
1484 return DP_TRAIN_PRE_EMPHASIS_6;
1485 case DP_TRAIN_VOLTAGE_SWING_600:
1486 return DP_TRAIN_PRE_EMPHASIS_6;
1487 case DP_TRAIN_VOLTAGE_SWING_800:
1488 return DP_TRAIN_PRE_EMPHASIS_3_5;
1489 case DP_TRAIN_VOLTAGE_SWING_1200:
1490 default:
1491 return DP_TRAIN_PRE_EMPHASIS_0;
1492 }
a4fc5ed6
KP		 1493 }
1494}
1495
1496static void
93f62dad 1497intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1498{
1499 uint8_t v = 0;
1500 uint8_t p = 0;
1501 int lane;
93f62dad 1502 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1a2eb460
KP		 1503 uint8_t voltage_max;
1504 uint8_t preemph_max;
a4fc5ed6 1505
33a34e4e 1506 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad
KP		 1507 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1508 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
a4fc5ed6
KP		 1509
1510 if (this_v > v)
1511 v = this_v;
1512 if (this_p > p)
1513 p = this_p;
1514 }
1515
1a2eb460 1516 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1517 if (v >= voltage_max)
1518 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1519
1a2eb460
KP		 1520 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1521 if (p >= preemph_max)
1522 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1523
1524 for (lane = 0; lane < 4; lane++)
33a34e4e 1525 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1526}
1527
1528static uint32_t
93f62dad 1529intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1530{
3cf2efb1 1531 uint32_t signal_levels = 0;
a4fc5ed6 1532
3cf2efb1 1533 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1534 case DP_TRAIN_VOLTAGE_SWING_400:
1535 default:
1536 signal_levels |= DP_VOLTAGE_0_4;
1537 break;
1538 case DP_TRAIN_VOLTAGE_SWING_600:
1539 signal_levels |= DP_VOLTAGE_0_6;
1540 break;
1541 case DP_TRAIN_VOLTAGE_SWING_800:
1542 signal_levels |= DP_VOLTAGE_0_8;
1543 break;
1544 case DP_TRAIN_VOLTAGE_SWING_1200:
1545 signal_levels |= DP_VOLTAGE_1_2;
1546 break;
1547 }
3cf2efb1 1548 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1549 case DP_TRAIN_PRE_EMPHASIS_0:
1550 default:
1551 signal_levels |= DP_PRE_EMPHASIS_0;
1552 break;
1553 case DP_TRAIN_PRE_EMPHASIS_3_5:
1554 signal_levels |= DP_PRE_EMPHASIS_3_5;
1555 break;
1556 case DP_TRAIN_PRE_EMPHASIS_6:
1557 signal_levels |= DP_PRE_EMPHASIS_6;
1558 break;
1559 case DP_TRAIN_PRE_EMPHASIS_9_5:
1560 signal_levels |= DP_PRE_EMPHASIS_9_5;
1561 break;
1562 }
1563 return signal_levels;
1564}
1565
e3421a18
ZW		 1566/* Gen6's DP voltage swing and pre-emphasis control */
1567static uint32_t
1568intel_gen6_edp_signal_levels(uint8_t train_set)
1569{
3c5a62b5
YL		 1570 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1571 DP_TRAIN_PRE_EMPHASIS_MASK);
1572 switch (signal_levels) {
e3421a18 1573 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1574 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1575 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1576 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1577 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1578 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1579 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1580 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1581 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1582 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1583 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1584 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1585 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1586 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1587 default:
3c5a62b5
YL		 1588 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1589 "0x%x\n", signal_levels);
1590 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1591 }
1592}
1593
1a2eb460
KP		 1594/* Gen7's DP voltage swing and pre-emphasis control */
1595static uint32_t
1596intel_gen7_edp_signal_levels(uint8_t train_set)
1597{
1598 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1599 DP_TRAIN_PRE_EMPHASIS_MASK);
1600 switch (signal_levels) {
1601 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1602 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1603 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1604 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1605 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1606 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1607
1608 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1609 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1610 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1611 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1612
1613 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1614 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1615 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1616 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1617
1618 default:
1619 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1620 "0x%x\n", signal_levels);
1621 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1622 }
1623}
1624
a4fc5ed6
KP		 1625static uint8_t
1626intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1627 int lane)
1628{
a4fc5ed6 1629 int s = (lane & 1) * 4;
93f62dad 1630 uint8_t l = link_status[lane>>1];
a4fc5ed6
KP		 1631
1632 return (l >> s) & 0xf;
1633}
1634
1635/* Check for clock recovery is done on all channels */
1636static bool
1637intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1638{
1639 int lane;
1640 uint8_t lane_status;
1641
1642 for (lane = 0; lane < lane_count; lane++) {
1643 lane_status = intel_get_lane_status(link_status, lane);
1644 if ((lane_status & DP_LANE_CR_DONE) == 0)
1645 return false;
1646 }
1647 return true;
1648}
1649
1650/* Check to see if channel eq is done on all channels */
1651#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1652 DP_LANE_CHANNEL_EQ_DONE|\
1653 DP_LANE_SYMBOL_LOCKED)
1654static bool
93f62dad 1655intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1656{
1657 uint8_t lane_align;
1658 uint8_t lane_status;
1659 int lane;
1660
93f62dad 1661 lane_align = intel_dp_link_status(link_status,
a4fc5ed6
KP		 1662 DP_LANE_ALIGN_STATUS_UPDATED);
1663 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1664 return false;
33a34e4e 1665 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad 1666 lane_status = intel_get_lane_status(link_status, lane);
a4fc5ed6
KP		 1667 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1668 return false;
1669 }
1670 return true;
1671}
1672
1673static bool
ea5b213a 1674intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1675 uint32_t dp_reg_value,
58e10eb9 1676 uint8_t dp_train_pat)
a4fc5ed6 1677{
4ef69c7a 1678 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1679 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1680 int ret;
1681
47ea7542
PZ		 1682 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1683 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1684
1685 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1686 case DP_TRAINING_PATTERN_DISABLE:
1687 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1688 break;
1689 case DP_TRAINING_PATTERN_1:
1690 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1691 break;
1692 case DP_TRAINING_PATTERN_2:
1693 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1694 break;
1695 case DP_TRAINING_PATTERN_3:
1696 DRM_ERROR("DP training pattern 3 not supported\n");
1697 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1698 break;
1699 }
1700
1701 } else {
1702 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1703
1704 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1705 case DP_TRAINING_PATTERN_DISABLE:
1706 dp_reg_value |= DP_LINK_TRAIN_OFF;
1707 break;
1708 case DP_TRAINING_PATTERN_1:
1709 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1710 break;
1711 case DP_TRAINING_PATTERN_2:
1712 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1713 break;
1714 case DP_TRAINING_PATTERN_3:
1715 DRM_ERROR("DP training pattern 3 not supported\n");
1716 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1717 break;
1718 }
1719 }
1720
ea5b213a
CW		 1721 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1722 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1723
ea5b213a 1724 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1725 DP_TRAINING_PATTERN_SET,
1726 dp_train_pat);
1727
47ea7542
PZ		 1728 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1729 DP_TRAINING_PATTERN_DISABLE) {
1730 ret = intel_dp_aux_native_write(intel_dp,
1731 DP_TRAINING_LANE0_SET,
1732 intel_dp->train_set,
1733 intel_dp->lane_count);
1734 if (ret != intel_dp->lane_count)
1735 return false;
1736 }
a4fc5ed6
KP		 1737
1738 return true;
1739}
1740
33a34e4e 1741/* Enable corresponding port and start training pattern 1 */
a4fc5ed6 1742static void
33a34e4e 1743intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1744{
4ef69c7a 1745 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 1746 int i;
1747 uint8_t voltage;
1748 bool clock_recovery = false;
cdb0e95b 1749 int voltage_tries, loop_tries;
ea5b213a 1750 uint32_t DP = intel_dp->DP;
a4fc5ed6 1751
3cf2efb1
CW		 1752 /* Write the link configuration data */
1753 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1754 intel_dp->link_configuration,
1755 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1756
1757 DP |= DP_PORT_EN;
1a2eb460 1758
33a34e4e 1759 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1760 voltage = 0xff;
cdb0e95b
KP		 1761 voltage_tries = 0;
1762 loop_tries = 0;
a4fc5ed6
KP		 1763 clock_recovery = false;
1764 for (;;) {
33a34e4e 1765 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1766 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1767 uint32_t signal_levels;
417e822d 1768
1a2eb460
KP		 1769
1770 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1771 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1772 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1773 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1774 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1775 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1776 } else {
93f62dad
KP		 1777 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1778 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
e3421a18
ZW		 1779 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1780 }
a4fc5ed6 1781
47ea7542 1782 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1783 DP_TRAINING_PATTERN_1 |
1784 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1785 break;
a4fc5ed6
KP		 1786 /* Set training pattern 1 */
1787
3cf2efb1 1788 udelay(100);
93f62dad
KP		 1789 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1790 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1791 break;
93f62dad 1792 }
a4fc5ed6 1793
93f62dad
KP		 1794 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1795 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1796 clock_recovery = true;
1797 break;
1798 }
1799
1800 /* Check to see if we've tried the max voltage */
1801 for (i = 0; i < intel_dp->lane_count; i++)
1802 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1803 break;
0d710688 1804 if (i == intel_dp->lane_count && voltage_tries == 5) {
cdb0e95b
KP		 1805 ++loop_tries;
1806 if (loop_tries == 5) {
1807 DRM_DEBUG_KMS("too many full retries, give up\n");
1808 break;
1809 }
1810 memset(intel_dp->train_set, 0, 4);
1811 voltage_tries = 0;
1812 continue;
1813 }
a4fc5ed6 1814
3cf2efb1
CW		 1815 /* Check to see if we've tried the same voltage 5 times */
1816 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
cdb0e95b
KP		 1817 ++voltage_tries;
1818 if (voltage_tries == 5) {
1819 DRM_DEBUG_KMS("too many voltage retries, give up\n");
a4fc5ed6 1820 break;
cdb0e95b 1821 }
3cf2efb1 1822 } else
cdb0e95b 1823 voltage_tries = 0;
3cf2efb1 1824 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1825
3cf2efb1 1826 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1827 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1828 }
1829
33a34e4e
JB		 1830 intel_dp->DP = DP;
1831}
1832
1833static void
1834intel_dp_complete_link_train(struct intel_dp *intel_dp)
1835{
4ef69c7a 1836 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e 1837 bool channel_eq = false;
37f80975 1838 int tries, cr_tries;
33a34e4e
JB		 1839 uint32_t DP = intel_dp->DP;
1840
a4fc5ed6
KP		 1841 /* channel equalization */
1842 tries = 0;
37f80975 1843 cr_tries = 0;
a4fc5ed6
KP		 1844 channel_eq = false;
1845 for (;;) {
33a34e4e 1846 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1847 uint32_t signal_levels;
93f62dad 1848 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1849
37f80975
JB		 1850 if (cr_tries > 5) {
1851 DRM_ERROR("failed to train DP, aborting\n");
1852 intel_dp_link_down(intel_dp);
1853 break;
1854 }
1855
1a2eb460
KP		 1856 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1857 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1858 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1859 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1860 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1861 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1862 } else {
93f62dad 1863 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1864 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1865 }
1866
a4fc5ed6 1867 /* channel eq pattern */
47ea7542 1868 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1869 DP_TRAINING_PATTERN_2 |
1870 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1871 break;
1872
3cf2efb1 1873 udelay(400);
93f62dad 1874 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1875 break;
a4fc5ed6 1876
37f80975 1877 /* Make sure clock is still ok */
93f62dad 1878 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1879 intel_dp_start_link_train(intel_dp);
1880 cr_tries++;
1881 continue;
1882 }
1883
93f62dad 1884 if (intel_channel_eq_ok(intel_dp, link_status)) {
3cf2efb1
CW		 1885 channel_eq = true;
1886 break;
1887 }
a4fc5ed6 1888
37f80975
JB		 1889 /* Try 5 times, then try clock recovery if that fails */
1890 if (tries > 5) {
1891 intel_dp_link_down(intel_dp);
1892 intel_dp_start_link_train(intel_dp);
1893 tries = 0;
1894 cr_tries++;
1895 continue;
1896 }
a4fc5ed6 1897
3cf2efb1 1898 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1899 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1900 ++tries;
869184a6 1901 }
3cf2efb1 1902
47ea7542 1903 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 1904}
1905
1906static void
ea5b213a 1907intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1908{
4ef69c7a 1909 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1910 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1911 uint32_t DP = intel_dp->DP;
a4fc5ed6 1912
1b39d6f3
CW		 1913 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1914 return;
1915
28c97730 1916 DRM_DEBUG_KMS("\n");
32f9d658 1917
cfcb0fc9 1918 if (is_edp(intel_dp)) {
32f9d658 1919 DP &= ~DP_PLL_ENABLE;
ea5b213a
CW		 1920 I915_WRITE(intel_dp->output_reg, DP);
1921 POSTING_READ(intel_dp->output_reg);
32f9d658
ZW		 1922 udelay(100);
1923 }
1924
1a2eb460 1925 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1926 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1927 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1928 } else {
1929 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1930 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1931 }
fe255d00 1932 POSTING_READ(intel_dp->output_reg);
5eb08b69 1933
fe255d00 1934 msleep(17);
5eb08b69 1935
417e822d 1936 if (is_edp(intel_dp)) {
1a2eb460 1937 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
417e822d
KP		 1938 DP |= DP_LINK_TRAIN_OFF_CPT;
1939 else
1940 DP |= DP_LINK_TRAIN_OFF;
1941 }
5bddd17f 1942
493a7081 1943 if (HAS_PCH_IBX(dev) &&
1b39d6f3 1944 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 1945 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1946
5bddd17f
EA		 1947 /* Hardware workaround: leaving our transcoder select
1948 * set to transcoder B while it's off will prevent the
1949 * corresponding HDMI output on transcoder A.
1950 *
1951 * Combine this with another hardware workaround:
1952 * transcoder select bit can only be cleared while the
1953 * port is enabled.
1954 */
1955 DP &= ~DP_PIPEB_SELECT;
1956 I915_WRITE(intel_dp->output_reg, DP);
1957
1958 /* Changes to enable or select take place the vblank
1959 * after being written.
1960 */
31acbcc4
CW		 1961 if (crtc == NULL) {
1962 /* We can arrive here never having been attached
1963 * to a CRTC, for instance, due to inheriting
1964 * random state from the BIOS.
1965 *
1966 * If the pipe is not running, play safe and
1967 * wait for the clocks to stabilise before
1968 * continuing.
1969 */
1970 POSTING_READ(intel_dp->output_reg);
1971 msleep(50);
1972 } else
1973 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 1974 }
1975
832afda6 1976 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 1977 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1978 POSTING_READ(intel_dp->output_reg);
f01eca2e 1979 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 1980}
1981
26d61aad
KP		 1982static bool
1983intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 1984{
92fd8fd1 1985 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
0206e353 1986 sizeof(intel_dp->dpcd)) &&
92fd8fd1 1987 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
26d61aad 1988 return true;
92fd8fd1
KP		 1989 }
1990
26d61aad 1991 return false;
92fd8fd1
KP		 1992}
1993
0d198328
AJ		 1994static void
1995intel_dp_probe_oui(struct intel_dp *intel_dp)
1996{
1997 u8 buf[3];
1998
1999 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2000 return;
2001
351cfc34
DV		 2002 ironlake_edp_panel_vdd_on(intel_dp);
2003
0d198328
AJ		 2004 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2005 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2006 buf[0], buf[1], buf[2]);
2007
2008 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2009 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2010 buf[0], buf[1], buf[2]);
351cfc34
DV		 2011
2012 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2013}
2014
a60f0e38
JB		 2015static bool
2016intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2017{
2018 int ret;
2019
2020 ret = intel_dp_aux_native_read_retry(intel_dp,
2021 DP_DEVICE_SERVICE_IRQ_VECTOR,
2022 sink_irq_vector, 1);
2023 if (!ret)
2024 return false;
2025
2026 return true;
2027}
2028
2029static void
2030intel_dp_handle_test_request(struct intel_dp *intel_dp)
2031{
2032 /* NAK by default */
2033 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2034}
2035
a4fc5ed6
KP		 2036/*
2037 * According to DP spec
2038 * 5.1.2:
2039 * 1. Read DPCD
2040 * 2. Configure link according to Receiver Capabilities
2041 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2042 * 4. Check link status on receipt of hot-plug interrupt
2043 */
2044
2045static void
ea5b213a 2046intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2047{
a60f0e38 2048 u8 sink_irq_vector;
93f62dad 2049 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2050
24e804ba 2051 if (!intel_dp->base.connectors_active)
d2b996ac 2052 return;
59cd09e1 2053
24e804ba 2054 if (WARN_ON(!intel_dp->base.base.crtc))
a4fc5ed6
KP		 2055 return;
2056
92fd8fd1 2057 /* Try to read receiver status if the link appears to be up */
93f62dad 2058 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2059 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2060 return;
2061 }
2062
92fd8fd1 2063 /* Now read the DPCD to see if it's actually running */
26d61aad 2064 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2065 intel_dp_link_down(intel_dp);
2066 return;
2067 }
2068
a60f0e38
JB		 2069 /* Try to read the source of the interrupt */
2070 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2071 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2072 /* Clear interrupt source */
2073 intel_dp_aux_native_write_1(intel_dp,
2074 DP_DEVICE_SERVICE_IRQ_VECTOR,
2075 sink_irq_vector);
2076
2077 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2078 intel_dp_handle_test_request(intel_dp);
2079 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2080 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2081 }
2082
93f62dad 2083 if (!intel_channel_eq_ok(intel_dp, link_status)) {
92fd8fd1
KP		 2084 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2085 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2086 intel_dp_start_link_train(intel_dp);
2087 intel_dp_complete_link_train(intel_dp);
2088 }
a4fc5ed6 2089}
a4fc5ed6 2090
71ba9000 2091static enum drm_connector_status
26d61aad 2092intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2093{
26d61aad
KP		 2094 if (intel_dp_get_dpcd(intel_dp))
2095 return connector_status_connected;
2096 return connector_status_disconnected;
71ba9000
AJ		 2097}
2098
5eb08b69 2099static enum drm_connector_status
a9756bb5 2100ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2101{
5eb08b69
ZW		 2102 enum drm_connector_status status;
2103
fe16d949
CW		 2104 /* Can't disconnect eDP, but you can close the lid... */
2105 if (is_edp(intel_dp)) {
2106 status = intel_panel_detect(intel_dp->base.base.dev);
2107 if (status == connector_status_unknown)
2108 status = connector_status_connected;
2109 return status;
2110 }
01cb9ea6 2111
26d61aad 2112 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2113}
2114
a4fc5ed6 2115static enum drm_connector_status
a9756bb5 2116g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2117{
4ef69c7a 2118 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2119 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2120 uint32_t bit;
5eb08b69 2121
ea5b213a 2122 switch (intel_dp->output_reg) {
a4fc5ed6 2123 case DP_B:
10f76a38 2124 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2125 break;
2126 case DP_C:
10f76a38 2127 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2128 break;
2129 case DP_D:
10f76a38 2130 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2131 break;
2132 default:
2133 return connector_status_unknown;
2134 }
2135
10f76a38 2136 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2137 return connector_status_disconnected;
2138
26d61aad 2139 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2140}
2141
8c241fef
KP		 2142static struct edid *
2143intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2144{
2145 struct intel_dp *intel_dp = intel_attached_dp(connector);
2146 struct edid *edid;
d6f24d0f
JB		 2147 int size;
2148
2149 if (is_edp(intel_dp)) {
2150 if (!intel_dp->edid)
2151 return NULL;
2152
2153 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2154 edid = kmalloc(size, GFP_KERNEL);
2155 if (!edid)
2156 return NULL;
2157
2158 memcpy(edid, intel_dp->edid, size);
2159 return edid;
2160 }
8c241fef 2161
8c241fef 2162 edid = drm_get_edid(connector, adapter);
8c241fef
KP		 2163 return edid;
2164}
2165
2166static int
2167intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2168{
2169 struct intel_dp *intel_dp = intel_attached_dp(connector);
2170 int ret;
2171
d6f24d0f
JB		 2172 if (is_edp(intel_dp)) {
2173 drm_mode_connector_update_edid_property(connector,
2174 intel_dp->edid);
2175 ret = drm_add_edid_modes(connector, intel_dp->edid);
2176 drm_edid_to_eld(connector,
2177 intel_dp->edid);
d6f24d0f
JB		 2178 return intel_dp->edid_mode_count;
2179 }
2180
8c241fef 2181 ret = intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2182 return ret;
2183}
2184
2185
a9756bb5
ZW		 2186/**
2187 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2188 *
2189 * \return true if DP port is connected.
2190 * \return false if DP port is disconnected.
2191 */
2192static enum drm_connector_status
2193intel_dp_detect(struct drm_connector *connector, bool force)
2194{
2195 struct intel_dp *intel_dp = intel_attached_dp(connector);
2196 struct drm_device *dev = intel_dp->base.base.dev;
2197 enum drm_connector_status status;
2198 struct edid *edid = NULL;
2199
2200 intel_dp->has_audio = false;
2201
2202 if (HAS_PCH_SPLIT(dev))
2203 status = ironlake_dp_detect(intel_dp);
2204 else
2205 status = g4x_dp_detect(intel_dp);
1b9be9d0 2206
ac66ae83
AJ		 2207 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2208 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2209 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2210 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 2211
a9756bb5
ZW		 2212 if (status != connector_status_connected)
2213 return status;
2214
0d198328
AJ		 2215 intel_dp_probe_oui(intel_dp);
2216
c3e5f67b
DV		 2217 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2218 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2219 } else {
8c241fef 2220 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2221 if (edid) {
2222 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2223 kfree(edid);
2224 }
a9756bb5
ZW		 2225 }
2226
2227 return connector_status_connected;
a4fc5ed6
KP		 2228}
2229
2230static int intel_dp_get_modes(struct drm_connector *connector)
2231{
df0e9248 2232 struct intel_dp *intel_dp = intel_attached_dp(connector);
4ef69c7a 2233 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 int ret;
a4fc5ed6
KP		 2236
2237 /* We should parse the EDID data and find out if it has an audio sink
2238 */
2239
8c241fef 2240 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
b9efc480 2241 if (ret) {
d15456de 2242 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
b9efc480
ZY		 2243 struct drm_display_mode *newmode;
2244 list_for_each_entry(newmode, &connector->probed_modes,
2245 head) {
d15456de
KP		 2246 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2247 intel_dp->panel_fixed_mode =
b9efc480
ZY		 2248 drm_mode_duplicate(dev, newmode);
2249 break;
2250 }
2251 }
2252 }
32f9d658 2253 return ret;
b9efc480 2254 }
32f9d658
ZW		 2255
2256 /* if eDP has no EDID, try to use fixed panel mode from VBT */
4d926461 2257 if (is_edp(intel_dp)) {
47f0eb22 2258 /* initialize panel mode from VBT if available for eDP */
d15456de
KP		 2259 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2260 intel_dp->panel_fixed_mode =
47f0eb22 2261 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
d15456de
KP		 2262 if (intel_dp->panel_fixed_mode) {
2263 intel_dp->panel_fixed_mode->type |=
47f0eb22
KP		 2264 DRM_MODE_TYPE_PREFERRED;
2265 }
2266 }
d15456de 2267 if (intel_dp->panel_fixed_mode) {
32f9d658 2268 struct drm_display_mode *mode;
d15456de 2269 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
32f9d658
ZW		 2270 drm_mode_probed_add(connector, mode);
2271 return 1;
2272 }
2273 }
2274 return 0;
a4fc5ed6
KP		 2275}
2276
1aad7ac0
CW		 2277static bool
2278intel_dp_detect_audio(struct drm_connector *connector)
2279{
2280 struct intel_dp *intel_dp = intel_attached_dp(connector);
2281 struct edid *edid;
2282 bool has_audio = false;
2283
8c241fef 2284 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2285 if (edid) {
2286 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2287 kfree(edid);
2288 }
2289
2290 return has_audio;
2291}
2292
f684960e
CW		 2293static int
2294intel_dp_set_property(struct drm_connector *connector,
2295 struct drm_property *property,
2296 uint64_t val)
2297{
e953fd7b 2298 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2299 struct intel_dp *intel_dp = intel_attached_dp(connector);
2300 int ret;
2301
2302 ret = drm_connector_property_set_value(connector, property, val);
2303 if (ret)
2304 return ret;
2305
3f43c48d 2306 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2307 int i = val;
2308 bool has_audio;
2309
2310 if (i == intel_dp->force_audio)
f684960e
CW		 2311 return 0;
2312
1aad7ac0 2313 intel_dp->force_audio = i;
f684960e 2314
c3e5f67b 2315 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2316 has_audio = intel_dp_detect_audio(connector);
2317 else
c3e5f67b 2318 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2319
2320 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2321 return 0;
2322
1aad7ac0 2323 intel_dp->has_audio = has_audio;
f684960e
CW		 2324 goto done;
2325 }
2326
e953fd7b
CW		 2327 if (property == dev_priv->broadcast_rgb_property) {
2328 if (val == !!intel_dp->color_range)
2329 return 0;
2330
2331 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2332 goto done;
2333 }
2334
f684960e
CW		 2335 return -EINVAL;
2336
2337done:
2338 if (intel_dp->base.base.crtc) {
2339 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a6778b3c
DV		 2340 intel_set_mode(crtc, &crtc->mode,
2341 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2342 }
2343
2344 return 0;
2345}
2346
a4fc5ed6 2347static void
0206e353 2348intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2349{
aaa6fd2a
MG		 2350 struct drm_device *dev = connector->dev;
2351
2352 if (intel_dpd_is_edp(dev))
2353 intel_panel_destroy_backlight(dev);
2354
a4fc5ed6
KP		 2355 drm_sysfs_connector_remove(connector);
2356 drm_connector_cleanup(connector);
55f78c43 2357 kfree(connector);
a4fc5ed6
KP		 2358}
2359
24d05927
DV		 2360static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2361{
2362 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2363
2364 i2c_del_adapter(&intel_dp->adapter);
2365 drm_encoder_cleanup(encoder);
bd943159 2366 if (is_edp(intel_dp)) {
d6f24d0f 2367 kfree(intel_dp->edid);
bd943159
KP		 2368 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2369 ironlake_panel_vdd_off_sync(intel_dp);
2370 }
24d05927
DV		 2371 kfree(intel_dp);
2372}
2373
a4fc5ed6 2374static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2375 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2376 .mode_set = intel_dp_mode_set,
1f703855 2377 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2378};
2379
2380static const struct drm_connector_funcs intel_dp_connector_funcs = {
e8cb4558 2381 .dpms = intel_dp_dpms,
a4fc5ed6
KP		 2382 .detect = intel_dp_detect,
2383 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2384 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2385 .destroy = intel_dp_destroy,
2386};
2387
2388static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2389 .get_modes = intel_dp_get_modes,
2390 .mode_valid = intel_dp_mode_valid,
df0e9248 2391 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2392};
2393
a4fc5ed6 2394static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2395 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2396};
2397
995b6762 2398static void
21d40d37 2399intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2400{
ea5b213a 2401 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2402
885a5014 2403 intel_dp_check_link_status(intel_dp);
c8110e52 2404}
6207937d 2405
e3421a18
ZW		 2406/* Return which DP Port should be selected for Transcoder DP control */
2407int
0206e353 2408intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2409{
2410 struct drm_device *dev = crtc->dev;
6c2b7c12 2411 struct intel_encoder *encoder;
e3421a18 2412
6c2b7c12
DV		 2413 for_each_encoder_on_crtc(dev, crtc, encoder) {
2414 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
e3421a18 2415
417e822d
KP		 2416 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2417 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2418 return intel_dp->output_reg;
e3421a18 2419 }
ea5b213a 2420
e3421a18
ZW		 2421 return -1;
2422}
2423
36e83a18 2424/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2425bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2426{
2427 struct drm_i915_private *dev_priv = dev->dev_private;
2428 struct child_device_config *p_child;
2429 int i;
2430
2431 if (!dev_priv->child_dev_num)
2432 return false;
2433
2434 for (i = 0; i < dev_priv->child_dev_num; i++) {
2435 p_child = dev_priv->child_dev + i;
2436
2437 if (p_child->dvo_port == PORT_IDPD &&
2438 p_child->device_type == DEVICE_TYPE_eDP)
2439 return true;
2440 }
2441 return false;
2442}
2443
f684960e
CW		 2444static void
2445intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2446{
3f43c48d 2447 intel_attach_force_audio_property(connector);
e953fd7b 2448 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2449}
2450
a4fc5ed6 2451void
ab9d7c30 2452intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
a4fc5ed6
KP		 2453{
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 struct drm_connector *connector;
ea5b213a 2456 struct intel_dp *intel_dp;
21d40d37 2457 struct intel_encoder *intel_encoder;
55f78c43 2458 struct intel_connector *intel_connector;
5eb08b69 2459 const char *name = NULL;
b329530c 2460 int type;
a4fc5ed6 2461
ea5b213a
CW		 2462 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2463 if (!intel_dp)
a4fc5ed6
KP		 2464 return;
2465
3d3dc149 2466 intel_dp->output_reg = output_reg;
ab9d7c30 2467 intel_dp->port = port;
3d3dc149 2468
55f78c43
ZW		 2469 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2470 if (!intel_connector) {
ea5b213a 2471 kfree(intel_dp);
55f78c43
ZW		 2472 return;
2473 }
ea5b213a 2474 intel_encoder = &intel_dp->base;
55f78c43 2475
ea5b213a 2476 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2477 if (intel_dpd_is_edp(dev))
ea5b213a 2478 intel_dp->is_pch_edp = true;
b329530c 2479
cfcb0fc9 2480 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2481 type = DRM_MODE_CONNECTOR_eDP;
2482 intel_encoder->type = INTEL_OUTPUT_EDP;
2483 } else {
2484 type = DRM_MODE_CONNECTOR_DisplayPort;
2485 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2486 }
2487
55f78c43 2488 connector = &intel_connector->base;
b329530c 2489 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2490 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2491
eb1f8e4f
DA		 2492 connector->polled = DRM_CONNECTOR_POLL_HPD;
2493
66a9278e 2494 intel_encoder->cloneable = false;
f8aed700 2495
66a9278e
DV		 2496 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2497 ironlake_panel_vdd_work);
6251ec0a 2498
27f8227b 2499 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2500
a4fc5ed6
KP		 2501 connector->interlace_allowed = true;
2502 connector->doublescan_allowed = 0;
2503
4ef69c7a 2504 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2505 DRM_MODE_ENCODER_TMDS);
4ef69c7a 2506 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
a4fc5ed6 2507
df0e9248 2508 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2509 drm_sysfs_connector_add(connector);
2510
e8cb4558
DV		 2511 intel_encoder->enable = intel_enable_dp;
2512 intel_encoder->disable = intel_disable_dp;
19d8fe15
DV		 2513 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2514 intel_connector->get_hw_state = intel_connector_get_hw_state;
e8cb4558 2515
a4fc5ed6 2516 /* Set up the DDC bus. */
ab9d7c30
PZ		 2517 switch (port) {
2518 case PORT_A:
2519 name = "DPDDC-A";
2520 break;
2521 case PORT_B:
2522 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2523 name = "DPDDC-B";
2524 break;
2525 case PORT_C:
2526 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2527 name = "DPDDC-C";
2528 break;
2529 case PORT_D:
2530 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2531 name = "DPDDC-D";
2532 break;
2533 default:
2534 WARN(1, "Invalid port %c\n", port_name(port));
2535 break;
5eb08b69
ZW		 2536 }
2537
d6f24d0f
JB		 2538 intel_dp_i2c_init(intel_dp, intel_connector, name);
2539
89667383
JB		 2540 /* Cache some DPCD data in the eDP case */
2541 if (is_edp(intel_dp)) {
59f3e272 2542 bool ret;
f01eca2e
KP		 2543 struct edp_power_seq cur, vbt;
2544 u32 pp_on, pp_off, pp_div;
d6f24d0f 2545 struct edid *edid;
5d613501
JB		 2546
2547 pp_on = I915_READ(PCH_PP_ON_DELAYS);
f01eca2e 2548 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
5d613501 2549 pp_div = I915_READ(PCH_PP_DIVISOR);
89667383 2550
bfa3384a
JB		 2551 if (!pp_on || !pp_off || !pp_div) {
2552 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2553 intel_dp_encoder_destroy(&intel_dp->base.base);
2554 intel_dp_destroy(&intel_connector->base);
2555 return;
2556 }
2557
f01eca2e
KP		 2558 /* Pull timing values out of registers */
2559 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2560 PANEL_POWER_UP_DELAY_SHIFT;
2561
2562 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2563 PANEL_LIGHT_ON_DELAY_SHIFT;
f2e8b18a 2564
f01eca2e
KP		 2565 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2566 PANEL_LIGHT_OFF_DELAY_SHIFT;
2567
2568 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2569 PANEL_POWER_DOWN_DELAY_SHIFT;
2570
2571 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2572 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2573
2574 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2575 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2576
2577 vbt = dev_priv->edp.pps;
2578
2579 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2580 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2581
2582#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2583
2584 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2585 intel_dp->backlight_on_delay = get_delay(t8);
2586 intel_dp->backlight_off_delay = get_delay(t9);
2587 intel_dp->panel_power_down_delay = get_delay(t10);
2588 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2589
2590 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2591 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2592 intel_dp->panel_power_cycle_delay);
2593
2594 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2595 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5d613501
JB		 2596
2597 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2598 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2599 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2600
59f3e272 2601 if (ret) {
7183dc29
JB		 2602 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2603 dev_priv->no_aux_handshake =
2604 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2605 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2606 } else {
3d3dc149 2607 /* if this fails, presume the device is a ghost */
48898b03 2608 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2609 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2610 intel_dp_destroy(&intel_connector->base);
3d3dc149 2611 return;
89667383 2612 }
89667383 2613
d6f24d0f
JB		 2614 ironlake_edp_panel_vdd_on(intel_dp);
2615 edid = drm_get_edid(connector, &intel_dp->adapter);
2616 if (edid) {
2617 drm_mode_connector_update_edid_property(connector,
2618 edid);
2619 intel_dp->edid_mode_count =
2620 drm_add_edid_modes(connector, edid);
2621 drm_edid_to_eld(connector, edid);
2622 intel_dp->edid = edid;
2623 }
2624 ironlake_edp_panel_vdd_off(intel_dp, false);
2625 }
552fb0b7 2626
21d40d37 2627 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2628
4d926461 2629 if (is_edp(intel_dp)) {
aaa6fd2a
MG		 2630 dev_priv->int_edp_connector = connector;
2631 intel_panel_setup_backlight(dev);
32f9d658
ZW		 2632 }
2633
f684960e
CW		 2634 intel_dp_add_properties(intel_dp, connector);
2635
a4fc5ed6
KP		 2636 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2637 * 0xd. Failure to do so will result in spurious interrupts being
2638 * generated on the port when a cable is not attached.
2639 */
2640 if (IS_G4X(dev) && !IS_GM45(dev)) {
2641 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2642 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2643 }
2644}
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