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drm/i915: Add automated testing support for Displayport compliance testing
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
9dd4ffdf
CML		 44struct dp_link_dpll {
45 int link_bw;
46 struct dpll dpll;
47};
48
49static const struct dp_link_dpll gen4_dpll[] = {
50 { DP_LINK_BW_1_62,
51 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
52 { DP_LINK_BW_2_7,
53 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
54};
55
56static const struct dp_link_dpll pch_dpll[] = {
57 { DP_LINK_BW_1_62,
58 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
59 { DP_LINK_BW_2_7,
60 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
61};
62
65ce4bf5
CML		 63static const struct dp_link_dpll vlv_dpll[] = {
64 { DP_LINK_BW_1_62,
58f6e632 65 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 66 { DP_LINK_BW_2_7,
67 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
68};
69
ef9348c8
CML		 70/*
71 * CHV supports eDP 1.4 that have more link rates.
72 * Below only provides the fixed rate but exclude variable rate.
73 */
74static const struct dp_link_dpll chv_dpll[] = {
75 /*
76 * CHV requires to program fractional division for m2.
77 * m2 is stored in fixed point format using formula below
78 * (m2_int << 22) | m2_fraction
79 */
80 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
81 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
82 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
83 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
84 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
85 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
86};
a8f3ef61 87/* Skylake supports following rates */
f4896f15
VS		 88static const int gen9_rates[] = { 162000, 216000, 270000,
89 324000, 432000, 540000 };
fe51bfb9
VS		 90static const int chv_rates[] = { 162000, 202500, 210000, 216000,
91 243000, 270000, 324000, 405000,
92 420000, 432000, 540000 };
f4896f15 93static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 94
cfcb0fc9
JB		 95/**
96 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
97 * @intel_dp: DP struct
98 *
99 * If a CPU or PCH DP output is attached to an eDP panel, this function
100 * will return true, and false otherwise.
101 */
102static bool is_edp(struct intel_dp *intel_dp)
103{
da63a9f2
PZ		 104 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
105
106 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 107}
108
68b4d824 109static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 110{
68b4d824
ID		 111 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
112
113 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 114}
115
df0e9248
CW		 116static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
117{
fa90ecef 118 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 119}
120
ea5b213a 121static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 122static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 123static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 124static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 125static void vlv_steal_power_sequencer(struct drm_device *dev,
126 enum pipe pipe);
a4fc5ed6 127
ed4e9c1d
VS		 128static int
129intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 130{
7183dc29 131 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 132
133 switch (max_link_bw) {
134 case DP_LINK_BW_1_62:
135 case DP_LINK_BW_2_7:
1db10e28 136 case DP_LINK_BW_5_4:
d4eead50 137 break;
a4fc5ed6 138 default:
d4eead50
ID		 139 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
140 max_link_bw);
a4fc5ed6
KP		 141 max_link_bw = DP_LINK_BW_1_62;
142 break;
143 }
144 return max_link_bw;
145}
146
eeb6324d
PZ		 147static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
148{
149 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
150 struct drm_device *dev = intel_dig_port->base.base.dev;
151 u8 source_max, sink_max;
152
153 source_max = 4;
154 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
155 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
156 source_max = 2;
157
158 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
159
160 return min(source_max, sink_max);
161}
162
cd9dde44
AJ		 163/*
164 * The units on the numbers in the next two are... bizarre. Examples will
165 * make it clearer; this one parallels an example in the eDP spec.
166 *
167 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
168 *
169 * 270000 * 1 * 8 / 10 == 216000
170 *
171 * The actual data capacity of that configuration is 2.16Gbit/s, so the
172 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
173 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
174 * 119000. At 18bpp that's 2142000 kilobits per second.
175 *
176 * Thus the strange-looking division by 10 in intel_dp_link_required, to
177 * get the result in decakilobits instead of kilobits.
178 */
179
a4fc5ed6 180static int
c898261c 181intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 182{
cd9dde44 183 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 184}
185
fe27d53e
DA		 186static int
187intel_dp_max_data_rate(int max_link_clock, int max_lanes)
188{
189 return (max_link_clock * max_lanes * 8) / 10;
190}
191
c19de8eb 192static enum drm_mode_status
a4fc5ed6
KP		 193intel_dp_mode_valid(struct drm_connector *connector,
194 struct drm_display_mode *mode)
195{
df0e9248 196 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 197 struct intel_connector *intel_connector = to_intel_connector(connector);
198 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 199 int target_clock = mode->clock;
200 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 201
dd06f90e
JN		 202 if (is_edp(intel_dp) && fixed_mode) {
203 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 204 return MODE_PANEL;
205
dd06f90e 206 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 207 return MODE_PANEL;
03afc4a2
DV		 208
209 target_clock = fixed_mode->clock;
7de56f43
ZY		 210 }
211
50fec21a 212 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 213 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 214
215 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
216 mode_rate = intel_dp_link_required(target_clock, 18);
217
218 if (mode_rate > max_rate)
c4867936 219 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 220
221 if (mode->clock < 10000)
222 return MODE_CLOCK_LOW;
223
0af78a2b
DV		 224 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
225 return MODE_H_ILLEGAL;
226
a4fc5ed6
KP		 227 return MODE_OK;
228}
229
a4f1289e 230uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 231{
232 int i;
233 uint32_t v = 0;
234
235 if (src_bytes > 4)
236 src_bytes = 4;
237 for (i = 0; i < src_bytes; i++)
238 v |= ((uint32_t) src[i]) << ((3-i) * 8);
239 return v;
240}
241
c2af70e2 242static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 243{
244 int i;
245 if (dst_bytes > 4)
246 dst_bytes = 4;
247 for (i = 0; i < dst_bytes; i++)
248 dst[i] = src >> ((3-i) * 8);
249}
250
fb0f8fbf
KP		 251/* hrawclock is 1/4 the FSB frequency */
252static int
253intel_hrawclk(struct drm_device *dev)
254{
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 uint32_t clkcfg;
257
9473c8f4
VP		 258 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
259 if (IS_VALLEYVIEW(dev))
260 return 200;
261
fb0f8fbf
KP		 262 clkcfg = I915_READ(CLKCFG);
263 switch (clkcfg & CLKCFG_FSB_MASK) {
264 case CLKCFG_FSB_400:
265 return 100;
266 case CLKCFG_FSB_533:
267 return 133;
268 case CLKCFG_FSB_667:
269 return 166;
270 case CLKCFG_FSB_800:
271 return 200;
272 case CLKCFG_FSB_1067:
273 return 266;
274 case CLKCFG_FSB_1333:
275 return 333;
276 /* these two are just a guess; one of them might be right */
277 case CLKCFG_FSB_1600:
278 case CLKCFG_FSB_1600_ALT:
279 return 400;
280 default:
281 return 133;
282 }
283}
284
bf13e81b
JN		 285static void
286intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 287 struct intel_dp *intel_dp);
bf13e81b
JN		 288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 290 struct intel_dp *intel_dp);
bf13e81b 291
773538e8
VS		 292static void pps_lock(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct intel_encoder *encoder = &intel_dig_port->base;
296 struct drm_device *dev = encoder->base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum intel_display_power_domain power_domain;
299
300 /*
301 * See vlv_power_sequencer_reset() why we need
302 * a power domain reference here.
303 */
304 power_domain = intel_display_port_power_domain(encoder);
305 intel_display_power_get(dev_priv, power_domain);
306
307 mutex_lock(&dev_priv->pps_mutex);
308}
309
310static void pps_unlock(struct intel_dp *intel_dp)
311{
312 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
313 struct intel_encoder *encoder = &intel_dig_port->base;
314 struct drm_device *dev = encoder->base.dev;
315 struct drm_i915_private *dev_priv = dev->dev_private;
316 enum intel_display_power_domain power_domain;
317
318 mutex_unlock(&dev_priv->pps_mutex);
319
320 power_domain = intel_display_port_power_domain(encoder);
321 intel_display_power_put(dev_priv, power_domain);
322}
323
961a0db0
VS		 324static void
325vlv_power_sequencer_kick(struct intel_dp *intel_dp)
326{
327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
328 struct drm_device *dev = intel_dig_port->base.base.dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330 enum pipe pipe = intel_dp->pps_pipe;
d288f65f 331 bool pll_enabled;
961a0db0
VS		 332 uint32_t DP;
333
334 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
335 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
336 pipe_name(pipe), port_name(intel_dig_port->port)))
337 return;
338
339 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
340 pipe_name(pipe), port_name(intel_dig_port->port));
341
342 /* Preserve the BIOS-computed detected bit. This is
343 * supposed to be read-only.
344 */
345 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
346 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
347 DP |= DP_PORT_WIDTH(1);
348 DP |= DP_LINK_TRAIN_PAT_1;
349
350 if (IS_CHERRYVIEW(dev))
351 DP |= DP_PIPE_SELECT_CHV(pipe);
352 else if (pipe == PIPE_B)
353 DP |= DP_PIPEB_SELECT;
354
d288f65f
VS		 355 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
356
357 /*
358 * The DPLL for the pipe must be enabled for this to work.
359 * So enable temporarily it if it's not already enabled.
360 */
361 if (!pll_enabled)
362 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
363 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
364
961a0db0
VS		 365 /*
366 * Similar magic as in intel_dp_enable_port().
367 * We _must_ do this port enable + disable trick
368 * to make this power seqeuencer lock onto the port.
369 * Otherwise even VDD force bit won't work.
370 */
371 I915_WRITE(intel_dp->output_reg, DP);
372 POSTING_READ(intel_dp->output_reg);
373
374 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
375 POSTING_READ(intel_dp->output_reg);
376
377 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
378 POSTING_READ(intel_dp->output_reg);
d288f65f
VS		 379
380 if (!pll_enabled)
381 vlv_force_pll_off(dev, pipe);
961a0db0
VS		 382}
383
bf13e81b
JN		 384static enum pipe
385vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
386{
387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 388 struct drm_device *dev = intel_dig_port->base.base.dev;
389 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 390 struct intel_encoder *encoder;
391 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 392 enum pipe pipe;
bf13e81b 393
e39b999a 394 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 395
a8c3344e
VS		 396 /* We should never land here with regular DP ports */
397 WARN_ON(!is_edp(intel_dp));
398
a4a5d2f8
VS		 399 if (intel_dp->pps_pipe != INVALID_PIPE)
400 return intel_dp->pps_pipe;
401
402 /*
403 * We don't have power sequencer currently.
404 * Pick one that's not used by other ports.
405 */
406 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
407 base.head) {
408 struct intel_dp *tmp;
409
410 if (encoder->type != INTEL_OUTPUT_EDP)
411 continue;
412
413 tmp = enc_to_intel_dp(&encoder->base);
414
415 if (tmp->pps_pipe != INVALID_PIPE)
416 pipes &= ~(1 << tmp->pps_pipe);
417 }
418
419 /*
420 * Didn't find one. This should not happen since there
421 * are two power sequencers and up to two eDP ports.
422 */
423 if (WARN_ON(pipes == 0))
a8c3344e
VS		 424 pipe = PIPE_A;
425 else
426 pipe = ffs(pipes) - 1;
a4a5d2f8 427
a8c3344e
VS		 428 vlv_steal_power_sequencer(dev, pipe);
429 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 430
431 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
432 pipe_name(intel_dp->pps_pipe),
433 port_name(intel_dig_port->port));
434
435 /* init power sequencer on this pipe and port */
36b5f425
VS		 436 intel_dp_init_panel_power_sequencer(dev, intel_dp);
437 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 438
961a0db0
VS		 439 /*
440 * Even vdd force doesn't work until we've made
441 * the power sequencer lock in on the port.
442 */
443 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 444
445 return intel_dp->pps_pipe;
446}
447
6491ab27
VS		 448typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
449 enum pipe pipe);
450
451static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
452 enum pipe pipe)
453{
454 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
455}
456
457static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
458 enum pipe pipe)
459{
460 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
461}
462
463static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
464 enum pipe pipe)
465{
466 return true;
467}
bf13e81b 468
a4a5d2f8 469static enum pipe
6491ab27
VS		 470vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
471 enum port port,
472 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 473{
474 enum pipe pipe;
bf13e81b 475
bf13e81b
JN		 476 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
477 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
478 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 479
480 if (port_sel != PANEL_PORT_SELECT_VLV(port))
481 continue;
482
6491ab27
VS		 483 if (!pipe_check(dev_priv, pipe))
484 continue;
485
a4a5d2f8 486 return pipe;
bf13e81b
JN		 487 }
488
a4a5d2f8
VS		 489 return INVALID_PIPE;
490}
491
492static void
493vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
494{
495 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
496 struct drm_device *dev = intel_dig_port->base.base.dev;
497 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 498 enum port port = intel_dig_port->port;
499
500 lockdep_assert_held(&dev_priv->pps_mutex);
501
502 /* try to find a pipe with this port selected */
6491ab27
VS		 503 /* first pick one where the panel is on */
504 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
505 vlv_pipe_has_pp_on);
506 /* didn't find one? pick one where vdd is on */
507 if (intel_dp->pps_pipe == INVALID_PIPE)
508 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
509 vlv_pipe_has_vdd_on);
510 /* didn't find one? pick one with just the correct port */
511 if (intel_dp->pps_pipe == INVALID_PIPE)
512 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
513 vlv_pipe_any);
a4a5d2f8
VS		 514
515 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
516 if (intel_dp->pps_pipe == INVALID_PIPE) {
517 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
518 port_name(port));
519 return;
bf13e81b
JN		 520 }
521
a4a5d2f8
VS		 522 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
523 port_name(port), pipe_name(intel_dp->pps_pipe));
524
36b5f425
VS		 525 intel_dp_init_panel_power_sequencer(dev, intel_dp);
526 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 527}
528
773538e8
VS		 529void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
530{
531 struct drm_device *dev = dev_priv->dev;
532 struct intel_encoder *encoder;
533
534 if (WARN_ON(!IS_VALLEYVIEW(dev)))
535 return;
536
537 /*
538 * We can't grab pps_mutex here due to deadlock with power_domain
539 * mutex when power_domain functions are called while holding pps_mutex.
540 * That also means that in order to use pps_pipe the code needs to
541 * hold both a power domain reference and pps_mutex, and the power domain
542 * reference get/put must be done while _not_ holding pps_mutex.
543 * pps_{lock,unlock}() do these steps in the correct order, so one
544 * should use them always.
545 */
546
547 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
548 struct intel_dp *intel_dp;
549
550 if (encoder->type != INTEL_OUTPUT_EDP)
551 continue;
552
553 intel_dp = enc_to_intel_dp(&encoder->base);
554 intel_dp->pps_pipe = INVALID_PIPE;
555 }
bf13e81b
JN		 556}
557
558static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
559{
560 struct drm_device *dev = intel_dp_to_dev(intel_dp);
561
562 if (HAS_PCH_SPLIT(dev))
563 return PCH_PP_CONTROL;
564 else
565 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
566}
567
568static u32 _pp_stat_reg(struct intel_dp *intel_dp)
569{
570 struct drm_device *dev = intel_dp_to_dev(intel_dp);
571
572 if (HAS_PCH_SPLIT(dev))
573 return PCH_PP_STATUS;
574 else
575 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
576}
577
01527b31
CT		 578/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
579 This function only applicable when panel PM state is not to be tracked */
580static int edp_notify_handler(struct notifier_block *this, unsigned long code,
581 void *unused)
582{
583 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
584 edp_notifier);
585 struct drm_device *dev = intel_dp_to_dev(intel_dp);
586 struct drm_i915_private *dev_priv = dev->dev_private;
587 u32 pp_div;
588 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 589
590 if (!is_edp(intel_dp) || code != SYS_RESTART)
591 return 0;
592
773538e8 593 pps_lock(intel_dp);
e39b999a 594
01527b31 595 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 596 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
597
01527b31
CT		 598 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
599 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
600 pp_div = I915_READ(pp_div_reg);
601 pp_div &= PP_REFERENCE_DIVIDER_MASK;
602
603 /* 0x1F write to PP_DIV_REG sets max cycle delay */
604 I915_WRITE(pp_div_reg, pp_div | 0x1F);
605 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
606 msleep(intel_dp->panel_power_cycle_delay);
607 }
608
773538e8 609 pps_unlock(intel_dp);
e39b999a 610
01527b31
CT		 611 return 0;
612}
613
4be73780 614static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 615{
30add22d 616 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 617 struct drm_i915_private *dev_priv = dev->dev_private;
618
e39b999a
VS		 619 lockdep_assert_held(&dev_priv->pps_mutex);
620
9a42356b
VS		 621 if (IS_VALLEYVIEW(dev) &&
622 intel_dp->pps_pipe == INVALID_PIPE)
623 return false;
624
bf13e81b 625 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 626}
627
4be73780 628static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 629{
30add22d 630 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 631 struct drm_i915_private *dev_priv = dev->dev_private;
632
e39b999a
VS		 633 lockdep_assert_held(&dev_priv->pps_mutex);
634
9a42356b
VS		 635 if (IS_VALLEYVIEW(dev) &&
636 intel_dp->pps_pipe == INVALID_PIPE)
637 return false;
638
773538e8 639 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 640}
641
9b984dae
KP		 642static void
643intel_dp_check_edp(struct intel_dp *intel_dp)
644{
30add22d 645 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 646 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 647
9b984dae
KP		 648 if (!is_edp(intel_dp))
649 return;
453c5420 650
4be73780 651 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 652 WARN(1, "eDP powered off while attempting aux channel communication.\n");
653 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 654 I915_READ(_pp_stat_reg(intel_dp)),
655 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 656 }
657}
658
9ee32fea
DV		 659static uint32_t
660intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
661{
662 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
663 struct drm_device *dev = intel_dig_port->base.base.dev;
664 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 665 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 666 uint32_t status;
667 bool done;
668
ef04f00d 669#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 670 if (has_aux_irq)
b18ac466 671 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 672 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 673 else
674 done = wait_for_atomic(C, 10) == 0;
675 if (!done)
676 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
677 has_aux_irq);
678#undef C
679
680 return status;
681}
682
ec5b01dd 683static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 684{
174edf1f
PZ		 685 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
686 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 687
ec5b01dd
DL		 688 /*
689 * The clock divider is based off the hrawclk, and would like to run at
690 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 691 */
ec5b01dd
DL		 692 return index ? 0 : intel_hrawclk(dev) / 2;
693}
694
695static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
696{
697 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
698 struct drm_device *dev = intel_dig_port->base.base.dev;
469d4b2a 699 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd
DL		 700
701 if (index)
702 return 0;
703
704 if (intel_dig_port->port == PORT_A) {
469d4b2a 705 return DIV_ROUND_UP(dev_priv->display.get_display_clock_speed(dev), 2000);
ec5b01dd
DL		 706 } else {
707 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
708 }
709}
710
711static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
712{
713 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
714 struct drm_device *dev = intel_dig_port->base.base.dev;
715 struct drm_i915_private *dev_priv = dev->dev_private;
716
717 if (intel_dig_port->port == PORT_A) {
718 if (index)
719 return 0;
1652d19e 720 return DIV_ROUND_CLOSEST(dev_priv->display.get_display_clock_speed(dev), 2000);
2c55c336
JN		 721 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
722 /* Workaround for non-ULT HSW */
bc86625a
CW		 723 switch (index) {
724 case 0: return 63;
725 case 1: return 72;
726 default: return 0;
727 }
ec5b01dd 728 } else {
bc86625a 729 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 730 }
b84a1cf8
RV		 731}
732
ec5b01dd
DL		 733static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
734{
735 return index ? 0 : 100;
736}
737
b6b5e383
DL		 738static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
739{
740 /*
741 * SKL doesn't need us to program the AUX clock divider (Hardware will
742 * derive the clock from CDCLK automatically). We still implement the
743 * get_aux_clock_divider vfunc to plug-in into the existing code.
744 */
745 return index ? 0 : 1;
746}
747
5ed12a19
DL		 748static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
749 bool has_aux_irq,
750 int send_bytes,
751 uint32_t aux_clock_divider)
752{
753 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
754 struct drm_device *dev = intel_dig_port->base.base.dev;
755 uint32_t precharge, timeout;
756
757 if (IS_GEN6(dev))
758 precharge = 3;
759 else
760 precharge = 5;
761
762 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
763 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
764 else
765 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
766
767 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 768 DP_AUX_CH_CTL_DONE |
5ed12a19 769 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 770 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 771 timeout |
788d4433 772 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 773 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
774 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 775 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 776}
777
b9ca5fad
DL		 778static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
779 bool has_aux_irq,
780 int send_bytes,
781 uint32_t unused)
782{
783 return DP_AUX_CH_CTL_SEND_BUSY |
784 DP_AUX_CH_CTL_DONE |
785 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
786 DP_AUX_CH_CTL_TIME_OUT_ERROR |
787 DP_AUX_CH_CTL_TIME_OUT_1600us |
788 DP_AUX_CH_CTL_RECEIVE_ERROR |
789 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
790 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
791}
792
b84a1cf8
RV		 793static int
794intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 795 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 796 uint8_t *recv, int recv_size)
797{
798 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
799 struct drm_device *dev = intel_dig_port->base.base.dev;
800 struct drm_i915_private *dev_priv = dev->dev_private;
801 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
802 uint32_t ch_data = ch_ctl + 4;
bc86625a 803 uint32_t aux_clock_divider;
b84a1cf8
RV		 804 int i, ret, recv_bytes;
805 uint32_t status;
5ed12a19 806 int try, clock = 0;
4e6b788c 807 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 808 bool vdd;
809
773538e8 810 pps_lock(intel_dp);
e39b999a 811
72c3500a
VS		 812 /*
813 * We will be called with VDD already enabled for dpcd/edid/oui reads.
814 * In such cases we want to leave VDD enabled and it's up to upper layers
815 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
816 * ourselves.
817 */
1e0560e0 818 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 819
820 /* dp aux is extremely sensitive to irq latency, hence request the
821 * lowest possible wakeup latency and so prevent the cpu from going into
822 * deep sleep states.
823 */
824 pm_qos_update_request(&dev_priv->pm_qos, 0);
825
826 intel_dp_check_edp(intel_dp);
5eb08b69 827
c67a470b
PZ		 828 intel_aux_display_runtime_get(dev_priv);
829
11bee43e
JB		 830 /* Try to wait for any previous AUX channel activity */
831 for (try = 0; try < 3; try++) {
ef04f00d 832 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 833 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
834 break;
835 msleep(1);
836 }
837
838 if (try == 3) {
839 WARN(1, "dp_aux_ch not started status 0x%08x\n",
840 I915_READ(ch_ctl));
9ee32fea
DV		 841 ret = -EBUSY;
842 goto out;
4f7f7b7e
CW		 843 }
844
46a5ae9f
PZ		 845 /* Only 5 data registers! */
846 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
847 ret = -E2BIG;
848 goto out;
849 }
850
ec5b01dd 851 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 852 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
853 has_aux_irq,
854 send_bytes,
855 aux_clock_divider);
5ed12a19 856
bc86625a
CW		 857 /* Must try at least 3 times according to DP spec */
858 for (try = 0; try < 5; try++) {
859 /* Load the send data into the aux channel data registers */
860 for (i = 0; i < send_bytes; i += 4)
861 I915_WRITE(ch_data + i,
a4f1289e
RV		 862 intel_dp_pack_aux(send + i,
863 send_bytes - i));
bc86625a
CW		 864
865 /* Send the command and wait for it to complete */
5ed12a19 866 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 867
868 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
869
870 /* Clear done status and any errors */
871 I915_WRITE(ch_ctl,
872 status |
873 DP_AUX_CH_CTL_DONE |
874 DP_AUX_CH_CTL_TIME_OUT_ERROR |
875 DP_AUX_CH_CTL_RECEIVE_ERROR);
876
877 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
878 DP_AUX_CH_CTL_RECEIVE_ERROR))
879 continue;
880 if (status & DP_AUX_CH_CTL_DONE)
881 break;
882 }
4f7f7b7e 883 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 884 break;
885 }
886
a4fc5ed6 887 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 888 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 889 ret = -EBUSY;
890 goto out;
a4fc5ed6
KP		 891 }
892
893 /* Check for timeout or receive error.
894 * Timeouts occur when the sink is not connected
895 */
a5b3da54 896 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 897 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 898 ret = -EIO;
899 goto out;
a5b3da54 900 }
1ae8c0a5
KP		 901
902 /* Timeouts occur when the device isn't connected, so they're
903 * "normal" -- don't fill the kernel log with these */
a5b3da54 904 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 905 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 906 ret = -ETIMEDOUT;
907 goto out;
a4fc5ed6
KP		 908 }
909
910 /* Unload any bytes sent back from the other side */
911 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
912 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 913 if (recv_bytes > recv_size)
914 recv_bytes = recv_size;
0206e353 915
4f7f7b7e 916 for (i = 0; i < recv_bytes; i += 4)
a4f1289e
RV		 917 intel_dp_unpack_aux(I915_READ(ch_data + i),
918 recv + i, recv_bytes - i);
a4fc5ed6 919
9ee32fea
DV		 920 ret = recv_bytes;
921out:
922 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 923 intel_aux_display_runtime_put(dev_priv);
9ee32fea 924
884f19e9
JN		 925 if (vdd)
926 edp_panel_vdd_off(intel_dp, false);
927
773538e8 928 pps_unlock(intel_dp);
e39b999a 929
9ee32fea 930 return ret;
a4fc5ed6
KP		 931}
932
a6c8aff0
JN		 933#define BARE_ADDRESS_SIZE 3
934#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 935static ssize_t
936intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 937{
9d1a1031
JN		 938 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
939 uint8_t txbuf[20], rxbuf[20];
940 size_t txsize, rxsize;
a4fc5ed6 941 int ret;
a4fc5ed6 942
d2d9cbbd
VS		 943 txbuf[0] = (msg->request << 4) |
944 ((msg->address >> 16) & 0xf);
945 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 946 txbuf[2] = msg->address & 0xff;
947 txbuf[3] = msg->size - 1;
46a5ae9f 948
9d1a1031
JN		 949 switch (msg->request & ~DP_AUX_I2C_MOT) {
950 case DP_AUX_NATIVE_WRITE:
951 case DP_AUX_I2C_WRITE:
a6c8aff0 952 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 953 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 954
9d1a1031
JN		 955 if (WARN_ON(txsize > 20))
956 return -E2BIG;
a4fc5ed6 957
9d1a1031 958 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 959
9d1a1031
JN		 960 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
961 if (ret > 0) {
962 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 963
a1ddefd8
JN		 964 if (ret > 1) {
965 /* Number of bytes written in a short write. */
966 ret = clamp_t(int, rxbuf[1], 0, msg->size);
967 } else {
968 /* Return payload size. */
969 ret = msg->size;
970 }
9d1a1031
JN		 971 }
972 break;
46a5ae9f 973
9d1a1031
JN		 974 case DP_AUX_NATIVE_READ:
975 case DP_AUX_I2C_READ:
a6c8aff0 976 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 977 rxsize = msg->size + 1;
a4fc5ed6 978
9d1a1031
JN		 979 if (WARN_ON(rxsize > 20))
980 return -E2BIG;
a4fc5ed6 981
9d1a1031
JN		 982 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
983 if (ret > 0) {
984 msg->reply = rxbuf[0] >> 4;
985 /*
986 * Assume happy day, and copy the data. The caller is
987 * expected to check msg->reply before touching it.
988 *
989 * Return payload size.
990 */
991 ret--;
992 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 993 }
9d1a1031
JN		 994 break;
995
996 default:
997 ret = -EINVAL;
998 break;
a4fc5ed6 999 }
f51a44b9 1000
9d1a1031 1001 return ret;
a4fc5ed6
KP		 1002}
1003
9d1a1031
JN		 1004static void
1005intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1006{
1007 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 1008 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1009 enum port port = intel_dig_port->port;
0b99836f 1010 const char *name = NULL;
ab2c0672
DA		 1011 int ret;
1012
33ad6626
JN		 1013 switch (port) {
1014 case PORT_A:
1015 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 1016 name = "DPDDC-A";
ab2c0672 1017 break;
33ad6626
JN		 1018 case PORT_B:
1019 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1020 name = "DPDDC-B";
ab2c0672 1021 break;
33ad6626
JN		 1022 case PORT_C:
1023 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1024 name = "DPDDC-C";
ab2c0672 1025 break;
33ad6626
JN		 1026 case PORT_D:
1027 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1028 name = "DPDDC-D";
33ad6626
JN		 1029 break;
1030 default:
1031 BUG();
ab2c0672
DA		 1032 }
1033
1b1aad75
DL		 1034 /*
1035 * The AUX_CTL register is usually DP_CTL + 0x10.
1036 *
1037 * On Haswell and Broadwell though:
1038 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1039 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1040 *
1041 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1042 */
1043 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1044 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1045
0b99836f 1046 intel_dp->aux.name = name;
9d1a1031
JN		 1047 intel_dp->aux.dev = dev->dev;
1048 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1049
0b99836f
JN		 1050 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1051 connector->base.kdev->kobj.name);
8316f337 1052
4f71d0cb 1053 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1054 if (ret < 0) {
4f71d0cb 1055 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1056 name, ret);
1057 return;
ab2c0672 1058 }
8a5e6aeb 1059
0b99836f
JN		 1060 ret = sysfs_create_link(&connector->base.kdev->kobj,
1061 &intel_dp->aux.ddc.dev.kobj,
1062 intel_dp->aux.ddc.dev.kobj.name);
1063 if (ret < 0) {
1064 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1065 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1066 }
a4fc5ed6
KP		 1067}
1068
80f65de3
ID		 1069static void
1070intel_dp_connector_unregister(struct intel_connector *intel_connector)
1071{
1072 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1073
0e32b39c
DA		 1074 if (!intel_connector->mst_port)
1075 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1076 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1077 intel_connector_unregister(intel_connector);
1078}
1079
5416d871 1080static void
c3346ef6 1081skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
5416d871
DL		 1082{
1083 u32 ctrl1;
1084
1085 pipe_config->ddi_pll_sel = SKL_DPLL0;
1086 pipe_config->dpll_hw_state.cfgcr1 = 0;
1087 pipe_config->dpll_hw_state.cfgcr2 = 0;
1088
1089 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
c3346ef6
SJ		 1090 switch (link_clock / 2) {
1091 case 81000:
5416d871
DL		 1092 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
1093 SKL_DPLL0);
1094 break;
c3346ef6 1095 case 135000:
5416d871
DL		 1096 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
1097 SKL_DPLL0);
1098 break;
c3346ef6 1099 case 270000:
5416d871
DL		 1100 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
1101 SKL_DPLL0);
1102 break;
c3346ef6
SJ		 1103 case 162000:
1104 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1620,
1105 SKL_DPLL0);
1106 break;
1107 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1108 results in CDCLK change. Need to handle the change of CDCLK by
1109 disabling pipes and re-enabling them */
1110 case 108000:
1111 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1080,
1112 SKL_DPLL0);
1113 break;
1114 case 216000:
1115 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2160,
1116 SKL_DPLL0);
1117 break;
1118
5416d871
DL		 1119 }
1120 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1121}
1122
0e50338c 1123static void
5cec258b 1124hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
0e50338c
DV		 1125{
1126 switch (link_bw) {
1127 case DP_LINK_BW_1_62:
1128 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1129 break;
1130 case DP_LINK_BW_2_7:
1131 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1132 break;
1133 case DP_LINK_BW_5_4:
1134 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1135 break;
1136 }
1137}
1138
fc0f8e25 1139static int
12f6a2e2 1140intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1141{
94ca719e
VS		 1142 if (intel_dp->num_sink_rates) {
1143 *sink_rates = intel_dp->sink_rates;
1144 return intel_dp->num_sink_rates;
fc0f8e25 1145 }
12f6a2e2
VS		 1146
1147 *sink_rates = default_rates;
1148
1149 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1150}
1151
a8f3ef61 1152static int
1db10e28 1153intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
a8f3ef61 1154{
636280ba
VS		 1155 if (INTEL_INFO(dev)->gen >= 9) {
1156 *source_rates = gen9_rates;
1157 return ARRAY_SIZE(gen9_rates);
fe51bfb9
VS		 1158 } else if (IS_CHERRYVIEW(dev)) {
1159 *source_rates = chv_rates;
1160 return ARRAY_SIZE(chv_rates);
a8f3ef61 1161 }
636280ba
VS		 1162
1163 *source_rates = default_rates;
1164
1db10e28
VS		 1165 if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
1166 /* WaDisableHBR2:skl */
1167 return (DP_LINK_BW_2_7 >> 3) + 1;
1168 else if (INTEL_INFO(dev)->gen >= 8 ||
1169 (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
1170 return (DP_LINK_BW_5_4 >> 3) + 1;
1171 else
1172 return (DP_LINK_BW_2_7 >> 3) + 1;
a8f3ef61
SJ		 1173}
1174
c6bb3538
DV		 1175static void
1176intel_dp_set_clock(struct intel_encoder *encoder,
5cec258b 1177 struct intel_crtc_state *pipe_config, int link_bw)
c6bb3538
DV		 1178{
1179 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1180 const struct dp_link_dpll *divisor = NULL;
1181 int i, count = 0;
c6bb3538
DV		 1182
1183 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1184 divisor = gen4_dpll;
1185 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1186 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1187 divisor = pch_dpll;
1188 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1189 } else if (IS_CHERRYVIEW(dev)) {
1190 divisor = chv_dpll;
1191 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1192 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1193 divisor = vlv_dpll;
1194 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1195 }
9dd4ffdf
CML		 1196
1197 if (divisor && count) {
1198 for (i = 0; i < count; i++) {
1199 if (link_bw == divisor[i].link_bw) {
1200 pipe_config->dpll = divisor[i].dpll;
1201 pipe_config->clock_set = true;
1202 break;
1203 }
1204 }
c6bb3538
DV		 1205 }
1206}
1207
2ecae76a
VS		 1208static int intersect_rates(const int *source_rates, int source_len,
1209 const int *sink_rates, int sink_len,
94ca719e 1210 int *common_rates)
a8f3ef61
SJ		 1211{
1212 int i = 0, j = 0, k = 0;
1213
a8f3ef61
SJ		 1214 while (i < source_len && j < sink_len) {
1215 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1216 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1217 return k;
94ca719e 1218 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1219 ++k;
1220 ++i;
1221 ++j;
1222 } else if (source_rates[i] < sink_rates[j]) {
1223 ++i;
1224 } else {
1225 ++j;
1226 }
1227 }
1228 return k;
1229}
1230
94ca719e
VS		 1231static int intel_dp_common_rates(struct intel_dp *intel_dp,
1232 int *common_rates)
2ecae76a
VS		 1233{
1234 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1235 const int *source_rates, *sink_rates;
1236 int source_len, sink_len;
1237
1238 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1239 source_len = intel_dp_source_rates(dev, &source_rates);
1240
1241 return intersect_rates(source_rates, source_len,
1242 sink_rates, sink_len,
94ca719e 1243 common_rates);
2ecae76a
VS		 1244}
1245
0336400e
VS		 1246static void snprintf_int_array(char *str, size_t len,
1247 const int *array, int nelem)
1248{
1249 int i;
1250
1251 str[0] = '\0';
1252
1253 for (i = 0; i < nelem; i++) {
1254 int r = snprintf(str, len, "%d,", array[i]);
1255 if (r >= len)
1256 return;
1257 str += r;
1258 len -= r;
1259 }
1260}
1261
1262static void intel_dp_print_rates(struct intel_dp *intel_dp)
1263{
1264 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1265 const int *source_rates, *sink_rates;
94ca719e
VS		 1266 int source_len, sink_len, common_len;
1267 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1268 char str[128]; /* FIXME: too big for stack? */
1269
1270 if ((drm_debug & DRM_UT_KMS) == 0)
1271 return;
1272
1273 source_len = intel_dp_source_rates(dev, &source_rates);
1274 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1275 DRM_DEBUG_KMS("source rates: %s\n", str);
1276
1277 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1278 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1279 DRM_DEBUG_KMS("sink rates: %s\n", str);
1280
94ca719e
VS		 1281 common_len = intel_dp_common_rates(intel_dp, common_rates);
1282 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1283 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1284}
1285
f4896f15 1286static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1287{
1288 int i = 0;
1289
1290 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1291 if (find == rates[i])
1292 break;
1293
1294 return i;
1295}
1296
50fec21a
VS		 1297int
1298intel_dp_max_link_rate(struct intel_dp *intel_dp)
1299{
1300 int rates[DP_MAX_SUPPORTED_RATES] = {};
1301 int len;
1302
94ca719e 1303 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1304 if (WARN_ON(len <= 0))
1305 return 162000;
1306
1307 return rates[rate_to_index(0, rates) - 1];
1308}
1309
ed4e9c1d
VS		 1310int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1311{
94ca719e 1312 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1313}
1314
00c09d70 1315bool
5bfe2ac0 1316intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1317 struct intel_crtc_state *pipe_config)
a4fc5ed6 1318{
5bfe2ac0 1319 struct drm_device *dev = encoder->base.dev;
36008365 1320 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1321 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1322 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1323 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1324 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1325 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1326 int lane_count, clock;
56071a20 1327 int min_lane_count = 1;
eeb6324d 1328 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1329 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1330 int min_clock = 0;
a8f3ef61 1331 int max_clock;
083f9560 1332 int bpp, mode_rate;
ff9a6750 1333 int link_avail, link_clock;
94ca719e
VS		 1334 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1335 int common_len;
a8f3ef61 1336
94ca719e 1337 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1338
1339 /* No common link rates between source and sink */
94ca719e 1340 WARN_ON(common_len <= 0);
a8f3ef61 1341
94ca719e 1342 max_clock = common_len - 1;
a4fc5ed6 1343
bc7d38a4 1344 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1345 pipe_config->has_pch_encoder = true;
1346
03afc4a2 1347 pipe_config->has_dp_encoder = true;
f769cd24 1348 pipe_config->has_drrs = false;
9ed109a7 1349 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1350
dd06f90e
JN		 1351 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1352 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1353 adjusted_mode);
a1b2278e
CK		 1354
1355 if (INTEL_INFO(dev)->gen >= 9) {
1356 int ret;
1357 ret = skl_update_scaler_users(intel_crtc, pipe_config, NULL, NULL, 0);
1358 if (ret)
1359 return ret;
1360 }
1361
2dd24552
JB		 1362 if (!HAS_PCH_SPLIT(dev))
1363 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1364 intel_connector->panel.fitting_mode);
1365 else
b074cec8
JB		 1366 intel_pch_panel_fitting(intel_crtc, pipe_config,
1367 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1368 }
1369
cb1793ce 1370 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1371 return false;
1372
083f9560 1373 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1374 "max bw %d pixel clock %iKHz\n",
94ca719e 1375 max_lane_count, common_rates[max_clock],
241bfc38 1376 adjusted_mode->crtc_clock);
083f9560 1377
36008365
DV		 1378 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1379 * bpc in between. */
3e7ca985 1380 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1381 if (is_edp(intel_dp)) {
1382 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1383 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1384 dev_priv->vbt.edp_bpp);
1385 bpp = dev_priv->vbt.edp_bpp;
1386 }
1387
344c5bbc
JN		 1388 /*
1389 * Use the maximum clock and number of lanes the eDP panel
1390 * advertizes being capable of. The panels are generally
1391 * designed to support only a single clock and lane
1392 * configuration, and typically these values correspond to the
1393 * native resolution of the panel.
1394 */
1395 min_lane_count = max_lane_count;
1396 min_clock = max_clock;
7984211e 1397 }
657445fe 1398
36008365 1399 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1400 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1401 bpp);
36008365 1402
c6930992 1403 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1404 for (lane_count = min_lane_count;
1405 lane_count <= max_lane_count;
1406 lane_count <<= 1) {
1407
94ca719e 1408 link_clock = common_rates[clock];
36008365
DV		 1409 link_avail = intel_dp_max_data_rate(link_clock,
1410 lane_count);
1411
1412 if (mode_rate <= link_avail) {
1413 goto found;
1414 }
1415 }
1416 }
1417 }
c4867936 1418
36008365 1419 return false;
3685a8f3 1420
36008365 1421found:
55bc60db
VS		 1422 if (intel_dp->color_range_auto) {
1423 /*
1424 * See:
1425 * CEA-861-E - 5.1 Default Encoding Parameters
1426 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1427 */
18316c8c 1428 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1429 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1430 else
1431 intel_dp->color_range = 0;
1432 }
1433
3685a8f3 1434 if (intel_dp->color_range)
50f3b016 1435 pipe_config->limited_color_range = true;
a4fc5ed6 1436
36008365 1437 intel_dp->lane_count = lane_count;
a8f3ef61 1438
94ca719e 1439 if (intel_dp->num_sink_rates) {
bc27b7d3 1440 intel_dp->link_bw = 0;
a8f3ef61 1441 intel_dp->rate_select =
94ca719e 1442 intel_dp_rate_select(intel_dp, common_rates[clock]);
bc27b7d3
VS		 1443 } else {
1444 intel_dp->link_bw =
94ca719e 1445 drm_dp_link_rate_to_bw_code(common_rates[clock]);
bc27b7d3 1446 intel_dp->rate_select = 0;
a8f3ef61
SJ		 1447 }
1448
657445fe 1449 pipe_config->pipe_bpp = bpp;
94ca719e 1450 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1451
36008365
DV		 1452 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1453 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1454 pipe_config->port_clock, bpp);
36008365
DV		 1455 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1456 mode_rate, link_avail);
a4fc5ed6 1457
03afc4a2 1458 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1459 adjusted_mode->crtc_clock,
1460 pipe_config->port_clock,
03afc4a2 1461 &pipe_config->dp_m_n);
9d1a455b 1462
439d7ac0 1463 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1464 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1465 pipe_config->has_drrs = true;
439d7ac0
PB		 1466 intel_link_compute_m_n(bpp, lane_count,
1467 intel_connector->panel.downclock_mode->clock,
1468 pipe_config->port_clock,
1469 &pipe_config->dp_m2_n2);
1470 }
1471
5416d871 1472 if (IS_SKYLAKE(dev) && is_edp(intel_dp))
94ca719e 1473 skl_edp_set_pll_config(pipe_config, common_rates[clock]);
977bb38d
S		 1474 else if (IS_BROXTON(dev))
1475 /* handled in ddi */;
5416d871 1476 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1477 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1478 else
1479 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1480
03afc4a2 1481 return true;
a4fc5ed6
KP		 1482}
1483
7c62a164 1484static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1485{
7c62a164
DV		 1486 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1487 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1488 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490 u32 dpa_ctl;
1491
6e3c9717
ACO		 1492 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1493 crtc->config->port_clock);
ea9b6006
DV		 1494 dpa_ctl = I915_READ(DP_A);
1495 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1496
6e3c9717 1497 if (crtc->config->port_clock == 162000) {
1ce17038
DV		 1498 /* For a long time we've carried around a ILK-DevA w/a for the
1499 * 160MHz clock. If we're really unlucky, it's still required.
1500 */
1501 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1502 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1503 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1504 } else {
1505 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1506 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1507 }
1ce17038 1508
ea9b6006
DV		 1509 I915_WRITE(DP_A, dpa_ctl);
1510
1511 POSTING_READ(DP_A);
1512 udelay(500);
1513}
1514
8ac33ed3 1515static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1516{
b934223d 1517 struct drm_device *dev = encoder->base.dev;
417e822d 1518 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1519 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1520 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1521 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
6e3c9717 1522 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1523
417e822d 1524 /*
1a2eb460 1525 * There are four kinds of DP registers:
417e822d
KP		 1526 *
1527 * IBX PCH
1a2eb460
KP		 1528 * SNB CPU
1529 * IVB CPU
417e822d
KP		 1530 * CPT PCH
1531 *
1532 * IBX PCH and CPU are the same for almost everything,
1533 * except that the CPU DP PLL is configured in this
1534 * register
1535 *
1536 * CPT PCH is quite different, having many bits moved
1537 * to the TRANS_DP_CTL register instead. That
1538 * configuration happens (oddly) in ironlake_pch_enable
1539 */
9c9e7927 1540
417e822d
KP		 1541 /* Preserve the BIOS-computed detected bit. This is
1542 * supposed to be read-only.
1543 */
1544 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1545
417e822d 1546 /* Handle DP bits in common between all three register formats */
417e822d 1547 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1548 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1549
6e3c9717 1550 if (crtc->config->has_audio)
ea5b213a 1551 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
247d89f6 1552
417e822d 1553 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1554
bc7d38a4 1555 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1556 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1557 intel_dp->DP |= DP_SYNC_HS_HIGH;
1558 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1559 intel_dp->DP |= DP_SYNC_VS_HIGH;
1560 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1561
6aba5b6c 1562 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1563 intel_dp->DP |= DP_ENHANCED_FRAMING;
1564
7c62a164 1565 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1566 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1567 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1568 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1569
1570 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1571 intel_dp->DP |= DP_SYNC_HS_HIGH;
1572 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1573 intel_dp->DP |= DP_SYNC_VS_HIGH;
1574 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1575
6aba5b6c 1576 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1577 intel_dp->DP |= DP_ENHANCED_FRAMING;
1578
44f37d1f
CML		 1579 if (!IS_CHERRYVIEW(dev)) {
1580 if (crtc->pipe == 1)
1581 intel_dp->DP |= DP_PIPEB_SELECT;
1582 } else {
1583 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1584 }
417e822d
KP		 1585 } else {
1586 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1587 }
a4fc5ed6
KP		 1588}
1589
ffd6749d
PZ		 1590#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1591#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1592
1a5ef5b7
PZ		 1593#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1594#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1595
ffd6749d
PZ		 1596#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1597#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1598
4be73780 1599static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1600 u32 mask,
1601 u32 value)
bd943159 1602{
30add22d 1603 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1604 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1605 u32 pp_stat_reg, pp_ctrl_reg;
1606
e39b999a
VS		 1607 lockdep_assert_held(&dev_priv->pps_mutex);
1608
bf13e81b
JN		 1609 pp_stat_reg = _pp_stat_reg(intel_dp);
1610 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1611
99ea7127 1612 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1613 mask, value,
1614 I915_READ(pp_stat_reg),
1615 I915_READ(pp_ctrl_reg));
32ce697c 1616
453c5420 1617 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1618 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1619 I915_READ(pp_stat_reg),
1620 I915_READ(pp_ctrl_reg));
32ce697c 1621 }
54c136d4
CW		 1622
1623 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1624}
32ce697c 1625
4be73780 1626static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1627{
1628 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1629 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1630}
1631
4be73780 1632static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1633{
1634 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1635 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1636}
1637
4be73780 1638static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1639{
1640 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1641
1642 /* When we disable the VDD override bit last we have to do the manual
1643 * wait. */
1644 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1645 intel_dp->panel_power_cycle_delay);
1646
4be73780 1647 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1648}
1649
4be73780 1650static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1651{
1652 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1653 intel_dp->backlight_on_delay);
1654}
1655
4be73780 1656static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1657{
1658 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1659 intel_dp->backlight_off_delay);
1660}
99ea7127 1661
832dd3c1
KP		 1662/* Read the current pp_control value, unlocking the register if it
1663 * is locked
1664 */
1665
453c5420 1666static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1667{
453c5420
JB		 1668 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 u32 control;
832dd3c1 1671
e39b999a
VS		 1672 lockdep_assert_held(&dev_priv->pps_mutex);
1673
bf13e81b 1674 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1675 control &= ~PANEL_UNLOCK_MASK;
1676 control |= PANEL_UNLOCK_REGS;
1677 return control;
bd943159
KP		 1678}
1679
951468f3
VS		 1680/*
1681 * Must be paired with edp_panel_vdd_off().
1682 * Must hold pps_mutex around the whole on/off sequence.
1683 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1684 */
1e0560e0 1685static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1686{
30add22d 1687 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1688 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1689 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1690 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1691 enum intel_display_power_domain power_domain;
5d613501 1692 u32 pp;
453c5420 1693 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1694 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1695
e39b999a
VS		 1696 lockdep_assert_held(&dev_priv->pps_mutex);
1697
97af61f5 1698 if (!is_edp(intel_dp))
adddaaf4 1699 return false;
bd943159 1700
2c623c11 1701 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1702 intel_dp->want_panel_vdd = true;
99ea7127 1703
4be73780 1704 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1705 return need_to_disable;
b0665d57 1706
4e6e1a54
ID		 1707 power_domain = intel_display_port_power_domain(intel_encoder);
1708 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1709
3936fcf4
VS		 1710 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1711 port_name(intel_dig_port->port));
bd943159 1712
4be73780
DV		 1713 if (!edp_have_panel_power(intel_dp))
1714 wait_panel_power_cycle(intel_dp);
99ea7127 1715
453c5420 1716 pp = ironlake_get_pp_control(intel_dp);
5d613501 1717 pp |= EDP_FORCE_VDD;
ebf33b18 1718
bf13e81b
JN		 1719 pp_stat_reg = _pp_stat_reg(intel_dp);
1720 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1721
1722 I915_WRITE(pp_ctrl_reg, pp);
1723 POSTING_READ(pp_ctrl_reg);
1724 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1725 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1726 /*
1727 * If the panel wasn't on, delay before accessing aux channel
1728 */
4be73780 1729 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1730 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1731 port_name(intel_dig_port->port));
f01eca2e 1732 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1733 }
adddaaf4
JN		 1734
1735 return need_to_disable;
1736}
1737
951468f3
VS		 1738/*
1739 * Must be paired with intel_edp_panel_vdd_off() or
1740 * intel_edp_panel_off().
1741 * Nested calls to these functions are not allowed since
1742 * we drop the lock. Caller must use some higher level
1743 * locking to prevent nested calls from other threads.
1744 */
b80d6c78 1745void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1746{
c695b6b6 1747 bool vdd;
adddaaf4 1748
c695b6b6
VS		 1749 if (!is_edp(intel_dp))
1750 return;
1751
773538e8 1752 pps_lock(intel_dp);
c695b6b6 1753 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1754 pps_unlock(intel_dp);
c695b6b6 1755
e2c719b7 1756 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1757 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1758}
1759
4be73780 1760static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1761{
30add22d 1762 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1763 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1764 struct intel_digital_port *intel_dig_port =
1765 dp_to_dig_port(intel_dp);
1766 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1767 enum intel_display_power_domain power_domain;
5d613501 1768 u32 pp;
453c5420 1769 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1770
e39b999a 1771 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1772
15e899a0 1773 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1774
15e899a0 1775 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1776 return;
b0665d57 1777
3936fcf4
VS		 1778 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1779 port_name(intel_dig_port->port));
bd943159 1780
be2c9196
VS		 1781 pp = ironlake_get_pp_control(intel_dp);
1782 pp &= ~EDP_FORCE_VDD;
453c5420 1783
be2c9196
VS		 1784 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1785 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1786
be2c9196
VS		 1787 I915_WRITE(pp_ctrl_reg, pp);
1788 POSTING_READ(pp_ctrl_reg);
90791a5c 1789
be2c9196
VS		 1790 /* Make sure sequencer is idle before allowing subsequent activity */
1791 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1792 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1793
be2c9196
VS		 1794 if ((pp & POWER_TARGET_ON) == 0)
1795 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1796
be2c9196
VS		 1797 power_domain = intel_display_port_power_domain(intel_encoder);
1798 intel_display_power_put(dev_priv, power_domain);
bd943159 1799}
5d613501 1800
4be73780 1801static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1802{
1803 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1804 struct intel_dp, panel_vdd_work);
bd943159 1805
773538e8 1806 pps_lock(intel_dp);
15e899a0
VS		 1807 if (!intel_dp->want_panel_vdd)
1808 edp_panel_vdd_off_sync(intel_dp);
773538e8 1809 pps_unlock(intel_dp);
bd943159
KP		 1810}
1811
aba86890
ID		 1812static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1813{
1814 unsigned long delay;
1815
1816 /*
1817 * Queue the timer to fire a long time from now (relative to the power
1818 * down delay) to keep the panel power up across a sequence of
1819 * operations.
1820 */
1821 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1822 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1823}
1824
951468f3
VS		 1825/*
1826 * Must be paired with edp_panel_vdd_on().
1827 * Must hold pps_mutex around the whole on/off sequence.
1828 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1829 */
4be73780 1830static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1831{
e39b999a
VS		 1832 struct drm_i915_private *dev_priv =
1833 intel_dp_to_dev(intel_dp)->dev_private;
1834
1835 lockdep_assert_held(&dev_priv->pps_mutex);
1836
97af61f5
KP		 1837 if (!is_edp(intel_dp))
1838 return;
5d613501 1839
e2c719b7 1840 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1841 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1842
bd943159
KP		 1843 intel_dp->want_panel_vdd = false;
1844
aba86890 1845 if (sync)
4be73780 1846 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1847 else
1848 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1849}
1850
9f0fb5be 1851static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1852{
30add22d 1853 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1854 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1855 u32 pp;
453c5420 1856 u32 pp_ctrl_reg;
9934c132 1857
9f0fb5be
VS		 1858 lockdep_assert_held(&dev_priv->pps_mutex);
1859
97af61f5 1860 if (!is_edp(intel_dp))
bd943159 1861 return;
99ea7127 1862
3936fcf4
VS		 1863 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1864 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1865
e7a89ace
VS		 1866 if (WARN(edp_have_panel_power(intel_dp),
1867 "eDP port %c panel power already on\n",
1868 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1869 return;
9934c132 1870
4be73780 1871 wait_panel_power_cycle(intel_dp);
37c6c9b0 1872
bf13e81b 1873 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1874 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1875 if (IS_GEN5(dev)) {
1876 /* ILK workaround: disable reset around power sequence */
1877 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1878 I915_WRITE(pp_ctrl_reg, pp);
1879 POSTING_READ(pp_ctrl_reg);
05ce1a49 1880 }
37c6c9b0 1881
1c0ae80a 1882 pp |= POWER_TARGET_ON;
99ea7127
KP		 1883 if (!IS_GEN5(dev))
1884 pp |= PANEL_POWER_RESET;
1885
453c5420
JB		 1886 I915_WRITE(pp_ctrl_reg, pp);
1887 POSTING_READ(pp_ctrl_reg);
9934c132 1888
4be73780 1889 wait_panel_on(intel_dp);
dce56b3c 1890 intel_dp->last_power_on = jiffies;
9934c132 1891
05ce1a49
KP		 1892 if (IS_GEN5(dev)) {
1893 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1894 I915_WRITE(pp_ctrl_reg, pp);
1895 POSTING_READ(pp_ctrl_reg);
05ce1a49 1896 }
9f0fb5be 1897}
e39b999a 1898
9f0fb5be
VS		 1899void intel_edp_panel_on(struct intel_dp *intel_dp)
1900{
1901 if (!is_edp(intel_dp))
1902 return;
1903
1904 pps_lock(intel_dp);
1905 edp_panel_on(intel_dp);
773538e8 1906 pps_unlock(intel_dp);
9934c132
JB		 1907}
1908
9f0fb5be
VS		 1909
1910static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1911{
4e6e1a54
ID		 1912 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1913 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1914 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1915 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1916 enum intel_display_power_domain power_domain;
99ea7127 1917 u32 pp;
453c5420 1918 u32 pp_ctrl_reg;
9934c132 1919
9f0fb5be
VS		 1920 lockdep_assert_held(&dev_priv->pps_mutex);
1921
97af61f5
KP		 1922 if (!is_edp(intel_dp))
1923 return;
37c6c9b0 1924
3936fcf4
VS		 1925 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1926 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 1927
3936fcf4
VS		 1928 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1929 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 1930
453c5420 1931 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1932 /* We need to switch off panel power _and_ force vdd, for otherwise some
1933 * panels get very unhappy and cease to work. */
b3064154
PJ		 1934 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1935 EDP_BLC_ENABLE);
453c5420 1936
bf13e81b 1937 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1938
849e39f5
PZ		 1939 intel_dp->want_panel_vdd = false;
1940
453c5420
JB		 1941 I915_WRITE(pp_ctrl_reg, pp);
1942 POSTING_READ(pp_ctrl_reg);
9934c132 1943
dce56b3c 1944 intel_dp->last_power_cycle = jiffies;
4be73780 1945 wait_panel_off(intel_dp);
849e39f5
PZ		 1946
1947 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1948 power_domain = intel_display_port_power_domain(intel_encoder);
1949 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1950}
e39b999a 1951
9f0fb5be
VS		 1952void intel_edp_panel_off(struct intel_dp *intel_dp)
1953{
1954 if (!is_edp(intel_dp))
1955 return;
e39b999a 1956
9f0fb5be
VS		 1957 pps_lock(intel_dp);
1958 edp_panel_off(intel_dp);
773538e8 1959 pps_unlock(intel_dp);
9934c132
JB		 1960}
1961
1250d107
JN		 1962/* Enable backlight in the panel power control. */
1963static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1964{
da63a9f2
PZ		 1965 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1966 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1967 struct drm_i915_private *dev_priv = dev->dev_private;
1968 u32 pp;
453c5420 1969 u32 pp_ctrl_reg;
32f9d658 1970
01cb9ea6
JB		 1971 /*
1972 * If we enable the backlight right away following a panel power
1973 * on, we may see slight flicker as the panel syncs with the eDP
1974 * link. So delay a bit to make sure the image is solid before
1975 * allowing it to appear.
1976 */
4be73780 1977 wait_backlight_on(intel_dp);
e39b999a 1978
773538e8 1979 pps_lock(intel_dp);
e39b999a 1980
453c5420 1981 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1982 pp |= EDP_BLC_ENABLE;
453c5420 1983
bf13e81b 1984 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1985
1986 I915_WRITE(pp_ctrl_reg, pp);
1987 POSTING_READ(pp_ctrl_reg);
e39b999a 1988
773538e8 1989 pps_unlock(intel_dp);
32f9d658
ZW		 1990}
1991
1250d107
JN		 1992/* Enable backlight PWM and backlight PP control. */
1993void intel_edp_backlight_on(struct intel_dp *intel_dp)
1994{
1995 if (!is_edp(intel_dp))
1996 return;
1997
1998 DRM_DEBUG_KMS("\n");
1999
2000 intel_panel_enable_backlight(intel_dp->attached_connector);
2001 _intel_edp_backlight_on(intel_dp);
2002}
2003
2004/* Disable backlight in the panel power control. */
2005static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2006{
30add22d 2007 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 2008 struct drm_i915_private *dev_priv = dev->dev_private;
2009 u32 pp;
453c5420 2010 u32 pp_ctrl_reg;
32f9d658 2011
f01eca2e
KP		 2012 if (!is_edp(intel_dp))
2013 return;
2014
773538e8 2015 pps_lock(intel_dp);
e39b999a 2016
453c5420 2017 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2018 pp &= ~EDP_BLC_ENABLE;
453c5420 2019
bf13e81b 2020 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2021
2022 I915_WRITE(pp_ctrl_reg, pp);
2023 POSTING_READ(pp_ctrl_reg);
f7d2323c 2024
773538e8 2025 pps_unlock(intel_dp);
e39b999a
VS		 2026
2027 intel_dp->last_backlight_off = jiffies;
f7d2323c 2028 edp_wait_backlight_off(intel_dp);
1250d107 2029}
f7d2323c 2030
1250d107
JN		 2031/* Disable backlight PP control and backlight PWM. */
2032void intel_edp_backlight_off(struct intel_dp *intel_dp)
2033{
2034 if (!is_edp(intel_dp))
2035 return;
2036
2037 DRM_DEBUG_KMS("\n");
f7d2323c 2038
1250d107 2039 _intel_edp_backlight_off(intel_dp);
f7d2323c 2040 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2041}
a4fc5ed6 2042
73580fb7
JN		 2043/*
2044 * Hook for controlling the panel power control backlight through the bl_power
2045 * sysfs attribute. Take care to handle multiple calls.
2046 */
2047static void intel_edp_backlight_power(struct intel_connector *connector,
2048 bool enable)
2049{
2050 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2051 bool is_enabled;
2052
773538e8 2053 pps_lock(intel_dp);
e39b999a 2054 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2055 pps_unlock(intel_dp);
73580fb7
JN		 2056
2057 if (is_enabled == enable)
2058 return;
2059
23ba9373
JN		 2060 DRM_DEBUG_KMS("panel power control backlight %s\n",
2061 enable ? "enable" : "disable");
73580fb7
JN		 2062
2063 if (enable)
2064 _intel_edp_backlight_on(intel_dp);
2065 else
2066 _intel_edp_backlight_off(intel_dp);
2067}
2068
2bd2ad64 2069static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2070{
da63a9f2
PZ		 2071 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2072 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2073 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2074 struct drm_i915_private *dev_priv = dev->dev_private;
2075 u32 dpa_ctl;
2076
2bd2ad64
DV		 2077 assert_pipe_disabled(dev_priv,
2078 to_intel_crtc(crtc)->pipe);
2079
d240f20f
JB		 2080 DRM_DEBUG_KMS("\n");
2081 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2082 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
2083 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2084
2085 /* We don't adjust intel_dp->DP while tearing down the link, to
2086 * facilitate link retraining (e.g. after hotplug). Hence clear all
2087 * enable bits here to ensure that we don't enable too much. */
2088 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
2089 intel_dp->DP |= DP_PLL_ENABLE;
2090 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2091 POSTING_READ(DP_A);
2092 udelay(200);
d240f20f
JB		 2093}
2094
2bd2ad64 2095static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2096{
da63a9f2
PZ		 2097 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2098 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2099 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2100 struct drm_i915_private *dev_priv = dev->dev_private;
2101 u32 dpa_ctl;
2102
2bd2ad64
DV		 2103 assert_pipe_disabled(dev_priv,
2104 to_intel_crtc(crtc)->pipe);
2105
d240f20f 2106 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2107 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
2108 "dp pll off, should be on\n");
2109 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2110
2111 /* We can't rely on the value tracked for the DP register in
2112 * intel_dp->DP because link_down must not change that (otherwise link
2113 * re-training will fail. */
298b0b39 2114 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 2115 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 2116 POSTING_READ(DP_A);
d240f20f
JB		 2117 udelay(200);
2118}
2119
c7ad3810 2120/* If the sink supports it, try to set the power state appropriately */
c19b0669 2121void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2122{
2123 int ret, i;
2124
2125 /* Should have a valid DPCD by this point */
2126 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2127 return;
2128
2129 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2130 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2131 DP_SET_POWER_D3);
c7ad3810
JB		 2132 } else {
2133 /*
2134 * When turning on, we need to retry for 1ms to give the sink
2135 * time to wake up.
2136 */
2137 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2138 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2139 DP_SET_POWER_D0);
c7ad3810
JB		 2140 if (ret == 1)
2141 break;
2142 msleep(1);
2143 }
2144 }
f9cac721
JN		 2145
2146 if (ret != 1)
2147 DRM_DEBUG_KMS("failed to %s sink power state\n",
2148 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2149}
2150
19d8fe15
DV		 2151static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2152 enum pipe *pipe)
d240f20f 2153{
19d8fe15 2154 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2155 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2156 struct drm_device *dev = encoder->base.dev;
2157 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2158 enum intel_display_power_domain power_domain;
2159 u32 tmp;
2160
2161 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 2162 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 2163 return false;
2164
2165 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2166
2167 if (!(tmp & DP_PORT_EN))
2168 return false;
2169
bc7d38a4 2170 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 2171 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 2172 } else if (IS_CHERRYVIEW(dev)) {
2173 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 2174 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 2175 *pipe = PORT_TO_PIPE(tmp);
2176 } else {
2177 u32 trans_sel;
2178 u32 trans_dp;
2179 int i;
2180
2181 switch (intel_dp->output_reg) {
2182 case PCH_DP_B:
2183 trans_sel = TRANS_DP_PORT_SEL_B;
2184 break;
2185 case PCH_DP_C:
2186 trans_sel = TRANS_DP_PORT_SEL_C;
2187 break;
2188 case PCH_DP_D:
2189 trans_sel = TRANS_DP_PORT_SEL_D;
2190 break;
2191 default:
2192 return true;
2193 }
2194
055e393f 2195 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 2196 trans_dp = I915_READ(TRANS_DP_CTL(i));
2197 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
2198 *pipe = i;
2199 return true;
2200 }
2201 }
19d8fe15 2202
4a0833ec
DV		 2203 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2204 intel_dp->output_reg);
2205 }
d240f20f 2206
19d8fe15
DV		 2207 return true;
2208}
d240f20f 2209
045ac3b5 2210static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2211 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2212{
2213 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2214 u32 tmp, flags = 0;
63000ef6
XZ		 2215 struct drm_device *dev = encoder->base.dev;
2216 struct drm_i915_private *dev_priv = dev->dev_private;
2217 enum port port = dp_to_dig_port(intel_dp)->port;
2218 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 2219 int dotclock;
045ac3b5 2220
9ed109a7
DV		 2221 tmp = I915_READ(intel_dp->output_reg);
2222 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2223 pipe_config->has_audio = true;
2224
63000ef6 2225 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 2226 if (tmp & DP_SYNC_HS_HIGH)
2227 flags |= DRM_MODE_FLAG_PHSYNC;
2228 else
2229 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2230
63000ef6
XZ		 2231 if (tmp & DP_SYNC_VS_HIGH)
2232 flags |= DRM_MODE_FLAG_PVSYNC;
2233 else
2234 flags |= DRM_MODE_FLAG_NVSYNC;
2235 } else {
2236 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2237 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2238 flags |= DRM_MODE_FLAG_PHSYNC;
2239 else
2240 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2241
63000ef6
XZ		 2242 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2243 flags |= DRM_MODE_FLAG_PVSYNC;
2244 else
2245 flags |= DRM_MODE_FLAG_NVSYNC;
2246 }
045ac3b5 2247
2d112de7 2248 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2249
8c875fca
VS		 2250 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2251 tmp & DP_COLOR_RANGE_16_235)
2252 pipe_config->limited_color_range = true;
2253
eb14cb74
VS		 2254 pipe_config->has_dp_encoder = true;
2255
2256 intel_dp_get_m_n(crtc, pipe_config);
2257
18442d08 2258 if (port == PORT_A) {
f1f644dc
JB		 2259 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2260 pipe_config->port_clock = 162000;
2261 else
2262 pipe_config->port_clock = 270000;
2263 }
18442d08
VS		 2264
2265 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2266 &pipe_config->dp_m_n);
2267
2268 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2269 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2270
2d112de7 2271 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2272
c6cd2ee2
JN		 2273 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2274 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2275 /*
2276 * This is a big fat ugly hack.
2277 *
2278 * Some machines in UEFI boot mode provide us a VBT that has 18
2279 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2280 * unknown we fail to light up. Yet the same BIOS boots up with
2281 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2282 * max, not what it tells us to use.
2283 *
2284 * Note: This will still be broken if the eDP panel is not lit
2285 * up by the BIOS, and thus we can't get the mode at module
2286 * load.
2287 */
2288 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2289 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2290 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2291 }
045ac3b5
JB		 2292}
2293
e8cb4558 2294static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2295{
e8cb4558 2296 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2297 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2298 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2299
6e3c9717 2300 if (crtc->config->has_audio)
495a5bb8 2301 intel_audio_codec_disable(encoder);
6cb49835 2302
b32c6f48
RV		 2303 if (HAS_PSR(dev) && !HAS_DDI(dev))
2304 intel_psr_disable(intel_dp);
2305
6cb49835
DV		 2306 /* Make sure the panel is off before trying to change the mode. But also
2307 * ensure that we have vdd while we switch off the panel. */
24f3e092 2308 intel_edp_panel_vdd_on(intel_dp);
4be73780 2309 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2310 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2311 intel_edp_panel_off(intel_dp);
3739850b 2312
08aff3fe
VS		 2313 /* disable the port before the pipe on g4x */
2314 if (INTEL_INFO(dev)->gen < 5)
3739850b 2315 intel_dp_link_down(intel_dp);
d240f20f
JB		 2316}
2317
08aff3fe 2318static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2319{
2bd2ad64 2320 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2321 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2322
49277c31 2323 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2324 if (port == PORT_A)
2325 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2326}
2327
2328static void vlv_post_disable_dp(struct intel_encoder *encoder)
2329{
2330 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2331
2332 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2333}
2334
580d3811
VS		 2335static void chv_post_disable_dp(struct intel_encoder *encoder)
2336{
2337 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2338 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2339 struct drm_device *dev = encoder->base.dev;
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341 struct intel_crtc *intel_crtc =
2342 to_intel_crtc(encoder->base.crtc);
2343 enum dpio_channel ch = vlv_dport_to_channel(dport);
2344 enum pipe pipe = intel_crtc->pipe;
2345 u32 val;
2346
2347 intel_dp_link_down(intel_dp);
2348
2349 mutex_lock(&dev_priv->dpio_lock);
2350
2351 /* Propagate soft reset to data lane reset */
97fd4d5c 2352 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2353 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2354 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2355
97fd4d5c
VS		 2356 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2357 val |= CHV_PCS_REQ_SOFTRESET_EN;
2358 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2359
2360 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2361 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2362 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2363
2364 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2365 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2366 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2367
2368 mutex_unlock(&dev_priv->dpio_lock);
2369}
2370
7b13b58a
VS		 2371static void
2372_intel_dp_set_link_train(struct intel_dp *intel_dp,
2373 uint32_t *DP,
2374 uint8_t dp_train_pat)
2375{
2376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2377 struct drm_device *dev = intel_dig_port->base.base.dev;
2378 struct drm_i915_private *dev_priv = dev->dev_private;
2379 enum port port = intel_dig_port->port;
2380
2381 if (HAS_DDI(dev)) {
2382 uint32_t temp = I915_READ(DP_TP_CTL(port));
2383
2384 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2385 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2386 else
2387 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2388
2389 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2390 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2391 case DP_TRAINING_PATTERN_DISABLE:
2392 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2393
2394 break;
2395 case DP_TRAINING_PATTERN_1:
2396 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2397 break;
2398 case DP_TRAINING_PATTERN_2:
2399 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2400 break;
2401 case DP_TRAINING_PATTERN_3:
2402 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2403 break;
2404 }
2405 I915_WRITE(DP_TP_CTL(port), temp);
2406
2407 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2408 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2409
2410 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2411 case DP_TRAINING_PATTERN_DISABLE:
2412 *DP |= DP_LINK_TRAIN_OFF_CPT;
2413 break;
2414 case DP_TRAINING_PATTERN_1:
2415 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2416 break;
2417 case DP_TRAINING_PATTERN_2:
2418 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2419 break;
2420 case DP_TRAINING_PATTERN_3:
2421 DRM_ERROR("DP training pattern 3 not supported\n");
2422 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2423 break;
2424 }
2425
2426 } else {
2427 if (IS_CHERRYVIEW(dev))
2428 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2429 else
2430 *DP &= ~DP_LINK_TRAIN_MASK;
2431
2432 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2433 case DP_TRAINING_PATTERN_DISABLE:
2434 *DP |= DP_LINK_TRAIN_OFF;
2435 break;
2436 case DP_TRAINING_PATTERN_1:
2437 *DP |= DP_LINK_TRAIN_PAT_1;
2438 break;
2439 case DP_TRAINING_PATTERN_2:
2440 *DP |= DP_LINK_TRAIN_PAT_2;
2441 break;
2442 case DP_TRAINING_PATTERN_3:
2443 if (IS_CHERRYVIEW(dev)) {
2444 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2445 } else {
2446 DRM_ERROR("DP training pattern 3 not supported\n");
2447 *DP |= DP_LINK_TRAIN_PAT_2;
2448 }
2449 break;
2450 }
2451 }
2452}
2453
2454static void intel_dp_enable_port(struct intel_dp *intel_dp)
2455{
2456 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2457 struct drm_i915_private *dev_priv = dev->dev_private;
2458
7b13b58a
VS		 2459 /* enable with pattern 1 (as per spec) */
2460 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2461 DP_TRAINING_PATTERN_1);
2462
2463 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2464 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2465
2466 /*
2467 * Magic for VLV/CHV. We _must_ first set up the register
2468 * without actually enabling the port, and then do another
2469 * write to enable the port. Otherwise link training will
2470 * fail when the power sequencer is freshly used for this port.
2471 */
2472 intel_dp->DP |= DP_PORT_EN;
2473
2474 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2475 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2476}
2477
e8cb4558 2478static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2479{
e8cb4558
DV		 2480 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2481 struct drm_device *dev = encoder->base.dev;
2482 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2483 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2484 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2485
0c33d8d7
DV		 2486 if (WARN_ON(dp_reg & DP_PORT_EN))
2487 return;
5d613501 2488
093e3f13
VS		 2489 pps_lock(intel_dp);
2490
2491 if (IS_VALLEYVIEW(dev))
2492 vlv_init_panel_power_sequencer(intel_dp);
2493
7b13b58a 2494 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2495
2496 edp_panel_vdd_on(intel_dp);
2497 edp_panel_on(intel_dp);
2498 edp_panel_vdd_off(intel_dp, true);
2499
2500 pps_unlock(intel_dp);
2501
61234fa5
VS		 2502 if (IS_VALLEYVIEW(dev))
2503 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2504
f01eca2e 2505 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2506 intel_dp_start_link_train(intel_dp);
33a34e4e 2507 intel_dp_complete_link_train(intel_dp);
3ab9c637 2508 intel_dp_stop_link_train(intel_dp);
c1dec79a 2509
6e3c9717 2510 if (crtc->config->has_audio) {
c1dec79a
JN		 2511 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2512 pipe_name(crtc->pipe));
2513 intel_audio_codec_enable(encoder);
2514 }
ab1f90f9 2515}
89b667f8 2516
ecff4f3b
JN		 2517static void g4x_enable_dp(struct intel_encoder *encoder)
2518{
828f5c6e
JN		 2519 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2520
ecff4f3b 2521 intel_enable_dp(encoder);
4be73780 2522 intel_edp_backlight_on(intel_dp);
ab1f90f9 2523}
89b667f8 2524
ab1f90f9
JN		 2525static void vlv_enable_dp(struct intel_encoder *encoder)
2526{
828f5c6e
JN		 2527 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2528
4be73780 2529 intel_edp_backlight_on(intel_dp);
b32c6f48 2530 intel_psr_enable(intel_dp);
d240f20f
JB		 2531}
2532
ecff4f3b 2533static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2534{
2535 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2536 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2537
8ac33ed3
DV		 2538 intel_dp_prepare(encoder);
2539
d41f1efb
DV		 2540 /* Only ilk+ has port A */
2541 if (dport->port == PORT_A) {
2542 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2543 ironlake_edp_pll_on(intel_dp);
d41f1efb 2544 }
ab1f90f9
JN		 2545}
2546
83b84597
VS		 2547static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2548{
2549 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2550 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2551 enum pipe pipe = intel_dp->pps_pipe;
2552 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2553
2554 edp_panel_vdd_off_sync(intel_dp);
2555
2556 /*
2557 * VLV seems to get confused when multiple power seqeuencers
2558 * have the same port selected (even if only one has power/vdd
2559 * enabled). The failure manifests as vlv_wait_port_ready() failing
2560 * CHV on the other hand doesn't seem to mind having the same port
2561 * selected in multiple power seqeuencers, but let's clear the
2562 * port select always when logically disconnecting a power sequencer
2563 * from a port.
2564 */
2565 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2566 pipe_name(pipe), port_name(intel_dig_port->port));
2567 I915_WRITE(pp_on_reg, 0);
2568 POSTING_READ(pp_on_reg);
2569
2570 intel_dp->pps_pipe = INVALID_PIPE;
2571}
2572
a4a5d2f8
VS		 2573static void vlv_steal_power_sequencer(struct drm_device *dev,
2574 enum pipe pipe)
2575{
2576 struct drm_i915_private *dev_priv = dev->dev_private;
2577 struct intel_encoder *encoder;
2578
2579 lockdep_assert_held(&dev_priv->pps_mutex);
2580
ac3c12e4
VS		 2581 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2582 return;
2583
a4a5d2f8
VS		 2584 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2585 base.head) {
2586 struct intel_dp *intel_dp;
773538e8 2587 enum port port;
a4a5d2f8
VS		 2588
2589 if (encoder->type != INTEL_OUTPUT_EDP)
2590 continue;
2591
2592 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2593 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2594
2595 if (intel_dp->pps_pipe != pipe)
2596 continue;
2597
2598 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2599 pipe_name(pipe), port_name(port));
a4a5d2f8 2600
034e43c6
VS		 2601 WARN(encoder->connectors_active,
2602 "stealing pipe %c power sequencer from active eDP port %c\n",
2603 pipe_name(pipe), port_name(port));
a4a5d2f8 2604
a4a5d2f8 2605 /* make sure vdd is off before we steal it */
83b84597 2606 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2607 }
2608}
2609
2610static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2611{
2612 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2613 struct intel_encoder *encoder = &intel_dig_port->base;
2614 struct drm_device *dev = encoder->base.dev;
2615 struct drm_i915_private *dev_priv = dev->dev_private;
2616 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2617
2618 lockdep_assert_held(&dev_priv->pps_mutex);
2619
093e3f13
VS		 2620 if (!is_edp(intel_dp))
2621 return;
2622
a4a5d2f8
VS		 2623 if (intel_dp->pps_pipe == crtc->pipe)
2624 return;
2625
2626 /*
2627 * If another power sequencer was being used on this
2628 * port previously make sure to turn off vdd there while
2629 * we still have control of it.
2630 */
2631 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2632 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2633
2634 /*
2635 * We may be stealing the power
2636 * sequencer from another port.
2637 */
2638 vlv_steal_power_sequencer(dev, crtc->pipe);
2639
2640 /* now it's all ours */
2641 intel_dp->pps_pipe = crtc->pipe;
2642
2643 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2644 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2645
2646 /* init power sequencer on this pipe and port */
36b5f425
VS		 2647 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2648 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2649}
2650
ab1f90f9 2651static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2652{
2bd2ad64 2653 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2654 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2655 struct drm_device *dev = encoder->base.dev;
89b667f8 2656 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2657 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2658 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2659 int pipe = intel_crtc->pipe;
2660 u32 val;
a4fc5ed6 2661
ab1f90f9 2662 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2663
ab3c759a 2664 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2665 val = 0;
2666 if (pipe)
2667 val |= (1<<21);
2668 else
2669 val &= ~(1<<21);
2670 val |= 0x001000c4;
ab3c759a
CML		 2671 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2672 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2673 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2674
ab1f90f9
JN		 2675 mutex_unlock(&dev_priv->dpio_lock);
2676
2677 intel_enable_dp(encoder);
89b667f8
JB		 2678}
2679
ecff4f3b 2680static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2681{
2682 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2683 struct drm_device *dev = encoder->base.dev;
2684 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2685 struct intel_crtc *intel_crtc =
2686 to_intel_crtc(encoder->base.crtc);
e4607fcf 2687 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2688 int pipe = intel_crtc->pipe;
89b667f8 2689
8ac33ed3
DV		 2690 intel_dp_prepare(encoder);
2691
89b667f8 2692 /* Program Tx lane resets to default */
0980a60f 2693 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2694 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2695 DPIO_PCS_TX_LANE2_RESET |
2696 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2697 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2698 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2699 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2700 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2701 DPIO_PCS_CLK_SOFT_RESET);
2702
2703 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2704 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2705 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2706 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2707 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2708}
2709
e4a1d846
CML		 2710static void chv_pre_enable_dp(struct intel_encoder *encoder)
2711{
2712 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2713 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2714 struct drm_device *dev = encoder->base.dev;
2715 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2716 struct intel_crtc *intel_crtc =
2717 to_intel_crtc(encoder->base.crtc);
2718 enum dpio_channel ch = vlv_dport_to_channel(dport);
2719 int pipe = intel_crtc->pipe;
2720 int data, i;
949c1d43 2721 u32 val;
e4a1d846 2722
e4a1d846 2723 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2724
570e2a74
VS		 2725 /* allow hardware to manage TX FIFO reset source */
2726 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2727 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2728 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2729
2730 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2731 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2732 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2733
949c1d43 2734 /* Deassert soft data lane reset*/
97fd4d5c 2735 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2736 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2737 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2738
2739 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2740 val |= CHV_PCS_REQ_SOFTRESET_EN;
2741 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2742
2743 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2744 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2745 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2746
97fd4d5c 2747 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2748 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2749 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2750
2751 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2752 for (i = 0; i < 4; i++) {
2753 /* Set the latency optimal bit */
2754 data = (i == 1) ? 0x0 : 0x6;
2755 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2756 data << DPIO_FRC_LATENCY_SHFIT);
2757
2758 /* Set the upar bit */
2759 data = (i == 1) ? 0x0 : 0x1;
2760 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2761 data << DPIO_UPAR_SHIFT);
2762 }
2763
2764 /* Data lane stagger programming */
2765 /* FIXME: Fix up value only after power analysis */
2766
2767 mutex_unlock(&dev_priv->dpio_lock);
2768
e4a1d846 2769 intel_enable_dp(encoder);
e4a1d846
CML		 2770}
2771
9197c88b
VS		 2772static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2773{
2774 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2775 struct drm_device *dev = encoder->base.dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 struct intel_crtc *intel_crtc =
2778 to_intel_crtc(encoder->base.crtc);
2779 enum dpio_channel ch = vlv_dport_to_channel(dport);
2780 enum pipe pipe = intel_crtc->pipe;
2781 u32 val;
2782
625695f8
VS		 2783 intel_dp_prepare(encoder);
2784
9197c88b
VS		 2785 mutex_lock(&dev_priv->dpio_lock);
2786
b9e5ac3c
VS		 2787 /* program left/right clock distribution */
2788 if (pipe != PIPE_B) {
2789 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2790 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2791 if (ch == DPIO_CH0)
2792 val |= CHV_BUFLEFTENA1_FORCE;
2793 if (ch == DPIO_CH1)
2794 val |= CHV_BUFRIGHTENA1_FORCE;
2795 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2796 } else {
2797 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2798 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2799 if (ch == DPIO_CH0)
2800 val |= CHV_BUFLEFTENA2_FORCE;
2801 if (ch == DPIO_CH1)
2802 val |= CHV_BUFRIGHTENA2_FORCE;
2803 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2804 }
2805
9197c88b
VS		 2806 /* program clock channel usage */
2807 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2808 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2809 if (pipe != PIPE_B)
2810 val &= ~CHV_PCS_USEDCLKCHANNEL;
2811 else
2812 val |= CHV_PCS_USEDCLKCHANNEL;
2813 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2814
2815 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2816 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2817 if (pipe != PIPE_B)
2818 val &= ~CHV_PCS_USEDCLKCHANNEL;
2819 else
2820 val |= CHV_PCS_USEDCLKCHANNEL;
2821 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2822
2823 /*
2824 * This a a bit weird since generally CL
2825 * matches the pipe, but here we need to
2826 * pick the CL based on the port.
2827 */
2828 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2829 if (pipe != PIPE_B)
2830 val &= ~CHV_CMN_USEDCLKCHANNEL;
2831 else
2832 val |= CHV_CMN_USEDCLKCHANNEL;
2833 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2834
2835 mutex_unlock(&dev_priv->dpio_lock);
2836}
2837
a4fc5ed6 2838/*
df0c237d
JB		 2839 * Native read with retry for link status and receiver capability reads for
2840 * cases where the sink may still be asleep.
9d1a1031
JN		 2841 *
2842 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2843 * supposed to retry 3 times per the spec.
a4fc5ed6 2844 */
9d1a1031
JN		 2845static ssize_t
2846intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2847 void *buffer, size_t size)
a4fc5ed6 2848{
9d1a1031
JN		 2849 ssize_t ret;
2850 int i;
61da5fab 2851
f6a19066
VS		 2852 /*
2853 * Sometime we just get the same incorrect byte repeated
2854 * over the entire buffer. Doing just one throw away read
2855 * initially seems to "solve" it.
2856 */
2857 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2858
61da5fab 2859 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2860 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2861 if (ret == size)
2862 return ret;
61da5fab
JB		 2863 msleep(1);
2864 }
a4fc5ed6 2865
9d1a1031 2866 return ret;
a4fc5ed6
KP		 2867}
2868
2869/*
2870 * Fetch AUX CH registers 0x202 - 0x207 which contain
2871 * link status information
2872 */
2873static bool
93f62dad 2874intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2875{
9d1a1031
JN		 2876 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2877 DP_LANE0_1_STATUS,
2878 link_status,
2879 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2880}
2881
1100244e 2882/* These are source-specific values. */
a4fc5ed6 2883static uint8_t
1a2eb460 2884intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2885{
30add22d 2886 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 2887 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 2888 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2889
9314726b
VK		 2890 if (IS_BROXTON(dev))
2891 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2892 else if (INTEL_INFO(dev)->gen >= 9) {
7ad14a29
SJ		 2893 if (dev_priv->vbt.edp_low_vswing && port == PORT_A)
2894 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2895 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
7ad14a29 2896 } else if (IS_VALLEYVIEW(dev))
bd60018a 2897 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2898 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2899 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2900 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2901 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2902 else
bd60018a 2903 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2904}
2905
2906static uint8_t
2907intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2908{
30add22d 2909 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2910 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2911
5a9d1f1a
DL		 2912 if (INTEL_INFO(dev)->gen >= 9) {
2913 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2914 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2915 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2916 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2917 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2918 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2919 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 2920 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2921 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 2922 default:
2923 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2924 }
2925 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2926 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2927 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2928 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2930 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2931 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2932 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2934 default:
bd60018a 2935 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2936 }
e2fa6fba
P		 2937 } else if (IS_VALLEYVIEW(dev)) {
2938 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2940 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2941 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2942 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2943 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2944 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2945 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2946 default:
bd60018a 2947 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2948 }
bc7d38a4 2949 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2950 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2951 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2952 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2953 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2954 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2955 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2956 default:
bd60018a 2957 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2958 }
2959 } else {
2960 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2961 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2962 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2963 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2964 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2965 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2966 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2968 default:
bd60018a 2969 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2970 }
a4fc5ed6
KP		 2971 }
2972}
2973
5829975c 2974static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba
P		 2975{
2976 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2977 struct drm_i915_private *dev_priv = dev->dev_private;
2978 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2979 struct intel_crtc *intel_crtc =
2980 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2981 unsigned long demph_reg_value, preemph_reg_value,
2982 uniqtranscale_reg_value;
2983 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2984 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2985 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2986
2987 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2988 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2989 preemph_reg_value = 0x0004000;
2990 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2991 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2992 demph_reg_value = 0x2B405555;
2993 uniqtranscale_reg_value = 0x552AB83A;
2994 break;
bd60018a 2995 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2996 demph_reg_value = 0x2B404040;
2997 uniqtranscale_reg_value = 0x5548B83A;
2998 break;
bd60018a 2999 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3000 demph_reg_value = 0x2B245555;
3001 uniqtranscale_reg_value = 0x5560B83A;
3002 break;
bd60018a 3003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3004 demph_reg_value = 0x2B405555;
3005 uniqtranscale_reg_value = 0x5598DA3A;
3006 break;
3007 default:
3008 return 0;
3009 }
3010 break;
bd60018a 3011 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3012 preemph_reg_value = 0x0002000;
3013 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3014 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3015 demph_reg_value = 0x2B404040;
3016 uniqtranscale_reg_value = 0x5552B83A;
3017 break;
bd60018a 3018 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3019 demph_reg_value = 0x2B404848;
3020 uniqtranscale_reg_value = 0x5580B83A;
3021 break;
bd60018a 3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3023 demph_reg_value = 0x2B404040;
3024 uniqtranscale_reg_value = 0x55ADDA3A;
3025 break;
3026 default:
3027 return 0;
3028 }
3029 break;
bd60018a 3030 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3031 preemph_reg_value = 0x0000000;
3032 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3034 demph_reg_value = 0x2B305555;
3035 uniqtranscale_reg_value = 0x5570B83A;
3036 break;
bd60018a 3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3038 demph_reg_value = 0x2B2B4040;
3039 uniqtranscale_reg_value = 0x55ADDA3A;
3040 break;
3041 default:
3042 return 0;
3043 }
3044 break;
bd60018a 3045 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3046 preemph_reg_value = 0x0006000;
3047 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3048 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3049 demph_reg_value = 0x1B405555;
3050 uniqtranscale_reg_value = 0x55ADDA3A;
3051 break;
3052 default:
3053 return 0;
3054 }
3055 break;
3056 default:
3057 return 0;
3058 }
3059
0980a60f 3060 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3061 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3062 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3063 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3064 uniqtranscale_reg_value);
ab3c759a
CML		 3065 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3066 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3067 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3068 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3069 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3070
3071 return 0;
3072}
3073
5829975c 3074static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846
CML		 3075{
3076 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3079 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3080 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3081 uint8_t train_set = intel_dp->train_set[0];
3082 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3083 enum pipe pipe = intel_crtc->pipe;
3084 int i;
e4a1d846
CML		 3085
3086 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3087 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3088 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3090 deemph_reg_value = 128;
3091 margin_reg_value = 52;
3092 break;
bd60018a 3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3094 deemph_reg_value = 128;
3095 margin_reg_value = 77;
3096 break;
bd60018a 3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3098 deemph_reg_value = 128;
3099 margin_reg_value = 102;
3100 break;
bd60018a 3101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3102 deemph_reg_value = 128;
3103 margin_reg_value = 154;
3104 /* FIXME extra to set for 1200 */
3105 break;
3106 default:
3107 return 0;
3108 }
3109 break;
bd60018a 3110 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3111 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3112 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3113 deemph_reg_value = 85;
3114 margin_reg_value = 78;
3115 break;
bd60018a 3116 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3117 deemph_reg_value = 85;
3118 margin_reg_value = 116;
3119 break;
bd60018a 3120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3121 deemph_reg_value = 85;
3122 margin_reg_value = 154;
3123 break;
3124 default:
3125 return 0;
3126 }
3127 break;
bd60018a 3128 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3129 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3130 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3131 deemph_reg_value = 64;
3132 margin_reg_value = 104;
3133 break;
bd60018a 3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3135 deemph_reg_value = 64;
3136 margin_reg_value = 154;
3137 break;
3138 default:
3139 return 0;
3140 }
3141 break;
bd60018a 3142 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3143 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3144 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3145 deemph_reg_value = 43;
3146 margin_reg_value = 154;
3147 break;
3148 default:
3149 return 0;
3150 }
3151 break;
3152 default:
3153 return 0;
3154 }
3155
3156 mutex_lock(&dev_priv->dpio_lock);
3157
3158 /* Clear calc init */
1966e59e
VS		 3159 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3160 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3161 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3162 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3163 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3164
3165 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3166 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3167 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3168 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3169 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3170
a02ef3c7
VS		 3171 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3172 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3173 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3174 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3175
3176 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3177 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3178 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3179 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3180
e4a1d846 3181 /* Program swing deemph */
f72df8db
VS		 3182 for (i = 0; i < 4; i++) {
3183 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3184 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3185 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3186 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3187 }
e4a1d846
CML		 3188
3189 /* Program swing margin */
f72df8db
VS		 3190 for (i = 0; i < 4; i++) {
3191 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3192 val &= ~DPIO_SWING_MARGIN000_MASK;
3193 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3194 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3195 }
e4a1d846
CML		 3196
3197 /* Disable unique transition scale */
f72df8db
VS		 3198 for (i = 0; i < 4; i++) {
3199 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3200 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3201 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3202 }
e4a1d846
CML		 3203
3204 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3205 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3206 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3207 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3208
3209 /*
3210 * The document said it needs to set bit 27 for ch0 and bit 26
3211 * for ch1. Might be a typo in the doc.
3212 * For now, for this unique transition scale selection, set bit
3213 * 27 for ch0 and ch1.
3214 */
f72df8db
VS		 3215 for (i = 0; i < 4; i++) {
3216 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3217 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3218 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3219 }
e4a1d846 3220
f72df8db
VS		 3221 for (i = 0; i < 4; i++) {
3222 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3223 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3224 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3225 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3226 }
e4a1d846
CML		 3227 }
3228
3229 /* Start swing calculation */
1966e59e
VS		 3230 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3231 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3232 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3233
3234 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3235 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3236 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3237
3238 /* LRC Bypass */
3239 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3240 val |= DPIO_LRC_BYPASS;
3241 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3242
3243 mutex_unlock(&dev_priv->dpio_lock);
3244
3245 return 0;
3246}
3247
a4fc5ed6 3248static void
0301b3ac
JN		 3249intel_get_adjust_train(struct intel_dp *intel_dp,
3250 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3251{
3252 uint8_t v = 0;
3253 uint8_t p = 0;
3254 int lane;
1a2eb460
KP		 3255 uint8_t voltage_max;
3256 uint8_t preemph_max;
a4fc5ed6 3257
33a34e4e 3258 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3259 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3260 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3261
3262 if (this_v > v)
3263 v = this_v;
3264 if (this_p > p)
3265 p = this_p;
3266 }
3267
1a2eb460 3268 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3269 if (v >= voltage_max)
3270 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3271
1a2eb460
KP		 3272 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3273 if (p >= preemph_max)
3274 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3275
3276 for (lane = 0; lane < 4; lane++)
33a34e4e 3277 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3278}
3279
3280static uint32_t
5829975c 3281gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3282{
3cf2efb1 3283 uint32_t signal_levels = 0;
a4fc5ed6 3284
3cf2efb1 3285 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3287 default:
3288 signal_levels |= DP_VOLTAGE_0_4;
3289 break;
bd60018a 3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3291 signal_levels |= DP_VOLTAGE_0_6;
3292 break;
bd60018a 3293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3294 signal_levels |= DP_VOLTAGE_0_8;
3295 break;
bd60018a 3296 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3297 signal_levels |= DP_VOLTAGE_1_2;
3298 break;
3299 }
3cf2efb1 3300 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3301 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3302 default:
3303 signal_levels |= DP_PRE_EMPHASIS_0;
3304 break;
bd60018a 3305 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3306 signal_levels |= DP_PRE_EMPHASIS_3_5;
3307 break;
bd60018a 3308 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3309 signal_levels |= DP_PRE_EMPHASIS_6;
3310 break;
bd60018a 3311 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3312 signal_levels |= DP_PRE_EMPHASIS_9_5;
3313 break;
3314 }
3315 return signal_levels;
3316}
3317
e3421a18
ZW		 3318/* Gen6's DP voltage swing and pre-emphasis control */
3319static uint32_t
5829975c 3320gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3321{
3c5a62b5
YL		 3322 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3323 DP_TRAIN_PRE_EMPHASIS_MASK);
3324 switch (signal_levels) {
bd60018a
SJ		 3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3326 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3327 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3328 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3329 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3330 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3331 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3332 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3334 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3335 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3336 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3337 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3338 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3339 default:
3c5a62b5
YL		 3340 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3341 "0x%x\n", signal_levels);
3342 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3343 }
3344}
3345
1a2eb460
KP		 3346/* Gen7's DP voltage swing and pre-emphasis control */
3347static uint32_t
5829975c 3348gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3349{
3350 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3351 DP_TRAIN_PRE_EMPHASIS_MASK);
3352 switch (signal_levels) {
bd60018a 3353 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3354 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3355 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3356 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3357 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3358 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3359
bd60018a 3360 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3361 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3362 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3363 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3364
bd60018a 3365 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3366 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3367 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3368 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3369
3370 default:
3371 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3372 "0x%x\n", signal_levels);
3373 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3374 }
3375}
3376
d6c0d722
PZ		 3377/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3378static uint32_t
5829975c 3379hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3380{
d6c0d722
PZ		 3381 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3382 DP_TRAIN_PRE_EMPHASIS_MASK);
3383 switch (signal_levels) {
bd60018a 3384 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3385 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3386 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3387 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3388 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3389 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3390 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3391 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3392
bd60018a 3393 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3394 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3395 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3396 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3397 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3398 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3399
bd60018a 3400 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3401 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3402 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3403 return DDI_BUF_TRANS_SELECT(8);
7ad14a29
SJ		 3404
3405 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3406 return DDI_BUF_TRANS_SELECT(9);
d6c0d722
PZ		 3407 default:
3408 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3409 "0x%x\n", signal_levels);
c5fe6a06 3410 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3411 }
a4fc5ed6
KP		 3412}
3413
5829975c 3414static void bxt_signal_levels(struct intel_dp *intel_dp)
96fb9f9b
VK		 3415{
3416 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3417 enum port port = dport->port;
3418 struct drm_device *dev = dport->base.base.dev;
3419 struct intel_encoder *encoder = &dport->base;
3420 uint8_t train_set = intel_dp->train_set[0];
3421 uint32_t level = 0;
3422
3423 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3424 DP_TRAIN_PRE_EMPHASIS_MASK);
3425 switch (signal_levels) {
3426 default:
3427 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emph level\n");
3428 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3429 level = 0;
3430 break;
3431 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3432 level = 1;
3433 break;
3434 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3435 level = 2;
3436 break;
3437 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3438 level = 3;
3439 break;
3440 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3441 level = 4;
3442 break;
3443 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3444 level = 5;
3445 break;
3446 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3447 level = 6;
3448 break;
3449 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3450 level = 7;
3451 break;
3452 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3453 level = 8;
3454 break;
3455 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3456 level = 9;
3457 break;
3458 }
3459
3460 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
3461}
3462
f0a3424e
PZ		 3463/* Properly updates "DP" with the correct signal levels. */
3464static void
3465intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3466{
3467 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3468 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3469 struct drm_device *dev = intel_dig_port->base.base.dev;
3470 uint32_t signal_levels, mask;
3471 uint8_t train_set = intel_dp->train_set[0];
3472
96fb9f9b
VK		 3473 if (IS_BROXTON(dev)) {
3474 signal_levels = 0;
5829975c 3475 bxt_signal_levels(intel_dp);
96fb9f9b
VK		 3476 mask = 0;
3477 } else if (HAS_DDI(dev)) {
5829975c 3478 signal_levels = hsw_signal_levels(train_set);
f0a3424e 3479 mask = DDI_BUF_EMP_MASK;
e4a1d846 3480 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3481 signal_levels = chv_signal_levels(intel_dp);
e4a1d846 3482 mask = 0;
e2fa6fba 3483 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3484 signal_levels = vlv_signal_levels(intel_dp);
e2fa6fba 3485 mask = 0;
bc7d38a4 3486 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3487 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3488 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3489 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3490 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3491 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3492 } else {
5829975c 3493 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3494 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3495 }
3496
96fb9f9b
VK		 3497 if (mask)
3498 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3499
3500 DRM_DEBUG_KMS("Using vswing level %d\n",
3501 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3502 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3503 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3504 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e
PZ		 3505
3506 *DP = (*DP & ~mask) | signal_levels;
3507}
3508
a4fc5ed6 3509static bool
ea5b213a 3510intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3511 uint32_t *DP,
58e10eb9 3512 uint8_t dp_train_pat)
a4fc5ed6 3513{
174edf1f
PZ		 3514 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3515 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3516 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3517 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3518 int ret, len;
a4fc5ed6 3519
7b13b58a 3520 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3521
70aff66c 3522 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3523 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3524
2cdfe6c8
JN		 3525 buf[0] = dp_train_pat;
3526 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3527 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3528 /* don't write DP_TRAINING_LANEx_SET on disable */
3529 len = 1;
3530 } else {
3531 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3532 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3533 len = intel_dp->lane_count + 1;
47ea7542 3534 }
a4fc5ed6 3535
9d1a1031
JN		 3536 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3537 buf, len);
2cdfe6c8
JN		 3538
3539 return ret == len;
a4fc5ed6
KP		 3540}
3541
70aff66c
JN		 3542static bool
3543intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3544 uint8_t dp_train_pat)
3545{
953d22e8 3546 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3547 intel_dp_set_signal_levels(intel_dp, DP);
3548 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3549}
3550
3551static bool
3552intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3553 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3554{
3555 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3556 struct drm_device *dev = intel_dig_port->base.base.dev;
3557 struct drm_i915_private *dev_priv = dev->dev_private;
3558 int ret;
3559
3560 intel_get_adjust_train(intel_dp, link_status);
3561 intel_dp_set_signal_levels(intel_dp, DP);
3562
3563 I915_WRITE(intel_dp->output_reg, *DP);
3564 POSTING_READ(intel_dp->output_reg);
3565
9d1a1031
JN		 3566 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3567 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3568
3569 return ret == intel_dp->lane_count;
3570}
3571
3ab9c637
ID		 3572static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3573{
3574 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3575 struct drm_device *dev = intel_dig_port->base.base.dev;
3576 struct drm_i915_private *dev_priv = dev->dev_private;
3577 enum port port = intel_dig_port->port;
3578 uint32_t val;
3579
3580 if (!HAS_DDI(dev))
3581 return;
3582
3583 val = I915_READ(DP_TP_CTL(port));
3584 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3585 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3586 I915_WRITE(DP_TP_CTL(port), val);
3587
3588 /*
3589 * On PORT_A we can have only eDP in SST mode. There the only reason
3590 * we need to set idle transmission mode is to work around a HW issue
3591 * where we enable the pipe while not in idle link-training mode.
3592 * In this case there is requirement to wait for a minimum number of
3593 * idle patterns to be sent.
3594 */
3595 if (port == PORT_A)
3596 return;
3597
3598 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3599 1))
3600 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3601}
3602
33a34e4e 3603/* Enable corresponding port and start training pattern 1 */
c19b0669 3604void
33a34e4e 3605intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3606{
da63a9f2 3607 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3608 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3609 int i;
3610 uint8_t voltage;
cdb0e95b 3611 int voltage_tries, loop_tries;
ea5b213a 3612 uint32_t DP = intel_dp->DP;
6aba5b6c 3613 uint8_t link_config[2];
a4fc5ed6 3614
affa9354 3615 if (HAS_DDI(dev))
c19b0669
PZ		 3616 intel_ddi_prepare_link_retrain(encoder);
3617
3cf2efb1 3618 /* Write the link configuration data */
6aba5b6c
JN		 3619 link_config[0] = intel_dp->link_bw;
3620 link_config[1] = intel_dp->lane_count;
3621 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3622 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3623 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
94ca719e 3624 if (intel_dp->num_sink_rates)
a8f3ef61
SJ		 3625 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
3626 &intel_dp->rate_select, 1);
6aba5b6c
JN		 3627
3628 link_config[0] = 0;
3629 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3630 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3631
3632 DP |= DP_PORT_EN;
1a2eb460 3633
70aff66c
JN		 3634 /* clock recovery */
3635 if (!intel_dp_reset_link_train(intel_dp, &DP,
3636 DP_TRAINING_PATTERN_1 |
3637 DP_LINK_SCRAMBLING_DISABLE)) {
3638 DRM_ERROR("failed to enable link training\n");
3639 return;
3640 }
3641
a4fc5ed6 3642 voltage = 0xff;
cdb0e95b
KP		 3643 voltage_tries = 0;
3644 loop_tries = 0;
a4fc5ed6 3645 for (;;) {
70aff66c 3646 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3647
a7c9655f 3648 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3649 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3650 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3651 break;
93f62dad 3652 }
a4fc5ed6 3653
01916270 3654 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3655 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3656 break;
3657 }
3658
3659 /* Check to see if we've tried the max voltage */
3660 for (i = 0; i < intel_dp->lane_count; i++)
3661 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3662 break;
3b4f819d 3663 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3664 ++loop_tries;
3665 if (loop_tries == 5) {
3def84b3 3666 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3667 break;
3668 }
70aff66c
JN		 3669 intel_dp_reset_link_train(intel_dp, &DP,
3670 DP_TRAINING_PATTERN_1 |
3671 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3672 voltage_tries = 0;
3673 continue;
3674 }
a4fc5ed6 3675
3cf2efb1 3676 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3677 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3678 ++voltage_tries;
b06fbda3 3679 if (voltage_tries == 5) {
3def84b3 3680 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3681 break;
3682 }
3683 } else
3684 voltage_tries = 0;
3685 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3686
70aff66c
JN		 3687 /* Update training set as requested by target */
3688 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3689 DRM_ERROR("failed to update link training\n");
3690 break;
3691 }
a4fc5ed6
KP		 3692 }
3693
33a34e4e
JB		 3694 intel_dp->DP = DP;
3695}
3696
c19b0669 3697void
33a34e4e
JB		 3698intel_dp_complete_link_train(struct intel_dp *intel_dp)
3699{
33a34e4e 3700 bool channel_eq = false;
37f80975 3701 int tries, cr_tries;
33a34e4e 3702 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3703 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3704
3705 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3706 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3707 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3708
a4fc5ed6 3709 /* channel equalization */
70aff66c 3710 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3711 training_pattern |
70aff66c
JN		 3712 DP_LINK_SCRAMBLING_DISABLE)) {
3713 DRM_ERROR("failed to start channel equalization\n");
3714 return;
3715 }
3716
a4fc5ed6 3717 tries = 0;
37f80975 3718 cr_tries = 0;
a4fc5ed6
KP		 3719 channel_eq = false;
3720 for (;;) {
70aff66c 3721 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3722
37f80975
JB		 3723 if (cr_tries > 5) {
3724 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3725 break;
3726 }
3727
a7c9655f 3728 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3729 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3730 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3731 break;
70aff66c 3732 }
a4fc5ed6 3733
37f80975 3734 /* Make sure clock is still ok */
01916270 3735 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3736 intel_dp_start_link_train(intel_dp);
70aff66c 3737 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3738 training_pattern |
70aff66c 3739 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3740 cr_tries++;
3741 continue;
3742 }
3743
1ffdff13 3744 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3745 channel_eq = true;
3746 break;
3747 }
a4fc5ed6 3748
37f80975
JB		 3749 /* Try 5 times, then try clock recovery if that fails */
3750 if (tries > 5) {
37f80975 3751 intel_dp_start_link_train(intel_dp);
70aff66c 3752 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3753 training_pattern |
70aff66c 3754 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3755 tries = 0;
3756 cr_tries++;
3757 continue;
3758 }
a4fc5ed6 3759
70aff66c
JN		 3760 /* Update training set as requested by target */
3761 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3762 DRM_ERROR("failed to update link training\n");
3763 break;
3764 }
3cf2efb1 3765 ++tries;
869184a6 3766 }
3cf2efb1 3767
3ab9c637
ID		 3768 intel_dp_set_idle_link_train(intel_dp);
3769
3770 intel_dp->DP = DP;
3771
d6c0d722 3772 if (channel_eq)
07f42258 3773 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3774
3ab9c637
ID		 3775}
3776
3777void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3778{
70aff66c 3779 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3780 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3781}
3782
3783static void
ea5b213a 3784intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3785{
da63a9f2 3786 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3787 enum port port = intel_dig_port->port;
da63a9f2 3788 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3789 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3790 uint32_t DP = intel_dp->DP;
a4fc5ed6 3791
bc76e320 3792 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3793 return;
3794
0c33d8d7 3795 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3796 return;
3797
28c97730 3798 DRM_DEBUG_KMS("\n");
32f9d658 3799
bc7d38a4 3800 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3801 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3802 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3803 } else {
aad3d14d
VS		 3804 if (IS_CHERRYVIEW(dev))
3805 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3806 else
3807 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3808 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3809 }
fe255d00 3810 POSTING_READ(intel_dp->output_reg);
5eb08b69 3811
493a7081 3812 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3813 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
5bddd17f
EA		 3814 /* Hardware workaround: leaving our transcoder select
3815 * set to transcoder B while it's off will prevent the
3816 * corresponding HDMI output on transcoder A.
3817 *
3818 * Combine this with another hardware workaround:
3819 * transcoder select bit can only be cleared while the
3820 * port is enabled.
3821 */
3822 DP &= ~DP_PIPEB_SELECT;
3823 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3824 POSTING_READ(intel_dp->output_reg);
5bddd17f
EA		 3825 }
3826
832afda6 3827 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3828 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3829 POSTING_READ(intel_dp->output_reg);
f01eca2e 3830 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3831}
3832
26d61aad
KP		 3833static bool
3834intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3835{
a031d709
RV		 3836 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3837 struct drm_device *dev = dig_port->base.base.dev;
3838 struct drm_i915_private *dev_priv = dev->dev_private;
fc0f8e25 3839 uint8_t rev;
a031d709 3840
9d1a1031
JN		 3841 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3842 sizeof(intel_dp->dpcd)) < 0)
edb39244 3843 return false; /* aux transfer failed */
92fd8fd1 3844
a8e98153 3845 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3846
edb39244
AJ		 3847 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3848 return false; /* DPCD not present */
3849
2293bb5c
SK		 3850 /* Check if the panel supports PSR */
3851 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3852 if (is_edp(intel_dp)) {
9d1a1031
JN		 3853 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3854 intel_dp->psr_dpcd,
3855 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3856 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3857 dev_priv->psr.sink_support = true;
50003939 3858 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3859 }
474d1ec4
SJ		 3860
3861 if (INTEL_INFO(dev)->gen >= 9 &&
3862 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3863 uint8_t frame_sync_cap;
3864
3865 dev_priv->psr.sink_support = true;
3866 intel_dp_dpcd_read_wake(&intel_dp->aux,
3867 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3868 &frame_sync_cap, 1);
3869 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3870 /* PSR2 needs frame sync as well */
3871 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3872 DRM_DEBUG_KMS("PSR2 %s on sink",
3873 dev_priv->psr.psr2_support ? "supported" : "not supported");
3874 }
50003939
JN		 3875 }
3876
7809a611 3877 /* Training Pattern 3 support, both source and sink */
06ea66b6 3878 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
7809a611
JN		 3879 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3880 (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
06ea66b6 3881 intel_dp->use_tps3 = true;
f8d8a672 3882 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3883 } else
3884 intel_dp->use_tps3 = false;
3885
fc0f8e25
SJ		 3886 /* Intermediate frequency support */
3887 if (is_edp(intel_dp) &&
3888 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3889 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3890 (rev >= 0x03)) { /* eDp v1.4 or higher */
94ca719e 3891 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3892 int i;
3893
fc0f8e25
SJ		 3894 intel_dp_dpcd_read_wake(&intel_dp->aux,
3895 DP_SUPPORTED_LINK_RATES,
94ca719e
VS		 3896 sink_rates,
3897 sizeof(sink_rates));
ea2d8a42 3898
94ca719e
VS		 3899 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3900 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3901
3902 if (val == 0)
3903 break;
3904
94ca719e 3905 intel_dp->sink_rates[i] = val * 200;
ea2d8a42 3906 }
94ca719e 3907 intel_dp->num_sink_rates = i;
fc0f8e25 3908 }
0336400e
VS		 3909
3910 intel_dp_print_rates(intel_dp);
3911
edb39244
AJ		 3912 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3913 DP_DWN_STRM_PORT_PRESENT))
3914 return true; /* native DP sink */
3915
3916 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3917 return true; /* no per-port downstream info */
3918
9d1a1031
JN		 3919 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3920 intel_dp->downstream_ports,
3921 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3922 return false; /* downstream port status fetch failed */
3923
3924 return true;
92fd8fd1
KP		 3925}
3926
0d198328
AJ		 3927static void
3928intel_dp_probe_oui(struct intel_dp *intel_dp)
3929{
3930 u8 buf[3];
3931
3932 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3933 return;
3934
9d1a1031 3935 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3936 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3937 buf[0], buf[1], buf[2]);
3938
9d1a1031 3939 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3940 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3941 buf[0], buf[1], buf[2]);
3942}
3943
0e32b39c
DA		 3944static bool
3945intel_dp_probe_mst(struct intel_dp *intel_dp)
3946{
3947 u8 buf[1];
3948
3949 if (!intel_dp->can_mst)
3950 return false;
3951
3952 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3953 return false;
3954
0e32b39c
DA		 3955 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3956 if (buf[0] & DP_MST_CAP) {
3957 DRM_DEBUG_KMS("Sink is MST capable\n");
3958 intel_dp->is_mst = true;
3959 } else {
3960 DRM_DEBUG_KMS("Sink is not MST capable\n");
3961 intel_dp->is_mst = false;
3962 }
3963 }
0e32b39c
DA		 3964
3965 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3966 return intel_dp->is_mst;
3967}
3968
d2e216d0
RV		 3969int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3970{
3971 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3972 struct drm_device *dev = intel_dig_port->base.base.dev;
3973 struct intel_crtc *intel_crtc =
3974 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3975 u8 buf;
3976 int test_crc_count;
3977 int attempts = 6;
d2e216d0 3978
ad9dc91b 3979 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3980 return -EIO;
d2e216d0 3981
ad9dc91b 3982 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3983 return -ENOTTY;
3984
1dda5f93
RV		 3985 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3986 return -EIO;
3987
9d1a1031 3988 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3989 buf | DP_TEST_SINK_START) < 0)
bda0381e 3990 return -EIO;
d2e216d0 3991
1dda5f93 3992 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3993 return -EIO;
ad9dc91b 3994 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3995
ad9dc91b 3996 do {
1dda5f93
RV		 3997 if (drm_dp_dpcd_readb(&intel_dp->aux,
3998 DP_TEST_SINK_MISC, &buf) < 0)
3999 return -EIO;
ad9dc91b
RV		 4000 intel_wait_for_vblank(dev, intel_crtc->pipe);
4001 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
4002
4003 if (attempts == 0) {
90bd1f46
DV		 4004 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
4005 return -ETIMEDOUT;
ad9dc91b 4006 }
d2e216d0 4007
9d1a1031 4008 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 4009 return -EIO;
d2e216d0 4010
1dda5f93
RV		 4011 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4012 return -EIO;
4013 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4014 buf & ~DP_TEST_SINK_START) < 0)
4015 return -EIO;
ce31d9f4 4016
d2e216d0
RV		 4017 return 0;
4018}
4019
a60f0e38
JB		 4020static bool
4021intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4022{
9d1a1031
JN		 4023 return intel_dp_dpcd_read_wake(&intel_dp->aux,
4024 DP_DEVICE_SERVICE_IRQ_VECTOR,
4025 sink_irq_vector, 1) == 1;
a60f0e38
JB		 4026}
4027
0e32b39c
DA		 4028static bool
4029intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4030{
4031 int ret;
4032
4033 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4034 DP_SINK_COUNT_ESI,
4035 sink_irq_vector, 14);
4036 if (ret != 14)
4037 return false;
4038
4039 return true;
4040}
4041
c5d5ab7a
TP		 4042static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4043{
4044 uint8_t test_result = DP_TEST_ACK;
4045 return test_result;
4046}
4047
4048static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4049{
4050 uint8_t test_result = DP_TEST_NAK;
4051 return test_result;
4052}
4053
4054static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4055{
4056 uint8_t test_result = DP_TEST_NAK;
4057 return test_result;
4058}
4059
4060static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 4061{
c5d5ab7a
TP		 4062 uint8_t test_result = DP_TEST_NAK;
4063 return test_result;
4064}
4065
4066static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4067{
4068 uint8_t response = DP_TEST_NAK;
4069 uint8_t rxdata = 0;
4070 int status = 0;
4071
4072 intel_dp->compliance_test_type = 0;
4073 intel_dp->aux.i2c_nack_count = 0;
4074 intel_dp->aux.i2c_defer_count = 0;
4075
4076 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4077 if (status <= 0) {
4078 DRM_DEBUG_KMS("Could not read test request from sink\n");
4079 goto update_status;
4080 }
4081
4082 switch (rxdata) {
4083 case DP_TEST_LINK_TRAINING:
4084 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4085 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4086 response = intel_dp_autotest_link_training(intel_dp);
4087 break;
4088 case DP_TEST_LINK_VIDEO_PATTERN:
4089 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4090 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4091 response = intel_dp_autotest_video_pattern(intel_dp);
4092 break;
4093 case DP_TEST_LINK_EDID_READ:
4094 DRM_DEBUG_KMS("EDID test requested\n");
4095 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4096 response = intel_dp_autotest_edid(intel_dp);
4097 break;
4098 case DP_TEST_LINK_PHY_TEST_PATTERN:
4099 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4100 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4101 response = intel_dp_autotest_phy_pattern(intel_dp);
4102 break;
4103 default:
4104 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4105 break;
4106 }
4107
4108update_status:
4109 status = drm_dp_dpcd_write(&intel_dp->aux,
4110 DP_TEST_RESPONSE,
4111 &response, 1);
4112 if (status <= 0)
4113 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 4114}
4115
0e32b39c
DA		 4116static int
4117intel_dp_check_mst_status(struct intel_dp *intel_dp)
4118{
4119 bool bret;
4120
4121 if (intel_dp->is_mst) {
4122 u8 esi[16] = { 0 };
4123 int ret = 0;
4124 int retry;
4125 bool handled;
4126 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4127go_again:
4128 if (bret == true) {
4129
4130 /* check link status - esi[10] = 0x200c */
4131 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4132 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4133 intel_dp_start_link_train(intel_dp);
4134 intel_dp_complete_link_train(intel_dp);
4135 intel_dp_stop_link_train(intel_dp);
4136 }
4137
6f34cc39 4138 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 4139 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4140
4141 if (handled) {
4142 for (retry = 0; retry < 3; retry++) {
4143 int wret;
4144 wret = drm_dp_dpcd_write(&intel_dp->aux,
4145 DP_SINK_COUNT_ESI+1,
4146 &esi[1], 3);
4147 if (wret == 3) {
4148 break;
4149 }
4150 }
4151
4152 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4153 if (bret == true) {
6f34cc39 4154 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 4155 goto go_again;
4156 }
4157 } else
4158 ret = 0;
4159
4160 return ret;
4161 } else {
4162 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4163 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4164 intel_dp->is_mst = false;
4165 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4166 /* send a hotplug event */
4167 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4168 }
4169 }
4170 return -EINVAL;
4171}
4172
a4fc5ed6
KP		 4173/*
4174 * According to DP spec
4175 * 5.1.2:
4176 * 1. Read DPCD
4177 * 2. Configure link according to Receiver Capabilities
4178 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4179 * 4. Check link status on receipt of hot-plug interrupt
4180 */
a5146200 4181static void
ea5b213a 4182intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4183{
5b215bcf 4184 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4185 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4186 u8 sink_irq_vector;
93f62dad 4187 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4188
5b215bcf
DA		 4189 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4190
da63a9f2 4191 if (!intel_encoder->connectors_active)
d2b996ac 4192 return;
59cd09e1 4193
da63a9f2 4194 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4195 return;
4196
1a125d8a
ID		 4197 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4198 return;
4199
92fd8fd1 4200 /* Try to read receiver status if the link appears to be up */
93f62dad 4201 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4202 return;
4203 }
4204
92fd8fd1 4205 /* Now read the DPCD to see if it's actually running */
26d61aad 4206 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4207 return;
4208 }
4209
a60f0e38
JB		 4210 /* Try to read the source of the interrupt */
4211 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4212 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4213 /* Clear interrupt source */
9d1a1031
JN		 4214 drm_dp_dpcd_writeb(&intel_dp->aux,
4215 DP_DEVICE_SERVICE_IRQ_VECTOR,
4216 sink_irq_vector);
a60f0e38
JB		 4217
4218 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4219 intel_dp_handle_test_request(intel_dp);
4220 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4221 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4222 }
4223
1ffdff13 4224 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4225 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4226 intel_encoder->base.name);
33a34e4e
JB		 4227 intel_dp_start_link_train(intel_dp);
4228 intel_dp_complete_link_train(intel_dp);
3ab9c637 4229 intel_dp_stop_link_train(intel_dp);
33a34e4e 4230 }
a4fc5ed6 4231}
a4fc5ed6 4232
caf9ab24 4233/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4234static enum drm_connector_status
26d61aad 4235intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4236{
caf9ab24 4237 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4238 uint8_t type;
4239
4240 if (!intel_dp_get_dpcd(intel_dp))
4241 return connector_status_disconnected;
4242
4243 /* if there's no downstream port, we're done */
4244 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4245 return connector_status_connected;
caf9ab24
AJ		 4246
4247 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4248 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4249 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4250 uint8_t reg;
9d1a1031
JN		 4251
4252 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4253 &reg, 1) < 0)
caf9ab24 4254 return connector_status_unknown;
9d1a1031 4255
23235177
AJ		 4256 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4257 : connector_status_disconnected;
caf9ab24
AJ		 4258 }
4259
4260 /* If no HPD, poke DDC gently */
0b99836f 4261 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4262 return connector_status_connected;
caf9ab24
AJ		 4263
4264 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4265 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4266 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4267 if (type == DP_DS_PORT_TYPE_VGA ||
4268 type == DP_DS_PORT_TYPE_NON_EDID)
4269 return connector_status_unknown;
4270 } else {
4271 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4272 DP_DWN_STRM_PORT_TYPE_MASK;
4273 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4274 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4275 return connector_status_unknown;
4276 }
caf9ab24
AJ		 4277
4278 /* Anything else is out of spec, warn and ignore */
4279 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4280 return connector_status_disconnected;
71ba9000
AJ		 4281}
4282
d410b56d
CW		 4283static enum drm_connector_status
4284edp_detect(struct intel_dp *intel_dp)
4285{
4286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4287 enum drm_connector_status status;
4288
4289 status = intel_panel_detect(dev);
4290 if (status == connector_status_unknown)
4291 status = connector_status_connected;
4292
4293 return status;
4294}
4295
5eb08b69 4296static enum drm_connector_status
a9756bb5 4297ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4298{
30add22d 4299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4300 struct drm_i915_private *dev_priv = dev->dev_private;
4301 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4302
1b469639
DL		 4303 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4304 return connector_status_disconnected;
4305
26d61aad 4306 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4307}
4308
2a592bec
DA		 4309static int g4x_digital_port_connected(struct drm_device *dev,
4310 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4311{
a4fc5ed6 4312 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4313 uint32_t bit;
5eb08b69 4314
232a6ee9
TP		 4315 if (IS_VALLEYVIEW(dev)) {
4316 switch (intel_dig_port->port) {
4317 case PORT_B:
4318 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4319 break;
4320 case PORT_C:
4321 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4322 break;
4323 case PORT_D:
4324 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4325 break;
4326 default:
2a592bec 4327 return -EINVAL;
232a6ee9
TP		 4328 }
4329 } else {
4330 switch (intel_dig_port->port) {
4331 case PORT_B:
4332 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4333 break;
4334 case PORT_C:
4335 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4336 break;
4337 case PORT_D:
4338 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4339 break;
4340 default:
2a592bec 4341 return -EINVAL;
232a6ee9 4342 }
a4fc5ed6
KP		 4343 }
4344
10f76a38 4345 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4346 return 0;
4347 return 1;
4348}
4349
4350static enum drm_connector_status
4351g4x_dp_detect(struct intel_dp *intel_dp)
4352{
4353 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4354 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4355 int ret;
4356
4357 /* Can't disconnect eDP, but you can close the lid... */
4358 if (is_edp(intel_dp)) {
4359 enum drm_connector_status status;
4360
4361 status = intel_panel_detect(dev);
4362 if (status == connector_status_unknown)
4363 status = connector_status_connected;
4364 return status;
4365 }
4366
4367 ret = g4x_digital_port_connected(dev, intel_dig_port);
4368 if (ret == -EINVAL)
4369 return connector_status_unknown;
4370 else if (ret == 0)
a4fc5ed6
KP		 4371 return connector_status_disconnected;
4372
26d61aad 4373 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4374}
4375
8c241fef 4376static struct edid *
beb60608 4377intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4378{
beb60608 4379 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4380
9cd300e0
JN		 4381 /* use cached edid if we have one */
4382 if (intel_connector->edid) {
9cd300e0
JN		 4383 /* invalid edid */
4384 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4385 return NULL;
4386
55e9edeb 4387 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4388 } else
4389 return drm_get_edid(&intel_connector->base,
4390 &intel_dp->aux.ddc);
4391}
8c241fef 4392
beb60608
CW		 4393static void
4394intel_dp_set_edid(struct intel_dp *intel_dp)
4395{
4396 struct intel_connector *intel_connector = intel_dp->attached_connector;
4397 struct edid *edid;
8c241fef 4398
beb60608
CW		 4399 edid = intel_dp_get_edid(intel_dp);
4400 intel_connector->detect_edid = edid;
4401
4402 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4403 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4404 else
4405 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4406}
4407
beb60608
CW		 4408static void
4409intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4410{
beb60608 4411 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4412
beb60608
CW		 4413 kfree(intel_connector->detect_edid);
4414 intel_connector->detect_edid = NULL;
9cd300e0 4415
beb60608
CW		 4416 intel_dp->has_audio = false;
4417}
d6f24d0f 4418
beb60608
CW		 4419static enum intel_display_power_domain
4420intel_dp_power_get(struct intel_dp *dp)
4421{
4422 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4423 enum intel_display_power_domain power_domain;
4424
4425 power_domain = intel_display_port_power_domain(encoder);
4426 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4427
4428 return power_domain;
4429}
d6f24d0f 4430
beb60608
CW		 4431static void
4432intel_dp_power_put(struct intel_dp *dp,
4433 enum intel_display_power_domain power_domain)
4434{
4435 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4436 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4437}
4438
a9756bb5
ZW		 4439static enum drm_connector_status
4440intel_dp_detect(struct drm_connector *connector, bool force)
4441{
4442 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4443 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4444 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4445 struct drm_device *dev = connector->dev;
a9756bb5 4446 enum drm_connector_status status;
671dedd2 4447 enum intel_display_power_domain power_domain;
0e32b39c 4448 bool ret;
a9756bb5 4449
164c8598 4450 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4451 connector->base.id, connector->name);
beb60608 4452 intel_dp_unset_edid(intel_dp);
164c8598 4453
0e32b39c
DA		 4454 if (intel_dp->is_mst) {
4455 /* MST devices are disconnected from a monitor POV */
4456 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4457 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4458 return connector_status_disconnected;
0e32b39c
DA		 4459 }
4460
beb60608 4461 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4462
d410b56d
CW		 4463 /* Can't disconnect eDP, but you can close the lid... */
4464 if (is_edp(intel_dp))
4465 status = edp_detect(intel_dp);
4466 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4467 status = ironlake_dp_detect(intel_dp);
4468 else
4469 status = g4x_dp_detect(intel_dp);
4470 if (status != connector_status_connected)
c8c8fb33 4471 goto out;
a9756bb5 4472
0d198328
AJ		 4473 intel_dp_probe_oui(intel_dp);
4474
0e32b39c
DA		 4475 ret = intel_dp_probe_mst(intel_dp);
4476 if (ret) {
4477 /* if we are in MST mode then this connector
4478 won't appear connected or have anything with EDID on it */
4479 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4480 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4481 status = connector_status_disconnected;
4482 goto out;
4483 }
4484
beb60608 4485 intel_dp_set_edid(intel_dp);
a9756bb5 4486
d63885da
PZ		 4487 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4488 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4489 status = connector_status_connected;
4490
4491out:
beb60608 4492 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4493 return status;
a4fc5ed6
KP		 4494}
4495
beb60608
CW		 4496static void
4497intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4498{
df0e9248 4499 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4500 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4501 enum intel_display_power_domain power_domain;
a4fc5ed6 4502
beb60608
CW		 4503 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4504 connector->base.id, connector->name);
4505 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4506
beb60608
CW		 4507 if (connector->status != connector_status_connected)
4508 return;
671dedd2 4509
beb60608
CW		 4510 power_domain = intel_dp_power_get(intel_dp);
4511
4512 intel_dp_set_edid(intel_dp);
4513
4514 intel_dp_power_put(intel_dp, power_domain);
4515
4516 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4517 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4518}
4519
4520static int intel_dp_get_modes(struct drm_connector *connector)
4521{
4522 struct intel_connector *intel_connector = to_intel_connector(connector);
4523 struct edid *edid;
4524
4525 edid = intel_connector->detect_edid;
4526 if (edid) {
4527 int ret = intel_connector_update_modes(connector, edid);
4528 if (ret)
4529 return ret;
4530 }
32f9d658 4531
f8779fda 4532 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4533 if (is_edp(intel_attached_dp(connector)) &&
4534 intel_connector->panel.fixed_mode) {
f8779fda 4535 struct drm_display_mode *mode;
beb60608
CW		 4536
4537 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4538 intel_connector->panel.fixed_mode);
f8779fda 4539 if (mode) {
32f9d658
ZW		 4540 drm_mode_probed_add(connector, mode);
4541 return 1;
4542 }
4543 }
beb60608 4544
32f9d658 4545 return 0;
a4fc5ed6
KP		 4546}
4547
1aad7ac0
CW		 4548static bool
4549intel_dp_detect_audio(struct drm_connector *connector)
4550{
1aad7ac0 4551 bool has_audio = false;
beb60608 4552 struct edid *edid;
1aad7ac0 4553
beb60608
CW		 4554 edid = to_intel_connector(connector)->detect_edid;
4555 if (edid)
1aad7ac0 4556 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4557
1aad7ac0
CW		 4558 return has_audio;
4559}
4560
f684960e
CW		 4561static int
4562intel_dp_set_property(struct drm_connector *connector,
4563 struct drm_property *property,
4564 uint64_t val)
4565{
e953fd7b 4566 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4567 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4568 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4569 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4570 int ret;
4571
662595df 4572 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4573 if (ret)
4574 return ret;
4575
3f43c48d 4576 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4577 int i = val;
4578 bool has_audio;
4579
4580 if (i == intel_dp->force_audio)
f684960e
CW		 4581 return 0;
4582
1aad7ac0 4583 intel_dp->force_audio = i;
f684960e 4584
c3e5f67b 4585 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4586 has_audio = intel_dp_detect_audio(connector);
4587 else
c3e5f67b 4588 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4589
4590 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4591 return 0;
4592
1aad7ac0 4593 intel_dp->has_audio = has_audio;
f684960e
CW		 4594 goto done;
4595 }
4596
e953fd7b 4597 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4598 bool old_auto = intel_dp->color_range_auto;
4599 uint32_t old_range = intel_dp->color_range;
4600
55bc60db
VS		 4601 switch (val) {
4602 case INTEL_BROADCAST_RGB_AUTO:
4603 intel_dp->color_range_auto = true;
4604 break;
4605 case INTEL_BROADCAST_RGB_FULL:
4606 intel_dp->color_range_auto = false;
4607 intel_dp->color_range = 0;
4608 break;
4609 case INTEL_BROADCAST_RGB_LIMITED:
4610 intel_dp->color_range_auto = false;
4611 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4612 break;
4613 default:
4614 return -EINVAL;
4615 }
ae4edb80
DV		 4616
4617 if (old_auto == intel_dp->color_range_auto &&
4618 old_range == intel_dp->color_range)
4619 return 0;
4620
e953fd7b
CW		 4621 goto done;
4622 }
4623
53b41837
YN		 4624 if (is_edp(intel_dp) &&
4625 property == connector->dev->mode_config.scaling_mode_property) {
4626 if (val == DRM_MODE_SCALE_NONE) {
4627 DRM_DEBUG_KMS("no scaling not supported\n");
4628 return -EINVAL;
4629 }
4630
4631 if (intel_connector->panel.fitting_mode == val) {
4632 /* the eDP scaling property is not changed */
4633 return 0;
4634 }
4635 intel_connector->panel.fitting_mode = val;
4636
4637 goto done;
4638 }
4639
f684960e
CW		 4640 return -EINVAL;
4641
4642done:
c0c36b94
CW		 4643 if (intel_encoder->base.crtc)
4644 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4645
4646 return 0;
4647}
4648
a4fc5ed6 4649static void
73845adf 4650intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4651{
1d508706 4652 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4653
10e972d3 4654 kfree(intel_connector->detect_edid);
beb60608 4655
9cd300e0
JN		 4656 if (!IS_ERR_OR_NULL(intel_connector->edid))
4657 kfree(intel_connector->edid);
4658
acd8db10
PZ		 4659 /* Can't call is_edp() since the encoder may have been destroyed
4660 * already. */
4661 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4662 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4663
a4fc5ed6 4664 drm_connector_cleanup(connector);
55f78c43 4665 kfree(connector);
a4fc5ed6
KP		 4666}
4667
00c09d70 4668void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4669{
da63a9f2
PZ		 4670 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4671 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4672
4f71d0cb 4673 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4674 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4675 if (is_edp(intel_dp)) {
4676 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4677 /*
4678 * vdd might still be enabled do to the delayed vdd off.
4679 * Make sure vdd is actually turned off here.
4680 */
773538e8 4681 pps_lock(intel_dp);
4be73780 4682 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4683 pps_unlock(intel_dp);
4684
01527b31
CT		 4685 if (intel_dp->edp_notifier.notifier_call) {
4686 unregister_reboot_notifier(&intel_dp->edp_notifier);
4687 intel_dp->edp_notifier.notifier_call = NULL;
4688 }
bd943159 4689 }
c8bd0e49 4690 drm_encoder_cleanup(encoder);
da63a9f2 4691 kfree(intel_dig_port);
24d05927
DV		 4692}
4693
07f9cd0b
ID		 4694static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4695{
4696 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4697
4698 if (!is_edp(intel_dp))
4699 return;
4700
951468f3
VS		 4701 /*
4702 * vdd might still be enabled do to the delayed vdd off.
4703 * Make sure vdd is actually turned off here.
4704 */
afa4e53a 4705 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4706 pps_lock(intel_dp);
07f9cd0b 4707 edp_panel_vdd_off_sync(intel_dp);
773538e8 4708 pps_unlock(intel_dp);
07f9cd0b
ID		 4709}
4710
49e6bc51
VS		 4711static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4712{
4713 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4714 struct drm_device *dev = intel_dig_port->base.base.dev;
4715 struct drm_i915_private *dev_priv = dev->dev_private;
4716 enum intel_display_power_domain power_domain;
4717
4718 lockdep_assert_held(&dev_priv->pps_mutex);
4719
4720 if (!edp_have_panel_vdd(intel_dp))
4721 return;
4722
4723 /*
4724 * The VDD bit needs a power domain reference, so if the bit is
4725 * already enabled when we boot or resume, grab this reference and
4726 * schedule a vdd off, so we don't hold on to the reference
4727 * indefinitely.
4728 */
4729 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4730 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4731 intel_display_power_get(dev_priv, power_domain);
4732
4733 edp_panel_vdd_schedule_off(intel_dp);
4734}
4735
6d93c0c4
ID		 4736static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4737{
49e6bc51
VS		 4738 struct intel_dp *intel_dp;
4739
4740 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4741 return;
4742
4743 intel_dp = enc_to_intel_dp(encoder);
4744
4745 pps_lock(intel_dp);
4746
4747 /*
4748 * Read out the current power sequencer assignment,
4749 * in case the BIOS did something with it.
4750 */
4751 if (IS_VALLEYVIEW(encoder->dev))
4752 vlv_initial_power_sequencer_setup(intel_dp);
4753
4754 intel_edp_panel_vdd_sanitize(intel_dp);
4755
4756 pps_unlock(intel_dp);
6d93c0c4
ID		 4757}
4758
a4fc5ed6 4759static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4760 .dpms = intel_connector_dpms,
a4fc5ed6 4761 .detect = intel_dp_detect,
beb60608 4762 .force = intel_dp_force,
a4fc5ed6 4763 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4764 .set_property = intel_dp_set_property,
2545e4a6 4765 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4766 .destroy = intel_dp_connector_destroy,
c6f95f27 4767 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4768 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4769};
4770
4771static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4772 .get_modes = intel_dp_get_modes,
4773 .mode_valid = intel_dp_mode_valid,
df0e9248 4774 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4775};
4776
a4fc5ed6 4777static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4778 .reset = intel_dp_encoder_reset,
24d05927 4779 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4780};
4781
0e32b39c 4782void
21d40d37 4783intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4784{
0e32b39c 4785 return;
c8110e52 4786}
6207937d 4787
b2c5c181 4788enum irqreturn
13cf5504
DA		 4789intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4790{
4791 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4792 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4793 struct drm_device *dev = intel_dig_port->base.base.dev;
4794 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4795 enum intel_display_power_domain power_domain;
b2c5c181 4796 enum irqreturn ret = IRQ_NONE;
1c767b33 4797
0e32b39c
DA		 4798 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4799 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4800
7a7f84cc
VS		 4801 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4802 /*
4803 * vdd off can generate a long pulse on eDP which
4804 * would require vdd on to handle it, and thus we
4805 * would end up in an endless cycle of
4806 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4807 */
4808 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4809 port_name(intel_dig_port->port));
a8b3d52f 4810 return IRQ_HANDLED;
7a7f84cc
VS		 4811 }
4812
26fbb774
VS		 4813 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4814 port_name(intel_dig_port->port),
0e32b39c 4815 long_hpd ? "long" : "short");
13cf5504 4816
1c767b33
ID		 4817 power_domain = intel_display_port_power_domain(intel_encoder);
4818 intel_display_power_get(dev_priv, power_domain);
4819
0e32b39c 4820 if (long_hpd) {
2a592bec
DA		 4821
4822 if (HAS_PCH_SPLIT(dev)) {
4823 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4824 goto mst_fail;
4825 } else {
4826 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4827 goto mst_fail;
4828 }
0e32b39c
DA		 4829
4830 if (!intel_dp_get_dpcd(intel_dp)) {
4831 goto mst_fail;
4832 }
4833
4834 intel_dp_probe_oui(intel_dp);
4835
4836 if (!intel_dp_probe_mst(intel_dp))
4837 goto mst_fail;
4838
4839 } else {
4840 if (intel_dp->is_mst) {
1c767b33 4841 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4842 goto mst_fail;
4843 }
4844
4845 if (!intel_dp->is_mst) {
4846 /*
4847 * we'll check the link status via the normal hot plug path later -
4848 * but for short hpds we should check it now
4849 */
5b215bcf 4850 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4851 intel_dp_check_link_status(intel_dp);
5b215bcf 4852 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4853 }
4854 }
b2c5c181
DV		 4855
4856 ret = IRQ_HANDLED;
4857
1c767b33 4858 goto put_power;
0e32b39c
DA		 4859mst_fail:
4860 /* if we were in MST mode, and device is not there get out of MST mode */
4861 if (intel_dp->is_mst) {
4862 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4863 intel_dp->is_mst = false;
4864 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4865 }
1c767b33
ID		 4866put_power:
4867 intel_display_power_put(dev_priv, power_domain);
4868
4869 return ret;
13cf5504
DA		 4870}
4871
e3421a18
ZW		 4872/* Return which DP Port should be selected for Transcoder DP control */
4873int
0206e353 4874intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4875{
4876 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4877 struct intel_encoder *intel_encoder;
4878 struct intel_dp *intel_dp;
e3421a18 4879
fa90ecef
PZ		 4880 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4881 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4882
fa90ecef
PZ		 4883 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4884 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4885 return intel_dp->output_reg;
e3421a18 4886 }
ea5b213a 4887
e3421a18
ZW		 4888 return -1;
4889}
4890
36e83a18 4891/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4892bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4893{
4894 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4895 union child_device_config *p_child;
36e83a18 4896 int i;
5d8a7752
VS		 4897 static const short port_mapping[] = {
4898 [PORT_B] = PORT_IDPB,
4899 [PORT_C] = PORT_IDPC,
4900 [PORT_D] = PORT_IDPD,
4901 };
36e83a18 4902
3b32a35b
VS		 4903 if (port == PORT_A)
4904 return true;
4905
41aa3448 4906 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4907 return false;
4908
41aa3448
RV		 4909 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4910 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4911
5d8a7752 4912 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4913 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4914 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4915 return true;
4916 }
4917 return false;
4918}
4919
0e32b39c 4920void
f684960e
CW		 4921intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4922{
53b41837
YN		 4923 struct intel_connector *intel_connector = to_intel_connector(connector);
4924
3f43c48d 4925 intel_attach_force_audio_property(connector);
e953fd7b 4926 intel_attach_broadcast_rgb_property(connector);
55bc60db 4927 intel_dp->color_range_auto = true;
53b41837
YN		 4928
4929 if (is_edp(intel_dp)) {
4930 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4931 drm_object_attach_property(
4932 &connector->base,
53b41837 4933 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4934 DRM_MODE_SCALE_ASPECT);
4935 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4936 }
f684960e
CW		 4937}
4938
dada1a9f
ID		 4939static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4940{
4941 intel_dp->last_power_cycle = jiffies;
4942 intel_dp->last_power_on = jiffies;
4943 intel_dp->last_backlight_off = jiffies;
4944}
4945
67a54566
DV		 4946static void
4947intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4948 struct intel_dp *intel_dp)
67a54566
DV		 4949{
4950 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4951 struct edp_power_seq cur, vbt, spec,
4952 *final = &intel_dp->pps_delays;
67a54566 4953 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4954 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4955
e39b999a
VS		 4956 lockdep_assert_held(&dev_priv->pps_mutex);
4957
81ddbc69
VS		 4958 /* already initialized? */
4959 if (final->t11_t12 != 0)
4960 return;
4961
453c5420 4962 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4963 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4964 pp_on_reg = PCH_PP_ON_DELAYS;
4965 pp_off_reg = PCH_PP_OFF_DELAYS;
4966 pp_div_reg = PCH_PP_DIVISOR;
4967 } else {
bf13e81b
JN		 4968 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4969
4970 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4971 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4972 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4973 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4974 }
67a54566
DV		 4975
4976 /* Workaround: Need to write PP_CONTROL with the unlock key as
4977 * the very first thing. */
453c5420 4978 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4979 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4980
453c5420
JB		 4981 pp_on = I915_READ(pp_on_reg);
4982 pp_off = I915_READ(pp_off_reg);
4983 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4984
4985 /* Pull timing values out of registers */
4986 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4987 PANEL_POWER_UP_DELAY_SHIFT;
4988
4989 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4990 PANEL_LIGHT_ON_DELAY_SHIFT;
4991
4992 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4993 PANEL_LIGHT_OFF_DELAY_SHIFT;
4994
4995 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4996 PANEL_POWER_DOWN_DELAY_SHIFT;
4997
4998 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4999 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5000
5001 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5002 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5003
41aa3448 5004 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 5005
5006 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5007 * our hw here, which are all in 100usec. */
5008 spec.t1_t3 = 210 * 10;
5009 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5010 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5011 spec.t10 = 500 * 10;
5012 /* This one is special and actually in units of 100ms, but zero
5013 * based in the hw (so we need to add 100 ms). But the sw vbt
5014 * table multiplies it with 1000 to make it in units of 100usec,
5015 * too. */
5016 spec.t11_t12 = (510 + 100) * 10;
5017
5018 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5019 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5020
5021 /* Use the max of the register settings and vbt. If both are
5022 * unset, fall back to the spec limits. */
36b5f425 5023#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 5024 spec.field : \
5025 max(cur.field, vbt.field))
5026 assign_final(t1_t3);
5027 assign_final(t8);
5028 assign_final(t9);
5029 assign_final(t10);
5030 assign_final(t11_t12);
5031#undef assign_final
5032
36b5f425 5033#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 5034 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5035 intel_dp->backlight_on_delay = get_delay(t8);
5036 intel_dp->backlight_off_delay = get_delay(t9);
5037 intel_dp->panel_power_down_delay = get_delay(t10);
5038 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5039#undef get_delay
5040
f30d26e4
JN		 5041 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5042 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5043 intel_dp->panel_power_cycle_delay);
5044
5045 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5046 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 5047}
5048
5049static void
5050intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 5051 struct intel_dp *intel_dp)
f30d26e4
JN		 5052{
5053 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 5054 u32 pp_on, pp_off, pp_div, port_sel = 0;
5055 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
5056 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 5057 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 5058 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 5059
e39b999a 5060 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 5061
5062 if (HAS_PCH_SPLIT(dev)) {
5063 pp_on_reg = PCH_PP_ON_DELAYS;
5064 pp_off_reg = PCH_PP_OFF_DELAYS;
5065 pp_div_reg = PCH_PP_DIVISOR;
5066 } else {
bf13e81b
JN		 5067 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5068
5069 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5070 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5071 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 5072 }
5073
b2f19d1a
PZ		 5074 /*
5075 * And finally store the new values in the power sequencer. The
5076 * backlight delays are set to 1 because we do manual waits on them. For
5077 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5078 * we'll end up waiting for the backlight off delay twice: once when we
5079 * do the manual sleep, and once when we disable the panel and wait for
5080 * the PP_STATUS bit to become zero.
5081 */
f30d26e4 5082 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 5083 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5084 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5085 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5086 /* Compute the divisor for the pp clock, simply match the Bspec
5087 * formula. */
453c5420 5088 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 5089 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 5090 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5091
5092 /* Haswell doesn't have any port selection bits for the panel
5093 * power sequencer any more. */
bc7d38a4 5094 if (IS_VALLEYVIEW(dev)) {
ad933b56 5095 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 5096 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 5097 if (port == PORT_A)
a24c144c 5098 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5099 else
a24c144c 5100 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5101 }
5102
453c5420
JB		 5103 pp_on |= port_sel;
5104
5105 I915_WRITE(pp_on_reg, pp_on);
5106 I915_WRITE(pp_off_reg, pp_off);
5107 I915_WRITE(pp_div_reg, pp_div);
67a54566 5108
67a54566 5109 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 5110 I915_READ(pp_on_reg),
5111 I915_READ(pp_off_reg),
5112 I915_READ(pp_div_reg));
f684960e
CW		 5113}
5114
b33a2815
VK		 5115/**
5116 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5117 * @dev: DRM device
5118 * @refresh_rate: RR to be programmed
5119 *
5120 * This function gets called when refresh rate (RR) has to be changed from
5121 * one frequency to another. Switches can be between high and low RR
5122 * supported by the panel or to any other RR based on media playback (in
5123 * this case, RR value needs to be passed from user space).
5124 *
5125 * The caller of this function needs to take a lock on dev_priv->drrs.
5126 */
96178eeb 5127static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 5128{
5129 struct drm_i915_private *dev_priv = dev->dev_private;
5130 struct intel_encoder *encoder;
96178eeb
VK		 5131 struct intel_digital_port *dig_port = NULL;
5132 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 5133 struct intel_crtc_state *config = NULL;
439d7ac0 5134 struct intel_crtc *intel_crtc = NULL;
439d7ac0 5135 u32 reg, val;
96178eeb 5136 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5137
5138 if (refresh_rate <= 0) {
5139 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5140 return;
5141 }
5142
96178eeb
VK		 5143 if (intel_dp == NULL) {
5144 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5145 return;
5146 }
5147
1fcc9d1c 5148 /*
e4d59f6b
RV		 5149 * FIXME: This needs proper synchronization with psr state for some
5150 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5151 */
439d7ac0 5152
96178eeb
VK		 5153 dig_port = dp_to_dig_port(intel_dp);
5154 encoder = &dig_port->base;
723f9aab 5155 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5156
5157 if (!intel_crtc) {
5158 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5159 return;
5160 }
5161
6e3c9717 5162 config = intel_crtc->config;
439d7ac0 5163
96178eeb 5164 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5165 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5166 return;
5167 }
5168
96178eeb
VK		 5169 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5170 refresh_rate)
439d7ac0
PB		 5171 index = DRRS_LOW_RR;
5172
96178eeb 5173 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5174 DRM_DEBUG_KMS(
5175 "DRRS requested for previously set RR...ignoring\n");
5176 return;
5177 }
5178
5179 if (!intel_crtc->active) {
5180 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5181 return;
5182 }
5183
44395bfe 5184 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5185 switch (index) {
5186 case DRRS_HIGH_RR:
5187 intel_dp_set_m_n(intel_crtc, M1_N1);
5188 break;
5189 case DRRS_LOW_RR:
5190 intel_dp_set_m_n(intel_crtc, M2_N2);
5191 break;
5192 case DRRS_MAX_RR:
5193 default:
5194 DRM_ERROR("Unsupported refreshrate type\n");
5195 }
5196 } else if (INTEL_INFO(dev)->gen > 6) {
6e3c9717 5197 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
439d7ac0 5198 val = I915_READ(reg);
a4c30b1d 5199
439d7ac0 5200 if (index > DRRS_HIGH_RR) {
6fa7aec1
VK		 5201 if (IS_VALLEYVIEW(dev))
5202 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5203 else
5204 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5205 } else {
6fa7aec1
VK		 5206 if (IS_VALLEYVIEW(dev))
5207 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5208 else
5209 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5210 }
5211 I915_WRITE(reg, val);
5212 }
5213
4e9ac947
VK		 5214 dev_priv->drrs.refresh_rate_type = index;
5215
5216 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5217}
5218
b33a2815
VK		 5219/**
5220 * intel_edp_drrs_enable - init drrs struct if supported
5221 * @intel_dp: DP struct
5222 *
5223 * Initializes frontbuffer_bits and drrs.dp
5224 */
c395578e
VK		 5225void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5226{
5227 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5228 struct drm_i915_private *dev_priv = dev->dev_private;
5229 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5230 struct drm_crtc *crtc = dig_port->base.base.crtc;
5231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5232
5233 if (!intel_crtc->config->has_drrs) {
5234 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5235 return;
5236 }
5237
5238 mutex_lock(&dev_priv->drrs.mutex);
5239 if (WARN_ON(dev_priv->drrs.dp)) {
5240 DRM_ERROR("DRRS already enabled\n");
5241 goto unlock;
5242 }
5243
5244 dev_priv->drrs.busy_frontbuffer_bits = 0;
5245
5246 dev_priv->drrs.dp = intel_dp;
5247
5248unlock:
5249 mutex_unlock(&dev_priv->drrs.mutex);
5250}
5251
b33a2815
VK		 5252/**
5253 * intel_edp_drrs_disable - Disable DRRS
5254 * @intel_dp: DP struct
5255 *
5256 */
c395578e
VK		 5257void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5258{
5259 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5260 struct drm_i915_private *dev_priv = dev->dev_private;
5261 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5262 struct drm_crtc *crtc = dig_port->base.base.crtc;
5263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5264
5265 if (!intel_crtc->config->has_drrs)
5266 return;
5267
5268 mutex_lock(&dev_priv->drrs.mutex);
5269 if (!dev_priv->drrs.dp) {
5270 mutex_unlock(&dev_priv->drrs.mutex);
5271 return;
5272 }
5273
5274 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5275 intel_dp_set_drrs_state(dev_priv->dev,
5276 intel_dp->attached_connector->panel.
5277 fixed_mode->vrefresh);
5278
5279 dev_priv->drrs.dp = NULL;
5280 mutex_unlock(&dev_priv->drrs.mutex);
5281
5282 cancel_delayed_work_sync(&dev_priv->drrs.work);
5283}
5284
4e9ac947
VK		 5285static void intel_edp_drrs_downclock_work(struct work_struct *work)
5286{
5287 struct drm_i915_private *dev_priv =
5288 container_of(work, typeof(*dev_priv), drrs.work.work);
5289 struct intel_dp *intel_dp;
5290
5291 mutex_lock(&dev_priv->drrs.mutex);
5292
5293 intel_dp = dev_priv->drrs.dp;
5294
5295 if (!intel_dp)
5296 goto unlock;
5297
439d7ac0 5298 /*
4e9ac947
VK		 5299 * The delayed work can race with an invalidate hence we need to
5300 * recheck.
439d7ac0
PB		 5301 */
5302
4e9ac947
VK		 5303 if (dev_priv->drrs.busy_frontbuffer_bits)
5304 goto unlock;
439d7ac0 5305
4e9ac947
VK		 5306 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5307 intel_dp_set_drrs_state(dev_priv->dev,
5308 intel_dp->attached_connector->panel.
5309 downclock_mode->vrefresh);
439d7ac0 5310
4e9ac947 5311unlock:
439d7ac0 5312
4e9ac947 5313 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5314}
5315
b33a2815
VK		 5316/**
5317 * intel_edp_drrs_invalidate - Invalidate DRRS
5318 * @dev: DRM device
5319 * @frontbuffer_bits: frontbuffer plane tracking bits
5320 *
5321 * When there is a disturbance on screen (due to cursor movement/time
5322 * update etc), DRRS needs to be invalidated, i.e. need to switch to
5323 * high RR.
5324 *
5325 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5326 */
a93fad0f
VK		 5327void intel_edp_drrs_invalidate(struct drm_device *dev,
5328 unsigned frontbuffer_bits)
5329{
5330 struct drm_i915_private *dev_priv = dev->dev_private;
5331 struct drm_crtc *crtc;
5332 enum pipe pipe;
5333
5334 if (!dev_priv->drrs.dp)
5335 return;
5336
3954e733
R		 5337 cancel_delayed_work_sync(&dev_priv->drrs.work);
5338
a93fad0f
VK		 5339 mutex_lock(&dev_priv->drrs.mutex);
5340 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5341 pipe = to_intel_crtc(crtc)->pipe;
5342
5343 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
a93fad0f
VK		 5344 intel_dp_set_drrs_state(dev_priv->dev,
5345 dev_priv->drrs.dp->attached_connector->panel.
5346 fixed_mode->vrefresh);
5347 }
5348
5349 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5350
5351 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5352 mutex_unlock(&dev_priv->drrs.mutex);
5353}
5354
b33a2815
VK		 5355/**
5356 * intel_edp_drrs_flush - Flush DRRS
5357 * @dev: DRM device
5358 * @frontbuffer_bits: frontbuffer plane tracking bits
5359 *
5360 * When there is no movement on screen, DRRS work can be scheduled.
5361 * This DRRS work is responsible for setting relevant registers after a
5362 * timeout of 1 second.
5363 *
5364 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5365 */
a93fad0f
VK		 5366void intel_edp_drrs_flush(struct drm_device *dev,
5367 unsigned frontbuffer_bits)
5368{
5369 struct drm_i915_private *dev_priv = dev->dev_private;
5370 struct drm_crtc *crtc;
5371 enum pipe pipe;
5372
5373 if (!dev_priv->drrs.dp)
5374 return;
5375
3954e733
R		 5376 cancel_delayed_work_sync(&dev_priv->drrs.work);
5377
a93fad0f
VK		 5378 mutex_lock(&dev_priv->drrs.mutex);
5379 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5380 pipe = to_intel_crtc(crtc)->pipe;
5381 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5382
a93fad0f
VK		 5383 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR &&
5384 !dev_priv->drrs.busy_frontbuffer_bits)
5385 schedule_delayed_work(&dev_priv->drrs.work,
5386 msecs_to_jiffies(1000));
5387 mutex_unlock(&dev_priv->drrs.mutex);
5388}
5389
b33a2815
VK		 5390/**
5391 * DOC: Display Refresh Rate Switching (DRRS)
5392 *
5393 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5394 * which enables swtching between low and high refresh rates,
5395 * dynamically, based on the usage scenario. This feature is applicable
5396 * for internal panels.
5397 *
5398 * Indication that the panel supports DRRS is given by the panel EDID, which
5399 * would list multiple refresh rates for one resolution.
5400 *
5401 * DRRS is of 2 types - static and seamless.
5402 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5403 * (may appear as a blink on screen) and is used in dock-undock scenario.
5404 * Seamless DRRS involves changing RR without any visual effect to the user
5405 * and can be used during normal system usage. This is done by programming
5406 * certain registers.
5407 *
5408 * Support for static/seamless DRRS may be indicated in the VBT based on
5409 * inputs from the panel spec.
5410 *
5411 * DRRS saves power by switching to low RR based on usage scenarios.
5412 *
5413 * eDP DRRS:-
5414 * The implementation is based on frontbuffer tracking implementation.
5415 * When there is a disturbance on the screen triggered by user activity or a
5416 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5417 * When there is no movement on screen, after a timeout of 1 second, a switch
5418 * to low RR is made.
5419 * For integration with frontbuffer tracking code,
5420 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5421 *
5422 * DRRS can be further extended to support other internal panels and also
5423 * the scenario of video playback wherein RR is set based on the rate
5424 * requested by userspace.
5425 */
5426
5427/**
5428 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5429 * @intel_connector: eDP connector
5430 * @fixed_mode: preferred mode of panel
5431 *
5432 * This function is called only once at driver load to initialize basic
5433 * DRRS stuff.
5434 *
5435 * Returns:
5436 * Downclock mode if panel supports it, else return NULL.
5437 * DRRS support is determined by the presence of downclock mode (apart
5438 * from VBT setting).
5439 */
4f9db5b5 5440static struct drm_display_mode *
96178eeb
VK		 5441intel_dp_drrs_init(struct intel_connector *intel_connector,
5442 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5443{
5444 struct drm_connector *connector = &intel_connector->base;
96178eeb 5445 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5446 struct drm_i915_private *dev_priv = dev->dev_private;
5447 struct drm_display_mode *downclock_mode = NULL;
5448
5449 if (INTEL_INFO(dev)->gen <= 6) {
5450 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5451 return NULL;
5452 }
5453
5454 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5455 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5456 return NULL;
5457 }
5458
5459 downclock_mode = intel_find_panel_downclock
5460 (dev, fixed_mode, connector);
5461
5462 if (!downclock_mode) {
a1d26342 5463 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5464 return NULL;
5465 }
5466
4e9ac947
VK		 5467 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5468
96178eeb 5469 mutex_init(&dev_priv->drrs.mutex);
439d7ac0 5470
96178eeb 5471 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5472
96178eeb 5473 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5474 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5475 return downclock_mode;
5476}
5477
ed92f0b2 5478static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5479 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5480{
5481 struct drm_connector *connector = &intel_connector->base;
5482 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5483 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5484 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5485 struct drm_i915_private *dev_priv = dev->dev_private;
5486 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5487 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5488 bool has_dpcd;
5489 struct drm_display_mode *scan;
5490 struct edid *edid;
6517d273 5491 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5492
5493 if (!is_edp(intel_dp))
5494 return true;
5495
49e6bc51
VS		 5496 pps_lock(intel_dp);
5497 intel_edp_panel_vdd_sanitize(intel_dp);
5498 pps_unlock(intel_dp);
63635217 5499
ed92f0b2 5500 /* Cache DPCD and EDID for edp. */
ed92f0b2 5501 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5502
5503 if (has_dpcd) {
5504 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5505 dev_priv->no_aux_handshake =
5506 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5507 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5508 } else {
5509 /* if this fails, presume the device is a ghost */
5510 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5511 return false;
5512 }
5513
5514 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5515 pps_lock(intel_dp);
36b5f425 5516 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5517 pps_unlock(intel_dp);
ed92f0b2 5518
060c8778 5519 mutex_lock(&dev->mode_config.mutex);
0b99836f 5520 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5521 if (edid) {
5522 if (drm_add_edid_modes(connector, edid)) {
5523 drm_mode_connector_update_edid_property(connector,
5524 edid);
5525 drm_edid_to_eld(connector, edid);
5526 } else {
5527 kfree(edid);
5528 edid = ERR_PTR(-EINVAL);
5529 }
5530 } else {
5531 edid = ERR_PTR(-ENOENT);
5532 }
5533 intel_connector->edid = edid;
5534
5535 /* prefer fixed mode from EDID if available */
5536 list_for_each_entry(scan, &connector->probed_modes, head) {
5537 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5538 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5539 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5540 intel_connector, fixed_mode);
ed92f0b2
PZ		 5541 break;
5542 }
5543 }
5544
5545 /* fallback to VBT if available for eDP */
5546 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5547 fixed_mode = drm_mode_duplicate(dev,
5548 dev_priv->vbt.lfp_lvds_vbt_mode);
5549 if (fixed_mode)
5550 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5551 }
060c8778 5552 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5553
01527b31
CT		 5554 if (IS_VALLEYVIEW(dev)) {
5555 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5556 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5557
5558 /*
5559 * Figure out the current pipe for the initial backlight setup.
5560 * If the current pipe isn't valid, try the PPS pipe, and if that
5561 * fails just assume pipe A.
5562 */
5563 if (IS_CHERRYVIEW(dev))
5564 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5565 else
5566 pipe = PORT_TO_PIPE(intel_dp->DP);
5567
5568 if (pipe != PIPE_A && pipe != PIPE_B)
5569 pipe = intel_dp->pps_pipe;
5570
5571 if (pipe != PIPE_A && pipe != PIPE_B)
5572 pipe = PIPE_A;
5573
5574 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5575 pipe_name(pipe));
01527b31
CT		 5576 }
5577
4f9db5b5 5578 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5579 intel_connector->panel.backlight_power = intel_edp_backlight_power;
6517d273 5580 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5581
5582 return true;
5583}
5584
16c25533 5585bool
f0fec3f2
PZ		 5586intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5587 struct intel_connector *intel_connector)
a4fc5ed6 5588{
f0fec3f2
PZ		 5589 struct drm_connector *connector = &intel_connector->base;
5590 struct intel_dp *intel_dp = &intel_dig_port->dp;
5591 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5592 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5593 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5594 enum port port = intel_dig_port->port;
0b99836f 5595 int type;
a4fc5ed6 5596
a4a5d2f8
VS		 5597 intel_dp->pps_pipe = INVALID_PIPE;
5598
ec5b01dd 5599 /* intel_dp vfuncs */
b6b5e383
DL		 5600 if (INTEL_INFO(dev)->gen >= 9)
5601 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5602 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5603 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5604 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5605 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5606 else if (HAS_PCH_SPLIT(dev))
5607 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5608 else
5609 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5610
b9ca5fad
DL		 5611 if (INTEL_INFO(dev)->gen >= 9)
5612 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5613 else
5614 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5615
0767935e
DV		 5616 /* Preserve the current hw state. */
5617 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5618 intel_dp->attached_connector = intel_connector;
3d3dc149 5619
3b32a35b 5620 if (intel_dp_is_edp(dev, port))
b329530c 5621 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5622 else
5623 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5624
f7d24902
ID		 5625 /*
5626 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5627 * for DP the encoder type can be set by the caller to
5628 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5629 */
5630 if (type == DRM_MODE_CONNECTOR_eDP)
5631 intel_encoder->type = INTEL_OUTPUT_EDP;
5632
c17ed5b5
VS		 5633 /* eDP only on port B and/or C on vlv/chv */
5634 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5635 port != PORT_B && port != PORT_C))
5636 return false;
5637
e7281eab
ID		 5638 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5639 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5640 port_name(port));
5641
b329530c 5642 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5643 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5644
a4fc5ed6
KP		 5645 connector->interlace_allowed = true;
5646 connector->doublescan_allowed = 0;
5647
f0fec3f2 5648 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5649 edp_panel_vdd_work);
a4fc5ed6 5650
df0e9248 5651 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5652 drm_connector_register(connector);
a4fc5ed6 5653
affa9354 5654 if (HAS_DDI(dev))
bcbc889b
PZ		 5655 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5656 else
5657 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5658 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5659
0b99836f 5660 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5661 switch (port) {
5662 case PORT_A:
1d843f9d 5663 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5664 break;
5665 case PORT_B:
1d843f9d 5666 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5667 break;
5668 case PORT_C:
1d843f9d 5669 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5670 break;
5671 case PORT_D:
1d843f9d 5672 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5673 break;
5674 default:
ad1c0b19 5675 BUG();
5eb08b69
ZW		 5676 }
5677
dada1a9f 5678 if (is_edp(intel_dp)) {
773538e8 5679 pps_lock(intel_dp);
1e74a324
VS		 5680 intel_dp_init_panel_power_timestamps(intel_dp);
5681 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5682 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5683 else
36b5f425 5684 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5685 pps_unlock(intel_dp);
dada1a9f 5686 }
0095e6dc 5687
9d1a1031 5688 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5689
0e32b39c 5690 /* init MST on ports that can support it */
c86ea3d0 5691 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
0e32b39c 5692 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5693 intel_dp_mst_encoder_init(intel_dig_port,
5694 intel_connector->base.base.id);
0e32b39c
DA		 5695 }
5696 }
5697
36b5f425 5698 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5699 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5700 if (is_edp(intel_dp)) {
5701 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5702 /*
5703 * vdd might still be enabled do to the delayed vdd off.
5704 * Make sure vdd is actually turned off here.
5705 */
773538e8 5706 pps_lock(intel_dp);
4be73780 5707 edp_panel_vdd_off_sync(intel_dp);
773538e8 5708 pps_unlock(intel_dp);
15b1d171 5709 }
34ea3d38 5710 drm_connector_unregister(connector);
b2f246a8 5711 drm_connector_cleanup(connector);
16c25533 5712 return false;
b2f246a8 5713 }
32f9d658 5714
f684960e
CW		 5715 intel_dp_add_properties(intel_dp, connector);
5716
a4fc5ed6
KP		 5717 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5718 * 0xd. Failure to do so will result in spurious interrupts being
5719 * generated on the port when a cable is not attached.
5720 */
5721 if (IS_G4X(dev) && !IS_GM45(dev)) {
5722 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5723 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5724 }
16c25533 5725
aa7471d2
JN		 5726 i915_debugfs_connector_add(connector);
5727
16c25533 5728 return true;
a4fc5ed6 5729}
f0fec3f2
PZ		 5730
5731void
5732intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5733{
13cf5504 5734 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5735 struct intel_digital_port *intel_dig_port;
5736 struct intel_encoder *intel_encoder;
5737 struct drm_encoder *encoder;
5738 struct intel_connector *intel_connector;
5739
b14c5679 5740 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5741 if (!intel_dig_port)
5742 return;
5743
9bdbd0b9 5744 intel_connector = intel_connector_alloc();
f0fec3f2
PZ		 5745 if (!intel_connector) {
5746 kfree(intel_dig_port);
5747 return;
5748 }
5749
5750 intel_encoder = &intel_dig_port->base;
5751 encoder = &intel_encoder->base;
5752
5753 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5754 DRM_MODE_ENCODER_TMDS);
5755
5bfe2ac0 5756 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5757 intel_encoder->disable = intel_disable_dp;
00c09d70 5758 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5759 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5760 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5761 if (IS_CHERRYVIEW(dev)) {
9197c88b 5762 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5763 intel_encoder->pre_enable = chv_pre_enable_dp;
5764 intel_encoder->enable = vlv_enable_dp;
580d3811 5765 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5766 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5767 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5768 intel_encoder->pre_enable = vlv_pre_enable_dp;
5769 intel_encoder->enable = vlv_enable_dp;
49277c31 5770 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5771 } else {
ecff4f3b
JN		 5772 intel_encoder->pre_enable = g4x_pre_enable_dp;
5773 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5774 if (INTEL_INFO(dev)->gen >= 5)
5775 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5776 }
f0fec3f2 5777
174edf1f 5778 intel_dig_port->port = port;
f0fec3f2
PZ		 5779 intel_dig_port->dp.output_reg = output_reg;
5780
00c09d70 5781 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5782 if (IS_CHERRYVIEW(dev)) {
5783 if (port == PORT_D)
5784 intel_encoder->crtc_mask = 1 << 2;
5785 else
5786 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5787 } else {
5788 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5789 }
bc079e8b 5790 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5791 intel_encoder->hot_plug = intel_dp_hot_plug;
5792
13cf5504
DA		 5793 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5794 dev_priv->hpd_irq_port[port] = intel_dig_port;
5795
15b1d171
PZ		 5796 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5797 drm_encoder_cleanup(encoder);
5798 kfree(intel_dig_port);
b2f246a8 5799 kfree(intel_connector);
15b1d171 5800 }
f0fec3f2 5801}
0e32b39c
DA		 5802
5803void intel_dp_mst_suspend(struct drm_device *dev)
5804{
5805 struct drm_i915_private *dev_priv = dev->dev_private;
5806 int i;
5807
5808 /* disable MST */
5809 for (i = 0; i < I915_MAX_PORTS; i++) {
5810 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5811 if (!intel_dig_port)
5812 continue;
5813
5814 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5815 if (!intel_dig_port->dp.can_mst)
5816 continue;
5817 if (intel_dig_port->dp.is_mst)
5818 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5819 }
5820 }
5821}
5822
5823void intel_dp_mst_resume(struct drm_device *dev)
5824{
5825 struct drm_i915_private *dev_priv = dev->dev_private;
5826 int i;
5827
5828 for (i = 0; i < I915_MAX_PORTS; i++) {
5829 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5830 if (!intel_dig_port)
5831 continue;
5832 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5833 int ret;
5834
5835 if (!intel_dig_port->dp.can_mst)
5836 continue;
5837
5838 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5839 if (ret != 0) {
5840 intel_dp_check_mst_status(&intel_dig_port->dp);
5841 }
5842 }
5843 }
5844}
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