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drm/i915/audio: rewrite vlv/chv and gen 5-7 audio codec enable sequence
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 116static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 117static void vlv_steal_power_sequencer(struct drm_device *dev,
118 enum pipe pipe);
a4fc5ed6 119
0e32b39c 120int
ea5b213a 121intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 122{
7183dc29 123 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 124 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 125
126 switch (max_link_bw) {
127 case DP_LINK_BW_1_62:
128 case DP_LINK_BW_2_7:
129 break;
d4eead50 130 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 131 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
132 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 133 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
134 max_link_bw = DP_LINK_BW_5_4;
135 else
136 max_link_bw = DP_LINK_BW_2_7;
d4eead50 137 break;
a4fc5ed6 138 default:
d4eead50
ID		 139 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
140 max_link_bw);
a4fc5ed6
KP		 141 max_link_bw = DP_LINK_BW_1_62;
142 break;
143 }
144 return max_link_bw;
145}
146
eeb6324d
PZ		 147static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
148{
149 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
150 struct drm_device *dev = intel_dig_port->base.base.dev;
151 u8 source_max, sink_max;
152
153 source_max = 4;
154 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
155 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
156 source_max = 2;
157
158 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
159
160 return min(source_max, sink_max);
161}
162
cd9dde44
AJ		 163/*
164 * The units on the numbers in the next two are... bizarre. Examples will
165 * make it clearer; this one parallels an example in the eDP spec.
166 *
167 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
168 *
169 * 270000 * 1 * 8 / 10 == 216000
170 *
171 * The actual data capacity of that configuration is 2.16Gbit/s, so the
172 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
173 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
174 * 119000. At 18bpp that's 2142000 kilobits per second.
175 *
176 * Thus the strange-looking division by 10 in intel_dp_link_required, to
177 * get the result in decakilobits instead of kilobits.
178 */
179
a4fc5ed6 180static int
c898261c 181intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 182{
cd9dde44 183 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 184}
185
fe27d53e
DA		 186static int
187intel_dp_max_data_rate(int max_link_clock, int max_lanes)
188{
189 return (max_link_clock * max_lanes * 8) / 10;
190}
191
c19de8eb 192static enum drm_mode_status
a4fc5ed6
KP		 193intel_dp_mode_valid(struct drm_connector *connector,
194 struct drm_display_mode *mode)
195{
df0e9248 196 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 197 struct intel_connector *intel_connector = to_intel_connector(connector);
198 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 199 int target_clock = mode->clock;
200 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 201
dd06f90e
JN		 202 if (is_edp(intel_dp) && fixed_mode) {
203 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 204 return MODE_PANEL;
205
dd06f90e 206 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 207 return MODE_PANEL;
03afc4a2
DV		 208
209 target_clock = fixed_mode->clock;
7de56f43
ZY		 210 }
211
36008365 212 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 213 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 214
215 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
216 mode_rate = intel_dp_link_required(target_clock, 18);
217
218 if (mode_rate > max_rate)
c4867936 219 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 220
221 if (mode->clock < 10000)
222 return MODE_CLOCK_LOW;
223
0af78a2b
DV		 224 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
225 return MODE_H_ILLEGAL;
226
a4fc5ed6
KP		 227 return MODE_OK;
228}
229
230static uint32_t
5ca476f8 231pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 232{
233 int i;
234 uint32_t v = 0;
235
236 if (src_bytes > 4)
237 src_bytes = 4;
238 for (i = 0; i < src_bytes; i++)
239 v |= ((uint32_t) src[i]) << ((3-i) * 8);
240 return v;
241}
242
243static void
244unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
245{
246 int i;
247 if (dst_bytes > 4)
248 dst_bytes = 4;
249 for (i = 0; i < dst_bytes; i++)
250 dst[i] = src >> ((3-i) * 8);
251}
252
fb0f8fbf
KP		 253/* hrawclock is 1/4 the FSB frequency */
254static int
255intel_hrawclk(struct drm_device *dev)
256{
257 struct drm_i915_private *dev_priv = dev->dev_private;
258 uint32_t clkcfg;
259
9473c8f4
VP		 260 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
261 if (IS_VALLEYVIEW(dev))
262 return 200;
263
fb0f8fbf
KP		 264 clkcfg = I915_READ(CLKCFG);
265 switch (clkcfg & CLKCFG_FSB_MASK) {
266 case CLKCFG_FSB_400:
267 return 100;
268 case CLKCFG_FSB_533:
269 return 133;
270 case CLKCFG_FSB_667:
271 return 166;
272 case CLKCFG_FSB_800:
273 return 200;
274 case CLKCFG_FSB_1067:
275 return 266;
276 case CLKCFG_FSB_1333:
277 return 333;
278 /* these two are just a guess; one of them might be right */
279 case CLKCFG_FSB_1600:
280 case CLKCFG_FSB_1600_ALT:
281 return 400;
282 default:
283 return 133;
284 }
285}
286
bf13e81b
JN		 287static void
288intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 289 struct intel_dp *intel_dp);
bf13e81b
JN		 290static void
291intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 292 struct intel_dp *intel_dp);
bf13e81b 293
773538e8
VS		 294static void pps_lock(struct intel_dp *intel_dp)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct intel_encoder *encoder = &intel_dig_port->base;
298 struct drm_device *dev = encoder->base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum intel_display_power_domain power_domain;
301
302 /*
303 * See vlv_power_sequencer_reset() why we need
304 * a power domain reference here.
305 */
306 power_domain = intel_display_port_power_domain(encoder);
307 intel_display_power_get(dev_priv, power_domain);
308
309 mutex_lock(&dev_priv->pps_mutex);
310}
311
312static void pps_unlock(struct intel_dp *intel_dp)
313{
314 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
315 struct intel_encoder *encoder = &intel_dig_port->base;
316 struct drm_device *dev = encoder->base.dev;
317 struct drm_i915_private *dev_priv = dev->dev_private;
318 enum intel_display_power_domain power_domain;
319
320 mutex_unlock(&dev_priv->pps_mutex);
321
322 power_domain = intel_display_port_power_domain(encoder);
323 intel_display_power_put(dev_priv, power_domain);
324}
325
961a0db0
VS		 326static void
327vlv_power_sequencer_kick(struct intel_dp *intel_dp)
328{
329 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
330 struct drm_device *dev = intel_dig_port->base.base.dev;
331 struct drm_i915_private *dev_priv = dev->dev_private;
332 enum pipe pipe = intel_dp->pps_pipe;
d288f65f 333 bool pll_enabled;
961a0db0
VS		 334 uint32_t DP;
335
336 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
337 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
338 pipe_name(pipe), port_name(intel_dig_port->port)))
339 return;
340
341 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
342 pipe_name(pipe), port_name(intel_dig_port->port));
343
344 /* Preserve the BIOS-computed detected bit. This is
345 * supposed to be read-only.
346 */
347 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
348 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
349 DP |= DP_PORT_WIDTH(1);
350 DP |= DP_LINK_TRAIN_PAT_1;
351
352 if (IS_CHERRYVIEW(dev))
353 DP |= DP_PIPE_SELECT_CHV(pipe);
354 else if (pipe == PIPE_B)
355 DP |= DP_PIPEB_SELECT;
356
d288f65f
VS		 357 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
358
359 /*
360 * The DPLL for the pipe must be enabled for this to work.
361 * So enable temporarily it if it's not already enabled.
362 */
363 if (!pll_enabled)
364 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
365 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
366
961a0db0
VS		 367 /*
368 * Similar magic as in intel_dp_enable_port().
369 * We _must_ do this port enable + disable trick
370 * to make this power seqeuencer lock onto the port.
371 * Otherwise even VDD force bit won't work.
372 */
373 I915_WRITE(intel_dp->output_reg, DP);
374 POSTING_READ(intel_dp->output_reg);
375
376 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
377 POSTING_READ(intel_dp->output_reg);
378
379 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
380 POSTING_READ(intel_dp->output_reg);
d288f65f
VS		 381
382 if (!pll_enabled)
383 vlv_force_pll_off(dev, pipe);
961a0db0
VS		 384}
385
bf13e81b
JN		 386static enum pipe
387vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
388{
389 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 390 struct drm_device *dev = intel_dig_port->base.base.dev;
391 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 392 struct intel_encoder *encoder;
393 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 394 enum pipe pipe;
bf13e81b 395
e39b999a 396 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 397
a8c3344e
VS		 398 /* We should never land here with regular DP ports */
399 WARN_ON(!is_edp(intel_dp));
400
a4a5d2f8
VS		 401 if (intel_dp->pps_pipe != INVALID_PIPE)
402 return intel_dp->pps_pipe;
403
404 /*
405 * We don't have power sequencer currently.
406 * Pick one that's not used by other ports.
407 */
408 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
409 base.head) {
410 struct intel_dp *tmp;
411
412 if (encoder->type != INTEL_OUTPUT_EDP)
413 continue;
414
415 tmp = enc_to_intel_dp(&encoder->base);
416
417 if (tmp->pps_pipe != INVALID_PIPE)
418 pipes &= ~(1 << tmp->pps_pipe);
419 }
420
421 /*
422 * Didn't find one. This should not happen since there
423 * are two power sequencers and up to two eDP ports.
424 */
425 if (WARN_ON(pipes == 0))
a8c3344e
VS		 426 pipe = PIPE_A;
427 else
428 pipe = ffs(pipes) - 1;
a4a5d2f8 429
a8c3344e
VS		 430 vlv_steal_power_sequencer(dev, pipe);
431 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 432
433 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
434 pipe_name(intel_dp->pps_pipe),
435 port_name(intel_dig_port->port));
436
437 /* init power sequencer on this pipe and port */
36b5f425
VS		 438 intel_dp_init_panel_power_sequencer(dev, intel_dp);
439 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 440
961a0db0
VS		 441 /*
442 * Even vdd force doesn't work until we've made
443 * the power sequencer lock in on the port.
444 */
445 vlv_power_sequencer_kick(intel_dp);
446
a4a5d2f8
VS		 447 return intel_dp->pps_pipe;
448}
449
6491ab27
VS		 450typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
451 enum pipe pipe);
452
453static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
454 enum pipe pipe)
455{
456 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
457}
458
459static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
460 enum pipe pipe)
461{
462 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
463}
464
465static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
466 enum pipe pipe)
467{
468 return true;
469}
bf13e81b 470
a4a5d2f8 471static enum pipe
6491ab27
VS		 472vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
473 enum port port,
474 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 475{
476 enum pipe pipe;
bf13e81b 477
bf13e81b
JN		 478 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
479 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
480 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 481
482 if (port_sel != PANEL_PORT_SELECT_VLV(port))
483 continue;
484
6491ab27
VS		 485 if (!pipe_check(dev_priv, pipe))
486 continue;
487
a4a5d2f8 488 return pipe;
bf13e81b
JN		 489 }
490
a4a5d2f8
VS		 491 return INVALID_PIPE;
492}
493
494static void
495vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
496{
497 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
498 struct drm_device *dev = intel_dig_port->base.base.dev;
499 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 500 enum port port = intel_dig_port->port;
501
502 lockdep_assert_held(&dev_priv->pps_mutex);
503
504 /* try to find a pipe with this port selected */
6491ab27
VS		 505 /* first pick one where the panel is on */
506 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
507 vlv_pipe_has_pp_on);
508 /* didn't find one? pick one where vdd is on */
509 if (intel_dp->pps_pipe == INVALID_PIPE)
510 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
511 vlv_pipe_has_vdd_on);
512 /* didn't find one? pick one with just the correct port */
513 if (intel_dp->pps_pipe == INVALID_PIPE)
514 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
515 vlv_pipe_any);
a4a5d2f8
VS		 516
517 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
518 if (intel_dp->pps_pipe == INVALID_PIPE) {
519 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
520 port_name(port));
521 return;
bf13e81b
JN		 522 }
523
a4a5d2f8
VS		 524 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
525 port_name(port), pipe_name(intel_dp->pps_pipe));
526
36b5f425
VS		 527 intel_dp_init_panel_power_sequencer(dev, intel_dp);
528 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 529}
530
773538e8
VS		 531void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
532{
533 struct drm_device *dev = dev_priv->dev;
534 struct intel_encoder *encoder;
535
536 if (WARN_ON(!IS_VALLEYVIEW(dev)))
537 return;
538
539 /*
540 * We can't grab pps_mutex here due to deadlock with power_domain
541 * mutex when power_domain functions are called while holding pps_mutex.
542 * That also means that in order to use pps_pipe the code needs to
543 * hold both a power domain reference and pps_mutex, and the power domain
544 * reference get/put must be done while _not_ holding pps_mutex.
545 * pps_{lock,unlock}() do these steps in the correct order, so one
546 * should use them always.
547 */
548
549 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
550 struct intel_dp *intel_dp;
551
552 if (encoder->type != INTEL_OUTPUT_EDP)
553 continue;
554
555 intel_dp = enc_to_intel_dp(&encoder->base);
556 intel_dp->pps_pipe = INVALID_PIPE;
557 }
bf13e81b
JN		 558}
559
560static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
561{
562 struct drm_device *dev = intel_dp_to_dev(intel_dp);
563
564 if (HAS_PCH_SPLIT(dev))
565 return PCH_PP_CONTROL;
566 else
567 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
568}
569
570static u32 _pp_stat_reg(struct intel_dp *intel_dp)
571{
572 struct drm_device *dev = intel_dp_to_dev(intel_dp);
573
574 if (HAS_PCH_SPLIT(dev))
575 return PCH_PP_STATUS;
576 else
577 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
578}
579
01527b31
CT		 580/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
581 This function only applicable when panel PM state is not to be tracked */
582static int edp_notify_handler(struct notifier_block *this, unsigned long code,
583 void *unused)
584{
585 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
586 edp_notifier);
587 struct drm_device *dev = intel_dp_to_dev(intel_dp);
588 struct drm_i915_private *dev_priv = dev->dev_private;
589 u32 pp_div;
590 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 591
592 if (!is_edp(intel_dp) || code != SYS_RESTART)
593 return 0;
594
773538e8 595 pps_lock(intel_dp);
e39b999a 596
01527b31 597 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 598 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
599
01527b31
CT		 600 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
601 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
602 pp_div = I915_READ(pp_div_reg);
603 pp_div &= PP_REFERENCE_DIVIDER_MASK;
604
605 /* 0x1F write to PP_DIV_REG sets max cycle delay */
606 I915_WRITE(pp_div_reg, pp_div | 0x1F);
607 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
608 msleep(intel_dp->panel_power_cycle_delay);
609 }
610
773538e8 611 pps_unlock(intel_dp);
e39b999a 612
01527b31
CT		 613 return 0;
614}
615
4be73780 616static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 617{
30add22d 618 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 619 struct drm_i915_private *dev_priv = dev->dev_private;
620
e39b999a
VS		 621 lockdep_assert_held(&dev_priv->pps_mutex);
622
9a42356b
VS		 623 if (IS_VALLEYVIEW(dev) &&
624 intel_dp->pps_pipe == INVALID_PIPE)
625 return false;
626
bf13e81b 627 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 628}
629
4be73780 630static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 631{
30add22d 632 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 633 struct drm_i915_private *dev_priv = dev->dev_private;
634
e39b999a
VS		 635 lockdep_assert_held(&dev_priv->pps_mutex);
636
9a42356b
VS		 637 if (IS_VALLEYVIEW(dev) &&
638 intel_dp->pps_pipe == INVALID_PIPE)
639 return false;
640
773538e8 641 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 642}
643
9b984dae
KP		 644static void
645intel_dp_check_edp(struct intel_dp *intel_dp)
646{
30add22d 647 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 648 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 649
9b984dae
KP		 650 if (!is_edp(intel_dp))
651 return;
453c5420 652
4be73780 653 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 654 WARN(1, "eDP powered off while attempting aux channel communication.\n");
655 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 656 I915_READ(_pp_stat_reg(intel_dp)),
657 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 658 }
659}
660
9ee32fea
DV		 661static uint32_t
662intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
663{
664 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
665 struct drm_device *dev = intel_dig_port->base.base.dev;
666 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 667 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 668 uint32_t status;
669 bool done;
670
ef04f00d 671#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 672 if (has_aux_irq)
b18ac466 673 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 674 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 675 else
676 done = wait_for_atomic(C, 10) == 0;
677 if (!done)
678 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
679 has_aux_irq);
680#undef C
681
682 return status;
683}
684
ec5b01dd 685static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 686{
174edf1f
PZ		 687 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
688 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 689
ec5b01dd
DL		 690 /*
691 * The clock divider is based off the hrawclk, and would like to run at
692 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 693 */
ec5b01dd
DL		 694 return index ? 0 : intel_hrawclk(dev) / 2;
695}
696
697static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
698{
699 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
700 struct drm_device *dev = intel_dig_port->base.base.dev;
701
702 if (index)
703 return 0;
704
705 if (intel_dig_port->port == PORT_A) {
706 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 707 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 708 else
b84a1cf8 709 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 710 } else {
711 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
712 }
713}
714
715static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
716{
717 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
718 struct drm_device *dev = intel_dig_port->base.base.dev;
719 struct drm_i915_private *dev_priv = dev->dev_private;
720
721 if (intel_dig_port->port == PORT_A) {
722 if (index)
723 return 0;
724 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 725 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
726 /* Workaround for non-ULT HSW */
bc86625a
CW		 727 switch (index) {
728 case 0: return 63;
729 case 1: return 72;
730 default: return 0;
731 }
ec5b01dd 732 } else {
bc86625a 733 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 734 }
b84a1cf8
RV		 735}
736
ec5b01dd
DL		 737static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
738{
739 return index ? 0 : 100;
740}
741
b6b5e383
DL		 742static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
743{
744 /*
745 * SKL doesn't need us to program the AUX clock divider (Hardware will
746 * derive the clock from CDCLK automatically). We still implement the
747 * get_aux_clock_divider vfunc to plug-in into the existing code.
748 */
749 return index ? 0 : 1;
750}
751
5ed12a19
DL		 752static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
753 bool has_aux_irq,
754 int send_bytes,
755 uint32_t aux_clock_divider)
756{
757 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
758 struct drm_device *dev = intel_dig_port->base.base.dev;
759 uint32_t precharge, timeout;
760
761 if (IS_GEN6(dev))
762 precharge = 3;
763 else
764 precharge = 5;
765
766 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
767 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
768 else
769 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
770
771 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 772 DP_AUX_CH_CTL_DONE |
5ed12a19 773 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 774 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 775 timeout |
788d4433 776 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 777 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
778 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 779 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 780}
781
b9ca5fad
DL		 782static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
783 bool has_aux_irq,
784 int send_bytes,
785 uint32_t unused)
786{
787 return DP_AUX_CH_CTL_SEND_BUSY |
788 DP_AUX_CH_CTL_DONE |
789 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
790 DP_AUX_CH_CTL_TIME_OUT_ERROR |
791 DP_AUX_CH_CTL_TIME_OUT_1600us |
792 DP_AUX_CH_CTL_RECEIVE_ERROR |
793 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
794 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
795}
796
b84a1cf8
RV		 797static int
798intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 799 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 800 uint8_t *recv, int recv_size)
801{
802 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
803 struct drm_device *dev = intel_dig_port->base.base.dev;
804 struct drm_i915_private *dev_priv = dev->dev_private;
805 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
806 uint32_t ch_data = ch_ctl + 4;
bc86625a 807 uint32_t aux_clock_divider;
b84a1cf8
RV		 808 int i, ret, recv_bytes;
809 uint32_t status;
5ed12a19 810 int try, clock = 0;
4e6b788c 811 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 812 bool vdd;
813
773538e8 814 pps_lock(intel_dp);
e39b999a 815
72c3500a
VS		 816 /*
817 * We will be called with VDD already enabled for dpcd/edid/oui reads.
818 * In such cases we want to leave VDD enabled and it's up to upper layers
819 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
820 * ourselves.
821 */
1e0560e0 822 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 823
824 /* dp aux is extremely sensitive to irq latency, hence request the
825 * lowest possible wakeup latency and so prevent the cpu from going into
826 * deep sleep states.
827 */
828 pm_qos_update_request(&dev_priv->pm_qos, 0);
829
830 intel_dp_check_edp(intel_dp);
5eb08b69 831
c67a470b
PZ		 832 intel_aux_display_runtime_get(dev_priv);
833
11bee43e
JB		 834 /* Try to wait for any previous AUX channel activity */
835 for (try = 0; try < 3; try++) {
ef04f00d 836 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 837 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
838 break;
839 msleep(1);
840 }
841
842 if (try == 3) {
843 WARN(1, "dp_aux_ch not started status 0x%08x\n",
844 I915_READ(ch_ctl));
9ee32fea
DV		 845 ret = -EBUSY;
846 goto out;
4f7f7b7e
CW		 847 }
848
46a5ae9f
PZ		 849 /* Only 5 data registers! */
850 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
851 ret = -E2BIG;
852 goto out;
853 }
854
ec5b01dd 855 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 856 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
857 has_aux_irq,
858 send_bytes,
859 aux_clock_divider);
5ed12a19 860
bc86625a
CW		 861 /* Must try at least 3 times according to DP spec */
862 for (try = 0; try < 5; try++) {
863 /* Load the send data into the aux channel data registers */
864 for (i = 0; i < send_bytes; i += 4)
865 I915_WRITE(ch_data + i,
866 pack_aux(send + i, send_bytes - i));
867
868 /* Send the command and wait for it to complete */
5ed12a19 869 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 870
871 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
872
873 /* Clear done status and any errors */
874 I915_WRITE(ch_ctl,
875 status |
876 DP_AUX_CH_CTL_DONE |
877 DP_AUX_CH_CTL_TIME_OUT_ERROR |
878 DP_AUX_CH_CTL_RECEIVE_ERROR);
879
880 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
881 DP_AUX_CH_CTL_RECEIVE_ERROR))
882 continue;
883 if (status & DP_AUX_CH_CTL_DONE)
884 break;
885 }
4f7f7b7e 886 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 887 break;
888 }
889
a4fc5ed6 890 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 891 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 892 ret = -EBUSY;
893 goto out;
a4fc5ed6
KP		 894 }
895
896 /* Check for timeout or receive error.
897 * Timeouts occur when the sink is not connected
898 */
a5b3da54 899 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 900 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 901 ret = -EIO;
902 goto out;
a5b3da54 903 }
1ae8c0a5
KP		 904
905 /* Timeouts occur when the device isn't connected, so they're
906 * "normal" -- don't fill the kernel log with these */
a5b3da54 907 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 908 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 909 ret = -ETIMEDOUT;
910 goto out;
a4fc5ed6
KP		 911 }
912
913 /* Unload any bytes sent back from the other side */
914 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
915 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 916 if (recv_bytes > recv_size)
917 recv_bytes = recv_size;
0206e353 918
4f7f7b7e
CW		 919 for (i = 0; i < recv_bytes; i += 4)
920 unpack_aux(I915_READ(ch_data + i),
921 recv + i, recv_bytes - i);
a4fc5ed6 922
9ee32fea
DV		 923 ret = recv_bytes;
924out:
925 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 926 intel_aux_display_runtime_put(dev_priv);
9ee32fea 927
884f19e9
JN		 928 if (vdd)
929 edp_panel_vdd_off(intel_dp, false);
930
773538e8 931 pps_unlock(intel_dp);
e39b999a 932
9ee32fea 933 return ret;
a4fc5ed6
KP		 934}
935
a6c8aff0
JN		 936#define BARE_ADDRESS_SIZE 3
937#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 938static ssize_t
939intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 940{
9d1a1031
JN		 941 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
942 uint8_t txbuf[20], rxbuf[20];
943 size_t txsize, rxsize;
a4fc5ed6 944 int ret;
a4fc5ed6 945
9d1a1031
JN		 946 txbuf[0] = msg->request << 4;
947 txbuf[1] = msg->address >> 8;
948 txbuf[2] = msg->address & 0xff;
949 txbuf[3] = msg->size - 1;
46a5ae9f 950
9d1a1031
JN		 951 switch (msg->request & ~DP_AUX_I2C_MOT) {
952 case DP_AUX_NATIVE_WRITE:
953 case DP_AUX_I2C_WRITE:
a6c8aff0 954 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 955 rxsize = 1;
f51a44b9 956
9d1a1031
JN		 957 if (WARN_ON(txsize > 20))
958 return -E2BIG;
a4fc5ed6 959
9d1a1031 960 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 961
9d1a1031
JN		 962 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
963 if (ret > 0) {
964 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 965
9d1a1031
JN		 966 /* Return payload size. */
967 ret = msg->size;
968 }
969 break;
46a5ae9f 970
9d1a1031
JN		 971 case DP_AUX_NATIVE_READ:
972 case DP_AUX_I2C_READ:
a6c8aff0 973 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 974 rxsize = msg->size + 1;
a4fc5ed6 975
9d1a1031
JN		 976 if (WARN_ON(rxsize > 20))
977 return -E2BIG;
a4fc5ed6 978
9d1a1031
JN		 979 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
980 if (ret > 0) {
981 msg->reply = rxbuf[0] >> 4;
982 /*
983 * Assume happy day, and copy the data. The caller is
984 * expected to check msg->reply before touching it.
985 *
986 * Return payload size.
987 */
988 ret--;
989 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 990 }
9d1a1031
JN		 991 break;
992
993 default:
994 ret = -EINVAL;
995 break;
a4fc5ed6 996 }
f51a44b9 997
9d1a1031 998 return ret;
a4fc5ed6
KP		 999}
1000
9d1a1031
JN		 1001static void
1002intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1003{
1004 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 1005 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1006 enum port port = intel_dig_port->port;
0b99836f 1007 const char *name = NULL;
ab2c0672
DA		 1008 int ret;
1009
33ad6626
JN		 1010 switch (port) {
1011 case PORT_A:
1012 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 1013 name = "DPDDC-A";
ab2c0672 1014 break;
33ad6626
JN		 1015 case PORT_B:
1016 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1017 name = "DPDDC-B";
ab2c0672 1018 break;
33ad6626
JN		 1019 case PORT_C:
1020 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1021 name = "DPDDC-C";
ab2c0672 1022 break;
33ad6626
JN		 1023 case PORT_D:
1024 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1025 name = "DPDDC-D";
33ad6626
JN		 1026 break;
1027 default:
1028 BUG();
ab2c0672
DA		 1029 }
1030
1b1aad75
DL		 1031 /*
1032 * The AUX_CTL register is usually DP_CTL + 0x10.
1033 *
1034 * On Haswell and Broadwell though:
1035 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1036 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1037 *
1038 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1039 */
1040 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1041 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1042
0b99836f 1043 intel_dp->aux.name = name;
9d1a1031
JN		 1044 intel_dp->aux.dev = dev->dev;
1045 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1046
0b99836f
JN		 1047 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1048 connector->base.kdev->kobj.name);
8316f337 1049
4f71d0cb 1050 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1051 if (ret < 0) {
4f71d0cb 1052 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1053 name, ret);
1054 return;
ab2c0672 1055 }
8a5e6aeb 1056
0b99836f
JN		 1057 ret = sysfs_create_link(&connector->base.kdev->kobj,
1058 &intel_dp->aux.ddc.dev.kobj,
1059 intel_dp->aux.ddc.dev.kobj.name);
1060 if (ret < 0) {
1061 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1062 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1063 }
a4fc5ed6
KP		 1064}
1065
80f65de3
ID		 1066static void
1067intel_dp_connector_unregister(struct intel_connector *intel_connector)
1068{
1069 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1070
0e32b39c
DA		 1071 if (!intel_connector->mst_port)
1072 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1073 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1074 intel_connector_unregister(intel_connector);
1075}
1076
0e50338c
DV		 1077static void
1078hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
1079{
1080 switch (link_bw) {
1081 case DP_LINK_BW_1_62:
1082 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1083 break;
1084 case DP_LINK_BW_2_7:
1085 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1086 break;
1087 case DP_LINK_BW_5_4:
1088 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1089 break;
1090 }
1091}
1092
c6bb3538
DV		 1093static void
1094intel_dp_set_clock(struct intel_encoder *encoder,
1095 struct intel_crtc_config *pipe_config, int link_bw)
1096{
1097 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1098 const struct dp_link_dpll *divisor = NULL;
1099 int i, count = 0;
c6bb3538
DV		 1100
1101 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1102 divisor = gen4_dpll;
1103 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1104 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1105 divisor = pch_dpll;
1106 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1107 } else if (IS_CHERRYVIEW(dev)) {
1108 divisor = chv_dpll;
1109 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1110 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1111 divisor = vlv_dpll;
1112 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1113 }
9dd4ffdf
CML		 1114
1115 if (divisor && count) {
1116 for (i = 0; i < count; i++) {
1117 if (link_bw == divisor[i].link_bw) {
1118 pipe_config->dpll = divisor[i].dpll;
1119 pipe_config->clock_set = true;
1120 break;
1121 }
1122 }
c6bb3538
DV		 1123 }
1124}
1125
00c09d70 1126bool
5bfe2ac0
DV		 1127intel_dp_compute_config(struct intel_encoder *encoder,
1128 struct intel_crtc_config *pipe_config)
a4fc5ed6 1129{
5bfe2ac0 1130 struct drm_device *dev = encoder->base.dev;
36008365 1131 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1132 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1133 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1134 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1135 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1136 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1137 int lane_count, clock;
56071a20 1138 int min_lane_count = 1;
eeb6324d 1139 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1140 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1141 int min_clock = 0;
06ea66b6 1142 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1143 int bpp, mode_rate;
06ea66b6 1144 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1145 int link_avail, link_clock;
a4fc5ed6 1146
bc7d38a4 1147 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1148 pipe_config->has_pch_encoder = true;
1149
03afc4a2 1150 pipe_config->has_dp_encoder = true;
f769cd24 1151 pipe_config->has_drrs = false;
9ed109a7 1152 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1153
dd06f90e
JN		 1154 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1155 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1156 adjusted_mode);
2dd24552
JB		 1157 if (!HAS_PCH_SPLIT(dev))
1158 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1159 intel_connector->panel.fitting_mode);
1160 else
b074cec8
JB		 1161 intel_pch_panel_fitting(intel_crtc, pipe_config,
1162 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1163 }
1164
cb1793ce 1165 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1166 return false;
1167
083f9560
DV		 1168 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1169 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1170 max_lane_count, bws[max_clock],
1171 adjusted_mode->crtc_clock);
083f9560 1172
36008365
DV		 1173 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1174 * bpc in between. */
3e7ca985 1175 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1176 if (is_edp(intel_dp)) {
1177 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1178 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1179 dev_priv->vbt.edp_bpp);
1180 bpp = dev_priv->vbt.edp_bpp;
1181 }
1182
344c5bbc
JN		 1183 /*
1184 * Use the maximum clock and number of lanes the eDP panel
1185 * advertizes being capable of. The panels are generally
1186 * designed to support only a single clock and lane
1187 * configuration, and typically these values correspond to the
1188 * native resolution of the panel.
1189 */
1190 min_lane_count = max_lane_count;
1191 min_clock = max_clock;
7984211e 1192 }
657445fe 1193
36008365 1194 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1195 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1196 bpp);
36008365 1197
c6930992
DA		 1198 for (clock = min_clock; clock <= max_clock; clock++) {
1199 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1200 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1201 link_avail = intel_dp_max_data_rate(link_clock,
1202 lane_count);
1203
1204 if (mode_rate <= link_avail) {
1205 goto found;
1206 }
1207 }
1208 }
1209 }
c4867936 1210
36008365 1211 return false;
3685a8f3 1212
36008365 1213found:
55bc60db
VS		 1214 if (intel_dp->color_range_auto) {
1215 /*
1216 * See:
1217 * CEA-861-E - 5.1 Default Encoding Parameters
1218 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1219 */
18316c8c 1220 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1221 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1222 else
1223 intel_dp->color_range = 0;
1224 }
1225
3685a8f3 1226 if (intel_dp->color_range)
50f3b016 1227 pipe_config->limited_color_range = true;
a4fc5ed6 1228
36008365
DV		 1229 intel_dp->link_bw = bws[clock];
1230 intel_dp->lane_count = lane_count;
657445fe 1231 pipe_config->pipe_bpp = bpp;
ff9a6750 1232 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1233
36008365
DV		 1234 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1235 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1236 pipe_config->port_clock, bpp);
36008365
DV		 1237 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1238 mode_rate, link_avail);
a4fc5ed6 1239
03afc4a2 1240 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1241 adjusted_mode->crtc_clock,
1242 pipe_config->port_clock,
03afc4a2 1243 &pipe_config->dp_m_n);
9d1a455b 1244
439d7ac0
PB		 1245 if (intel_connector->panel.downclock_mode != NULL &&
1246 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1247 pipe_config->has_drrs = true;
439d7ac0
PB		 1248 intel_link_compute_m_n(bpp, lane_count,
1249 intel_connector->panel.downclock_mode->clock,
1250 pipe_config->port_clock,
1251 &pipe_config->dp_m2_n2);
1252 }
1253
ea155f32 1254 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1255 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1256 else
1257 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1258
03afc4a2 1259 return true;
a4fc5ed6
KP		 1260}
1261
7c62a164 1262static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1263{
7c62a164
DV		 1264 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1265 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1266 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1267 struct drm_i915_private *dev_priv = dev->dev_private;
1268 u32 dpa_ctl;
1269
ff9a6750 1270 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1271 dpa_ctl = I915_READ(DP_A);
1272 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1273
ff9a6750 1274 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1275 /* For a long time we've carried around a ILK-DevA w/a for the
1276 * 160MHz clock. If we're really unlucky, it's still required.
1277 */
1278 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1279 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1280 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1281 } else {
1282 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1283 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1284 }
1ce17038 1285
ea9b6006
DV		 1286 I915_WRITE(DP_A, dpa_ctl);
1287
1288 POSTING_READ(DP_A);
1289 udelay(500);
1290}
1291
8ac33ed3 1292static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1293{
b934223d 1294 struct drm_device *dev = encoder->base.dev;
417e822d 1295 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1296 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1297 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1298 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1299 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1300
417e822d 1301 /*
1a2eb460 1302 * There are four kinds of DP registers:
417e822d
KP		 1303 *
1304 * IBX PCH
1a2eb460
KP		 1305 * SNB CPU
1306 * IVB CPU
417e822d
KP		 1307 * CPT PCH
1308 *
1309 * IBX PCH and CPU are the same for almost everything,
1310 * except that the CPU DP PLL is configured in this
1311 * register
1312 *
1313 * CPT PCH is quite different, having many bits moved
1314 * to the TRANS_DP_CTL register instead. That
1315 * configuration happens (oddly) in ironlake_pch_enable
1316 */
9c9e7927 1317
417e822d
KP		 1318 /* Preserve the BIOS-computed detected bit. This is
1319 * supposed to be read-only.
1320 */
1321 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1322
417e822d 1323 /* Handle DP bits in common between all three register formats */
417e822d 1324 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1325 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1326
9ed109a7 1327 if (crtc->config.has_audio) {
e0dac65e 1328 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1329 pipe_name(crtc->pipe));
ea5b213a 1330 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
69bfe1a9 1331 intel_audio_codec_enable(encoder);
e0dac65e 1332 }
247d89f6 1333
417e822d 1334 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1335
bc7d38a4 1336 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1337 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1338 intel_dp->DP |= DP_SYNC_HS_HIGH;
1339 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1340 intel_dp->DP |= DP_SYNC_VS_HIGH;
1341 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1342
6aba5b6c 1343 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1344 intel_dp->DP |= DP_ENHANCED_FRAMING;
1345
7c62a164 1346 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1347 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1348 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1349 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1350
1351 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1352 intel_dp->DP |= DP_SYNC_HS_HIGH;
1353 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1354 intel_dp->DP |= DP_SYNC_VS_HIGH;
1355 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1356
6aba5b6c 1357 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1358 intel_dp->DP |= DP_ENHANCED_FRAMING;
1359
44f37d1f
CML		 1360 if (!IS_CHERRYVIEW(dev)) {
1361 if (crtc->pipe == 1)
1362 intel_dp->DP |= DP_PIPEB_SELECT;
1363 } else {
1364 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1365 }
417e822d
KP		 1366 } else {
1367 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1368 }
a4fc5ed6
KP		 1369}
1370
ffd6749d
PZ		 1371#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1372#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1373
1a5ef5b7
PZ		 1374#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1375#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1376
ffd6749d
PZ		 1377#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1378#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1379
4be73780 1380static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1381 u32 mask,
1382 u32 value)
bd943159 1383{
30add22d 1384 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1385 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1386 u32 pp_stat_reg, pp_ctrl_reg;
1387
e39b999a
VS		 1388 lockdep_assert_held(&dev_priv->pps_mutex);
1389
bf13e81b
JN		 1390 pp_stat_reg = _pp_stat_reg(intel_dp);
1391 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1392
99ea7127 1393 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1394 mask, value,
1395 I915_READ(pp_stat_reg),
1396 I915_READ(pp_ctrl_reg));
32ce697c 1397
453c5420 1398 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1399 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1400 I915_READ(pp_stat_reg),
1401 I915_READ(pp_ctrl_reg));
32ce697c 1402 }
54c136d4
CW		 1403
1404 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1405}
32ce697c 1406
4be73780 1407static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1408{
1409 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1410 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1411}
1412
4be73780 1413static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1414{
1415 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1416 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1417}
1418
4be73780 1419static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1420{
1421 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1422
1423 /* When we disable the VDD override bit last we have to do the manual
1424 * wait. */
1425 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1426 intel_dp->panel_power_cycle_delay);
1427
4be73780 1428 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1429}
1430
4be73780 1431static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1432{
1433 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1434 intel_dp->backlight_on_delay);
1435}
1436
4be73780 1437static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1438{
1439 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1440 intel_dp->backlight_off_delay);
1441}
99ea7127 1442
832dd3c1
KP		 1443/* Read the current pp_control value, unlocking the register if it
1444 * is locked
1445 */
1446
453c5420 1447static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1448{
453c5420
JB		 1449 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1450 struct drm_i915_private *dev_priv = dev->dev_private;
1451 u32 control;
832dd3c1 1452
e39b999a
VS		 1453 lockdep_assert_held(&dev_priv->pps_mutex);
1454
bf13e81b 1455 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1456 control &= ~PANEL_UNLOCK_MASK;
1457 control |= PANEL_UNLOCK_REGS;
1458 return control;
bd943159
KP		 1459}
1460
951468f3
VS		 1461/*
1462 * Must be paired with edp_panel_vdd_off().
1463 * Must hold pps_mutex around the whole on/off sequence.
1464 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1465 */
1e0560e0 1466static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1467{
30add22d 1468 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1469 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1470 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1471 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1472 enum intel_display_power_domain power_domain;
5d613501 1473 u32 pp;
453c5420 1474 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1475 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1476
e39b999a
VS		 1477 lockdep_assert_held(&dev_priv->pps_mutex);
1478
97af61f5 1479 if (!is_edp(intel_dp))
adddaaf4 1480 return false;
bd943159
KP		 1481
1482 intel_dp->want_panel_vdd = true;
99ea7127 1483
4be73780 1484 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1485 return need_to_disable;
b0665d57 1486
4e6e1a54
ID		 1487 power_domain = intel_display_port_power_domain(intel_encoder);
1488 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1489
3936fcf4
VS		 1490 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1491 port_name(intel_dig_port->port));
bd943159 1492
4be73780
DV		 1493 if (!edp_have_panel_power(intel_dp))
1494 wait_panel_power_cycle(intel_dp);
99ea7127 1495
453c5420 1496 pp = ironlake_get_pp_control(intel_dp);
5d613501 1497 pp |= EDP_FORCE_VDD;
ebf33b18 1498
bf13e81b
JN		 1499 pp_stat_reg = _pp_stat_reg(intel_dp);
1500 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1501
1502 I915_WRITE(pp_ctrl_reg, pp);
1503 POSTING_READ(pp_ctrl_reg);
1504 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1505 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1506 /*
1507 * If the panel wasn't on, delay before accessing aux channel
1508 */
4be73780 1509 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1510 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1511 port_name(intel_dig_port->port));
f01eca2e 1512 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1513 }
adddaaf4
JN		 1514
1515 return need_to_disable;
1516}
1517
951468f3
VS		 1518/*
1519 * Must be paired with intel_edp_panel_vdd_off() or
1520 * intel_edp_panel_off().
1521 * Nested calls to these functions are not allowed since
1522 * we drop the lock. Caller must use some higher level
1523 * locking to prevent nested calls from other threads.
1524 */
b80d6c78 1525void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1526{
c695b6b6 1527 bool vdd;
adddaaf4 1528
c695b6b6
VS		 1529 if (!is_edp(intel_dp))
1530 return;
1531
773538e8 1532 pps_lock(intel_dp);
c695b6b6 1533 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1534 pps_unlock(intel_dp);
c695b6b6 1535
3936fcf4
VS		 1536 WARN(!vdd, "eDP port %c VDD already requested on\n",
1537 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1538}
1539
4be73780 1540static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1541{
30add22d 1542 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1543 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1544 struct intel_digital_port *intel_dig_port =
1545 dp_to_dig_port(intel_dp);
1546 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1547 enum intel_display_power_domain power_domain;
5d613501 1548 u32 pp;
453c5420 1549 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1550
e39b999a 1551 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1552
15e899a0 1553 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1554
15e899a0 1555 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1556 return;
b0665d57 1557
3936fcf4
VS		 1558 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1559 port_name(intel_dig_port->port));
bd943159 1560
be2c9196
VS		 1561 pp = ironlake_get_pp_control(intel_dp);
1562 pp &= ~EDP_FORCE_VDD;
453c5420 1563
be2c9196
VS		 1564 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1565 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1566
be2c9196
VS		 1567 I915_WRITE(pp_ctrl_reg, pp);
1568 POSTING_READ(pp_ctrl_reg);
90791a5c 1569
be2c9196
VS		 1570 /* Make sure sequencer is idle before allowing subsequent activity */
1571 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1572 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1573
be2c9196
VS		 1574 if ((pp & POWER_TARGET_ON) == 0)
1575 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1576
be2c9196
VS		 1577 power_domain = intel_display_port_power_domain(intel_encoder);
1578 intel_display_power_put(dev_priv, power_domain);
bd943159 1579}
5d613501 1580
4be73780 1581static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1582{
1583 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1584 struct intel_dp, panel_vdd_work);
bd943159 1585
773538e8 1586 pps_lock(intel_dp);
15e899a0
VS		 1587 if (!intel_dp->want_panel_vdd)
1588 edp_panel_vdd_off_sync(intel_dp);
773538e8 1589 pps_unlock(intel_dp);
bd943159
KP		 1590}
1591
aba86890
ID		 1592static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1593{
1594 unsigned long delay;
1595
1596 /*
1597 * Queue the timer to fire a long time from now (relative to the power
1598 * down delay) to keep the panel power up across a sequence of
1599 * operations.
1600 */
1601 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1602 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1603}
1604
951468f3
VS		 1605/*
1606 * Must be paired with edp_panel_vdd_on().
1607 * Must hold pps_mutex around the whole on/off sequence.
1608 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1609 */
4be73780 1610static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1611{
e39b999a
VS		 1612 struct drm_i915_private *dev_priv =
1613 intel_dp_to_dev(intel_dp)->dev_private;
1614
1615 lockdep_assert_held(&dev_priv->pps_mutex);
1616
97af61f5
KP		 1617 if (!is_edp(intel_dp))
1618 return;
5d613501 1619
3936fcf4
VS		 1620 WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
1621 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1622
bd943159
KP		 1623 intel_dp->want_panel_vdd = false;
1624
aba86890 1625 if (sync)
4be73780 1626 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1627 else
1628 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1629}
1630
9f0fb5be 1631static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1632{
30add22d 1633 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1634 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1635 u32 pp;
453c5420 1636 u32 pp_ctrl_reg;
9934c132 1637
9f0fb5be
VS		 1638 lockdep_assert_held(&dev_priv->pps_mutex);
1639
97af61f5 1640 if (!is_edp(intel_dp))
bd943159 1641 return;
99ea7127 1642
3936fcf4
VS		 1643 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1644 port_name(dp_to_dig_port(intel_dp)->port));
99ea7127 1645
e7a89ace
VS		 1646 if (WARN(edp_have_panel_power(intel_dp),
1647 "eDP port %c panel power already on\n",
1648 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1649 return;
9934c132 1650
4be73780 1651 wait_panel_power_cycle(intel_dp);
37c6c9b0 1652
bf13e81b 1653 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1654 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1655 if (IS_GEN5(dev)) {
1656 /* ILK workaround: disable reset around power sequence */
1657 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1658 I915_WRITE(pp_ctrl_reg, pp);
1659 POSTING_READ(pp_ctrl_reg);
05ce1a49 1660 }
37c6c9b0 1661
1c0ae80a 1662 pp |= POWER_TARGET_ON;
99ea7127
KP		 1663 if (!IS_GEN5(dev))
1664 pp |= PANEL_POWER_RESET;
1665
453c5420
JB		 1666 I915_WRITE(pp_ctrl_reg, pp);
1667 POSTING_READ(pp_ctrl_reg);
9934c132 1668
4be73780 1669 wait_panel_on(intel_dp);
dce56b3c 1670 intel_dp->last_power_on = jiffies;
9934c132 1671
05ce1a49
KP		 1672 if (IS_GEN5(dev)) {
1673 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1674 I915_WRITE(pp_ctrl_reg, pp);
1675 POSTING_READ(pp_ctrl_reg);
05ce1a49 1676 }
9f0fb5be 1677}
e39b999a 1678
9f0fb5be
VS		 1679void intel_edp_panel_on(struct intel_dp *intel_dp)
1680{
1681 if (!is_edp(intel_dp))
1682 return;
1683
1684 pps_lock(intel_dp);
1685 edp_panel_on(intel_dp);
773538e8 1686 pps_unlock(intel_dp);
9934c132
JB		 1687}
1688
9f0fb5be
VS		 1689
1690static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1691{
4e6e1a54
ID		 1692 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1693 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1694 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1695 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1696 enum intel_display_power_domain power_domain;
99ea7127 1697 u32 pp;
453c5420 1698 u32 pp_ctrl_reg;
9934c132 1699
9f0fb5be
VS		 1700 lockdep_assert_held(&dev_priv->pps_mutex);
1701
97af61f5
KP		 1702 if (!is_edp(intel_dp))
1703 return;
37c6c9b0 1704
3936fcf4
VS		 1705 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1706 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 1707
3936fcf4
VS		 1708 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1709 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 1710
453c5420 1711 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1712 /* We need to switch off panel power _and_ force vdd, for otherwise some
1713 * panels get very unhappy and cease to work. */
b3064154
PJ		 1714 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1715 EDP_BLC_ENABLE);
453c5420 1716
bf13e81b 1717 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1718
849e39f5
PZ		 1719 intel_dp->want_panel_vdd = false;
1720
453c5420
JB		 1721 I915_WRITE(pp_ctrl_reg, pp);
1722 POSTING_READ(pp_ctrl_reg);
9934c132 1723
dce56b3c 1724 intel_dp->last_power_cycle = jiffies;
4be73780 1725 wait_panel_off(intel_dp);
849e39f5
PZ		 1726
1727 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1728 power_domain = intel_display_port_power_domain(intel_encoder);
1729 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1730}
e39b999a 1731
9f0fb5be
VS		 1732void intel_edp_panel_off(struct intel_dp *intel_dp)
1733{
1734 if (!is_edp(intel_dp))
1735 return;
1736
1737 pps_lock(intel_dp);
1738 edp_panel_off(intel_dp);
773538e8 1739 pps_unlock(intel_dp);
9934c132
JB		 1740}
1741
1250d107
JN		 1742/* Enable backlight in the panel power control. */
1743static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1744{
da63a9f2
PZ		 1745 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1746 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1747 struct drm_i915_private *dev_priv = dev->dev_private;
1748 u32 pp;
453c5420 1749 u32 pp_ctrl_reg;
32f9d658 1750
01cb9ea6
JB		 1751 /*
1752 * If we enable the backlight right away following a panel power
1753 * on, we may see slight flicker as the panel syncs with the eDP
1754 * link. So delay a bit to make sure the image is solid before
1755 * allowing it to appear.
1756 */
4be73780 1757 wait_backlight_on(intel_dp);
e39b999a 1758
773538e8 1759 pps_lock(intel_dp);
e39b999a 1760
453c5420 1761 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1762 pp |= EDP_BLC_ENABLE;
453c5420 1763
bf13e81b 1764 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1765
1766 I915_WRITE(pp_ctrl_reg, pp);
1767 POSTING_READ(pp_ctrl_reg);
e39b999a 1768
773538e8 1769 pps_unlock(intel_dp);
32f9d658
ZW		 1770}
1771
1250d107
JN		 1772/* Enable backlight PWM and backlight PP control. */
1773void intel_edp_backlight_on(struct intel_dp *intel_dp)
1774{
1775 if (!is_edp(intel_dp))
1776 return;
1777
1778 DRM_DEBUG_KMS("\n");
1779
1780 intel_panel_enable_backlight(intel_dp->attached_connector);
1781 _intel_edp_backlight_on(intel_dp);
1782}
1783
1784/* Disable backlight in the panel power control. */
1785static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1786{
30add22d 1787 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1788 struct drm_i915_private *dev_priv = dev->dev_private;
1789 u32 pp;
453c5420 1790 u32 pp_ctrl_reg;
32f9d658 1791
f01eca2e
KP		 1792 if (!is_edp(intel_dp))
1793 return;
1794
773538e8 1795 pps_lock(intel_dp);
e39b999a 1796
453c5420 1797 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1798 pp &= ~EDP_BLC_ENABLE;
453c5420 1799
bf13e81b 1800 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1801
1802 I915_WRITE(pp_ctrl_reg, pp);
1803 POSTING_READ(pp_ctrl_reg);
f7d2323c 1804
773538e8 1805 pps_unlock(intel_dp);
e39b999a
VS		 1806
1807 intel_dp->last_backlight_off = jiffies;
f7d2323c 1808 edp_wait_backlight_off(intel_dp);
1250d107 1809}
f7d2323c 1810
1250d107
JN		 1811/* Disable backlight PP control and backlight PWM. */
1812void intel_edp_backlight_off(struct intel_dp *intel_dp)
1813{
1814 if (!is_edp(intel_dp))
1815 return;
1816
1817 DRM_DEBUG_KMS("\n");
f7d2323c 1818
1250d107 1819 _intel_edp_backlight_off(intel_dp);
f7d2323c 1820 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1821}
a4fc5ed6 1822
73580fb7
JN		 1823/*
1824 * Hook for controlling the panel power control backlight through the bl_power
1825 * sysfs attribute. Take care to handle multiple calls.
1826 */
1827static void intel_edp_backlight_power(struct intel_connector *connector,
1828 bool enable)
1829{
1830 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1831 bool is_enabled;
1832
773538e8 1833 pps_lock(intel_dp);
e39b999a 1834 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1835 pps_unlock(intel_dp);
73580fb7
JN		 1836
1837 if (is_enabled == enable)
1838 return;
1839
23ba9373
JN		 1840 DRM_DEBUG_KMS("panel power control backlight %s\n",
1841 enable ? "enable" : "disable");
73580fb7
JN		 1842
1843 if (enable)
1844 _intel_edp_backlight_on(intel_dp);
1845 else
1846 _intel_edp_backlight_off(intel_dp);
1847}
1848
2bd2ad64 1849static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1850{
da63a9f2
PZ		 1851 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1852 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1853 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1854 struct drm_i915_private *dev_priv = dev->dev_private;
1855 u32 dpa_ctl;
1856
2bd2ad64
DV		 1857 assert_pipe_disabled(dev_priv,
1858 to_intel_crtc(crtc)->pipe);
1859
d240f20f
JB		 1860 DRM_DEBUG_KMS("\n");
1861 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1862 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1863 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1864
1865 /* We don't adjust intel_dp->DP while tearing down the link, to
1866 * facilitate link retraining (e.g. after hotplug). Hence clear all
1867 * enable bits here to ensure that we don't enable too much. */
1868 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1869 intel_dp->DP |= DP_PLL_ENABLE;
1870 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1871 POSTING_READ(DP_A);
1872 udelay(200);
d240f20f
JB		 1873}
1874
2bd2ad64 1875static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1876{
da63a9f2
PZ		 1877 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1878 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1879 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1880 struct drm_i915_private *dev_priv = dev->dev_private;
1881 u32 dpa_ctl;
1882
2bd2ad64
DV		 1883 assert_pipe_disabled(dev_priv,
1884 to_intel_crtc(crtc)->pipe);
1885
d240f20f 1886 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1887 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1888 "dp pll off, should be on\n");
1889 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1890
1891 /* We can't rely on the value tracked for the DP register in
1892 * intel_dp->DP because link_down must not change that (otherwise link
1893 * re-training will fail. */
298b0b39 1894 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1895 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1896 POSTING_READ(DP_A);
d240f20f
JB		 1897 udelay(200);
1898}
1899
c7ad3810 1900/* If the sink supports it, try to set the power state appropriately */
c19b0669 1901void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1902{
1903 int ret, i;
1904
1905 /* Should have a valid DPCD by this point */
1906 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1907 return;
1908
1909 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1910 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1911 DP_SET_POWER_D3);
c7ad3810
JB		 1912 } else {
1913 /*
1914 * When turning on, we need to retry for 1ms to give the sink
1915 * time to wake up.
1916 */
1917 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1918 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1919 DP_SET_POWER_D0);
c7ad3810
JB		 1920 if (ret == 1)
1921 break;
1922 msleep(1);
1923 }
1924 }
f9cac721
JN		 1925
1926 if (ret != 1)
1927 DRM_DEBUG_KMS("failed to %s sink power state\n",
1928 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1929}
1930
19d8fe15
DV		 1931static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1932 enum pipe *pipe)
d240f20f 1933{
19d8fe15 1934 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1935 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1936 struct drm_device *dev = encoder->base.dev;
1937 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1938 enum intel_display_power_domain power_domain;
1939 u32 tmp;
1940
1941 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1942 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1943 return false;
1944
1945 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1946
1947 if (!(tmp & DP_PORT_EN))
1948 return false;
1949
bc7d38a4 1950 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1951 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1952 } else if (IS_CHERRYVIEW(dev)) {
1953 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1954 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1955 *pipe = PORT_TO_PIPE(tmp);
1956 } else {
1957 u32 trans_sel;
1958 u32 trans_dp;
1959 int i;
1960
1961 switch (intel_dp->output_reg) {
1962 case PCH_DP_B:
1963 trans_sel = TRANS_DP_PORT_SEL_B;
1964 break;
1965 case PCH_DP_C:
1966 trans_sel = TRANS_DP_PORT_SEL_C;
1967 break;
1968 case PCH_DP_D:
1969 trans_sel = TRANS_DP_PORT_SEL_D;
1970 break;
1971 default:
1972 return true;
1973 }
1974
055e393f 1975 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1976 trans_dp = I915_READ(TRANS_DP_CTL(i));
1977 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1978 *pipe = i;
1979 return true;
1980 }
1981 }
19d8fe15 1982
4a0833ec
DV		 1983 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1984 intel_dp->output_reg);
1985 }
d240f20f 1986
19d8fe15
DV		 1987 return true;
1988}
d240f20f 1989
045ac3b5
JB		 1990static void intel_dp_get_config(struct intel_encoder *encoder,
1991 struct intel_crtc_config *pipe_config)
1992{
1993 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1994 u32 tmp, flags = 0;
63000ef6
XZ		 1995 struct drm_device *dev = encoder->base.dev;
1996 struct drm_i915_private *dev_priv = dev->dev_private;
1997 enum port port = dp_to_dig_port(intel_dp)->port;
1998 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1999 int dotclock;
045ac3b5 2000
9ed109a7
DV		 2001 tmp = I915_READ(intel_dp->output_reg);
2002 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2003 pipe_config->has_audio = true;
2004
63000ef6 2005 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 2006 if (tmp & DP_SYNC_HS_HIGH)
2007 flags |= DRM_MODE_FLAG_PHSYNC;
2008 else
2009 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2010
63000ef6
XZ		 2011 if (tmp & DP_SYNC_VS_HIGH)
2012 flags |= DRM_MODE_FLAG_PVSYNC;
2013 else
2014 flags |= DRM_MODE_FLAG_NVSYNC;
2015 } else {
2016 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2017 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2018 flags |= DRM_MODE_FLAG_PHSYNC;
2019 else
2020 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2021
63000ef6
XZ		 2022 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2023 flags |= DRM_MODE_FLAG_PVSYNC;
2024 else
2025 flags |= DRM_MODE_FLAG_NVSYNC;
2026 }
045ac3b5
JB		 2027
2028 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 2029
8c875fca
VS		 2030 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2031 tmp & DP_COLOR_RANGE_16_235)
2032 pipe_config->limited_color_range = true;
2033
eb14cb74
VS		 2034 pipe_config->has_dp_encoder = true;
2035
2036 intel_dp_get_m_n(crtc, pipe_config);
2037
18442d08 2038 if (port == PORT_A) {
f1f644dc
JB		 2039 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2040 pipe_config->port_clock = 162000;
2041 else
2042 pipe_config->port_clock = 270000;
2043 }
18442d08
VS		 2044
2045 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2046 &pipe_config->dp_m_n);
2047
2048 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2049 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2050
241bfc38 2051 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2052
c6cd2ee2
JN		 2053 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2054 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2055 /*
2056 * This is a big fat ugly hack.
2057 *
2058 * Some machines in UEFI boot mode provide us a VBT that has 18
2059 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2060 * unknown we fail to light up. Yet the same BIOS boots up with
2061 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2062 * max, not what it tells us to use.
2063 *
2064 * Note: This will still be broken if the eDP panel is not lit
2065 * up by the BIOS, and thus we can't get the mode at module
2066 * load.
2067 */
2068 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2069 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2070 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2071 }
045ac3b5
JB		 2072}
2073
34eb7579 2074static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 2075{
34eb7579 2076 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 2077}
2078
2b28bb1b
RV		 2079static bool intel_edp_is_psr_enabled(struct drm_device *dev)
2080{
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082
18b5992c 2083 if (!HAS_PSR(dev))
2b28bb1b
RV		 2084 return false;
2085
18b5992c 2086 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 2087}
2088
2089static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
2090 struct edp_vsc_psr *vsc_psr)
2091{
2092 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2093 struct drm_device *dev = dig_port->base.base.dev;
2094 struct drm_i915_private *dev_priv = dev->dev_private;
2095 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
2096 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
2097 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
2098 uint32_t *data = (uint32_t *) vsc_psr;
2099 unsigned int i;
2100
2101 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2102 the video DIP being updated before program video DIP data buffer
2103 registers for DIP being updated. */
2104 I915_WRITE(ctl_reg, 0);
2105 POSTING_READ(ctl_reg);
2106
2107 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
2108 if (i < sizeof(struct edp_vsc_psr))
2109 I915_WRITE(data_reg + i, *data++);
2110 else
2111 I915_WRITE(data_reg + i, 0);
2112 }
2113
2114 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
2115 POSTING_READ(ctl_reg);
2116}
2117
ba80f4d4 2118static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
2b28bb1b 2119{
2b28bb1b
RV		 2120 struct edp_vsc_psr psr_vsc;
2121
2b28bb1b
RV		 2122 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2123 memset(&psr_vsc, 0, sizeof(psr_vsc));
2124 psr_vsc.sdp_header.HB0 = 0;
2125 psr_vsc.sdp_header.HB1 = 0x7;
2126 psr_vsc.sdp_header.HB2 = 0x2;
2127 psr_vsc.sdp_header.HB3 = 0x8;
2128 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2b28bb1b
RV		 2129}
2130
2131static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2132{
0e0ae652
RV		 2133 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2134 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2135 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2136 uint32_t aux_clock_divider;
2b28bb1b 2137 int precharge = 0x3;
0e0ae652 2138 bool only_standby = false;
5ca476f8
VS		 2139 static const uint8_t aux_msg[] = {
2140 [0] = DP_AUX_NATIVE_WRITE << 4,
2141 [1] = DP_SET_POWER >> 8,
2142 [2] = DP_SET_POWER & 0xff,
2143 [3] = 1 - 1,
2144 [4] = DP_SET_POWER_D0,
2145 };
2146 int i;
2147
2148 BUILD_BUG_ON(sizeof(aux_msg) > 20);
2b28bb1b 2149
ec5b01dd
DL		 2150 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2151
0e0ae652
RV		 2152 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2153 only_standby = true;
2154
2b28bb1b 2155 /* Enable PSR in sink */
0e0ae652 2156 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2157 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2158 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2159 else
9d1a1031
JN		 2160 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2161 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2162
2163 /* Setup AUX registers */
5ca476f8
VS		 2164 for (i = 0; i < sizeof(aux_msg); i += 4)
2165 I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
2166 pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
2167
18b5992c 2168 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b 2169 DP_AUX_CH_CTL_TIME_OUT_400us |
5ca476f8 2170 (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2b28bb1b
RV		 2171 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2172 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2173}
2174
2175static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2176{
0e0ae652
RV		 2177 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2178 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 uint32_t max_sleep_time = 0x1f;
2181 uint32_t idle_frames = 1;
2182 uint32_t val = 0x0;
ed8546ac 2183 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2184 bool only_standby = false;
2185
2186 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2187 only_standby = true;
2b28bb1b 2188
0e0ae652 2189 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2190 val |= EDP_PSR_LINK_STANDBY;
2191 val |= EDP_PSR_TP2_TP3_TIME_0us;
2192 val |= EDP_PSR_TP1_TIME_0us;
2193 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2194 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2195 } else
2196 val |= EDP_PSR_LINK_DISABLE;
2197
18b5992c 2198 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2199 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2200 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2201 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2202 EDP_PSR_ENABLE);
2203}
2204
3f51e471
RV		 2205static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2206{
2207 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2208 struct drm_device *dev = dig_port->base.base.dev;
2209 struct drm_i915_private *dev_priv = dev->dev_private;
2210 struct drm_crtc *crtc = dig_port->base.base.crtc;
2211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2212
f0355c4a 2213 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2214 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2215 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2216
a031d709
RV		 2217 dev_priv->psr.source_ok = false;
2218
9ca15301 2219 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2220 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2221 return false;
2222 }
2223
d330a953 2224 if (!i915.enable_psr) {
105b7c11 2225 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2226 return false;
2227 }
2228
4c8c7000
RV		 2229 /* Below limitations aren't valid for Broadwell */
2230 if (IS_BROADWELL(dev))
2231 goto out;
2232
3f51e471
RV		 2233 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2234 S3D_ENABLE) {
2235 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2236 return false;
2237 }
2238
ca73b4f0 2239 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2240 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2241 return false;
2242 }
2243
4c8c7000 2244 out:
a031d709 2245 dev_priv->psr.source_ok = true;
3f51e471
RV		 2246 return true;
2247}
2248
3d739d92 2249static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2250{
7c8f8a70
RV		 2251 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2252 struct drm_device *dev = intel_dig_port->base.base.dev;
2253 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2254
3638379c
DV		 2255 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2256 WARN_ON(dev_priv->psr.active);
f0355c4a 2257 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2258
7ca5a41f 2259 /* Enable/Re-enable PSR on the host */
2b28bb1b 2260 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2261
7c8f8a70 2262 dev_priv->psr.active = true;
2b28bb1b
RV		 2263}
2264
3d739d92
RV		 2265void intel_edp_psr_enable(struct intel_dp *intel_dp)
2266{
2267 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2268 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2269
4704c573
RV		 2270 if (!HAS_PSR(dev)) {
2271 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2272 return;
2273 }
2274
34eb7579
RV		 2275 if (!is_edp_psr(intel_dp)) {
2276 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2277 return;
2278 }
2279
f0355c4a 2280 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2281 if (dev_priv->psr.enabled) {
2282 DRM_DEBUG_KMS("PSR already in use\n");
0aa48783 2283 goto unlock;
109fc2ad
DV		 2284 }
2285
0aa48783
RV		 2286 if (!intel_edp_psr_match_conditions(intel_dp))
2287 goto unlock;
2288
9ca15301
DV		 2289 dev_priv->psr.busy_frontbuffer_bits = 0;
2290
ba80f4d4 2291 intel_edp_psr_setup_vsc(intel_dp);
16487254 2292
ba80f4d4
RV		 2293 /* Avoid continuous PSR exit by masking memup and hpd */
2294 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2295 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
16487254 2296
7ca5a41f
RV		 2297 /* Enable PSR on the panel */
2298 intel_edp_psr_enable_sink(intel_dp);
2299
0aa48783
RV		 2300 dev_priv->psr.enabled = intel_dp;
2301unlock:
f0355c4a 2302 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2303}
2304
2b28bb1b
RV		 2305void intel_edp_psr_disable(struct intel_dp *intel_dp)
2306{
2307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2308 struct drm_i915_private *dev_priv = dev->dev_private;
2309
f0355c4a
DV		 2310 mutex_lock(&dev_priv->psr.lock);
2311 if (!dev_priv->psr.enabled) {
2312 mutex_unlock(&dev_priv->psr.lock);
2313 return;
2314 }
2315
3638379c
DV		 2316 if (dev_priv->psr.active) {
2317 I915_WRITE(EDP_PSR_CTL(dev),
2318 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2319
2320 /* Wait till PSR is idle */
2321 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2322 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2323 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2324
3638379c
DV		 2325 dev_priv->psr.active = false;
2326 } else {
2327 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2328 }
7c8f8a70 2329
2807cf69 2330 dev_priv->psr.enabled = NULL;
f0355c4a 2331 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2332
2333 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2334}
2335
f02a326e 2336static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2337{
2338 struct drm_i915_private *dev_priv =
2339 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2340 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2341
8d7f4fe9
RV		 2342 /* We have to make sure PSR is ready for re-enable
2343 * otherwise it keeps disabled until next full enable/disable cycle.
2344 * PSR might take some time to get fully disabled
2345 * and be ready for re-enable.
2346 */
2347 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
2348 EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
2349 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2350 return;
2351 }
2352
f0355c4a
DV		 2353 mutex_lock(&dev_priv->psr.lock);
2354 intel_dp = dev_priv->psr.enabled;
2355
2807cf69 2356 if (!intel_dp)
f0355c4a 2357 goto unlock;
2807cf69 2358
9ca15301
DV		 2359 /*
2360 * The delayed work can race with an invalidate hence we need to
2361 * recheck. Since psr_flush first clears this and then reschedules we
2362 * won't ever miss a flush when bailing out here.
2363 */
2364 if (dev_priv->psr.busy_frontbuffer_bits)
2365 goto unlock;
2366
2367 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2368unlock:
2369 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2370}
2371
9ca15301 2372static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2373{
2374 struct drm_i915_private *dev_priv = dev->dev_private;
2375
3638379c
DV		 2376 if (dev_priv->psr.active) {
2377 u32 val = I915_READ(EDP_PSR_CTL(dev));
2378
2379 WARN_ON(!(val & EDP_PSR_ENABLE));
2380
2381 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2382
2383 dev_priv->psr.active = false;
2384 }
7c8f8a70 2385
9ca15301
DV		 2386}
2387
2388void intel_edp_psr_invalidate(struct drm_device *dev,
2389 unsigned frontbuffer_bits)
2390{
2391 struct drm_i915_private *dev_priv = dev->dev_private;
2392 struct drm_crtc *crtc;
2393 enum pipe pipe;
2394
9ca15301
DV		 2395 mutex_lock(&dev_priv->psr.lock);
2396 if (!dev_priv->psr.enabled) {
2397 mutex_unlock(&dev_priv->psr.lock);
2398 return;
2399 }
2400
2401 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2402 pipe = to_intel_crtc(crtc)->pipe;
2403
2404 intel_edp_psr_do_exit(dev);
2405
2406 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2407
2408 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2409 mutex_unlock(&dev_priv->psr.lock);
2410}
2411
2412void intel_edp_psr_flush(struct drm_device *dev,
2413 unsigned frontbuffer_bits)
2414{
2415 struct drm_i915_private *dev_priv = dev->dev_private;
2416 struct drm_crtc *crtc;
2417 enum pipe pipe;
2418
9ca15301
DV		 2419 mutex_lock(&dev_priv->psr.lock);
2420 if (!dev_priv->psr.enabled) {
2421 mutex_unlock(&dev_priv->psr.lock);
2422 return;
2423 }
2424
2425 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2426 pipe = to_intel_crtc(crtc)->pipe;
2427 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2428
2429 /*
2430 * On Haswell sprite plane updates don't result in a psr invalidating
2431 * signal in the hardware. Which means we need to manually fake this in
2432 * software for all flushes, not just when we've seen a preceding
2433 * invalidation through frontbuffer rendering.
2434 */
2435 if (IS_HASWELL(dev) &&
2436 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2437 intel_edp_psr_do_exit(dev);
2438
2439 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2440 schedule_delayed_work(&dev_priv->psr.work,
2441 msecs_to_jiffies(100));
f0355c4a 2442 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2443}
2444
2445void intel_edp_psr_init(struct drm_device *dev)
2446{
2447 struct drm_i915_private *dev_priv = dev->dev_private;
2448
7c8f8a70 2449 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2450 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2451}
2452
e8cb4558 2453static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2454{
e8cb4558 2455 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2456 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2457
2458 /* Make sure the panel is off before trying to change the mode. But also
2459 * ensure that we have vdd while we switch off the panel. */
24f3e092 2460 intel_edp_panel_vdd_on(intel_dp);
4be73780 2461 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2462 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2463 intel_edp_panel_off(intel_dp);
3739850b 2464
08aff3fe
VS		 2465 /* disable the port before the pipe on g4x */
2466 if (INTEL_INFO(dev)->gen < 5)
3739850b 2467 intel_dp_link_down(intel_dp);
d240f20f
JB		 2468}
2469
08aff3fe 2470static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2471{
2bd2ad64 2472 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2473 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2474
49277c31 2475 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2476 if (port == PORT_A)
2477 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2478}
2479
2480static void vlv_post_disable_dp(struct intel_encoder *encoder)
2481{
2482 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2483
2484 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2485}
2486
580d3811
VS		 2487static void chv_post_disable_dp(struct intel_encoder *encoder)
2488{
2489 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2490 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2491 struct drm_device *dev = encoder->base.dev;
2492 struct drm_i915_private *dev_priv = dev->dev_private;
2493 struct intel_crtc *intel_crtc =
2494 to_intel_crtc(encoder->base.crtc);
2495 enum dpio_channel ch = vlv_dport_to_channel(dport);
2496 enum pipe pipe = intel_crtc->pipe;
2497 u32 val;
2498
2499 intel_dp_link_down(intel_dp);
2500
2501 mutex_lock(&dev_priv->dpio_lock);
2502
2503 /* Propagate soft reset to data lane reset */
97fd4d5c 2504 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2505 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2506 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2507
97fd4d5c
VS		 2508 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2509 val |= CHV_PCS_REQ_SOFTRESET_EN;
2510 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2511
2512 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2513 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2514 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2515
2516 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2517 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2518 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2519
2520 mutex_unlock(&dev_priv->dpio_lock);
2521}
2522
7b13b58a
VS		 2523static void
2524_intel_dp_set_link_train(struct intel_dp *intel_dp,
2525 uint32_t *DP,
2526 uint8_t dp_train_pat)
2527{
2528 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2529 struct drm_device *dev = intel_dig_port->base.base.dev;
2530 struct drm_i915_private *dev_priv = dev->dev_private;
2531 enum port port = intel_dig_port->port;
2532
2533 if (HAS_DDI(dev)) {
2534 uint32_t temp = I915_READ(DP_TP_CTL(port));
2535
2536 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2537 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2538 else
2539 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2540
2541 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2542 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2543 case DP_TRAINING_PATTERN_DISABLE:
2544 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2545
2546 break;
2547 case DP_TRAINING_PATTERN_1:
2548 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2549 break;
2550 case DP_TRAINING_PATTERN_2:
2551 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2552 break;
2553 case DP_TRAINING_PATTERN_3:
2554 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2555 break;
2556 }
2557 I915_WRITE(DP_TP_CTL(port), temp);
2558
2559 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2560 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2561
2562 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2563 case DP_TRAINING_PATTERN_DISABLE:
2564 *DP |= DP_LINK_TRAIN_OFF_CPT;
2565 break;
2566 case DP_TRAINING_PATTERN_1:
2567 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2568 break;
2569 case DP_TRAINING_PATTERN_2:
2570 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2571 break;
2572 case DP_TRAINING_PATTERN_3:
2573 DRM_ERROR("DP training pattern 3 not supported\n");
2574 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2575 break;
2576 }
2577
2578 } else {
2579 if (IS_CHERRYVIEW(dev))
2580 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2581 else
2582 *DP &= ~DP_LINK_TRAIN_MASK;
2583
2584 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2585 case DP_TRAINING_PATTERN_DISABLE:
2586 *DP |= DP_LINK_TRAIN_OFF;
2587 break;
2588 case DP_TRAINING_PATTERN_1:
2589 *DP |= DP_LINK_TRAIN_PAT_1;
2590 break;
2591 case DP_TRAINING_PATTERN_2:
2592 *DP |= DP_LINK_TRAIN_PAT_2;
2593 break;
2594 case DP_TRAINING_PATTERN_3:
2595 if (IS_CHERRYVIEW(dev)) {
2596 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2597 } else {
2598 DRM_ERROR("DP training pattern 3 not supported\n");
2599 *DP |= DP_LINK_TRAIN_PAT_2;
2600 }
2601 break;
2602 }
2603 }
2604}
2605
2606static void intel_dp_enable_port(struct intel_dp *intel_dp)
2607{
2608 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2609 struct drm_i915_private *dev_priv = dev->dev_private;
2610
7b13b58a
VS		 2611 /* enable with pattern 1 (as per spec) */
2612 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2613 DP_TRAINING_PATTERN_1);
2614
2615 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2616 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2617
2618 /*
2619 * Magic for VLV/CHV. We _must_ first set up the register
2620 * without actually enabling the port, and then do another
2621 * write to enable the port. Otherwise link training will
2622 * fail when the power sequencer is freshly used for this port.
2623 */
2624 intel_dp->DP |= DP_PORT_EN;
2625
2626 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2627 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2628}
2629
e8cb4558 2630static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2631{
e8cb4558
DV		 2632 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2633 struct drm_device *dev = encoder->base.dev;
2634 struct drm_i915_private *dev_priv = dev->dev_private;
2635 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2636
0c33d8d7
DV		 2637 if (WARN_ON(dp_reg & DP_PORT_EN))
2638 return;
5d613501 2639
093e3f13
VS		 2640 pps_lock(intel_dp);
2641
2642 if (IS_VALLEYVIEW(dev))
2643 vlv_init_panel_power_sequencer(intel_dp);
2644
7b13b58a 2645 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2646
2647 edp_panel_vdd_on(intel_dp);
2648 edp_panel_on(intel_dp);
2649 edp_panel_vdd_off(intel_dp, true);
2650
2651 pps_unlock(intel_dp);
2652
61234fa5
VS		 2653 if (IS_VALLEYVIEW(dev))
2654 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2655
f01eca2e 2656 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2657 intel_dp_start_link_train(intel_dp);
33a34e4e 2658 intel_dp_complete_link_train(intel_dp);
3ab9c637 2659 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2660}
89b667f8 2661
ecff4f3b
JN		 2662static void g4x_enable_dp(struct intel_encoder *encoder)
2663{
828f5c6e
JN		 2664 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2665
ecff4f3b 2666 intel_enable_dp(encoder);
4be73780 2667 intel_edp_backlight_on(intel_dp);
ab1f90f9 2668}
89b667f8 2669
ab1f90f9
JN		 2670static void vlv_enable_dp(struct intel_encoder *encoder)
2671{
828f5c6e
JN		 2672 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2673
4be73780 2674 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2675}
2676
ecff4f3b 2677static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2678{
2679 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2680 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2681
8ac33ed3
DV		 2682 intel_dp_prepare(encoder);
2683
d41f1efb
DV		 2684 /* Only ilk+ has port A */
2685 if (dport->port == PORT_A) {
2686 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2687 ironlake_edp_pll_on(intel_dp);
d41f1efb 2688 }
ab1f90f9
JN		 2689}
2690
83b84597
VS		 2691static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2692{
2693 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2694 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2695 enum pipe pipe = intel_dp->pps_pipe;
2696 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2697
2698 edp_panel_vdd_off_sync(intel_dp);
2699
2700 /*
2701 * VLV seems to get confused when multiple power seqeuencers
2702 * have the same port selected (even if only one has power/vdd
2703 * enabled). The failure manifests as vlv_wait_port_ready() failing
2704 * CHV on the other hand doesn't seem to mind having the same port
2705 * selected in multiple power seqeuencers, but let's clear the
2706 * port select always when logically disconnecting a power sequencer
2707 * from a port.
2708 */
2709 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2710 pipe_name(pipe), port_name(intel_dig_port->port));
2711 I915_WRITE(pp_on_reg, 0);
2712 POSTING_READ(pp_on_reg);
2713
2714 intel_dp->pps_pipe = INVALID_PIPE;
2715}
2716
a4a5d2f8
VS		 2717static void vlv_steal_power_sequencer(struct drm_device *dev,
2718 enum pipe pipe)
2719{
2720 struct drm_i915_private *dev_priv = dev->dev_private;
2721 struct intel_encoder *encoder;
2722
2723 lockdep_assert_held(&dev_priv->pps_mutex);
2724
ac3c12e4
VS		 2725 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2726 return;
2727
a4a5d2f8
VS		 2728 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2729 base.head) {
2730 struct intel_dp *intel_dp;
773538e8 2731 enum port port;
a4a5d2f8
VS		 2732
2733 if (encoder->type != INTEL_OUTPUT_EDP)
2734 continue;
2735
2736 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2737 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2738
2739 if (intel_dp->pps_pipe != pipe)
2740 continue;
2741
2742 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2743 pipe_name(pipe), port_name(port));
a4a5d2f8 2744
034e43c6
VS		 2745 WARN(encoder->connectors_active,
2746 "stealing pipe %c power sequencer from active eDP port %c\n",
2747 pipe_name(pipe), port_name(port));
2748
a4a5d2f8 2749 /* make sure vdd is off before we steal it */
83b84597 2750 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2751 }
2752}
2753
2754static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2755{
2756 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2757 struct intel_encoder *encoder = &intel_dig_port->base;
2758 struct drm_device *dev = encoder->base.dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2761
2762 lockdep_assert_held(&dev_priv->pps_mutex);
2763
093e3f13
VS		 2764 if (!is_edp(intel_dp))
2765 return;
2766
a4a5d2f8
VS		 2767 if (intel_dp->pps_pipe == crtc->pipe)
2768 return;
2769
2770 /*
2771 * If another power sequencer was being used on this
2772 * port previously make sure to turn off vdd there while
2773 * we still have control of it.
2774 */
2775 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2776 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2777
2778 /*
2779 * We may be stealing the power
2780 * sequencer from another port.
2781 */
2782 vlv_steal_power_sequencer(dev, crtc->pipe);
2783
2784 /* now it's all ours */
2785 intel_dp->pps_pipe = crtc->pipe;
2786
2787 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2788 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2789
2790 /* init power sequencer on this pipe and port */
36b5f425
VS		 2791 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2792 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2793}
2794
ab1f90f9 2795static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2796{
2bd2ad64 2797 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2798 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2799 struct drm_device *dev = encoder->base.dev;
89b667f8 2800 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2801 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2802 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2803 int pipe = intel_crtc->pipe;
2804 u32 val;
a4fc5ed6 2805
ab1f90f9 2806 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2807
ab3c759a 2808 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2809 val = 0;
2810 if (pipe)
2811 val |= (1<<21);
2812 else
2813 val &= ~(1<<21);
2814 val |= 0x001000c4;
ab3c759a
CML		 2815 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2816 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2817 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2818
ab1f90f9
JN		 2819 mutex_unlock(&dev_priv->dpio_lock);
2820
2821 intel_enable_dp(encoder);
89b667f8
JB		 2822}
2823
ecff4f3b 2824static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2825{
2826 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2827 struct drm_device *dev = encoder->base.dev;
2828 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2829 struct intel_crtc *intel_crtc =
2830 to_intel_crtc(encoder->base.crtc);
e4607fcf 2831 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2832 int pipe = intel_crtc->pipe;
89b667f8 2833
8ac33ed3
DV		 2834 intel_dp_prepare(encoder);
2835
89b667f8 2836 /* Program Tx lane resets to default */
0980a60f 2837 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2838 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2839 DPIO_PCS_TX_LANE2_RESET |
2840 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2841 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2842 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2843 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2844 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2845 DPIO_PCS_CLK_SOFT_RESET);
2846
2847 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2848 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2849 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2850 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2851 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2852}
2853
e4a1d846
CML		 2854static void chv_pre_enable_dp(struct intel_encoder *encoder)
2855{
2856 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2857 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2858 struct drm_device *dev = encoder->base.dev;
2859 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2860 struct intel_crtc *intel_crtc =
2861 to_intel_crtc(encoder->base.crtc);
2862 enum dpio_channel ch = vlv_dport_to_channel(dport);
2863 int pipe = intel_crtc->pipe;
2864 int data, i;
949c1d43 2865 u32 val;
e4a1d846 2866
e4a1d846 2867 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2868
570e2a74
VS		 2869 /* allow hardware to manage TX FIFO reset source */
2870 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2871 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2872 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2873
2874 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2875 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2876 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2877
949c1d43 2878 /* Deassert soft data lane reset*/
97fd4d5c 2879 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2880 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2881 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2882
2883 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2884 val |= CHV_PCS_REQ_SOFTRESET_EN;
2885 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2886
2887 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2888 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2889 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2890
97fd4d5c 2891 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2892 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2893 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2894
2895 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2896 for (i = 0; i < 4; i++) {
2897 /* Set the latency optimal bit */
2898 data = (i == 1) ? 0x0 : 0x6;
2899 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2900 data << DPIO_FRC_LATENCY_SHFIT);
2901
2902 /* Set the upar bit */
2903 data = (i == 1) ? 0x0 : 0x1;
2904 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2905 data << DPIO_UPAR_SHIFT);
2906 }
2907
2908 /* Data lane stagger programming */
2909 /* FIXME: Fix up value only after power analysis */
2910
2911 mutex_unlock(&dev_priv->dpio_lock);
2912
e4a1d846 2913 intel_enable_dp(encoder);
e4a1d846
CML		 2914}
2915
9197c88b
VS		 2916static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2917{
2918 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2919 struct drm_device *dev = encoder->base.dev;
2920 struct drm_i915_private *dev_priv = dev->dev_private;
2921 struct intel_crtc *intel_crtc =
2922 to_intel_crtc(encoder->base.crtc);
2923 enum dpio_channel ch = vlv_dport_to_channel(dport);
2924 enum pipe pipe = intel_crtc->pipe;
2925 u32 val;
2926
625695f8
VS		 2927 intel_dp_prepare(encoder);
2928
9197c88b
VS		 2929 mutex_lock(&dev_priv->dpio_lock);
2930
b9e5ac3c
VS		 2931 /* program left/right clock distribution */
2932 if (pipe != PIPE_B) {
2933 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2934 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2935 if (ch == DPIO_CH0)
2936 val |= CHV_BUFLEFTENA1_FORCE;
2937 if (ch == DPIO_CH1)
2938 val |= CHV_BUFRIGHTENA1_FORCE;
2939 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2940 } else {
2941 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2942 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2943 if (ch == DPIO_CH0)
2944 val |= CHV_BUFLEFTENA2_FORCE;
2945 if (ch == DPIO_CH1)
2946 val |= CHV_BUFRIGHTENA2_FORCE;
2947 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2948 }
2949
9197c88b
VS		 2950 /* program clock channel usage */
2951 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2952 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2953 if (pipe != PIPE_B)
2954 val &= ~CHV_PCS_USEDCLKCHANNEL;
2955 else
2956 val |= CHV_PCS_USEDCLKCHANNEL;
2957 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2958
2959 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2960 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2961 if (pipe != PIPE_B)
2962 val &= ~CHV_PCS_USEDCLKCHANNEL;
2963 else
2964 val |= CHV_PCS_USEDCLKCHANNEL;
2965 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2966
2967 /*
2968 * This a a bit weird since generally CL
2969 * matches the pipe, but here we need to
2970 * pick the CL based on the port.
2971 */
2972 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2973 if (pipe != PIPE_B)
2974 val &= ~CHV_CMN_USEDCLKCHANNEL;
2975 else
2976 val |= CHV_CMN_USEDCLKCHANNEL;
2977 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2978
2979 mutex_unlock(&dev_priv->dpio_lock);
2980}
2981
a4fc5ed6 2982/*
df0c237d
JB		 2983 * Native read with retry for link status and receiver capability reads for
2984 * cases where the sink may still be asleep.
9d1a1031
JN		 2985 *
2986 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2987 * supposed to retry 3 times per the spec.
a4fc5ed6 2988 */
9d1a1031
JN		 2989static ssize_t
2990intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2991 void *buffer, size_t size)
a4fc5ed6 2992{
9d1a1031
JN		 2993 ssize_t ret;
2994 int i;
61da5fab 2995
61da5fab 2996 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2997 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2998 if (ret == size)
2999 return ret;
61da5fab
JB		 3000 msleep(1);
3001 }
a4fc5ed6 3002
9d1a1031 3003 return ret;
a4fc5ed6
KP		 3004}
3005
3006/*
3007 * Fetch AUX CH registers 0x202 - 0x207 which contain
3008 * link status information
3009 */
3010static bool
93f62dad 3011intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 3012{
9d1a1031
JN		 3013 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3014 DP_LANE0_1_STATUS,
3015 link_status,
3016 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 3017}
3018
1100244e 3019/* These are source-specific values. */
a4fc5ed6 3020static uint8_t
1a2eb460 3021intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 3022{
30add22d 3023 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 3024 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3025
5a9d1f1a
DL		 3026 if (INTEL_INFO(dev)->gen >= 9)
3027 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3028 else if (IS_VALLEYVIEW(dev))
bd60018a 3029 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 3030 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 3031 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 3032 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 3033 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 3034 else
bd60018a 3035 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 3036}
3037
3038static uint8_t
3039intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3040{
30add22d 3041 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 3042 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3043
5a9d1f1a
DL		 3044 if (INTEL_INFO(dev)->gen >= 9) {
3045 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3047 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3048 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3049 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3051 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3052 default:
3053 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3054 }
3055 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 3056 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3058 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3060 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3061 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3062 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3063 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 3064 default:
bd60018a 3065 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 3066 }
e2fa6fba
P		 3067 } else if (IS_VALLEYVIEW(dev)) {
3068 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3069 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3070 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3071 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3072 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3073 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3074 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3075 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 3076 default:
bd60018a 3077 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3078 }
bc7d38a4 3079 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 3080 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3081 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3082 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3083 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3084 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3085 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3086 default:
bd60018a 3087 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3088 }
3089 } else {
3090 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3092 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3094 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3096 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3098 default:
bd60018a 3099 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3100 }
a4fc5ed6
KP		 3101 }
3102}
3103
e2fa6fba
P		 3104static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
3105{
3106 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3107 struct drm_i915_private *dev_priv = dev->dev_private;
3108 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 3109 struct intel_crtc *intel_crtc =
3110 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 3111 unsigned long demph_reg_value, preemph_reg_value,
3112 uniqtranscale_reg_value;
3113 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 3114 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 3115 int pipe = intel_crtc->pipe;
e2fa6fba
P		 3116
3117 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3118 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3119 preemph_reg_value = 0x0004000;
3120 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3121 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3122 demph_reg_value = 0x2B405555;
3123 uniqtranscale_reg_value = 0x552AB83A;
3124 break;
bd60018a 3125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3126 demph_reg_value = 0x2B404040;
3127 uniqtranscale_reg_value = 0x5548B83A;
3128 break;
bd60018a 3129 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3130 demph_reg_value = 0x2B245555;
3131 uniqtranscale_reg_value = 0x5560B83A;
3132 break;
bd60018a 3133 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3134 demph_reg_value = 0x2B405555;
3135 uniqtranscale_reg_value = 0x5598DA3A;
3136 break;
3137 default:
3138 return 0;
3139 }
3140 break;
bd60018a 3141 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3142 preemph_reg_value = 0x0002000;
3143 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3144 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3145 demph_reg_value = 0x2B404040;
3146 uniqtranscale_reg_value = 0x5552B83A;
3147 break;
bd60018a 3148 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3149 demph_reg_value = 0x2B404848;
3150 uniqtranscale_reg_value = 0x5580B83A;
3151 break;
bd60018a 3152 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3153 demph_reg_value = 0x2B404040;
3154 uniqtranscale_reg_value = 0x55ADDA3A;
3155 break;
3156 default:
3157 return 0;
3158 }
3159 break;
bd60018a 3160 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3161 preemph_reg_value = 0x0000000;
3162 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3163 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3164 demph_reg_value = 0x2B305555;
3165 uniqtranscale_reg_value = 0x5570B83A;
3166 break;
bd60018a 3167 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3168 demph_reg_value = 0x2B2B4040;
3169 uniqtranscale_reg_value = 0x55ADDA3A;
3170 break;
3171 default:
3172 return 0;
3173 }
3174 break;
bd60018a 3175 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3176 preemph_reg_value = 0x0006000;
3177 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3178 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3179 demph_reg_value = 0x1B405555;
3180 uniqtranscale_reg_value = 0x55ADDA3A;
3181 break;
3182 default:
3183 return 0;
3184 }
3185 break;
3186 default:
3187 return 0;
3188 }
3189
0980a60f 3190 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3191 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3192 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3193 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3194 uniqtranscale_reg_value);
ab3c759a
CML		 3195 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3196 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3197 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3198 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3199 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3200
3201 return 0;
3202}
3203
e4a1d846
CML		 3204static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3205{
3206 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3207 struct drm_i915_private *dev_priv = dev->dev_private;
3208 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3209 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3210 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3211 uint8_t train_set = intel_dp->train_set[0];
3212 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3213 enum pipe pipe = intel_crtc->pipe;
3214 int i;
e4a1d846
CML		 3215
3216 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3217 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3218 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3220 deemph_reg_value = 128;
3221 margin_reg_value = 52;
3222 break;
bd60018a 3223 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3224 deemph_reg_value = 128;
3225 margin_reg_value = 77;
3226 break;
bd60018a 3227 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3228 deemph_reg_value = 128;
3229 margin_reg_value = 102;
3230 break;
bd60018a 3231 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3232 deemph_reg_value = 128;
3233 margin_reg_value = 154;
3234 /* FIXME extra to set for 1200 */
3235 break;
3236 default:
3237 return 0;
3238 }
3239 break;
bd60018a 3240 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3241 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3243 deemph_reg_value = 85;
3244 margin_reg_value = 78;
3245 break;
bd60018a 3246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3247 deemph_reg_value = 85;
3248 margin_reg_value = 116;
3249 break;
bd60018a 3250 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3251 deemph_reg_value = 85;
3252 margin_reg_value = 154;
3253 break;
3254 default:
3255 return 0;
3256 }
3257 break;
bd60018a 3258 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3259 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3260 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3261 deemph_reg_value = 64;
3262 margin_reg_value = 104;
3263 break;
bd60018a 3264 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3265 deemph_reg_value = 64;
3266 margin_reg_value = 154;
3267 break;
3268 default:
3269 return 0;
3270 }
3271 break;
bd60018a 3272 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3273 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3274 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3275 deemph_reg_value = 43;
3276 margin_reg_value = 154;
3277 break;
3278 default:
3279 return 0;
3280 }
3281 break;
3282 default:
3283 return 0;
3284 }
3285
3286 mutex_lock(&dev_priv->dpio_lock);
3287
3288 /* Clear calc init */
1966e59e
VS		 3289 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3290 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3291 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3292 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3293 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3294
3295 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3296 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3297 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3298 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3299 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3300
a02ef3c7
VS		 3301 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3302 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3303 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3304 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3305
3306 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3307 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3308 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3309 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3310
e4a1d846 3311 /* Program swing deemph */
f72df8db
VS		 3312 for (i = 0; i < 4; i++) {
3313 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3314 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3315 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3316 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3317 }
e4a1d846
CML		 3318
3319 /* Program swing margin */
f72df8db
VS		 3320 for (i = 0; i < 4; i++) {
3321 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3322 val &= ~DPIO_SWING_MARGIN000_MASK;
3323 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3324 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3325 }
e4a1d846
CML		 3326
3327 /* Disable unique transition scale */
f72df8db
VS		 3328 for (i = 0; i < 4; i++) {
3329 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3330 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3331 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3332 }
e4a1d846
CML		 3333
3334 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3335 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3336 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3337 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3338
3339 /*
3340 * The document said it needs to set bit 27 for ch0 and bit 26
3341 * for ch1. Might be a typo in the doc.
3342 * For now, for this unique transition scale selection, set bit
3343 * 27 for ch0 and ch1.
3344 */
f72df8db
VS		 3345 for (i = 0; i < 4; i++) {
3346 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3347 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3348 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3349 }
e4a1d846 3350
f72df8db
VS		 3351 for (i = 0; i < 4; i++) {
3352 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3353 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3354 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3355 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3356 }
e4a1d846
CML		 3357 }
3358
3359 /* Start swing calculation */
1966e59e
VS		 3360 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3361 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3362 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3363
3364 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3365 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3366 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3367
3368 /* LRC Bypass */
3369 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3370 val |= DPIO_LRC_BYPASS;
3371 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3372
3373 mutex_unlock(&dev_priv->dpio_lock);
3374
3375 return 0;
3376}
3377
a4fc5ed6 3378static void
0301b3ac
JN		 3379intel_get_adjust_train(struct intel_dp *intel_dp,
3380 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3381{
3382 uint8_t v = 0;
3383 uint8_t p = 0;
3384 int lane;
1a2eb460
KP		 3385 uint8_t voltage_max;
3386 uint8_t preemph_max;
a4fc5ed6 3387
33a34e4e 3388 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3389 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3390 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3391
3392 if (this_v > v)
3393 v = this_v;
3394 if (this_p > p)
3395 p = this_p;
3396 }
3397
1a2eb460 3398 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3399 if (v >= voltage_max)
3400 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3401
1a2eb460
KP		 3402 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3403 if (p >= preemph_max)
3404 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3405
3406 for (lane = 0; lane < 4; lane++)
33a34e4e 3407 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3408}
3409
3410static uint32_t
f0a3424e 3411intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3412{
3cf2efb1 3413 uint32_t signal_levels = 0;
a4fc5ed6 3414
3cf2efb1 3415 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3416 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3417 default:
3418 signal_levels |= DP_VOLTAGE_0_4;
3419 break;
bd60018a 3420 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3421 signal_levels |= DP_VOLTAGE_0_6;
3422 break;
bd60018a 3423 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3424 signal_levels |= DP_VOLTAGE_0_8;
3425 break;
bd60018a 3426 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3427 signal_levels |= DP_VOLTAGE_1_2;
3428 break;
3429 }
3cf2efb1 3430 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3431 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3432 default:
3433 signal_levels |= DP_PRE_EMPHASIS_0;
3434 break;
bd60018a 3435 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3436 signal_levels |= DP_PRE_EMPHASIS_3_5;
3437 break;
bd60018a 3438 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3439 signal_levels |= DP_PRE_EMPHASIS_6;
3440 break;
bd60018a 3441 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3442 signal_levels |= DP_PRE_EMPHASIS_9_5;
3443 break;
3444 }
3445 return signal_levels;
3446}
3447
e3421a18
ZW		 3448/* Gen6's DP voltage swing and pre-emphasis control */
3449static uint32_t
3450intel_gen6_edp_signal_levels(uint8_t train_set)
3451{
3c5a62b5
YL		 3452 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3453 DP_TRAIN_PRE_EMPHASIS_MASK);
3454 switch (signal_levels) {
bd60018a
SJ		 3455 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3456 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3457 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3458 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3459 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3460 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3461 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3462 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3463 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3464 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3465 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3466 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3467 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3468 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3469 default:
3c5a62b5
YL		 3470 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3471 "0x%x\n", signal_levels);
3472 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3473 }
3474}
3475
1a2eb460
KP		 3476/* Gen7's DP voltage swing and pre-emphasis control */
3477static uint32_t
3478intel_gen7_edp_signal_levels(uint8_t train_set)
3479{
3480 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3481 DP_TRAIN_PRE_EMPHASIS_MASK);
3482 switch (signal_levels) {
bd60018a 3483 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3484 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3485 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3486 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3487 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3488 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3489
bd60018a 3490 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3491 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3492 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3493 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3494
bd60018a 3495 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3496 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3497 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3498 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3499
3500 default:
3501 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3502 "0x%x\n", signal_levels);
3503 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3504 }
3505}
3506
d6c0d722
PZ		 3507/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3508static uint32_t
f0a3424e 3509intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3510{
d6c0d722
PZ		 3511 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3512 DP_TRAIN_PRE_EMPHASIS_MASK);
3513 switch (signal_levels) {
bd60018a 3514 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3515 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3516 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3517 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3518 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3519 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3520 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3521 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3522
bd60018a 3523 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3524 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3525 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3526 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3527 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3528 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3529
bd60018a 3530 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3531 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3532 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3533 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3534 default:
3535 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3536 "0x%x\n", signal_levels);
c5fe6a06 3537 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3538 }
a4fc5ed6
KP		 3539}
3540
f0a3424e
PZ		 3541/* Properly updates "DP" with the correct signal levels. */
3542static void
3543intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3544{
3545 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3546 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3547 struct drm_device *dev = intel_dig_port->base.base.dev;
3548 uint32_t signal_levels, mask;
3549 uint8_t train_set = intel_dp->train_set[0];
3550
5a9d1f1a 3551 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3552 signal_levels = intel_hsw_signal_levels(train_set);
3553 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3554 } else if (IS_CHERRYVIEW(dev)) {
3555 signal_levels = intel_chv_signal_levels(intel_dp);
3556 mask = 0;
e2fa6fba
P		 3557 } else if (IS_VALLEYVIEW(dev)) {
3558 signal_levels = intel_vlv_signal_levels(intel_dp);
3559 mask = 0;
bc7d38a4 3560 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3561 signal_levels = intel_gen7_edp_signal_levels(train_set);
3562 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3563 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3564 signal_levels = intel_gen6_edp_signal_levels(train_set);
3565 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3566 } else {
3567 signal_levels = intel_gen4_signal_levels(train_set);
3568 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3569 }
3570
3571 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3572
3573 *DP = (*DP & ~mask) | signal_levels;
3574}
3575
a4fc5ed6 3576static bool
ea5b213a 3577intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3578 uint32_t *DP,
58e10eb9 3579 uint8_t dp_train_pat)
a4fc5ed6 3580{
174edf1f
PZ		 3581 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3582 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3583 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3584 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3585 int ret, len;
a4fc5ed6 3586
7b13b58a 3587 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3588
70aff66c 3589 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3590 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3591
2cdfe6c8
JN		 3592 buf[0] = dp_train_pat;
3593 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3594 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3595 /* don't write DP_TRAINING_LANEx_SET on disable */
3596 len = 1;
3597 } else {
3598 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3599 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3600 len = intel_dp->lane_count + 1;
47ea7542 3601 }
a4fc5ed6 3602
9d1a1031
JN		 3603 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3604 buf, len);
2cdfe6c8
JN		 3605
3606 return ret == len;
a4fc5ed6
KP		 3607}
3608
70aff66c
JN		 3609static bool
3610intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3611 uint8_t dp_train_pat)
3612{
953d22e8 3613 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3614 intel_dp_set_signal_levels(intel_dp, DP);
3615 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3616}
3617
3618static bool
3619intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3620 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3621{
3622 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3623 struct drm_device *dev = intel_dig_port->base.base.dev;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 int ret;
3626
3627 intel_get_adjust_train(intel_dp, link_status);
3628 intel_dp_set_signal_levels(intel_dp, DP);
3629
3630 I915_WRITE(intel_dp->output_reg, *DP);
3631 POSTING_READ(intel_dp->output_reg);
3632
9d1a1031
JN		 3633 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3634 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3635
3636 return ret == intel_dp->lane_count;
3637}
3638
3ab9c637
ID		 3639static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3640{
3641 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3642 struct drm_device *dev = intel_dig_port->base.base.dev;
3643 struct drm_i915_private *dev_priv = dev->dev_private;
3644 enum port port = intel_dig_port->port;
3645 uint32_t val;
3646
3647 if (!HAS_DDI(dev))
3648 return;
3649
3650 val = I915_READ(DP_TP_CTL(port));
3651 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3652 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3653 I915_WRITE(DP_TP_CTL(port), val);
3654
3655 /*
3656 * On PORT_A we can have only eDP in SST mode. There the only reason
3657 * we need to set idle transmission mode is to work around a HW issue
3658 * where we enable the pipe while not in idle link-training mode.
3659 * In this case there is requirement to wait for a minimum number of
3660 * idle patterns to be sent.
3661 */
3662 if (port == PORT_A)
3663 return;
3664
3665 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3666 1))
3667 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3668}
3669
33a34e4e 3670/* Enable corresponding port and start training pattern 1 */
c19b0669 3671void
33a34e4e 3672intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3673{
da63a9f2 3674 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3675 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3676 int i;
3677 uint8_t voltage;
cdb0e95b 3678 int voltage_tries, loop_tries;
ea5b213a 3679 uint32_t DP = intel_dp->DP;
6aba5b6c 3680 uint8_t link_config[2];
a4fc5ed6 3681
affa9354 3682 if (HAS_DDI(dev))
c19b0669
PZ		 3683 intel_ddi_prepare_link_retrain(encoder);
3684
3cf2efb1 3685 /* Write the link configuration data */
6aba5b6c
JN		 3686 link_config[0] = intel_dp->link_bw;
3687 link_config[1] = intel_dp->lane_count;
3688 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3689 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3690 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3691
3692 link_config[0] = 0;
3693 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3694 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3695
3696 DP |= DP_PORT_EN;
1a2eb460 3697
70aff66c
JN		 3698 /* clock recovery */
3699 if (!intel_dp_reset_link_train(intel_dp, &DP,
3700 DP_TRAINING_PATTERN_1 |
3701 DP_LINK_SCRAMBLING_DISABLE)) {
3702 DRM_ERROR("failed to enable link training\n");
3703 return;
3704 }
3705
a4fc5ed6 3706 voltage = 0xff;
cdb0e95b
KP		 3707 voltage_tries = 0;
3708 loop_tries = 0;
a4fc5ed6 3709 for (;;) {
70aff66c 3710 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3711
a7c9655f 3712 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3713 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3714 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3715 break;
93f62dad 3716 }
a4fc5ed6 3717
01916270 3718 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3719 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3720 break;
3721 }
3722
3723 /* Check to see if we've tried the max voltage */
3724 for (i = 0; i < intel_dp->lane_count; i++)
3725 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3726 break;
3b4f819d 3727 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3728 ++loop_tries;
3729 if (loop_tries == 5) {
3def84b3 3730 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3731 break;
3732 }
70aff66c
JN		 3733 intel_dp_reset_link_train(intel_dp, &DP,
3734 DP_TRAINING_PATTERN_1 |
3735 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3736 voltage_tries = 0;
3737 continue;
3738 }
a4fc5ed6 3739
3cf2efb1 3740 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3741 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3742 ++voltage_tries;
b06fbda3 3743 if (voltage_tries == 5) {
3def84b3 3744 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3745 break;
3746 }
3747 } else
3748 voltage_tries = 0;
3749 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3750
70aff66c
JN		 3751 /* Update training set as requested by target */
3752 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3753 DRM_ERROR("failed to update link training\n");
3754 break;
3755 }
a4fc5ed6
KP		 3756 }
3757
33a34e4e
JB		 3758 intel_dp->DP = DP;
3759}
3760
c19b0669 3761void
33a34e4e
JB		 3762intel_dp_complete_link_train(struct intel_dp *intel_dp)
3763{
33a34e4e 3764 bool channel_eq = false;
37f80975 3765 int tries, cr_tries;
33a34e4e 3766 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3767 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3768
3769 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3770 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3771 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3772
a4fc5ed6 3773 /* channel equalization */
70aff66c 3774 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3775 training_pattern |
70aff66c
JN		 3776 DP_LINK_SCRAMBLING_DISABLE)) {
3777 DRM_ERROR("failed to start channel equalization\n");
3778 return;
3779 }
3780
a4fc5ed6 3781 tries = 0;
37f80975 3782 cr_tries = 0;
a4fc5ed6
KP		 3783 channel_eq = false;
3784 for (;;) {
70aff66c 3785 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3786
37f80975
JB		 3787 if (cr_tries > 5) {
3788 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3789 break;
3790 }
3791
a7c9655f 3792 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3793 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3794 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3795 break;
70aff66c 3796 }
a4fc5ed6 3797
37f80975 3798 /* Make sure clock is still ok */
01916270 3799 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3800 intel_dp_start_link_train(intel_dp);
70aff66c 3801 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3802 training_pattern |
70aff66c 3803 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3804 cr_tries++;
3805 continue;
3806 }
3807
1ffdff13 3808 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3809 channel_eq = true;
3810 break;
3811 }
a4fc5ed6 3812
37f80975
JB		 3813 /* Try 5 times, then try clock recovery if that fails */
3814 if (tries > 5) {
37f80975 3815 intel_dp_start_link_train(intel_dp);
70aff66c 3816 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3817 training_pattern |
70aff66c 3818 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3819 tries = 0;
3820 cr_tries++;
3821 continue;
3822 }
a4fc5ed6 3823
70aff66c
JN		 3824 /* Update training set as requested by target */
3825 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3826 DRM_ERROR("failed to update link training\n");
3827 break;
3828 }
3cf2efb1 3829 ++tries;
869184a6 3830 }
3cf2efb1 3831
3ab9c637
ID		 3832 intel_dp_set_idle_link_train(intel_dp);
3833
3834 intel_dp->DP = DP;
3835
d6c0d722 3836 if (channel_eq)
07f42258 3837 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3838
3ab9c637
ID		 3839}
3840
3841void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3842{
70aff66c 3843 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3844 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3845}
3846
3847static void
ea5b213a 3848intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3849{
da63a9f2 3850 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3851 enum port port = intel_dig_port->port;
da63a9f2 3852 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3853 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3854 struct intel_crtc *intel_crtc =
3855 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3856 uint32_t DP = intel_dp->DP;
a4fc5ed6 3857
bc76e320 3858 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3859 return;
3860
0c33d8d7 3861 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3862 return;
3863
28c97730 3864 DRM_DEBUG_KMS("\n");
32f9d658 3865
bc7d38a4 3866 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3867 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3868 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3869 } else {
aad3d14d
VS		 3870 if (IS_CHERRYVIEW(dev))
3871 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3872 else
3873 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3874 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3875 }
fe255d00 3876 POSTING_READ(intel_dp->output_reg);
5eb08b69 3877
493a7081 3878 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3879 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3880 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3881
5bddd17f
EA		 3882 /* Hardware workaround: leaving our transcoder select
3883 * set to transcoder B while it's off will prevent the
3884 * corresponding HDMI output on transcoder A.
3885 *
3886 * Combine this with another hardware workaround:
3887 * transcoder select bit can only be cleared while the
3888 * port is enabled.
3889 */
3890 DP &= ~DP_PIPEB_SELECT;
3891 I915_WRITE(intel_dp->output_reg, DP);
3892
3893 /* Changes to enable or select take place the vblank
3894 * after being written.
3895 */
ff50afe9
DV		 3896 if (WARN_ON(crtc == NULL)) {
3897 /* We should never try to disable a port without a crtc
3898 * attached. For paranoia keep the code around for a
3899 * bit. */
31acbcc4
CW		 3900 POSTING_READ(intel_dp->output_reg);
3901 msleep(50);
3902 } else
ab527efc 3903 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3904 }
3905
832afda6 3906 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3907 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3908 POSTING_READ(intel_dp->output_reg);
f01eca2e 3909 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3910}
3911
26d61aad
KP		 3912static bool
3913intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3914{
a031d709
RV		 3915 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3916 struct drm_device *dev = dig_port->base.base.dev;
3917 struct drm_i915_private *dev_priv = dev->dev_private;
3918
9d1a1031
JN		 3919 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3920 sizeof(intel_dp->dpcd)) < 0)
edb39244 3921 return false; /* aux transfer failed */
92fd8fd1 3922
a8e98153 3923 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3924
edb39244
AJ		 3925 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3926 return false; /* DPCD not present */
3927
2293bb5c
SK		 3928 /* Check if the panel supports PSR */
3929 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3930 if (is_edp(intel_dp)) {
9d1a1031
JN		 3931 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3932 intel_dp->psr_dpcd,
3933 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3934 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3935 dev_priv->psr.sink_support = true;
50003939 3936 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3937 }
50003939
JN		 3938 }
3939
06ea66b6
TP		 3940 /* Training Pattern 3 support */
3941 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3942 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3943 intel_dp->use_tps3 = true;
f8d8a672 3944 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3945 } else
3946 intel_dp->use_tps3 = false;
3947
edb39244
AJ		 3948 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3949 DP_DWN_STRM_PORT_PRESENT))
3950 return true; /* native DP sink */
3951
3952 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3953 return true; /* no per-port downstream info */
3954
9d1a1031
JN		 3955 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3956 intel_dp->downstream_ports,
3957 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3958 return false; /* downstream port status fetch failed */
3959
3960 return true;
92fd8fd1
KP		 3961}
3962
0d198328
AJ		 3963static void
3964intel_dp_probe_oui(struct intel_dp *intel_dp)
3965{
3966 u8 buf[3];
3967
3968 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3969 return;
3970
9d1a1031 3971 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3972 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3973 buf[0], buf[1], buf[2]);
3974
9d1a1031 3975 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3976 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3977 buf[0], buf[1], buf[2]);
3978}
3979
0e32b39c
DA		 3980static bool
3981intel_dp_probe_mst(struct intel_dp *intel_dp)
3982{
3983 u8 buf[1];
3984
3985 if (!intel_dp->can_mst)
3986 return false;
3987
3988 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3989 return false;
3990
0e32b39c
DA		 3991 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3992 if (buf[0] & DP_MST_CAP) {
3993 DRM_DEBUG_KMS("Sink is MST capable\n");
3994 intel_dp->is_mst = true;
3995 } else {
3996 DRM_DEBUG_KMS("Sink is not MST capable\n");
3997 intel_dp->is_mst = false;
3998 }
3999 }
0e32b39c
DA		 4000
4001 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4002 return intel_dp->is_mst;
4003}
4004
d2e216d0
RV		 4005int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
4006{
4007 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4008 struct drm_device *dev = intel_dig_port->base.base.dev;
4009 struct intel_crtc *intel_crtc =
4010 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 4011 u8 buf;
4012 int test_crc_count;
4013 int attempts = 6;
d2e216d0 4014
ad9dc91b 4015 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 4016 return -EIO;
d2e216d0 4017
ad9dc91b 4018 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 4019 return -ENOTTY;
4020
1dda5f93
RV		 4021 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4022 return -EIO;
4023
9d1a1031 4024 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 4025 buf | DP_TEST_SINK_START) < 0)
bda0381e 4026 return -EIO;
d2e216d0 4027
1dda5f93 4028 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 4029 return -EIO;
ad9dc91b 4030 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 4031
ad9dc91b 4032 do {
1dda5f93
RV		 4033 if (drm_dp_dpcd_readb(&intel_dp->aux,
4034 DP_TEST_SINK_MISC, &buf) < 0)
4035 return -EIO;
ad9dc91b
RV		 4036 intel_wait_for_vblank(dev, intel_crtc->pipe);
4037 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
4038
4039 if (attempts == 0) {
4040 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
4041 return -EIO;
4042 }
d2e216d0 4043
9d1a1031 4044 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 4045 return -EIO;
d2e216d0 4046
1dda5f93
RV		 4047 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4048 return -EIO;
4049 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4050 buf & ~DP_TEST_SINK_START) < 0)
4051 return -EIO;
ce31d9f4 4052
d2e216d0
RV		 4053 return 0;
4054}
4055
a60f0e38
JB		 4056static bool
4057intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4058{
9d1a1031
JN		 4059 return intel_dp_dpcd_read_wake(&intel_dp->aux,
4060 DP_DEVICE_SERVICE_IRQ_VECTOR,
4061 sink_irq_vector, 1) == 1;
a60f0e38
JB		 4062}
4063
0e32b39c
DA		 4064static bool
4065intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4066{
4067 int ret;
4068
4069 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4070 DP_SINK_COUNT_ESI,
4071 sink_irq_vector, 14);
4072 if (ret != 14)
4073 return false;
4074
4075 return true;
4076}
4077
a60f0e38
JB		 4078static void
4079intel_dp_handle_test_request(struct intel_dp *intel_dp)
4080{
4081 /* NAK by default */
9d1a1031 4082 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 4083}
4084
0e32b39c
DA		 4085static int
4086intel_dp_check_mst_status(struct intel_dp *intel_dp)
4087{
4088 bool bret;
4089
4090 if (intel_dp->is_mst) {
4091 u8 esi[16] = { 0 };
4092 int ret = 0;
4093 int retry;
4094 bool handled;
4095 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4096go_again:
4097 if (bret == true) {
4098
4099 /* check link status - esi[10] = 0x200c */
4100 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4101 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4102 intel_dp_start_link_train(intel_dp);
4103 intel_dp_complete_link_train(intel_dp);
4104 intel_dp_stop_link_train(intel_dp);
4105 }
4106
4107 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4108 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4109
4110 if (handled) {
4111 for (retry = 0; retry < 3; retry++) {
4112 int wret;
4113 wret = drm_dp_dpcd_write(&intel_dp->aux,
4114 DP_SINK_COUNT_ESI+1,
4115 &esi[1], 3);
4116 if (wret == 3) {
4117 break;
4118 }
4119 }
4120
4121 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4122 if (bret == true) {
4123 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
4124 goto go_again;
4125 }
4126 } else
4127 ret = 0;
4128
4129 return ret;
4130 } else {
4131 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4132 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4133 intel_dp->is_mst = false;
4134 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4135 /* send a hotplug event */
4136 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4137 }
4138 }
4139 return -EINVAL;
4140}
4141
a4fc5ed6
KP		 4142/*
4143 * According to DP spec
4144 * 5.1.2:
4145 * 1. Read DPCD
4146 * 2. Configure link according to Receiver Capabilities
4147 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4148 * 4. Check link status on receipt of hot-plug interrupt
4149 */
00c09d70 4150void
ea5b213a 4151intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4152{
5b215bcf 4153 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4154 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4155 u8 sink_irq_vector;
93f62dad 4156 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4157
5b215bcf
DA		 4158 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4159
da63a9f2 4160 if (!intel_encoder->connectors_active)
d2b996ac 4161 return;
59cd09e1 4162
da63a9f2 4163 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4164 return;
4165
1a125d8a
ID		 4166 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4167 return;
4168
92fd8fd1 4169 /* Try to read receiver status if the link appears to be up */
93f62dad 4170 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4171 return;
4172 }
4173
92fd8fd1 4174 /* Now read the DPCD to see if it's actually running */
26d61aad 4175 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4176 return;
4177 }
4178
a60f0e38
JB		 4179 /* Try to read the source of the interrupt */
4180 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4181 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4182 /* Clear interrupt source */
9d1a1031
JN		 4183 drm_dp_dpcd_writeb(&intel_dp->aux,
4184 DP_DEVICE_SERVICE_IRQ_VECTOR,
4185 sink_irq_vector);
a60f0e38
JB		 4186
4187 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4188 intel_dp_handle_test_request(intel_dp);
4189 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4190 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4191 }
4192
1ffdff13 4193 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4194 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4195 intel_encoder->base.name);
33a34e4e
JB		 4196 intel_dp_start_link_train(intel_dp);
4197 intel_dp_complete_link_train(intel_dp);
3ab9c637 4198 intel_dp_stop_link_train(intel_dp);
33a34e4e 4199 }
a4fc5ed6 4200}
a4fc5ed6 4201
caf9ab24 4202/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4203static enum drm_connector_status
26d61aad 4204intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4205{
caf9ab24 4206 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4207 uint8_t type;
4208
4209 if (!intel_dp_get_dpcd(intel_dp))
4210 return connector_status_disconnected;
4211
4212 /* if there's no downstream port, we're done */
4213 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4214 return connector_status_connected;
caf9ab24
AJ		 4215
4216 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4217 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4218 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4219 uint8_t reg;
9d1a1031
JN		 4220
4221 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4222 &reg, 1) < 0)
caf9ab24 4223 return connector_status_unknown;
9d1a1031 4224
23235177
AJ		 4225 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4226 : connector_status_disconnected;
caf9ab24
AJ		 4227 }
4228
4229 /* If no HPD, poke DDC gently */
0b99836f 4230 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4231 return connector_status_connected;
caf9ab24
AJ		 4232
4233 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4234 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4235 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4236 if (type == DP_DS_PORT_TYPE_VGA ||
4237 type == DP_DS_PORT_TYPE_NON_EDID)
4238 return connector_status_unknown;
4239 } else {
4240 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4241 DP_DWN_STRM_PORT_TYPE_MASK;
4242 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4243 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4244 return connector_status_unknown;
4245 }
caf9ab24
AJ		 4246
4247 /* Anything else is out of spec, warn and ignore */
4248 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4249 return connector_status_disconnected;
71ba9000
AJ		 4250}
4251
d410b56d
CW		 4252static enum drm_connector_status
4253edp_detect(struct intel_dp *intel_dp)
4254{
4255 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4256 enum drm_connector_status status;
4257
4258 status = intel_panel_detect(dev);
4259 if (status == connector_status_unknown)
4260 status = connector_status_connected;
4261
4262 return status;
4263}
4264
5eb08b69 4265static enum drm_connector_status
a9756bb5 4266ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4267{
30add22d 4268 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4269 struct drm_i915_private *dev_priv = dev->dev_private;
4270 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4271
1b469639
DL		 4272 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4273 return connector_status_disconnected;
4274
26d61aad 4275 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4276}
4277
2a592bec
DA		 4278static int g4x_digital_port_connected(struct drm_device *dev,
4279 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4280{
a4fc5ed6 4281 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4282 uint32_t bit;
5eb08b69 4283
232a6ee9
TP		 4284 if (IS_VALLEYVIEW(dev)) {
4285 switch (intel_dig_port->port) {
4286 case PORT_B:
4287 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4288 break;
4289 case PORT_C:
4290 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4291 break;
4292 case PORT_D:
4293 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4294 break;
4295 default:
2a592bec 4296 return -EINVAL;
232a6ee9
TP		 4297 }
4298 } else {
4299 switch (intel_dig_port->port) {
4300 case PORT_B:
4301 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4302 break;
4303 case PORT_C:
4304 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4305 break;
4306 case PORT_D:
4307 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4308 break;
4309 default:
2a592bec 4310 return -EINVAL;
232a6ee9 4311 }
a4fc5ed6
KP		 4312 }
4313
10f76a38 4314 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4315 return 0;
4316 return 1;
4317}
4318
4319static enum drm_connector_status
4320g4x_dp_detect(struct intel_dp *intel_dp)
4321{
4322 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4323 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4324 int ret;
4325
4326 /* Can't disconnect eDP, but you can close the lid... */
4327 if (is_edp(intel_dp)) {
4328 enum drm_connector_status status;
4329
4330 status = intel_panel_detect(dev);
4331 if (status == connector_status_unknown)
4332 status = connector_status_connected;
4333 return status;
4334 }
4335
4336 ret = g4x_digital_port_connected(dev, intel_dig_port);
4337 if (ret == -EINVAL)
4338 return connector_status_unknown;
4339 else if (ret == 0)
a4fc5ed6
KP		 4340 return connector_status_disconnected;
4341
26d61aad 4342 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4343}
4344
8c241fef 4345static struct edid *
beb60608 4346intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4347{
beb60608 4348 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4349
9cd300e0
JN		 4350 /* use cached edid if we have one */
4351 if (intel_connector->edid) {
9cd300e0
JN		 4352 /* invalid edid */
4353 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4354 return NULL;
4355
55e9edeb 4356 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4357 } else
4358 return drm_get_edid(&intel_connector->base,
4359 &intel_dp->aux.ddc);
4360}
8c241fef 4361
beb60608
CW		 4362static void
4363intel_dp_set_edid(struct intel_dp *intel_dp)
4364{
4365 struct intel_connector *intel_connector = intel_dp->attached_connector;
4366 struct edid *edid;
8c241fef 4367
beb60608
CW		 4368 edid = intel_dp_get_edid(intel_dp);
4369 intel_connector->detect_edid = edid;
4370
4371 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4372 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4373 else
4374 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4375}
4376
beb60608
CW		 4377static void
4378intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4379{
beb60608 4380 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4381
beb60608
CW		 4382 kfree(intel_connector->detect_edid);
4383 intel_connector->detect_edid = NULL;
9cd300e0 4384
beb60608
CW		 4385 intel_dp->has_audio = false;
4386}
d6f24d0f 4387
beb60608
CW		 4388static enum intel_display_power_domain
4389intel_dp_power_get(struct intel_dp *dp)
4390{
4391 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4392 enum intel_display_power_domain power_domain;
4393
4394 power_domain = intel_display_port_power_domain(encoder);
4395 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4396
4397 return power_domain;
4398}
d6f24d0f 4399
beb60608
CW		 4400static void
4401intel_dp_power_put(struct intel_dp *dp,
4402 enum intel_display_power_domain power_domain)
4403{
4404 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4405 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4406}
4407
a9756bb5
ZW		 4408static enum drm_connector_status
4409intel_dp_detect(struct drm_connector *connector, bool force)
4410{
4411 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4412 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4413 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4414 struct drm_device *dev = connector->dev;
a9756bb5 4415 enum drm_connector_status status;
671dedd2 4416 enum intel_display_power_domain power_domain;
0e32b39c 4417 bool ret;
a9756bb5 4418
164c8598 4419 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4420 connector->base.id, connector->name);
beb60608 4421 intel_dp_unset_edid(intel_dp);
164c8598 4422
0e32b39c
DA		 4423 if (intel_dp->is_mst) {
4424 /* MST devices are disconnected from a monitor POV */
4425 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4426 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4427 return connector_status_disconnected;
0e32b39c
DA		 4428 }
4429
beb60608 4430 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4431
d410b56d
CW		 4432 /* Can't disconnect eDP, but you can close the lid... */
4433 if (is_edp(intel_dp))
4434 status = edp_detect(intel_dp);
4435 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4436 status = ironlake_dp_detect(intel_dp);
4437 else
4438 status = g4x_dp_detect(intel_dp);
4439 if (status != connector_status_connected)
c8c8fb33 4440 goto out;
a9756bb5 4441
0d198328
AJ		 4442 intel_dp_probe_oui(intel_dp);
4443
0e32b39c
DA		 4444 ret = intel_dp_probe_mst(intel_dp);
4445 if (ret) {
4446 /* if we are in MST mode then this connector
4447 won't appear connected or have anything with EDID on it */
4448 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4449 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4450 status = connector_status_disconnected;
4451 goto out;
4452 }
4453
beb60608 4454 intel_dp_set_edid(intel_dp);
a9756bb5 4455
d63885da
PZ		 4456 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4457 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4458 status = connector_status_connected;
4459
4460out:
beb60608 4461 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4462 return status;
a4fc5ed6
KP		 4463}
4464
beb60608
CW		 4465static void
4466intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4467{
df0e9248 4468 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4469 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4470 enum intel_display_power_domain power_domain;
a4fc5ed6 4471
beb60608
CW		 4472 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4473 connector->base.id, connector->name);
4474 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4475
beb60608
CW		 4476 if (connector->status != connector_status_connected)
4477 return;
671dedd2 4478
beb60608
CW		 4479 power_domain = intel_dp_power_get(intel_dp);
4480
4481 intel_dp_set_edid(intel_dp);
4482
4483 intel_dp_power_put(intel_dp, power_domain);
4484
4485 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4486 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4487}
4488
4489static int intel_dp_get_modes(struct drm_connector *connector)
4490{
4491 struct intel_connector *intel_connector = to_intel_connector(connector);
4492 struct edid *edid;
4493
4494 edid = intel_connector->detect_edid;
4495 if (edid) {
4496 int ret = intel_connector_update_modes(connector, edid);
4497 if (ret)
4498 return ret;
4499 }
32f9d658 4500
f8779fda 4501 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4502 if (is_edp(intel_attached_dp(connector)) &&
4503 intel_connector->panel.fixed_mode) {
f8779fda 4504 struct drm_display_mode *mode;
beb60608
CW		 4505
4506 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4507 intel_connector->panel.fixed_mode);
f8779fda 4508 if (mode) {
32f9d658
ZW		 4509 drm_mode_probed_add(connector, mode);
4510 return 1;
4511 }
4512 }
beb60608 4513
32f9d658 4514 return 0;
a4fc5ed6
KP		 4515}
4516
1aad7ac0
CW		 4517static bool
4518intel_dp_detect_audio(struct drm_connector *connector)
4519{
1aad7ac0 4520 bool has_audio = false;
beb60608 4521 struct edid *edid;
1aad7ac0 4522
beb60608
CW		 4523 edid = to_intel_connector(connector)->detect_edid;
4524 if (edid)
1aad7ac0 4525 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4526
1aad7ac0
CW		 4527 return has_audio;
4528}
4529
f684960e
CW		 4530static int
4531intel_dp_set_property(struct drm_connector *connector,
4532 struct drm_property *property,
4533 uint64_t val)
4534{
e953fd7b 4535 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4536 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4537 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4538 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4539 int ret;
4540
662595df 4541 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4542 if (ret)
4543 return ret;
4544
3f43c48d 4545 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4546 int i = val;
4547 bool has_audio;
4548
4549 if (i == intel_dp->force_audio)
f684960e
CW		 4550 return 0;
4551
1aad7ac0 4552 intel_dp->force_audio = i;
f684960e 4553
c3e5f67b 4554 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4555 has_audio = intel_dp_detect_audio(connector);
4556 else
c3e5f67b 4557 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4558
4559 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4560 return 0;
4561
1aad7ac0 4562 intel_dp->has_audio = has_audio;
f684960e
CW		 4563 goto done;
4564 }
4565
e953fd7b 4566 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4567 bool old_auto = intel_dp->color_range_auto;
4568 uint32_t old_range = intel_dp->color_range;
4569
55bc60db
VS		 4570 switch (val) {
4571 case INTEL_BROADCAST_RGB_AUTO:
4572 intel_dp->color_range_auto = true;
4573 break;
4574 case INTEL_BROADCAST_RGB_FULL:
4575 intel_dp->color_range_auto = false;
4576 intel_dp->color_range = 0;
4577 break;
4578 case INTEL_BROADCAST_RGB_LIMITED:
4579 intel_dp->color_range_auto = false;
4580 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4581 break;
4582 default:
4583 return -EINVAL;
4584 }
ae4edb80
DV		 4585
4586 if (old_auto == intel_dp->color_range_auto &&
4587 old_range == intel_dp->color_range)
4588 return 0;
4589
e953fd7b
CW		 4590 goto done;
4591 }
4592
53b41837
YN		 4593 if (is_edp(intel_dp) &&
4594 property == connector->dev->mode_config.scaling_mode_property) {
4595 if (val == DRM_MODE_SCALE_NONE) {
4596 DRM_DEBUG_KMS("no scaling not supported\n");
4597 return -EINVAL;
4598 }
4599
4600 if (intel_connector->panel.fitting_mode == val) {
4601 /* the eDP scaling property is not changed */
4602 return 0;
4603 }
4604 intel_connector->panel.fitting_mode = val;
4605
4606 goto done;
4607 }
4608
f684960e
CW		 4609 return -EINVAL;
4610
4611done:
c0c36b94
CW		 4612 if (intel_encoder->base.crtc)
4613 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4614
4615 return 0;
4616}
4617
a4fc5ed6 4618static void
73845adf 4619intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4620{
1d508706 4621 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4622
10e972d3 4623 kfree(intel_connector->detect_edid);
beb60608 4624
9cd300e0
JN		 4625 if (!IS_ERR_OR_NULL(intel_connector->edid))
4626 kfree(intel_connector->edid);
4627
acd8db10
PZ		 4628 /* Can't call is_edp() since the encoder may have been destroyed
4629 * already. */
4630 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4631 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4632
a4fc5ed6 4633 drm_connector_cleanup(connector);
55f78c43 4634 kfree(connector);
a4fc5ed6
KP		 4635}
4636
00c09d70 4637void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4638{
da63a9f2
PZ		 4639 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4640 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4641
4f71d0cb 4642 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4643 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4644 drm_encoder_cleanup(encoder);
bd943159
KP		 4645 if (is_edp(intel_dp)) {
4646 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4647 /*
4648 * vdd might still be enabled do to the delayed vdd off.
4649 * Make sure vdd is actually turned off here.
4650 */
773538e8 4651 pps_lock(intel_dp);
4be73780 4652 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4653 pps_unlock(intel_dp);
4654
01527b31
CT		 4655 if (intel_dp->edp_notifier.notifier_call) {
4656 unregister_reboot_notifier(&intel_dp->edp_notifier);
4657 intel_dp->edp_notifier.notifier_call = NULL;
4658 }
bd943159 4659 }
da63a9f2 4660 kfree(intel_dig_port);
24d05927
DV		 4661}
4662
07f9cd0b
ID		 4663static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4664{
4665 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4666
4667 if (!is_edp(intel_dp))
4668 return;
4669
951468f3
VS		 4670 /*
4671 * vdd might still be enabled do to the delayed vdd off.
4672 * Make sure vdd is actually turned off here.
4673 */
773538e8 4674 pps_lock(intel_dp);
07f9cd0b 4675 edp_panel_vdd_off_sync(intel_dp);
773538e8 4676 pps_unlock(intel_dp);
07f9cd0b
ID		 4677}
4678
49e6bc51
VS		 4679static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4680{
4681 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4682 struct drm_device *dev = intel_dig_port->base.base.dev;
4683 struct drm_i915_private *dev_priv = dev->dev_private;
4684 enum intel_display_power_domain power_domain;
4685
4686 lockdep_assert_held(&dev_priv->pps_mutex);
4687
4688 if (!edp_have_panel_vdd(intel_dp))
4689 return;
4690
4691 /*
4692 * The VDD bit needs a power domain reference, so if the bit is
4693 * already enabled when we boot or resume, grab this reference and
4694 * schedule a vdd off, so we don't hold on to the reference
4695 * indefinitely.
4696 */
4697 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4698 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4699 intel_display_power_get(dev_priv, power_domain);
4700
4701 edp_panel_vdd_schedule_off(intel_dp);
4702}
4703
6d93c0c4
ID		 4704static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4705{
49e6bc51
VS		 4706 struct intel_dp *intel_dp;
4707
4708 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4709 return;
4710
4711 intel_dp = enc_to_intel_dp(encoder);
4712
4713 pps_lock(intel_dp);
4714
4715 /*
4716 * Read out the current power sequencer assignment,
4717 * in case the BIOS did something with it.
4718 */
4719 if (IS_VALLEYVIEW(encoder->dev))
4720 vlv_initial_power_sequencer_setup(intel_dp);
4721
4722 intel_edp_panel_vdd_sanitize(intel_dp);
4723
4724 pps_unlock(intel_dp);
6d93c0c4
ID		 4725}
4726
a4fc5ed6 4727static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4728 .dpms = intel_connector_dpms,
a4fc5ed6 4729 .detect = intel_dp_detect,
beb60608 4730 .force = intel_dp_force,
a4fc5ed6 4731 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4732 .set_property = intel_dp_set_property,
73845adf 4733 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4734};
4735
4736static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4737 .get_modes = intel_dp_get_modes,
4738 .mode_valid = intel_dp_mode_valid,
df0e9248 4739 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4740};
4741
a4fc5ed6 4742static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4743 .reset = intel_dp_encoder_reset,
24d05927 4744 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4745};
4746
0e32b39c 4747void
21d40d37 4748intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4749{
0e32b39c 4750 return;
c8110e52 4751}
6207937d 4752
13cf5504
DA		 4753bool
4754intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4755{
4756 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4757 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4758 struct drm_device *dev = intel_dig_port->base.base.dev;
4759 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4760 enum intel_display_power_domain power_domain;
4761 bool ret = true;
4762
0e32b39c
DA		 4763 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4764 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4765
26fbb774
VS		 4766 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4767 port_name(intel_dig_port->port),
0e32b39c 4768 long_hpd ? "long" : "short");
13cf5504 4769
1c767b33
ID		 4770 power_domain = intel_display_port_power_domain(intel_encoder);
4771 intel_display_power_get(dev_priv, power_domain);
4772
0e32b39c 4773 if (long_hpd) {
2a592bec
DA		 4774
4775 if (HAS_PCH_SPLIT(dev)) {
4776 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4777 goto mst_fail;
4778 } else {
4779 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4780 goto mst_fail;
4781 }
0e32b39c
DA		 4782
4783 if (!intel_dp_get_dpcd(intel_dp)) {
4784 goto mst_fail;
4785 }
4786
4787 intel_dp_probe_oui(intel_dp);
4788
4789 if (!intel_dp_probe_mst(intel_dp))
4790 goto mst_fail;
4791
4792 } else {
4793 if (intel_dp->is_mst) {
1c767b33 4794 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4795 goto mst_fail;
4796 }
4797
4798 if (!intel_dp->is_mst) {
4799 /*
4800 * we'll check the link status via the normal hot plug path later -
4801 * but for short hpds we should check it now
4802 */
5b215bcf 4803 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4804 intel_dp_check_link_status(intel_dp);
5b215bcf 4805 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4806 }
4807 }
1c767b33
ID		 4808 ret = false;
4809 goto put_power;
0e32b39c
DA		 4810mst_fail:
4811 /* if we were in MST mode, and device is not there get out of MST mode */
4812 if (intel_dp->is_mst) {
4813 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4814 intel_dp->is_mst = false;
4815 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4816 }
1c767b33
ID		 4817put_power:
4818 intel_display_power_put(dev_priv, power_domain);
4819
4820 return ret;
13cf5504
DA		 4821}
4822
e3421a18
ZW		 4823/* Return which DP Port should be selected for Transcoder DP control */
4824int
0206e353 4825intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4826{
4827 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4828 struct intel_encoder *intel_encoder;
4829 struct intel_dp *intel_dp;
e3421a18 4830
fa90ecef
PZ		 4831 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4832 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4833
fa90ecef
PZ		 4834 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4835 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4836 return intel_dp->output_reg;
e3421a18 4837 }
ea5b213a 4838
e3421a18
ZW		 4839 return -1;
4840}
4841
36e83a18 4842/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4843bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4844{
4845 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4846 union child_device_config *p_child;
36e83a18 4847 int i;
5d8a7752
VS		 4848 static const short port_mapping[] = {
4849 [PORT_B] = PORT_IDPB,
4850 [PORT_C] = PORT_IDPC,
4851 [PORT_D] = PORT_IDPD,
4852 };
36e83a18 4853
3b32a35b
VS		 4854 if (port == PORT_A)
4855 return true;
4856
41aa3448 4857 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4858 return false;
4859
41aa3448
RV		 4860 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4861 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4862
5d8a7752 4863 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4864 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4865 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4866 return true;
4867 }
4868 return false;
4869}
4870
0e32b39c 4871void
f684960e
CW		 4872intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4873{
53b41837
YN		 4874 struct intel_connector *intel_connector = to_intel_connector(connector);
4875
3f43c48d 4876 intel_attach_force_audio_property(connector);
e953fd7b 4877 intel_attach_broadcast_rgb_property(connector);
55bc60db 4878 intel_dp->color_range_auto = true;
53b41837
YN		 4879
4880 if (is_edp(intel_dp)) {
4881 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4882 drm_object_attach_property(
4883 &connector->base,
53b41837 4884 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4885 DRM_MODE_SCALE_ASPECT);
4886 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4887 }
f684960e
CW		 4888}
4889
dada1a9f
ID		 4890static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4891{
4892 intel_dp->last_power_cycle = jiffies;
4893 intel_dp->last_power_on = jiffies;
4894 intel_dp->last_backlight_off = jiffies;
4895}
4896
67a54566
DV		 4897static void
4898intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4899 struct intel_dp *intel_dp)
67a54566
DV		 4900{
4901 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4902 struct edp_power_seq cur, vbt, spec,
4903 *final = &intel_dp->pps_delays;
67a54566 4904 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4905 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4906
e39b999a
VS		 4907 lockdep_assert_held(&dev_priv->pps_mutex);
4908
81ddbc69
VS		 4909 /* already initialized? */
4910 if (final->t11_t12 != 0)
4911 return;
4912
453c5420 4913 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4914 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4915 pp_on_reg = PCH_PP_ON_DELAYS;
4916 pp_off_reg = PCH_PP_OFF_DELAYS;
4917 pp_div_reg = PCH_PP_DIVISOR;
4918 } else {
bf13e81b
JN		 4919 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4920
4921 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4922 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4923 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4924 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4925 }
67a54566
DV		 4926
4927 /* Workaround: Need to write PP_CONTROL with the unlock key as
4928 * the very first thing. */
453c5420 4929 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4930 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4931
453c5420
JB		 4932 pp_on = I915_READ(pp_on_reg);
4933 pp_off = I915_READ(pp_off_reg);
4934 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4935
4936 /* Pull timing values out of registers */
4937 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4938 PANEL_POWER_UP_DELAY_SHIFT;
4939
4940 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4941 PANEL_LIGHT_ON_DELAY_SHIFT;
4942
4943 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4944 PANEL_LIGHT_OFF_DELAY_SHIFT;
4945
4946 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4947 PANEL_POWER_DOWN_DELAY_SHIFT;
4948
4949 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4950 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4951
4952 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4953 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4954
41aa3448 4955 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4956
4957 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4958 * our hw here, which are all in 100usec. */
4959 spec.t1_t3 = 210 * 10;
4960 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4961 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4962 spec.t10 = 500 * 10;
4963 /* This one is special and actually in units of 100ms, but zero
4964 * based in the hw (so we need to add 100 ms). But the sw vbt
4965 * table multiplies it with 1000 to make it in units of 100usec,
4966 * too. */
4967 spec.t11_t12 = (510 + 100) * 10;
4968
4969 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4970 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4971
4972 /* Use the max of the register settings and vbt. If both are
4973 * unset, fall back to the spec limits. */
36b5f425 4974#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4975 spec.field : \
4976 max(cur.field, vbt.field))
4977 assign_final(t1_t3);
4978 assign_final(t8);
4979 assign_final(t9);
4980 assign_final(t10);
4981 assign_final(t11_t12);
4982#undef assign_final
4983
36b5f425 4984#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4985 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4986 intel_dp->backlight_on_delay = get_delay(t8);
4987 intel_dp->backlight_off_delay = get_delay(t9);
4988 intel_dp->panel_power_down_delay = get_delay(t10);
4989 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4990#undef get_delay
4991
f30d26e4
JN		 4992 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4993 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4994 intel_dp->panel_power_cycle_delay);
4995
4996 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4997 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4998}
4999
5000static void
5001intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 5002 struct intel_dp *intel_dp)
f30d26e4
JN		 5003{
5004 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 5005 u32 pp_on, pp_off, pp_div, port_sel = 0;
5006 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
5007 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 5008 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 5009 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 5010
e39b999a 5011 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 5012
5013 if (HAS_PCH_SPLIT(dev)) {
5014 pp_on_reg = PCH_PP_ON_DELAYS;
5015 pp_off_reg = PCH_PP_OFF_DELAYS;
5016 pp_div_reg = PCH_PP_DIVISOR;
5017 } else {
bf13e81b
JN		 5018 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5019
5020 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5021 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5022 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 5023 }
5024
b2f19d1a
PZ		 5025 /*
5026 * And finally store the new values in the power sequencer. The
5027 * backlight delays are set to 1 because we do manual waits on them. For
5028 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5029 * we'll end up waiting for the backlight off delay twice: once when we
5030 * do the manual sleep, and once when we disable the panel and wait for
5031 * the PP_STATUS bit to become zero.
5032 */
f30d26e4 5033 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 5034 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5035 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5036 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5037 /* Compute the divisor for the pp clock, simply match the Bspec
5038 * formula. */
453c5420 5039 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 5040 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 5041 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5042
5043 /* Haswell doesn't have any port selection bits for the panel
5044 * power sequencer any more. */
bc7d38a4 5045 if (IS_VALLEYVIEW(dev)) {
ad933b56 5046 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 5047 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 5048 if (port == PORT_A)
a24c144c 5049 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5050 else
a24c144c 5051 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5052 }
5053
453c5420
JB		 5054 pp_on |= port_sel;
5055
5056 I915_WRITE(pp_on_reg, pp_on);
5057 I915_WRITE(pp_off_reg, pp_off);
5058 I915_WRITE(pp_div_reg, pp_div);
67a54566 5059
67a54566 5060 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 5061 I915_READ(pp_on_reg),
5062 I915_READ(pp_off_reg),
5063 I915_READ(pp_div_reg));
f684960e
CW		 5064}
5065
439d7ac0
PB		 5066void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5067{
5068 struct drm_i915_private *dev_priv = dev->dev_private;
5069 struct intel_encoder *encoder;
5070 struct intel_dp *intel_dp = NULL;
5071 struct intel_crtc_config *config = NULL;
5072 struct intel_crtc *intel_crtc = NULL;
5073 struct intel_connector *intel_connector = dev_priv->drrs.connector;
5074 u32 reg, val;
5075 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
5076
5077 if (refresh_rate <= 0) {
5078 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5079 return;
5080 }
5081
5082 if (intel_connector == NULL) {
5083 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
5084 return;
5085 }
5086
1fcc9d1c
DV		 5087 /*
5088 * FIXME: This needs proper synchronization with psr state. But really
5089 * hard to tell without seeing the user of this function of this code.
5090 * Check locking and ordering once that lands.
5091 */
439d7ac0
PB		 5092 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
5093 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
5094 return;
5095 }
5096
5097 encoder = intel_attached_encoder(&intel_connector->base);
5098 intel_dp = enc_to_intel_dp(&encoder->base);
5099 intel_crtc = encoder->new_crtc;
5100
5101 if (!intel_crtc) {
5102 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5103 return;
5104 }
5105
5106 config = &intel_crtc->config;
5107
5108 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
5109 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5110 return;
5111 }
5112
5113 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
5114 index = DRRS_LOW_RR;
5115
5116 if (index == intel_dp->drrs_state.refresh_rate_type) {
5117 DRM_DEBUG_KMS(
5118 "DRRS requested for previously set RR...ignoring\n");
5119 return;
5120 }
5121
5122 if (!intel_crtc->active) {
5123 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5124 return;
5125 }
5126
5127 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
5128 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
5129 val = I915_READ(reg);
5130 if (index > DRRS_HIGH_RR) {
5131 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 5132 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 5133 } else {
5134 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5135 }
5136 I915_WRITE(reg, val);
5137 }
5138
5139 /*
5140 * mutex taken to ensure that there is no race between differnt
5141 * drrs calls trying to update refresh rate. This scenario may occur
5142 * in future when idleness detection based DRRS in kernel and
5143 * possible calls from user space to set differnt RR are made.
5144 */
5145
5146 mutex_lock(&intel_dp->drrs_state.mutex);
5147
5148 intel_dp->drrs_state.refresh_rate_type = index;
5149
5150 mutex_unlock(&intel_dp->drrs_state.mutex);
5151
5152 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5153}
5154
4f9db5b5
PB		 5155static struct drm_display_mode *
5156intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
5157 struct intel_connector *intel_connector,
5158 struct drm_display_mode *fixed_mode)
5159{
5160 struct drm_connector *connector = &intel_connector->base;
5161 struct intel_dp *intel_dp = &intel_dig_port->dp;
5162 struct drm_device *dev = intel_dig_port->base.base.dev;
5163 struct drm_i915_private *dev_priv = dev->dev_private;
5164 struct drm_display_mode *downclock_mode = NULL;
5165
5166 if (INTEL_INFO(dev)->gen <= 6) {
5167 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5168 return NULL;
5169 }
5170
5171 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5172 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5173 return NULL;
5174 }
5175
5176 downclock_mode = intel_find_panel_downclock
5177 (dev, fixed_mode, connector);
5178
5179 if (!downclock_mode) {
4079b8d1 5180 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 5181 return NULL;
5182 }
5183
439d7ac0
PB		 5184 dev_priv->drrs.connector = intel_connector;
5185
5186 mutex_init(&intel_dp->drrs_state.mutex);
5187
4f9db5b5
PB		 5188 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
5189
5190 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5191 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5192 return downclock_mode;
5193}
5194
ed92f0b2 5195static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5196 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5197{
5198 struct drm_connector *connector = &intel_connector->base;
5199 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5200 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5201 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5202 struct drm_i915_private *dev_priv = dev->dev_private;
5203 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5204 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5205 bool has_dpcd;
5206 struct drm_display_mode *scan;
5207 struct edid *edid;
5208
4f9db5b5
PB		 5209 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
5210
ed92f0b2
PZ		 5211 if (!is_edp(intel_dp))
5212 return true;
5213
49e6bc51
VS		 5214 pps_lock(intel_dp);
5215 intel_edp_panel_vdd_sanitize(intel_dp);
5216 pps_unlock(intel_dp);
63635217 5217
ed92f0b2 5218 /* Cache DPCD and EDID for edp. */
ed92f0b2 5219 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5220
5221 if (has_dpcd) {
5222 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5223 dev_priv->no_aux_handshake =
5224 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5225 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5226 } else {
5227 /* if this fails, presume the device is a ghost */
5228 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5229 return false;
5230 }
5231
5232 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5233 pps_lock(intel_dp);
36b5f425 5234 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5235 pps_unlock(intel_dp);
ed92f0b2 5236
060c8778 5237 mutex_lock(&dev->mode_config.mutex);
0b99836f 5238 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5239 if (edid) {
5240 if (drm_add_edid_modes(connector, edid)) {
5241 drm_mode_connector_update_edid_property(connector,
5242 edid);
5243 drm_edid_to_eld(connector, edid);
5244 } else {
5245 kfree(edid);
5246 edid = ERR_PTR(-EINVAL);
5247 }
5248 } else {
5249 edid = ERR_PTR(-ENOENT);
5250 }
5251 intel_connector->edid = edid;
5252
5253 /* prefer fixed mode from EDID if available */
5254 list_for_each_entry(scan, &connector->probed_modes, head) {
5255 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5256 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5257 downclock_mode = intel_dp_drrs_init(
5258 intel_dig_port,
5259 intel_connector, fixed_mode);
ed92f0b2
PZ		 5260 break;
5261 }
5262 }
5263
5264 /* fallback to VBT if available for eDP */
5265 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5266 fixed_mode = drm_mode_duplicate(dev,
5267 dev_priv->vbt.lfp_lvds_vbt_mode);
5268 if (fixed_mode)
5269 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5270 }
060c8778 5271 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5272
01527b31
CT		 5273 if (IS_VALLEYVIEW(dev)) {
5274 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5275 register_reboot_notifier(&intel_dp->edp_notifier);
5276 }
5277
4f9db5b5 5278 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5279 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5280 intel_panel_setup_backlight(connector);
5281
5282 return true;
5283}
5284
16c25533 5285bool
f0fec3f2
PZ		 5286intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5287 struct intel_connector *intel_connector)
a4fc5ed6 5288{
f0fec3f2
PZ		 5289 struct drm_connector *connector = &intel_connector->base;
5290 struct intel_dp *intel_dp = &intel_dig_port->dp;
5291 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5292 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5293 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5294 enum port port = intel_dig_port->port;
0b99836f 5295 int type;
a4fc5ed6 5296
a4a5d2f8
VS		 5297 intel_dp->pps_pipe = INVALID_PIPE;
5298
ec5b01dd 5299 /* intel_dp vfuncs */
b6b5e383
DL		 5300 if (INTEL_INFO(dev)->gen >= 9)
5301 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5302 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5303 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5304 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5305 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5306 else if (HAS_PCH_SPLIT(dev))
5307 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5308 else
5309 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5310
b9ca5fad
DL		 5311 if (INTEL_INFO(dev)->gen >= 9)
5312 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5313 else
5314 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5315
0767935e
DV		 5316 /* Preserve the current hw state. */
5317 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5318 intel_dp->attached_connector = intel_connector;
3d3dc149 5319
3b32a35b 5320 if (intel_dp_is_edp(dev, port))
b329530c 5321 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5322 else
5323 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5324
f7d24902
ID		 5325 /*
5326 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5327 * for DP the encoder type can be set by the caller to
5328 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5329 */
5330 if (type == DRM_MODE_CONNECTOR_eDP)
5331 intel_encoder->type = INTEL_OUTPUT_EDP;
5332
c17ed5b5
VS		 5333 /* eDP only on port B and/or C on vlv/chv */
5334 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5335 port != PORT_B && port != PORT_C))
5336 return false;
5337
e7281eab
ID		 5338 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5339 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5340 port_name(port));
5341
b329530c 5342 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5343 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5344
a4fc5ed6
KP		 5345 connector->interlace_allowed = true;
5346 connector->doublescan_allowed = 0;
5347
f0fec3f2 5348 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5349 edp_panel_vdd_work);
a4fc5ed6 5350
df0e9248 5351 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5352 drm_connector_register(connector);
a4fc5ed6 5353
affa9354 5354 if (HAS_DDI(dev))
bcbc889b
PZ		 5355 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5356 else
5357 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5358 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5359
0b99836f 5360 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5361 switch (port) {
5362 case PORT_A:
1d843f9d 5363 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5364 break;
5365 case PORT_B:
1d843f9d 5366 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5367 break;
5368 case PORT_C:
1d843f9d 5369 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5370 break;
5371 case PORT_D:
1d843f9d 5372 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5373 break;
5374 default:
ad1c0b19 5375 BUG();
5eb08b69
ZW		 5376 }
5377
dada1a9f 5378 if (is_edp(intel_dp)) {
773538e8 5379 pps_lock(intel_dp);
1e74a324
VS		 5380 intel_dp_init_panel_power_timestamps(intel_dp);
5381 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5382 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5383 else
36b5f425 5384 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5385 pps_unlock(intel_dp);
dada1a9f 5386 }
0095e6dc 5387
9d1a1031 5388 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5389
0e32b39c
DA		 5390 /* init MST on ports that can support it */
5391 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5392 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5393 intel_dp_mst_encoder_init(intel_dig_port,
5394 intel_connector->base.base.id);
0e32b39c
DA		 5395 }
5396 }
5397
36b5f425 5398 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5399 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5400 if (is_edp(intel_dp)) {
5401 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5402 /*
5403 * vdd might still be enabled do to the delayed vdd off.
5404 * Make sure vdd is actually turned off here.
5405 */
773538e8 5406 pps_lock(intel_dp);
4be73780 5407 edp_panel_vdd_off_sync(intel_dp);
773538e8 5408 pps_unlock(intel_dp);
15b1d171 5409 }
34ea3d38 5410 drm_connector_unregister(connector);
b2f246a8 5411 drm_connector_cleanup(connector);
16c25533 5412 return false;
b2f246a8 5413 }
32f9d658 5414
f684960e
CW		 5415 intel_dp_add_properties(intel_dp, connector);
5416
a4fc5ed6
KP		 5417 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5418 * 0xd. Failure to do so will result in spurious interrupts being
5419 * generated on the port when a cable is not attached.
5420 */
5421 if (IS_G4X(dev) && !IS_GM45(dev)) {
5422 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5423 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5424 }
16c25533
PZ		 5425
5426 return true;
a4fc5ed6 5427}
f0fec3f2
PZ		 5428
5429void
5430intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5431{
13cf5504 5432 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5433 struct intel_digital_port *intel_dig_port;
5434 struct intel_encoder *intel_encoder;
5435 struct drm_encoder *encoder;
5436 struct intel_connector *intel_connector;
5437
b14c5679 5438 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5439 if (!intel_dig_port)
5440 return;
5441
b14c5679 5442 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5443 if (!intel_connector) {
5444 kfree(intel_dig_port);
5445 return;
5446 }
5447
5448 intel_encoder = &intel_dig_port->base;
5449 encoder = &intel_encoder->base;
5450
5451 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5452 DRM_MODE_ENCODER_TMDS);
5453
5bfe2ac0 5454 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5455 intel_encoder->disable = intel_disable_dp;
00c09d70 5456 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5457 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5458 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5459 if (IS_CHERRYVIEW(dev)) {
9197c88b 5460 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5461 intel_encoder->pre_enable = chv_pre_enable_dp;
5462 intel_encoder->enable = vlv_enable_dp;
580d3811 5463 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5464 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5465 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5466 intel_encoder->pre_enable = vlv_pre_enable_dp;
5467 intel_encoder->enable = vlv_enable_dp;
49277c31 5468 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5469 } else {
ecff4f3b
JN		 5470 intel_encoder->pre_enable = g4x_pre_enable_dp;
5471 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5472 if (INTEL_INFO(dev)->gen >= 5)
5473 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5474 }
f0fec3f2 5475
174edf1f 5476 intel_dig_port->port = port;
f0fec3f2
PZ		 5477 intel_dig_port->dp.output_reg = output_reg;
5478
00c09d70 5479 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5480 if (IS_CHERRYVIEW(dev)) {
5481 if (port == PORT_D)
5482 intel_encoder->crtc_mask = 1 << 2;
5483 else
5484 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5485 } else {
5486 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5487 }
bc079e8b 5488 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5489 intel_encoder->hot_plug = intel_dp_hot_plug;
5490
13cf5504
DA		 5491 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5492 dev_priv->hpd_irq_port[port] = intel_dig_port;
5493
15b1d171
PZ		 5494 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5495 drm_encoder_cleanup(encoder);
5496 kfree(intel_dig_port);
b2f246a8 5497 kfree(intel_connector);
15b1d171 5498 }
f0fec3f2 5499}
0e32b39c
DA		 5500
5501void intel_dp_mst_suspend(struct drm_device *dev)
5502{
5503 struct drm_i915_private *dev_priv = dev->dev_private;
5504 int i;
5505
5506 /* disable MST */
5507 for (i = 0; i < I915_MAX_PORTS; i++) {
5508 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5509 if (!intel_dig_port)
5510 continue;
5511
5512 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5513 if (!intel_dig_port->dp.can_mst)
5514 continue;
5515 if (intel_dig_port->dp.is_mst)
5516 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5517 }
5518 }
5519}
5520
5521void intel_dp_mst_resume(struct drm_device *dev)
5522{
5523 struct drm_i915_private *dev_priv = dev->dev_private;
5524 int i;
5525
5526 for (i = 0; i < I915_MAX_PORTS; i++) {
5527 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5528 if (!intel_dig_port)
5529 continue;
5530 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5531 int ret;
5532
5533 if (!intel_dig_port->dp.can_mst)
5534 continue;
5535
5536 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5537 if (ret != 0) {
5538 intel_dp_check_mst_status(&intel_dig_port->dp);
5539 }
5540 }
5541 }
5542}
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