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drm/i915/chv: Set soft reset override bit for data lane resets
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
ef9348c8
CML		 67/*
68 * CHV supports eDP 1.4 that have more link rates.
69 * Below only provides the fixed rate but exclude variable rate.
70 */
71static const struct dp_link_dpll chv_dpll[] = {
72 /*
73 * CHV requires to program fractional division for m2.
74 * m2 is stored in fixed point format using formula below
75 * (m2_int << 22) | m2_fraction
76 */
77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
83};
84
cfcb0fc9
JB		 85/**
86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
87 * @intel_dp: DP struct
88 *
89 * If a CPU or PCH DP output is attached to an eDP panel, this function
90 * will return true, and false otherwise.
91 */
92static bool is_edp(struct intel_dp *intel_dp)
93{
da63a9f2
PZ		 94 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
95
96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 97}
98
68b4d824 99static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 100{
68b4d824
ID		 101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
102
103 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 104}
105
df0e9248
CW		 106static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
107{
fa90ecef 108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 109}
110
ea5b213a 111static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 112static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 113static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 114
a4fc5ed6 115static int
ea5b213a 116intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 117{
7183dc29 118 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 119 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 120
121 switch (max_link_bw) {
122 case DP_LINK_BW_1_62:
123 case DP_LINK_BW_2_7:
124 break;
d4eead50 125 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 126 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
127 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
128 max_link_bw = DP_LINK_BW_5_4;
129 else
130 max_link_bw = DP_LINK_BW_2_7;
d4eead50 131 break;
a4fc5ed6 132 default:
d4eead50
ID		 133 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
134 max_link_bw);
a4fc5ed6
KP		 135 max_link_bw = DP_LINK_BW_1_62;
136 break;
137 }
138 return max_link_bw;
139}
140
cd9dde44
AJ		 141/*
142 * The units on the numbers in the next two are... bizarre. Examples will
143 * make it clearer; this one parallels an example in the eDP spec.
144 *
145 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
146 *
147 * 270000 * 1 * 8 / 10 == 216000
148 *
149 * The actual data capacity of that configuration is 2.16Gbit/s, so the
150 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
151 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
152 * 119000. At 18bpp that's 2142000 kilobits per second.
153 *
154 * Thus the strange-looking division by 10 in intel_dp_link_required, to
155 * get the result in decakilobits instead of kilobits.
156 */
157
a4fc5ed6 158static int
c898261c 159intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 160{
cd9dde44 161 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 162}
163
fe27d53e
DA		 164static int
165intel_dp_max_data_rate(int max_link_clock, int max_lanes)
166{
167 return (max_link_clock * max_lanes * 8) / 10;
168}
169
c19de8eb 170static enum drm_mode_status
a4fc5ed6
KP		 171intel_dp_mode_valid(struct drm_connector *connector,
172 struct drm_display_mode *mode)
173{
df0e9248 174 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 175 struct intel_connector *intel_connector = to_intel_connector(connector);
176 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 177 int target_clock = mode->clock;
178 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 179
dd06f90e
JN		 180 if (is_edp(intel_dp) && fixed_mode) {
181 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 182 return MODE_PANEL;
183
dd06f90e 184 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 185 return MODE_PANEL;
03afc4a2
DV		 186
187 target_clock = fixed_mode->clock;
7de56f43
ZY		 188 }
189
36008365
DV		 190 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
191 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
192
193 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
194 mode_rate = intel_dp_link_required(target_clock, 18);
195
196 if (mode_rate > max_rate)
c4867936 197 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 198
199 if (mode->clock < 10000)
200 return MODE_CLOCK_LOW;
201
0af78a2b
DV		 202 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
203 return MODE_H_ILLEGAL;
204
a4fc5ed6
KP		 205 return MODE_OK;
206}
207
208static uint32_t
209pack_aux(uint8_t *src, int src_bytes)
210{
211 int i;
212 uint32_t v = 0;
213
214 if (src_bytes > 4)
215 src_bytes = 4;
216 for (i = 0; i < src_bytes; i++)
217 v |= ((uint32_t) src[i]) << ((3-i) * 8);
218 return v;
219}
220
221static void
222unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
223{
224 int i;
225 if (dst_bytes > 4)
226 dst_bytes = 4;
227 for (i = 0; i < dst_bytes; i++)
228 dst[i] = src >> ((3-i) * 8);
229}
230
fb0f8fbf
KP		 231/* hrawclock is 1/4 the FSB frequency */
232static int
233intel_hrawclk(struct drm_device *dev)
234{
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 uint32_t clkcfg;
237
9473c8f4
VP		 238 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
239 if (IS_VALLEYVIEW(dev))
240 return 200;
241
fb0f8fbf
KP		 242 clkcfg = I915_READ(CLKCFG);
243 switch (clkcfg & CLKCFG_FSB_MASK) {
244 case CLKCFG_FSB_400:
245 return 100;
246 case CLKCFG_FSB_533:
247 return 133;
248 case CLKCFG_FSB_667:
249 return 166;
250 case CLKCFG_FSB_800:
251 return 200;
252 case CLKCFG_FSB_1067:
253 return 266;
254 case CLKCFG_FSB_1333:
255 return 333;
256 /* these two are just a guess; one of them might be right */
257 case CLKCFG_FSB_1600:
258 case CLKCFG_FSB_1600_ALT:
259 return 400;
260 default:
261 return 133;
262 }
263}
264
bf13e81b
JN		 265static void
266intel_dp_init_panel_power_sequencer(struct drm_device *dev,
267 struct intel_dp *intel_dp,
268 struct edp_power_seq *out);
269static void
270intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
271 struct intel_dp *intel_dp,
272 struct edp_power_seq *out);
273
274static enum pipe
275vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
276{
277 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
278 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
279 struct drm_device *dev = intel_dig_port->base.base.dev;
280 struct drm_i915_private *dev_priv = dev->dev_private;
281 enum port port = intel_dig_port->port;
282 enum pipe pipe;
283
284 /* modeset should have pipe */
285 if (crtc)
286 return to_intel_crtc(crtc)->pipe;
287
288 /* init time, try to find a pipe with this port selected */
289 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
290 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
291 PANEL_PORT_SELECT_MASK;
292 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
293 return pipe;
294 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
295 return pipe;
296 }
297
298 /* shrug */
299 return PIPE_A;
300}
301
302static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
303{
304 struct drm_device *dev = intel_dp_to_dev(intel_dp);
305
306 if (HAS_PCH_SPLIT(dev))
307 return PCH_PP_CONTROL;
308 else
309 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
310}
311
312static u32 _pp_stat_reg(struct intel_dp *intel_dp)
313{
314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
315
316 if (HAS_PCH_SPLIT(dev))
317 return PCH_PP_STATUS;
318 else
319 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
320}
321
4be73780 322static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 323{
30add22d 324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 325 struct drm_i915_private *dev_priv = dev->dev_private;
326
bf13e81b 327 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 328}
329
4be73780 330static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 331{
30add22d 332 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 333 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 334 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
335 struct intel_encoder *intel_encoder = &intel_dig_port->base;
336 enum intel_display_power_domain power_domain;
ebf33b18 337
bb4932c4
ID		 338 power_domain = intel_display_port_power_domain(intel_encoder);
339 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 340 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 341}
342
9b984dae
KP		 343static void
344intel_dp_check_edp(struct intel_dp *intel_dp)
345{
30add22d 346 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 347 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 348
9b984dae
KP		 349 if (!is_edp(intel_dp))
350 return;
453c5420 351
4be73780 352 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 353 WARN(1, "eDP powered off while attempting aux channel communication.\n");
354 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 355 I915_READ(_pp_stat_reg(intel_dp)),
356 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 357 }
358}
359
9ee32fea
DV		 360static uint32_t
361intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
362{
363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
364 struct drm_device *dev = intel_dig_port->base.base.dev;
365 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 366 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 367 uint32_t status;
368 bool done;
369
ef04f00d 370#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 371 if (has_aux_irq)
b18ac466 372 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 373 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 374 else
375 done = wait_for_atomic(C, 10) == 0;
376 if (!done)
377 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
378 has_aux_irq);
379#undef C
380
381 return status;
382}
383
ec5b01dd 384static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 385{
174edf1f
PZ		 386 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
387 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 388
ec5b01dd
DL		 389 /*
390 * The clock divider is based off the hrawclk, and would like to run at
391 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 392 */
ec5b01dd
DL		 393 return index ? 0 : intel_hrawclk(dev) / 2;
394}
395
396static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
397{
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400
401 if (index)
402 return 0;
403
404 if (intel_dig_port->port == PORT_A) {
405 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 406 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 407 else
b84a1cf8 408 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 409 } else {
410 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
411 }
412}
413
414static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
415{
416 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
417 struct drm_device *dev = intel_dig_port->base.base.dev;
418 struct drm_i915_private *dev_priv = dev->dev_private;
419
420 if (intel_dig_port->port == PORT_A) {
421 if (index)
422 return 0;
423 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 424 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
425 /* Workaround for non-ULT HSW */
bc86625a
CW		 426 switch (index) {
427 case 0: return 63;
428 case 1: return 72;
429 default: return 0;
430 }
ec5b01dd 431 } else {
bc86625a 432 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 433 }
b84a1cf8
RV		 434}
435
ec5b01dd
DL		 436static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
437{
438 return index ? 0 : 100;
439}
440
5ed12a19
DL		 441static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
442 bool has_aux_irq,
443 int send_bytes,
444 uint32_t aux_clock_divider)
445{
446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
447 struct drm_device *dev = intel_dig_port->base.base.dev;
448 uint32_t precharge, timeout;
449
450 if (IS_GEN6(dev))
451 precharge = 3;
452 else
453 precharge = 5;
454
455 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
456 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
457 else
458 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
459
460 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 461 DP_AUX_CH_CTL_DONE |
5ed12a19 462 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 463 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 464 timeout |
788d4433 465 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 466 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
467 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 468 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 469}
470
b84a1cf8
RV		 471static int
472intel_dp_aux_ch(struct intel_dp *intel_dp,
473 uint8_t *send, int send_bytes,
474 uint8_t *recv, int recv_size)
475{
476 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
477 struct drm_device *dev = intel_dig_port->base.base.dev;
478 struct drm_i915_private *dev_priv = dev->dev_private;
479 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
480 uint32_t ch_data = ch_ctl + 4;
bc86625a 481 uint32_t aux_clock_divider;
b84a1cf8
RV		 482 int i, ret, recv_bytes;
483 uint32_t status;
5ed12a19 484 int try, clock = 0;
4e6b788c 485 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 486 bool vdd;
487
488 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 489
490 /* dp aux is extremely sensitive to irq latency, hence request the
491 * lowest possible wakeup latency and so prevent the cpu from going into
492 * deep sleep states.
493 */
494 pm_qos_update_request(&dev_priv->pm_qos, 0);
495
496 intel_dp_check_edp(intel_dp);
5eb08b69 497
c67a470b
PZ		 498 intel_aux_display_runtime_get(dev_priv);
499
11bee43e
JB		 500 /* Try to wait for any previous AUX channel activity */
501 for (try = 0; try < 3; try++) {
ef04f00d 502 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 503 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
504 break;
505 msleep(1);
506 }
507
508 if (try == 3) {
509 WARN(1, "dp_aux_ch not started status 0x%08x\n",
510 I915_READ(ch_ctl));
9ee32fea
DV		 511 ret = -EBUSY;
512 goto out;
4f7f7b7e
CW		 513 }
514
46a5ae9f
PZ		 515 /* Only 5 data registers! */
516 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
517 ret = -E2BIG;
518 goto out;
519 }
520
ec5b01dd 521 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 522 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
523 has_aux_irq,
524 send_bytes,
525 aux_clock_divider);
5ed12a19 526
bc86625a
CW		 527 /* Must try at least 3 times according to DP spec */
528 for (try = 0; try < 5; try++) {
529 /* Load the send data into the aux channel data registers */
530 for (i = 0; i < send_bytes; i += 4)
531 I915_WRITE(ch_data + i,
532 pack_aux(send + i, send_bytes - i));
533
534 /* Send the command and wait for it to complete */
5ed12a19 535 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 536
537 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
538
539 /* Clear done status and any errors */
540 I915_WRITE(ch_ctl,
541 status |
542 DP_AUX_CH_CTL_DONE |
543 DP_AUX_CH_CTL_TIME_OUT_ERROR |
544 DP_AUX_CH_CTL_RECEIVE_ERROR);
545
546 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
547 DP_AUX_CH_CTL_RECEIVE_ERROR))
548 continue;
549 if (status & DP_AUX_CH_CTL_DONE)
550 break;
551 }
4f7f7b7e 552 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 553 break;
554 }
555
a4fc5ed6 556 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 557 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 558 ret = -EBUSY;
559 goto out;
a4fc5ed6
KP		 560 }
561
562 /* Check for timeout or receive error.
563 * Timeouts occur when the sink is not connected
564 */
a5b3da54 565 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 566 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 567 ret = -EIO;
568 goto out;
a5b3da54 569 }
1ae8c0a5
KP		 570
571 /* Timeouts occur when the device isn't connected, so they're
572 * "normal" -- don't fill the kernel log with these */
a5b3da54 573 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 574 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 575 ret = -ETIMEDOUT;
576 goto out;
a4fc5ed6
KP		 577 }
578
579 /* Unload any bytes sent back from the other side */
580 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
581 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 582 if (recv_bytes > recv_size)
583 recv_bytes = recv_size;
0206e353 584
4f7f7b7e
CW		 585 for (i = 0; i < recv_bytes; i += 4)
586 unpack_aux(I915_READ(ch_data + i),
587 recv + i, recv_bytes - i);
a4fc5ed6 588
9ee32fea
DV		 589 ret = recv_bytes;
590out:
591 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 592 intel_aux_display_runtime_put(dev_priv);
9ee32fea 593
884f19e9
JN		 594 if (vdd)
595 edp_panel_vdd_off(intel_dp, false);
596
9ee32fea 597 return ret;
a4fc5ed6
KP		 598}
599
a6c8aff0
JN		 600#define BARE_ADDRESS_SIZE 3
601#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 602static ssize_t
603intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 604{
9d1a1031
JN		 605 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
606 uint8_t txbuf[20], rxbuf[20];
607 size_t txsize, rxsize;
a4fc5ed6 608 int ret;
a4fc5ed6 609
9d1a1031
JN		 610 txbuf[0] = msg->request << 4;
611 txbuf[1] = msg->address >> 8;
612 txbuf[2] = msg->address & 0xff;
613 txbuf[3] = msg->size - 1;
46a5ae9f 614
9d1a1031
JN		 615 switch (msg->request & ~DP_AUX_I2C_MOT) {
616 case DP_AUX_NATIVE_WRITE:
617 case DP_AUX_I2C_WRITE:
a6c8aff0 618 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 619 rxsize = 1;
f51a44b9 620
9d1a1031
JN		 621 if (WARN_ON(txsize > 20))
622 return -E2BIG;
a4fc5ed6 623
9d1a1031 624 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 625
9d1a1031
JN		 626 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
627 if (ret > 0) {
628 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 629
9d1a1031
JN		 630 /* Return payload size. */
631 ret = msg->size;
632 }
633 break;
46a5ae9f 634
9d1a1031
JN		 635 case DP_AUX_NATIVE_READ:
636 case DP_AUX_I2C_READ:
a6c8aff0 637 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 638 rxsize = msg->size + 1;
a4fc5ed6 639
9d1a1031
JN		 640 if (WARN_ON(rxsize > 20))
641 return -E2BIG;
a4fc5ed6 642
9d1a1031
JN		 643 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
644 if (ret > 0) {
645 msg->reply = rxbuf[0] >> 4;
646 /*
647 * Assume happy day, and copy the data. The caller is
648 * expected to check msg->reply before touching it.
649 *
650 * Return payload size.
651 */
652 ret--;
653 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 654 }
9d1a1031
JN		 655 break;
656
657 default:
658 ret = -EINVAL;
659 break;
a4fc5ed6 660 }
f51a44b9 661
9d1a1031 662 return ret;
a4fc5ed6
KP		 663}
664
9d1a1031
JN		 665static void
666intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
667{
668 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
670 enum port port = intel_dig_port->port;
0b99836f 671 const char *name = NULL;
ab2c0672
DA		 672 int ret;
673
33ad6626
JN		 674 switch (port) {
675 case PORT_A:
676 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 677 name = "DPDDC-A";
ab2c0672 678 break;
33ad6626
JN		 679 case PORT_B:
680 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 681 name = "DPDDC-B";
ab2c0672 682 break;
33ad6626
JN		 683 case PORT_C:
684 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 685 name = "DPDDC-C";
ab2c0672 686 break;
33ad6626
JN		 687 case PORT_D:
688 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 689 name = "DPDDC-D";
33ad6626
JN		 690 break;
691 default:
692 BUG();
ab2c0672
DA		 693 }
694
33ad6626
JN		 695 if (!HAS_DDI(dev))
696 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 697
0b99836f 698 intel_dp->aux.name = name;
9d1a1031
JN		 699 intel_dp->aux.dev = dev->dev;
700 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 701
0b99836f
JN		 702 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
703 connector->base.kdev->kobj.name);
8316f337 704
0b99836f
JN		 705 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
706 if (ret < 0) {
707 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
708 name, ret);
709 return;
ab2c0672 710 }
8a5e6aeb 711
0b99836f
JN		 712 ret = sysfs_create_link(&connector->base.kdev->kobj,
713 &intel_dp->aux.ddc.dev.kobj,
714 intel_dp->aux.ddc.dev.kobj.name);
715 if (ret < 0) {
716 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
717 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
ab2c0672 718 }
a4fc5ed6
KP		 719}
720
80f65de3
ID		 721static void
722intel_dp_connector_unregister(struct intel_connector *intel_connector)
723{
724 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
725
726 sysfs_remove_link(&intel_connector->base.kdev->kobj,
0b99836f 727 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 728 intel_connector_unregister(intel_connector);
729}
730
c6bb3538
DV		 731static void
732intel_dp_set_clock(struct intel_encoder *encoder,
733 struct intel_crtc_config *pipe_config, int link_bw)
734{
735 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 736 const struct dp_link_dpll *divisor = NULL;
737 int i, count = 0;
c6bb3538
DV		 738
739 if (IS_G4X(dev)) {
9dd4ffdf
CML		 740 divisor = gen4_dpll;
741 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 742 } else if (IS_HASWELL(dev)) {
743 /* Haswell has special-purpose DP DDI clocks. */
744 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 745 divisor = pch_dpll;
746 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 747 } else if (IS_CHERRYVIEW(dev)) {
748 divisor = chv_dpll;
749 count = ARRAY_SIZE(chv_dpll);
c6bb3538 750 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 751 divisor = vlv_dpll;
752 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 753 }
9dd4ffdf
CML		 754
755 if (divisor && count) {
756 for (i = 0; i < count; i++) {
757 if (link_bw == divisor[i].link_bw) {
758 pipe_config->dpll = divisor[i].dpll;
759 pipe_config->clock_set = true;
760 break;
761 }
762 }
c6bb3538
DV		 763 }
764}
765
439d7ac0
PB		 766static void
767intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
768{
769 struct drm_device *dev = crtc->base.dev;
770 struct drm_i915_private *dev_priv = dev->dev_private;
771 enum transcoder transcoder = crtc->config.cpu_transcoder;
772
773 I915_WRITE(PIPE_DATA_M2(transcoder),
774 TU_SIZE(m_n->tu) | m_n->gmch_m);
775 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
776 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
777 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
778}
779
00c09d70 780bool
5bfe2ac0
DV		 781intel_dp_compute_config(struct intel_encoder *encoder,
782 struct intel_crtc_config *pipe_config)
a4fc5ed6 783{
5bfe2ac0 784 struct drm_device *dev = encoder->base.dev;
36008365 785 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 786 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 787 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 788 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 789 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 790 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 791 int lane_count, clock;
397fe157 792 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 793 /* Conveniently, the link BW constants become indices with a shift...*/
794 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 795 int bpp, mode_rate;
06ea66b6 796 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 797 int link_avail, link_clock;
a4fc5ed6 798
bc7d38a4 799 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 800 pipe_config->has_pch_encoder = true;
801
03afc4a2 802 pipe_config->has_dp_encoder = true;
9ed109a7 803 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 804
dd06f90e
JN		 805 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
806 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
807 adjusted_mode);
2dd24552
JB		 808 if (!HAS_PCH_SPLIT(dev))
809 intel_gmch_panel_fitting(intel_crtc, pipe_config,
810 intel_connector->panel.fitting_mode);
811 else
b074cec8
JB		 812 intel_pch_panel_fitting(intel_crtc, pipe_config,
813 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 814 }
815
cb1793ce 816 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 817 return false;
818
083f9560
DV		 819 DRM_DEBUG_KMS("DP link computation with max lane count %i "
820 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 821 max_lane_count, bws[max_clock],
822 adjusted_mode->crtc_clock);
083f9560 823
36008365
DV		 824 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
825 * bpc in between. */
3e7ca985 826 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 827 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
828 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 829 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
830 dev_priv->vbt.edp_bpp);
6da7f10d 831 bpp = dev_priv->vbt.edp_bpp;
7984211e 832 }
657445fe 833
36008365 834 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 835 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
836 bpp);
36008365 837
38aecea0
DV		 838 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
839 for (clock = 0; clock <= max_clock; clock++) {
36008365
DV		 840 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
841 link_avail = intel_dp_max_data_rate(link_clock,
842 lane_count);
843
844 if (mode_rate <= link_avail) {
845 goto found;
846 }
847 }
848 }
849 }
c4867936 850
36008365 851 return false;
3685a8f3 852
36008365 853found:
55bc60db
VS		 854 if (intel_dp->color_range_auto) {
855 /*
856 * See:
857 * CEA-861-E - 5.1 Default Encoding Parameters
858 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
859 */
18316c8c 860 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 861 intel_dp->color_range = DP_COLOR_RANGE_16_235;
862 else
863 intel_dp->color_range = 0;
864 }
865
3685a8f3 866 if (intel_dp->color_range)
50f3b016 867 pipe_config->limited_color_range = true;
a4fc5ed6 868
36008365
DV		 869 intel_dp->link_bw = bws[clock];
870 intel_dp->lane_count = lane_count;
657445fe 871 pipe_config->pipe_bpp = bpp;
ff9a6750 872 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 873
36008365
DV		 874 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
875 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 876 pipe_config->port_clock, bpp);
36008365
DV		 877 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
878 mode_rate, link_avail);
a4fc5ed6 879
03afc4a2 880 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 881 adjusted_mode->crtc_clock,
882 pipe_config->port_clock,
03afc4a2 883 &pipe_config->dp_m_n);
9d1a455b 884
439d7ac0
PB		 885 if (intel_connector->panel.downclock_mode != NULL &&
886 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
887 intel_link_compute_m_n(bpp, lane_count,
888 intel_connector->panel.downclock_mode->clock,
889 pipe_config->port_clock,
890 &pipe_config->dp_m2_n2);
891 }
892
c6bb3538
DV		 893 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
894
03afc4a2 895 return true;
a4fc5ed6
KP		 896}
897
7c62a164 898static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 899{
7c62a164
DV		 900 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
901 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
902 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 903 struct drm_i915_private *dev_priv = dev->dev_private;
904 u32 dpa_ctl;
905
ff9a6750 906 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 907 dpa_ctl = I915_READ(DP_A);
908 dpa_ctl &= ~DP_PLL_FREQ_MASK;
909
ff9a6750 910 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 911 /* For a long time we've carried around a ILK-DevA w/a for the
912 * 160MHz clock. If we're really unlucky, it's still required.
913 */
914 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 915 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 916 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 917 } else {
918 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 919 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 920 }
1ce17038 921
ea9b6006
DV		 922 I915_WRITE(DP_A, dpa_ctl);
923
924 POSTING_READ(DP_A);
925 udelay(500);
926}
927
8ac33ed3 928static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 929{
b934223d 930 struct drm_device *dev = encoder->base.dev;
417e822d 931 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 932 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 933 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 934 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
935 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 936
417e822d 937 /*
1a2eb460 938 * There are four kinds of DP registers:
417e822d
KP		 939 *
940 * IBX PCH
1a2eb460
KP		 941 * SNB CPU
942 * IVB CPU
417e822d
KP		 943 * CPT PCH
944 *
945 * IBX PCH and CPU are the same for almost everything,
946 * except that the CPU DP PLL is configured in this
947 * register
948 *
949 * CPT PCH is quite different, having many bits moved
950 * to the TRANS_DP_CTL register instead. That
951 * configuration happens (oddly) in ironlake_pch_enable
952 */
9c9e7927 953
417e822d
KP		 954 /* Preserve the BIOS-computed detected bit. This is
955 * supposed to be read-only.
956 */
957 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 958
417e822d 959 /* Handle DP bits in common between all three register formats */
417e822d 960 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 961 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 962
9ed109a7 963 if (crtc->config.has_audio) {
e0dac65e 964 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 965 pipe_name(crtc->pipe));
ea5b213a 966 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 967 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 968 }
247d89f6 969
417e822d 970 /* Split out the IBX/CPU vs CPT settings */
32f9d658 971
bc7d38a4 972 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 973 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
974 intel_dp->DP |= DP_SYNC_HS_HIGH;
975 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
976 intel_dp->DP |= DP_SYNC_VS_HIGH;
977 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
978
6aba5b6c 979 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 980 intel_dp->DP |= DP_ENHANCED_FRAMING;
981
7c62a164 982 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 983 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 984 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 985 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 986
987 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
988 intel_dp->DP |= DP_SYNC_HS_HIGH;
989 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
990 intel_dp->DP |= DP_SYNC_VS_HIGH;
991 intel_dp->DP |= DP_LINK_TRAIN_OFF;
992
6aba5b6c 993 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 994 intel_dp->DP |= DP_ENHANCED_FRAMING;
995
44f37d1f
CML		 996 if (!IS_CHERRYVIEW(dev)) {
997 if (crtc->pipe == 1)
998 intel_dp->DP |= DP_PIPEB_SELECT;
999 } else {
1000 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1001 }
417e822d
KP		 1002 } else {
1003 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1004 }
a4fc5ed6
KP		 1005}
1006
ffd6749d
PZ		 1007#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1008#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1009
1a5ef5b7
PZ		 1010#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1011#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1012
ffd6749d
PZ		 1013#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1014#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1015
4be73780 1016static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1017 u32 mask,
1018 u32 value)
bd943159 1019{
30add22d 1020 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1021 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1022 u32 pp_stat_reg, pp_ctrl_reg;
1023
bf13e81b
JN		 1024 pp_stat_reg = _pp_stat_reg(intel_dp);
1025 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1026
99ea7127 1027 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1028 mask, value,
1029 I915_READ(pp_stat_reg),
1030 I915_READ(pp_ctrl_reg));
32ce697c 1031
453c5420 1032 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1033 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1034 I915_READ(pp_stat_reg),
1035 I915_READ(pp_ctrl_reg));
32ce697c 1036 }
54c136d4
CW		 1037
1038 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1039}
32ce697c 1040
4be73780 1041static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1042{
1043 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1044 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1045}
1046
4be73780 1047static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1048{
1049 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1050 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1051}
1052
4be73780 1053static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1054{
1055 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1056
1057 /* When we disable the VDD override bit last we have to do the manual
1058 * wait. */
1059 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1060 intel_dp->panel_power_cycle_delay);
1061
4be73780 1062 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1063}
1064
4be73780 1065static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1066{
1067 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1068 intel_dp->backlight_on_delay);
1069}
1070
4be73780 1071static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1072{
1073 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1074 intel_dp->backlight_off_delay);
1075}
99ea7127 1076
832dd3c1
KP		 1077/* Read the current pp_control value, unlocking the register if it
1078 * is locked
1079 */
1080
453c5420 1081static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1082{
453c5420
JB		 1083 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1084 struct drm_i915_private *dev_priv = dev->dev_private;
1085 u32 control;
832dd3c1 1086
bf13e81b 1087 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1088 control &= ~PANEL_UNLOCK_MASK;
1089 control |= PANEL_UNLOCK_REGS;
1090 return control;
bd943159
KP		 1091}
1092
adddaaf4 1093static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1094{
30add22d 1095 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1096 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1097 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1098 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1099 enum intel_display_power_domain power_domain;
5d613501 1100 u32 pp;
453c5420 1101 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1102 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1103
97af61f5 1104 if (!is_edp(intel_dp))
adddaaf4 1105 return false;
bd943159
KP		 1106
1107 intel_dp->want_panel_vdd = true;
99ea7127 1108
4be73780 1109 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1110 return need_to_disable;
b0665d57 1111
4e6e1a54
ID		 1112 power_domain = intel_display_port_power_domain(intel_encoder);
1113 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1114
b0665d57 1115 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1116
4be73780
DV		 1117 if (!edp_have_panel_power(intel_dp))
1118 wait_panel_power_cycle(intel_dp);
99ea7127 1119
453c5420 1120 pp = ironlake_get_pp_control(intel_dp);
5d613501 1121 pp |= EDP_FORCE_VDD;
ebf33b18 1122
bf13e81b
JN		 1123 pp_stat_reg = _pp_stat_reg(intel_dp);
1124 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1125
1126 I915_WRITE(pp_ctrl_reg, pp);
1127 POSTING_READ(pp_ctrl_reg);
1128 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1129 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1130 /*
1131 * If the panel wasn't on, delay before accessing aux channel
1132 */
4be73780 1133 if (!edp_have_panel_power(intel_dp)) {
bd943159 1134 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1135 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1136 }
adddaaf4
JN		 1137
1138 return need_to_disable;
1139}
1140
b80d6c78 1141void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1142{
1143 if (is_edp(intel_dp)) {
1144 bool vdd = _edp_panel_vdd_on(intel_dp);
1145
1146 WARN(!vdd, "eDP VDD already requested on\n");
1147 }
5d613501
JB		 1148}
1149
4be73780 1150static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1151{
30add22d 1152 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1153 struct drm_i915_private *dev_priv = dev->dev_private;
1154 u32 pp;
453c5420 1155 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1156
a0e99e68
DV		 1157 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1158
4be73780 1159 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1160 struct intel_digital_port *intel_dig_port =
1161 dp_to_dig_port(intel_dp);
1162 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1163 enum intel_display_power_domain power_domain;
1164
b0665d57
PZ		 1165 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1166
453c5420 1167 pp = ironlake_get_pp_control(intel_dp);
bd943159 1168 pp &= ~EDP_FORCE_VDD;
bd943159 1169
9f08ef59
PZ		 1170 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1171 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1172
1173 I915_WRITE(pp_ctrl_reg, pp);
1174 POSTING_READ(pp_ctrl_reg);
99ea7127 1175
453c5420
JB		 1176 /* Make sure sequencer is idle before allowing subsequent activity */
1177 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1178 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1179
1180 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1181 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1182
4e6e1a54
ID		 1183 power_domain = intel_display_port_power_domain(intel_encoder);
1184 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1185 }
1186}
5d613501 1187
4be73780 1188static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1189{
1190 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1191 struct intel_dp, panel_vdd_work);
30add22d 1192 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1193
627f7675 1194 mutex_lock(&dev->mode_config.mutex);
4be73780 1195 edp_panel_vdd_off_sync(intel_dp);
627f7675 1196 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1197}
1198
4be73780 1199static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1200{
97af61f5
KP		 1201 if (!is_edp(intel_dp))
1202 return;
5d613501 1203
bd943159 1204 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1205
bd943159
KP		 1206 intel_dp->want_panel_vdd = false;
1207
1208 if (sync) {
4be73780 1209 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1210 } else {
1211 /*
1212 * Queue the timer to fire a long
1213 * time from now (relative to the power down delay)
1214 * to keep the panel power up across a sequence of operations
1215 */
1216 schedule_delayed_work(&intel_dp->panel_vdd_work,
1217 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1218 }
5d613501
JB		 1219}
1220
4be73780 1221void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1222{
30add22d 1223 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1224 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1225 u32 pp;
453c5420 1226 u32 pp_ctrl_reg;
9934c132 1227
97af61f5 1228 if (!is_edp(intel_dp))
bd943159 1229 return;
99ea7127
KP		 1230
1231 DRM_DEBUG_KMS("Turn eDP power on\n");
1232
4be73780 1233 if (edp_have_panel_power(intel_dp)) {
99ea7127 1234 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1235 return;
99ea7127 1236 }
9934c132 1237
4be73780 1238 wait_panel_power_cycle(intel_dp);
37c6c9b0 1239
bf13e81b 1240 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1241 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1242 if (IS_GEN5(dev)) {
1243 /* ILK workaround: disable reset around power sequence */
1244 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1245 I915_WRITE(pp_ctrl_reg, pp);
1246 POSTING_READ(pp_ctrl_reg);
05ce1a49 1247 }
37c6c9b0 1248
1c0ae80a 1249 pp |= POWER_TARGET_ON;
99ea7127
KP		 1250 if (!IS_GEN5(dev))
1251 pp |= PANEL_POWER_RESET;
1252
453c5420
JB		 1253 I915_WRITE(pp_ctrl_reg, pp);
1254 POSTING_READ(pp_ctrl_reg);
9934c132 1255
4be73780 1256 wait_panel_on(intel_dp);
dce56b3c 1257 intel_dp->last_power_on = jiffies;
9934c132 1258
05ce1a49
KP		 1259 if (IS_GEN5(dev)) {
1260 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1261 I915_WRITE(pp_ctrl_reg, pp);
1262 POSTING_READ(pp_ctrl_reg);
05ce1a49 1263 }
9934c132
JB		 1264}
1265
4be73780 1266void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1267{
4e6e1a54
ID		 1268 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1269 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1270 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1271 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1272 enum intel_display_power_domain power_domain;
99ea7127 1273 u32 pp;
453c5420 1274 u32 pp_ctrl_reg;
9934c132 1275
97af61f5
KP		 1276 if (!is_edp(intel_dp))
1277 return;
37c6c9b0 1278
99ea7127 1279 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1280
4be73780 1281 edp_wait_backlight_off(intel_dp);
dce56b3c 1282
24f3e092
JN		 1283 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1284
453c5420 1285 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1286 /* We need to switch off panel power _and_ force vdd, for otherwise some
1287 * panels get very unhappy and cease to work. */
b3064154
PJ		 1288 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1289 EDP_BLC_ENABLE);
453c5420 1290
bf13e81b 1291 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1292
849e39f5
PZ		 1293 intel_dp->want_panel_vdd = false;
1294
453c5420
JB		 1295 I915_WRITE(pp_ctrl_reg, pp);
1296 POSTING_READ(pp_ctrl_reg);
9934c132 1297
dce56b3c 1298 intel_dp->last_power_cycle = jiffies;
4be73780 1299 wait_panel_off(intel_dp);
849e39f5
PZ		 1300
1301 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1302 power_domain = intel_display_port_power_domain(intel_encoder);
1303 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1304}
1305
4be73780 1306void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1307{
da63a9f2
PZ		 1308 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1309 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1310 struct drm_i915_private *dev_priv = dev->dev_private;
1311 u32 pp;
453c5420 1312 u32 pp_ctrl_reg;
32f9d658 1313
f01eca2e
KP		 1314 if (!is_edp(intel_dp))
1315 return;
1316
28c97730 1317 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1318 /*
1319 * If we enable the backlight right away following a panel power
1320 * on, we may see slight flicker as the panel syncs with the eDP
1321 * link. So delay a bit to make sure the image is solid before
1322 * allowing it to appear.
1323 */
4be73780 1324 wait_backlight_on(intel_dp);
453c5420 1325 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1326 pp |= EDP_BLC_ENABLE;
453c5420 1327
bf13e81b 1328 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1329
1330 I915_WRITE(pp_ctrl_reg, pp);
1331 POSTING_READ(pp_ctrl_reg);
035aa3de 1332
752aa88a 1333 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1334}
1335
4be73780 1336void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1337{
30add22d 1338 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1339 struct drm_i915_private *dev_priv = dev->dev_private;
1340 u32 pp;
453c5420 1341 u32 pp_ctrl_reg;
32f9d658 1342
f01eca2e
KP		 1343 if (!is_edp(intel_dp))
1344 return;
1345
752aa88a 1346 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1347
28c97730 1348 DRM_DEBUG_KMS("\n");
453c5420 1349 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1350 pp &= ~EDP_BLC_ENABLE;
453c5420 1351
bf13e81b 1352 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1353
1354 I915_WRITE(pp_ctrl_reg, pp);
1355 POSTING_READ(pp_ctrl_reg);
dce56b3c 1356 intel_dp->last_backlight_off = jiffies;
32f9d658 1357}
a4fc5ed6 1358
2bd2ad64 1359static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1360{
da63a9f2
PZ		 1361 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1362 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1363 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1364 struct drm_i915_private *dev_priv = dev->dev_private;
1365 u32 dpa_ctl;
1366
2bd2ad64
DV		 1367 assert_pipe_disabled(dev_priv,
1368 to_intel_crtc(crtc)->pipe);
1369
d240f20f
JB		 1370 DRM_DEBUG_KMS("\n");
1371 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1372 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1373 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1374
1375 /* We don't adjust intel_dp->DP while tearing down the link, to
1376 * facilitate link retraining (e.g. after hotplug). Hence clear all
1377 * enable bits here to ensure that we don't enable too much. */
1378 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1379 intel_dp->DP |= DP_PLL_ENABLE;
1380 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1381 POSTING_READ(DP_A);
1382 udelay(200);
d240f20f
JB		 1383}
1384
2bd2ad64 1385static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1386{
da63a9f2
PZ		 1387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1388 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1389 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1390 struct drm_i915_private *dev_priv = dev->dev_private;
1391 u32 dpa_ctl;
1392
2bd2ad64
DV		 1393 assert_pipe_disabled(dev_priv,
1394 to_intel_crtc(crtc)->pipe);
1395
d240f20f 1396 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1397 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1398 "dp pll off, should be on\n");
1399 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1400
1401 /* We can't rely on the value tracked for the DP register in
1402 * intel_dp->DP because link_down must not change that (otherwise link
1403 * re-training will fail. */
298b0b39 1404 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1405 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1406 POSTING_READ(DP_A);
d240f20f
JB		 1407 udelay(200);
1408}
1409
c7ad3810 1410/* If the sink supports it, try to set the power state appropriately */
c19b0669 1411void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1412{
1413 int ret, i;
1414
1415 /* Should have a valid DPCD by this point */
1416 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1417 return;
1418
1419 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1420 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1421 DP_SET_POWER_D3);
c7ad3810
JB		 1422 if (ret != 1)
1423 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1424 } else {
1425 /*
1426 * When turning on, we need to retry for 1ms to give the sink
1427 * time to wake up.
1428 */
1429 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1430 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1431 DP_SET_POWER_D0);
c7ad3810
JB		 1432 if (ret == 1)
1433 break;
1434 msleep(1);
1435 }
1436 }
1437}
1438
19d8fe15
DV		 1439static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1440 enum pipe *pipe)
d240f20f 1441{
19d8fe15 1442 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1443 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1444 struct drm_device *dev = encoder->base.dev;
1445 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1446 enum intel_display_power_domain power_domain;
1447 u32 tmp;
1448
1449 power_domain = intel_display_port_power_domain(encoder);
1450 if (!intel_display_power_enabled(dev_priv, power_domain))
1451 return false;
1452
1453 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1454
1455 if (!(tmp & DP_PORT_EN))
1456 return false;
1457
bc7d38a4 1458 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1459 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1460 } else if (IS_CHERRYVIEW(dev)) {
1461 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1462 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1463 *pipe = PORT_TO_PIPE(tmp);
1464 } else {
1465 u32 trans_sel;
1466 u32 trans_dp;
1467 int i;
1468
1469 switch (intel_dp->output_reg) {
1470 case PCH_DP_B:
1471 trans_sel = TRANS_DP_PORT_SEL_B;
1472 break;
1473 case PCH_DP_C:
1474 trans_sel = TRANS_DP_PORT_SEL_C;
1475 break;
1476 case PCH_DP_D:
1477 trans_sel = TRANS_DP_PORT_SEL_D;
1478 break;
1479 default:
1480 return true;
1481 }
1482
1483 for_each_pipe(i) {
1484 trans_dp = I915_READ(TRANS_DP_CTL(i));
1485 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1486 *pipe = i;
1487 return true;
1488 }
1489 }
19d8fe15 1490
4a0833ec
DV		 1491 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1492 intel_dp->output_reg);
1493 }
d240f20f 1494
19d8fe15
DV		 1495 return true;
1496}
d240f20f 1497
045ac3b5
JB		 1498static void intel_dp_get_config(struct intel_encoder *encoder,
1499 struct intel_crtc_config *pipe_config)
1500{
1501 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1502 u32 tmp, flags = 0;
63000ef6
XZ		 1503 struct drm_device *dev = encoder->base.dev;
1504 struct drm_i915_private *dev_priv = dev->dev_private;
1505 enum port port = dp_to_dig_port(intel_dp)->port;
1506 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1507 int dotclock;
045ac3b5 1508
9ed109a7
DV		 1509 tmp = I915_READ(intel_dp->output_reg);
1510 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1511 pipe_config->has_audio = true;
1512
63000ef6 1513 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1514 if (tmp & DP_SYNC_HS_HIGH)
1515 flags |= DRM_MODE_FLAG_PHSYNC;
1516 else
1517 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1518
63000ef6
XZ		 1519 if (tmp & DP_SYNC_VS_HIGH)
1520 flags |= DRM_MODE_FLAG_PVSYNC;
1521 else
1522 flags |= DRM_MODE_FLAG_NVSYNC;
1523 } else {
1524 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1525 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1526 flags |= DRM_MODE_FLAG_PHSYNC;
1527 else
1528 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1529
63000ef6
XZ		 1530 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1531 flags |= DRM_MODE_FLAG_PVSYNC;
1532 else
1533 flags |= DRM_MODE_FLAG_NVSYNC;
1534 }
045ac3b5
JB		 1535
1536 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1537
eb14cb74
VS		 1538 pipe_config->has_dp_encoder = true;
1539
1540 intel_dp_get_m_n(crtc, pipe_config);
1541
18442d08 1542 if (port == PORT_A) {
f1f644dc
JB		 1543 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1544 pipe_config->port_clock = 162000;
1545 else
1546 pipe_config->port_clock = 270000;
1547 }
18442d08
VS		 1548
1549 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1550 &pipe_config->dp_m_n);
1551
1552 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1553 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1554
241bfc38 1555 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1556
c6cd2ee2
JN		 1557 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1558 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1559 /*
1560 * This is a big fat ugly hack.
1561 *
1562 * Some machines in UEFI boot mode provide us a VBT that has 18
1563 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1564 * unknown we fail to light up. Yet the same BIOS boots up with
1565 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1566 * max, not what it tells us to use.
1567 *
1568 * Note: This will still be broken if the eDP panel is not lit
1569 * up by the BIOS, and thus we can't get the mode at module
1570 * load.
1571 */
1572 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1573 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1574 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1575 }
045ac3b5
JB		 1576}
1577
a031d709 1578static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1579{
a031d709
RV		 1580 struct drm_i915_private *dev_priv = dev->dev_private;
1581
1582 return dev_priv->psr.sink_support;
2293bb5c
SK		 1583}
1584
2b28bb1b
RV		 1585static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1586{
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588
18b5992c 1589 if (!HAS_PSR(dev))
2b28bb1b
RV		 1590 return false;
1591
18b5992c 1592 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1593}
1594
1595static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1596 struct edp_vsc_psr *vsc_psr)
1597{
1598 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1599 struct drm_device *dev = dig_port->base.base.dev;
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1602 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1603 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1604 uint32_t *data = (uint32_t *) vsc_psr;
1605 unsigned int i;
1606
1607 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1608 the video DIP being updated before program video DIP data buffer
1609 registers for DIP being updated. */
1610 I915_WRITE(ctl_reg, 0);
1611 POSTING_READ(ctl_reg);
1612
1613 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1614 if (i < sizeof(struct edp_vsc_psr))
1615 I915_WRITE(data_reg + i, *data++);
1616 else
1617 I915_WRITE(data_reg + i, 0);
1618 }
1619
1620 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1621 POSTING_READ(ctl_reg);
1622}
1623
1624static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1625{
1626 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1627 struct drm_i915_private *dev_priv = dev->dev_private;
1628 struct edp_vsc_psr psr_vsc;
1629
1630 if (intel_dp->psr_setup_done)
1631 return;
1632
1633 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1634 memset(&psr_vsc, 0, sizeof(psr_vsc));
1635 psr_vsc.sdp_header.HB0 = 0;
1636 psr_vsc.sdp_header.HB1 = 0x7;
1637 psr_vsc.sdp_header.HB2 = 0x2;
1638 psr_vsc.sdp_header.HB3 = 0x8;
1639 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1640
1641 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1642 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1643 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1644
1645 intel_dp->psr_setup_done = true;
1646}
1647
1648static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1649{
1650 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1651 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1652 uint32_t aux_clock_divider;
2b28bb1b
RV		 1653 int precharge = 0x3;
1654 int msg_size = 5; /* Header(4) + Message(1) */
1655
ec5b01dd
DL		 1656 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1657
2b28bb1b
RV		 1658 /* Enable PSR in sink */
1659 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
9d1a1031
JN		 1660 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1661 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1662 else
9d1a1031
JN		 1663 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1664 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1665
1666 /* Setup AUX registers */
18b5992c
BW		 1667 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1668 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1669 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1670 DP_AUX_CH_CTL_TIME_OUT_400us |
1671 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1672 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1673 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1674}
1675
1676static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1677{
1678 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1679 struct drm_i915_private *dev_priv = dev->dev_private;
1680 uint32_t max_sleep_time = 0x1f;
1681 uint32_t idle_frames = 1;
1682 uint32_t val = 0x0;
ed8546ac 1683 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1684
1685 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1686 val |= EDP_PSR_LINK_STANDBY;
1687 val |= EDP_PSR_TP2_TP3_TIME_0us;
1688 val |= EDP_PSR_TP1_TIME_0us;
1689 val |= EDP_PSR_SKIP_AUX_EXIT;
1690 } else
1691 val |= EDP_PSR_LINK_DISABLE;
1692
18b5992c 1693 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1694 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1695 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1696 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1697 EDP_PSR_ENABLE);
1698}
1699
3f51e471
RV		 1700static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1701{
1702 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1703 struct drm_device *dev = dig_port->base.base.dev;
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1705 struct drm_crtc *crtc = dig_port->base.base.crtc;
1706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f4510a27 1707 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1708 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1709
a031d709
RV		 1710 dev_priv->psr.source_ok = false;
1711
18b5992c 1712 if (!HAS_PSR(dev)) {
3f51e471 1713 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1714 return false;
1715 }
1716
1717 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1718 (dig_port->port != PORT_A)) {
1719 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1720 return false;
1721 }
1722
d330a953 1723 if (!i915.enable_psr) {
105b7c11 1724 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1725 return false;
1726 }
1727
cd234b0b
CW		 1728 crtc = dig_port->base.base.crtc;
1729 if (crtc == NULL) {
1730 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1731 return false;
1732 }
1733
1734 intel_crtc = to_intel_crtc(crtc);
20ddf665 1735 if (!intel_crtc_active(crtc)) {
3f51e471 1736 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1737 return false;
1738 }
1739
f4510a27 1740 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1741 if (obj->tiling_mode != I915_TILING_X ||
1742 obj->fence_reg == I915_FENCE_REG_NONE) {
1743 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1744 return false;
1745 }
1746
1747 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1748 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1749 return false;
1750 }
1751
1752 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1753 S3D_ENABLE) {
1754 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1755 return false;
1756 }
1757
ca73b4f0 1758 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1759 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1760 return false;
1761 }
1762
a031d709 1763 dev_priv->psr.source_ok = true;
3f51e471
RV		 1764 return true;
1765}
1766
3d739d92 1767static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1768{
1769 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1770
3f51e471
RV		 1771 if (!intel_edp_psr_match_conditions(intel_dp) ||
1772 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1773 return;
1774
1775 /* Setup PSR once */
1776 intel_edp_psr_setup(intel_dp);
1777
1778 /* Enable PSR on the panel */
1779 intel_edp_psr_enable_sink(intel_dp);
1780
1781 /* Enable PSR on the host */
1782 intel_edp_psr_enable_source(intel_dp);
1783}
1784
3d739d92
RV		 1785void intel_edp_psr_enable(struct intel_dp *intel_dp)
1786{
1787 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1788
1789 if (intel_edp_psr_match_conditions(intel_dp) &&
1790 !intel_edp_is_psr_enabled(dev))
1791 intel_edp_psr_do_enable(intel_dp);
1792}
1793
2b28bb1b
RV		 1794void intel_edp_psr_disable(struct intel_dp *intel_dp)
1795{
1796 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1797 struct drm_i915_private *dev_priv = dev->dev_private;
1798
1799 if (!intel_edp_is_psr_enabled(dev))
1800 return;
1801
18b5992c
BW		 1802 I915_WRITE(EDP_PSR_CTL(dev),
1803 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1804
1805 /* Wait till PSR is idle */
18b5992c 1806 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1807 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1808 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1809}
1810
3d739d92
RV		 1811void intel_edp_psr_update(struct drm_device *dev)
1812{
1813 struct intel_encoder *encoder;
1814 struct intel_dp *intel_dp = NULL;
1815
1816 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1817 if (encoder->type == INTEL_OUTPUT_EDP) {
1818 intel_dp = enc_to_intel_dp(&encoder->base);
1819
a031d709 1820 if (!is_edp_psr(dev))
3d739d92
RV		 1821 return;
1822
1823 if (!intel_edp_psr_match_conditions(intel_dp))
1824 intel_edp_psr_disable(intel_dp);
1825 else
1826 if (!intel_edp_is_psr_enabled(dev))
1827 intel_edp_psr_do_enable(intel_dp);
1828 }
1829}
1830
e8cb4558 1831static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1832{
e8cb4558 1833 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1834 enum port port = dp_to_dig_port(intel_dp)->port;
1835 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1836
1837 /* Make sure the panel is off before trying to change the mode. But also
1838 * ensure that we have vdd while we switch off the panel. */
24f3e092 1839 intel_edp_panel_vdd_on(intel_dp);
4be73780 1840 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1841 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1842 intel_edp_panel_off(intel_dp);
3739850b
DV		 1843
1844 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1845 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1846 intel_dp_link_down(intel_dp);
d240f20f
JB		 1847}
1848
49277c31 1849static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1850{
2bd2ad64 1851 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1852 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 1853
49277c31
VS		 1854 if (port != PORT_A)
1855 return;
1856
1857 intel_dp_link_down(intel_dp);
1858 ironlake_edp_pll_off(intel_dp);
1859}
1860
1861static void vlv_post_disable_dp(struct intel_encoder *encoder)
1862{
1863 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1864
1865 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 1866}
1867
580d3811
VS		 1868static void chv_post_disable_dp(struct intel_encoder *encoder)
1869{
1870 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1871 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1872 struct drm_device *dev = encoder->base.dev;
1873 struct drm_i915_private *dev_priv = dev->dev_private;
1874 struct intel_crtc *intel_crtc =
1875 to_intel_crtc(encoder->base.crtc);
1876 enum dpio_channel ch = vlv_dport_to_channel(dport);
1877 enum pipe pipe = intel_crtc->pipe;
1878 u32 val;
1879
1880 intel_dp_link_down(intel_dp);
1881
1882 mutex_lock(&dev_priv->dpio_lock);
1883
1884 /* Propagate soft reset to data lane reset */
d2152b25
VS		 1885 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
1886 val |= CHV_PCS_REQ_SOFTRESET_EN;
1887 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
1888
580d3811
VS		 1889 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
1890 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1891 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
1892
1893 mutex_unlock(&dev_priv->dpio_lock);
1894}
1895
e8cb4558 1896static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1897{
e8cb4558
DV		 1898 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1899 struct drm_device *dev = encoder->base.dev;
1900 struct drm_i915_private *dev_priv = dev->dev_private;
1901 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1902
0c33d8d7
DV		 1903 if (WARN_ON(dp_reg & DP_PORT_EN))
1904 return;
5d613501 1905
24f3e092 1906 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 1907 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1908 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1909 intel_edp_panel_on(intel_dp);
1910 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1911 intel_dp_complete_link_train(intel_dp);
3ab9c637 1912 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1913}
89b667f8 1914
ecff4f3b
JN		 1915static void g4x_enable_dp(struct intel_encoder *encoder)
1916{
828f5c6e
JN		 1917 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1918
ecff4f3b 1919 intel_enable_dp(encoder);
4be73780 1920 intel_edp_backlight_on(intel_dp);
ab1f90f9 1921}
89b667f8 1922
ab1f90f9
JN		 1923static void vlv_enable_dp(struct intel_encoder *encoder)
1924{
828f5c6e
JN		 1925 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1926
4be73780 1927 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1928}
1929
ecff4f3b 1930static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1931{
1932 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1933 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1934
8ac33ed3
DV		 1935 intel_dp_prepare(encoder);
1936
d41f1efb
DV		 1937 /* Only ilk+ has port A */
1938 if (dport->port == PORT_A) {
1939 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 1940 ironlake_edp_pll_on(intel_dp);
d41f1efb 1941 }
ab1f90f9
JN		 1942}
1943
1944static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1945{
2bd2ad64 1946 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1947 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1948 struct drm_device *dev = encoder->base.dev;
89b667f8 1949 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1950 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1951 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1952 int pipe = intel_crtc->pipe;
bf13e81b 1953 struct edp_power_seq power_seq;
ab1f90f9 1954 u32 val;
a4fc5ed6 1955
ab1f90f9 1956 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1957
ab3c759a 1958 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1959 val = 0;
1960 if (pipe)
1961 val |= (1<<21);
1962 else
1963 val &= ~(1<<21);
1964 val |= 0x001000c4;
ab3c759a
CML		 1965 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1966 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1967 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1968
ab1f90f9
JN		 1969 mutex_unlock(&dev_priv->dpio_lock);
1970
2cac613b
ID		 1971 if (is_edp(intel_dp)) {
1972 /* init power sequencer on this pipe and port */
1973 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1974 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1975 &power_seq);
1976 }
bf13e81b 1977
ab1f90f9
JN		 1978 intel_enable_dp(encoder);
1979
e4607fcf 1980 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1981}
1982
ecff4f3b 1983static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1984{
1985 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1986 struct drm_device *dev = encoder->base.dev;
1987 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1988 struct intel_crtc *intel_crtc =
1989 to_intel_crtc(encoder->base.crtc);
e4607fcf 1990 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1991 int pipe = intel_crtc->pipe;
89b667f8 1992
8ac33ed3
DV		 1993 intel_dp_prepare(encoder);
1994
89b667f8 1995 /* Program Tx lane resets to default */
0980a60f 1996 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 1997 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1998 DPIO_PCS_TX_LANE2_RESET |
1999 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2000 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2001 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2002 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2003 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2004 DPIO_PCS_CLK_SOFT_RESET);
2005
2006 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2007 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2008 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2009 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2010 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2011}
2012
e4a1d846
CML		 2013static void chv_pre_enable_dp(struct intel_encoder *encoder)
2014{
2015 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2016 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2017 struct drm_device *dev = encoder->base.dev;
2018 struct drm_i915_private *dev_priv = dev->dev_private;
2019 struct edp_power_seq power_seq;
2020 struct intel_crtc *intel_crtc =
2021 to_intel_crtc(encoder->base.crtc);
2022 enum dpio_channel ch = vlv_dport_to_channel(dport);
2023 int pipe = intel_crtc->pipe;
2024 int data, i;
949c1d43 2025 u32 val;
e4a1d846 2026
e4a1d846 2027 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2028
2029 /* Deassert soft data lane reset*/
d2152b25
VS		 2030 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW1(ch));
2031 val |= CHV_PCS_REQ_SOFTRESET_EN;
2032 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(ch), val);
2033
949c1d43
VS		 2034 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
2035 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2036 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
2037
2038 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2039 for (i = 0; i < 4; i++) {
2040 /* Set the latency optimal bit */
2041 data = (i == 1) ? 0x0 : 0x6;
2042 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2043 data << DPIO_FRC_LATENCY_SHFIT);
2044
2045 /* Set the upar bit */
2046 data = (i == 1) ? 0x0 : 0x1;
2047 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2048 data << DPIO_UPAR_SHIFT);
2049 }
2050
2051 /* Data lane stagger programming */
2052 /* FIXME: Fix up value only after power analysis */
2053
2054 mutex_unlock(&dev_priv->dpio_lock);
2055
2056 if (is_edp(intel_dp)) {
2057 /* init power sequencer on this pipe and port */
2058 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2059 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2060 &power_seq);
2061 }
2062
2063 intel_enable_dp(encoder);
2064
2065 vlv_wait_port_ready(dev_priv, dport);
2066}
2067
a4fc5ed6 2068/*
df0c237d
JB		 2069 * Native read with retry for link status and receiver capability reads for
2070 * cases where the sink may still be asleep.
9d1a1031
JN		 2071 *
2072 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2073 * supposed to retry 3 times per the spec.
a4fc5ed6 2074 */
9d1a1031
JN		 2075static ssize_t
2076intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2077 void *buffer, size_t size)
a4fc5ed6 2078{
9d1a1031
JN		 2079 ssize_t ret;
2080 int i;
61da5fab 2081
61da5fab 2082 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2083 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2084 if (ret == size)
2085 return ret;
61da5fab
JB		 2086 msleep(1);
2087 }
a4fc5ed6 2088
9d1a1031 2089 return ret;
a4fc5ed6
KP		 2090}
2091
2092/*
2093 * Fetch AUX CH registers 0x202 - 0x207 which contain
2094 * link status information
2095 */
2096static bool
93f62dad 2097intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2098{
9d1a1031
JN		 2099 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2100 DP_LANE0_1_STATUS,
2101 link_status,
2102 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2103}
2104
a4fc5ed6
KP		 2105/*
2106 * These are source-specific values; current Intel hardware supports
2107 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2108 */
a4fc5ed6
KP		 2109
2110static uint8_t
1a2eb460 2111intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2112{
30add22d 2113 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2114 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2115
8f93f4f1 2116 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 2117 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2118 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2119 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2120 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2121 return DP_TRAIN_VOLTAGE_SWING_1200;
2122 else
2123 return DP_TRAIN_VOLTAGE_SWING_800;
2124}
2125
2126static uint8_t
2127intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2128{
30add22d 2129 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2130 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2131
8f93f4f1
PZ		 2132 if (IS_BROADWELL(dev)) {
2133 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2134 case DP_TRAIN_VOLTAGE_SWING_400:
2135 case DP_TRAIN_VOLTAGE_SWING_600:
2136 return DP_TRAIN_PRE_EMPHASIS_6;
2137 case DP_TRAIN_VOLTAGE_SWING_800:
2138 return DP_TRAIN_PRE_EMPHASIS_3_5;
2139 case DP_TRAIN_VOLTAGE_SWING_1200:
2140 default:
2141 return DP_TRAIN_PRE_EMPHASIS_0;
2142 }
2143 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2144 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2145 case DP_TRAIN_VOLTAGE_SWING_400:
2146 return DP_TRAIN_PRE_EMPHASIS_9_5;
2147 case DP_TRAIN_VOLTAGE_SWING_600:
2148 return DP_TRAIN_PRE_EMPHASIS_6;
2149 case DP_TRAIN_VOLTAGE_SWING_800:
2150 return DP_TRAIN_PRE_EMPHASIS_3_5;
2151 case DP_TRAIN_VOLTAGE_SWING_1200:
2152 default:
2153 return DP_TRAIN_PRE_EMPHASIS_0;
2154 }
e2fa6fba
P		 2155 } else if (IS_VALLEYVIEW(dev)) {
2156 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2157 case DP_TRAIN_VOLTAGE_SWING_400:
2158 return DP_TRAIN_PRE_EMPHASIS_9_5;
2159 case DP_TRAIN_VOLTAGE_SWING_600:
2160 return DP_TRAIN_PRE_EMPHASIS_6;
2161 case DP_TRAIN_VOLTAGE_SWING_800:
2162 return DP_TRAIN_PRE_EMPHASIS_3_5;
2163 case DP_TRAIN_VOLTAGE_SWING_1200:
2164 default:
2165 return DP_TRAIN_PRE_EMPHASIS_0;
2166 }
bc7d38a4 2167 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2168 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2169 case DP_TRAIN_VOLTAGE_SWING_400:
2170 return DP_TRAIN_PRE_EMPHASIS_6;
2171 case DP_TRAIN_VOLTAGE_SWING_600:
2172 case DP_TRAIN_VOLTAGE_SWING_800:
2173 return DP_TRAIN_PRE_EMPHASIS_3_5;
2174 default:
2175 return DP_TRAIN_PRE_EMPHASIS_0;
2176 }
2177 } else {
2178 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2179 case DP_TRAIN_VOLTAGE_SWING_400:
2180 return DP_TRAIN_PRE_EMPHASIS_6;
2181 case DP_TRAIN_VOLTAGE_SWING_600:
2182 return DP_TRAIN_PRE_EMPHASIS_6;
2183 case DP_TRAIN_VOLTAGE_SWING_800:
2184 return DP_TRAIN_PRE_EMPHASIS_3_5;
2185 case DP_TRAIN_VOLTAGE_SWING_1200:
2186 default:
2187 return DP_TRAIN_PRE_EMPHASIS_0;
2188 }
a4fc5ed6
KP		 2189 }
2190}
2191
e2fa6fba
P		 2192static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2193{
2194 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2195 struct drm_i915_private *dev_priv = dev->dev_private;
2196 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2197 struct intel_crtc *intel_crtc =
2198 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2199 unsigned long demph_reg_value, preemph_reg_value,
2200 uniqtranscale_reg_value;
2201 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2202 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2203 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2204
2205 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2206 case DP_TRAIN_PRE_EMPHASIS_0:
2207 preemph_reg_value = 0x0004000;
2208 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2209 case DP_TRAIN_VOLTAGE_SWING_400:
2210 demph_reg_value = 0x2B405555;
2211 uniqtranscale_reg_value = 0x552AB83A;
2212 break;
2213 case DP_TRAIN_VOLTAGE_SWING_600:
2214 demph_reg_value = 0x2B404040;
2215 uniqtranscale_reg_value = 0x5548B83A;
2216 break;
2217 case DP_TRAIN_VOLTAGE_SWING_800:
2218 demph_reg_value = 0x2B245555;
2219 uniqtranscale_reg_value = 0x5560B83A;
2220 break;
2221 case DP_TRAIN_VOLTAGE_SWING_1200:
2222 demph_reg_value = 0x2B405555;
2223 uniqtranscale_reg_value = 0x5598DA3A;
2224 break;
2225 default:
2226 return 0;
2227 }
2228 break;
2229 case DP_TRAIN_PRE_EMPHASIS_3_5:
2230 preemph_reg_value = 0x0002000;
2231 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2232 case DP_TRAIN_VOLTAGE_SWING_400:
2233 demph_reg_value = 0x2B404040;
2234 uniqtranscale_reg_value = 0x5552B83A;
2235 break;
2236 case DP_TRAIN_VOLTAGE_SWING_600:
2237 demph_reg_value = 0x2B404848;
2238 uniqtranscale_reg_value = 0x5580B83A;
2239 break;
2240 case DP_TRAIN_VOLTAGE_SWING_800:
2241 demph_reg_value = 0x2B404040;
2242 uniqtranscale_reg_value = 0x55ADDA3A;
2243 break;
2244 default:
2245 return 0;
2246 }
2247 break;
2248 case DP_TRAIN_PRE_EMPHASIS_6:
2249 preemph_reg_value = 0x0000000;
2250 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2251 case DP_TRAIN_VOLTAGE_SWING_400:
2252 demph_reg_value = 0x2B305555;
2253 uniqtranscale_reg_value = 0x5570B83A;
2254 break;
2255 case DP_TRAIN_VOLTAGE_SWING_600:
2256 demph_reg_value = 0x2B2B4040;
2257 uniqtranscale_reg_value = 0x55ADDA3A;
2258 break;
2259 default:
2260 return 0;
2261 }
2262 break;
2263 case DP_TRAIN_PRE_EMPHASIS_9_5:
2264 preemph_reg_value = 0x0006000;
2265 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2266 case DP_TRAIN_VOLTAGE_SWING_400:
2267 demph_reg_value = 0x1B405555;
2268 uniqtranscale_reg_value = 0x55ADDA3A;
2269 break;
2270 default:
2271 return 0;
2272 }
2273 break;
2274 default:
2275 return 0;
2276 }
2277
0980a60f 2278 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2279 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2280 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2281 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2282 uniqtranscale_reg_value);
ab3c759a
CML		 2283 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2284 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2285 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2286 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2287 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2288
2289 return 0;
2290}
2291
e4a1d846
CML		 2292static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2293{
2294 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2295 struct drm_i915_private *dev_priv = dev->dev_private;
2296 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2297 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2298 u32 deemph_reg_value, margin_reg_value, val, tx_dw2;
2299 uint8_t train_set = intel_dp->train_set[0];
2300 enum dpio_channel ch = vlv_dport_to_channel(dport);
2301 int pipe = intel_crtc->pipe;
2302
2303 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2304 case DP_TRAIN_PRE_EMPHASIS_0:
2305 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2306 case DP_TRAIN_VOLTAGE_SWING_400:
2307 deemph_reg_value = 128;
2308 margin_reg_value = 52;
2309 break;
2310 case DP_TRAIN_VOLTAGE_SWING_600:
2311 deemph_reg_value = 128;
2312 margin_reg_value = 77;
2313 break;
2314 case DP_TRAIN_VOLTAGE_SWING_800:
2315 deemph_reg_value = 128;
2316 margin_reg_value = 102;
2317 break;
2318 case DP_TRAIN_VOLTAGE_SWING_1200:
2319 deemph_reg_value = 128;
2320 margin_reg_value = 154;
2321 /* FIXME extra to set for 1200 */
2322 break;
2323 default:
2324 return 0;
2325 }
2326 break;
2327 case DP_TRAIN_PRE_EMPHASIS_3_5:
2328 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2329 case DP_TRAIN_VOLTAGE_SWING_400:
2330 deemph_reg_value = 85;
2331 margin_reg_value = 78;
2332 break;
2333 case DP_TRAIN_VOLTAGE_SWING_600:
2334 deemph_reg_value = 85;
2335 margin_reg_value = 116;
2336 break;
2337 case DP_TRAIN_VOLTAGE_SWING_800:
2338 deemph_reg_value = 85;
2339 margin_reg_value = 154;
2340 break;
2341 default:
2342 return 0;
2343 }
2344 break;
2345 case DP_TRAIN_PRE_EMPHASIS_6:
2346 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2347 case DP_TRAIN_VOLTAGE_SWING_400:
2348 deemph_reg_value = 64;
2349 margin_reg_value = 104;
2350 break;
2351 case DP_TRAIN_VOLTAGE_SWING_600:
2352 deemph_reg_value = 64;
2353 margin_reg_value = 154;
2354 break;
2355 default:
2356 return 0;
2357 }
2358 break;
2359 case DP_TRAIN_PRE_EMPHASIS_9_5:
2360 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2361 case DP_TRAIN_VOLTAGE_SWING_400:
2362 deemph_reg_value = 43;
2363 margin_reg_value = 154;
2364 break;
2365 default:
2366 return 0;
2367 }
2368 break;
2369 default:
2370 return 0;
2371 }
2372
2373 mutex_lock(&dev_priv->dpio_lock);
2374
2375 /* Clear calc init */
2376 vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
2377
2378 /* Program swing deemph */
2379 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch));
2380 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2381 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2382 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val);
2383
2384 /* Program swing margin */
2385 tx_dw2 = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch));
2386 tx_dw2 &= ~DPIO_SWING_MARGIN_MASK;
2387 tx_dw2 |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2388 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
2389
2390 /* Disable unique transition scale */
2391 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
2392 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2393 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
2394
2395 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2396 == DP_TRAIN_PRE_EMPHASIS_0) &&
2397 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2398 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2399
2400 /*
2401 * The document said it needs to set bit 27 for ch0 and bit 26
2402 * for ch1. Might be a typo in the doc.
2403 * For now, for this unique transition scale selection, set bit
2404 * 27 for ch0 and ch1.
2405 */
2406 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
2407 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2408 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
2409
2410 tx_dw2 |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2411 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
2412 }
2413
2414 /* Start swing calculation */
2415 vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
2416 (DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3));
2417
2418 /* LRC Bypass */
2419 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2420 val |= DPIO_LRC_BYPASS;
2421 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2422
2423 mutex_unlock(&dev_priv->dpio_lock);
2424
2425 return 0;
2426}
2427
a4fc5ed6 2428static void
0301b3ac
JN		 2429intel_get_adjust_train(struct intel_dp *intel_dp,
2430 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2431{
2432 uint8_t v = 0;
2433 uint8_t p = 0;
2434 int lane;
1a2eb460
KP		 2435 uint8_t voltage_max;
2436 uint8_t preemph_max;
a4fc5ed6 2437
33a34e4e 2438 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2439 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2440 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2441
2442 if (this_v > v)
2443 v = this_v;
2444 if (this_p > p)
2445 p = this_p;
2446 }
2447
1a2eb460 2448 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2449 if (v >= voltage_max)
2450 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2451
1a2eb460
KP		 2452 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2453 if (p >= preemph_max)
2454 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2455
2456 for (lane = 0; lane < 4; lane++)
33a34e4e 2457 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2458}
2459
2460static uint32_t
f0a3424e 2461intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2462{
3cf2efb1 2463 uint32_t signal_levels = 0;
a4fc5ed6 2464
3cf2efb1 2465 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2466 case DP_TRAIN_VOLTAGE_SWING_400:
2467 default:
2468 signal_levels |= DP_VOLTAGE_0_4;
2469 break;
2470 case DP_TRAIN_VOLTAGE_SWING_600:
2471 signal_levels |= DP_VOLTAGE_0_6;
2472 break;
2473 case DP_TRAIN_VOLTAGE_SWING_800:
2474 signal_levels |= DP_VOLTAGE_0_8;
2475 break;
2476 case DP_TRAIN_VOLTAGE_SWING_1200:
2477 signal_levels |= DP_VOLTAGE_1_2;
2478 break;
2479 }
3cf2efb1 2480 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2481 case DP_TRAIN_PRE_EMPHASIS_0:
2482 default:
2483 signal_levels |= DP_PRE_EMPHASIS_0;
2484 break;
2485 case DP_TRAIN_PRE_EMPHASIS_3_5:
2486 signal_levels |= DP_PRE_EMPHASIS_3_5;
2487 break;
2488 case DP_TRAIN_PRE_EMPHASIS_6:
2489 signal_levels |= DP_PRE_EMPHASIS_6;
2490 break;
2491 case DP_TRAIN_PRE_EMPHASIS_9_5:
2492 signal_levels |= DP_PRE_EMPHASIS_9_5;
2493 break;
2494 }
2495 return signal_levels;
2496}
2497
e3421a18
ZW		 2498/* Gen6's DP voltage swing and pre-emphasis control */
2499static uint32_t
2500intel_gen6_edp_signal_levels(uint8_t train_set)
2501{
3c5a62b5
YL		 2502 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2503 DP_TRAIN_PRE_EMPHASIS_MASK);
2504 switch (signal_levels) {
e3421a18 2505 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2506 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2507 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2508 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2509 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2510 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2511 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2512 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2513 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2514 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2515 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2516 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2517 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2518 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2519 default:
3c5a62b5
YL		 2520 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2521 "0x%x\n", signal_levels);
2522 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2523 }
2524}
2525
1a2eb460
KP		 2526/* Gen7's DP voltage swing and pre-emphasis control */
2527static uint32_t
2528intel_gen7_edp_signal_levels(uint8_t train_set)
2529{
2530 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2531 DP_TRAIN_PRE_EMPHASIS_MASK);
2532 switch (signal_levels) {
2533 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2534 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2535 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2536 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2537 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2538 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2539
2540 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2541 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2542 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2543 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2544
2545 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2546 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2547 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2548 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2549
2550 default:
2551 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2552 "0x%x\n", signal_levels);
2553 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2554 }
2555}
2556
d6c0d722
PZ		 2557/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2558static uint32_t
f0a3424e 2559intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2560{
d6c0d722
PZ		 2561 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2562 DP_TRAIN_PRE_EMPHASIS_MASK);
2563 switch (signal_levels) {
2564 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2565 return DDI_BUF_EMP_400MV_0DB_HSW;
2566 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2567 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2568 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2569 return DDI_BUF_EMP_400MV_6DB_HSW;
2570 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2571 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2572
d6c0d722
PZ		 2573 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2574 return DDI_BUF_EMP_600MV_0DB_HSW;
2575 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2576 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2577 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2578 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2579
d6c0d722
PZ		 2580 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2581 return DDI_BUF_EMP_800MV_0DB_HSW;
2582 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2583 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2584 default:
2585 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2586 "0x%x\n", signal_levels);
2587 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2588 }
a4fc5ed6
KP		 2589}
2590
8f93f4f1
PZ		 2591static uint32_t
2592intel_bdw_signal_levels(uint8_t train_set)
2593{
2594 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2595 DP_TRAIN_PRE_EMPHASIS_MASK);
2596 switch (signal_levels) {
2597 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2598 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2599 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2600 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2601 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2602 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2603
2604 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2605 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2606 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2607 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2608 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2609 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2610
2611 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2612 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2613 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2614 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2615
2616 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2617 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2618
2619 default:
2620 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2621 "0x%x\n", signal_levels);
2622 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2623 }
2624}
2625
f0a3424e
PZ		 2626/* Properly updates "DP" with the correct signal levels. */
2627static void
2628intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2629{
2630 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2631 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2632 struct drm_device *dev = intel_dig_port->base.base.dev;
2633 uint32_t signal_levels, mask;
2634 uint8_t train_set = intel_dp->train_set[0];
2635
8f93f4f1
PZ		 2636 if (IS_BROADWELL(dev)) {
2637 signal_levels = intel_bdw_signal_levels(train_set);
2638 mask = DDI_BUF_EMP_MASK;
2639 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2640 signal_levels = intel_hsw_signal_levels(train_set);
2641 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2642 } else if (IS_CHERRYVIEW(dev)) {
2643 signal_levels = intel_chv_signal_levels(intel_dp);
2644 mask = 0;
e2fa6fba
P		 2645 } else if (IS_VALLEYVIEW(dev)) {
2646 signal_levels = intel_vlv_signal_levels(intel_dp);
2647 mask = 0;
bc7d38a4 2648 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2649 signal_levels = intel_gen7_edp_signal_levels(train_set);
2650 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2651 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2652 signal_levels = intel_gen6_edp_signal_levels(train_set);
2653 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2654 } else {
2655 signal_levels = intel_gen4_signal_levels(train_set);
2656 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2657 }
2658
2659 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2660
2661 *DP = (*DP & ~mask) | signal_levels;
2662}
2663
a4fc5ed6 2664static bool
ea5b213a 2665intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2666 uint32_t *DP,
58e10eb9 2667 uint8_t dp_train_pat)
a4fc5ed6 2668{
174edf1f
PZ		 2669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2670 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2671 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2672 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2673 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2674 int ret, len;
a4fc5ed6 2675
22b8bf17 2676 if (HAS_DDI(dev)) {
3ab9c637 2677 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2678
2679 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2680 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2681 else
2682 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2683
2684 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2685 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2686 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2687 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2688
2689 break;
2690 case DP_TRAINING_PATTERN_1:
2691 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2692 break;
2693 case DP_TRAINING_PATTERN_2:
2694 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2695 break;
2696 case DP_TRAINING_PATTERN_3:
2697 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2698 break;
2699 }
174edf1f 2700 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2701
bc7d38a4 2702 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2703 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2704
2705 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2706 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2707 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2708 break;
2709 case DP_TRAINING_PATTERN_1:
70aff66c 2710 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2711 break;
2712 case DP_TRAINING_PATTERN_2:
70aff66c 2713 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2714 break;
2715 case DP_TRAINING_PATTERN_3:
2716 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2717 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2718 break;
2719 }
2720
2721 } else {
70aff66c 2722 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2723
2724 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2725 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2726 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2727 break;
2728 case DP_TRAINING_PATTERN_1:
70aff66c 2729 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2730 break;
2731 case DP_TRAINING_PATTERN_2:
70aff66c 2732 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2733 break;
2734 case DP_TRAINING_PATTERN_3:
2735 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2736 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2737 break;
2738 }
2739 }
2740
70aff66c 2741 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2742 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2743
2cdfe6c8
JN		 2744 buf[0] = dp_train_pat;
2745 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2746 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2747 /* don't write DP_TRAINING_LANEx_SET on disable */
2748 len = 1;
2749 } else {
2750 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2751 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2752 len = intel_dp->lane_count + 1;
47ea7542 2753 }
a4fc5ed6 2754
9d1a1031
JN		 2755 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2756 buf, len);
2cdfe6c8
JN		 2757
2758 return ret == len;
a4fc5ed6
KP		 2759}
2760
70aff66c
JN		 2761static bool
2762intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2763 uint8_t dp_train_pat)
2764{
953d22e8 2765 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2766 intel_dp_set_signal_levels(intel_dp, DP);
2767 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2768}
2769
2770static bool
2771intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2772 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2773{
2774 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2775 struct drm_device *dev = intel_dig_port->base.base.dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 int ret;
2778
2779 intel_get_adjust_train(intel_dp, link_status);
2780 intel_dp_set_signal_levels(intel_dp, DP);
2781
2782 I915_WRITE(intel_dp->output_reg, *DP);
2783 POSTING_READ(intel_dp->output_reg);
2784
9d1a1031
JN		 2785 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2786 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2787
2788 return ret == intel_dp->lane_count;
2789}
2790
3ab9c637
ID		 2791static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2792{
2793 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2794 struct drm_device *dev = intel_dig_port->base.base.dev;
2795 struct drm_i915_private *dev_priv = dev->dev_private;
2796 enum port port = intel_dig_port->port;
2797 uint32_t val;
2798
2799 if (!HAS_DDI(dev))
2800 return;
2801
2802 val = I915_READ(DP_TP_CTL(port));
2803 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2804 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2805 I915_WRITE(DP_TP_CTL(port), val);
2806
2807 /*
2808 * On PORT_A we can have only eDP in SST mode. There the only reason
2809 * we need to set idle transmission mode is to work around a HW issue
2810 * where we enable the pipe while not in idle link-training mode.
2811 * In this case there is requirement to wait for a minimum number of
2812 * idle patterns to be sent.
2813 */
2814 if (port == PORT_A)
2815 return;
2816
2817 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2818 1))
2819 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2820}
2821
33a34e4e 2822/* Enable corresponding port and start training pattern 1 */
c19b0669 2823void
33a34e4e 2824intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2825{
da63a9f2 2826 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2827 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2828 int i;
2829 uint8_t voltage;
cdb0e95b 2830 int voltage_tries, loop_tries;
ea5b213a 2831 uint32_t DP = intel_dp->DP;
6aba5b6c 2832 uint8_t link_config[2];
a4fc5ed6 2833
affa9354 2834 if (HAS_DDI(dev))
c19b0669
PZ		 2835 intel_ddi_prepare_link_retrain(encoder);
2836
3cf2efb1 2837 /* Write the link configuration data */
6aba5b6c
JN		 2838 link_config[0] = intel_dp->link_bw;
2839 link_config[1] = intel_dp->lane_count;
2840 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2841 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 2842 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 2843
2844 link_config[0] = 0;
2845 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 2846 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2847
2848 DP |= DP_PORT_EN;
1a2eb460 2849
70aff66c
JN		 2850 /* clock recovery */
2851 if (!intel_dp_reset_link_train(intel_dp, &DP,
2852 DP_TRAINING_PATTERN_1 |
2853 DP_LINK_SCRAMBLING_DISABLE)) {
2854 DRM_ERROR("failed to enable link training\n");
2855 return;
2856 }
2857
a4fc5ed6 2858 voltage = 0xff;
cdb0e95b
KP		 2859 voltage_tries = 0;
2860 loop_tries = 0;
a4fc5ed6 2861 for (;;) {
70aff66c 2862 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2863
a7c9655f 2864 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2865 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2866 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2867 break;
93f62dad 2868 }
a4fc5ed6 2869
01916270 2870 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2871 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2872 break;
2873 }
2874
2875 /* Check to see if we've tried the max voltage */
2876 for (i = 0; i < intel_dp->lane_count; i++)
2877 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2878 break;
3b4f819d 2879 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2880 ++loop_tries;
2881 if (loop_tries == 5) {
3def84b3 2882 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2883 break;
2884 }
70aff66c
JN		 2885 intel_dp_reset_link_train(intel_dp, &DP,
2886 DP_TRAINING_PATTERN_1 |
2887 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2888 voltage_tries = 0;
2889 continue;
2890 }
a4fc5ed6 2891
3cf2efb1 2892 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2893 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2894 ++voltage_tries;
b06fbda3 2895 if (voltage_tries == 5) {
3def84b3 2896 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2897 break;
2898 }
2899 } else
2900 voltage_tries = 0;
2901 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2902
70aff66c
JN		 2903 /* Update training set as requested by target */
2904 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2905 DRM_ERROR("failed to update link training\n");
2906 break;
2907 }
a4fc5ed6
KP		 2908 }
2909
33a34e4e
JB		 2910 intel_dp->DP = DP;
2911}
2912
c19b0669 2913void
33a34e4e
JB		 2914intel_dp_complete_link_train(struct intel_dp *intel_dp)
2915{
33a34e4e 2916 bool channel_eq = false;
37f80975 2917 int tries, cr_tries;
33a34e4e 2918 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2919 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2920
2921 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2922 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2923 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2924
a4fc5ed6 2925 /* channel equalization */
70aff66c 2926 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2927 training_pattern |
70aff66c
JN		 2928 DP_LINK_SCRAMBLING_DISABLE)) {
2929 DRM_ERROR("failed to start channel equalization\n");
2930 return;
2931 }
2932
a4fc5ed6 2933 tries = 0;
37f80975 2934 cr_tries = 0;
a4fc5ed6
KP		 2935 channel_eq = false;
2936 for (;;) {
70aff66c 2937 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2938
37f80975
JB		 2939 if (cr_tries > 5) {
2940 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2941 break;
2942 }
2943
a7c9655f 2944 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2945 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2946 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2947 break;
70aff66c 2948 }
a4fc5ed6 2949
37f80975 2950 /* Make sure clock is still ok */
01916270 2951 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2952 intel_dp_start_link_train(intel_dp);
70aff66c 2953 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2954 training_pattern |
70aff66c 2955 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2956 cr_tries++;
2957 continue;
2958 }
2959
1ffdff13 2960 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2961 channel_eq = true;
2962 break;
2963 }
a4fc5ed6 2964
37f80975
JB		 2965 /* Try 5 times, then try clock recovery if that fails */
2966 if (tries > 5) {
2967 intel_dp_link_down(intel_dp);
2968 intel_dp_start_link_train(intel_dp);
70aff66c 2969 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2970 training_pattern |
70aff66c 2971 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2972 tries = 0;
2973 cr_tries++;
2974 continue;
2975 }
a4fc5ed6 2976
70aff66c
JN		 2977 /* Update training set as requested by target */
2978 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2979 DRM_ERROR("failed to update link training\n");
2980 break;
2981 }
3cf2efb1 2982 ++tries;
869184a6 2983 }
3cf2efb1 2984
3ab9c637
ID		 2985 intel_dp_set_idle_link_train(intel_dp);
2986
2987 intel_dp->DP = DP;
2988
d6c0d722 2989 if (channel_eq)
07f42258 2990 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2991
3ab9c637
ID		 2992}
2993
2994void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2995{
70aff66c 2996 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2997 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2998}
2999
3000static void
ea5b213a 3001intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3002{
da63a9f2 3003 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3004 enum port port = intel_dig_port->port;
da63a9f2 3005 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3006 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3007 struct intel_crtc *intel_crtc =
3008 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3009 uint32_t DP = intel_dp->DP;
a4fc5ed6 3010
c19b0669
PZ		 3011 /*
3012 * DDI code has a strict mode set sequence and we should try to respect
3013 * it, otherwise we might hang the machine in many different ways. So we
3014 * really should be disabling the port only on a complete crtc_disable
3015 * sequence. This function is just called under two conditions on DDI
3016 * code:
3017 * - Link train failed while doing crtc_enable, and on this case we
3018 * really should respect the mode set sequence and wait for a
3019 * crtc_disable.
3020 * - Someone turned the monitor off and intel_dp_check_link_status
3021 * called us. We don't need to disable the whole port on this case, so
3022 * when someone turns the monitor on again,
3023 * intel_ddi_prepare_link_retrain will take care of redoing the link
3024 * train.
3025 */
affa9354 3026 if (HAS_DDI(dev))
c19b0669
PZ		 3027 return;
3028
0c33d8d7 3029 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3030 return;
3031
28c97730 3032 DRM_DEBUG_KMS("\n");
32f9d658 3033
bc7d38a4 3034 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3035 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3036 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 3037 } else {
3038 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3039 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3040 }
fe255d00 3041 POSTING_READ(intel_dp->output_reg);
5eb08b69 3042
493a7081 3043 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3044 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3045 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3046
5bddd17f
EA		 3047 /* Hardware workaround: leaving our transcoder select
3048 * set to transcoder B while it's off will prevent the
3049 * corresponding HDMI output on transcoder A.
3050 *
3051 * Combine this with another hardware workaround:
3052 * transcoder select bit can only be cleared while the
3053 * port is enabled.
3054 */
3055 DP &= ~DP_PIPEB_SELECT;
3056 I915_WRITE(intel_dp->output_reg, DP);
3057
3058 /* Changes to enable or select take place the vblank
3059 * after being written.
3060 */
ff50afe9
DV		 3061 if (WARN_ON(crtc == NULL)) {
3062 /* We should never try to disable a port without a crtc
3063 * attached. For paranoia keep the code around for a
3064 * bit. */
31acbcc4
CW		 3065 POSTING_READ(intel_dp->output_reg);
3066 msleep(50);
3067 } else
ab527efc 3068 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3069 }
3070
832afda6 3071 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3072 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3073 POSTING_READ(intel_dp->output_reg);
f01eca2e 3074 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3075}
3076
26d61aad
KP		 3077static bool
3078intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3079{
a031d709
RV		 3080 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3081 struct drm_device *dev = dig_port->base.base.dev;
3082 struct drm_i915_private *dev_priv = dev->dev_private;
3083
577c7a50
DL		 3084 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3085
9d1a1031
JN		 3086 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3087 sizeof(intel_dp->dpcd)) < 0)
edb39244 3088 return false; /* aux transfer failed */
92fd8fd1 3089
577c7a50
DL		 3090 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3091 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3092 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3093
edb39244
AJ		 3094 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3095 return false; /* DPCD not present */
3096
2293bb5c
SK		 3097 /* Check if the panel supports PSR */
3098 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3099 if (is_edp(intel_dp)) {
9d1a1031
JN		 3100 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3101 intel_dp->psr_dpcd,
3102 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3103 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3104 dev_priv->psr.sink_support = true;
50003939 3105 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3106 }
50003939
JN		 3107 }
3108
06ea66b6
TP		 3109 /* Training Pattern 3 support */
3110 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3111 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3112 intel_dp->use_tps3 = true;
3113 DRM_DEBUG_KMS("Displayport TPS3 supported");
3114 } else
3115 intel_dp->use_tps3 = false;
3116
edb39244
AJ		 3117 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3118 DP_DWN_STRM_PORT_PRESENT))
3119 return true; /* native DP sink */
3120
3121 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3122 return true; /* no per-port downstream info */
3123
9d1a1031
JN		 3124 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3125 intel_dp->downstream_ports,
3126 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3127 return false; /* downstream port status fetch failed */
3128
3129 return true;
92fd8fd1
KP		 3130}
3131
0d198328
AJ		 3132static void
3133intel_dp_probe_oui(struct intel_dp *intel_dp)
3134{
3135 u8 buf[3];
3136
3137 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3138 return;
3139
24f3e092 3140 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3141
9d1a1031 3142 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3143 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3144 buf[0], buf[1], buf[2]);
3145
9d1a1031 3146 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3147 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3148 buf[0], buf[1], buf[2]);
351cfc34 3149
4be73780 3150 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3151}
3152
d2e216d0
RV		 3153int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3154{
3155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3156 struct drm_device *dev = intel_dig_port->base.base.dev;
3157 struct intel_crtc *intel_crtc =
3158 to_intel_crtc(intel_dig_port->base.base.crtc);
3159 u8 buf[1];
3160
9d1a1031 3161 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3162 return -EAGAIN;
3163
3164 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3165 return -ENOTTY;
3166
9d1a1031
JN		 3167 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3168 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3169 return -EAGAIN;
3170
3171 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3172 intel_wait_for_vblank(dev, intel_crtc->pipe);
3173 intel_wait_for_vblank(dev, intel_crtc->pipe);
3174
9d1a1031 3175 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3176 return -EAGAIN;
3177
9d1a1031 3178 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3179 return 0;
3180}
3181
a60f0e38
JB		 3182static bool
3183intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3184{
9d1a1031
JN		 3185 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3186 DP_DEVICE_SERVICE_IRQ_VECTOR,
3187 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3188}
3189
3190static void
3191intel_dp_handle_test_request(struct intel_dp *intel_dp)
3192{
3193 /* NAK by default */
9d1a1031 3194 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3195}
3196
a4fc5ed6
KP		 3197/*
3198 * According to DP spec
3199 * 5.1.2:
3200 * 1. Read DPCD
3201 * 2. Configure link according to Receiver Capabilities
3202 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3203 * 4. Check link status on receipt of hot-plug interrupt
3204 */
3205
00c09d70 3206void
ea5b213a 3207intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3208{
da63a9f2 3209 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3210 u8 sink_irq_vector;
93f62dad 3211 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3212
da63a9f2 3213 if (!intel_encoder->connectors_active)
d2b996ac 3214 return;
59cd09e1 3215
da63a9f2 3216 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3217 return;
3218
92fd8fd1 3219 /* Try to read receiver status if the link appears to be up */
93f62dad 3220 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3221 return;
3222 }
3223
92fd8fd1 3224 /* Now read the DPCD to see if it's actually running */
26d61aad 3225 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3226 return;
3227 }
3228
a60f0e38
JB		 3229 /* Try to read the source of the interrupt */
3230 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3231 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3232 /* Clear interrupt source */
9d1a1031
JN		 3233 drm_dp_dpcd_writeb(&intel_dp->aux,
3234 DP_DEVICE_SERVICE_IRQ_VECTOR,
3235 sink_irq_vector);
a60f0e38
JB		 3236
3237 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3238 intel_dp_handle_test_request(intel_dp);
3239 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3240 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3241 }
3242
1ffdff13 3243 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3244 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 3245 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 3246 intel_dp_start_link_train(intel_dp);
3247 intel_dp_complete_link_train(intel_dp);
3ab9c637 3248 intel_dp_stop_link_train(intel_dp);
33a34e4e 3249 }
a4fc5ed6 3250}
a4fc5ed6 3251
caf9ab24 3252/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3253static enum drm_connector_status
26d61aad 3254intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3255{
caf9ab24 3256 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3257 uint8_t type;
3258
3259 if (!intel_dp_get_dpcd(intel_dp))
3260 return connector_status_disconnected;
3261
3262 /* if there's no downstream port, we're done */
3263 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3264 return connector_status_connected;
caf9ab24
AJ		 3265
3266 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3267 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3268 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3269 uint8_t reg;
9d1a1031
JN		 3270
3271 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3272 &reg, 1) < 0)
caf9ab24 3273 return connector_status_unknown;
9d1a1031 3274
23235177
AJ		 3275 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3276 : connector_status_disconnected;
caf9ab24
AJ		 3277 }
3278
3279 /* If no HPD, poke DDC gently */
0b99836f 3280 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3281 return connector_status_connected;
caf9ab24
AJ		 3282
3283 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3284 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3285 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3286 if (type == DP_DS_PORT_TYPE_VGA ||
3287 type == DP_DS_PORT_TYPE_NON_EDID)
3288 return connector_status_unknown;
3289 } else {
3290 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3291 DP_DWN_STRM_PORT_TYPE_MASK;
3292 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3293 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3294 return connector_status_unknown;
3295 }
caf9ab24
AJ		 3296
3297 /* Anything else is out of spec, warn and ignore */
3298 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3299 return connector_status_disconnected;
71ba9000
AJ		 3300}
3301
5eb08b69 3302static enum drm_connector_status
a9756bb5 3303ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3304{
30add22d 3305 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3306 struct drm_i915_private *dev_priv = dev->dev_private;
3307 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3308 enum drm_connector_status status;
3309
fe16d949
CW		 3310 /* Can't disconnect eDP, but you can close the lid... */
3311 if (is_edp(intel_dp)) {
30add22d 3312 status = intel_panel_detect(dev);
fe16d949
CW		 3313 if (status == connector_status_unknown)
3314 status = connector_status_connected;
3315 return status;
3316 }
01cb9ea6 3317
1b469639
DL		 3318 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3319 return connector_status_disconnected;
3320
26d61aad 3321 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3322}
3323
a4fc5ed6 3324static enum drm_connector_status
a9756bb5 3325g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3326{
30add22d 3327 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3328 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3329 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3330 uint32_t bit;
5eb08b69 3331
35aad75f
JB		 3332 /* Can't disconnect eDP, but you can close the lid... */
3333 if (is_edp(intel_dp)) {
3334 enum drm_connector_status status;
3335
3336 status = intel_panel_detect(dev);
3337 if (status == connector_status_unknown)
3338 status = connector_status_connected;
3339 return status;
3340 }
3341
232a6ee9
TP		 3342 if (IS_VALLEYVIEW(dev)) {
3343 switch (intel_dig_port->port) {
3344 case PORT_B:
3345 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3346 break;
3347 case PORT_C:
3348 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3349 break;
3350 case PORT_D:
3351 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3352 break;
3353 default:
3354 return connector_status_unknown;
3355 }
3356 } else {
3357 switch (intel_dig_port->port) {
3358 case PORT_B:
3359 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3360 break;
3361 case PORT_C:
3362 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3363 break;
3364 case PORT_D:
3365 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3366 break;
3367 default:
3368 return connector_status_unknown;
3369 }
a4fc5ed6
KP		 3370 }
3371
10f76a38 3372 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3373 return connector_status_disconnected;
3374
26d61aad 3375 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3376}
3377
8c241fef
KP		 3378static struct edid *
3379intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3380{
9cd300e0 3381 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3382
9cd300e0
JN		 3383 /* use cached edid if we have one */
3384 if (intel_connector->edid) {
9cd300e0
JN		 3385 /* invalid edid */
3386 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3387 return NULL;
3388
55e9edeb 3389 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3390 }
8c241fef 3391
9cd300e0 3392 return drm_get_edid(connector, adapter);
8c241fef
KP		 3393}
3394
3395static int
3396intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3397{
9cd300e0 3398 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3399
9cd300e0
JN		 3400 /* use cached edid if we have one */
3401 if (intel_connector->edid) {
3402 /* invalid edid */
3403 if (IS_ERR(intel_connector->edid))
3404 return 0;
3405
3406 return intel_connector_update_modes(connector,
3407 intel_connector->edid);
d6f24d0f
JB		 3408 }
3409
9cd300e0 3410 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3411}
3412
a9756bb5
ZW		 3413static enum drm_connector_status
3414intel_dp_detect(struct drm_connector *connector, bool force)
3415{
3416 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3417 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3418 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3419 struct drm_device *dev = connector->dev;
c8c8fb33 3420 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3421 enum drm_connector_status status;
671dedd2 3422 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3423 struct edid *edid = NULL;
3424
c8c8fb33
PZ		 3425 intel_runtime_pm_get(dev_priv);
3426
671dedd2
ID		 3427 power_domain = intel_display_port_power_domain(intel_encoder);
3428 intel_display_power_get(dev_priv, power_domain);
3429
164c8598
CW		 3430 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3431 connector->base.id, drm_get_connector_name(connector));
3432
a9756bb5
ZW		 3433 intel_dp->has_audio = false;
3434
3435 if (HAS_PCH_SPLIT(dev))
3436 status = ironlake_dp_detect(intel_dp);
3437 else
3438 status = g4x_dp_detect(intel_dp);
1b9be9d0 3439
a9756bb5 3440 if (status != connector_status_connected)
c8c8fb33 3441 goto out;
a9756bb5 3442
0d198328
AJ		 3443 intel_dp_probe_oui(intel_dp);
3444
c3e5f67b
DV		 3445 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3446 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3447 } else {
0b99836f 3448 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3449 if (edid) {
3450 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3451 kfree(edid);
3452 }
a9756bb5
ZW		 3453 }
3454
d63885da
PZ		 3455 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3456 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3457 status = connector_status_connected;
3458
3459out:
671dedd2
ID		 3460 intel_display_power_put(dev_priv, power_domain);
3461
c8c8fb33 3462 intel_runtime_pm_put(dev_priv);
671dedd2 3463
c8c8fb33 3464 return status;
a4fc5ed6
KP		 3465}
3466
3467static int intel_dp_get_modes(struct drm_connector *connector)
3468{
df0e9248 3469 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3470 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3471 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3472 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3473 struct drm_device *dev = connector->dev;
671dedd2
ID		 3474 struct drm_i915_private *dev_priv = dev->dev_private;
3475 enum intel_display_power_domain power_domain;
32f9d658 3476 int ret;
a4fc5ed6
KP		 3477
3478 /* We should parse the EDID data and find out if it has an audio sink
3479 */
3480
671dedd2
ID		 3481 power_domain = intel_display_port_power_domain(intel_encoder);
3482 intel_display_power_get(dev_priv, power_domain);
3483
0b99836f 3484 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3485 intel_display_power_put(dev_priv, power_domain);
f8779fda 3486 if (ret)
32f9d658
ZW		 3487 return ret;
3488
f8779fda 3489 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3490 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3491 struct drm_display_mode *mode;
dd06f90e
JN		 3492 mode = drm_mode_duplicate(dev,
3493 intel_connector->panel.fixed_mode);
f8779fda 3494 if (mode) {
32f9d658
ZW		 3495 drm_mode_probed_add(connector, mode);
3496 return 1;
3497 }
3498 }
3499 return 0;
a4fc5ed6
KP		 3500}
3501
1aad7ac0
CW		 3502static bool
3503intel_dp_detect_audio(struct drm_connector *connector)
3504{
3505 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3506 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3507 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3508 struct drm_device *dev = connector->dev;
3509 struct drm_i915_private *dev_priv = dev->dev_private;
3510 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3511 struct edid *edid;
3512 bool has_audio = false;
3513
671dedd2
ID		 3514 power_domain = intel_display_port_power_domain(intel_encoder);
3515 intel_display_power_get(dev_priv, power_domain);
3516
0b99836f 3517 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3518 if (edid) {
3519 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3520 kfree(edid);
3521 }
3522
671dedd2
ID		 3523 intel_display_power_put(dev_priv, power_domain);
3524
1aad7ac0
CW		 3525 return has_audio;
3526}
3527
f684960e
CW		 3528static int
3529intel_dp_set_property(struct drm_connector *connector,
3530 struct drm_property *property,
3531 uint64_t val)
3532{
e953fd7b 3533 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3534 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3535 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3536 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3537 int ret;
3538
662595df 3539 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3540 if (ret)
3541 return ret;
3542
3f43c48d 3543 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3544 int i = val;
3545 bool has_audio;
3546
3547 if (i == intel_dp->force_audio)
f684960e
CW		 3548 return 0;
3549
1aad7ac0 3550 intel_dp->force_audio = i;
f684960e 3551
c3e5f67b 3552 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3553 has_audio = intel_dp_detect_audio(connector);
3554 else
c3e5f67b 3555 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3556
3557 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3558 return 0;
3559
1aad7ac0 3560 intel_dp->has_audio = has_audio;
f684960e
CW		 3561 goto done;
3562 }
3563
e953fd7b 3564 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3565 bool old_auto = intel_dp->color_range_auto;
3566 uint32_t old_range = intel_dp->color_range;
3567
55bc60db
VS		 3568 switch (val) {
3569 case INTEL_BROADCAST_RGB_AUTO:
3570 intel_dp->color_range_auto = true;
3571 break;
3572 case INTEL_BROADCAST_RGB_FULL:
3573 intel_dp->color_range_auto = false;
3574 intel_dp->color_range = 0;
3575 break;
3576 case INTEL_BROADCAST_RGB_LIMITED:
3577 intel_dp->color_range_auto = false;
3578 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3579 break;
3580 default:
3581 return -EINVAL;
3582 }
ae4edb80
DV		 3583
3584 if (old_auto == intel_dp->color_range_auto &&
3585 old_range == intel_dp->color_range)
3586 return 0;
3587
e953fd7b
CW		 3588 goto done;
3589 }
3590
53b41837
YN		 3591 if (is_edp(intel_dp) &&
3592 property == connector->dev->mode_config.scaling_mode_property) {
3593 if (val == DRM_MODE_SCALE_NONE) {
3594 DRM_DEBUG_KMS("no scaling not supported\n");
3595 return -EINVAL;
3596 }
3597
3598 if (intel_connector->panel.fitting_mode == val) {
3599 /* the eDP scaling property is not changed */
3600 return 0;
3601 }
3602 intel_connector->panel.fitting_mode = val;
3603
3604 goto done;
3605 }
3606
f684960e
CW		 3607 return -EINVAL;
3608
3609done:
c0c36b94
CW		 3610 if (intel_encoder->base.crtc)
3611 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3612
3613 return 0;
3614}
3615
a4fc5ed6 3616static void
73845adf 3617intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3618{
1d508706 3619 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3620
9cd300e0
JN		 3621 if (!IS_ERR_OR_NULL(intel_connector->edid))
3622 kfree(intel_connector->edid);
3623
acd8db10
PZ		 3624 /* Can't call is_edp() since the encoder may have been destroyed
3625 * already. */
3626 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3627 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3628
a4fc5ed6 3629 drm_connector_cleanup(connector);
55f78c43 3630 kfree(connector);
a4fc5ed6
KP		 3631}
3632
00c09d70 3633void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3634{
da63a9f2
PZ		 3635 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3636 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3637 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3638
0b99836f 3639 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
24d05927 3640 drm_encoder_cleanup(encoder);
bd943159
KP		 3641 if (is_edp(intel_dp)) {
3642 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3643 mutex_lock(&dev->mode_config.mutex);
4be73780 3644 edp_panel_vdd_off_sync(intel_dp);
bd173813 3645 mutex_unlock(&dev->mode_config.mutex);
bd943159 3646 }
da63a9f2 3647 kfree(intel_dig_port);
24d05927
DV		 3648}
3649
a4fc5ed6 3650static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3651 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3652 .detect = intel_dp_detect,
3653 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3654 .set_property = intel_dp_set_property,
73845adf 3655 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3656};
3657
3658static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3659 .get_modes = intel_dp_get_modes,
3660 .mode_valid = intel_dp_mode_valid,
df0e9248 3661 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3662};
3663
a4fc5ed6 3664static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3665 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3666};
3667
995b6762 3668static void
21d40d37 3669intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3670{
fa90ecef 3671 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3672
885a5014 3673 intel_dp_check_link_status(intel_dp);
c8110e52 3674}
6207937d 3675
e3421a18
ZW		 3676/* Return which DP Port should be selected for Transcoder DP control */
3677int
0206e353 3678intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3679{
3680 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3681 struct intel_encoder *intel_encoder;
3682 struct intel_dp *intel_dp;
e3421a18 3683
fa90ecef
PZ		 3684 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3685 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3686
fa90ecef
PZ		 3687 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3688 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3689 return intel_dp->output_reg;
e3421a18 3690 }
ea5b213a 3691
e3421a18
ZW		 3692 return -1;
3693}
3694
36e83a18 3695/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3696bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3697{
3698 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3699 union child_device_config *p_child;
36e83a18 3700 int i;
5d8a7752
VS		 3701 static const short port_mapping[] = {
3702 [PORT_B] = PORT_IDPB,
3703 [PORT_C] = PORT_IDPC,
3704 [PORT_D] = PORT_IDPD,
3705 };
36e83a18 3706
3b32a35b
VS		 3707 if (port == PORT_A)
3708 return true;
3709
41aa3448 3710 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3711 return false;
3712
41aa3448
RV		 3713 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3714 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3715
5d8a7752 3716 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3717 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3718 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3719 return true;
3720 }
3721 return false;
3722}
3723
f684960e
CW		 3724static void
3725intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3726{
53b41837
YN		 3727 struct intel_connector *intel_connector = to_intel_connector(connector);
3728
3f43c48d 3729 intel_attach_force_audio_property(connector);
e953fd7b 3730 intel_attach_broadcast_rgb_property(connector);
55bc60db 3731 intel_dp->color_range_auto = true;
53b41837
YN		 3732
3733 if (is_edp(intel_dp)) {
3734 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3735 drm_object_attach_property(
3736 &connector->base,
53b41837 3737 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3738 DRM_MODE_SCALE_ASPECT);
3739 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3740 }
f684960e
CW		 3741}
3742
dada1a9f
ID		 3743static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3744{
3745 intel_dp->last_power_cycle = jiffies;
3746 intel_dp->last_power_on = jiffies;
3747 intel_dp->last_backlight_off = jiffies;
3748}
3749
67a54566
DV		 3750static void
3751intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3752 struct intel_dp *intel_dp,
3753 struct edp_power_seq *out)
67a54566
DV		 3754{
3755 struct drm_i915_private *dev_priv = dev->dev_private;
3756 struct edp_power_seq cur, vbt, spec, final;
3757 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3758 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3759
3760 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3761 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3762 pp_on_reg = PCH_PP_ON_DELAYS;
3763 pp_off_reg = PCH_PP_OFF_DELAYS;
3764 pp_div_reg = PCH_PP_DIVISOR;
3765 } else {
bf13e81b
JN		 3766 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3767
3768 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3769 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3770 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3771 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3772 }
67a54566
DV		 3773
3774 /* Workaround: Need to write PP_CONTROL with the unlock key as
3775 * the very first thing. */
453c5420 3776 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3777 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3778
453c5420
JB		 3779 pp_on = I915_READ(pp_on_reg);
3780 pp_off = I915_READ(pp_off_reg);
3781 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3782
3783 /* Pull timing values out of registers */
3784 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3785 PANEL_POWER_UP_DELAY_SHIFT;
3786
3787 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3788 PANEL_LIGHT_ON_DELAY_SHIFT;
3789
3790 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3791 PANEL_LIGHT_OFF_DELAY_SHIFT;
3792
3793 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3794 PANEL_POWER_DOWN_DELAY_SHIFT;
3795
3796 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3797 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3798
3799 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3800 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3801
41aa3448 3802 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3803
3804 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3805 * our hw here, which are all in 100usec. */
3806 spec.t1_t3 = 210 * 10;
3807 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3808 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3809 spec.t10 = 500 * 10;
3810 /* This one is special and actually in units of 100ms, but zero
3811 * based in the hw (so we need to add 100 ms). But the sw vbt
3812 * table multiplies it with 1000 to make it in units of 100usec,
3813 * too. */
3814 spec.t11_t12 = (510 + 100) * 10;
3815
3816 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3817 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3818
3819 /* Use the max of the register settings and vbt. If both are
3820 * unset, fall back to the spec limits. */
3821#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3822 spec.field : \
3823 max(cur.field, vbt.field))
3824 assign_final(t1_t3);
3825 assign_final(t8);
3826 assign_final(t9);
3827 assign_final(t10);
3828 assign_final(t11_t12);
3829#undef assign_final
3830
3831#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3832 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3833 intel_dp->backlight_on_delay = get_delay(t8);
3834 intel_dp->backlight_off_delay = get_delay(t9);
3835 intel_dp->panel_power_down_delay = get_delay(t10);
3836 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3837#undef get_delay
3838
f30d26e4
JN		 3839 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3840 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3841 intel_dp->panel_power_cycle_delay);
3842
3843 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3844 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3845
3846 if (out)
3847 *out = final;
3848}
3849
3850static void
3851intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3852 struct intel_dp *intel_dp,
3853 struct edp_power_seq *seq)
3854{
3855 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3856 u32 pp_on, pp_off, pp_div, port_sel = 0;
3857 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3858 int pp_on_reg, pp_off_reg, pp_div_reg;
3859
3860 if (HAS_PCH_SPLIT(dev)) {
3861 pp_on_reg = PCH_PP_ON_DELAYS;
3862 pp_off_reg = PCH_PP_OFF_DELAYS;
3863 pp_div_reg = PCH_PP_DIVISOR;
3864 } else {
bf13e81b
JN		 3865 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3866
3867 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3868 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3869 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3870 }
3871
b2f19d1a
PZ		 3872 /*
3873 * And finally store the new values in the power sequencer. The
3874 * backlight delays are set to 1 because we do manual waits on them. For
3875 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3876 * we'll end up waiting for the backlight off delay twice: once when we
3877 * do the manual sleep, and once when we disable the panel and wait for
3878 * the PP_STATUS bit to become zero.
3879 */
f30d26e4 3880 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3881 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3882 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3883 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3884 /* Compute the divisor for the pp clock, simply match the Bspec
3885 * formula. */
453c5420 3886 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3887 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3888 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3889
3890 /* Haswell doesn't have any port selection bits for the panel
3891 * power sequencer any more. */
bc7d38a4 3892 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3893 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3894 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3895 else
3896 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3897 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3898 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3899 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3900 else
a24c144c 3901 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3902 }
3903
453c5420
JB		 3904 pp_on |= port_sel;
3905
3906 I915_WRITE(pp_on_reg, pp_on);
3907 I915_WRITE(pp_off_reg, pp_off);
3908 I915_WRITE(pp_div_reg, pp_div);
67a54566 3909
67a54566 3910 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3911 I915_READ(pp_on_reg),
3912 I915_READ(pp_off_reg),
3913 I915_READ(pp_div_reg));
f684960e
CW		 3914}
3915
439d7ac0
PB		 3916void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
3917{
3918 struct drm_i915_private *dev_priv = dev->dev_private;
3919 struct intel_encoder *encoder;
3920 struct intel_dp *intel_dp = NULL;
3921 struct intel_crtc_config *config = NULL;
3922 struct intel_crtc *intel_crtc = NULL;
3923 struct intel_connector *intel_connector = dev_priv->drrs.connector;
3924 u32 reg, val;
3925 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
3926
3927 if (refresh_rate <= 0) {
3928 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
3929 return;
3930 }
3931
3932 if (intel_connector == NULL) {
3933 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
3934 return;
3935 }
3936
3937 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
3938 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
3939 return;
3940 }
3941
3942 encoder = intel_attached_encoder(&intel_connector->base);
3943 intel_dp = enc_to_intel_dp(&encoder->base);
3944 intel_crtc = encoder->new_crtc;
3945
3946 if (!intel_crtc) {
3947 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
3948 return;
3949 }
3950
3951 config = &intel_crtc->config;
3952
3953 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
3954 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
3955 return;
3956 }
3957
3958 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
3959 index = DRRS_LOW_RR;
3960
3961 if (index == intel_dp->drrs_state.refresh_rate_type) {
3962 DRM_DEBUG_KMS(
3963 "DRRS requested for previously set RR...ignoring\n");
3964 return;
3965 }
3966
3967 if (!intel_crtc->active) {
3968 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
3969 return;
3970 }
3971
3972 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
3973 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
3974 val = I915_READ(reg);
3975 if (index > DRRS_HIGH_RR) {
3976 val |= PIPECONF_EDP_RR_MODE_SWITCH;
3977 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
3978 } else {
3979 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
3980 }
3981 I915_WRITE(reg, val);
3982 }
3983
3984 /*
3985 * mutex taken to ensure that there is no race between differnt
3986 * drrs calls trying to update refresh rate. This scenario may occur
3987 * in future when idleness detection based DRRS in kernel and
3988 * possible calls from user space to set differnt RR are made.
3989 */
3990
3991 mutex_lock(&intel_dp->drrs_state.mutex);
3992
3993 intel_dp->drrs_state.refresh_rate_type = index;
3994
3995 mutex_unlock(&intel_dp->drrs_state.mutex);
3996
3997 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
3998}
3999
4f9db5b5
PB		 4000static struct drm_display_mode *
4001intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4002 struct intel_connector *intel_connector,
4003 struct drm_display_mode *fixed_mode)
4004{
4005 struct drm_connector *connector = &intel_connector->base;
4006 struct intel_dp *intel_dp = &intel_dig_port->dp;
4007 struct drm_device *dev = intel_dig_port->base.base.dev;
4008 struct drm_i915_private *dev_priv = dev->dev_private;
4009 struct drm_display_mode *downclock_mode = NULL;
4010
4011 if (INTEL_INFO(dev)->gen <= 6) {
4012 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4013 return NULL;
4014 }
4015
4016 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4017 DRM_INFO("VBT doesn't support DRRS\n");
4018 return NULL;
4019 }
4020
4021 downclock_mode = intel_find_panel_downclock
4022 (dev, fixed_mode, connector);
4023
4024 if (!downclock_mode) {
4025 DRM_INFO("DRRS not supported\n");
4026 return NULL;
4027 }
4028
439d7ac0
PB		 4029 dev_priv->drrs.connector = intel_connector;
4030
4031 mutex_init(&intel_dp->drrs_state.mutex);
4032
4f9db5b5
PB		 4033 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4034
4035 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4036 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4037 return downclock_mode;
4038}
4039
ed92f0b2 4040static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4041 struct intel_connector *intel_connector,
4042 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4043{
4044 struct drm_connector *connector = &intel_connector->base;
4045 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4046 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4047 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4050 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4051 bool has_dpcd;
4052 struct drm_display_mode *scan;
4053 struct edid *edid;
4054
4f9db5b5
PB		 4055 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4056
ed92f0b2
PZ		 4057 if (!is_edp(intel_dp))
4058 return true;
4059
63635217
PZ		 4060 /* The VDD bit needs a power domain reference, so if the bit is already
4061 * enabled when we boot, grab this reference. */
4062 if (edp_have_panel_vdd(intel_dp)) {
4063 enum intel_display_power_domain power_domain;
4064 power_domain = intel_display_port_power_domain(intel_encoder);
4065 intel_display_power_get(dev_priv, power_domain);
4066 }
4067
ed92f0b2 4068 /* Cache DPCD and EDID for edp. */
24f3e092 4069 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4070 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 4071 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4072
4073 if (has_dpcd) {
4074 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4075 dev_priv->no_aux_handshake =
4076 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4077 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4078 } else {
4079 /* if this fails, presume the device is a ghost */
4080 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4081 return false;
4082 }
4083
4084 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4085 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4086
060c8778 4087 mutex_lock(&dev->mode_config.mutex);
0b99836f 4088 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4089 if (edid) {
4090 if (drm_add_edid_modes(connector, edid)) {
4091 drm_mode_connector_update_edid_property(connector,
4092 edid);
4093 drm_edid_to_eld(connector, edid);
4094 } else {
4095 kfree(edid);
4096 edid = ERR_PTR(-EINVAL);
4097 }
4098 } else {
4099 edid = ERR_PTR(-ENOENT);
4100 }
4101 intel_connector->edid = edid;
4102
4103 /* prefer fixed mode from EDID if available */
4104 list_for_each_entry(scan, &connector->probed_modes, head) {
4105 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4106 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4107 downclock_mode = intel_dp_drrs_init(
4108 intel_dig_port,
4109 intel_connector, fixed_mode);
ed92f0b2
PZ		 4110 break;
4111 }
4112 }
4113
4114 /* fallback to VBT if available for eDP */
4115 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4116 fixed_mode = drm_mode_duplicate(dev,
4117 dev_priv->vbt.lfp_lvds_vbt_mode);
4118 if (fixed_mode)
4119 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4120 }
060c8778 4121 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4122
4f9db5b5 4123 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
ed92f0b2
PZ		 4124 intel_panel_setup_backlight(connector);
4125
4126 return true;
4127}
4128
16c25533 4129bool
f0fec3f2
PZ		 4130intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4131 struct intel_connector *intel_connector)
a4fc5ed6 4132{
f0fec3f2
PZ		 4133 struct drm_connector *connector = &intel_connector->base;
4134 struct intel_dp *intel_dp = &intel_dig_port->dp;
4135 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4136 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4137 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4138 enum port port = intel_dig_port->port;
0095e6dc 4139 struct edp_power_seq power_seq = { 0 };
0b99836f 4140 int type;
a4fc5ed6 4141
ec5b01dd
DL		 4142 /* intel_dp vfuncs */
4143 if (IS_VALLEYVIEW(dev))
4144 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4145 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4146 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4147 else if (HAS_PCH_SPLIT(dev))
4148 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4149 else
4150 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4151
153b1100
DL		 4152 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4153
0767935e
DV		 4154 /* Preserve the current hw state. */
4155 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4156 intel_dp->attached_connector = intel_connector;
3d3dc149 4157
3b32a35b 4158 if (intel_dp_is_edp(dev, port))
b329530c 4159 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4160 else
4161 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4162
f7d24902
ID		 4163 /*
4164 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4165 * for DP the encoder type can be set by the caller to
4166 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4167 */
4168 if (type == DRM_MODE_CONNECTOR_eDP)
4169 intel_encoder->type = INTEL_OUTPUT_EDP;
4170
e7281eab
ID		 4171 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4172 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4173 port_name(port));
4174
b329530c 4175 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4176 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4177
a4fc5ed6
KP		 4178 connector->interlace_allowed = true;
4179 connector->doublescan_allowed = 0;
4180
f0fec3f2 4181 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4182 edp_panel_vdd_work);
a4fc5ed6 4183
df0e9248 4184 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 4185 drm_sysfs_connector_add(connector);
4186
affa9354 4187 if (HAS_DDI(dev))
bcbc889b
PZ		 4188 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4189 else
4190 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4191 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4192
0b99836f 4193 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4194 switch (port) {
4195 case PORT_A:
1d843f9d 4196 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4197 break;
4198 case PORT_B:
1d843f9d 4199 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4200 break;
4201 case PORT_C:
1d843f9d 4202 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4203 break;
4204 case PORT_D:
1d843f9d 4205 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4206 break;
4207 default:
ad1c0b19 4208 BUG();
5eb08b69
ZW		 4209 }
4210
dada1a9f
ID		 4211 if (is_edp(intel_dp)) {
4212 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4213 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4214 }
0095e6dc 4215
9d1a1031 4216 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4217
2b28bb1b
RV		 4218 intel_dp->psr_setup_done = false;
4219
0095e6dc 4220 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
0b99836f 4221 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
15b1d171
PZ		 4222 if (is_edp(intel_dp)) {
4223 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4224 mutex_lock(&dev->mode_config.mutex);
4be73780 4225 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 4226 mutex_unlock(&dev->mode_config.mutex);
4227 }
b2f246a8
PZ		 4228 drm_sysfs_connector_remove(connector);
4229 drm_connector_cleanup(connector);
16c25533 4230 return false;
b2f246a8 4231 }
32f9d658 4232
f684960e
CW		 4233 intel_dp_add_properties(intel_dp, connector);
4234
a4fc5ed6
KP		 4235 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4236 * 0xd. Failure to do so will result in spurious interrupts being
4237 * generated on the port when a cable is not attached.
4238 */
4239 if (IS_G4X(dev) && !IS_GM45(dev)) {
4240 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4241 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4242 }
16c25533
PZ		 4243
4244 return true;
a4fc5ed6 4245}
f0fec3f2
PZ		 4246
4247void
4248intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4249{
4250 struct intel_digital_port *intel_dig_port;
4251 struct intel_encoder *intel_encoder;
4252 struct drm_encoder *encoder;
4253 struct intel_connector *intel_connector;
4254
b14c5679 4255 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4256 if (!intel_dig_port)
4257 return;
4258
b14c5679 4259 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4260 if (!intel_connector) {
4261 kfree(intel_dig_port);
4262 return;
4263 }
4264
4265 intel_encoder = &intel_dig_port->base;
4266 encoder = &intel_encoder->base;
4267
4268 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4269 DRM_MODE_ENCODER_TMDS);
4270
5bfe2ac0 4271 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4272 intel_encoder->disable = intel_disable_dp;
00c09d70 4273 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4274 intel_encoder->get_config = intel_dp_get_config;
e4a1d846
CML		 4275 if (IS_CHERRYVIEW(dev)) {
4276 intel_encoder->pre_enable = chv_pre_enable_dp;
4277 intel_encoder->enable = vlv_enable_dp;
580d3811 4278 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4279 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4280 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4281 intel_encoder->pre_enable = vlv_pre_enable_dp;
4282 intel_encoder->enable = vlv_enable_dp;
49277c31 4283 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4284 } else {
ecff4f3b
JN		 4285 intel_encoder->pre_enable = g4x_pre_enable_dp;
4286 intel_encoder->enable = g4x_enable_dp;
49277c31 4287 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4288 }
f0fec3f2 4289
174edf1f 4290 intel_dig_port->port = port;
f0fec3f2
PZ		 4291 intel_dig_port->dp.output_reg = output_reg;
4292
00c09d70 4293 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4294 if (IS_CHERRYVIEW(dev)) {
4295 if (port == PORT_D)
4296 intel_encoder->crtc_mask = 1 << 2;
4297 else
4298 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4299 } else {
4300 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4301 }
bc079e8b 4302 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4303 intel_encoder->hot_plug = intel_dp_hot_plug;
4304
15b1d171
PZ		 4305 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4306 drm_encoder_cleanup(encoder);
4307 kfree(intel_dig_port);
b2f246a8 4308 kfree(intel_connector);
15b1d171 4309 }
f0fec3f2 4310}
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