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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
01527b31 CT |
31 | #include <linux/notifier.h> |
32 | #include <linux/reboot.h> | |
760285e7 DH |
33 | #include <drm/drmP.h> |
34 | #include <drm/drm_crtc.h> | |
35 | #include <drm/drm_crtc_helper.h> | |
36 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
a4fc5ed6 | 39 | #include "i915_drv.h" |
a4fc5ed6 | 40 | |
a4fc5ed6 KP |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
42 | ||
9dd4ffdf CML |
43 | struct dp_link_dpll { |
44 | int link_bw; | |
45 | struct dpll dpll; | |
46 | }; | |
47 | ||
48 | static const struct dp_link_dpll gen4_dpll[] = { | |
49 | { DP_LINK_BW_1_62, | |
50 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, | |
51 | { DP_LINK_BW_2_7, | |
52 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } | |
53 | }; | |
54 | ||
55 | static const struct dp_link_dpll pch_dpll[] = { | |
56 | { DP_LINK_BW_1_62, | |
57 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, | |
58 | { DP_LINK_BW_2_7, | |
59 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } | |
60 | }; | |
61 | ||
65ce4bf5 CML |
62 | static const struct dp_link_dpll vlv_dpll[] = { |
63 | { DP_LINK_BW_1_62, | |
58f6e632 | 64 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
65ce4bf5 CML |
65 | { DP_LINK_BW_2_7, |
66 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } | |
67 | }; | |
68 | ||
ef9348c8 CML |
69 | /* |
70 | * CHV supports eDP 1.4 that have more link rates. | |
71 | * Below only provides the fixed rate but exclude variable rate. | |
72 | */ | |
73 | static const struct dp_link_dpll chv_dpll[] = { | |
74 | /* | |
75 | * CHV requires to program fractional division for m2. | |
76 | * m2 is stored in fixed point format using formula below | |
77 | * (m2_int << 22) | m2_fraction | |
78 | */ | |
79 | { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */ | |
80 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, | |
81 | { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */ | |
82 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, | |
83 | { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */ | |
84 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } | |
85 | }; | |
86 | ||
cfcb0fc9 JB |
87 | /** |
88 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
89 | * @intel_dp: DP struct | |
90 | * | |
91 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
92 | * will return true, and false otherwise. | |
93 | */ | |
94 | static bool is_edp(struct intel_dp *intel_dp) | |
95 | { | |
da63a9f2 PZ |
96 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
97 | ||
98 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
99 | } |
100 | ||
68b4d824 | 101 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 102 | { |
68b4d824 ID |
103 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
104 | ||
105 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
106 | } |
107 | ||
df0e9248 CW |
108 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
109 | { | |
fa90ecef | 110 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
111 | } |
112 | ||
ea5b213a | 113 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
1e0560e0 | 114 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 115 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
093e3f13 | 116 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
a8c3344e VS |
117 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
118 | enum pipe pipe); | |
a4fc5ed6 | 119 | |
0e32b39c | 120 | int |
ea5b213a | 121 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 122 | { |
7183dc29 | 123 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
06ea66b6 | 124 | struct drm_device *dev = intel_dp->attached_connector->base.dev; |
a4fc5ed6 KP |
125 | |
126 | switch (max_link_bw) { | |
127 | case DP_LINK_BW_1_62: | |
128 | case DP_LINK_BW_2_7: | |
129 | break; | |
d4eead50 | 130 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ |
9bbfd20a PZ |
131 | if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || |
132 | INTEL_INFO(dev)->gen >= 8) && | |
06ea66b6 TP |
133 | intel_dp->dpcd[DP_DPCD_REV] >= 0x12) |
134 | max_link_bw = DP_LINK_BW_5_4; | |
135 | else | |
136 | max_link_bw = DP_LINK_BW_2_7; | |
d4eead50 | 137 | break; |
a4fc5ed6 | 138 | default: |
d4eead50 ID |
139 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
140 | max_link_bw); | |
a4fc5ed6 KP |
141 | max_link_bw = DP_LINK_BW_1_62; |
142 | break; | |
143 | } | |
144 | return max_link_bw; | |
145 | } | |
146 | ||
eeb6324d PZ |
147 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
148 | { | |
149 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
150 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
151 | u8 source_max, sink_max; | |
152 | ||
153 | source_max = 4; | |
154 | if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && | |
155 | (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) | |
156 | source_max = 2; | |
157 | ||
158 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); | |
159 | ||
160 | return min(source_max, sink_max); | |
161 | } | |
162 | ||
cd9dde44 AJ |
163 | /* |
164 | * The units on the numbers in the next two are... bizarre. Examples will | |
165 | * make it clearer; this one parallels an example in the eDP spec. | |
166 | * | |
167 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
168 | * | |
169 | * 270000 * 1 * 8 / 10 == 216000 | |
170 | * | |
171 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
172 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
173 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
174 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
175 | * | |
176 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
177 | * get the result in decakilobits instead of kilobits. | |
178 | */ | |
179 | ||
a4fc5ed6 | 180 | static int |
c898261c | 181 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 182 | { |
cd9dde44 | 183 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
184 | } |
185 | ||
fe27d53e DA |
186 | static int |
187 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
188 | { | |
189 | return (max_link_clock * max_lanes * 8) / 10; | |
190 | } | |
191 | ||
c19de8eb | 192 | static enum drm_mode_status |
a4fc5ed6 KP |
193 | intel_dp_mode_valid(struct drm_connector *connector, |
194 | struct drm_display_mode *mode) | |
195 | { | |
df0e9248 | 196 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
197 | struct intel_connector *intel_connector = to_intel_connector(connector); |
198 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
199 | int target_clock = mode->clock; |
200 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
a4fc5ed6 | 201 | |
dd06f90e JN |
202 | if (is_edp(intel_dp) && fixed_mode) { |
203 | if (mode->hdisplay > fixed_mode->hdisplay) | |
7de56f43 ZY |
204 | return MODE_PANEL; |
205 | ||
dd06f90e | 206 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 207 | return MODE_PANEL; |
03afc4a2 DV |
208 | |
209 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
210 | } |
211 | ||
36008365 | 212 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
eeb6324d | 213 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 DV |
214 | |
215 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
216 | mode_rate = intel_dp_link_required(target_clock, 18); | |
217 | ||
218 | if (mode_rate > max_rate) | |
c4867936 | 219 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
220 | |
221 | if (mode->clock < 10000) | |
222 | return MODE_CLOCK_LOW; | |
223 | ||
0af78a2b DV |
224 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
225 | return MODE_H_ILLEGAL; | |
226 | ||
a4fc5ed6 KP |
227 | return MODE_OK; |
228 | } | |
229 | ||
230 | static uint32_t | |
5ca476f8 | 231 | pack_aux(const uint8_t *src, int src_bytes) |
a4fc5ed6 KP |
232 | { |
233 | int i; | |
234 | uint32_t v = 0; | |
235 | ||
236 | if (src_bytes > 4) | |
237 | src_bytes = 4; | |
238 | for (i = 0; i < src_bytes; i++) | |
239 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
240 | return v; | |
241 | } | |
242 | ||
243 | static void | |
244 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
245 | { | |
246 | int i; | |
247 | if (dst_bytes > 4) | |
248 | dst_bytes = 4; | |
249 | for (i = 0; i < dst_bytes; i++) | |
250 | dst[i] = src >> ((3-i) * 8); | |
251 | } | |
252 | ||
fb0f8fbf KP |
253 | /* hrawclock is 1/4 the FSB frequency */ |
254 | static int | |
255 | intel_hrawclk(struct drm_device *dev) | |
256 | { | |
257 | struct drm_i915_private *dev_priv = dev->dev_private; | |
258 | uint32_t clkcfg; | |
259 | ||
9473c8f4 VP |
260 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
261 | if (IS_VALLEYVIEW(dev)) | |
262 | return 200; | |
263 | ||
fb0f8fbf KP |
264 | clkcfg = I915_READ(CLKCFG); |
265 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
266 | case CLKCFG_FSB_400: | |
267 | return 100; | |
268 | case CLKCFG_FSB_533: | |
269 | return 133; | |
270 | case CLKCFG_FSB_667: | |
271 | return 166; | |
272 | case CLKCFG_FSB_800: | |
273 | return 200; | |
274 | case CLKCFG_FSB_1067: | |
275 | return 266; | |
276 | case CLKCFG_FSB_1333: | |
277 | return 333; | |
278 | /* these two are just a guess; one of them might be right */ | |
279 | case CLKCFG_FSB_1600: | |
280 | case CLKCFG_FSB_1600_ALT: | |
281 | return 400; | |
282 | default: | |
283 | return 133; | |
284 | } | |
285 | } | |
286 | ||
bf13e81b JN |
287 | static void |
288 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
36b5f425 | 289 | struct intel_dp *intel_dp); |
bf13e81b JN |
290 | static void |
291 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
36b5f425 | 292 | struct intel_dp *intel_dp); |
bf13e81b | 293 | |
773538e8 VS |
294 | static void pps_lock(struct intel_dp *intel_dp) |
295 | { | |
296 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
297 | struct intel_encoder *encoder = &intel_dig_port->base; | |
298 | struct drm_device *dev = encoder->base.dev; | |
299 | struct drm_i915_private *dev_priv = dev->dev_private; | |
300 | enum intel_display_power_domain power_domain; | |
301 | ||
302 | /* | |
303 | * See vlv_power_sequencer_reset() why we need | |
304 | * a power domain reference here. | |
305 | */ | |
306 | power_domain = intel_display_port_power_domain(encoder); | |
307 | intel_display_power_get(dev_priv, power_domain); | |
308 | ||
309 | mutex_lock(&dev_priv->pps_mutex); | |
310 | } | |
311 | ||
312 | static void pps_unlock(struct intel_dp *intel_dp) | |
313 | { | |
314 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
315 | struct intel_encoder *encoder = &intel_dig_port->base; | |
316 | struct drm_device *dev = encoder->base.dev; | |
317 | struct drm_i915_private *dev_priv = dev->dev_private; | |
318 | enum intel_display_power_domain power_domain; | |
319 | ||
320 | mutex_unlock(&dev_priv->pps_mutex); | |
321 | ||
322 | power_domain = intel_display_port_power_domain(encoder); | |
323 | intel_display_power_put(dev_priv, power_domain); | |
324 | } | |
325 | ||
961a0db0 VS |
326 | static void |
327 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) | |
328 | { | |
329 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
330 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
331 | struct drm_i915_private *dev_priv = dev->dev_private; | |
332 | enum pipe pipe = intel_dp->pps_pipe; | |
d288f65f | 333 | bool pll_enabled; |
961a0db0 VS |
334 | uint32_t DP; |
335 | ||
336 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, | |
337 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", | |
338 | pipe_name(pipe), port_name(intel_dig_port->port))) | |
339 | return; | |
340 | ||
341 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", | |
342 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
343 | ||
344 | /* Preserve the BIOS-computed detected bit. This is | |
345 | * supposed to be read-only. | |
346 | */ | |
347 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
348 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
349 | DP |= DP_PORT_WIDTH(1); | |
350 | DP |= DP_LINK_TRAIN_PAT_1; | |
351 | ||
352 | if (IS_CHERRYVIEW(dev)) | |
353 | DP |= DP_PIPE_SELECT_CHV(pipe); | |
354 | else if (pipe == PIPE_B) | |
355 | DP |= DP_PIPEB_SELECT; | |
356 | ||
d288f65f VS |
357 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
358 | ||
359 | /* | |
360 | * The DPLL for the pipe must be enabled for this to work. | |
361 | * So enable temporarily it if it's not already enabled. | |
362 | */ | |
363 | if (!pll_enabled) | |
364 | vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? | |
365 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll); | |
366 | ||
961a0db0 VS |
367 | /* |
368 | * Similar magic as in intel_dp_enable_port(). | |
369 | * We _must_ do this port enable + disable trick | |
370 | * to make this power seqeuencer lock onto the port. | |
371 | * Otherwise even VDD force bit won't work. | |
372 | */ | |
373 | I915_WRITE(intel_dp->output_reg, DP); | |
374 | POSTING_READ(intel_dp->output_reg); | |
375 | ||
376 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); | |
377 | POSTING_READ(intel_dp->output_reg); | |
378 | ||
379 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); | |
380 | POSTING_READ(intel_dp->output_reg); | |
d288f65f VS |
381 | |
382 | if (!pll_enabled) | |
383 | vlv_force_pll_off(dev, pipe); | |
961a0db0 VS |
384 | } |
385 | ||
bf13e81b JN |
386 | static enum pipe |
387 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
388 | { | |
389 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bf13e81b JN |
390 | struct drm_device *dev = intel_dig_port->base.base.dev; |
391 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4a5d2f8 VS |
392 | struct intel_encoder *encoder; |
393 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); | |
a8c3344e | 394 | enum pipe pipe; |
bf13e81b | 395 | |
e39b999a | 396 | lockdep_assert_held(&dev_priv->pps_mutex); |
bf13e81b | 397 | |
a8c3344e VS |
398 | /* We should never land here with regular DP ports */ |
399 | WARN_ON(!is_edp(intel_dp)); | |
400 | ||
a4a5d2f8 VS |
401 | if (intel_dp->pps_pipe != INVALID_PIPE) |
402 | return intel_dp->pps_pipe; | |
403 | ||
404 | /* | |
405 | * We don't have power sequencer currently. | |
406 | * Pick one that's not used by other ports. | |
407 | */ | |
408 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
409 | base.head) { | |
410 | struct intel_dp *tmp; | |
411 | ||
412 | if (encoder->type != INTEL_OUTPUT_EDP) | |
413 | continue; | |
414 | ||
415 | tmp = enc_to_intel_dp(&encoder->base); | |
416 | ||
417 | if (tmp->pps_pipe != INVALID_PIPE) | |
418 | pipes &= ~(1 << tmp->pps_pipe); | |
419 | } | |
420 | ||
421 | /* | |
422 | * Didn't find one. This should not happen since there | |
423 | * are two power sequencers and up to two eDP ports. | |
424 | */ | |
425 | if (WARN_ON(pipes == 0)) | |
a8c3344e VS |
426 | pipe = PIPE_A; |
427 | else | |
428 | pipe = ffs(pipes) - 1; | |
a4a5d2f8 | 429 | |
a8c3344e VS |
430 | vlv_steal_power_sequencer(dev, pipe); |
431 | intel_dp->pps_pipe = pipe; | |
a4a5d2f8 VS |
432 | |
433 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", | |
434 | pipe_name(intel_dp->pps_pipe), | |
435 | port_name(intel_dig_port->port)); | |
436 | ||
437 | /* init power sequencer on this pipe and port */ | |
36b5f425 VS |
438 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
439 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
a4a5d2f8 | 440 | |
961a0db0 VS |
441 | /* |
442 | * Even vdd force doesn't work until we've made | |
443 | * the power sequencer lock in on the port. | |
444 | */ | |
445 | vlv_power_sequencer_kick(intel_dp); | |
446 | ||
a4a5d2f8 VS |
447 | return intel_dp->pps_pipe; |
448 | } | |
449 | ||
6491ab27 VS |
450 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
451 | enum pipe pipe); | |
452 | ||
453 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, | |
454 | enum pipe pipe) | |
455 | { | |
456 | return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; | |
457 | } | |
458 | ||
459 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, | |
460 | enum pipe pipe) | |
461 | { | |
462 | return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; | |
463 | } | |
464 | ||
465 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, | |
466 | enum pipe pipe) | |
467 | { | |
468 | return true; | |
469 | } | |
bf13e81b | 470 | |
a4a5d2f8 | 471 | static enum pipe |
6491ab27 VS |
472 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
473 | enum port port, | |
474 | vlv_pipe_check pipe_check) | |
a4a5d2f8 VS |
475 | { |
476 | enum pipe pipe; | |
bf13e81b | 477 | |
bf13e81b JN |
478 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
479 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & | |
480 | PANEL_PORT_SELECT_MASK; | |
a4a5d2f8 VS |
481 | |
482 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) | |
483 | continue; | |
484 | ||
6491ab27 VS |
485 | if (!pipe_check(dev_priv, pipe)) |
486 | continue; | |
487 | ||
a4a5d2f8 | 488 | return pipe; |
bf13e81b JN |
489 | } |
490 | ||
a4a5d2f8 VS |
491 | return INVALID_PIPE; |
492 | } | |
493 | ||
494 | static void | |
495 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) | |
496 | { | |
497 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
498 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
499 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4a5d2f8 VS |
500 | enum port port = intel_dig_port->port; |
501 | ||
502 | lockdep_assert_held(&dev_priv->pps_mutex); | |
503 | ||
504 | /* try to find a pipe with this port selected */ | |
6491ab27 VS |
505 | /* first pick one where the panel is on */ |
506 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
507 | vlv_pipe_has_pp_on); | |
508 | /* didn't find one? pick one where vdd is on */ | |
509 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
510 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
511 | vlv_pipe_has_vdd_on); | |
512 | /* didn't find one? pick one with just the correct port */ | |
513 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
514 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
515 | vlv_pipe_any); | |
a4a5d2f8 VS |
516 | |
517 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ | |
518 | if (intel_dp->pps_pipe == INVALID_PIPE) { | |
519 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", | |
520 | port_name(port)); | |
521 | return; | |
bf13e81b JN |
522 | } |
523 | ||
a4a5d2f8 VS |
524 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
525 | port_name(port), pipe_name(intel_dp->pps_pipe)); | |
526 | ||
36b5f425 VS |
527 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
528 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
bf13e81b JN |
529 | } |
530 | ||
773538e8 VS |
531 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
532 | { | |
533 | struct drm_device *dev = dev_priv->dev; | |
534 | struct intel_encoder *encoder; | |
535 | ||
536 | if (WARN_ON(!IS_VALLEYVIEW(dev))) | |
537 | return; | |
538 | ||
539 | /* | |
540 | * We can't grab pps_mutex here due to deadlock with power_domain | |
541 | * mutex when power_domain functions are called while holding pps_mutex. | |
542 | * That also means that in order to use pps_pipe the code needs to | |
543 | * hold both a power domain reference and pps_mutex, and the power domain | |
544 | * reference get/put must be done while _not_ holding pps_mutex. | |
545 | * pps_{lock,unlock}() do these steps in the correct order, so one | |
546 | * should use them always. | |
547 | */ | |
548 | ||
549 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
550 | struct intel_dp *intel_dp; | |
551 | ||
552 | if (encoder->type != INTEL_OUTPUT_EDP) | |
553 | continue; | |
554 | ||
555 | intel_dp = enc_to_intel_dp(&encoder->base); | |
556 | intel_dp->pps_pipe = INVALID_PIPE; | |
557 | } | |
bf13e81b JN |
558 | } |
559 | ||
560 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) | |
561 | { | |
562 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
563 | ||
564 | if (HAS_PCH_SPLIT(dev)) | |
565 | return PCH_PP_CONTROL; | |
566 | else | |
567 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); | |
568 | } | |
569 | ||
570 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) | |
571 | { | |
572 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
573 | ||
574 | if (HAS_PCH_SPLIT(dev)) | |
575 | return PCH_PP_STATUS; | |
576 | else | |
577 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); | |
578 | } | |
579 | ||
01527b31 CT |
580 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
581 | This function only applicable when panel PM state is not to be tracked */ | |
582 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, | |
583 | void *unused) | |
584 | { | |
585 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), | |
586 | edp_notifier); | |
587 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
588 | struct drm_i915_private *dev_priv = dev->dev_private; | |
589 | u32 pp_div; | |
590 | u32 pp_ctrl_reg, pp_div_reg; | |
01527b31 CT |
591 | |
592 | if (!is_edp(intel_dp) || code != SYS_RESTART) | |
593 | return 0; | |
594 | ||
773538e8 | 595 | pps_lock(intel_dp); |
e39b999a | 596 | |
01527b31 | 597 | if (IS_VALLEYVIEW(dev)) { |
e39b999a VS |
598 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
599 | ||
01527b31 CT |
600 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
601 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
602 | pp_div = I915_READ(pp_div_reg); | |
603 | pp_div &= PP_REFERENCE_DIVIDER_MASK; | |
604 | ||
605 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ | |
606 | I915_WRITE(pp_div_reg, pp_div | 0x1F); | |
607 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); | |
608 | msleep(intel_dp->panel_power_cycle_delay); | |
609 | } | |
610 | ||
773538e8 | 611 | pps_unlock(intel_dp); |
e39b999a | 612 | |
01527b31 CT |
613 | return 0; |
614 | } | |
615 | ||
4be73780 | 616 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 617 | { |
30add22d | 618 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
619 | struct drm_i915_private *dev_priv = dev->dev_private; |
620 | ||
e39b999a VS |
621 | lockdep_assert_held(&dev_priv->pps_mutex); |
622 | ||
9a42356b VS |
623 | if (IS_VALLEYVIEW(dev) && |
624 | intel_dp->pps_pipe == INVALID_PIPE) | |
625 | return false; | |
626 | ||
bf13e81b | 627 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
628 | } |
629 | ||
4be73780 | 630 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 631 | { |
30add22d | 632 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
633 | struct drm_i915_private *dev_priv = dev->dev_private; |
634 | ||
e39b999a VS |
635 | lockdep_assert_held(&dev_priv->pps_mutex); |
636 | ||
9a42356b VS |
637 | if (IS_VALLEYVIEW(dev) && |
638 | intel_dp->pps_pipe == INVALID_PIPE) | |
639 | return false; | |
640 | ||
773538e8 | 641 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
ebf33b18 KP |
642 | } |
643 | ||
9b984dae KP |
644 | static void |
645 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
646 | { | |
30add22d | 647 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9b984dae | 648 | struct drm_i915_private *dev_priv = dev->dev_private; |
ebf33b18 | 649 | |
9b984dae KP |
650 | if (!is_edp(intel_dp)) |
651 | return; | |
453c5420 | 652 | |
4be73780 | 653 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
654 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
655 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
656 | I915_READ(_pp_stat_reg(intel_dp)), |
657 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
658 | } |
659 | } | |
660 | ||
9ee32fea DV |
661 | static uint32_t |
662 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
663 | { | |
664 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
665 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
666 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9ed35ab1 | 667 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
668 | uint32_t status; |
669 | bool done; | |
670 | ||
ef04f00d | 671 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 672 | if (has_aux_irq) |
b18ac466 | 673 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 674 | msecs_to_jiffies_timeout(10)); |
9ee32fea DV |
675 | else |
676 | done = wait_for_atomic(C, 10) == 0; | |
677 | if (!done) | |
678 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
679 | has_aux_irq); | |
680 | #undef C | |
681 | ||
682 | return status; | |
683 | } | |
684 | ||
ec5b01dd | 685 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 686 | { |
174edf1f PZ |
687 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
688 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
9ee32fea | 689 | |
ec5b01dd DL |
690 | /* |
691 | * The clock divider is based off the hrawclk, and would like to run at | |
692 | * 2MHz. So, take the hrawclk value and divide by 2 and use that | |
a4fc5ed6 | 693 | */ |
ec5b01dd DL |
694 | return index ? 0 : intel_hrawclk(dev) / 2; |
695 | } | |
696 | ||
697 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
698 | { | |
699 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
700 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
701 | ||
702 | if (index) | |
703 | return 0; | |
704 | ||
705 | if (intel_dig_port->port == PORT_A) { | |
706 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
b84a1cf8 | 707 | return 200; /* SNB & IVB eDP input clock at 400Mhz */ |
e3421a18 | 708 | else |
b84a1cf8 | 709 | return 225; /* eDP input clock at 450Mhz */ |
ec5b01dd DL |
710 | } else { |
711 | return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); | |
712 | } | |
713 | } | |
714 | ||
715 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
716 | { | |
717 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
718 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
719 | struct drm_i915_private *dev_priv = dev->dev_private; | |
720 | ||
721 | if (intel_dig_port->port == PORT_A) { | |
722 | if (index) | |
723 | return 0; | |
724 | return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); | |
2c55c336 JN |
725 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
726 | /* Workaround for non-ULT HSW */ | |
bc86625a CW |
727 | switch (index) { |
728 | case 0: return 63; | |
729 | case 1: return 72; | |
730 | default: return 0; | |
731 | } | |
ec5b01dd | 732 | } else { |
bc86625a | 733 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
2c55c336 | 734 | } |
b84a1cf8 RV |
735 | } |
736 | ||
ec5b01dd DL |
737 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
738 | { | |
739 | return index ? 0 : 100; | |
740 | } | |
741 | ||
b6b5e383 DL |
742 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
743 | { | |
744 | /* | |
745 | * SKL doesn't need us to program the AUX clock divider (Hardware will | |
746 | * derive the clock from CDCLK automatically). We still implement the | |
747 | * get_aux_clock_divider vfunc to plug-in into the existing code. | |
748 | */ | |
749 | return index ? 0 : 1; | |
750 | } | |
751 | ||
5ed12a19 DL |
752 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
753 | bool has_aux_irq, | |
754 | int send_bytes, | |
755 | uint32_t aux_clock_divider) | |
756 | { | |
757 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
758 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
759 | uint32_t precharge, timeout; | |
760 | ||
761 | if (IS_GEN6(dev)) | |
762 | precharge = 3; | |
763 | else | |
764 | precharge = 5; | |
765 | ||
766 | if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) | |
767 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; | |
768 | else | |
769 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
770 | ||
771 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 772 | DP_AUX_CH_CTL_DONE | |
5ed12a19 | 773 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
788d4433 | 774 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 775 | timeout | |
788d4433 | 776 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
777 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
778 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 779 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
780 | } |
781 | ||
b9ca5fad DL |
782 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
783 | bool has_aux_irq, | |
784 | int send_bytes, | |
785 | uint32_t unused) | |
786 | { | |
787 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788 | DP_AUX_CH_CTL_DONE | | |
789 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | | |
790 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
791 | DP_AUX_CH_CTL_TIME_OUT_1600us | | |
792 | DP_AUX_CH_CTL_RECEIVE_ERROR | | |
793 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
794 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); | |
795 | } | |
796 | ||
b84a1cf8 RV |
797 | static int |
798 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
bd9f74a5 | 799 | const uint8_t *send, int send_bytes, |
b84a1cf8 RV |
800 | uint8_t *recv, int recv_size) |
801 | { | |
802 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
803 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
804 | struct drm_i915_private *dev_priv = dev->dev_private; | |
805 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; | |
806 | uint32_t ch_data = ch_ctl + 4; | |
bc86625a | 807 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
808 | int i, ret, recv_bytes; |
809 | uint32_t status; | |
5ed12a19 | 810 | int try, clock = 0; |
4e6b788c | 811 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
884f19e9 JN |
812 | bool vdd; |
813 | ||
773538e8 | 814 | pps_lock(intel_dp); |
e39b999a | 815 | |
72c3500a VS |
816 | /* |
817 | * We will be called with VDD already enabled for dpcd/edid/oui reads. | |
818 | * In such cases we want to leave VDD enabled and it's up to upper layers | |
819 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off | |
820 | * ourselves. | |
821 | */ | |
1e0560e0 | 822 | vdd = edp_panel_vdd_on(intel_dp); |
b84a1cf8 RV |
823 | |
824 | /* dp aux is extremely sensitive to irq latency, hence request the | |
825 | * lowest possible wakeup latency and so prevent the cpu from going into | |
826 | * deep sleep states. | |
827 | */ | |
828 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
829 | ||
830 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 831 | |
c67a470b PZ |
832 | intel_aux_display_runtime_get(dev_priv); |
833 | ||
11bee43e JB |
834 | /* Try to wait for any previous AUX channel activity */ |
835 | for (try = 0; try < 3; try++) { | |
ef04f00d | 836 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
837 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
838 | break; | |
839 | msleep(1); | |
840 | } | |
841 | ||
842 | if (try == 3) { | |
843 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
844 | I915_READ(ch_ctl)); | |
9ee32fea DV |
845 | ret = -EBUSY; |
846 | goto out; | |
4f7f7b7e CW |
847 | } |
848 | ||
46a5ae9f PZ |
849 | /* Only 5 data registers! */ |
850 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
851 | ret = -E2BIG; | |
852 | goto out; | |
853 | } | |
854 | ||
ec5b01dd | 855 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
153b1100 DL |
856 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
857 | has_aux_irq, | |
858 | send_bytes, | |
859 | aux_clock_divider); | |
5ed12a19 | 860 | |
bc86625a CW |
861 | /* Must try at least 3 times according to DP spec */ |
862 | for (try = 0; try < 5; try++) { | |
863 | /* Load the send data into the aux channel data registers */ | |
864 | for (i = 0; i < send_bytes; i += 4) | |
865 | I915_WRITE(ch_data + i, | |
866 | pack_aux(send + i, send_bytes - i)); | |
867 | ||
868 | /* Send the command and wait for it to complete */ | |
5ed12a19 | 869 | I915_WRITE(ch_ctl, send_ctl); |
bc86625a CW |
870 | |
871 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
872 | ||
873 | /* Clear done status and any errors */ | |
874 | I915_WRITE(ch_ctl, | |
875 | status | | |
876 | DP_AUX_CH_CTL_DONE | | |
877 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
878 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
879 | ||
880 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
881 | DP_AUX_CH_CTL_RECEIVE_ERROR)) | |
882 | continue; | |
883 | if (status & DP_AUX_CH_CTL_DONE) | |
884 | break; | |
885 | } | |
4f7f7b7e | 886 | if (status & DP_AUX_CH_CTL_DONE) |
a4fc5ed6 KP |
887 | break; |
888 | } | |
889 | ||
a4fc5ed6 | 890 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 891 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
892 | ret = -EBUSY; |
893 | goto out; | |
a4fc5ed6 KP |
894 | } |
895 | ||
896 | /* Check for timeout or receive error. | |
897 | * Timeouts occur when the sink is not connected | |
898 | */ | |
a5b3da54 | 899 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 900 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
901 | ret = -EIO; |
902 | goto out; | |
a5b3da54 | 903 | } |
1ae8c0a5 KP |
904 | |
905 | /* Timeouts occur when the device isn't connected, so they're | |
906 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 907 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 908 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
909 | ret = -ETIMEDOUT; |
910 | goto out; | |
a4fc5ed6 KP |
911 | } |
912 | ||
913 | /* Unload any bytes sent back from the other side */ | |
914 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
915 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
916 | if (recv_bytes > recv_size) |
917 | recv_bytes = recv_size; | |
0206e353 | 918 | |
4f7f7b7e CW |
919 | for (i = 0; i < recv_bytes; i += 4) |
920 | unpack_aux(I915_READ(ch_data + i), | |
921 | recv + i, recv_bytes - i); | |
a4fc5ed6 | 922 | |
9ee32fea DV |
923 | ret = recv_bytes; |
924 | out: | |
925 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
c67a470b | 926 | intel_aux_display_runtime_put(dev_priv); |
9ee32fea | 927 | |
884f19e9 JN |
928 | if (vdd) |
929 | edp_panel_vdd_off(intel_dp, false); | |
930 | ||
773538e8 | 931 | pps_unlock(intel_dp); |
e39b999a | 932 | |
9ee32fea | 933 | return ret; |
a4fc5ed6 KP |
934 | } |
935 | ||
a6c8aff0 JN |
936 | #define BARE_ADDRESS_SIZE 3 |
937 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
9d1a1031 JN |
938 | static ssize_t |
939 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 940 | { |
9d1a1031 JN |
941 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
942 | uint8_t txbuf[20], rxbuf[20]; | |
943 | size_t txsize, rxsize; | |
a4fc5ed6 | 944 | int ret; |
a4fc5ed6 | 945 | |
9d1a1031 JN |
946 | txbuf[0] = msg->request << 4; |
947 | txbuf[1] = msg->address >> 8; | |
948 | txbuf[2] = msg->address & 0xff; | |
949 | txbuf[3] = msg->size - 1; | |
46a5ae9f | 950 | |
9d1a1031 JN |
951 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
952 | case DP_AUX_NATIVE_WRITE: | |
953 | case DP_AUX_I2C_WRITE: | |
a6c8aff0 | 954 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
9d1a1031 | 955 | rxsize = 1; |
f51a44b9 | 956 | |
9d1a1031 JN |
957 | if (WARN_ON(txsize > 20)) |
958 | return -E2BIG; | |
a4fc5ed6 | 959 | |
9d1a1031 | 960 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
a4fc5ed6 | 961 | |
9d1a1031 JN |
962 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
963 | if (ret > 0) { | |
964 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 965 | |
9d1a1031 JN |
966 | /* Return payload size. */ |
967 | ret = msg->size; | |
968 | } | |
969 | break; | |
46a5ae9f | 970 | |
9d1a1031 JN |
971 | case DP_AUX_NATIVE_READ: |
972 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 973 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 974 | rxsize = msg->size + 1; |
a4fc5ed6 | 975 | |
9d1a1031 JN |
976 | if (WARN_ON(rxsize > 20)) |
977 | return -E2BIG; | |
a4fc5ed6 | 978 | |
9d1a1031 JN |
979 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
980 | if (ret > 0) { | |
981 | msg->reply = rxbuf[0] >> 4; | |
982 | /* | |
983 | * Assume happy day, and copy the data. The caller is | |
984 | * expected to check msg->reply before touching it. | |
985 | * | |
986 | * Return payload size. | |
987 | */ | |
988 | ret--; | |
989 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 990 | } |
9d1a1031 JN |
991 | break; |
992 | ||
993 | default: | |
994 | ret = -EINVAL; | |
995 | break; | |
a4fc5ed6 | 996 | } |
f51a44b9 | 997 | |
9d1a1031 | 998 | return ret; |
a4fc5ed6 KP |
999 | } |
1000 | ||
9d1a1031 JN |
1001 | static void |
1002 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) | |
1003 | { | |
1004 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
33ad6626 JN |
1005 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1006 | enum port port = intel_dig_port->port; | |
0b99836f | 1007 | const char *name = NULL; |
ab2c0672 DA |
1008 | int ret; |
1009 | ||
33ad6626 JN |
1010 | switch (port) { |
1011 | case PORT_A: | |
1012 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; | |
0b99836f | 1013 | name = "DPDDC-A"; |
ab2c0672 | 1014 | break; |
33ad6626 JN |
1015 | case PORT_B: |
1016 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; | |
0b99836f | 1017 | name = "DPDDC-B"; |
ab2c0672 | 1018 | break; |
33ad6626 JN |
1019 | case PORT_C: |
1020 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; | |
0b99836f | 1021 | name = "DPDDC-C"; |
ab2c0672 | 1022 | break; |
33ad6626 JN |
1023 | case PORT_D: |
1024 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; | |
0b99836f | 1025 | name = "DPDDC-D"; |
33ad6626 JN |
1026 | break; |
1027 | default: | |
1028 | BUG(); | |
ab2c0672 DA |
1029 | } |
1030 | ||
1b1aad75 DL |
1031 | /* |
1032 | * The AUX_CTL register is usually DP_CTL + 0x10. | |
1033 | * | |
1034 | * On Haswell and Broadwell though: | |
1035 | * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU | |
1036 | * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU | |
1037 | * | |
1038 | * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU. | |
1039 | */ | |
1040 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) | |
33ad6626 | 1041 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
8316f337 | 1042 | |
0b99836f | 1043 | intel_dp->aux.name = name; |
9d1a1031 JN |
1044 | intel_dp->aux.dev = dev->dev; |
1045 | intel_dp->aux.transfer = intel_dp_aux_transfer; | |
8316f337 | 1046 | |
0b99836f JN |
1047 | DRM_DEBUG_KMS("registering %s bus for %s\n", name, |
1048 | connector->base.kdev->kobj.name); | |
8316f337 | 1049 | |
4f71d0cb | 1050 | ret = drm_dp_aux_register(&intel_dp->aux); |
0b99836f | 1051 | if (ret < 0) { |
4f71d0cb | 1052 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
0b99836f JN |
1053 | name, ret); |
1054 | return; | |
ab2c0672 | 1055 | } |
8a5e6aeb | 1056 | |
0b99836f JN |
1057 | ret = sysfs_create_link(&connector->base.kdev->kobj, |
1058 | &intel_dp->aux.ddc.dev.kobj, | |
1059 | intel_dp->aux.ddc.dev.kobj.name); | |
1060 | if (ret < 0) { | |
1061 | DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret); | |
4f71d0cb | 1062 | drm_dp_aux_unregister(&intel_dp->aux); |
ab2c0672 | 1063 | } |
a4fc5ed6 KP |
1064 | } |
1065 | ||
80f65de3 ID |
1066 | static void |
1067 | intel_dp_connector_unregister(struct intel_connector *intel_connector) | |
1068 | { | |
1069 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); | |
1070 | ||
0e32b39c DA |
1071 | if (!intel_connector->mst_port) |
1072 | sysfs_remove_link(&intel_connector->base.kdev->kobj, | |
1073 | intel_dp->aux.ddc.dev.kobj.name); | |
80f65de3 ID |
1074 | intel_connector_unregister(intel_connector); |
1075 | } | |
1076 | ||
0e50338c DV |
1077 | static void |
1078 | hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw) | |
1079 | { | |
1080 | switch (link_bw) { | |
1081 | case DP_LINK_BW_1_62: | |
1082 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; | |
1083 | break; | |
1084 | case DP_LINK_BW_2_7: | |
1085 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; | |
1086 | break; | |
1087 | case DP_LINK_BW_5_4: | |
1088 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; | |
1089 | break; | |
1090 | } | |
1091 | } | |
1092 | ||
c6bb3538 DV |
1093 | static void |
1094 | intel_dp_set_clock(struct intel_encoder *encoder, | |
1095 | struct intel_crtc_config *pipe_config, int link_bw) | |
1096 | { | |
1097 | struct drm_device *dev = encoder->base.dev; | |
9dd4ffdf CML |
1098 | const struct dp_link_dpll *divisor = NULL; |
1099 | int i, count = 0; | |
c6bb3538 DV |
1100 | |
1101 | if (IS_G4X(dev)) { | |
9dd4ffdf CML |
1102 | divisor = gen4_dpll; |
1103 | count = ARRAY_SIZE(gen4_dpll); | |
c6bb3538 | 1104 | } else if (HAS_PCH_SPLIT(dev)) { |
9dd4ffdf CML |
1105 | divisor = pch_dpll; |
1106 | count = ARRAY_SIZE(pch_dpll); | |
ef9348c8 CML |
1107 | } else if (IS_CHERRYVIEW(dev)) { |
1108 | divisor = chv_dpll; | |
1109 | count = ARRAY_SIZE(chv_dpll); | |
c6bb3538 | 1110 | } else if (IS_VALLEYVIEW(dev)) { |
65ce4bf5 CML |
1111 | divisor = vlv_dpll; |
1112 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 1113 | } |
9dd4ffdf CML |
1114 | |
1115 | if (divisor && count) { | |
1116 | for (i = 0; i < count; i++) { | |
1117 | if (link_bw == divisor[i].link_bw) { | |
1118 | pipe_config->dpll = divisor[i].dpll; | |
1119 | pipe_config->clock_set = true; | |
1120 | break; | |
1121 | } | |
1122 | } | |
c6bb3538 DV |
1123 | } |
1124 | } | |
1125 | ||
00c09d70 | 1126 | bool |
5bfe2ac0 DV |
1127 | intel_dp_compute_config(struct intel_encoder *encoder, |
1128 | struct intel_crtc_config *pipe_config) | |
a4fc5ed6 | 1129 | { |
5bfe2ac0 | 1130 | struct drm_device *dev = encoder->base.dev; |
36008365 | 1131 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfe2ac0 | 1132 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
5bfe2ac0 | 1133 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1134 | enum port port = dp_to_dig_port(intel_dp)->port; |
2dd24552 | 1135 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
dd06f90e | 1136 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
a4fc5ed6 | 1137 | int lane_count, clock; |
56071a20 | 1138 | int min_lane_count = 1; |
eeb6324d | 1139 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
06ea66b6 | 1140 | /* Conveniently, the link BW constants become indices with a shift...*/ |
56071a20 | 1141 | int min_clock = 0; |
06ea66b6 | 1142 | int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; |
083f9560 | 1143 | int bpp, mode_rate; |
06ea66b6 | 1144 | static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; |
ff9a6750 | 1145 | int link_avail, link_clock; |
a4fc5ed6 | 1146 | |
bc7d38a4 | 1147 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
5bfe2ac0 DV |
1148 | pipe_config->has_pch_encoder = true; |
1149 | ||
03afc4a2 | 1150 | pipe_config->has_dp_encoder = true; |
f769cd24 | 1151 | pipe_config->has_drrs = false; |
9ed109a7 | 1152 | pipe_config->has_audio = intel_dp->has_audio; |
a4fc5ed6 | 1153 | |
dd06f90e JN |
1154 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
1155 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
1156 | adjusted_mode); | |
2dd24552 JB |
1157 | if (!HAS_PCH_SPLIT(dev)) |
1158 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
1159 | intel_connector->panel.fitting_mode); | |
1160 | else | |
b074cec8 JB |
1161 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
1162 | intel_connector->panel.fitting_mode); | |
0d3a1bee ZY |
1163 | } |
1164 | ||
cb1793ce | 1165 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
1166 | return false; |
1167 | ||
083f9560 DV |
1168 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
1169 | "max bw %02x pixel clock %iKHz\n", | |
241bfc38 DL |
1170 | max_lane_count, bws[max_clock], |
1171 | adjusted_mode->crtc_clock); | |
083f9560 | 1172 | |
36008365 DV |
1173 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1174 | * bpc in between. */ | |
3e7ca985 | 1175 | bpp = pipe_config->pipe_bpp; |
56071a20 JN |
1176 | if (is_edp(intel_dp)) { |
1177 | if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) { | |
1178 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", | |
1179 | dev_priv->vbt.edp_bpp); | |
1180 | bpp = dev_priv->vbt.edp_bpp; | |
1181 | } | |
1182 | ||
344c5bbc JN |
1183 | /* |
1184 | * Use the maximum clock and number of lanes the eDP panel | |
1185 | * advertizes being capable of. The panels are generally | |
1186 | * designed to support only a single clock and lane | |
1187 | * configuration, and typically these values correspond to the | |
1188 | * native resolution of the panel. | |
1189 | */ | |
1190 | min_lane_count = max_lane_count; | |
1191 | min_clock = max_clock; | |
7984211e | 1192 | } |
657445fe | 1193 | |
36008365 | 1194 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
1195 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1196 | bpp); | |
36008365 | 1197 | |
c6930992 DA |
1198 | for (clock = min_clock; clock <= max_clock; clock++) { |
1199 | for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) { | |
36008365 DV |
1200 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); |
1201 | link_avail = intel_dp_max_data_rate(link_clock, | |
1202 | lane_count); | |
1203 | ||
1204 | if (mode_rate <= link_avail) { | |
1205 | goto found; | |
1206 | } | |
1207 | } | |
1208 | } | |
1209 | } | |
c4867936 | 1210 | |
36008365 | 1211 | return false; |
3685a8f3 | 1212 | |
36008365 | 1213 | found: |
55bc60db VS |
1214 | if (intel_dp->color_range_auto) { |
1215 | /* | |
1216 | * See: | |
1217 | * CEA-861-E - 5.1 Default Encoding Parameters | |
1218 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
1219 | */ | |
18316c8c | 1220 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
55bc60db VS |
1221 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
1222 | else | |
1223 | intel_dp->color_range = 0; | |
1224 | } | |
1225 | ||
3685a8f3 | 1226 | if (intel_dp->color_range) |
50f3b016 | 1227 | pipe_config->limited_color_range = true; |
a4fc5ed6 | 1228 | |
36008365 DV |
1229 | intel_dp->link_bw = bws[clock]; |
1230 | intel_dp->lane_count = lane_count; | |
657445fe | 1231 | pipe_config->pipe_bpp = bpp; |
ff9a6750 | 1232 | pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
a4fc5ed6 | 1233 | |
36008365 DV |
1234 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
1235 | intel_dp->link_bw, intel_dp->lane_count, | |
ff9a6750 | 1236 | pipe_config->port_clock, bpp); |
36008365 DV |
1237 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1238 | mode_rate, link_avail); | |
a4fc5ed6 | 1239 | |
03afc4a2 | 1240 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
1241 | adjusted_mode->crtc_clock, |
1242 | pipe_config->port_clock, | |
03afc4a2 | 1243 | &pipe_config->dp_m_n); |
9d1a455b | 1244 | |
439d7ac0 PB |
1245 | if (intel_connector->panel.downclock_mode != NULL && |
1246 | intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { | |
f769cd24 | 1247 | pipe_config->has_drrs = true; |
439d7ac0 PB |
1248 | intel_link_compute_m_n(bpp, lane_count, |
1249 | intel_connector->panel.downclock_mode->clock, | |
1250 | pipe_config->port_clock, | |
1251 | &pipe_config->dp_m2_n2); | |
1252 | } | |
1253 | ||
ea155f32 | 1254 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
0e50338c DV |
1255 | hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); |
1256 | else | |
1257 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); | |
c6bb3538 | 1258 | |
03afc4a2 | 1259 | return true; |
a4fc5ed6 KP |
1260 | } |
1261 | ||
7c62a164 | 1262 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
ea9b6006 | 1263 | { |
7c62a164 DV |
1264 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1265 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); | |
1266 | struct drm_device *dev = crtc->base.dev; | |
ea9b6006 DV |
1267 | struct drm_i915_private *dev_priv = dev->dev_private; |
1268 | u32 dpa_ctl; | |
1269 | ||
ff9a6750 | 1270 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); |
ea9b6006 DV |
1271 | dpa_ctl = I915_READ(DP_A); |
1272 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
1273 | ||
ff9a6750 | 1274 | if (crtc->config.port_clock == 162000) { |
1ce17038 DV |
1275 | /* For a long time we've carried around a ILK-DevA w/a for the |
1276 | * 160MHz clock. If we're really unlucky, it's still required. | |
1277 | */ | |
1278 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); | |
ea9b6006 | 1279 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
7c62a164 | 1280 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
ea9b6006 DV |
1281 | } else { |
1282 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
7c62a164 | 1283 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
ea9b6006 | 1284 | } |
1ce17038 | 1285 | |
ea9b6006 DV |
1286 | I915_WRITE(DP_A, dpa_ctl); |
1287 | ||
1288 | POSTING_READ(DP_A); | |
1289 | udelay(500); | |
1290 | } | |
1291 | ||
8ac33ed3 | 1292 | static void intel_dp_prepare(struct intel_encoder *encoder) |
a4fc5ed6 | 1293 | { |
b934223d | 1294 | struct drm_device *dev = encoder->base.dev; |
417e822d | 1295 | struct drm_i915_private *dev_priv = dev->dev_private; |
b934223d | 1296 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1297 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d DV |
1298 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1299 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
a4fc5ed6 | 1300 | |
417e822d | 1301 | /* |
1a2eb460 | 1302 | * There are four kinds of DP registers: |
417e822d KP |
1303 | * |
1304 | * IBX PCH | |
1a2eb460 KP |
1305 | * SNB CPU |
1306 | * IVB CPU | |
417e822d KP |
1307 | * CPT PCH |
1308 | * | |
1309 | * IBX PCH and CPU are the same for almost everything, | |
1310 | * except that the CPU DP PLL is configured in this | |
1311 | * register | |
1312 | * | |
1313 | * CPT PCH is quite different, having many bits moved | |
1314 | * to the TRANS_DP_CTL register instead. That | |
1315 | * configuration happens (oddly) in ironlake_pch_enable | |
1316 | */ | |
9c9e7927 | 1317 | |
417e822d KP |
1318 | /* Preserve the BIOS-computed detected bit. This is |
1319 | * supposed to be read-only. | |
1320 | */ | |
1321 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 1322 | |
417e822d | 1323 | /* Handle DP bits in common between all three register formats */ |
417e822d | 1324 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
17aa6be9 | 1325 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
a4fc5ed6 | 1326 | |
c1dec79a | 1327 | if (crtc->config.has_audio) |
ea5b213a | 1328 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
247d89f6 | 1329 | |
417e822d | 1330 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 1331 | |
bc7d38a4 | 1332 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
1a2eb460 KP |
1333 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1334 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1335 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1336 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1337 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
1338 | ||
6aba5b6c | 1339 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
1340 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1341 | ||
7c62a164 | 1342 | intel_dp->DP |= crtc->pipe << 29; |
bc7d38a4 | 1343 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
b2634017 | 1344 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) |
3685a8f3 | 1345 | intel_dp->DP |= intel_dp->color_range; |
417e822d KP |
1346 | |
1347 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
1348 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1349 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1350 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1351 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
1352 | ||
6aba5b6c | 1353 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
1354 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1355 | ||
44f37d1f CML |
1356 | if (!IS_CHERRYVIEW(dev)) { |
1357 | if (crtc->pipe == 1) | |
1358 | intel_dp->DP |= DP_PIPEB_SELECT; | |
1359 | } else { | |
1360 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); | |
1361 | } | |
417e822d KP |
1362 | } else { |
1363 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
32f9d658 | 1364 | } |
a4fc5ed6 KP |
1365 | } |
1366 | ||
ffd6749d PZ |
1367 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1368 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 1369 | |
1a5ef5b7 PZ |
1370 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1371 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 1372 | |
ffd6749d PZ |
1373 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1374 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 1375 | |
4be73780 | 1376 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
1377 | u32 mask, |
1378 | u32 value) | |
bd943159 | 1379 | { |
30add22d | 1380 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
99ea7127 | 1381 | struct drm_i915_private *dev_priv = dev->dev_private; |
453c5420 JB |
1382 | u32 pp_stat_reg, pp_ctrl_reg; |
1383 | ||
e39b999a VS |
1384 | lockdep_assert_held(&dev_priv->pps_mutex); |
1385 | ||
bf13e81b JN |
1386 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1387 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 1388 | |
99ea7127 | 1389 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
1390 | mask, value, |
1391 | I915_READ(pp_stat_reg), | |
1392 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1393 | |
453c5420 | 1394 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
99ea7127 | 1395 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
1396 | I915_READ(pp_stat_reg), |
1397 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1398 | } |
54c136d4 CW |
1399 | |
1400 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 1401 | } |
32ce697c | 1402 | |
4be73780 | 1403 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
1404 | { |
1405 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 1406 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
1407 | } |
1408 | ||
4be73780 | 1409 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
1410 | { |
1411 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 1412 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
1413 | } |
1414 | ||
4be73780 | 1415 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 KP |
1416 | { |
1417 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); | |
dce56b3c PZ |
1418 | |
1419 | /* When we disable the VDD override bit last we have to do the manual | |
1420 | * wait. */ | |
1421 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, | |
1422 | intel_dp->panel_power_cycle_delay); | |
1423 | ||
4be73780 | 1424 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
1425 | } |
1426 | ||
4be73780 | 1427 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
1428 | { |
1429 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
1430 | intel_dp->backlight_on_delay); | |
1431 | } | |
1432 | ||
4be73780 | 1433 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
1434 | { |
1435 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
1436 | intel_dp->backlight_off_delay); | |
1437 | } | |
99ea7127 | 1438 | |
832dd3c1 KP |
1439 | /* Read the current pp_control value, unlocking the register if it |
1440 | * is locked | |
1441 | */ | |
1442 | ||
453c5420 | 1443 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 1444 | { |
453c5420 JB |
1445 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1446 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1447 | u32 control; | |
832dd3c1 | 1448 | |
e39b999a VS |
1449 | lockdep_assert_held(&dev_priv->pps_mutex); |
1450 | ||
bf13e81b | 1451 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
832dd3c1 KP |
1452 | control &= ~PANEL_UNLOCK_MASK; |
1453 | control |= PANEL_UNLOCK_REGS; | |
1454 | return control; | |
bd943159 KP |
1455 | } |
1456 | ||
951468f3 VS |
1457 | /* |
1458 | * Must be paired with edp_panel_vdd_off(). | |
1459 | * Must hold pps_mutex around the whole on/off sequence. | |
1460 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
1461 | */ | |
1e0560e0 | 1462 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 1463 | { |
30add22d | 1464 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4e6e1a54 ID |
1465 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1466 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
5d613501 | 1467 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e6e1a54 | 1468 | enum intel_display_power_domain power_domain; |
5d613501 | 1469 | u32 pp; |
453c5420 | 1470 | u32 pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 1471 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 1472 | |
e39b999a VS |
1473 | lockdep_assert_held(&dev_priv->pps_mutex); |
1474 | ||
97af61f5 | 1475 | if (!is_edp(intel_dp)) |
adddaaf4 | 1476 | return false; |
bd943159 KP |
1477 | |
1478 | intel_dp->want_panel_vdd = true; | |
99ea7127 | 1479 | |
4be73780 | 1480 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 1481 | return need_to_disable; |
b0665d57 | 1482 | |
4e6e1a54 ID |
1483 | power_domain = intel_display_port_power_domain(intel_encoder); |
1484 | intel_display_power_get(dev_priv, power_domain); | |
e9cb81a2 | 1485 | |
3936fcf4 VS |
1486 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
1487 | port_name(intel_dig_port->port)); | |
bd943159 | 1488 | |
4be73780 DV |
1489 | if (!edp_have_panel_power(intel_dp)) |
1490 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 1491 | |
453c5420 | 1492 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 1493 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 1494 | |
bf13e81b JN |
1495 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1496 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
1497 | |
1498 | I915_WRITE(pp_ctrl_reg, pp); | |
1499 | POSTING_READ(pp_ctrl_reg); | |
1500 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1501 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
1502 | /* |
1503 | * If the panel wasn't on, delay before accessing aux channel | |
1504 | */ | |
4be73780 | 1505 | if (!edp_have_panel_power(intel_dp)) { |
3936fcf4 VS |
1506 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
1507 | port_name(intel_dig_port->port)); | |
f01eca2e | 1508 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 1509 | } |
adddaaf4 JN |
1510 | |
1511 | return need_to_disable; | |
1512 | } | |
1513 | ||
951468f3 VS |
1514 | /* |
1515 | * Must be paired with intel_edp_panel_vdd_off() or | |
1516 | * intel_edp_panel_off(). | |
1517 | * Nested calls to these functions are not allowed since | |
1518 | * we drop the lock. Caller must use some higher level | |
1519 | * locking to prevent nested calls from other threads. | |
1520 | */ | |
b80d6c78 | 1521 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 | 1522 | { |
c695b6b6 | 1523 | bool vdd; |
adddaaf4 | 1524 | |
c695b6b6 VS |
1525 | if (!is_edp(intel_dp)) |
1526 | return; | |
1527 | ||
773538e8 | 1528 | pps_lock(intel_dp); |
c695b6b6 | 1529 | vdd = edp_panel_vdd_on(intel_dp); |
773538e8 | 1530 | pps_unlock(intel_dp); |
c695b6b6 | 1531 | |
3936fcf4 VS |
1532 | WARN(!vdd, "eDP port %c VDD already requested on\n", |
1533 | port_name(dp_to_dig_port(intel_dp)->port)); | |
5d613501 JB |
1534 | } |
1535 | ||
4be73780 | 1536 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 1537 | { |
30add22d | 1538 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5d613501 | 1539 | struct drm_i915_private *dev_priv = dev->dev_private; |
be2c9196 VS |
1540 | struct intel_digital_port *intel_dig_port = |
1541 | dp_to_dig_port(intel_dp); | |
1542 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1543 | enum intel_display_power_domain power_domain; | |
5d613501 | 1544 | u32 pp; |
453c5420 | 1545 | u32 pp_stat_reg, pp_ctrl_reg; |
5d613501 | 1546 | |
e39b999a | 1547 | lockdep_assert_held(&dev_priv->pps_mutex); |
a0e99e68 | 1548 | |
15e899a0 | 1549 | WARN_ON(intel_dp->want_panel_vdd); |
4e6e1a54 | 1550 | |
15e899a0 | 1551 | if (!edp_have_panel_vdd(intel_dp)) |
be2c9196 | 1552 | return; |
b0665d57 | 1553 | |
3936fcf4 VS |
1554 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
1555 | port_name(intel_dig_port->port)); | |
bd943159 | 1556 | |
be2c9196 VS |
1557 | pp = ironlake_get_pp_control(intel_dp); |
1558 | pp &= ~EDP_FORCE_VDD; | |
453c5420 | 1559 | |
be2c9196 VS |
1560 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1561 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
99ea7127 | 1562 | |
be2c9196 VS |
1563 | I915_WRITE(pp_ctrl_reg, pp); |
1564 | POSTING_READ(pp_ctrl_reg); | |
90791a5c | 1565 | |
be2c9196 VS |
1566 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1567 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1568 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
e9cb81a2 | 1569 | |
be2c9196 VS |
1570 | if ((pp & POWER_TARGET_ON) == 0) |
1571 | intel_dp->last_power_cycle = jiffies; | |
e9cb81a2 | 1572 | |
be2c9196 VS |
1573 | power_domain = intel_display_port_power_domain(intel_encoder); |
1574 | intel_display_power_put(dev_priv, power_domain); | |
bd943159 | 1575 | } |
5d613501 | 1576 | |
4be73780 | 1577 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
1578 | { |
1579 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
1580 | struct intel_dp, panel_vdd_work); | |
bd943159 | 1581 | |
773538e8 | 1582 | pps_lock(intel_dp); |
15e899a0 VS |
1583 | if (!intel_dp->want_panel_vdd) |
1584 | edp_panel_vdd_off_sync(intel_dp); | |
773538e8 | 1585 | pps_unlock(intel_dp); |
bd943159 KP |
1586 | } |
1587 | ||
aba86890 ID |
1588 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
1589 | { | |
1590 | unsigned long delay; | |
1591 | ||
1592 | /* | |
1593 | * Queue the timer to fire a long time from now (relative to the power | |
1594 | * down delay) to keep the panel power up across a sequence of | |
1595 | * operations. | |
1596 | */ | |
1597 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); | |
1598 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); | |
1599 | } | |
1600 | ||
951468f3 VS |
1601 | /* |
1602 | * Must be paired with edp_panel_vdd_on(). | |
1603 | * Must hold pps_mutex around the whole on/off sequence. | |
1604 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
1605 | */ | |
4be73780 | 1606 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 1607 | { |
e39b999a VS |
1608 | struct drm_i915_private *dev_priv = |
1609 | intel_dp_to_dev(intel_dp)->dev_private; | |
1610 | ||
1611 | lockdep_assert_held(&dev_priv->pps_mutex); | |
1612 | ||
97af61f5 KP |
1613 | if (!is_edp(intel_dp)) |
1614 | return; | |
5d613501 | 1615 | |
3936fcf4 VS |
1616 | WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
1617 | port_name(dp_to_dig_port(intel_dp)->port)); | |
f2e8b18a | 1618 | |
bd943159 KP |
1619 | intel_dp->want_panel_vdd = false; |
1620 | ||
aba86890 | 1621 | if (sync) |
4be73780 | 1622 | edp_panel_vdd_off_sync(intel_dp); |
aba86890 ID |
1623 | else |
1624 | edp_panel_vdd_schedule_off(intel_dp); | |
5d613501 JB |
1625 | } |
1626 | ||
9f0fb5be | 1627 | static void edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 1628 | { |
30add22d | 1629 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1630 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1631 | u32 pp; |
453c5420 | 1632 | u32 pp_ctrl_reg; |
9934c132 | 1633 | |
9f0fb5be VS |
1634 | lockdep_assert_held(&dev_priv->pps_mutex); |
1635 | ||
97af61f5 | 1636 | if (!is_edp(intel_dp)) |
bd943159 | 1637 | return; |
99ea7127 | 1638 | |
3936fcf4 VS |
1639 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
1640 | port_name(dp_to_dig_port(intel_dp)->port)); | |
99ea7127 | 1641 | |
e7a89ace VS |
1642 | if (WARN(edp_have_panel_power(intel_dp), |
1643 | "eDP port %c panel power already on\n", | |
1644 | port_name(dp_to_dig_port(intel_dp)->port))) | |
9f0fb5be | 1645 | return; |
9934c132 | 1646 | |
4be73780 | 1647 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 1648 | |
bf13e81b | 1649 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 1650 | pp = ironlake_get_pp_control(intel_dp); |
05ce1a49 KP |
1651 | if (IS_GEN5(dev)) { |
1652 | /* ILK workaround: disable reset around power sequence */ | |
1653 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
1654 | I915_WRITE(pp_ctrl_reg, pp); |
1655 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1656 | } |
37c6c9b0 | 1657 | |
1c0ae80a | 1658 | pp |= POWER_TARGET_ON; |
99ea7127 KP |
1659 | if (!IS_GEN5(dev)) |
1660 | pp |= PANEL_POWER_RESET; | |
1661 | ||
453c5420 JB |
1662 | I915_WRITE(pp_ctrl_reg, pp); |
1663 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1664 | |
4be73780 | 1665 | wait_panel_on(intel_dp); |
dce56b3c | 1666 | intel_dp->last_power_on = jiffies; |
9934c132 | 1667 | |
05ce1a49 KP |
1668 | if (IS_GEN5(dev)) { |
1669 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
bf13e81b JN |
1670 | I915_WRITE(pp_ctrl_reg, pp); |
1671 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1672 | } |
9f0fb5be | 1673 | } |
e39b999a | 1674 | |
9f0fb5be VS |
1675 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
1676 | { | |
1677 | if (!is_edp(intel_dp)) | |
1678 | return; | |
1679 | ||
1680 | pps_lock(intel_dp); | |
1681 | edp_panel_on(intel_dp); | |
773538e8 | 1682 | pps_unlock(intel_dp); |
9934c132 JB |
1683 | } |
1684 | ||
9f0fb5be VS |
1685 | |
1686 | static void edp_panel_off(struct intel_dp *intel_dp) | |
9934c132 | 1687 | { |
4e6e1a54 ID |
1688 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1689 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
30add22d | 1690 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1691 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e6e1a54 | 1692 | enum intel_display_power_domain power_domain; |
99ea7127 | 1693 | u32 pp; |
453c5420 | 1694 | u32 pp_ctrl_reg; |
9934c132 | 1695 | |
9f0fb5be VS |
1696 | lockdep_assert_held(&dev_priv->pps_mutex); |
1697 | ||
97af61f5 KP |
1698 | if (!is_edp(intel_dp)) |
1699 | return; | |
37c6c9b0 | 1700 | |
3936fcf4 VS |
1701 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
1702 | port_name(dp_to_dig_port(intel_dp)->port)); | |
37c6c9b0 | 1703 | |
3936fcf4 VS |
1704 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
1705 | port_name(dp_to_dig_port(intel_dp)->port)); | |
24f3e092 | 1706 | |
453c5420 | 1707 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
1708 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
1709 | * panels get very unhappy and cease to work. */ | |
b3064154 PJ |
1710 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
1711 | EDP_BLC_ENABLE); | |
453c5420 | 1712 | |
bf13e81b | 1713 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 1714 | |
849e39f5 PZ |
1715 | intel_dp->want_panel_vdd = false; |
1716 | ||
453c5420 JB |
1717 | I915_WRITE(pp_ctrl_reg, pp); |
1718 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1719 | |
dce56b3c | 1720 | intel_dp->last_power_cycle = jiffies; |
4be73780 | 1721 | wait_panel_off(intel_dp); |
849e39f5 PZ |
1722 | |
1723 | /* We got a reference when we enabled the VDD. */ | |
4e6e1a54 ID |
1724 | power_domain = intel_display_port_power_domain(intel_encoder); |
1725 | intel_display_power_put(dev_priv, power_domain); | |
9f0fb5be | 1726 | } |
e39b999a | 1727 | |
9f0fb5be VS |
1728 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
1729 | { | |
1730 | if (!is_edp(intel_dp)) | |
1731 | return; | |
1732 | ||
1733 | pps_lock(intel_dp); | |
1734 | edp_panel_off(intel_dp); | |
773538e8 | 1735 | pps_unlock(intel_dp); |
9934c132 JB |
1736 | } |
1737 | ||
1250d107 JN |
1738 | /* Enable backlight in the panel power control. */ |
1739 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) | |
32f9d658 | 1740 | { |
da63a9f2 PZ |
1741 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1742 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
32f9d658 ZW |
1743 | struct drm_i915_private *dev_priv = dev->dev_private; |
1744 | u32 pp; | |
453c5420 | 1745 | u32 pp_ctrl_reg; |
32f9d658 | 1746 | |
01cb9ea6 JB |
1747 | /* |
1748 | * If we enable the backlight right away following a panel power | |
1749 | * on, we may see slight flicker as the panel syncs with the eDP | |
1750 | * link. So delay a bit to make sure the image is solid before | |
1751 | * allowing it to appear. | |
1752 | */ | |
4be73780 | 1753 | wait_backlight_on(intel_dp); |
e39b999a | 1754 | |
773538e8 | 1755 | pps_lock(intel_dp); |
e39b999a | 1756 | |
453c5420 | 1757 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 1758 | pp |= EDP_BLC_ENABLE; |
453c5420 | 1759 | |
bf13e81b | 1760 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
1761 | |
1762 | I915_WRITE(pp_ctrl_reg, pp); | |
1763 | POSTING_READ(pp_ctrl_reg); | |
e39b999a | 1764 | |
773538e8 | 1765 | pps_unlock(intel_dp); |
32f9d658 ZW |
1766 | } |
1767 | ||
1250d107 JN |
1768 | /* Enable backlight PWM and backlight PP control. */ |
1769 | void intel_edp_backlight_on(struct intel_dp *intel_dp) | |
1770 | { | |
1771 | if (!is_edp(intel_dp)) | |
1772 | return; | |
1773 | ||
1774 | DRM_DEBUG_KMS("\n"); | |
1775 | ||
1776 | intel_panel_enable_backlight(intel_dp->attached_connector); | |
1777 | _intel_edp_backlight_on(intel_dp); | |
1778 | } | |
1779 | ||
1780 | /* Disable backlight in the panel power control. */ | |
1781 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) | |
32f9d658 | 1782 | { |
30add22d | 1783 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
32f9d658 ZW |
1784 | struct drm_i915_private *dev_priv = dev->dev_private; |
1785 | u32 pp; | |
453c5420 | 1786 | u32 pp_ctrl_reg; |
32f9d658 | 1787 | |
f01eca2e KP |
1788 | if (!is_edp(intel_dp)) |
1789 | return; | |
1790 | ||
773538e8 | 1791 | pps_lock(intel_dp); |
e39b999a | 1792 | |
453c5420 | 1793 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 1794 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 1795 | |
bf13e81b | 1796 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
1797 | |
1798 | I915_WRITE(pp_ctrl_reg, pp); | |
1799 | POSTING_READ(pp_ctrl_reg); | |
f7d2323c | 1800 | |
773538e8 | 1801 | pps_unlock(intel_dp); |
e39b999a VS |
1802 | |
1803 | intel_dp->last_backlight_off = jiffies; | |
f7d2323c | 1804 | edp_wait_backlight_off(intel_dp); |
1250d107 | 1805 | } |
f7d2323c | 1806 | |
1250d107 JN |
1807 | /* Disable backlight PP control and backlight PWM. */ |
1808 | void intel_edp_backlight_off(struct intel_dp *intel_dp) | |
1809 | { | |
1810 | if (!is_edp(intel_dp)) | |
1811 | return; | |
1812 | ||
1813 | DRM_DEBUG_KMS("\n"); | |
f7d2323c | 1814 | |
1250d107 | 1815 | _intel_edp_backlight_off(intel_dp); |
f7d2323c | 1816 | intel_panel_disable_backlight(intel_dp->attached_connector); |
32f9d658 | 1817 | } |
a4fc5ed6 | 1818 | |
73580fb7 JN |
1819 | /* |
1820 | * Hook for controlling the panel power control backlight through the bl_power | |
1821 | * sysfs attribute. Take care to handle multiple calls. | |
1822 | */ | |
1823 | static void intel_edp_backlight_power(struct intel_connector *connector, | |
1824 | bool enable) | |
1825 | { | |
1826 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); | |
e39b999a VS |
1827 | bool is_enabled; |
1828 | ||
773538e8 | 1829 | pps_lock(intel_dp); |
e39b999a | 1830 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
773538e8 | 1831 | pps_unlock(intel_dp); |
73580fb7 JN |
1832 | |
1833 | if (is_enabled == enable) | |
1834 | return; | |
1835 | ||
23ba9373 JN |
1836 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
1837 | enable ? "enable" : "disable"); | |
73580fb7 JN |
1838 | |
1839 | if (enable) | |
1840 | _intel_edp_backlight_on(intel_dp); | |
1841 | else | |
1842 | _intel_edp_backlight_off(intel_dp); | |
1843 | } | |
1844 | ||
2bd2ad64 | 1845 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
d240f20f | 1846 | { |
da63a9f2 PZ |
1847 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1848 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
1849 | struct drm_device *dev = crtc->dev; | |
d240f20f JB |
1850 | struct drm_i915_private *dev_priv = dev->dev_private; |
1851 | u32 dpa_ctl; | |
1852 | ||
2bd2ad64 DV |
1853 | assert_pipe_disabled(dev_priv, |
1854 | to_intel_crtc(crtc)->pipe); | |
1855 | ||
d240f20f JB |
1856 | DRM_DEBUG_KMS("\n"); |
1857 | dpa_ctl = I915_READ(DP_A); | |
0767935e DV |
1858 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
1859 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); | |
1860 | ||
1861 | /* We don't adjust intel_dp->DP while tearing down the link, to | |
1862 | * facilitate link retraining (e.g. after hotplug). Hence clear all | |
1863 | * enable bits here to ensure that we don't enable too much. */ | |
1864 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); | |
1865 | intel_dp->DP |= DP_PLL_ENABLE; | |
1866 | I915_WRITE(DP_A, intel_dp->DP); | |
298b0b39 JB |
1867 | POSTING_READ(DP_A); |
1868 | udelay(200); | |
d240f20f JB |
1869 | } |
1870 | ||
2bd2ad64 | 1871 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 1872 | { |
da63a9f2 PZ |
1873 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1874 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
1875 | struct drm_device *dev = crtc->dev; | |
d240f20f JB |
1876 | struct drm_i915_private *dev_priv = dev->dev_private; |
1877 | u32 dpa_ctl; | |
1878 | ||
2bd2ad64 DV |
1879 | assert_pipe_disabled(dev_priv, |
1880 | to_intel_crtc(crtc)->pipe); | |
1881 | ||
d240f20f | 1882 | dpa_ctl = I915_READ(DP_A); |
0767935e DV |
1883 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
1884 | "dp pll off, should be on\n"); | |
1885 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); | |
1886 | ||
1887 | /* We can't rely on the value tracked for the DP register in | |
1888 | * intel_dp->DP because link_down must not change that (otherwise link | |
1889 | * re-training will fail. */ | |
298b0b39 | 1890 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 1891 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 1892 | POSTING_READ(DP_A); |
d240f20f JB |
1893 | udelay(200); |
1894 | } | |
1895 | ||
c7ad3810 | 1896 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 1897 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
1898 | { |
1899 | int ret, i; | |
1900 | ||
1901 | /* Should have a valid DPCD by this point */ | |
1902 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
1903 | return; | |
1904 | ||
1905 | if (mode != DRM_MODE_DPMS_ON) { | |
9d1a1031 JN |
1906 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
1907 | DP_SET_POWER_D3); | |
c7ad3810 JB |
1908 | } else { |
1909 | /* | |
1910 | * When turning on, we need to retry for 1ms to give the sink | |
1911 | * time to wake up. | |
1912 | */ | |
1913 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
1914 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
1915 | DP_SET_POWER_D0); | |
c7ad3810 JB |
1916 | if (ret == 1) |
1917 | break; | |
1918 | msleep(1); | |
1919 | } | |
1920 | } | |
f9cac721 JN |
1921 | |
1922 | if (ret != 1) | |
1923 | DRM_DEBUG_KMS("failed to %s sink power state\n", | |
1924 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); | |
c7ad3810 JB |
1925 | } |
1926 | ||
19d8fe15 DV |
1927 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
1928 | enum pipe *pipe) | |
d240f20f | 1929 | { |
19d8fe15 | 1930 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1931 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 DV |
1932 | struct drm_device *dev = encoder->base.dev; |
1933 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d129bea ID |
1934 | enum intel_display_power_domain power_domain; |
1935 | u32 tmp; | |
1936 | ||
1937 | power_domain = intel_display_port_power_domain(encoder); | |
f458ebbc | 1938 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
1939 | return false; |
1940 | ||
1941 | tmp = I915_READ(intel_dp->output_reg); | |
19d8fe15 DV |
1942 | |
1943 | if (!(tmp & DP_PORT_EN)) | |
1944 | return false; | |
1945 | ||
bc7d38a4 | 1946 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
19d8fe15 | 1947 | *pipe = PORT_TO_PIPE_CPT(tmp); |
71485e0a VS |
1948 | } else if (IS_CHERRYVIEW(dev)) { |
1949 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); | |
bc7d38a4 | 1950 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
19d8fe15 DV |
1951 | *pipe = PORT_TO_PIPE(tmp); |
1952 | } else { | |
1953 | u32 trans_sel; | |
1954 | u32 trans_dp; | |
1955 | int i; | |
1956 | ||
1957 | switch (intel_dp->output_reg) { | |
1958 | case PCH_DP_B: | |
1959 | trans_sel = TRANS_DP_PORT_SEL_B; | |
1960 | break; | |
1961 | case PCH_DP_C: | |
1962 | trans_sel = TRANS_DP_PORT_SEL_C; | |
1963 | break; | |
1964 | case PCH_DP_D: | |
1965 | trans_sel = TRANS_DP_PORT_SEL_D; | |
1966 | break; | |
1967 | default: | |
1968 | return true; | |
1969 | } | |
1970 | ||
055e393f | 1971 | for_each_pipe(dev_priv, i) { |
19d8fe15 DV |
1972 | trans_dp = I915_READ(TRANS_DP_CTL(i)); |
1973 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { | |
1974 | *pipe = i; | |
1975 | return true; | |
1976 | } | |
1977 | } | |
19d8fe15 | 1978 | |
4a0833ec DV |
1979 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
1980 | intel_dp->output_reg); | |
1981 | } | |
d240f20f | 1982 | |
19d8fe15 DV |
1983 | return true; |
1984 | } | |
d240f20f | 1985 | |
045ac3b5 JB |
1986 | static void intel_dp_get_config(struct intel_encoder *encoder, |
1987 | struct intel_crtc_config *pipe_config) | |
1988 | { | |
1989 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 1990 | u32 tmp, flags = 0; |
63000ef6 XZ |
1991 | struct drm_device *dev = encoder->base.dev; |
1992 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1993 | enum port port = dp_to_dig_port(intel_dp)->port; | |
1994 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
18442d08 | 1995 | int dotclock; |
045ac3b5 | 1996 | |
9ed109a7 DV |
1997 | tmp = I915_READ(intel_dp->output_reg); |
1998 | if (tmp & DP_AUDIO_OUTPUT_ENABLE) | |
1999 | pipe_config->has_audio = true; | |
2000 | ||
63000ef6 | 2001 | if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { |
63000ef6 XZ |
2002 | if (tmp & DP_SYNC_HS_HIGH) |
2003 | flags |= DRM_MODE_FLAG_PHSYNC; | |
2004 | else | |
2005 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2006 | |
63000ef6 XZ |
2007 | if (tmp & DP_SYNC_VS_HIGH) |
2008 | flags |= DRM_MODE_FLAG_PVSYNC; | |
2009 | else | |
2010 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2011 | } else { | |
2012 | tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
2013 | if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
2014 | flags |= DRM_MODE_FLAG_PHSYNC; | |
2015 | else | |
2016 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2017 | |
63000ef6 XZ |
2018 | if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
2019 | flags |= DRM_MODE_FLAG_PVSYNC; | |
2020 | else | |
2021 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2022 | } | |
045ac3b5 JB |
2023 | |
2024 | pipe_config->adjusted_mode.flags |= flags; | |
f1f644dc | 2025 | |
8c875fca VS |
2026 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
2027 | tmp & DP_COLOR_RANGE_16_235) | |
2028 | pipe_config->limited_color_range = true; | |
2029 | ||
eb14cb74 VS |
2030 | pipe_config->has_dp_encoder = true; |
2031 | ||
2032 | intel_dp_get_m_n(crtc, pipe_config); | |
2033 | ||
18442d08 | 2034 | if (port == PORT_A) { |
f1f644dc JB |
2035 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
2036 | pipe_config->port_clock = 162000; | |
2037 | else | |
2038 | pipe_config->port_clock = 270000; | |
2039 | } | |
18442d08 VS |
2040 | |
2041 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, | |
2042 | &pipe_config->dp_m_n); | |
2043 | ||
2044 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) | |
2045 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
2046 | ||
241bfc38 | 2047 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
7f16e5c1 | 2048 | |
c6cd2ee2 JN |
2049 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
2050 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { | |
2051 | /* | |
2052 | * This is a big fat ugly hack. | |
2053 | * | |
2054 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2055 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2056 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2057 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2058 | * max, not what it tells us to use. | |
2059 | * | |
2060 | * Note: This will still be broken if the eDP panel is not lit | |
2061 | * up by the BIOS, and thus we can't get the mode at module | |
2062 | * load. | |
2063 | */ | |
2064 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
2065 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); | |
2066 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; | |
2067 | } | |
045ac3b5 JB |
2068 | } |
2069 | ||
34eb7579 | 2070 | static bool is_edp_psr(struct intel_dp *intel_dp) |
2293bb5c | 2071 | { |
34eb7579 | 2072 | return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; |
2293bb5c SK |
2073 | } |
2074 | ||
2b28bb1b RV |
2075 | static bool intel_edp_is_psr_enabled(struct drm_device *dev) |
2076 | { | |
2077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2078 | ||
18b5992c | 2079 | if (!HAS_PSR(dev)) |
2b28bb1b RV |
2080 | return false; |
2081 | ||
18b5992c | 2082 | return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
2b28bb1b RV |
2083 | } |
2084 | ||
2085 | static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, | |
2086 | struct edp_vsc_psr *vsc_psr) | |
2087 | { | |
2088 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2089 | struct drm_device *dev = dig_port->base.base.dev; | |
2090 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2091 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); | |
2092 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); | |
2093 | u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); | |
2094 | uint32_t *data = (uint32_t *) vsc_psr; | |
2095 | unsigned int i; | |
2096 | ||
2097 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable | |
2098 | the video DIP being updated before program video DIP data buffer | |
2099 | registers for DIP being updated. */ | |
2100 | I915_WRITE(ctl_reg, 0); | |
2101 | POSTING_READ(ctl_reg); | |
2102 | ||
2103 | for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { | |
2104 | if (i < sizeof(struct edp_vsc_psr)) | |
2105 | I915_WRITE(data_reg + i, *data++); | |
2106 | else | |
2107 | I915_WRITE(data_reg + i, 0); | |
2108 | } | |
2109 | ||
2110 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); | |
2111 | POSTING_READ(ctl_reg); | |
2112 | } | |
2113 | ||
ba80f4d4 | 2114 | static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp) |
2b28bb1b | 2115 | { |
2b28bb1b RV |
2116 | struct edp_vsc_psr psr_vsc; |
2117 | ||
2b28bb1b RV |
2118 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
2119 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
2120 | psr_vsc.sdp_header.HB0 = 0; | |
2121 | psr_vsc.sdp_header.HB1 = 0x7; | |
2122 | psr_vsc.sdp_header.HB2 = 0x2; | |
2123 | psr_vsc.sdp_header.HB3 = 0x8; | |
2124 | intel_edp_psr_write_vsc(intel_dp, &psr_vsc); | |
2b28bb1b RV |
2125 | } |
2126 | ||
2127 | static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) | |
2128 | { | |
0e0ae652 RV |
2129 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
2130 | struct drm_device *dev = dig_port->base.base.dev; | |
2b28bb1b | 2131 | struct drm_i915_private *dev_priv = dev->dev_private; |
ec5b01dd | 2132 | uint32_t aux_clock_divider; |
2b28bb1b | 2133 | int precharge = 0x3; |
0e0ae652 | 2134 | bool only_standby = false; |
5ca476f8 VS |
2135 | static const uint8_t aux_msg[] = { |
2136 | [0] = DP_AUX_NATIVE_WRITE << 4, | |
2137 | [1] = DP_SET_POWER >> 8, | |
2138 | [2] = DP_SET_POWER & 0xff, | |
2139 | [3] = 1 - 1, | |
2140 | [4] = DP_SET_POWER_D0, | |
2141 | }; | |
2142 | int i; | |
2143 | ||
2144 | BUILD_BUG_ON(sizeof(aux_msg) > 20); | |
2b28bb1b | 2145 | |
ec5b01dd DL |
2146 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
2147 | ||
0e0ae652 RV |
2148 | if (IS_BROADWELL(dev) && dig_port->port != PORT_A) |
2149 | only_standby = true; | |
2150 | ||
2b28bb1b | 2151 | /* Enable PSR in sink */ |
0e0ae652 | 2152 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) |
9d1a1031 JN |
2153 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
2154 | DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); | |
2b28bb1b | 2155 | else |
9d1a1031 JN |
2156 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
2157 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); | |
2b28bb1b RV |
2158 | |
2159 | /* Setup AUX registers */ | |
5ca476f8 VS |
2160 | for (i = 0; i < sizeof(aux_msg); i += 4) |
2161 | I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i, | |
2162 | pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); | |
2163 | ||
18b5992c | 2164 | I915_WRITE(EDP_PSR_AUX_CTL(dev), |
2b28bb1b | 2165 | DP_AUX_CH_CTL_TIME_OUT_400us | |
5ca476f8 | 2166 | (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
2b28bb1b RV |
2167 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
2168 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); | |
2169 | } | |
2170 | ||
2171 | static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) | |
2172 | { | |
0e0ae652 RV |
2173 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
2174 | struct drm_device *dev = dig_port->base.base.dev; | |
2b28bb1b RV |
2175 | struct drm_i915_private *dev_priv = dev->dev_private; |
2176 | uint32_t max_sleep_time = 0x1f; | |
2177 | uint32_t idle_frames = 1; | |
2178 | uint32_t val = 0x0; | |
ed8546ac | 2179 | const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
0e0ae652 RV |
2180 | bool only_standby = false; |
2181 | ||
2182 | if (IS_BROADWELL(dev) && dig_port->port != PORT_A) | |
2183 | only_standby = true; | |
2b28bb1b | 2184 | |
0e0ae652 | 2185 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) { |
2b28bb1b RV |
2186 | val |= EDP_PSR_LINK_STANDBY; |
2187 | val |= EDP_PSR_TP2_TP3_TIME_0us; | |
2188 | val |= EDP_PSR_TP1_TIME_0us; | |
2189 | val |= EDP_PSR_SKIP_AUX_EXIT; | |
82c56254 | 2190 | val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0; |
2b28bb1b RV |
2191 | } else |
2192 | val |= EDP_PSR_LINK_DISABLE; | |
2193 | ||
18b5992c | 2194 | I915_WRITE(EDP_PSR_CTL(dev), val | |
24bd9bf5 | 2195 | (IS_BROADWELL(dev) ? 0 : link_entry_time) | |
2b28bb1b RV |
2196 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | |
2197 | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | | |
2198 | EDP_PSR_ENABLE); | |
2199 | } | |
2200 | ||
3f51e471 RV |
2201 | static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) |
2202 | { | |
2203 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2204 | struct drm_device *dev = dig_port->base.base.dev; | |
2205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2206 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
2207 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3f51e471 | 2208 | |
f0355c4a | 2209 | lockdep_assert_held(&dev_priv->psr.lock); |
f0355c4a DV |
2210 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
2211 | WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); | |
2212 | ||
a031d709 RV |
2213 | dev_priv->psr.source_ok = false; |
2214 | ||
9ca15301 | 2215 | if (IS_HASWELL(dev) && dig_port->port != PORT_A) { |
3f51e471 | 2216 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); |
3f51e471 RV |
2217 | return false; |
2218 | } | |
2219 | ||
d330a953 | 2220 | if (!i915.enable_psr) { |
105b7c11 | 2221 | DRM_DEBUG_KMS("PSR disable by flag\n"); |
105b7c11 RV |
2222 | return false; |
2223 | } | |
2224 | ||
4c8c7000 RV |
2225 | /* Below limitations aren't valid for Broadwell */ |
2226 | if (IS_BROADWELL(dev)) | |
2227 | goto out; | |
2228 | ||
3f51e471 RV |
2229 | if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & |
2230 | S3D_ENABLE) { | |
2231 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); | |
3f51e471 RV |
2232 | return false; |
2233 | } | |
2234 | ||
ca73b4f0 | 2235 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
3f51e471 | 2236 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
3f51e471 RV |
2237 | return false; |
2238 | } | |
2239 | ||
4c8c7000 | 2240 | out: |
a031d709 | 2241 | dev_priv->psr.source_ok = true; |
3f51e471 RV |
2242 | return true; |
2243 | } | |
2244 | ||
3d739d92 | 2245 | static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) |
2b28bb1b | 2246 | { |
7c8f8a70 RV |
2247 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2248 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b28bb1b | 2250 | |
3638379c DV |
2251 | WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); |
2252 | WARN_ON(dev_priv->psr.active); | |
f0355c4a | 2253 | lockdep_assert_held(&dev_priv->psr.lock); |
2b28bb1b | 2254 | |
7ca5a41f | 2255 | /* Enable/Re-enable PSR on the host */ |
2b28bb1b | 2256 | intel_edp_psr_enable_source(intel_dp); |
7c8f8a70 | 2257 | |
7c8f8a70 | 2258 | dev_priv->psr.active = true; |
2b28bb1b RV |
2259 | } |
2260 | ||
3d739d92 RV |
2261 | void intel_edp_psr_enable(struct intel_dp *intel_dp) |
2262 | { | |
2263 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
109fc2ad | 2264 | struct drm_i915_private *dev_priv = dev->dev_private; |
3d739d92 | 2265 | |
4704c573 RV |
2266 | if (!HAS_PSR(dev)) { |
2267 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); | |
2268 | return; | |
2269 | } | |
2270 | ||
34eb7579 RV |
2271 | if (!is_edp_psr(intel_dp)) { |
2272 | DRM_DEBUG_KMS("PSR not supported by this panel\n"); | |
2273 | return; | |
2274 | } | |
2275 | ||
f0355c4a | 2276 | mutex_lock(&dev_priv->psr.lock); |
109fc2ad DV |
2277 | if (dev_priv->psr.enabled) { |
2278 | DRM_DEBUG_KMS("PSR already in use\n"); | |
0aa48783 | 2279 | goto unlock; |
109fc2ad DV |
2280 | } |
2281 | ||
0aa48783 RV |
2282 | if (!intel_edp_psr_match_conditions(intel_dp)) |
2283 | goto unlock; | |
2284 | ||
9ca15301 DV |
2285 | dev_priv->psr.busy_frontbuffer_bits = 0; |
2286 | ||
ba80f4d4 | 2287 | intel_edp_psr_setup_vsc(intel_dp); |
16487254 | 2288 | |
ba80f4d4 RV |
2289 | /* Avoid continuous PSR exit by masking memup and hpd */ |
2290 | I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | | |
2291 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); | |
16487254 | 2292 | |
7ca5a41f RV |
2293 | /* Enable PSR on the panel */ |
2294 | intel_edp_psr_enable_sink(intel_dp); | |
2295 | ||
0aa48783 RV |
2296 | dev_priv->psr.enabled = intel_dp; |
2297 | unlock: | |
f0355c4a | 2298 | mutex_unlock(&dev_priv->psr.lock); |
3d739d92 RV |
2299 | } |
2300 | ||
2b28bb1b RV |
2301 | void intel_edp_psr_disable(struct intel_dp *intel_dp) |
2302 | { | |
2303 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
2304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2305 | ||
f0355c4a DV |
2306 | mutex_lock(&dev_priv->psr.lock); |
2307 | if (!dev_priv->psr.enabled) { | |
2308 | mutex_unlock(&dev_priv->psr.lock); | |
2309 | return; | |
2310 | } | |
2311 | ||
3638379c DV |
2312 | if (dev_priv->psr.active) { |
2313 | I915_WRITE(EDP_PSR_CTL(dev), | |
2314 | I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); | |
2315 | ||
2316 | /* Wait till PSR is idle */ | |
2317 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & | |
2318 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) | |
2319 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); | |
2b28bb1b | 2320 | |
3638379c DV |
2321 | dev_priv->psr.active = false; |
2322 | } else { | |
2323 | WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); | |
2324 | } | |
7c8f8a70 | 2325 | |
2807cf69 | 2326 | dev_priv->psr.enabled = NULL; |
f0355c4a | 2327 | mutex_unlock(&dev_priv->psr.lock); |
9ca15301 DV |
2328 | |
2329 | cancel_delayed_work_sync(&dev_priv->psr.work); | |
2b28bb1b RV |
2330 | } |
2331 | ||
f02a326e | 2332 | static void intel_edp_psr_work(struct work_struct *work) |
7c8f8a70 RV |
2333 | { |
2334 | struct drm_i915_private *dev_priv = | |
2335 | container_of(work, typeof(*dev_priv), psr.work.work); | |
2807cf69 DV |
2336 | struct intel_dp *intel_dp = dev_priv->psr.enabled; |
2337 | ||
8d7f4fe9 RV |
2338 | /* We have to make sure PSR is ready for re-enable |
2339 | * otherwise it keeps disabled until next full enable/disable cycle. | |
2340 | * PSR might take some time to get fully disabled | |
2341 | * and be ready for re-enable. | |
2342 | */ | |
2343 | if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) & | |
2344 | EDP_PSR_STATUS_STATE_MASK) == 0, 50)) { | |
2345 | DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); | |
2346 | return; | |
2347 | } | |
2348 | ||
f0355c4a DV |
2349 | mutex_lock(&dev_priv->psr.lock); |
2350 | intel_dp = dev_priv->psr.enabled; | |
2351 | ||
2807cf69 | 2352 | if (!intel_dp) |
f0355c4a | 2353 | goto unlock; |
2807cf69 | 2354 | |
9ca15301 DV |
2355 | /* |
2356 | * The delayed work can race with an invalidate hence we need to | |
2357 | * recheck. Since psr_flush first clears this and then reschedules we | |
2358 | * won't ever miss a flush when bailing out here. | |
2359 | */ | |
2360 | if (dev_priv->psr.busy_frontbuffer_bits) | |
2361 | goto unlock; | |
2362 | ||
2363 | intel_edp_psr_do_enable(intel_dp); | |
f0355c4a DV |
2364 | unlock: |
2365 | mutex_unlock(&dev_priv->psr.lock); | |
3d739d92 RV |
2366 | } |
2367 | ||
9ca15301 | 2368 | static void intel_edp_psr_do_exit(struct drm_device *dev) |
7c8f8a70 RV |
2369 | { |
2370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2371 | ||
3638379c DV |
2372 | if (dev_priv->psr.active) { |
2373 | u32 val = I915_READ(EDP_PSR_CTL(dev)); | |
2374 | ||
2375 | WARN_ON(!(val & EDP_PSR_ENABLE)); | |
2376 | ||
2377 | I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE); | |
2378 | ||
2379 | dev_priv->psr.active = false; | |
2380 | } | |
7c8f8a70 | 2381 | |
9ca15301 DV |
2382 | } |
2383 | ||
2384 | void intel_edp_psr_invalidate(struct drm_device *dev, | |
2385 | unsigned frontbuffer_bits) | |
2386 | { | |
2387 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2388 | struct drm_crtc *crtc; | |
2389 | enum pipe pipe; | |
2390 | ||
9ca15301 DV |
2391 | mutex_lock(&dev_priv->psr.lock); |
2392 | if (!dev_priv->psr.enabled) { | |
2393 | mutex_unlock(&dev_priv->psr.lock); | |
2394 | return; | |
2395 | } | |
2396 | ||
2397 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
2398 | pipe = to_intel_crtc(crtc)->pipe; | |
2399 | ||
2400 | intel_edp_psr_do_exit(dev); | |
2401 | ||
2402 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
2403 | ||
2404 | dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; | |
2405 | mutex_unlock(&dev_priv->psr.lock); | |
2406 | } | |
2407 | ||
2408 | void intel_edp_psr_flush(struct drm_device *dev, | |
2409 | unsigned frontbuffer_bits) | |
2410 | { | |
2411 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2412 | struct drm_crtc *crtc; | |
2413 | enum pipe pipe; | |
2414 | ||
9ca15301 DV |
2415 | mutex_lock(&dev_priv->psr.lock); |
2416 | if (!dev_priv->psr.enabled) { | |
2417 | mutex_unlock(&dev_priv->psr.lock); | |
2418 | return; | |
2419 | } | |
2420 | ||
2421 | crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; | |
2422 | pipe = to_intel_crtc(crtc)->pipe; | |
2423 | dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; | |
2424 | ||
2425 | /* | |
2426 | * On Haswell sprite plane updates don't result in a psr invalidating | |
2427 | * signal in the hardware. Which means we need to manually fake this in | |
2428 | * software for all flushes, not just when we've seen a preceding | |
2429 | * invalidation through frontbuffer rendering. | |
2430 | */ | |
2431 | if (IS_HASWELL(dev) && | |
2432 | (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe))) | |
2433 | intel_edp_psr_do_exit(dev); | |
2434 | ||
2435 | if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) | |
2436 | schedule_delayed_work(&dev_priv->psr.work, | |
2437 | msecs_to_jiffies(100)); | |
f0355c4a | 2438 | mutex_unlock(&dev_priv->psr.lock); |
7c8f8a70 RV |
2439 | } |
2440 | ||
2441 | void intel_edp_psr_init(struct drm_device *dev) | |
2442 | { | |
2443 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2444 | ||
7c8f8a70 | 2445 | INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work); |
f0355c4a | 2446 | mutex_init(&dev_priv->psr.lock); |
7c8f8a70 RV |
2447 | } |
2448 | ||
e8cb4558 | 2449 | static void intel_disable_dp(struct intel_encoder *encoder) |
d240f20f | 2450 | { |
e8cb4558 | 2451 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2452 | struct drm_device *dev = encoder->base.dev; |
495a5bb8 JN |
2453 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2454 | ||
2455 | if (crtc->config.has_audio) | |
2456 | intel_audio_codec_disable(encoder); | |
6cb49835 DV |
2457 | |
2458 | /* Make sure the panel is off before trying to change the mode. But also | |
2459 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 2460 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 2461 | intel_edp_backlight_off(intel_dp); |
fdbc3b1f | 2462 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 2463 | intel_edp_panel_off(intel_dp); |
3739850b | 2464 | |
08aff3fe VS |
2465 | /* disable the port before the pipe on g4x */ |
2466 | if (INTEL_INFO(dev)->gen < 5) | |
3739850b | 2467 | intel_dp_link_down(intel_dp); |
d240f20f JB |
2468 | } |
2469 | ||
08aff3fe | 2470 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
d240f20f | 2471 | { |
2bd2ad64 | 2472 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2473 | enum port port = dp_to_dig_port(intel_dp)->port; |
2bd2ad64 | 2474 | |
49277c31 | 2475 | intel_dp_link_down(intel_dp); |
08aff3fe VS |
2476 | if (port == PORT_A) |
2477 | ironlake_edp_pll_off(intel_dp); | |
49277c31 VS |
2478 | } |
2479 | ||
2480 | static void vlv_post_disable_dp(struct intel_encoder *encoder) | |
2481 | { | |
2482 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2483 | ||
2484 | intel_dp_link_down(intel_dp); | |
2bd2ad64 DV |
2485 | } |
2486 | ||
580d3811 VS |
2487 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
2488 | { | |
2489 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2490 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
2491 | struct drm_device *dev = encoder->base.dev; | |
2492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2493 | struct intel_crtc *intel_crtc = | |
2494 | to_intel_crtc(encoder->base.crtc); | |
2495 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
2496 | enum pipe pipe = intel_crtc->pipe; | |
2497 | u32 val; | |
2498 | ||
2499 | intel_dp_link_down(intel_dp); | |
2500 | ||
2501 | mutex_lock(&dev_priv->dpio_lock); | |
2502 | ||
2503 | /* Propagate soft reset to data lane reset */ | |
97fd4d5c | 2504 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 2505 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c | 2506 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
d2152b25 | 2507 | |
97fd4d5c VS |
2508 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
2509 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
2510 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
2511 | ||
2512 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
2513 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
2514 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
2515 | ||
2516 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); | |
580d3811 | 2517 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 2518 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
580d3811 VS |
2519 | |
2520 | mutex_unlock(&dev_priv->dpio_lock); | |
2521 | } | |
2522 | ||
7b13b58a VS |
2523 | static void |
2524 | _intel_dp_set_link_train(struct intel_dp *intel_dp, | |
2525 | uint32_t *DP, | |
2526 | uint8_t dp_train_pat) | |
2527 | { | |
2528 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2529 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2530 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2531 | enum port port = intel_dig_port->port; | |
2532 | ||
2533 | if (HAS_DDI(dev)) { | |
2534 | uint32_t temp = I915_READ(DP_TP_CTL(port)); | |
2535 | ||
2536 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2537 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2538 | else | |
2539 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2540 | ||
2541 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2542 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2543 | case DP_TRAINING_PATTERN_DISABLE: | |
2544 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; | |
2545 | ||
2546 | break; | |
2547 | case DP_TRAINING_PATTERN_1: | |
2548 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2549 | break; | |
2550 | case DP_TRAINING_PATTERN_2: | |
2551 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2552 | break; | |
2553 | case DP_TRAINING_PATTERN_3: | |
2554 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2555 | break; | |
2556 | } | |
2557 | I915_WRITE(DP_TP_CTL(port), temp); | |
2558 | ||
2559 | } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { | |
2560 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; | |
2561 | ||
2562 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2563 | case DP_TRAINING_PATTERN_DISABLE: | |
2564 | *DP |= DP_LINK_TRAIN_OFF_CPT; | |
2565 | break; | |
2566 | case DP_TRAINING_PATTERN_1: | |
2567 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; | |
2568 | break; | |
2569 | case DP_TRAINING_PATTERN_2: | |
2570 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2571 | break; | |
2572 | case DP_TRAINING_PATTERN_3: | |
2573 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
2574 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2575 | break; | |
2576 | } | |
2577 | ||
2578 | } else { | |
2579 | if (IS_CHERRYVIEW(dev)) | |
2580 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; | |
2581 | else | |
2582 | *DP &= ~DP_LINK_TRAIN_MASK; | |
2583 | ||
2584 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2585 | case DP_TRAINING_PATTERN_DISABLE: | |
2586 | *DP |= DP_LINK_TRAIN_OFF; | |
2587 | break; | |
2588 | case DP_TRAINING_PATTERN_1: | |
2589 | *DP |= DP_LINK_TRAIN_PAT_1; | |
2590 | break; | |
2591 | case DP_TRAINING_PATTERN_2: | |
2592 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2593 | break; | |
2594 | case DP_TRAINING_PATTERN_3: | |
2595 | if (IS_CHERRYVIEW(dev)) { | |
2596 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; | |
2597 | } else { | |
2598 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
2599 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2600 | } | |
2601 | break; | |
2602 | } | |
2603 | } | |
2604 | } | |
2605 | ||
2606 | static void intel_dp_enable_port(struct intel_dp *intel_dp) | |
2607 | { | |
2608 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
2609 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2610 | ||
7b13b58a VS |
2611 | /* enable with pattern 1 (as per spec) */ |
2612 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, | |
2613 | DP_TRAINING_PATTERN_1); | |
2614 | ||
2615 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2616 | POSTING_READ(intel_dp->output_reg); | |
7b713f50 VS |
2617 | |
2618 | /* | |
2619 | * Magic for VLV/CHV. We _must_ first set up the register | |
2620 | * without actually enabling the port, and then do another | |
2621 | * write to enable the port. Otherwise link training will | |
2622 | * fail when the power sequencer is freshly used for this port. | |
2623 | */ | |
2624 | intel_dp->DP |= DP_PORT_EN; | |
2625 | ||
2626 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2627 | POSTING_READ(intel_dp->output_reg); | |
580d3811 VS |
2628 | } |
2629 | ||
e8cb4558 | 2630 | static void intel_enable_dp(struct intel_encoder *encoder) |
d240f20f | 2631 | { |
e8cb4558 DV |
2632 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2633 | struct drm_device *dev = encoder->base.dev; | |
2634 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1dec79a | 2635 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
e8cb4558 | 2636 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
5d613501 | 2637 | |
0c33d8d7 DV |
2638 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2639 | return; | |
5d613501 | 2640 | |
093e3f13 VS |
2641 | pps_lock(intel_dp); |
2642 | ||
2643 | if (IS_VALLEYVIEW(dev)) | |
2644 | vlv_init_panel_power_sequencer(intel_dp); | |
2645 | ||
7b13b58a | 2646 | intel_dp_enable_port(intel_dp); |
093e3f13 VS |
2647 | |
2648 | edp_panel_vdd_on(intel_dp); | |
2649 | edp_panel_on(intel_dp); | |
2650 | edp_panel_vdd_off(intel_dp, true); | |
2651 | ||
2652 | pps_unlock(intel_dp); | |
2653 | ||
61234fa5 VS |
2654 | if (IS_VALLEYVIEW(dev)) |
2655 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp)); | |
2656 | ||
f01eca2e | 2657 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 2658 | intel_dp_start_link_train(intel_dp); |
33a34e4e | 2659 | intel_dp_complete_link_train(intel_dp); |
3ab9c637 | 2660 | intel_dp_stop_link_train(intel_dp); |
c1dec79a JN |
2661 | |
2662 | if (crtc->config.has_audio) { | |
2663 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", | |
2664 | pipe_name(crtc->pipe)); | |
2665 | intel_audio_codec_enable(encoder); | |
2666 | } | |
ab1f90f9 | 2667 | } |
89b667f8 | 2668 | |
ecff4f3b JN |
2669 | static void g4x_enable_dp(struct intel_encoder *encoder) |
2670 | { | |
828f5c6e JN |
2671 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2672 | ||
ecff4f3b | 2673 | intel_enable_dp(encoder); |
4be73780 | 2674 | intel_edp_backlight_on(intel_dp); |
ab1f90f9 | 2675 | } |
89b667f8 | 2676 | |
ab1f90f9 JN |
2677 | static void vlv_enable_dp(struct intel_encoder *encoder) |
2678 | { | |
828f5c6e JN |
2679 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2680 | ||
4be73780 | 2681 | intel_edp_backlight_on(intel_dp); |
d240f20f JB |
2682 | } |
2683 | ||
ecff4f3b | 2684 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
ab1f90f9 JN |
2685 | { |
2686 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2687 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
2688 | ||
8ac33ed3 DV |
2689 | intel_dp_prepare(encoder); |
2690 | ||
d41f1efb DV |
2691 | /* Only ilk+ has port A */ |
2692 | if (dport->port == PORT_A) { | |
2693 | ironlake_set_pll_cpu_edp(intel_dp); | |
ab1f90f9 | 2694 | ironlake_edp_pll_on(intel_dp); |
d41f1efb | 2695 | } |
ab1f90f9 JN |
2696 | } |
2697 | ||
83b84597 VS |
2698 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2699 | { | |
2700 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2701 | struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; | |
2702 | enum pipe pipe = intel_dp->pps_pipe; | |
2703 | int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
2704 | ||
2705 | edp_panel_vdd_off_sync(intel_dp); | |
2706 | ||
2707 | /* | |
2708 | * VLV seems to get confused when multiple power seqeuencers | |
2709 | * have the same port selected (even if only one has power/vdd | |
2710 | * enabled). The failure manifests as vlv_wait_port_ready() failing | |
2711 | * CHV on the other hand doesn't seem to mind having the same port | |
2712 | * selected in multiple power seqeuencers, but let's clear the | |
2713 | * port select always when logically disconnecting a power sequencer | |
2714 | * from a port. | |
2715 | */ | |
2716 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", | |
2717 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
2718 | I915_WRITE(pp_on_reg, 0); | |
2719 | POSTING_READ(pp_on_reg); | |
2720 | ||
2721 | intel_dp->pps_pipe = INVALID_PIPE; | |
2722 | } | |
2723 | ||
a4a5d2f8 VS |
2724 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2725 | enum pipe pipe) | |
2726 | { | |
2727 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2728 | struct intel_encoder *encoder; | |
2729 | ||
2730 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2731 | ||
ac3c12e4 VS |
2732 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2733 | return; | |
2734 | ||
a4a5d2f8 VS |
2735 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
2736 | base.head) { | |
2737 | struct intel_dp *intel_dp; | |
773538e8 | 2738 | enum port port; |
a4a5d2f8 VS |
2739 | |
2740 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2741 | continue; | |
2742 | ||
2743 | intel_dp = enc_to_intel_dp(&encoder->base); | |
773538e8 | 2744 | port = dp_to_dig_port(intel_dp)->port; |
a4a5d2f8 VS |
2745 | |
2746 | if (intel_dp->pps_pipe != pipe) | |
2747 | continue; | |
2748 | ||
2749 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", | |
773538e8 | 2750 | pipe_name(pipe), port_name(port)); |
a4a5d2f8 | 2751 | |
034e43c6 VS |
2752 | WARN(encoder->connectors_active, |
2753 | "stealing pipe %c power sequencer from active eDP port %c\n", | |
2754 | pipe_name(pipe), port_name(port)); | |
2755 | ||
a4a5d2f8 | 2756 | /* make sure vdd is off before we steal it */ |
83b84597 | 2757 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2758 | } |
2759 | } | |
2760 | ||
2761 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) | |
2762 | { | |
2763 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2764 | struct intel_encoder *encoder = &intel_dig_port->base; | |
2765 | struct drm_device *dev = encoder->base.dev; | |
2766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2767 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
a4a5d2f8 VS |
2768 | |
2769 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2770 | ||
093e3f13 VS |
2771 | if (!is_edp(intel_dp)) |
2772 | return; | |
2773 | ||
a4a5d2f8 VS |
2774 | if (intel_dp->pps_pipe == crtc->pipe) |
2775 | return; | |
2776 | ||
2777 | /* | |
2778 | * If another power sequencer was being used on this | |
2779 | * port previously make sure to turn off vdd there while | |
2780 | * we still have control of it. | |
2781 | */ | |
2782 | if (intel_dp->pps_pipe != INVALID_PIPE) | |
83b84597 | 2783 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2784 | |
2785 | /* | |
2786 | * We may be stealing the power | |
2787 | * sequencer from another port. | |
2788 | */ | |
2789 | vlv_steal_power_sequencer(dev, crtc->pipe); | |
2790 | ||
2791 | /* now it's all ours */ | |
2792 | intel_dp->pps_pipe = crtc->pipe; | |
2793 | ||
2794 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", | |
2795 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); | |
2796 | ||
2797 | /* init power sequencer on this pipe and port */ | |
36b5f425 VS |
2798 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
2799 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
a4a5d2f8 VS |
2800 | } |
2801 | ||
ab1f90f9 | 2802 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
a4fc5ed6 | 2803 | { |
2bd2ad64 | 2804 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 2805 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
b2634017 | 2806 | struct drm_device *dev = encoder->base.dev; |
89b667f8 | 2807 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab1f90f9 | 2808 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
e4607fcf | 2809 | enum dpio_channel port = vlv_dport_to_channel(dport); |
ab1f90f9 JN |
2810 | int pipe = intel_crtc->pipe; |
2811 | u32 val; | |
a4fc5ed6 | 2812 | |
ab1f90f9 | 2813 | mutex_lock(&dev_priv->dpio_lock); |
89b667f8 | 2814 | |
ab3c759a | 2815 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
ab1f90f9 JN |
2816 | val = 0; |
2817 | if (pipe) | |
2818 | val |= (1<<21); | |
2819 | else | |
2820 | val &= ~(1<<21); | |
2821 | val |= 0x001000c4; | |
ab3c759a CML |
2822 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
2823 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); | |
2824 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
89b667f8 | 2825 | |
ab1f90f9 JN |
2826 | mutex_unlock(&dev_priv->dpio_lock); |
2827 | ||
2828 | intel_enable_dp(encoder); | |
89b667f8 JB |
2829 | } |
2830 | ||
ecff4f3b | 2831 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
2832 | { |
2833 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2834 | struct drm_device *dev = encoder->base.dev; | |
2835 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
2836 | struct intel_crtc *intel_crtc = |
2837 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 2838 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 2839 | int pipe = intel_crtc->pipe; |
89b667f8 | 2840 | |
8ac33ed3 DV |
2841 | intel_dp_prepare(encoder); |
2842 | ||
89b667f8 | 2843 | /* Program Tx lane resets to default */ |
0980a60f | 2844 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 2845 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
2846 | DPIO_PCS_TX_LANE2_RESET | |
2847 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 2848 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
2849 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
2850 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
2851 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
2852 | DPIO_PCS_CLK_SOFT_RESET); | |
2853 | ||
2854 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
2855 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
2856 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
2857 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
0980a60f | 2858 | mutex_unlock(&dev_priv->dpio_lock); |
a4fc5ed6 KP |
2859 | } |
2860 | ||
e4a1d846 CML |
2861 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
2862 | { | |
2863 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2864 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
2865 | struct drm_device *dev = encoder->base.dev; | |
2866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e4a1d846 CML |
2867 | struct intel_crtc *intel_crtc = |
2868 | to_intel_crtc(encoder->base.crtc); | |
2869 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
2870 | int pipe = intel_crtc->pipe; | |
2871 | int data, i; | |
949c1d43 | 2872 | u32 val; |
e4a1d846 | 2873 | |
e4a1d846 | 2874 | mutex_lock(&dev_priv->dpio_lock); |
949c1d43 | 2875 | |
570e2a74 VS |
2876 | /* allow hardware to manage TX FIFO reset source */ |
2877 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
2878 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
2879 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
2880 | ||
2881 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
2882 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
2883 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
2884 | ||
949c1d43 | 2885 | /* Deassert soft data lane reset*/ |
97fd4d5c | 2886 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 2887 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c VS |
2888 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
2889 | ||
2890 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); | |
2891 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
2892 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
2893 | ||
2894 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
2895 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
2896 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
d2152b25 | 2897 | |
97fd4d5c | 2898 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
949c1d43 | 2899 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 2900 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
949c1d43 VS |
2901 | |
2902 | /* Program Tx lane latency optimal setting*/ | |
e4a1d846 CML |
2903 | for (i = 0; i < 4; i++) { |
2904 | /* Set the latency optimal bit */ | |
2905 | data = (i == 1) ? 0x0 : 0x6; | |
2906 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), | |
2907 | data << DPIO_FRC_LATENCY_SHFIT); | |
2908 | ||
2909 | /* Set the upar bit */ | |
2910 | data = (i == 1) ? 0x0 : 0x1; | |
2911 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
2912 | data << DPIO_UPAR_SHIFT); | |
2913 | } | |
2914 | ||
2915 | /* Data lane stagger programming */ | |
2916 | /* FIXME: Fix up value only after power analysis */ | |
2917 | ||
2918 | mutex_unlock(&dev_priv->dpio_lock); | |
2919 | ||
e4a1d846 | 2920 | intel_enable_dp(encoder); |
e4a1d846 CML |
2921 | } |
2922 | ||
9197c88b VS |
2923 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
2924 | { | |
2925 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2926 | struct drm_device *dev = encoder->base.dev; | |
2927 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2928 | struct intel_crtc *intel_crtc = | |
2929 | to_intel_crtc(encoder->base.crtc); | |
2930 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
2931 | enum pipe pipe = intel_crtc->pipe; | |
2932 | u32 val; | |
2933 | ||
625695f8 VS |
2934 | intel_dp_prepare(encoder); |
2935 | ||
9197c88b VS |
2936 | mutex_lock(&dev_priv->dpio_lock); |
2937 | ||
b9e5ac3c VS |
2938 | /* program left/right clock distribution */ |
2939 | if (pipe != PIPE_B) { | |
2940 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
2941 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
2942 | if (ch == DPIO_CH0) | |
2943 | val |= CHV_BUFLEFTENA1_FORCE; | |
2944 | if (ch == DPIO_CH1) | |
2945 | val |= CHV_BUFRIGHTENA1_FORCE; | |
2946 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
2947 | } else { | |
2948 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
2949 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
2950 | if (ch == DPIO_CH0) | |
2951 | val |= CHV_BUFLEFTENA2_FORCE; | |
2952 | if (ch == DPIO_CH1) | |
2953 | val |= CHV_BUFRIGHTENA2_FORCE; | |
2954 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
2955 | } | |
2956 | ||
9197c88b VS |
2957 | /* program clock channel usage */ |
2958 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); | |
2959 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
2960 | if (pipe != PIPE_B) | |
2961 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
2962 | else | |
2963 | val |= CHV_PCS_USEDCLKCHANNEL; | |
2964 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); | |
2965 | ||
2966 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); | |
2967 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
2968 | if (pipe != PIPE_B) | |
2969 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
2970 | else | |
2971 | val |= CHV_PCS_USEDCLKCHANNEL; | |
2972 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); | |
2973 | ||
2974 | /* | |
2975 | * This a a bit weird since generally CL | |
2976 | * matches the pipe, but here we need to | |
2977 | * pick the CL based on the port. | |
2978 | */ | |
2979 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); | |
2980 | if (pipe != PIPE_B) | |
2981 | val &= ~CHV_CMN_USEDCLKCHANNEL; | |
2982 | else | |
2983 | val |= CHV_CMN_USEDCLKCHANNEL; | |
2984 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); | |
2985 | ||
2986 | mutex_unlock(&dev_priv->dpio_lock); | |
2987 | } | |
2988 | ||
a4fc5ed6 | 2989 | /* |
df0c237d JB |
2990 | * Native read with retry for link status and receiver capability reads for |
2991 | * cases where the sink may still be asleep. | |
9d1a1031 JN |
2992 | * |
2993 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also | |
2994 | * supposed to retry 3 times per the spec. | |
a4fc5ed6 | 2995 | */ |
9d1a1031 JN |
2996 | static ssize_t |
2997 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, | |
2998 | void *buffer, size_t size) | |
a4fc5ed6 | 2999 | { |
9d1a1031 JN |
3000 | ssize_t ret; |
3001 | int i; | |
61da5fab | 3002 | |
61da5fab | 3003 | for (i = 0; i < 3; i++) { |
9d1a1031 JN |
3004 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
3005 | if (ret == size) | |
3006 | return ret; | |
61da5fab JB |
3007 | msleep(1); |
3008 | } | |
a4fc5ed6 | 3009 | |
9d1a1031 | 3010 | return ret; |
a4fc5ed6 KP |
3011 | } |
3012 | ||
3013 | /* | |
3014 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
3015 | * link status information | |
3016 | */ | |
3017 | static bool | |
93f62dad | 3018 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 3019 | { |
9d1a1031 JN |
3020 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
3021 | DP_LANE0_1_STATUS, | |
3022 | link_status, | |
3023 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
3024 | } |
3025 | ||
1100244e | 3026 | /* These are source-specific values. */ |
a4fc5ed6 | 3027 | static uint8_t |
1a2eb460 | 3028 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 3029 | { |
30add22d | 3030 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 3031 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 3032 | |
5a9d1f1a DL |
3033 | if (INTEL_INFO(dev)->gen >= 9) |
3034 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; | |
3035 | else if (IS_VALLEYVIEW(dev)) | |
bd60018a | 3036 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
bc7d38a4 | 3037 | else if (IS_GEN7(dev) && port == PORT_A) |
bd60018a | 3038 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
bc7d38a4 | 3039 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
bd60018a | 3040 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
1a2eb460 | 3041 | else |
bd60018a | 3042 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
1a2eb460 KP |
3043 | } |
3044 | ||
3045 | static uint8_t | |
3046 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) | |
3047 | { | |
30add22d | 3048 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 3049 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 3050 | |
5a9d1f1a DL |
3051 | if (INTEL_INFO(dev)->gen >= 9) { |
3052 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
3053 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: | |
3054 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3055 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3056 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3057 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3058 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3059 | default: | |
3060 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
3061 | } | |
3062 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
d6c0d722 | 3063 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3064 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3065 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3066 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3067 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3068 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3069 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3070 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
d6c0d722 | 3071 | default: |
bd60018a | 3072 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
d6c0d722 | 3073 | } |
e2fa6fba P |
3074 | } else if (IS_VALLEYVIEW(dev)) { |
3075 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
3076 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3077 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3078 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3079 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3080 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3081 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3082 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
e2fa6fba | 3083 | default: |
bd60018a | 3084 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
e2fa6fba | 3085 | } |
bc7d38a4 | 3086 | } else if (IS_GEN7(dev) && port == PORT_A) { |
1a2eb460 | 3087 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3088 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3089 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3090 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3091 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3092 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
1a2eb460 | 3093 | default: |
bd60018a | 3094 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 KP |
3095 | } |
3096 | } else { | |
3097 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
3098 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3099 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3100 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3101 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3102 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3103 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3104 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
1a2eb460 | 3105 | default: |
bd60018a | 3106 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 | 3107 | } |
a4fc5ed6 KP |
3108 | } |
3109 | } | |
3110 | ||
e2fa6fba P |
3111 | static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) |
3112 | { | |
3113 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
3114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3115 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
5e69f97f CML |
3116 | struct intel_crtc *intel_crtc = |
3117 | to_intel_crtc(dport->base.base.crtc); | |
e2fa6fba P |
3118 | unsigned long demph_reg_value, preemph_reg_value, |
3119 | uniqtranscale_reg_value; | |
3120 | uint8_t train_set = intel_dp->train_set[0]; | |
e4607fcf | 3121 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 3122 | int pipe = intel_crtc->pipe; |
e2fa6fba P |
3123 | |
3124 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3125 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e2fa6fba P |
3126 | preemph_reg_value = 0x0004000; |
3127 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3128 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3129 | demph_reg_value = 0x2B405555; |
3130 | uniqtranscale_reg_value = 0x552AB83A; | |
3131 | break; | |
bd60018a | 3132 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3133 | demph_reg_value = 0x2B404040; |
3134 | uniqtranscale_reg_value = 0x5548B83A; | |
3135 | break; | |
bd60018a | 3136 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3137 | demph_reg_value = 0x2B245555; |
3138 | uniqtranscale_reg_value = 0x5560B83A; | |
3139 | break; | |
bd60018a | 3140 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e2fa6fba P |
3141 | demph_reg_value = 0x2B405555; |
3142 | uniqtranscale_reg_value = 0x5598DA3A; | |
3143 | break; | |
3144 | default: | |
3145 | return 0; | |
3146 | } | |
3147 | break; | |
bd60018a | 3148 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e2fa6fba P |
3149 | preemph_reg_value = 0x0002000; |
3150 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3151 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3152 | demph_reg_value = 0x2B404040; |
3153 | uniqtranscale_reg_value = 0x5552B83A; | |
3154 | break; | |
bd60018a | 3155 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3156 | demph_reg_value = 0x2B404848; |
3157 | uniqtranscale_reg_value = 0x5580B83A; | |
3158 | break; | |
bd60018a | 3159 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3160 | demph_reg_value = 0x2B404040; |
3161 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3162 | break; | |
3163 | default: | |
3164 | return 0; | |
3165 | } | |
3166 | break; | |
bd60018a | 3167 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e2fa6fba P |
3168 | preemph_reg_value = 0x0000000; |
3169 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3170 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3171 | demph_reg_value = 0x2B305555; |
3172 | uniqtranscale_reg_value = 0x5570B83A; | |
3173 | break; | |
bd60018a | 3174 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3175 | demph_reg_value = 0x2B2B4040; |
3176 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3177 | break; | |
3178 | default: | |
3179 | return 0; | |
3180 | } | |
3181 | break; | |
bd60018a | 3182 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e2fa6fba P |
3183 | preemph_reg_value = 0x0006000; |
3184 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3185 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3186 | demph_reg_value = 0x1B405555; |
3187 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3188 | break; | |
3189 | default: | |
3190 | return 0; | |
3191 | } | |
3192 | break; | |
3193 | default: | |
3194 | return 0; | |
3195 | } | |
3196 | ||
0980a60f | 3197 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a CML |
3198 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
3199 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); | |
3200 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), | |
e2fa6fba | 3201 | uniqtranscale_reg_value); |
ab3c759a CML |
3202 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
3203 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
3204 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); | |
3205 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); | |
0980a60f | 3206 | mutex_unlock(&dev_priv->dpio_lock); |
e2fa6fba P |
3207 | |
3208 | return 0; | |
3209 | } | |
3210 | ||
e4a1d846 CML |
3211 | static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp) |
3212 | { | |
3213 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
3214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3215 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
3216 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); | |
f72df8db | 3217 | u32 deemph_reg_value, margin_reg_value, val; |
e4a1d846 CML |
3218 | uint8_t train_set = intel_dp->train_set[0]; |
3219 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
f72df8db VS |
3220 | enum pipe pipe = intel_crtc->pipe; |
3221 | int i; | |
e4a1d846 CML |
3222 | |
3223 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3224 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e4a1d846 | 3225 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3226 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3227 | deemph_reg_value = 128; |
3228 | margin_reg_value = 52; | |
3229 | break; | |
bd60018a | 3230 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3231 | deemph_reg_value = 128; |
3232 | margin_reg_value = 77; | |
3233 | break; | |
bd60018a | 3234 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3235 | deemph_reg_value = 128; |
3236 | margin_reg_value = 102; | |
3237 | break; | |
bd60018a | 3238 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e4a1d846 CML |
3239 | deemph_reg_value = 128; |
3240 | margin_reg_value = 154; | |
3241 | /* FIXME extra to set for 1200 */ | |
3242 | break; | |
3243 | default: | |
3244 | return 0; | |
3245 | } | |
3246 | break; | |
bd60018a | 3247 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e4a1d846 | 3248 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3249 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3250 | deemph_reg_value = 85; |
3251 | margin_reg_value = 78; | |
3252 | break; | |
bd60018a | 3253 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3254 | deemph_reg_value = 85; |
3255 | margin_reg_value = 116; | |
3256 | break; | |
bd60018a | 3257 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3258 | deemph_reg_value = 85; |
3259 | margin_reg_value = 154; | |
3260 | break; | |
3261 | default: | |
3262 | return 0; | |
3263 | } | |
3264 | break; | |
bd60018a | 3265 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e4a1d846 | 3266 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3267 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3268 | deemph_reg_value = 64; |
3269 | margin_reg_value = 104; | |
3270 | break; | |
bd60018a | 3271 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3272 | deemph_reg_value = 64; |
3273 | margin_reg_value = 154; | |
3274 | break; | |
3275 | default: | |
3276 | return 0; | |
3277 | } | |
3278 | break; | |
bd60018a | 3279 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e4a1d846 | 3280 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3281 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3282 | deemph_reg_value = 43; |
3283 | margin_reg_value = 154; | |
3284 | break; | |
3285 | default: | |
3286 | return 0; | |
3287 | } | |
3288 | break; | |
3289 | default: | |
3290 | return 0; | |
3291 | } | |
3292 | ||
3293 | mutex_lock(&dev_priv->dpio_lock); | |
3294 | ||
3295 | /* Clear calc init */ | |
1966e59e VS |
3296 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
3297 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
3298 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
3299 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e VS |
3300 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
3301 | ||
3302 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
3303 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
3304 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
3305 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e | 3306 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
e4a1d846 | 3307 | |
a02ef3c7 VS |
3308 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
3309 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
3310 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
3311 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); | |
3312 | ||
3313 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); | |
3314 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
3315 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
3316 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); | |
3317 | ||
e4a1d846 | 3318 | /* Program swing deemph */ |
f72df8db VS |
3319 | for (i = 0; i < 4; i++) { |
3320 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); | |
3321 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
3322 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; | |
3323 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); | |
3324 | } | |
e4a1d846 CML |
3325 | |
3326 | /* Program swing margin */ | |
f72df8db VS |
3327 | for (i = 0; i < 4; i++) { |
3328 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
1fb44505 VS |
3329 | val &= ~DPIO_SWING_MARGIN000_MASK; |
3330 | val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; | |
f72df8db VS |
3331 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
3332 | } | |
e4a1d846 CML |
3333 | |
3334 | /* Disable unique transition scale */ | |
f72df8db VS |
3335 | for (i = 0; i < 4; i++) { |
3336 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
3337 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
3338 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
3339 | } | |
e4a1d846 CML |
3340 | |
3341 | if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) | |
bd60018a | 3342 | == DP_TRAIN_PRE_EMPH_LEVEL_0) && |
e4a1d846 | 3343 | ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) |
bd60018a | 3344 | == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) { |
e4a1d846 CML |
3345 | |
3346 | /* | |
3347 | * The document said it needs to set bit 27 for ch0 and bit 26 | |
3348 | * for ch1. Might be a typo in the doc. | |
3349 | * For now, for this unique transition scale selection, set bit | |
3350 | * 27 for ch0 and ch1. | |
3351 | */ | |
f72df8db VS |
3352 | for (i = 0; i < 4; i++) { |
3353 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
3354 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
3355 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
3356 | } | |
e4a1d846 | 3357 | |
f72df8db VS |
3358 | for (i = 0; i < 4; i++) { |
3359 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
3360 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); | |
3361 | val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT); | |
3362 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); | |
3363 | } | |
e4a1d846 CML |
3364 | } |
3365 | ||
3366 | /* Start swing calculation */ | |
1966e59e VS |
3367 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
3368 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
3369 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
3370 | ||
3371 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
3372 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
3373 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
e4a1d846 CML |
3374 | |
3375 | /* LRC Bypass */ | |
3376 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); | |
3377 | val |= DPIO_LRC_BYPASS; | |
3378 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); | |
3379 | ||
3380 | mutex_unlock(&dev_priv->dpio_lock); | |
3381 | ||
3382 | return 0; | |
3383 | } | |
3384 | ||
a4fc5ed6 | 3385 | static void |
0301b3ac JN |
3386 | intel_get_adjust_train(struct intel_dp *intel_dp, |
3387 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) | |
a4fc5ed6 KP |
3388 | { |
3389 | uint8_t v = 0; | |
3390 | uint8_t p = 0; | |
3391 | int lane; | |
1a2eb460 KP |
3392 | uint8_t voltage_max; |
3393 | uint8_t preemph_max; | |
a4fc5ed6 | 3394 | |
33a34e4e | 3395 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
0f037bde DV |
3396 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
3397 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); | |
a4fc5ed6 KP |
3398 | |
3399 | if (this_v > v) | |
3400 | v = this_v; | |
3401 | if (this_p > p) | |
3402 | p = this_p; | |
3403 | } | |
3404 | ||
1a2eb460 | 3405 | voltage_max = intel_dp_voltage_max(intel_dp); |
417e822d KP |
3406 | if (v >= voltage_max) |
3407 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; | |
a4fc5ed6 | 3408 | |
1a2eb460 KP |
3409 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
3410 | if (p >= preemph_max) | |
3411 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
a4fc5ed6 KP |
3412 | |
3413 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 3414 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
3415 | } |
3416 | ||
3417 | static uint32_t | |
f0a3424e | 3418 | intel_gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 3419 | { |
3cf2efb1 | 3420 | uint32_t signal_levels = 0; |
a4fc5ed6 | 3421 | |
3cf2efb1 | 3422 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3423 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
a4fc5ed6 KP |
3424 | default: |
3425 | signal_levels |= DP_VOLTAGE_0_4; | |
3426 | break; | |
bd60018a | 3427 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
a4fc5ed6 KP |
3428 | signal_levels |= DP_VOLTAGE_0_6; |
3429 | break; | |
bd60018a | 3430 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
a4fc5ed6 KP |
3431 | signal_levels |= DP_VOLTAGE_0_8; |
3432 | break; | |
bd60018a | 3433 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
a4fc5ed6 KP |
3434 | signal_levels |= DP_VOLTAGE_1_2; |
3435 | break; | |
3436 | } | |
3cf2efb1 | 3437 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
bd60018a | 3438 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
a4fc5ed6 KP |
3439 | default: |
3440 | signal_levels |= DP_PRE_EMPHASIS_0; | |
3441 | break; | |
bd60018a | 3442 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
a4fc5ed6 KP |
3443 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3444 | break; | |
bd60018a | 3445 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
a4fc5ed6 KP |
3446 | signal_levels |= DP_PRE_EMPHASIS_6; |
3447 | break; | |
bd60018a | 3448 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
a4fc5ed6 KP |
3449 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3450 | break; | |
3451 | } | |
3452 | return signal_levels; | |
3453 | } | |
3454 | ||
e3421a18 ZW |
3455 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3456 | static uint32_t | |
3457 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
3458 | { | |
3c5a62b5 YL |
3459 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3460 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3461 | switch (signal_levels) { | |
bd60018a SJ |
3462 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3463 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3464 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
bd60018a | 3465 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3c5a62b5 | 3466 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
bd60018a SJ |
3467 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3468 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
3c5a62b5 | 3469 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
bd60018a SJ |
3470 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3471 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
3c5a62b5 | 3472 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
bd60018a SJ |
3473 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3474 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3475 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
e3421a18 | 3476 | default: |
3c5a62b5 YL |
3477 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3478 | "0x%x\n", signal_levels); | |
3479 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
3480 | } |
3481 | } | |
3482 | ||
1a2eb460 KP |
3483 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3484 | static uint32_t | |
3485 | intel_gen7_edp_signal_levels(uint8_t train_set) | |
3486 | { | |
3487 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
3488 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3489 | switch (signal_levels) { | |
bd60018a | 3490 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3491 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
bd60018a | 3492 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 | 3493 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
bd60018a | 3494 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
1a2eb460 KP |
3495 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3496 | ||
bd60018a | 3497 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3498 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
bd60018a | 3499 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3500 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3501 | ||
bd60018a | 3502 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3503 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
bd60018a | 3504 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3505 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3506 | ||
3507 | default: | |
3508 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
3509 | "0x%x\n", signal_levels); | |
3510 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
3511 | } | |
3512 | } | |
3513 | ||
d6c0d722 PZ |
3514 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
3515 | static uint32_t | |
f0a3424e | 3516 | intel_hsw_signal_levels(uint8_t train_set) |
a4fc5ed6 | 3517 | { |
d6c0d722 PZ |
3518 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3519 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3520 | switch (signal_levels) { | |
bd60018a | 3521 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
c5fe6a06 | 3522 | return DDI_BUF_TRANS_SELECT(0); |
bd60018a | 3523 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
c5fe6a06 | 3524 | return DDI_BUF_TRANS_SELECT(1); |
bd60018a | 3525 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
c5fe6a06 | 3526 | return DDI_BUF_TRANS_SELECT(2); |
bd60018a | 3527 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: |
c5fe6a06 | 3528 | return DDI_BUF_TRANS_SELECT(3); |
a4fc5ed6 | 3529 | |
bd60018a | 3530 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
c5fe6a06 | 3531 | return DDI_BUF_TRANS_SELECT(4); |
bd60018a | 3532 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
c5fe6a06 | 3533 | return DDI_BUF_TRANS_SELECT(5); |
bd60018a | 3534 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
c5fe6a06 | 3535 | return DDI_BUF_TRANS_SELECT(6); |
a4fc5ed6 | 3536 | |
bd60018a | 3537 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
c5fe6a06 | 3538 | return DDI_BUF_TRANS_SELECT(7); |
bd60018a | 3539 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
c5fe6a06 | 3540 | return DDI_BUF_TRANS_SELECT(8); |
d6c0d722 PZ |
3541 | default: |
3542 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
3543 | "0x%x\n", signal_levels); | |
c5fe6a06 | 3544 | return DDI_BUF_TRANS_SELECT(0); |
a4fc5ed6 | 3545 | } |
a4fc5ed6 KP |
3546 | } |
3547 | ||
f0a3424e PZ |
3548 | /* Properly updates "DP" with the correct signal levels. */ |
3549 | static void | |
3550 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) | |
3551 | { | |
3552 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 3553 | enum port port = intel_dig_port->port; |
f0a3424e PZ |
3554 | struct drm_device *dev = intel_dig_port->base.base.dev; |
3555 | uint32_t signal_levels, mask; | |
3556 | uint8_t train_set = intel_dp->train_set[0]; | |
3557 | ||
5a9d1f1a | 3558 | if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
f0a3424e PZ |
3559 | signal_levels = intel_hsw_signal_levels(train_set); |
3560 | mask = DDI_BUF_EMP_MASK; | |
e4a1d846 CML |
3561 | } else if (IS_CHERRYVIEW(dev)) { |
3562 | signal_levels = intel_chv_signal_levels(intel_dp); | |
3563 | mask = 0; | |
e2fa6fba P |
3564 | } else if (IS_VALLEYVIEW(dev)) { |
3565 | signal_levels = intel_vlv_signal_levels(intel_dp); | |
3566 | mask = 0; | |
bc7d38a4 | 3567 | } else if (IS_GEN7(dev) && port == PORT_A) { |
f0a3424e PZ |
3568 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
3569 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; | |
bc7d38a4 | 3570 | } else if (IS_GEN6(dev) && port == PORT_A) { |
f0a3424e PZ |
3571 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
3572 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; | |
3573 | } else { | |
3574 | signal_levels = intel_gen4_signal_levels(train_set); | |
3575 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; | |
3576 | } | |
3577 | ||
3578 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
3579 | ||
3580 | *DP = (*DP & ~mask) | signal_levels; | |
3581 | } | |
3582 | ||
a4fc5ed6 | 3583 | static bool |
ea5b213a | 3584 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
70aff66c | 3585 | uint32_t *DP, |
58e10eb9 | 3586 | uint8_t dp_train_pat) |
a4fc5ed6 | 3587 | { |
174edf1f PZ |
3588 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3589 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
a4fc5ed6 | 3590 | struct drm_i915_private *dev_priv = dev->dev_private; |
2cdfe6c8 JN |
3591 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
3592 | int ret, len; | |
a4fc5ed6 | 3593 | |
7b13b58a | 3594 | _intel_dp_set_link_train(intel_dp, DP, dp_train_pat); |
47ea7542 | 3595 | |
70aff66c | 3596 | I915_WRITE(intel_dp->output_reg, *DP); |
ea5b213a | 3597 | POSTING_READ(intel_dp->output_reg); |
a4fc5ed6 | 3598 | |
2cdfe6c8 JN |
3599 | buf[0] = dp_train_pat; |
3600 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == | |
47ea7542 | 3601 | DP_TRAINING_PATTERN_DISABLE) { |
2cdfe6c8 JN |
3602 | /* don't write DP_TRAINING_LANEx_SET on disable */ |
3603 | len = 1; | |
3604 | } else { | |
3605 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ | |
3606 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); | |
3607 | len = intel_dp->lane_count + 1; | |
47ea7542 | 3608 | } |
a4fc5ed6 | 3609 | |
9d1a1031 JN |
3610 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, |
3611 | buf, len); | |
2cdfe6c8 JN |
3612 | |
3613 | return ret == len; | |
a4fc5ed6 KP |
3614 | } |
3615 | ||
70aff66c JN |
3616 | static bool |
3617 | intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, | |
3618 | uint8_t dp_train_pat) | |
3619 | { | |
953d22e8 | 3620 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); |
70aff66c JN |
3621 | intel_dp_set_signal_levels(intel_dp, DP); |
3622 | return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); | |
3623 | } | |
3624 | ||
3625 | static bool | |
3626 | intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, | |
0301b3ac | 3627 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
70aff66c JN |
3628 | { |
3629 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3630 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
3631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3632 | int ret; | |
3633 | ||
3634 | intel_get_adjust_train(intel_dp, link_status); | |
3635 | intel_dp_set_signal_levels(intel_dp, DP); | |
3636 | ||
3637 | I915_WRITE(intel_dp->output_reg, *DP); | |
3638 | POSTING_READ(intel_dp->output_reg); | |
3639 | ||
9d1a1031 JN |
3640 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, |
3641 | intel_dp->train_set, intel_dp->lane_count); | |
70aff66c JN |
3642 | |
3643 | return ret == intel_dp->lane_count; | |
3644 | } | |
3645 | ||
3ab9c637 ID |
3646 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3647 | { | |
3648 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3649 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
3650 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3651 | enum port port = intel_dig_port->port; | |
3652 | uint32_t val; | |
3653 | ||
3654 | if (!HAS_DDI(dev)) | |
3655 | return; | |
3656 | ||
3657 | val = I915_READ(DP_TP_CTL(port)); | |
3658 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
3659 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
3660 | I915_WRITE(DP_TP_CTL(port), val); | |
3661 | ||
3662 | /* | |
3663 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
3664 | * we need to set idle transmission mode is to work around a HW issue | |
3665 | * where we enable the pipe while not in idle link-training mode. | |
3666 | * In this case there is requirement to wait for a minimum number of | |
3667 | * idle patterns to be sent. | |
3668 | */ | |
3669 | if (port == PORT_A) | |
3670 | return; | |
3671 | ||
3672 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), | |
3673 | 1)) | |
3674 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); | |
3675 | } | |
3676 | ||
33a34e4e | 3677 | /* Enable corresponding port and start training pattern 1 */ |
c19b0669 | 3678 | void |
33a34e4e | 3679 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 3680 | { |
da63a9f2 | 3681 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
c19b0669 | 3682 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 KP |
3683 | int i; |
3684 | uint8_t voltage; | |
cdb0e95b | 3685 | int voltage_tries, loop_tries; |
ea5b213a | 3686 | uint32_t DP = intel_dp->DP; |
6aba5b6c | 3687 | uint8_t link_config[2]; |
a4fc5ed6 | 3688 | |
affa9354 | 3689 | if (HAS_DDI(dev)) |
c19b0669 PZ |
3690 | intel_ddi_prepare_link_retrain(encoder); |
3691 | ||
3cf2efb1 | 3692 | /* Write the link configuration data */ |
6aba5b6c JN |
3693 | link_config[0] = intel_dp->link_bw; |
3694 | link_config[1] = intel_dp->lane_count; | |
3695 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
3696 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; | |
9d1a1031 | 3697 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); |
6aba5b6c JN |
3698 | |
3699 | link_config[0] = 0; | |
3700 | link_config[1] = DP_SET_ANSI_8B10B; | |
9d1a1031 | 3701 | drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); |
a4fc5ed6 KP |
3702 | |
3703 | DP |= DP_PORT_EN; | |
1a2eb460 | 3704 | |
70aff66c JN |
3705 | /* clock recovery */ |
3706 | if (!intel_dp_reset_link_train(intel_dp, &DP, | |
3707 | DP_TRAINING_PATTERN_1 | | |
3708 | DP_LINK_SCRAMBLING_DISABLE)) { | |
3709 | DRM_ERROR("failed to enable link training\n"); | |
3710 | return; | |
3711 | } | |
3712 | ||
a4fc5ed6 | 3713 | voltage = 0xff; |
cdb0e95b KP |
3714 | voltage_tries = 0; |
3715 | loop_tries = 0; | |
a4fc5ed6 | 3716 | for (;;) { |
70aff66c | 3717 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
a4fc5ed6 | 3718 | |
a7c9655f | 3719 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
93f62dad KP |
3720 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
3721 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 3722 | break; |
93f62dad | 3723 | } |
a4fc5ed6 | 3724 | |
01916270 | 3725 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
93f62dad | 3726 | DRM_DEBUG_KMS("clock recovery OK\n"); |
3cf2efb1 CW |
3727 | break; |
3728 | } | |
3729 | ||
3730 | /* Check to see if we've tried the max voltage */ | |
3731 | for (i = 0; i < intel_dp->lane_count; i++) | |
3732 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 3733 | break; |
3b4f819d | 3734 | if (i == intel_dp->lane_count) { |
b06fbda3 DV |
3735 | ++loop_tries; |
3736 | if (loop_tries == 5) { | |
3def84b3 | 3737 | DRM_ERROR("too many full retries, give up\n"); |
cdb0e95b KP |
3738 | break; |
3739 | } | |
70aff66c JN |
3740 | intel_dp_reset_link_train(intel_dp, &DP, |
3741 | DP_TRAINING_PATTERN_1 | | |
3742 | DP_LINK_SCRAMBLING_DISABLE); | |
cdb0e95b KP |
3743 | voltage_tries = 0; |
3744 | continue; | |
3745 | } | |
a4fc5ed6 | 3746 | |
3cf2efb1 | 3747 | /* Check to see if we've tried the same voltage 5 times */ |
b06fbda3 | 3748 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
24773670 | 3749 | ++voltage_tries; |
b06fbda3 | 3750 | if (voltage_tries == 5) { |
3def84b3 | 3751 | DRM_ERROR("too many voltage retries, give up\n"); |
b06fbda3 DV |
3752 | break; |
3753 | } | |
3754 | } else | |
3755 | voltage_tries = 0; | |
3756 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 3757 | |
70aff66c JN |
3758 | /* Update training set as requested by target */ |
3759 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { | |
3760 | DRM_ERROR("failed to update link training\n"); | |
3761 | break; | |
3762 | } | |
a4fc5ed6 KP |
3763 | } |
3764 | ||
33a34e4e JB |
3765 | intel_dp->DP = DP; |
3766 | } | |
3767 | ||
c19b0669 | 3768 | void |
33a34e4e JB |
3769 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
3770 | { | |
33a34e4e | 3771 | bool channel_eq = false; |
37f80975 | 3772 | int tries, cr_tries; |
33a34e4e | 3773 | uint32_t DP = intel_dp->DP; |
06ea66b6 TP |
3774 | uint32_t training_pattern = DP_TRAINING_PATTERN_2; |
3775 | ||
3776 | /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ | |
3777 | if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) | |
3778 | training_pattern = DP_TRAINING_PATTERN_3; | |
33a34e4e | 3779 | |
a4fc5ed6 | 3780 | /* channel equalization */ |
70aff66c | 3781 | if (!intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 3782 | training_pattern | |
70aff66c JN |
3783 | DP_LINK_SCRAMBLING_DISABLE)) { |
3784 | DRM_ERROR("failed to start channel equalization\n"); | |
3785 | return; | |
3786 | } | |
3787 | ||
a4fc5ed6 | 3788 | tries = 0; |
37f80975 | 3789 | cr_tries = 0; |
a4fc5ed6 KP |
3790 | channel_eq = false; |
3791 | for (;;) { | |
70aff66c | 3792 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
e3421a18 | 3793 | |
37f80975 JB |
3794 | if (cr_tries > 5) { |
3795 | DRM_ERROR("failed to train DP, aborting\n"); | |
37f80975 JB |
3796 | break; |
3797 | } | |
3798 | ||
a7c9655f | 3799 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
70aff66c JN |
3800 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
3801 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 3802 | break; |
70aff66c | 3803 | } |
a4fc5ed6 | 3804 | |
37f80975 | 3805 | /* Make sure clock is still ok */ |
01916270 | 3806 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
37f80975 | 3807 | intel_dp_start_link_train(intel_dp); |
70aff66c | 3808 | intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 3809 | training_pattern | |
70aff66c | 3810 | DP_LINK_SCRAMBLING_DISABLE); |
37f80975 JB |
3811 | cr_tries++; |
3812 | continue; | |
3813 | } | |
3814 | ||
1ffdff13 | 3815 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
3cf2efb1 CW |
3816 | channel_eq = true; |
3817 | break; | |
3818 | } | |
a4fc5ed6 | 3819 | |
37f80975 JB |
3820 | /* Try 5 times, then try clock recovery if that fails */ |
3821 | if (tries > 5) { | |
37f80975 | 3822 | intel_dp_start_link_train(intel_dp); |
70aff66c | 3823 | intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 3824 | training_pattern | |
70aff66c | 3825 | DP_LINK_SCRAMBLING_DISABLE); |
37f80975 JB |
3826 | tries = 0; |
3827 | cr_tries++; | |
3828 | continue; | |
3829 | } | |
a4fc5ed6 | 3830 | |
70aff66c JN |
3831 | /* Update training set as requested by target */ |
3832 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { | |
3833 | DRM_ERROR("failed to update link training\n"); | |
3834 | break; | |
3835 | } | |
3cf2efb1 | 3836 | ++tries; |
869184a6 | 3837 | } |
3cf2efb1 | 3838 | |
3ab9c637 ID |
3839 | intel_dp_set_idle_link_train(intel_dp); |
3840 | ||
3841 | intel_dp->DP = DP; | |
3842 | ||
d6c0d722 | 3843 | if (channel_eq) |
07f42258 | 3844 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
d6c0d722 | 3845 | |
3ab9c637 ID |
3846 | } |
3847 | ||
3848 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) | |
3849 | { | |
70aff66c | 3850 | intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
3ab9c637 | 3851 | DP_TRAINING_PATTERN_DISABLE); |
a4fc5ed6 KP |
3852 | } |
3853 | ||
3854 | static void | |
ea5b213a | 3855 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 3856 | { |
da63a9f2 | 3857 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
bc7d38a4 | 3858 | enum port port = intel_dig_port->port; |
da63a9f2 | 3859 | struct drm_device *dev = intel_dig_port->base.base.dev; |
a4fc5ed6 | 3860 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab527efc DV |
3861 | struct intel_crtc *intel_crtc = |
3862 | to_intel_crtc(intel_dig_port->base.base.crtc); | |
ea5b213a | 3863 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 3864 | |
bc76e320 | 3865 | if (WARN_ON(HAS_DDI(dev))) |
c19b0669 PZ |
3866 | return; |
3867 | ||
0c33d8d7 | 3868 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
3869 | return; |
3870 | ||
28c97730 | 3871 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 3872 | |
bc7d38a4 | 3873 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
e3421a18 | 3874 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 3875 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 | 3876 | } else { |
aad3d14d VS |
3877 | if (IS_CHERRYVIEW(dev)) |
3878 | DP &= ~DP_LINK_TRAIN_MASK_CHV; | |
3879 | else | |
3880 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 3881 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 3882 | } |
fe255d00 | 3883 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 3884 | |
493a7081 | 3885 | if (HAS_PCH_IBX(dev) && |
1b39d6f3 | 3886 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
da63a9f2 | 3887 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
31acbcc4 | 3888 | |
5bddd17f EA |
3889 | /* Hardware workaround: leaving our transcoder select |
3890 | * set to transcoder B while it's off will prevent the | |
3891 | * corresponding HDMI output on transcoder A. | |
3892 | * | |
3893 | * Combine this with another hardware workaround: | |
3894 | * transcoder select bit can only be cleared while the | |
3895 | * port is enabled. | |
3896 | */ | |
3897 | DP &= ~DP_PIPEB_SELECT; | |
3898 | I915_WRITE(intel_dp->output_reg, DP); | |
3899 | ||
3900 | /* Changes to enable or select take place the vblank | |
3901 | * after being written. | |
3902 | */ | |
ff50afe9 DV |
3903 | if (WARN_ON(crtc == NULL)) { |
3904 | /* We should never try to disable a port without a crtc | |
3905 | * attached. For paranoia keep the code around for a | |
3906 | * bit. */ | |
31acbcc4 CW |
3907 | POSTING_READ(intel_dp->output_reg); |
3908 | msleep(50); | |
3909 | } else | |
ab527efc | 3910 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
5bddd17f EA |
3911 | } |
3912 | ||
832afda6 | 3913 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
ea5b213a CW |
3914 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
3915 | POSTING_READ(intel_dp->output_reg); | |
f01eca2e | 3916 | msleep(intel_dp->panel_power_down_delay); |
a4fc5ed6 KP |
3917 | } |
3918 | ||
26d61aad KP |
3919 | static bool |
3920 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 3921 | { |
a031d709 RV |
3922 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3923 | struct drm_device *dev = dig_port->base.base.dev; | |
3924 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3925 | ||
9d1a1031 JN |
3926 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3927 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 3928 | return false; /* aux transfer failed */ |
92fd8fd1 | 3929 | |
a8e98153 | 3930 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
577c7a50 | 3931 | |
edb39244 AJ |
3932 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
3933 | return false; /* DPCD not present */ | |
3934 | ||
2293bb5c SK |
3935 | /* Check if the panel supports PSR */ |
3936 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); | |
50003939 | 3937 | if (is_edp(intel_dp)) { |
9d1a1031 JN |
3938 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
3939 | intel_dp->psr_dpcd, | |
3940 | sizeof(intel_dp->psr_dpcd)); | |
a031d709 RV |
3941 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
3942 | dev_priv->psr.sink_support = true; | |
50003939 | 3943 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
a031d709 | 3944 | } |
50003939 JN |
3945 | } |
3946 | ||
06ea66b6 TP |
3947 | /* Training Pattern 3 support */ |
3948 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && | |
3949 | intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { | |
3950 | intel_dp->use_tps3 = true; | |
f8d8a672 | 3951 | DRM_DEBUG_KMS("Displayport TPS3 supported\n"); |
06ea66b6 TP |
3952 | } else |
3953 | intel_dp->use_tps3 = false; | |
3954 | ||
edb39244 AJ |
3955 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
3956 | DP_DWN_STRM_PORT_PRESENT)) | |
3957 | return true; /* native DP sink */ | |
3958 | ||
3959 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
3960 | return true; /* no per-port downstream info */ | |
3961 | ||
9d1a1031 JN |
3962 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3963 | intel_dp->downstream_ports, | |
3964 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
3965 | return false; /* downstream port status fetch failed */ |
3966 | ||
3967 | return true; | |
92fd8fd1 KP |
3968 | } |
3969 | ||
0d198328 AJ |
3970 | static void |
3971 | intel_dp_probe_oui(struct intel_dp *intel_dp) | |
3972 | { | |
3973 | u8 buf[3]; | |
3974 | ||
3975 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
3976 | return; | |
3977 | ||
9d1a1031 | 3978 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
0d198328 AJ |
3979 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
3980 | buf[0], buf[1], buf[2]); | |
3981 | ||
9d1a1031 | 3982 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
0d198328 AJ |
3983 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
3984 | buf[0], buf[1], buf[2]); | |
3985 | } | |
3986 | ||
0e32b39c DA |
3987 | static bool |
3988 | intel_dp_probe_mst(struct intel_dp *intel_dp) | |
3989 | { | |
3990 | u8 buf[1]; | |
3991 | ||
3992 | if (!intel_dp->can_mst) | |
3993 | return false; | |
3994 | ||
3995 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) | |
3996 | return false; | |
3997 | ||
0e32b39c DA |
3998 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
3999 | if (buf[0] & DP_MST_CAP) { | |
4000 | DRM_DEBUG_KMS("Sink is MST capable\n"); | |
4001 | intel_dp->is_mst = true; | |
4002 | } else { | |
4003 | DRM_DEBUG_KMS("Sink is not MST capable\n"); | |
4004 | intel_dp->is_mst = false; | |
4005 | } | |
4006 | } | |
0e32b39c DA |
4007 | |
4008 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
4009 | return intel_dp->is_mst; | |
4010 | } | |
4011 | ||
d2e216d0 RV |
4012 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
4013 | { | |
4014 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4015 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
4016 | struct intel_crtc *intel_crtc = | |
4017 | to_intel_crtc(intel_dig_port->base.base.crtc); | |
ad9dc91b RV |
4018 | u8 buf; |
4019 | int test_crc_count; | |
4020 | int attempts = 6; | |
d2e216d0 | 4021 | |
ad9dc91b | 4022 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
bda0381e | 4023 | return -EIO; |
d2e216d0 | 4024 | |
ad9dc91b | 4025 | if (!(buf & DP_TEST_CRC_SUPPORTED)) |
d2e216d0 RV |
4026 | return -ENOTTY; |
4027 | ||
1dda5f93 RV |
4028 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
4029 | return -EIO; | |
4030 | ||
9d1a1031 | 4031 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
ce31d9f4 | 4032 | buf | DP_TEST_SINK_START) < 0) |
bda0381e | 4033 | return -EIO; |
d2e216d0 | 4034 | |
1dda5f93 | 4035 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
bda0381e | 4036 | return -EIO; |
ad9dc91b | 4037 | test_crc_count = buf & DP_TEST_COUNT_MASK; |
d2e216d0 | 4038 | |
ad9dc91b | 4039 | do { |
1dda5f93 RV |
4040 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4041 | DP_TEST_SINK_MISC, &buf) < 0) | |
4042 | return -EIO; | |
ad9dc91b RV |
4043 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
4044 | } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count); | |
4045 | ||
4046 | if (attempts == 0) { | |
4047 | DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n"); | |
4048 | return -EIO; | |
4049 | } | |
d2e216d0 | 4050 | |
9d1a1031 | 4051 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) |
bda0381e | 4052 | return -EIO; |
d2e216d0 | 4053 | |
1dda5f93 RV |
4054 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) |
4055 | return -EIO; | |
4056 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, | |
4057 | buf & ~DP_TEST_SINK_START) < 0) | |
4058 | return -EIO; | |
ce31d9f4 | 4059 | |
d2e216d0 RV |
4060 | return 0; |
4061 | } | |
4062 | ||
a60f0e38 JB |
4063 | static bool |
4064 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
4065 | { | |
9d1a1031 JN |
4066 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
4067 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4068 | sink_irq_vector, 1) == 1; | |
a60f0e38 JB |
4069 | } |
4070 | ||
0e32b39c DA |
4071 | static bool |
4072 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
4073 | { | |
4074 | int ret; | |
4075 | ||
4076 | ret = intel_dp_dpcd_read_wake(&intel_dp->aux, | |
4077 | DP_SINK_COUNT_ESI, | |
4078 | sink_irq_vector, 14); | |
4079 | if (ret != 14) | |
4080 | return false; | |
4081 | ||
4082 | return true; | |
4083 | } | |
4084 | ||
a60f0e38 JB |
4085 | static void |
4086 | intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
4087 | { | |
4088 | /* NAK by default */ | |
9d1a1031 | 4089 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); |
a60f0e38 JB |
4090 | } |
4091 | ||
0e32b39c DA |
4092 | static int |
4093 | intel_dp_check_mst_status(struct intel_dp *intel_dp) | |
4094 | { | |
4095 | bool bret; | |
4096 | ||
4097 | if (intel_dp->is_mst) { | |
4098 | u8 esi[16] = { 0 }; | |
4099 | int ret = 0; | |
4100 | int retry; | |
4101 | bool handled; | |
4102 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
4103 | go_again: | |
4104 | if (bret == true) { | |
4105 | ||
4106 | /* check link status - esi[10] = 0x200c */ | |
4107 | if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { | |
4108 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); | |
4109 | intel_dp_start_link_train(intel_dp); | |
4110 | intel_dp_complete_link_train(intel_dp); | |
4111 | intel_dp_stop_link_train(intel_dp); | |
4112 | } | |
4113 | ||
4114 | DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]); | |
4115 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); | |
4116 | ||
4117 | if (handled) { | |
4118 | for (retry = 0; retry < 3; retry++) { | |
4119 | int wret; | |
4120 | wret = drm_dp_dpcd_write(&intel_dp->aux, | |
4121 | DP_SINK_COUNT_ESI+1, | |
4122 | &esi[1], 3); | |
4123 | if (wret == 3) { | |
4124 | break; | |
4125 | } | |
4126 | } | |
4127 | ||
4128 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
4129 | if (bret == true) { | |
4130 | DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]); | |
4131 | goto go_again; | |
4132 | } | |
4133 | } else | |
4134 | ret = 0; | |
4135 | ||
4136 | return ret; | |
4137 | } else { | |
4138 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4139 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); | |
4140 | intel_dp->is_mst = false; | |
4141 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
4142 | /* send a hotplug event */ | |
4143 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); | |
4144 | } | |
4145 | } | |
4146 | return -EINVAL; | |
4147 | } | |
4148 | ||
a4fc5ed6 KP |
4149 | /* |
4150 | * According to DP spec | |
4151 | * 5.1.2: | |
4152 | * 1. Read DPCD | |
4153 | * 2. Configure link according to Receiver Capabilities | |
4154 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
4155 | * 4. Check link status on receipt of hot-plug interrupt | |
4156 | */ | |
00c09d70 | 4157 | void |
ea5b213a | 4158 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 4159 | { |
5b215bcf | 4160 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
da63a9f2 | 4161 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
a60f0e38 | 4162 | u8 sink_irq_vector; |
93f62dad | 4163 | u8 link_status[DP_LINK_STATUS_SIZE]; |
a60f0e38 | 4164 | |
5b215bcf DA |
4165 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
4166 | ||
da63a9f2 | 4167 | if (!intel_encoder->connectors_active) |
d2b996ac | 4168 | return; |
59cd09e1 | 4169 | |
da63a9f2 | 4170 | if (WARN_ON(!intel_encoder->base.crtc)) |
a4fc5ed6 KP |
4171 | return; |
4172 | ||
1a125d8a ID |
4173 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) |
4174 | return; | |
4175 | ||
92fd8fd1 | 4176 | /* Try to read receiver status if the link appears to be up */ |
93f62dad | 4177 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
a4fc5ed6 KP |
4178 | return; |
4179 | } | |
4180 | ||
92fd8fd1 | 4181 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 4182 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
4183 | return; |
4184 | } | |
4185 | ||
a60f0e38 JB |
4186 | /* Try to read the source of the interrupt */ |
4187 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
4188 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
4189 | /* Clear interrupt source */ | |
9d1a1031 JN |
4190 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4191 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4192 | sink_irq_vector); | |
a60f0e38 JB |
4193 | |
4194 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
4195 | intel_dp_handle_test_request(intel_dp); | |
4196 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
4197 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4198 | } | |
4199 | ||
1ffdff13 | 4200 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
92fd8fd1 | 4201 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
8e329a03 | 4202 | intel_encoder->base.name); |
33a34e4e JB |
4203 | intel_dp_start_link_train(intel_dp); |
4204 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 | 4205 | intel_dp_stop_link_train(intel_dp); |
33a34e4e | 4206 | } |
a4fc5ed6 | 4207 | } |
a4fc5ed6 | 4208 | |
caf9ab24 | 4209 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 4210 | static enum drm_connector_status |
26d61aad | 4211 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 4212 | { |
caf9ab24 | 4213 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
4214 | uint8_t type; |
4215 | ||
4216 | if (!intel_dp_get_dpcd(intel_dp)) | |
4217 | return connector_status_disconnected; | |
4218 | ||
4219 | /* if there's no downstream port, we're done */ | |
4220 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) | |
26d61aad | 4221 | return connector_status_connected; |
caf9ab24 AJ |
4222 | |
4223 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
4224 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4225 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
23235177 | 4226 | uint8_t reg; |
9d1a1031 JN |
4227 | |
4228 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, | |
4229 | ®, 1) < 0) | |
caf9ab24 | 4230 | return connector_status_unknown; |
9d1a1031 | 4231 | |
23235177 AJ |
4232 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
4233 | : connector_status_disconnected; | |
caf9ab24 AJ |
4234 | } |
4235 | ||
4236 | /* If no HPD, poke DDC gently */ | |
0b99836f | 4237 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 4238 | return connector_status_connected; |
caf9ab24 AJ |
4239 | |
4240 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
4241 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4242 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
4243 | if (type == DP_DS_PORT_TYPE_VGA || | |
4244 | type == DP_DS_PORT_TYPE_NON_EDID) | |
4245 | return connector_status_unknown; | |
4246 | } else { | |
4247 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
4248 | DP_DWN_STRM_PORT_TYPE_MASK; | |
4249 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
4250 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
4251 | return connector_status_unknown; | |
4252 | } | |
caf9ab24 AJ |
4253 | |
4254 | /* Anything else is out of spec, warn and ignore */ | |
4255 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 4256 | return connector_status_disconnected; |
71ba9000 AJ |
4257 | } |
4258 | ||
d410b56d CW |
4259 | static enum drm_connector_status |
4260 | edp_detect(struct intel_dp *intel_dp) | |
4261 | { | |
4262 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
4263 | enum drm_connector_status status; | |
4264 | ||
4265 | status = intel_panel_detect(dev); | |
4266 | if (status == connector_status_unknown) | |
4267 | status = connector_status_connected; | |
4268 | ||
4269 | return status; | |
4270 | } | |
4271 | ||
5eb08b69 | 4272 | static enum drm_connector_status |
a9756bb5 | 4273 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 4274 | { |
30add22d | 4275 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1b469639 DL |
4276 | struct drm_i915_private *dev_priv = dev->dev_private; |
4277 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
01cb9ea6 | 4278 | |
1b469639 DL |
4279 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
4280 | return connector_status_disconnected; | |
4281 | ||
26d61aad | 4282 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
4283 | } |
4284 | ||
2a592bec DA |
4285 | static int g4x_digital_port_connected(struct drm_device *dev, |
4286 | struct intel_digital_port *intel_dig_port) | |
a4fc5ed6 | 4287 | { |
a4fc5ed6 | 4288 | struct drm_i915_private *dev_priv = dev->dev_private; |
10f76a38 | 4289 | uint32_t bit; |
5eb08b69 | 4290 | |
232a6ee9 TP |
4291 | if (IS_VALLEYVIEW(dev)) { |
4292 | switch (intel_dig_port->port) { | |
4293 | case PORT_B: | |
4294 | bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; | |
4295 | break; | |
4296 | case PORT_C: | |
4297 | bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; | |
4298 | break; | |
4299 | case PORT_D: | |
4300 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; | |
4301 | break; | |
4302 | default: | |
2a592bec | 4303 | return -EINVAL; |
232a6ee9 TP |
4304 | } |
4305 | } else { | |
4306 | switch (intel_dig_port->port) { | |
4307 | case PORT_B: | |
4308 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; | |
4309 | break; | |
4310 | case PORT_C: | |
4311 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; | |
4312 | break; | |
4313 | case PORT_D: | |
4314 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | |
4315 | break; | |
4316 | default: | |
2a592bec | 4317 | return -EINVAL; |
232a6ee9 | 4318 | } |
a4fc5ed6 KP |
4319 | } |
4320 | ||
10f76a38 | 4321 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
2a592bec DA |
4322 | return 0; |
4323 | return 1; | |
4324 | } | |
4325 | ||
4326 | static enum drm_connector_status | |
4327 | g4x_dp_detect(struct intel_dp *intel_dp) | |
4328 | { | |
4329 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
4330 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4331 | int ret; | |
4332 | ||
4333 | /* Can't disconnect eDP, but you can close the lid... */ | |
4334 | if (is_edp(intel_dp)) { | |
4335 | enum drm_connector_status status; | |
4336 | ||
4337 | status = intel_panel_detect(dev); | |
4338 | if (status == connector_status_unknown) | |
4339 | status = connector_status_connected; | |
4340 | return status; | |
4341 | } | |
4342 | ||
4343 | ret = g4x_digital_port_connected(dev, intel_dig_port); | |
4344 | if (ret == -EINVAL) | |
4345 | return connector_status_unknown; | |
4346 | else if (ret == 0) | |
a4fc5ed6 KP |
4347 | return connector_status_disconnected; |
4348 | ||
26d61aad | 4349 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
4350 | } |
4351 | ||
8c241fef | 4352 | static struct edid * |
beb60608 | 4353 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 4354 | { |
beb60608 | 4355 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
d6f24d0f | 4356 | |
9cd300e0 JN |
4357 | /* use cached edid if we have one */ |
4358 | if (intel_connector->edid) { | |
9cd300e0 JN |
4359 | /* invalid edid */ |
4360 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
4361 | return NULL; |
4362 | ||
55e9edeb | 4363 | return drm_edid_duplicate(intel_connector->edid); |
beb60608 CW |
4364 | } else |
4365 | return drm_get_edid(&intel_connector->base, | |
4366 | &intel_dp->aux.ddc); | |
4367 | } | |
8c241fef | 4368 | |
beb60608 CW |
4369 | static void |
4370 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
4371 | { | |
4372 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
4373 | struct edid *edid; | |
8c241fef | 4374 | |
beb60608 CW |
4375 | edid = intel_dp_get_edid(intel_dp); |
4376 | intel_connector->detect_edid = edid; | |
4377 | ||
4378 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) | |
4379 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; | |
4380 | else | |
4381 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
8c241fef KP |
4382 | } |
4383 | ||
beb60608 CW |
4384 | static void |
4385 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 4386 | { |
beb60608 | 4387 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8c241fef | 4388 | |
beb60608 CW |
4389 | kfree(intel_connector->detect_edid); |
4390 | intel_connector->detect_edid = NULL; | |
9cd300e0 | 4391 | |
beb60608 CW |
4392 | intel_dp->has_audio = false; |
4393 | } | |
d6f24d0f | 4394 | |
beb60608 CW |
4395 | static enum intel_display_power_domain |
4396 | intel_dp_power_get(struct intel_dp *dp) | |
4397 | { | |
4398 | struct intel_encoder *encoder = &dp_to_dig_port(dp)->base; | |
4399 | enum intel_display_power_domain power_domain; | |
4400 | ||
4401 | power_domain = intel_display_port_power_domain(encoder); | |
4402 | intel_display_power_get(to_i915(encoder->base.dev), power_domain); | |
4403 | ||
4404 | return power_domain; | |
4405 | } | |
d6f24d0f | 4406 | |
beb60608 CW |
4407 | static void |
4408 | intel_dp_power_put(struct intel_dp *dp, | |
4409 | enum intel_display_power_domain power_domain) | |
4410 | { | |
4411 | struct intel_encoder *encoder = &dp_to_dig_port(dp)->base; | |
4412 | intel_display_power_put(to_i915(encoder->base.dev), power_domain); | |
8c241fef KP |
4413 | } |
4414 | ||
a9756bb5 ZW |
4415 | static enum drm_connector_status |
4416 | intel_dp_detect(struct drm_connector *connector, bool force) | |
4417 | { | |
4418 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
d63885da PZ |
4419 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4420 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 4421 | struct drm_device *dev = connector->dev; |
a9756bb5 | 4422 | enum drm_connector_status status; |
671dedd2 | 4423 | enum intel_display_power_domain power_domain; |
0e32b39c | 4424 | bool ret; |
a9756bb5 | 4425 | |
164c8598 | 4426 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 4427 | connector->base.id, connector->name); |
beb60608 | 4428 | intel_dp_unset_edid(intel_dp); |
164c8598 | 4429 | |
0e32b39c DA |
4430 | if (intel_dp->is_mst) { |
4431 | /* MST devices are disconnected from a monitor POV */ | |
4432 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
4433 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
beb60608 | 4434 | return connector_status_disconnected; |
0e32b39c DA |
4435 | } |
4436 | ||
beb60608 | 4437 | power_domain = intel_dp_power_get(intel_dp); |
a9756bb5 | 4438 | |
d410b56d CW |
4439 | /* Can't disconnect eDP, but you can close the lid... */ |
4440 | if (is_edp(intel_dp)) | |
4441 | status = edp_detect(intel_dp); | |
4442 | else if (HAS_PCH_SPLIT(dev)) | |
a9756bb5 ZW |
4443 | status = ironlake_dp_detect(intel_dp); |
4444 | else | |
4445 | status = g4x_dp_detect(intel_dp); | |
4446 | if (status != connector_status_connected) | |
c8c8fb33 | 4447 | goto out; |
a9756bb5 | 4448 | |
0d198328 AJ |
4449 | intel_dp_probe_oui(intel_dp); |
4450 | ||
0e32b39c DA |
4451 | ret = intel_dp_probe_mst(intel_dp); |
4452 | if (ret) { | |
4453 | /* if we are in MST mode then this connector | |
4454 | won't appear connected or have anything with EDID on it */ | |
4455 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
4456 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
4457 | status = connector_status_disconnected; | |
4458 | goto out; | |
4459 | } | |
4460 | ||
beb60608 | 4461 | intel_dp_set_edid(intel_dp); |
a9756bb5 | 4462 | |
d63885da PZ |
4463 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4464 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
c8c8fb33 PZ |
4465 | status = connector_status_connected; |
4466 | ||
4467 | out: | |
beb60608 | 4468 | intel_dp_power_put(intel_dp, power_domain); |
c8c8fb33 | 4469 | return status; |
a4fc5ed6 KP |
4470 | } |
4471 | ||
beb60608 CW |
4472 | static void |
4473 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 4474 | { |
df0e9248 | 4475 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
beb60608 | 4476 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
671dedd2 | 4477 | enum intel_display_power_domain power_domain; |
a4fc5ed6 | 4478 | |
beb60608 CW |
4479 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4480 | connector->base.id, connector->name); | |
4481 | intel_dp_unset_edid(intel_dp); | |
a4fc5ed6 | 4482 | |
beb60608 CW |
4483 | if (connector->status != connector_status_connected) |
4484 | return; | |
671dedd2 | 4485 | |
beb60608 CW |
4486 | power_domain = intel_dp_power_get(intel_dp); |
4487 | ||
4488 | intel_dp_set_edid(intel_dp); | |
4489 | ||
4490 | intel_dp_power_put(intel_dp, power_domain); | |
4491 | ||
4492 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
4493 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
4494 | } | |
4495 | ||
4496 | static int intel_dp_get_modes(struct drm_connector *connector) | |
4497 | { | |
4498 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4499 | struct edid *edid; | |
4500 | ||
4501 | edid = intel_connector->detect_edid; | |
4502 | if (edid) { | |
4503 | int ret = intel_connector_update_modes(connector, edid); | |
4504 | if (ret) | |
4505 | return ret; | |
4506 | } | |
32f9d658 | 4507 | |
f8779fda | 4508 | /* if eDP has no EDID, fall back to fixed mode */ |
beb60608 CW |
4509 | if (is_edp(intel_attached_dp(connector)) && |
4510 | intel_connector->panel.fixed_mode) { | |
f8779fda | 4511 | struct drm_display_mode *mode; |
beb60608 CW |
4512 | |
4513 | mode = drm_mode_duplicate(connector->dev, | |
dd06f90e | 4514 | intel_connector->panel.fixed_mode); |
f8779fda | 4515 | if (mode) { |
32f9d658 ZW |
4516 | drm_mode_probed_add(connector, mode); |
4517 | return 1; | |
4518 | } | |
4519 | } | |
beb60608 | 4520 | |
32f9d658 | 4521 | return 0; |
a4fc5ed6 KP |
4522 | } |
4523 | ||
1aad7ac0 CW |
4524 | static bool |
4525 | intel_dp_detect_audio(struct drm_connector *connector) | |
4526 | { | |
1aad7ac0 | 4527 | bool has_audio = false; |
beb60608 | 4528 | struct edid *edid; |
1aad7ac0 | 4529 | |
beb60608 CW |
4530 | edid = to_intel_connector(connector)->detect_edid; |
4531 | if (edid) | |
1aad7ac0 | 4532 | has_audio = drm_detect_monitor_audio(edid); |
671dedd2 | 4533 | |
1aad7ac0 CW |
4534 | return has_audio; |
4535 | } | |
4536 | ||
f684960e CW |
4537 | static int |
4538 | intel_dp_set_property(struct drm_connector *connector, | |
4539 | struct drm_property *property, | |
4540 | uint64_t val) | |
4541 | { | |
e953fd7b | 4542 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
53b41837 | 4543 | struct intel_connector *intel_connector = to_intel_connector(connector); |
da63a9f2 PZ |
4544 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
4545 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
f684960e CW |
4546 | int ret; |
4547 | ||
662595df | 4548 | ret = drm_object_property_set_value(&connector->base, property, val); |
f684960e CW |
4549 | if (ret) |
4550 | return ret; | |
4551 | ||
3f43c48d | 4552 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
4553 | int i = val; |
4554 | bool has_audio; | |
4555 | ||
4556 | if (i == intel_dp->force_audio) | |
f684960e CW |
4557 | return 0; |
4558 | ||
1aad7ac0 | 4559 | intel_dp->force_audio = i; |
f684960e | 4560 | |
c3e5f67b | 4561 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
4562 | has_audio = intel_dp_detect_audio(connector); |
4563 | else | |
c3e5f67b | 4564 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
4565 | |
4566 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
4567 | return 0; |
4568 | ||
1aad7ac0 | 4569 | intel_dp->has_audio = has_audio; |
f684960e CW |
4570 | goto done; |
4571 | } | |
4572 | ||
e953fd7b | 4573 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
4574 | bool old_auto = intel_dp->color_range_auto; |
4575 | uint32_t old_range = intel_dp->color_range; | |
4576 | ||
55bc60db VS |
4577 | switch (val) { |
4578 | case INTEL_BROADCAST_RGB_AUTO: | |
4579 | intel_dp->color_range_auto = true; | |
4580 | break; | |
4581 | case INTEL_BROADCAST_RGB_FULL: | |
4582 | intel_dp->color_range_auto = false; | |
4583 | intel_dp->color_range = 0; | |
4584 | break; | |
4585 | case INTEL_BROADCAST_RGB_LIMITED: | |
4586 | intel_dp->color_range_auto = false; | |
4587 | intel_dp->color_range = DP_COLOR_RANGE_16_235; | |
4588 | break; | |
4589 | default: | |
4590 | return -EINVAL; | |
4591 | } | |
ae4edb80 DV |
4592 | |
4593 | if (old_auto == intel_dp->color_range_auto && | |
4594 | old_range == intel_dp->color_range) | |
4595 | return 0; | |
4596 | ||
e953fd7b CW |
4597 | goto done; |
4598 | } | |
4599 | ||
53b41837 YN |
4600 | if (is_edp(intel_dp) && |
4601 | property == connector->dev->mode_config.scaling_mode_property) { | |
4602 | if (val == DRM_MODE_SCALE_NONE) { | |
4603 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
4604 | return -EINVAL; | |
4605 | } | |
4606 | ||
4607 | if (intel_connector->panel.fitting_mode == val) { | |
4608 | /* the eDP scaling property is not changed */ | |
4609 | return 0; | |
4610 | } | |
4611 | intel_connector->panel.fitting_mode = val; | |
4612 | ||
4613 | goto done; | |
4614 | } | |
4615 | ||
f684960e CW |
4616 | return -EINVAL; |
4617 | ||
4618 | done: | |
c0c36b94 CW |
4619 | if (intel_encoder->base.crtc) |
4620 | intel_crtc_restore_mode(intel_encoder->base.crtc); | |
f684960e CW |
4621 | |
4622 | return 0; | |
4623 | } | |
4624 | ||
a4fc5ed6 | 4625 | static void |
73845adf | 4626 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 4627 | { |
1d508706 | 4628 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 4629 | |
10e972d3 | 4630 | kfree(intel_connector->detect_edid); |
beb60608 | 4631 | |
9cd300e0 JN |
4632 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4633 | kfree(intel_connector->edid); | |
4634 | ||
acd8db10 PZ |
4635 | /* Can't call is_edp() since the encoder may have been destroyed |
4636 | * already. */ | |
4637 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
1d508706 | 4638 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 4639 | |
a4fc5ed6 | 4640 | drm_connector_cleanup(connector); |
55f78c43 | 4641 | kfree(connector); |
a4fc5ed6 KP |
4642 | } |
4643 | ||
00c09d70 | 4644 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 4645 | { |
da63a9f2 PZ |
4646 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4647 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
24d05927 | 4648 | |
4f71d0cb | 4649 | drm_dp_aux_unregister(&intel_dp->aux); |
0e32b39c | 4650 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
24d05927 | 4651 | drm_encoder_cleanup(encoder); |
bd943159 KP |
4652 | if (is_edp(intel_dp)) { |
4653 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
951468f3 VS |
4654 | /* |
4655 | * vdd might still be enabled do to the delayed vdd off. | |
4656 | * Make sure vdd is actually turned off here. | |
4657 | */ | |
773538e8 | 4658 | pps_lock(intel_dp); |
4be73780 | 4659 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 VS |
4660 | pps_unlock(intel_dp); |
4661 | ||
01527b31 CT |
4662 | if (intel_dp->edp_notifier.notifier_call) { |
4663 | unregister_reboot_notifier(&intel_dp->edp_notifier); | |
4664 | intel_dp->edp_notifier.notifier_call = NULL; | |
4665 | } | |
bd943159 | 4666 | } |
da63a9f2 | 4667 | kfree(intel_dig_port); |
24d05927 DV |
4668 | } |
4669 | ||
07f9cd0b ID |
4670 | static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
4671 | { | |
4672 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
4673 | ||
4674 | if (!is_edp(intel_dp)) | |
4675 | return; | |
4676 | ||
951468f3 VS |
4677 | /* |
4678 | * vdd might still be enabled do to the delayed vdd off. | |
4679 | * Make sure vdd is actually turned off here. | |
4680 | */ | |
773538e8 | 4681 | pps_lock(intel_dp); |
07f9cd0b | 4682 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 | 4683 | pps_unlock(intel_dp); |
07f9cd0b ID |
4684 | } |
4685 | ||
49e6bc51 VS |
4686 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
4687 | { | |
4688 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4689 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
4690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4691 | enum intel_display_power_domain power_domain; | |
4692 | ||
4693 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4694 | ||
4695 | if (!edp_have_panel_vdd(intel_dp)) | |
4696 | return; | |
4697 | ||
4698 | /* | |
4699 | * The VDD bit needs a power domain reference, so if the bit is | |
4700 | * already enabled when we boot or resume, grab this reference and | |
4701 | * schedule a vdd off, so we don't hold on to the reference | |
4702 | * indefinitely. | |
4703 | */ | |
4704 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); | |
4705 | power_domain = intel_display_port_power_domain(&intel_dig_port->base); | |
4706 | intel_display_power_get(dev_priv, power_domain); | |
4707 | ||
4708 | edp_panel_vdd_schedule_off(intel_dp); | |
4709 | } | |
4710 | ||
6d93c0c4 ID |
4711 | static void intel_dp_encoder_reset(struct drm_encoder *encoder) |
4712 | { | |
49e6bc51 VS |
4713 | struct intel_dp *intel_dp; |
4714 | ||
4715 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) | |
4716 | return; | |
4717 | ||
4718 | intel_dp = enc_to_intel_dp(encoder); | |
4719 | ||
4720 | pps_lock(intel_dp); | |
4721 | ||
4722 | /* | |
4723 | * Read out the current power sequencer assignment, | |
4724 | * in case the BIOS did something with it. | |
4725 | */ | |
4726 | if (IS_VALLEYVIEW(encoder->dev)) | |
4727 | vlv_initial_power_sequencer_setup(intel_dp); | |
4728 | ||
4729 | intel_edp_panel_vdd_sanitize(intel_dp); | |
4730 | ||
4731 | pps_unlock(intel_dp); | |
6d93c0c4 ID |
4732 | } |
4733 | ||
a4fc5ed6 | 4734 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
2bd2ad64 | 4735 | .dpms = intel_connector_dpms, |
a4fc5ed6 | 4736 | .detect = intel_dp_detect, |
beb60608 | 4737 | .force = intel_dp_force, |
a4fc5ed6 | 4738 | .fill_modes = drm_helper_probe_single_connector_modes, |
f684960e | 4739 | .set_property = intel_dp_set_property, |
73845adf | 4740 | .destroy = intel_dp_connector_destroy, |
a4fc5ed6 KP |
4741 | }; |
4742 | ||
4743 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
4744 | .get_modes = intel_dp_get_modes, | |
4745 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 4746 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
4747 | }; |
4748 | ||
a4fc5ed6 | 4749 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
6d93c0c4 | 4750 | .reset = intel_dp_encoder_reset, |
24d05927 | 4751 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
4752 | }; |
4753 | ||
0e32b39c | 4754 | void |
21d40d37 | 4755 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 4756 | { |
0e32b39c | 4757 | return; |
c8110e52 | 4758 | } |
6207937d | 4759 | |
13cf5504 DA |
4760 | bool |
4761 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) | |
4762 | { | |
4763 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1c767b33 | 4764 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
0e32b39c DA |
4765 | struct drm_device *dev = intel_dig_port->base.base.dev; |
4766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1c767b33 ID |
4767 | enum intel_display_power_domain power_domain; |
4768 | bool ret = true; | |
4769 | ||
0e32b39c DA |
4770 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP) |
4771 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; | |
13cf5504 | 4772 | |
26fbb774 VS |
4773 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
4774 | port_name(intel_dig_port->port), | |
0e32b39c | 4775 | long_hpd ? "long" : "short"); |
13cf5504 | 4776 | |
1c767b33 ID |
4777 | power_domain = intel_display_port_power_domain(intel_encoder); |
4778 | intel_display_power_get(dev_priv, power_domain); | |
4779 | ||
0e32b39c | 4780 | if (long_hpd) { |
2a592bec DA |
4781 | |
4782 | if (HAS_PCH_SPLIT(dev)) { | |
4783 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) | |
4784 | goto mst_fail; | |
4785 | } else { | |
4786 | if (g4x_digital_port_connected(dev, intel_dig_port) != 1) | |
4787 | goto mst_fail; | |
4788 | } | |
0e32b39c DA |
4789 | |
4790 | if (!intel_dp_get_dpcd(intel_dp)) { | |
4791 | goto mst_fail; | |
4792 | } | |
4793 | ||
4794 | intel_dp_probe_oui(intel_dp); | |
4795 | ||
4796 | if (!intel_dp_probe_mst(intel_dp)) | |
4797 | goto mst_fail; | |
4798 | ||
4799 | } else { | |
4800 | if (intel_dp->is_mst) { | |
1c767b33 | 4801 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) |
0e32b39c DA |
4802 | goto mst_fail; |
4803 | } | |
4804 | ||
4805 | if (!intel_dp->is_mst) { | |
4806 | /* | |
4807 | * we'll check the link status via the normal hot plug path later - | |
4808 | * but for short hpds we should check it now | |
4809 | */ | |
5b215bcf | 4810 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
0e32b39c | 4811 | intel_dp_check_link_status(intel_dp); |
5b215bcf | 4812 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
0e32b39c DA |
4813 | } |
4814 | } | |
1c767b33 ID |
4815 | ret = false; |
4816 | goto put_power; | |
0e32b39c DA |
4817 | mst_fail: |
4818 | /* if we were in MST mode, and device is not there get out of MST mode */ | |
4819 | if (intel_dp->is_mst) { | |
4820 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state); | |
4821 | intel_dp->is_mst = false; | |
4822 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
4823 | } | |
1c767b33 ID |
4824 | put_power: |
4825 | intel_display_power_put(dev_priv, power_domain); | |
4826 | ||
4827 | return ret; | |
13cf5504 DA |
4828 | } |
4829 | ||
e3421a18 ZW |
4830 | /* Return which DP Port should be selected for Transcoder DP control */ |
4831 | int | |
0206e353 | 4832 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
e3421a18 ZW |
4833 | { |
4834 | struct drm_device *dev = crtc->dev; | |
fa90ecef PZ |
4835 | struct intel_encoder *intel_encoder; |
4836 | struct intel_dp *intel_dp; | |
e3421a18 | 4837 | |
fa90ecef PZ |
4838 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
4839 | intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
e3421a18 | 4840 | |
fa90ecef PZ |
4841 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
4842 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
ea5b213a | 4843 | return intel_dp->output_reg; |
e3421a18 | 4844 | } |
ea5b213a | 4845 | |
e3421a18 ZW |
4846 | return -1; |
4847 | } | |
4848 | ||
36e83a18 | 4849 | /* check the VBT to see whether the eDP is on DP-D port */ |
5d8a7752 | 4850 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
36e83a18 ZY |
4851 | { |
4852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
768f69c9 | 4853 | union child_device_config *p_child; |
36e83a18 | 4854 | int i; |
5d8a7752 VS |
4855 | static const short port_mapping[] = { |
4856 | [PORT_B] = PORT_IDPB, | |
4857 | [PORT_C] = PORT_IDPC, | |
4858 | [PORT_D] = PORT_IDPD, | |
4859 | }; | |
36e83a18 | 4860 | |
3b32a35b VS |
4861 | if (port == PORT_A) |
4862 | return true; | |
4863 | ||
41aa3448 | 4864 | if (!dev_priv->vbt.child_dev_num) |
36e83a18 ZY |
4865 | return false; |
4866 | ||
41aa3448 RV |
4867 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
4868 | p_child = dev_priv->vbt.child_dev + i; | |
36e83a18 | 4869 | |
5d8a7752 | 4870 | if (p_child->common.dvo_port == port_mapping[port] && |
f02586df VS |
4871 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
4872 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) | |
36e83a18 ZY |
4873 | return true; |
4874 | } | |
4875 | return false; | |
4876 | } | |
4877 | ||
0e32b39c | 4878 | void |
f684960e CW |
4879 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
4880 | { | |
53b41837 YN |
4881 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4882 | ||
3f43c48d | 4883 | intel_attach_force_audio_property(connector); |
e953fd7b | 4884 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 4885 | intel_dp->color_range_auto = true; |
53b41837 YN |
4886 | |
4887 | if (is_edp(intel_dp)) { | |
4888 | drm_mode_create_scaling_mode_property(connector->dev); | |
6de6d846 RC |
4889 | drm_object_attach_property( |
4890 | &connector->base, | |
53b41837 | 4891 | connector->dev->mode_config.scaling_mode_property, |
8e740cd1 YN |
4892 | DRM_MODE_SCALE_ASPECT); |
4893 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
53b41837 | 4894 | } |
f684960e CW |
4895 | } |
4896 | ||
dada1a9f ID |
4897 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
4898 | { | |
4899 | intel_dp->last_power_cycle = jiffies; | |
4900 | intel_dp->last_power_on = jiffies; | |
4901 | intel_dp->last_backlight_off = jiffies; | |
4902 | } | |
4903 | ||
67a54566 DV |
4904 | static void |
4905 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
36b5f425 | 4906 | struct intel_dp *intel_dp) |
67a54566 DV |
4907 | { |
4908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
36b5f425 VS |
4909 | struct edp_power_seq cur, vbt, spec, |
4910 | *final = &intel_dp->pps_delays; | |
67a54566 | 4911 | u32 pp_on, pp_off, pp_div, pp; |
bf13e81b | 4912 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
453c5420 | 4913 | |
e39b999a VS |
4914 | lockdep_assert_held(&dev_priv->pps_mutex); |
4915 | ||
81ddbc69 VS |
4916 | /* already initialized? */ |
4917 | if (final->t11_t12 != 0) | |
4918 | return; | |
4919 | ||
453c5420 | 4920 | if (HAS_PCH_SPLIT(dev)) { |
bf13e81b | 4921 | pp_ctrl_reg = PCH_PP_CONTROL; |
453c5420 JB |
4922 | pp_on_reg = PCH_PP_ON_DELAYS; |
4923 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
4924 | pp_div_reg = PCH_PP_DIVISOR; | |
4925 | } else { | |
bf13e81b JN |
4926 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
4927 | ||
4928 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); | |
4929 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
4930 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
4931 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 | 4932 | } |
67a54566 DV |
4933 | |
4934 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
4935 | * the very first thing. */ | |
453c5420 | 4936 | pp = ironlake_get_pp_control(intel_dp); |
bf13e81b | 4937 | I915_WRITE(pp_ctrl_reg, pp); |
67a54566 | 4938 | |
453c5420 JB |
4939 | pp_on = I915_READ(pp_on_reg); |
4940 | pp_off = I915_READ(pp_off_reg); | |
4941 | pp_div = I915_READ(pp_div_reg); | |
67a54566 DV |
4942 | |
4943 | /* Pull timing values out of registers */ | |
4944 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
4945 | PANEL_POWER_UP_DELAY_SHIFT; | |
4946 | ||
4947 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
4948 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
4949 | ||
4950 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
4951 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
4952 | ||
4953 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
4954 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
4955 | ||
4956 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
4957 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
4958 | ||
4959 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
4960 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
4961 | ||
41aa3448 | 4962 | vbt = dev_priv->vbt.edp_pps; |
67a54566 DV |
4963 | |
4964 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
4965 | * our hw here, which are all in 100usec. */ | |
4966 | spec.t1_t3 = 210 * 10; | |
4967 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
4968 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
4969 | spec.t10 = 500 * 10; | |
4970 | /* This one is special and actually in units of 100ms, but zero | |
4971 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
4972 | * table multiplies it with 1000 to make it in units of 100usec, | |
4973 | * too. */ | |
4974 | spec.t11_t12 = (510 + 100) * 10; | |
4975 | ||
4976 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
4977 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
4978 | ||
4979 | /* Use the max of the register settings and vbt. If both are | |
4980 | * unset, fall back to the spec limits. */ | |
36b5f425 | 4981 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
67a54566 DV |
4982 | spec.field : \ |
4983 | max(cur.field, vbt.field)) | |
4984 | assign_final(t1_t3); | |
4985 | assign_final(t8); | |
4986 | assign_final(t9); | |
4987 | assign_final(t10); | |
4988 | assign_final(t11_t12); | |
4989 | #undef assign_final | |
4990 | ||
36b5f425 | 4991 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
67a54566 DV |
4992 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
4993 | intel_dp->backlight_on_delay = get_delay(t8); | |
4994 | intel_dp->backlight_off_delay = get_delay(t9); | |
4995 | intel_dp->panel_power_down_delay = get_delay(t10); | |
4996 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
4997 | #undef get_delay | |
4998 | ||
f30d26e4 JN |
4999 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
5000 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
5001 | intel_dp->panel_power_cycle_delay); | |
5002 | ||
5003 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
5004 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
f30d26e4 JN |
5005 | } |
5006 | ||
5007 | static void | |
5008 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
36b5f425 | 5009 | struct intel_dp *intel_dp) |
f30d26e4 JN |
5010 | { |
5011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
453c5420 JB |
5012 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
5013 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); | |
5014 | int pp_on_reg, pp_off_reg, pp_div_reg; | |
ad933b56 | 5015 | enum port port = dp_to_dig_port(intel_dp)->port; |
36b5f425 | 5016 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
453c5420 | 5017 | |
e39b999a | 5018 | lockdep_assert_held(&dev_priv->pps_mutex); |
453c5420 JB |
5019 | |
5020 | if (HAS_PCH_SPLIT(dev)) { | |
5021 | pp_on_reg = PCH_PP_ON_DELAYS; | |
5022 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
5023 | pp_div_reg = PCH_PP_DIVISOR; | |
5024 | } else { | |
bf13e81b JN |
5025 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
5026 | ||
5027 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
5028 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
5029 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 JB |
5030 | } |
5031 | ||
b2f19d1a PZ |
5032 | /* |
5033 | * And finally store the new values in the power sequencer. The | |
5034 | * backlight delays are set to 1 because we do manual waits on them. For | |
5035 | * T8, even BSpec recommends doing it. For T9, if we don't do this, | |
5036 | * we'll end up waiting for the backlight off delay twice: once when we | |
5037 | * do the manual sleep, and once when we disable the panel and wait for | |
5038 | * the PP_STATUS bit to become zero. | |
5039 | */ | |
f30d26e4 | 5040 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
b2f19d1a PZ |
5041 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
5042 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 5043 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
5044 | /* Compute the divisor for the pp clock, simply match the Bspec |
5045 | * formula. */ | |
453c5420 | 5046 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
f30d26e4 | 5047 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
67a54566 DV |
5048 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
5049 | ||
5050 | /* Haswell doesn't have any port selection bits for the panel | |
5051 | * power sequencer any more. */ | |
bc7d38a4 | 5052 | if (IS_VALLEYVIEW(dev)) { |
ad933b56 | 5053 | port_sel = PANEL_PORT_SELECT_VLV(port); |
bc7d38a4 | 5054 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
ad933b56 | 5055 | if (port == PORT_A) |
a24c144c | 5056 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 5057 | else |
a24c144c | 5058 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
5059 | } |
5060 | ||
453c5420 JB |
5061 | pp_on |= port_sel; |
5062 | ||
5063 | I915_WRITE(pp_on_reg, pp_on); | |
5064 | I915_WRITE(pp_off_reg, pp_off); | |
5065 | I915_WRITE(pp_div_reg, pp_div); | |
67a54566 | 5066 | |
67a54566 | 5067 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
453c5420 JB |
5068 | I915_READ(pp_on_reg), |
5069 | I915_READ(pp_off_reg), | |
5070 | I915_READ(pp_div_reg)); | |
f684960e CW |
5071 | } |
5072 | ||
439d7ac0 PB |
5073 | void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
5074 | { | |
5075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5076 | struct intel_encoder *encoder; | |
5077 | struct intel_dp *intel_dp = NULL; | |
5078 | struct intel_crtc_config *config = NULL; | |
5079 | struct intel_crtc *intel_crtc = NULL; | |
5080 | struct intel_connector *intel_connector = dev_priv->drrs.connector; | |
5081 | u32 reg, val; | |
5082 | enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR; | |
5083 | ||
5084 | if (refresh_rate <= 0) { | |
5085 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); | |
5086 | return; | |
5087 | } | |
5088 | ||
5089 | if (intel_connector == NULL) { | |
5090 | DRM_DEBUG_KMS("DRRS supported for eDP only.\n"); | |
5091 | return; | |
5092 | } | |
5093 | ||
1fcc9d1c DV |
5094 | /* |
5095 | * FIXME: This needs proper synchronization with psr state. But really | |
5096 | * hard to tell without seeing the user of this function of this code. | |
5097 | * Check locking and ordering once that lands. | |
5098 | */ | |
439d7ac0 PB |
5099 | if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) { |
5100 | DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); | |
5101 | return; | |
5102 | } | |
5103 | ||
5104 | encoder = intel_attached_encoder(&intel_connector->base); | |
5105 | intel_dp = enc_to_intel_dp(&encoder->base); | |
5106 | intel_crtc = encoder->new_crtc; | |
5107 | ||
5108 | if (!intel_crtc) { | |
5109 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); | |
5110 | return; | |
5111 | } | |
5112 | ||
5113 | config = &intel_crtc->config; | |
5114 | ||
5115 | if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) { | |
5116 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); | |
5117 | return; | |
5118 | } | |
5119 | ||
5120 | if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate) | |
5121 | index = DRRS_LOW_RR; | |
5122 | ||
5123 | if (index == intel_dp->drrs_state.refresh_rate_type) { | |
5124 | DRM_DEBUG_KMS( | |
5125 | "DRRS requested for previously set RR...ignoring\n"); | |
5126 | return; | |
5127 | } | |
5128 | ||
5129 | if (!intel_crtc->active) { | |
5130 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); | |
5131 | return; | |
5132 | } | |
5133 | ||
5134 | if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { | |
5135 | reg = PIPECONF(intel_crtc->config.cpu_transcoder); | |
5136 | val = I915_READ(reg); | |
5137 | if (index > DRRS_HIGH_RR) { | |
5138 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
f769cd24 | 5139 | intel_dp_set_m_n(intel_crtc); |
439d7ac0 PB |
5140 | } else { |
5141 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
5142 | } | |
5143 | I915_WRITE(reg, val); | |
5144 | } | |
5145 | ||
5146 | /* | |
5147 | * mutex taken to ensure that there is no race between differnt | |
5148 | * drrs calls trying to update refresh rate. This scenario may occur | |
5149 | * in future when idleness detection based DRRS in kernel and | |
5150 | * possible calls from user space to set differnt RR are made. | |
5151 | */ | |
5152 | ||
5153 | mutex_lock(&intel_dp->drrs_state.mutex); | |
5154 | ||
5155 | intel_dp->drrs_state.refresh_rate_type = index; | |
5156 | ||
5157 | mutex_unlock(&intel_dp->drrs_state.mutex); | |
5158 | ||
5159 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); | |
5160 | } | |
5161 | ||
4f9db5b5 PB |
5162 | static struct drm_display_mode * |
5163 | intel_dp_drrs_init(struct intel_digital_port *intel_dig_port, | |
5164 | struct intel_connector *intel_connector, | |
5165 | struct drm_display_mode *fixed_mode) | |
5166 | { | |
5167 | struct drm_connector *connector = &intel_connector->base; | |
5168 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
5169 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
5170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5171 | struct drm_display_mode *downclock_mode = NULL; | |
5172 | ||
5173 | if (INTEL_INFO(dev)->gen <= 6) { | |
5174 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); | |
5175 | return NULL; | |
5176 | } | |
5177 | ||
5178 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
4079b8d1 | 5179 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
4f9db5b5 PB |
5180 | return NULL; |
5181 | } | |
5182 | ||
5183 | downclock_mode = intel_find_panel_downclock | |
5184 | (dev, fixed_mode, connector); | |
5185 | ||
5186 | if (!downclock_mode) { | |
4079b8d1 | 5187 | DRM_DEBUG_KMS("DRRS not supported\n"); |
4f9db5b5 PB |
5188 | return NULL; |
5189 | } | |
5190 | ||
439d7ac0 PB |
5191 | dev_priv->drrs.connector = intel_connector; |
5192 | ||
5193 | mutex_init(&intel_dp->drrs_state.mutex); | |
5194 | ||
4f9db5b5 PB |
5195 | intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; |
5196 | ||
5197 | intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; | |
4079b8d1 | 5198 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
4f9db5b5 PB |
5199 | return downclock_mode; |
5200 | } | |
5201 | ||
ed92f0b2 | 5202 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 5203 | struct intel_connector *intel_connector) |
ed92f0b2 PZ |
5204 | { |
5205 | struct drm_connector *connector = &intel_connector->base; | |
5206 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
63635217 PZ |
5207 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5208 | struct drm_device *dev = intel_encoder->base.dev; | |
ed92f0b2 PZ |
5209 | struct drm_i915_private *dev_priv = dev->dev_private; |
5210 | struct drm_display_mode *fixed_mode = NULL; | |
4f9db5b5 | 5211 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 PZ |
5212 | bool has_dpcd; |
5213 | struct drm_display_mode *scan; | |
5214 | struct edid *edid; | |
5215 | ||
4f9db5b5 PB |
5216 | intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED; |
5217 | ||
ed92f0b2 PZ |
5218 | if (!is_edp(intel_dp)) |
5219 | return true; | |
5220 | ||
49e6bc51 VS |
5221 | pps_lock(intel_dp); |
5222 | intel_edp_panel_vdd_sanitize(intel_dp); | |
5223 | pps_unlock(intel_dp); | |
63635217 | 5224 | |
ed92f0b2 | 5225 | /* Cache DPCD and EDID for edp. */ |
ed92f0b2 | 5226 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
ed92f0b2 PZ |
5227 | |
5228 | if (has_dpcd) { | |
5229 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) | |
5230 | dev_priv->no_aux_handshake = | |
5231 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
5232 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
5233 | } else { | |
5234 | /* if this fails, presume the device is a ghost */ | |
5235 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
ed92f0b2 PZ |
5236 | return false; |
5237 | } | |
5238 | ||
5239 | /* We now know it's not a ghost, init power sequence regs. */ | |
773538e8 | 5240 | pps_lock(intel_dp); |
36b5f425 | 5241 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
773538e8 | 5242 | pps_unlock(intel_dp); |
ed92f0b2 | 5243 | |
060c8778 | 5244 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 5245 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
5246 | if (edid) { |
5247 | if (drm_add_edid_modes(connector, edid)) { | |
5248 | drm_mode_connector_update_edid_property(connector, | |
5249 | edid); | |
5250 | drm_edid_to_eld(connector, edid); | |
5251 | } else { | |
5252 | kfree(edid); | |
5253 | edid = ERR_PTR(-EINVAL); | |
5254 | } | |
5255 | } else { | |
5256 | edid = ERR_PTR(-ENOENT); | |
5257 | } | |
5258 | intel_connector->edid = edid; | |
5259 | ||
5260 | /* prefer fixed mode from EDID if available */ | |
5261 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
5262 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
5263 | fixed_mode = drm_mode_duplicate(dev, scan); | |
4f9db5b5 PB |
5264 | downclock_mode = intel_dp_drrs_init( |
5265 | intel_dig_port, | |
5266 | intel_connector, fixed_mode); | |
ed92f0b2 PZ |
5267 | break; |
5268 | } | |
5269 | } | |
5270 | ||
5271 | /* fallback to VBT if available for eDP */ | |
5272 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
5273 | fixed_mode = drm_mode_duplicate(dev, | |
5274 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
5275 | if (fixed_mode) | |
5276 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
5277 | } | |
060c8778 | 5278 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 5279 | |
01527b31 CT |
5280 | if (IS_VALLEYVIEW(dev)) { |
5281 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; | |
5282 | register_reboot_notifier(&intel_dp->edp_notifier); | |
5283 | } | |
5284 | ||
4f9db5b5 | 5285 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
73580fb7 | 5286 | intel_connector->panel.backlight_power = intel_edp_backlight_power; |
ed92f0b2 PZ |
5287 | intel_panel_setup_backlight(connector); |
5288 | ||
5289 | return true; | |
5290 | } | |
5291 | ||
16c25533 | 5292 | bool |
f0fec3f2 PZ |
5293 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5294 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 5295 | { |
f0fec3f2 PZ |
5296 | struct drm_connector *connector = &intel_connector->base; |
5297 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
5298 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
5299 | struct drm_device *dev = intel_encoder->base.dev; | |
a4fc5ed6 | 5300 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 5301 | enum port port = intel_dig_port->port; |
0b99836f | 5302 | int type; |
a4fc5ed6 | 5303 | |
a4a5d2f8 VS |
5304 | intel_dp->pps_pipe = INVALID_PIPE; |
5305 | ||
ec5b01dd | 5306 | /* intel_dp vfuncs */ |
b6b5e383 DL |
5307 | if (INTEL_INFO(dev)->gen >= 9) |
5308 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; | |
5309 | else if (IS_VALLEYVIEW(dev)) | |
ec5b01dd DL |
5310 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
5311 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
5312 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; | |
5313 | else if (HAS_PCH_SPLIT(dev)) | |
5314 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; | |
5315 | else | |
5316 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; | |
5317 | ||
b9ca5fad DL |
5318 | if (INTEL_INFO(dev)->gen >= 9) |
5319 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; | |
5320 | else | |
5321 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; | |
153b1100 | 5322 | |
0767935e DV |
5323 | /* Preserve the current hw state. */ |
5324 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 5325 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 5326 | |
3b32a35b | 5327 | if (intel_dp_is_edp(dev, port)) |
b329530c | 5328 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
5329 | else |
5330 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 5331 | |
f7d24902 ID |
5332 | /* |
5333 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
5334 | * for DP the encoder type can be set by the caller to | |
5335 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
5336 | */ | |
5337 | if (type == DRM_MODE_CONNECTOR_eDP) | |
5338 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
5339 | ||
c17ed5b5 VS |
5340 | /* eDP only on port B and/or C on vlv/chv */ |
5341 | if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) && | |
5342 | port != PORT_B && port != PORT_C)) | |
5343 | return false; | |
5344 | ||
e7281eab ID |
5345 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
5346 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
5347 | port_name(port)); | |
5348 | ||
b329530c | 5349 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
5350 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
5351 | ||
a4fc5ed6 KP |
5352 | connector->interlace_allowed = true; |
5353 | connector->doublescan_allowed = 0; | |
5354 | ||
f0fec3f2 | 5355 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 5356 | edp_panel_vdd_work); |
a4fc5ed6 | 5357 | |
df0e9248 | 5358 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
34ea3d38 | 5359 | drm_connector_register(connector); |
a4fc5ed6 | 5360 | |
affa9354 | 5361 | if (HAS_DDI(dev)) |
bcbc889b PZ |
5362 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
5363 | else | |
5364 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
80f65de3 | 5365 | intel_connector->unregister = intel_dp_connector_unregister; |
bcbc889b | 5366 | |
0b99836f | 5367 | /* Set up the hotplug pin. */ |
ab9d7c30 PZ |
5368 | switch (port) { |
5369 | case PORT_A: | |
1d843f9d | 5370 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
5371 | break; |
5372 | case PORT_B: | |
1d843f9d | 5373 | intel_encoder->hpd_pin = HPD_PORT_B; |
ab9d7c30 PZ |
5374 | break; |
5375 | case PORT_C: | |
1d843f9d | 5376 | intel_encoder->hpd_pin = HPD_PORT_C; |
ab9d7c30 PZ |
5377 | break; |
5378 | case PORT_D: | |
1d843f9d | 5379 | intel_encoder->hpd_pin = HPD_PORT_D; |
ab9d7c30 PZ |
5380 | break; |
5381 | default: | |
ad1c0b19 | 5382 | BUG(); |
5eb08b69 ZW |
5383 | } |
5384 | ||
dada1a9f | 5385 | if (is_edp(intel_dp)) { |
773538e8 | 5386 | pps_lock(intel_dp); |
1e74a324 VS |
5387 | intel_dp_init_panel_power_timestamps(intel_dp); |
5388 | if (IS_VALLEYVIEW(dev)) | |
a4a5d2f8 | 5389 | vlv_initial_power_sequencer_setup(intel_dp); |
1e74a324 | 5390 | else |
36b5f425 | 5391 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
773538e8 | 5392 | pps_unlock(intel_dp); |
dada1a9f | 5393 | } |
0095e6dc | 5394 | |
9d1a1031 | 5395 | intel_dp_aux_init(intel_dp, intel_connector); |
c1f05264 | 5396 | |
0e32b39c DA |
5397 | /* init MST on ports that can support it */ |
5398 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
5399 | if (port == PORT_B || port == PORT_C || port == PORT_D) { | |
a4a5d2f8 VS |
5400 | intel_dp_mst_encoder_init(intel_dig_port, |
5401 | intel_connector->base.base.id); | |
0e32b39c DA |
5402 | } |
5403 | } | |
5404 | ||
36b5f425 | 5405 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
4f71d0cb | 5406 | drm_dp_aux_unregister(&intel_dp->aux); |
15b1d171 PZ |
5407 | if (is_edp(intel_dp)) { |
5408 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
951468f3 VS |
5409 | /* |
5410 | * vdd might still be enabled do to the delayed vdd off. | |
5411 | * Make sure vdd is actually turned off here. | |
5412 | */ | |
773538e8 | 5413 | pps_lock(intel_dp); |
4be73780 | 5414 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 | 5415 | pps_unlock(intel_dp); |
15b1d171 | 5416 | } |
34ea3d38 | 5417 | drm_connector_unregister(connector); |
b2f246a8 | 5418 | drm_connector_cleanup(connector); |
16c25533 | 5419 | return false; |
b2f246a8 | 5420 | } |
32f9d658 | 5421 | |
f684960e CW |
5422 | intel_dp_add_properties(intel_dp, connector); |
5423 | ||
a4fc5ed6 KP |
5424 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
5425 | * 0xd. Failure to do so will result in spurious interrupts being | |
5426 | * generated on the port when a cable is not attached. | |
5427 | */ | |
5428 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
5429 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
5430 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
5431 | } | |
16c25533 PZ |
5432 | |
5433 | return true; | |
a4fc5ed6 | 5434 | } |
f0fec3f2 PZ |
5435 | |
5436 | void | |
5437 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) | |
5438 | { | |
13cf5504 | 5439 | struct drm_i915_private *dev_priv = dev->dev_private; |
f0fec3f2 PZ |
5440 | struct intel_digital_port *intel_dig_port; |
5441 | struct intel_encoder *intel_encoder; | |
5442 | struct drm_encoder *encoder; | |
5443 | struct intel_connector *intel_connector; | |
5444 | ||
b14c5679 | 5445 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 PZ |
5446 | if (!intel_dig_port) |
5447 | return; | |
5448 | ||
b14c5679 | 5449 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
f0fec3f2 PZ |
5450 | if (!intel_connector) { |
5451 | kfree(intel_dig_port); | |
5452 | return; | |
5453 | } | |
5454 | ||
5455 | intel_encoder = &intel_dig_port->base; | |
5456 | encoder = &intel_encoder->base; | |
5457 | ||
5458 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, | |
5459 | DRM_MODE_ENCODER_TMDS); | |
5460 | ||
5bfe2ac0 | 5461 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 5462 | intel_encoder->disable = intel_disable_dp; |
00c09d70 | 5463 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 5464 | intel_encoder->get_config = intel_dp_get_config; |
07f9cd0b | 5465 | intel_encoder->suspend = intel_dp_encoder_suspend; |
e4a1d846 | 5466 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 5467 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
e4a1d846 CML |
5468 | intel_encoder->pre_enable = chv_pre_enable_dp; |
5469 | intel_encoder->enable = vlv_enable_dp; | |
580d3811 | 5470 | intel_encoder->post_disable = chv_post_disable_dp; |
e4a1d846 | 5471 | } else if (IS_VALLEYVIEW(dev)) { |
ecff4f3b | 5472 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
5473 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
5474 | intel_encoder->enable = vlv_enable_dp; | |
49277c31 | 5475 | intel_encoder->post_disable = vlv_post_disable_dp; |
ab1f90f9 | 5476 | } else { |
ecff4f3b JN |
5477 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
5478 | intel_encoder->enable = g4x_enable_dp; | |
08aff3fe VS |
5479 | if (INTEL_INFO(dev)->gen >= 5) |
5480 | intel_encoder->post_disable = ilk_post_disable_dp; | |
ab1f90f9 | 5481 | } |
f0fec3f2 | 5482 | |
174edf1f | 5483 | intel_dig_port->port = port; |
f0fec3f2 PZ |
5484 | intel_dig_port->dp.output_reg = output_reg; |
5485 | ||
00c09d70 | 5486 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
882ec384 VS |
5487 | if (IS_CHERRYVIEW(dev)) { |
5488 | if (port == PORT_D) | |
5489 | intel_encoder->crtc_mask = 1 << 2; | |
5490 | else | |
5491 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
5492 | } else { | |
5493 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
5494 | } | |
bc079e8b | 5495 | intel_encoder->cloneable = 0; |
f0fec3f2 PZ |
5496 | intel_encoder->hot_plug = intel_dp_hot_plug; |
5497 | ||
13cf5504 DA |
5498 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
5499 | dev_priv->hpd_irq_port[port] = intel_dig_port; | |
5500 | ||
15b1d171 PZ |
5501 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { |
5502 | drm_encoder_cleanup(encoder); | |
5503 | kfree(intel_dig_port); | |
b2f246a8 | 5504 | kfree(intel_connector); |
15b1d171 | 5505 | } |
f0fec3f2 | 5506 | } |
0e32b39c DA |
5507 | |
5508 | void intel_dp_mst_suspend(struct drm_device *dev) | |
5509 | { | |
5510 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5511 | int i; | |
5512 | ||
5513 | /* disable MST */ | |
5514 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5515 | struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i]; | |
5516 | if (!intel_dig_port) | |
5517 | continue; | |
5518 | ||
5519 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
5520 | if (!intel_dig_port->dp.can_mst) | |
5521 | continue; | |
5522 | if (intel_dig_port->dp.is_mst) | |
5523 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); | |
5524 | } | |
5525 | } | |
5526 | } | |
5527 | ||
5528 | void intel_dp_mst_resume(struct drm_device *dev) | |
5529 | { | |
5530 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5531 | int i; | |
5532 | ||
5533 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5534 | struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i]; | |
5535 | if (!intel_dig_port) | |
5536 | continue; | |
5537 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
5538 | int ret; | |
5539 | ||
5540 | if (!intel_dig_port->dp.can_mst) | |
5541 | continue; | |
5542 | ||
5543 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); | |
5544 | if (ret != 0) { | |
5545 | intel_dp_check_mst_status(&intel_dig_port->dp); | |
5546 | } | |
5547 | } | |
5548 | } | |
5549 | } |