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drm/i915: Hide underruns from eDP PLL and port enable on ILK
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf 50struct dp_link_dpll {
840b32b7 51 int clock;
9dd4ffdf
CML		 52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
840b32b7 56 { 162000,
9dd4ffdf 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
840b32b7 58 { 270000,
9dd4ffdf
CML		 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
840b32b7 63 { 162000,
9dd4ffdf 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
840b32b7 65 { 270000,
9dd4ffdf
CML		 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5 69static const struct dp_link_dpll vlv_dpll[] = {
840b32b7 70 { 162000,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
840b32b7 72 { 270000,
65ce4bf5
CML		 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
840b32b7 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
ef9348c8 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
840b32b7 88 { 270000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
840b32b7 90 { 540000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8
CML		 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15
VS		 97 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 99
cfcb0fc9
JB		 100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
da63a9f2
PZ		 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 112}
113
68b4d824 114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 115{
68b4d824
ID		 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 119}
120
df0e9248
CW		 121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
fa90ecef 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 124}
125
ea5b213a 126static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
a4fc5ed6 132
e0fce78f
VS		 133static unsigned int intel_dp_unused_lane_mask(int lane_count)
134{
135 return ~((1 << lane_count) - 1) & 0xf;
136}
137
ed4e9c1d
VS		 138static int
139intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 140{
7183dc29 141 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 142
143 switch (max_link_bw) {
144 case DP_LINK_BW_1_62:
145 case DP_LINK_BW_2_7:
1db10e28 146 case DP_LINK_BW_5_4:
d4eead50 147 break;
a4fc5ed6 148 default:
d4eead50
ID		 149 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
150 max_link_bw);
a4fc5ed6
KP		 151 max_link_bw = DP_LINK_BW_1_62;
152 break;
153 }
154 return max_link_bw;
155}
156
eeb6324d
PZ		 157static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
158{
159 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
160 struct drm_device *dev = intel_dig_port->base.base.dev;
161 u8 source_max, sink_max;
162
163 source_max = 4;
164 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
165 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
166 source_max = 2;
167
168 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
169
170 return min(source_max, sink_max);
171}
172
cd9dde44
AJ		 173/*
174 * The units on the numbers in the next two are... bizarre. Examples will
175 * make it clearer; this one parallels an example in the eDP spec.
176 *
177 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
178 *
179 * 270000 * 1 * 8 / 10 == 216000
180 *
181 * The actual data capacity of that configuration is 2.16Gbit/s, so the
182 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
183 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
184 * 119000. At 18bpp that's 2142000 kilobits per second.
185 *
186 * Thus the strange-looking division by 10 in intel_dp_link_required, to
187 * get the result in decakilobits instead of kilobits.
188 */
189
a4fc5ed6 190static int
c898261c 191intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 192{
cd9dde44 193 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 194}
195
fe27d53e
DA		 196static int
197intel_dp_max_data_rate(int max_link_clock, int max_lanes)
198{
199 return (max_link_clock * max_lanes * 8) / 10;
200}
201
c19de8eb 202static enum drm_mode_status
a4fc5ed6
KP		 203intel_dp_mode_valid(struct drm_connector *connector,
204 struct drm_display_mode *mode)
205{
df0e9248 206 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 207 struct intel_connector *intel_connector = to_intel_connector(connector);
208 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 209 int target_clock = mode->clock;
210 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 211
dd06f90e
JN		 212 if (is_edp(intel_dp) && fixed_mode) {
213 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 214 return MODE_PANEL;
215
dd06f90e 216 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 217 return MODE_PANEL;
03afc4a2
DV		 218
219 target_clock = fixed_mode->clock;
7de56f43
ZY		 220 }
221
50fec21a 222 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 223 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 224
225 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
226 mode_rate = intel_dp_link_required(target_clock, 18);
227
228 if (mode_rate > max_rate)
c4867936 229 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 230
231 if (mode->clock < 10000)
232 return MODE_CLOCK_LOW;
233
0af78a2b
DV		 234 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
235 return MODE_H_ILLEGAL;
236
a4fc5ed6
KP		 237 return MODE_OK;
238}
239
a4f1289e 240uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 241{
242 int i;
243 uint32_t v = 0;
244
245 if (src_bytes > 4)
246 src_bytes = 4;
247 for (i = 0; i < src_bytes; i++)
248 v |= ((uint32_t) src[i]) << ((3-i) * 8);
249 return v;
250}
251
c2af70e2 252static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 253{
254 int i;
255 if (dst_bytes > 4)
256 dst_bytes = 4;
257 for (i = 0; i < dst_bytes; i++)
258 dst[i] = src >> ((3-i) * 8);
259}
260
bf13e81b
JN		 261static void
262intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 263 struct intel_dp *intel_dp);
bf13e81b
JN		 264static void
265intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 266 struct intel_dp *intel_dp);
bf13e81b 267
773538e8
VS		 268static void pps_lock(struct intel_dp *intel_dp)
269{
270 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
271 struct intel_encoder *encoder = &intel_dig_port->base;
272 struct drm_device *dev = encoder->base.dev;
273 struct drm_i915_private *dev_priv = dev->dev_private;
274 enum intel_display_power_domain power_domain;
275
276 /*
277 * See vlv_power_sequencer_reset() why we need
278 * a power domain reference here.
279 */
280 power_domain = intel_display_port_power_domain(encoder);
281 intel_display_power_get(dev_priv, power_domain);
282
283 mutex_lock(&dev_priv->pps_mutex);
284}
285
286static void pps_unlock(struct intel_dp *intel_dp)
287{
288 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
289 struct intel_encoder *encoder = &intel_dig_port->base;
290 struct drm_device *dev = encoder->base.dev;
291 struct drm_i915_private *dev_priv = dev->dev_private;
292 enum intel_display_power_domain power_domain;
293
294 mutex_unlock(&dev_priv->pps_mutex);
295
296 power_domain = intel_display_port_power_domain(encoder);
297 intel_display_power_put(dev_priv, power_domain);
298}
299
961a0db0
VS		 300static void
301vlv_power_sequencer_kick(struct intel_dp *intel_dp)
302{
303 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
304 struct drm_device *dev = intel_dig_port->base.base.dev;
305 struct drm_i915_private *dev_priv = dev->dev_private;
306 enum pipe pipe = intel_dp->pps_pipe;
0047eedc
VS		 307 bool pll_enabled, release_cl_override = false;
308 enum dpio_phy phy = DPIO_PHY(pipe);
309 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
961a0db0
VS		 310 uint32_t DP;
311
312 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
313 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
314 pipe_name(pipe), port_name(intel_dig_port->port)))
315 return;
316
317 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
318 pipe_name(pipe), port_name(intel_dig_port->port));
319
320 /* Preserve the BIOS-computed detected bit. This is
321 * supposed to be read-only.
322 */
323 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
324 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
325 DP |= DP_PORT_WIDTH(1);
326 DP |= DP_LINK_TRAIN_PAT_1;
327
328 if (IS_CHERRYVIEW(dev))
329 DP |= DP_PIPE_SELECT_CHV(pipe);
330 else if (pipe == PIPE_B)
331 DP |= DP_PIPEB_SELECT;
332
d288f65f
VS		 333 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
334
335 /*
336 * The DPLL for the pipe must be enabled for this to work.
337 * So enable temporarily it if it's not already enabled.
338 */
0047eedc
VS		 339 if (!pll_enabled) {
340 release_cl_override = IS_CHERRYVIEW(dev) &&
341 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
342
d288f65f
VS		 343 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
344 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
0047eedc 345 }
d288f65f 346
961a0db0
VS		 347 /*
348 * Similar magic as in intel_dp_enable_port().
349 * We _must_ do this port enable + disable trick
350 * to make this power seqeuencer lock onto the port.
351 * Otherwise even VDD force bit won't work.
352 */
353 I915_WRITE(intel_dp->output_reg, DP);
354 POSTING_READ(intel_dp->output_reg);
355
356 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
357 POSTING_READ(intel_dp->output_reg);
358
359 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
360 POSTING_READ(intel_dp->output_reg);
d288f65f 361
0047eedc 362 if (!pll_enabled) {
d288f65f 363 vlv_force_pll_off(dev, pipe);
0047eedc
VS		 364
365 if (release_cl_override)
366 chv_phy_powergate_ch(dev_priv, phy, ch, false);
367 }
961a0db0
VS		 368}
369
bf13e81b
JN		 370static enum pipe
371vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
372{
373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 374 struct drm_device *dev = intel_dig_port->base.base.dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 376 struct intel_encoder *encoder;
377 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 378 enum pipe pipe;
bf13e81b 379
e39b999a 380 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 381
a8c3344e
VS		 382 /* We should never land here with regular DP ports */
383 WARN_ON(!is_edp(intel_dp));
384
a4a5d2f8
VS		 385 if (intel_dp->pps_pipe != INVALID_PIPE)
386 return intel_dp->pps_pipe;
387
388 /*
389 * We don't have power sequencer currently.
390 * Pick one that's not used by other ports.
391 */
392 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
393 base.head) {
394 struct intel_dp *tmp;
395
396 if (encoder->type != INTEL_OUTPUT_EDP)
397 continue;
398
399 tmp = enc_to_intel_dp(&encoder->base);
400
401 if (tmp->pps_pipe != INVALID_PIPE)
402 pipes &= ~(1 << tmp->pps_pipe);
403 }
404
405 /*
406 * Didn't find one. This should not happen since there
407 * are two power sequencers and up to two eDP ports.
408 */
409 if (WARN_ON(pipes == 0))
a8c3344e
VS		 410 pipe = PIPE_A;
411 else
412 pipe = ffs(pipes) - 1;
a4a5d2f8 413
a8c3344e
VS		 414 vlv_steal_power_sequencer(dev, pipe);
415 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 416
417 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
418 pipe_name(intel_dp->pps_pipe),
419 port_name(intel_dig_port->port));
420
421 /* init power sequencer on this pipe and port */
36b5f425
VS		 422 intel_dp_init_panel_power_sequencer(dev, intel_dp);
423 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 424
961a0db0
VS		 425 /*
426 * Even vdd force doesn't work until we've made
427 * the power sequencer lock in on the port.
428 */
429 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 430
431 return intel_dp->pps_pipe;
432}
433
6491ab27
VS		 434typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
435 enum pipe pipe);
436
437static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
438 enum pipe pipe)
439{
440 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
441}
442
443static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
444 enum pipe pipe)
445{
446 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
447}
448
449static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
450 enum pipe pipe)
451{
452 return true;
453}
bf13e81b 454
a4a5d2f8 455static enum pipe
6491ab27
VS		 456vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
457 enum port port,
458 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 459{
460 enum pipe pipe;
bf13e81b 461
bf13e81b
JN		 462 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
463 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
464 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 465
466 if (port_sel != PANEL_PORT_SELECT_VLV(port))
467 continue;
468
6491ab27
VS		 469 if (!pipe_check(dev_priv, pipe))
470 continue;
471
a4a5d2f8 472 return pipe;
bf13e81b
JN		 473 }
474
a4a5d2f8
VS		 475 return INVALID_PIPE;
476}
477
478static void
479vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
480{
481 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
482 struct drm_device *dev = intel_dig_port->base.base.dev;
483 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 484 enum port port = intel_dig_port->port;
485
486 lockdep_assert_held(&dev_priv->pps_mutex);
487
488 /* try to find a pipe with this port selected */
6491ab27
VS		 489 /* first pick one where the panel is on */
490 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
491 vlv_pipe_has_pp_on);
492 /* didn't find one? pick one where vdd is on */
493 if (intel_dp->pps_pipe == INVALID_PIPE)
494 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
495 vlv_pipe_has_vdd_on);
496 /* didn't find one? pick one with just the correct port */
497 if (intel_dp->pps_pipe == INVALID_PIPE)
498 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
499 vlv_pipe_any);
a4a5d2f8
VS		 500
501 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
502 if (intel_dp->pps_pipe == INVALID_PIPE) {
503 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
504 port_name(port));
505 return;
bf13e81b
JN		 506 }
507
a4a5d2f8
VS		 508 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
509 port_name(port), pipe_name(intel_dp->pps_pipe));
510
36b5f425
VS		 511 intel_dp_init_panel_power_sequencer(dev, intel_dp);
512 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 513}
514
773538e8
VS		 515void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
516{
517 struct drm_device *dev = dev_priv->dev;
518 struct intel_encoder *encoder;
519
520 if (WARN_ON(!IS_VALLEYVIEW(dev)))
521 return;
522
523 /*
524 * We can't grab pps_mutex here due to deadlock with power_domain
525 * mutex when power_domain functions are called while holding pps_mutex.
526 * That also means that in order to use pps_pipe the code needs to
527 * hold both a power domain reference and pps_mutex, and the power domain
528 * reference get/put must be done while _not_ holding pps_mutex.
529 * pps_{lock,unlock}() do these steps in the correct order, so one
530 * should use them always.
531 */
532
533 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
534 struct intel_dp *intel_dp;
535
536 if (encoder->type != INTEL_OUTPUT_EDP)
537 continue;
538
539 intel_dp = enc_to_intel_dp(&encoder->base);
540 intel_dp->pps_pipe = INVALID_PIPE;
541 }
bf13e81b
JN		 542}
543
544static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
545{
546 struct drm_device *dev = intel_dp_to_dev(intel_dp);
547
b0a08bec
VK		 548 if (IS_BROXTON(dev))
549 return BXT_PP_CONTROL(0);
550 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 551 return PCH_PP_CONTROL;
552 else
553 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
554}
555
556static u32 _pp_stat_reg(struct intel_dp *intel_dp)
557{
558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
559
b0a08bec
VK		 560 if (IS_BROXTON(dev))
561 return BXT_PP_STATUS(0);
562 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 563 return PCH_PP_STATUS;
564 else
565 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
566}
567
01527b31
CT		 568/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
569 This function only applicable when panel PM state is not to be tracked */
570static int edp_notify_handler(struct notifier_block *this, unsigned long code,
571 void *unused)
572{
573 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
574 edp_notifier);
575 struct drm_device *dev = intel_dp_to_dev(intel_dp);
576 struct drm_i915_private *dev_priv = dev->dev_private;
01527b31
CT		 577
578 if (!is_edp(intel_dp) || code != SYS_RESTART)
579 return 0;
580
773538e8 581 pps_lock(intel_dp);
e39b999a 582
01527b31 583 if (IS_VALLEYVIEW(dev)) {
e39b999a 584 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
649636ef
VS		 585 u32 pp_ctrl_reg, pp_div_reg;
586 u32 pp_div;
e39b999a 587
01527b31
CT		 588 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
589 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
590 pp_div = I915_READ(pp_div_reg);
591 pp_div &= PP_REFERENCE_DIVIDER_MASK;
592
593 /* 0x1F write to PP_DIV_REG sets max cycle delay */
594 I915_WRITE(pp_div_reg, pp_div | 0x1F);
595 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
596 msleep(intel_dp->panel_power_cycle_delay);
597 }
598
773538e8 599 pps_unlock(intel_dp);
e39b999a 600
01527b31
CT		 601 return 0;
602}
603
4be73780 604static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 605{
30add22d 606 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 607 struct drm_i915_private *dev_priv = dev->dev_private;
608
e39b999a
VS		 609 lockdep_assert_held(&dev_priv->pps_mutex);
610
9a42356b
VS		 611 if (IS_VALLEYVIEW(dev) &&
612 intel_dp->pps_pipe == INVALID_PIPE)
613 return false;
614
bf13e81b 615 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 616}
617
4be73780 618static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 619{
30add22d 620 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 621 struct drm_i915_private *dev_priv = dev->dev_private;
622
e39b999a
VS		 623 lockdep_assert_held(&dev_priv->pps_mutex);
624
9a42356b
VS		 625 if (IS_VALLEYVIEW(dev) &&
626 intel_dp->pps_pipe == INVALID_PIPE)
627 return false;
628
773538e8 629 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 630}
631
9b984dae
KP		 632static void
633intel_dp_check_edp(struct intel_dp *intel_dp)
634{
30add22d 635 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 636 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 637
9b984dae
KP		 638 if (!is_edp(intel_dp))
639 return;
453c5420 640
4be73780 641 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 642 WARN(1, "eDP powered off while attempting aux channel communication.\n");
643 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 644 I915_READ(_pp_stat_reg(intel_dp)),
645 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 646 }
647}
648
9ee32fea
DV		 649static uint32_t
650intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
651{
652 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
653 struct drm_device *dev = intel_dig_port->base.base.dev;
654 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 655 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 656 uint32_t status;
657 bool done;
658
ef04f00d 659#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 660 if (has_aux_irq)
b18ac466 661 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 662 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 663 else
664 done = wait_for_atomic(C, 10) == 0;
665 if (!done)
666 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
667 has_aux_irq);
668#undef C
669
670 return status;
671}
672
ec5b01dd 673static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 674{
174edf1f
PZ		 675 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
676 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 677
ec5b01dd
DL		 678 /*
679 * The clock divider is based off the hrawclk, and would like to run at
680 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 681 */
ec5b01dd
DL		 682 return index ? 0 : intel_hrawclk(dev) / 2;
683}
684
685static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
686{
687 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
688 struct drm_device *dev = intel_dig_port->base.base.dev;
469d4b2a 689 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd
DL		 690
691 if (index)
692 return 0;
693
694 if (intel_dig_port->port == PORT_A) {
05024da3
VS		 695 return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);
696
ec5b01dd
DL		 697 } else {
698 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
699 }
700}
701
702static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
703{
704 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
705 struct drm_device *dev = intel_dig_port->base.base.dev;
706 struct drm_i915_private *dev_priv = dev->dev_private;
707
708 if (intel_dig_port->port == PORT_A) {
709 if (index)
710 return 0;
05024da3 711 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
2c55c336
JN		 712 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
713 /* Workaround for non-ULT HSW */
bc86625a
CW		 714 switch (index) {
715 case 0: return 63;
716 case 1: return 72;
717 default: return 0;
718 }
ec5b01dd 719 } else {
bc86625a 720 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 721 }
b84a1cf8
RV		 722}
723
ec5b01dd
DL		 724static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
725{
726 return index ? 0 : 100;
727}
728
b6b5e383
DL		 729static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
730{
731 /*
732 * SKL doesn't need us to program the AUX clock divider (Hardware will
733 * derive the clock from CDCLK automatically). We still implement the
734 * get_aux_clock_divider vfunc to plug-in into the existing code.
735 */
736 return index ? 0 : 1;
737}
738
5ed12a19
DL		 739static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
740 bool has_aux_irq,
741 int send_bytes,
742 uint32_t aux_clock_divider)
743{
744 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
745 struct drm_device *dev = intel_dig_port->base.base.dev;
746 uint32_t precharge, timeout;
747
748 if (IS_GEN6(dev))
749 precharge = 3;
750 else
751 precharge = 5;
752
753 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
754 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
755 else
756 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
757
758 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 759 DP_AUX_CH_CTL_DONE |
5ed12a19 760 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 761 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 762 timeout |
788d4433 763 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 764 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
765 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 766 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 767}
768
b9ca5fad
DL		 769static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
770 bool has_aux_irq,
771 int send_bytes,
772 uint32_t unused)
773{
774 return DP_AUX_CH_CTL_SEND_BUSY |
775 DP_AUX_CH_CTL_DONE |
776 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
777 DP_AUX_CH_CTL_TIME_OUT_ERROR |
778 DP_AUX_CH_CTL_TIME_OUT_1600us |
779 DP_AUX_CH_CTL_RECEIVE_ERROR |
780 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
781 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
782}
783
b84a1cf8
RV		 784static int
785intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 786 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 787 uint8_t *recv, int recv_size)
788{
789 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
790 struct drm_device *dev = intel_dig_port->base.base.dev;
791 struct drm_i915_private *dev_priv = dev->dev_private;
792 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
793 uint32_t ch_data = ch_ctl + 4;
bc86625a 794 uint32_t aux_clock_divider;
b84a1cf8
RV		 795 int i, ret, recv_bytes;
796 uint32_t status;
5ed12a19 797 int try, clock = 0;
4e6b788c 798 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 799 bool vdd;
800
773538e8 801 pps_lock(intel_dp);
e39b999a 802
72c3500a
VS		 803 /*
804 * We will be called with VDD already enabled for dpcd/edid/oui reads.
805 * In such cases we want to leave VDD enabled and it's up to upper layers
806 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
807 * ourselves.
808 */
1e0560e0 809 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 810
811 /* dp aux is extremely sensitive to irq latency, hence request the
812 * lowest possible wakeup latency and so prevent the cpu from going into
813 * deep sleep states.
814 */
815 pm_qos_update_request(&dev_priv->pm_qos, 0);
816
817 intel_dp_check_edp(intel_dp);
5eb08b69 818
c67a470b
PZ		 819 intel_aux_display_runtime_get(dev_priv);
820
11bee43e
JB		 821 /* Try to wait for any previous AUX channel activity */
822 for (try = 0; try < 3; try++) {
ef04f00d 823 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 824 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
825 break;
826 msleep(1);
827 }
828
829 if (try == 3) {
02196c77
MK		 830 static u32 last_status = -1;
831 const u32 status = I915_READ(ch_ctl);
832
833 if (status != last_status) {
834 WARN(1, "dp_aux_ch not started status 0x%08x\n",
835 status);
836 last_status = status;
837 }
838
9ee32fea
DV		 839 ret = -EBUSY;
840 goto out;
4f7f7b7e
CW		 841 }
842
46a5ae9f
PZ		 843 /* Only 5 data registers! */
844 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
845 ret = -E2BIG;
846 goto out;
847 }
848
ec5b01dd 849 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 850 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
851 has_aux_irq,
852 send_bytes,
853 aux_clock_divider);
5ed12a19 854
bc86625a
CW		 855 /* Must try at least 3 times according to DP spec */
856 for (try = 0; try < 5; try++) {
857 /* Load the send data into the aux channel data registers */
858 for (i = 0; i < send_bytes; i += 4)
859 I915_WRITE(ch_data + i,
a4f1289e
RV		 860 intel_dp_pack_aux(send + i,
861 send_bytes - i));
bc86625a
CW		 862
863 /* Send the command and wait for it to complete */
5ed12a19 864 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 865
866 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
867
868 /* Clear done status and any errors */
869 I915_WRITE(ch_ctl,
870 status |
871 DP_AUX_CH_CTL_DONE |
872 DP_AUX_CH_CTL_TIME_OUT_ERROR |
873 DP_AUX_CH_CTL_RECEIVE_ERROR);
874
74ebf294 875 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 876 continue;
74ebf294
TP		 877
878 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
879 * 400us delay required for errors and timeouts
880 * Timeout errors from the HW already meet this
881 * requirement so skip to next iteration
882 */
883 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
884 usleep_range(400, 500);
bc86625a 885 continue;
74ebf294 886 }
bc86625a 887 if (status & DP_AUX_CH_CTL_DONE)
e058c945 888 goto done;
bc86625a 889 }
a4fc5ed6
KP		 890 }
891
a4fc5ed6 892 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 893 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 894 ret = -EBUSY;
895 goto out;
a4fc5ed6
KP		 896 }
897
e058c945 898done:
a4fc5ed6
KP		 899 /* Check for timeout or receive error.
900 * Timeouts occur when the sink is not connected
901 */
a5b3da54 902 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 903 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 904 ret = -EIO;
905 goto out;
a5b3da54 906 }
1ae8c0a5
KP		 907
908 /* Timeouts occur when the device isn't connected, so they're
909 * "normal" -- don't fill the kernel log with these */
a5b3da54 910 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 911 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 912 ret = -ETIMEDOUT;
913 goto out;
a4fc5ed6
KP		 914 }
915
916 /* Unload any bytes sent back from the other side */
917 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
918 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 919 if (recv_bytes > recv_size)
920 recv_bytes = recv_size;
0206e353 921
4f7f7b7e 922 for (i = 0; i < recv_bytes; i += 4)
a4f1289e
RV		 923 intel_dp_unpack_aux(I915_READ(ch_data + i),
924 recv + i, recv_bytes - i);
a4fc5ed6 925
9ee32fea
DV		 926 ret = recv_bytes;
927out:
928 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 929 intel_aux_display_runtime_put(dev_priv);
9ee32fea 930
884f19e9
JN		 931 if (vdd)
932 edp_panel_vdd_off(intel_dp, false);
933
773538e8 934 pps_unlock(intel_dp);
e39b999a 935
9ee32fea 936 return ret;
a4fc5ed6
KP		 937}
938
a6c8aff0
JN		 939#define BARE_ADDRESS_SIZE 3
940#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 941static ssize_t
942intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 943{
9d1a1031
JN		 944 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
945 uint8_t txbuf[20], rxbuf[20];
946 size_t txsize, rxsize;
a4fc5ed6 947 int ret;
a4fc5ed6 948
d2d9cbbd
VS		 949 txbuf[0] = (msg->request << 4) |
950 ((msg->address >> 16) & 0xf);
951 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 952 txbuf[2] = msg->address & 0xff;
953 txbuf[3] = msg->size - 1;
46a5ae9f 954
9d1a1031
JN		 955 switch (msg->request & ~DP_AUX_I2C_MOT) {
956 case DP_AUX_NATIVE_WRITE:
957 case DP_AUX_I2C_WRITE:
c1e74122 958 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
a6c8aff0 959 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 960 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 961
9d1a1031
JN		 962 if (WARN_ON(txsize > 20))
963 return -E2BIG;
a4fc5ed6 964
9d1a1031 965 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 966
9d1a1031
JN		 967 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
968 if (ret > 0) {
969 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 970
a1ddefd8
JN		 971 if (ret > 1) {
972 /* Number of bytes written in a short write. */
973 ret = clamp_t(int, rxbuf[1], 0, msg->size);
974 } else {
975 /* Return payload size. */
976 ret = msg->size;
977 }
9d1a1031
JN		 978 }
979 break;
46a5ae9f 980
9d1a1031
JN		 981 case DP_AUX_NATIVE_READ:
982 case DP_AUX_I2C_READ:
a6c8aff0 983 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 984 rxsize = msg->size + 1;
a4fc5ed6 985
9d1a1031
JN		 986 if (WARN_ON(rxsize > 20))
987 return -E2BIG;
a4fc5ed6 988
9d1a1031
JN		 989 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
990 if (ret > 0) {
991 msg->reply = rxbuf[0] >> 4;
992 /*
993 * Assume happy day, and copy the data. The caller is
994 * expected to check msg->reply before touching it.
995 *
996 * Return payload size.
997 */
998 ret--;
999 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1000 }
9d1a1031
JN		 1001 break;
1002
1003 default:
1004 ret = -EINVAL;
1005 break;
a4fc5ed6 1006 }
f51a44b9 1007
9d1a1031 1008 return ret;
a4fc5ed6
KP		 1009}
1010
9d1a1031
JN		 1011static void
1012intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1013{
1014 struct drm_device *dev = intel_dp_to_dev(intel_dp);
500ea70d 1015 struct drm_i915_private *dev_priv = dev->dev_private;
33ad6626
JN		 1016 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1017 enum port port = intel_dig_port->port;
500ea70d 1018 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
0b99836f 1019 const char *name = NULL;
500ea70d 1020 uint32_t porte_aux_ctl_reg = DPA_AUX_CH_CTL;
ab2c0672
DA		 1021 int ret;
1022
500ea70d
RV		 1023 /* On SKL we don't have Aux for port E so we rely on VBT to set
1024 * a proper alternate aux channel.
1025 */
ef11bdb3 1026 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && port == PORT_E) {
500ea70d
RV		 1027 switch (info->alternate_aux_channel) {
1028 case DP_AUX_B:
1029 porte_aux_ctl_reg = DPB_AUX_CH_CTL;
1030 break;
1031 case DP_AUX_C:
1032 porte_aux_ctl_reg = DPC_AUX_CH_CTL;
1033 break;
1034 case DP_AUX_D:
1035 porte_aux_ctl_reg = DPD_AUX_CH_CTL;
1036 break;
1037 case DP_AUX_A:
1038 default:
1039 porte_aux_ctl_reg = DPA_AUX_CH_CTL;
1040 }
1041 }
1042
33ad6626
JN		 1043 switch (port) {
1044 case PORT_A:
1045 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 1046 name = "DPDDC-A";
ab2c0672 1047 break;
33ad6626
JN		 1048 case PORT_B:
1049 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1050 name = "DPDDC-B";
ab2c0672 1051 break;
33ad6626
JN		 1052 case PORT_C:
1053 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1054 name = "DPDDC-C";
ab2c0672 1055 break;
33ad6626
JN		 1056 case PORT_D:
1057 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1058 name = "DPDDC-D";
33ad6626 1059 break;
500ea70d
RV		 1060 case PORT_E:
1061 intel_dp->aux_ch_ctl_reg = porte_aux_ctl_reg;
1062 name = "DPDDC-E";
1063 break;
33ad6626
JN		 1064 default:
1065 BUG();
ab2c0672
DA		 1066 }
1067
1b1aad75
DL		 1068 /*
1069 * The AUX_CTL register is usually DP_CTL + 0x10.
1070 *
1071 * On Haswell and Broadwell though:
1072 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1073 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1074 *
1075 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1076 */
500ea70d 1077 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && port != PORT_E)
33ad6626 1078 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1079
0b99836f 1080 intel_dp->aux.name = name;
9d1a1031
JN		 1081 intel_dp->aux.dev = dev->dev;
1082 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1083
0b99836f
JN		 1084 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1085 connector->base.kdev->kobj.name);
8316f337 1086
4f71d0cb 1087 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1088 if (ret < 0) {
4f71d0cb 1089 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1090 name, ret);
1091 return;
ab2c0672 1092 }
8a5e6aeb 1093
0b99836f
JN		 1094 ret = sysfs_create_link(&connector->base.kdev->kobj,
1095 &intel_dp->aux.ddc.dev.kobj,
1096 intel_dp->aux.ddc.dev.kobj.name);
1097 if (ret < 0) {
1098 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1099 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1100 }
a4fc5ed6
KP		 1101}
1102
80f65de3
ID		 1103static void
1104intel_dp_connector_unregister(struct intel_connector *intel_connector)
1105{
1106 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1107
0e32b39c
DA		 1108 if (!intel_connector->mst_port)
1109 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1110 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1111 intel_connector_unregister(intel_connector);
1112}
1113
5416d871 1114static void
840b32b7 1115skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
5416d871
DL		 1116{
1117 u32 ctrl1;
1118
dd3cd74a
ACO		 1119 memset(&pipe_config->dpll_hw_state, 0,
1120 sizeof(pipe_config->dpll_hw_state));
1121
5416d871
DL		 1122 pipe_config->ddi_pll_sel = SKL_DPLL0;
1123 pipe_config->dpll_hw_state.cfgcr1 = 0;
1124 pipe_config->dpll_hw_state.cfgcr2 = 0;
1125
1126 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
840b32b7 1127 switch (pipe_config->port_clock / 2) {
c3346ef6 1128 case 81000:
71cd8423 1129 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5416d871
DL		 1130 SKL_DPLL0);
1131 break;
c3346ef6 1132 case 135000:
71cd8423 1133 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
5416d871
DL		 1134 SKL_DPLL0);
1135 break;
c3346ef6 1136 case 270000:
71cd8423 1137 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
5416d871
DL		 1138 SKL_DPLL0);
1139 break;
c3346ef6 1140 case 162000:
71cd8423 1141 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
c3346ef6
SJ		 1142 SKL_DPLL0);
1143 break;
1144 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1145 results in CDCLK change. Need to handle the change of CDCLK by
1146 disabling pipes and re-enabling them */
1147 case 108000:
71cd8423 1148 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
c3346ef6
SJ		 1149 SKL_DPLL0);
1150 break;
1151 case 216000:
71cd8423 1152 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
c3346ef6
SJ		 1153 SKL_DPLL0);
1154 break;
1155
5416d871
DL		 1156 }
1157 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1158}
1159
6fa2d197 1160void
840b32b7 1161hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
0e50338c 1162{
ee46f3c7
ACO		 1163 memset(&pipe_config->dpll_hw_state, 0,
1164 sizeof(pipe_config->dpll_hw_state));
1165
840b32b7
VS		 1166 switch (pipe_config->port_clock / 2) {
1167 case 81000:
0e50338c
DV		 1168 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1169 break;
840b32b7 1170 case 135000:
0e50338c
DV		 1171 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1172 break;
840b32b7 1173 case 270000:
0e50338c
DV		 1174 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1175 break;
1176 }
1177}
1178
fc0f8e25 1179static int
12f6a2e2 1180intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1181{
94ca719e
VS		 1182 if (intel_dp->num_sink_rates) {
1183 *sink_rates = intel_dp->sink_rates;
1184 return intel_dp->num_sink_rates;
fc0f8e25 1185 }
12f6a2e2
VS		 1186
1187 *sink_rates = default_rates;
1188
1189 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1190}
1191
e588fa18 1192bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
ed63baaf 1193{
e588fa18
ACO		 1194 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1195 struct drm_device *dev = dig_port->base.base.dev;
1196
ed63baaf 1197 /* WaDisableHBR2:skl */
e87a005d 1198 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
ed63baaf
TS		 1199 return false;
1200
1201 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1202 (INTEL_INFO(dev)->gen >= 9))
1203 return true;
1204 else
1205 return false;
1206}
1207
a8f3ef61 1208static int
e588fa18 1209intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
a8f3ef61 1210{
e588fa18
ACO		 1211 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1212 struct drm_device *dev = dig_port->base.base.dev;
af7080f5
TS		 1213 int size;
1214
64987fc5
SJ		 1215 if (IS_BROXTON(dev)) {
1216 *source_rates = bxt_rates;
af7080f5 1217 size = ARRAY_SIZE(bxt_rates);
ef11bdb3 1218 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
637a9c63 1219 *source_rates = skl_rates;
af7080f5
TS		 1220 size = ARRAY_SIZE(skl_rates);
1221 } else {
1222 *source_rates = default_rates;
1223 size = ARRAY_SIZE(default_rates);
a8f3ef61 1224 }
636280ba 1225
ed63baaf 1226 /* This depends on the fact that 5.4 is last value in the array */
e588fa18 1227 if (!intel_dp_source_supports_hbr2(intel_dp))
af7080f5 1228 size--;
636280ba 1229
af7080f5 1230 return size;
a8f3ef61
SJ		 1231}
1232
c6bb3538
DV		 1233static void
1234intel_dp_set_clock(struct intel_encoder *encoder,
840b32b7 1235 struct intel_crtc_state *pipe_config)
c6bb3538
DV		 1236{
1237 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1238 const struct dp_link_dpll *divisor = NULL;
1239 int i, count = 0;
c6bb3538
DV		 1240
1241 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1242 divisor = gen4_dpll;
1243 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1244 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1245 divisor = pch_dpll;
1246 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1247 } else if (IS_CHERRYVIEW(dev)) {
1248 divisor = chv_dpll;
1249 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1250 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1251 divisor = vlv_dpll;
1252 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1253 }
9dd4ffdf
CML		 1254
1255 if (divisor && count) {
1256 for (i = 0; i < count; i++) {
840b32b7 1257 if (pipe_config->port_clock == divisor[i].clock) {
9dd4ffdf
CML		 1258 pipe_config->dpll = divisor[i].dpll;
1259 pipe_config->clock_set = true;
1260 break;
1261 }
1262 }
c6bb3538
DV		 1263 }
1264}
1265
2ecae76a
VS		 1266static int intersect_rates(const int *source_rates, int source_len,
1267 const int *sink_rates, int sink_len,
94ca719e 1268 int *common_rates)
a8f3ef61
SJ		 1269{
1270 int i = 0, j = 0, k = 0;
1271
a8f3ef61
SJ		 1272 while (i < source_len && j < sink_len) {
1273 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1274 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1275 return k;
94ca719e 1276 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1277 ++k;
1278 ++i;
1279 ++j;
1280 } else if (source_rates[i] < sink_rates[j]) {
1281 ++i;
1282 } else {
1283 ++j;
1284 }
1285 }
1286 return k;
1287}
1288
94ca719e
VS		 1289static int intel_dp_common_rates(struct intel_dp *intel_dp,
1290 int *common_rates)
2ecae76a 1291{
2ecae76a
VS		 1292 const int *source_rates, *sink_rates;
1293 int source_len, sink_len;
1294
1295 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
e588fa18 1296 source_len = intel_dp_source_rates(intel_dp, &source_rates);
2ecae76a
VS		 1297
1298 return intersect_rates(source_rates, source_len,
1299 sink_rates, sink_len,
94ca719e 1300 common_rates);
2ecae76a
VS		 1301}
1302
0336400e
VS		 1303static void snprintf_int_array(char *str, size_t len,
1304 const int *array, int nelem)
1305{
1306 int i;
1307
1308 str[0] = '\0';
1309
1310 for (i = 0; i < nelem; i++) {
b2f505be 1311 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1312 if (r >= len)
1313 return;
1314 str += r;
1315 len -= r;
1316 }
1317}
1318
1319static void intel_dp_print_rates(struct intel_dp *intel_dp)
1320{
0336400e 1321 const int *source_rates, *sink_rates;
94ca719e
VS		 1322 int source_len, sink_len, common_len;
1323 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1324 char str[128]; /* FIXME: too big for stack? */
1325
1326 if ((drm_debug & DRM_UT_KMS) == 0)
1327 return;
1328
e588fa18 1329 source_len = intel_dp_source_rates(intel_dp, &source_rates);
0336400e
VS		 1330 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1331 DRM_DEBUG_KMS("source rates: %s\n", str);
1332
1333 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1334 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1335 DRM_DEBUG_KMS("sink rates: %s\n", str);
1336
94ca719e
VS		 1337 common_len = intel_dp_common_rates(intel_dp, common_rates);
1338 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1339 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1340}
1341
f4896f15 1342static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1343{
1344 int i = 0;
1345
1346 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1347 if (find == rates[i])
1348 break;
1349
1350 return i;
1351}
1352
50fec21a
VS		 1353int
1354intel_dp_max_link_rate(struct intel_dp *intel_dp)
1355{
1356 int rates[DP_MAX_SUPPORTED_RATES] = {};
1357 int len;
1358
94ca719e 1359 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1360 if (WARN_ON(len <= 0))
1361 return 162000;
1362
1363 return rates[rate_to_index(0, rates) - 1];
1364}
1365
ed4e9c1d
VS		 1366int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1367{
94ca719e 1368 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1369}
1370
94223d04
ACO		 1371void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1372 uint8_t *link_bw, uint8_t *rate_select)
04a60f9f
VS		 1373{
1374 if (intel_dp->num_sink_rates) {
1375 *link_bw = 0;
1376 *rate_select =
1377 intel_dp_rate_select(intel_dp, port_clock);
1378 } else {
1379 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1380 *rate_select = 0;
1381 }
1382}
1383
00c09d70 1384bool
5bfe2ac0 1385intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1386 struct intel_crtc_state *pipe_config)
a4fc5ed6 1387{
5bfe2ac0 1388 struct drm_device *dev = encoder->base.dev;
36008365 1389 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1390 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1391 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1392 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1393 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1394 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1395 int lane_count, clock;
56071a20 1396 int min_lane_count = 1;
eeb6324d 1397 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1398 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1399 int min_clock = 0;
a8f3ef61 1400 int max_clock;
083f9560 1401 int bpp, mode_rate;
ff9a6750 1402 int link_avail, link_clock;
94ca719e
VS		 1403 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1404 int common_len;
04a60f9f 1405 uint8_t link_bw, rate_select;
a8f3ef61 1406
94ca719e 1407 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1408
1409 /* No common link rates between source and sink */
94ca719e 1410 WARN_ON(common_len <= 0);
a8f3ef61 1411
94ca719e 1412 max_clock = common_len - 1;
a4fc5ed6 1413
bc7d38a4 1414 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1415 pipe_config->has_pch_encoder = true;
1416
03afc4a2 1417 pipe_config->has_dp_encoder = true;
f769cd24 1418 pipe_config->has_drrs = false;
9fcb1704 1419 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1420
dd06f90e
JN		 1421 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1422 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1423 adjusted_mode);
a1b2278e
CK		 1424
1425 if (INTEL_INFO(dev)->gen >= 9) {
1426 int ret;
e435d6e5 1427 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1428 if (ret)
1429 return ret;
1430 }
1431
b5667627 1432 if (HAS_GMCH_DISPLAY(dev))
2dd24552
JB		 1433 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1434 intel_connector->panel.fitting_mode);
1435 else
b074cec8
JB		 1436 intel_pch_panel_fitting(intel_crtc, pipe_config,
1437 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1438 }
1439
cb1793ce 1440 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1441 return false;
1442
083f9560 1443 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1444 "max bw %d pixel clock %iKHz\n",
94ca719e 1445 max_lane_count, common_rates[max_clock],
241bfc38 1446 adjusted_mode->crtc_clock);
083f9560 1447
36008365
DV		 1448 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1449 * bpc in between. */
3e7ca985 1450 bpp = pipe_config->pipe_bpp;
56071a20 1451 if (is_edp(intel_dp)) {
22ce5628
TS		 1452
1453 /* Get bpp from vbt only for panels that dont have bpp in edid */
1454 if (intel_connector->base.display_info.bpc == 0 &&
1455 (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) {
56071a20
JN		 1456 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1457 dev_priv->vbt.edp_bpp);
1458 bpp = dev_priv->vbt.edp_bpp;
1459 }
1460
344c5bbc
JN		 1461 /*
1462 * Use the maximum clock and number of lanes the eDP panel
1463 * advertizes being capable of. The panels are generally
1464 * designed to support only a single clock and lane
1465 * configuration, and typically these values correspond to the
1466 * native resolution of the panel.
1467 */
1468 min_lane_count = max_lane_count;
1469 min_clock = max_clock;
7984211e 1470 }
657445fe 1471
36008365 1472 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1473 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1474 bpp);
36008365 1475
c6930992 1476 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1477 for (lane_count = min_lane_count;
1478 lane_count <= max_lane_count;
1479 lane_count <<= 1) {
1480
94ca719e 1481 link_clock = common_rates[clock];
36008365
DV		 1482 link_avail = intel_dp_max_data_rate(link_clock,
1483 lane_count);
1484
1485 if (mode_rate <= link_avail) {
1486 goto found;
1487 }
1488 }
1489 }
1490 }
c4867936 1491
36008365 1492 return false;
3685a8f3 1493
36008365 1494found:
55bc60db
VS		 1495 if (intel_dp->color_range_auto) {
1496 /*
1497 * See:
1498 * CEA-861-E - 5.1 Default Encoding Parameters
1499 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1500 */
0f2a2a75
VS		 1501 pipe_config->limited_color_range =
1502 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1503 } else {
1504 pipe_config->limited_color_range =
1505 intel_dp->limited_color_range;
55bc60db
VS		 1506 }
1507
90a6b7b0 1508 pipe_config->lane_count = lane_count;
a8f3ef61 1509
657445fe 1510 pipe_config->pipe_bpp = bpp;
94ca719e 1511 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1512
04a60f9f
VS		 1513 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1514 &link_bw, &rate_select);
1515
1516 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1517 link_bw, rate_select, pipe_config->lane_count,
ff9a6750 1518 pipe_config->port_clock, bpp);
36008365
DV		 1519 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1520 mode_rate, link_avail);
a4fc5ed6 1521
03afc4a2 1522 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1523 adjusted_mode->crtc_clock,
1524 pipe_config->port_clock,
03afc4a2 1525 &pipe_config->dp_m_n);
9d1a455b 1526
439d7ac0 1527 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1528 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1529 pipe_config->has_drrs = true;
439d7ac0
PB		 1530 intel_link_compute_m_n(bpp, lane_count,
1531 intel_connector->panel.downclock_mode->clock,
1532 pipe_config->port_clock,
1533 &pipe_config->dp_m2_n2);
1534 }
1535
ef11bdb3 1536 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp))
840b32b7 1537 skl_edp_set_pll_config(pipe_config);
977bb38d
S		 1538 else if (IS_BROXTON(dev))
1539 /* handled in ddi */;
5416d871 1540 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
840b32b7 1541 hsw_dp_set_ddi_pll_sel(pipe_config);
0e50338c 1542 else
840b32b7 1543 intel_dp_set_clock(encoder, pipe_config);
c6bb3538 1544
03afc4a2 1545 return true;
a4fc5ed6
KP		 1546}
1547
7c62a164 1548static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1549{
7c62a164
DV		 1550 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1551 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1552 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1553 struct drm_i915_private *dev_priv = dev->dev_private;
1554 u32 dpa_ctl;
1555
6e3c9717
ACO		 1556 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1557 crtc->config->port_clock);
ea9b6006
DV		 1558 dpa_ctl = I915_READ(DP_A);
1559 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1560
6e3c9717 1561 if (crtc->config->port_clock == 162000) {
1ce17038
DV		 1562 /* For a long time we've carried around a ILK-DevA w/a for the
1563 * 160MHz clock. If we're really unlucky, it's still required.
1564 */
1565 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1566 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1567 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1568 } else {
1569 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1570 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1571 }
1ce17038 1572
ea9b6006
DV		 1573 I915_WRITE(DP_A, dpa_ctl);
1574
1575 POSTING_READ(DP_A);
1576 udelay(500);
1577}
1578
901c2daf
VS		 1579void intel_dp_set_link_params(struct intel_dp *intel_dp,
1580 const struct intel_crtc_state *pipe_config)
1581{
1582 intel_dp->link_rate = pipe_config->port_clock;
1583 intel_dp->lane_count = pipe_config->lane_count;
1584}
1585
8ac33ed3 1586static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1587{
b934223d 1588 struct drm_device *dev = encoder->base.dev;
417e822d 1589 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1590 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1591 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1592 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
7c5f93b0 1593 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1594
901c2daf
VS		 1595 intel_dp_set_link_params(intel_dp, crtc->config);
1596
417e822d 1597 /*
1a2eb460 1598 * There are four kinds of DP registers:
417e822d
KP		 1599 *
1600 * IBX PCH
1a2eb460
KP		 1601 * SNB CPU
1602 * IVB CPU
417e822d
KP		 1603 * CPT PCH
1604 *
1605 * IBX PCH and CPU are the same for almost everything,
1606 * except that the CPU DP PLL is configured in this
1607 * register
1608 *
1609 * CPT PCH is quite different, having many bits moved
1610 * to the TRANS_DP_CTL register instead. That
1611 * configuration happens (oddly) in ironlake_pch_enable
1612 */
9c9e7927 1613
417e822d
KP		 1614 /* Preserve the BIOS-computed detected bit. This is
1615 * supposed to be read-only.
1616 */
1617 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1618
417e822d 1619 /* Handle DP bits in common between all three register formats */
417e822d 1620 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
90a6b7b0 1621 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
a4fc5ed6 1622
6e3c9717 1623 if (crtc->config->has_audio)
ea5b213a 1624 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
247d89f6 1625
417e822d 1626 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1627
39e5fa88 1628 if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1629 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1630 intel_dp->DP |= DP_SYNC_HS_HIGH;
1631 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1632 intel_dp->DP |= DP_SYNC_VS_HIGH;
1633 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1634
6aba5b6c 1635 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1636 intel_dp->DP |= DP_ENHANCED_FRAMING;
1637
7c62a164 1638 intel_dp->DP |= crtc->pipe << 29;
39e5fa88 1639 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
e3ef4479
VS		 1640 u32 trans_dp;
1641
39e5fa88 1642 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1643
1644 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1645 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1646 trans_dp |= TRANS_DP_ENH_FRAMING;
1647 else
1648 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1649 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1650 } else {
0f2a2a75
VS		 1651 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1652 crtc->config->limited_color_range)
1653 intel_dp->DP |= DP_COLOR_RANGE_16_235;
417e822d
KP		 1654
1655 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1656 intel_dp->DP |= DP_SYNC_HS_HIGH;
1657 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1658 intel_dp->DP |= DP_SYNC_VS_HIGH;
1659 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1660
6aba5b6c 1661 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1662 intel_dp->DP |= DP_ENHANCED_FRAMING;
1663
39e5fa88 1664 if (IS_CHERRYVIEW(dev))
44f37d1f 1665 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1666 else if (crtc->pipe == PIPE_B)
1667 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1668 }
a4fc5ed6
KP		 1669}
1670
ffd6749d
PZ		 1671#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1672#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1673
1a5ef5b7
PZ		 1674#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1675#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1676
ffd6749d
PZ		 1677#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1678#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1679
4be73780 1680static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1681 u32 mask,
1682 u32 value)
bd943159 1683{
30add22d 1684 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1685 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1686 u32 pp_stat_reg, pp_ctrl_reg;
1687
e39b999a
VS		 1688 lockdep_assert_held(&dev_priv->pps_mutex);
1689
bf13e81b
JN		 1690 pp_stat_reg = _pp_stat_reg(intel_dp);
1691 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1692
99ea7127 1693 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1694 mask, value,
1695 I915_READ(pp_stat_reg),
1696 I915_READ(pp_ctrl_reg));
32ce697c 1697
453c5420 1698 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1699 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1700 I915_READ(pp_stat_reg),
1701 I915_READ(pp_ctrl_reg));
32ce697c 1702 }
54c136d4
CW		 1703
1704 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1705}
32ce697c 1706
4be73780 1707static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1708{
1709 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1710 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1711}
1712
4be73780 1713static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1714{
1715 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1716 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1717}
1718
4be73780 1719static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1720{
1721 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1722
1723 /* When we disable the VDD override bit last we have to do the manual
1724 * wait. */
1725 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1726 intel_dp->panel_power_cycle_delay);
1727
4be73780 1728 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1729}
1730
4be73780 1731static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1732{
1733 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1734 intel_dp->backlight_on_delay);
1735}
1736
4be73780 1737static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1738{
1739 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1740 intel_dp->backlight_off_delay);
1741}
99ea7127 1742
832dd3c1
KP		 1743/* Read the current pp_control value, unlocking the register if it
1744 * is locked
1745 */
1746
453c5420 1747static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1748{
453c5420
JB		 1749 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1750 struct drm_i915_private *dev_priv = dev->dev_private;
1751 u32 control;
832dd3c1 1752
e39b999a
VS		 1753 lockdep_assert_held(&dev_priv->pps_mutex);
1754
bf13e81b 1755 control = I915_READ(_pp_ctrl_reg(intel_dp));
b0a08bec
VK		 1756 if (!IS_BROXTON(dev)) {
1757 control &= ~PANEL_UNLOCK_MASK;
1758 control |= PANEL_UNLOCK_REGS;
1759 }
832dd3c1 1760 return control;
bd943159
KP		 1761}
1762
951468f3
VS		 1763/*
1764 * Must be paired with edp_panel_vdd_off().
1765 * Must hold pps_mutex around the whole on/off sequence.
1766 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1767 */
1e0560e0 1768static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1769{
30add22d 1770 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1771 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1772 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1773 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1774 enum intel_display_power_domain power_domain;
5d613501 1775 u32 pp;
453c5420 1776 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1777 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1778
e39b999a
VS		 1779 lockdep_assert_held(&dev_priv->pps_mutex);
1780
97af61f5 1781 if (!is_edp(intel_dp))
adddaaf4 1782 return false;
bd943159 1783
2c623c11 1784 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1785 intel_dp->want_panel_vdd = true;
99ea7127 1786
4be73780 1787 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1788 return need_to_disable;
b0665d57 1789
4e6e1a54
ID		 1790 power_domain = intel_display_port_power_domain(intel_encoder);
1791 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1792
3936fcf4
VS		 1793 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1794 port_name(intel_dig_port->port));
bd943159 1795
4be73780
DV		 1796 if (!edp_have_panel_power(intel_dp))
1797 wait_panel_power_cycle(intel_dp);
99ea7127 1798
453c5420 1799 pp = ironlake_get_pp_control(intel_dp);
5d613501 1800 pp |= EDP_FORCE_VDD;
ebf33b18 1801
bf13e81b
JN		 1802 pp_stat_reg = _pp_stat_reg(intel_dp);
1803 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1804
1805 I915_WRITE(pp_ctrl_reg, pp);
1806 POSTING_READ(pp_ctrl_reg);
1807 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1808 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1809 /*
1810 * If the panel wasn't on, delay before accessing aux channel
1811 */
4be73780 1812 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1813 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1814 port_name(intel_dig_port->port));
f01eca2e 1815 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1816 }
adddaaf4
JN		 1817
1818 return need_to_disable;
1819}
1820
951468f3
VS		 1821/*
1822 * Must be paired with intel_edp_panel_vdd_off() or
1823 * intel_edp_panel_off().
1824 * Nested calls to these functions are not allowed since
1825 * we drop the lock. Caller must use some higher level
1826 * locking to prevent nested calls from other threads.
1827 */
b80d6c78 1828void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1829{
c695b6b6 1830 bool vdd;
adddaaf4 1831
c695b6b6
VS		 1832 if (!is_edp(intel_dp))
1833 return;
1834
773538e8 1835 pps_lock(intel_dp);
c695b6b6 1836 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1837 pps_unlock(intel_dp);
c695b6b6 1838
e2c719b7 1839 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1840 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1841}
1842
4be73780 1843static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1844{
30add22d 1845 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1846 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1847 struct intel_digital_port *intel_dig_port =
1848 dp_to_dig_port(intel_dp);
1849 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1850 enum intel_display_power_domain power_domain;
5d613501 1851 u32 pp;
453c5420 1852 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1853
e39b999a 1854 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1855
15e899a0 1856 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1857
15e899a0 1858 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1859 return;
b0665d57 1860
3936fcf4
VS		 1861 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1862 port_name(intel_dig_port->port));
bd943159 1863
be2c9196
VS		 1864 pp = ironlake_get_pp_control(intel_dp);
1865 pp &= ~EDP_FORCE_VDD;
453c5420 1866
be2c9196
VS		 1867 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1868 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1869
be2c9196
VS		 1870 I915_WRITE(pp_ctrl_reg, pp);
1871 POSTING_READ(pp_ctrl_reg);
90791a5c 1872
be2c9196
VS		 1873 /* Make sure sequencer is idle before allowing subsequent activity */
1874 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1875 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1876
be2c9196
VS		 1877 if ((pp & POWER_TARGET_ON) == 0)
1878 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1879
be2c9196
VS		 1880 power_domain = intel_display_port_power_domain(intel_encoder);
1881 intel_display_power_put(dev_priv, power_domain);
bd943159 1882}
5d613501 1883
4be73780 1884static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1885{
1886 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1887 struct intel_dp, panel_vdd_work);
bd943159 1888
773538e8 1889 pps_lock(intel_dp);
15e899a0
VS		 1890 if (!intel_dp->want_panel_vdd)
1891 edp_panel_vdd_off_sync(intel_dp);
773538e8 1892 pps_unlock(intel_dp);
bd943159
KP		 1893}
1894
aba86890
ID		 1895static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1896{
1897 unsigned long delay;
1898
1899 /*
1900 * Queue the timer to fire a long time from now (relative to the power
1901 * down delay) to keep the panel power up across a sequence of
1902 * operations.
1903 */
1904 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1905 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1906}
1907
951468f3
VS		 1908/*
1909 * Must be paired with edp_panel_vdd_on().
1910 * Must hold pps_mutex around the whole on/off sequence.
1911 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1912 */
4be73780 1913static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1914{
e39b999a
VS		 1915 struct drm_i915_private *dev_priv =
1916 intel_dp_to_dev(intel_dp)->dev_private;
1917
1918 lockdep_assert_held(&dev_priv->pps_mutex);
1919
97af61f5
KP		 1920 if (!is_edp(intel_dp))
1921 return;
5d613501 1922
e2c719b7 1923 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1924 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1925
bd943159
KP		 1926 intel_dp->want_panel_vdd = false;
1927
aba86890 1928 if (sync)
4be73780 1929 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1930 else
1931 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1932}
1933
9f0fb5be 1934static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1935{
30add22d 1936 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1937 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1938 u32 pp;
453c5420 1939 u32 pp_ctrl_reg;
9934c132 1940
9f0fb5be
VS		 1941 lockdep_assert_held(&dev_priv->pps_mutex);
1942
97af61f5 1943 if (!is_edp(intel_dp))
bd943159 1944 return;
99ea7127 1945
3936fcf4
VS		 1946 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1947 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1948
e7a89ace
VS		 1949 if (WARN(edp_have_panel_power(intel_dp),
1950 "eDP port %c panel power already on\n",
1951 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1952 return;
9934c132 1953
4be73780 1954 wait_panel_power_cycle(intel_dp);
37c6c9b0 1955
bf13e81b 1956 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1957 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1958 if (IS_GEN5(dev)) {
1959 /* ILK workaround: disable reset around power sequence */
1960 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1961 I915_WRITE(pp_ctrl_reg, pp);
1962 POSTING_READ(pp_ctrl_reg);
05ce1a49 1963 }
37c6c9b0 1964
1c0ae80a 1965 pp |= POWER_TARGET_ON;
99ea7127
KP		 1966 if (!IS_GEN5(dev))
1967 pp |= PANEL_POWER_RESET;
1968
453c5420
JB		 1969 I915_WRITE(pp_ctrl_reg, pp);
1970 POSTING_READ(pp_ctrl_reg);
9934c132 1971
4be73780 1972 wait_panel_on(intel_dp);
dce56b3c 1973 intel_dp->last_power_on = jiffies;
9934c132 1974
05ce1a49
KP		 1975 if (IS_GEN5(dev)) {
1976 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1977 I915_WRITE(pp_ctrl_reg, pp);
1978 POSTING_READ(pp_ctrl_reg);
05ce1a49 1979 }
9f0fb5be 1980}
e39b999a 1981
9f0fb5be
VS		 1982void intel_edp_panel_on(struct intel_dp *intel_dp)
1983{
1984 if (!is_edp(intel_dp))
1985 return;
1986
1987 pps_lock(intel_dp);
1988 edp_panel_on(intel_dp);
773538e8 1989 pps_unlock(intel_dp);
9934c132
JB		 1990}
1991
9f0fb5be
VS		 1992
1993static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1994{
4e6e1a54
ID		 1995 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1996 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1997 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1998 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1999 enum intel_display_power_domain power_domain;
99ea7127 2000 u32 pp;
453c5420 2001 u32 pp_ctrl_reg;
9934c132 2002
9f0fb5be
VS		 2003 lockdep_assert_held(&dev_priv->pps_mutex);
2004
97af61f5
KP		 2005 if (!is_edp(intel_dp))
2006 return;
37c6c9b0 2007
3936fcf4
VS		 2008 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2009 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 2010
3936fcf4
VS		 2011 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2012 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 2013
453c5420 2014 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 2015 /* We need to switch off panel power _and_ force vdd, for otherwise some
2016 * panels get very unhappy and cease to work. */
b3064154
PJ		 2017 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2018 EDP_BLC_ENABLE);
453c5420 2019
bf13e81b 2020 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2021
849e39f5
PZ		 2022 intel_dp->want_panel_vdd = false;
2023
453c5420
JB		 2024 I915_WRITE(pp_ctrl_reg, pp);
2025 POSTING_READ(pp_ctrl_reg);
9934c132 2026
dce56b3c 2027 intel_dp->last_power_cycle = jiffies;
4be73780 2028 wait_panel_off(intel_dp);
849e39f5
PZ		 2029
2030 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 2031 power_domain = intel_display_port_power_domain(intel_encoder);
2032 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 2033}
e39b999a 2034
9f0fb5be
VS		 2035void intel_edp_panel_off(struct intel_dp *intel_dp)
2036{
2037 if (!is_edp(intel_dp))
2038 return;
e39b999a 2039
9f0fb5be
VS		 2040 pps_lock(intel_dp);
2041 edp_panel_off(intel_dp);
773538e8 2042 pps_unlock(intel_dp);
9934c132
JB		 2043}
2044
1250d107
JN		 2045/* Enable backlight in the panel power control. */
2046static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2047{
da63a9f2
PZ		 2048 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2049 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 2050 struct drm_i915_private *dev_priv = dev->dev_private;
2051 u32 pp;
453c5420 2052 u32 pp_ctrl_reg;
32f9d658 2053
01cb9ea6
JB		 2054 /*
2055 * If we enable the backlight right away following a panel power
2056 * on, we may see slight flicker as the panel syncs with the eDP
2057 * link. So delay a bit to make sure the image is solid before
2058 * allowing it to appear.
2059 */
4be73780 2060 wait_backlight_on(intel_dp);
e39b999a 2061
773538e8 2062 pps_lock(intel_dp);
e39b999a 2063
453c5420 2064 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2065 pp |= EDP_BLC_ENABLE;
453c5420 2066
bf13e81b 2067 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2068
2069 I915_WRITE(pp_ctrl_reg, pp);
2070 POSTING_READ(pp_ctrl_reg);
e39b999a 2071
773538e8 2072 pps_unlock(intel_dp);
32f9d658
ZW		 2073}
2074
1250d107
JN		 2075/* Enable backlight PWM and backlight PP control. */
2076void intel_edp_backlight_on(struct intel_dp *intel_dp)
2077{
2078 if (!is_edp(intel_dp))
2079 return;
2080
2081 DRM_DEBUG_KMS("\n");
2082
2083 intel_panel_enable_backlight(intel_dp->attached_connector);
2084 _intel_edp_backlight_on(intel_dp);
2085}
2086
2087/* Disable backlight in the panel power control. */
2088static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2089{
30add22d 2090 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 2091 struct drm_i915_private *dev_priv = dev->dev_private;
2092 u32 pp;
453c5420 2093 u32 pp_ctrl_reg;
32f9d658 2094
f01eca2e
KP		 2095 if (!is_edp(intel_dp))
2096 return;
2097
773538e8 2098 pps_lock(intel_dp);
e39b999a 2099
453c5420 2100 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2101 pp &= ~EDP_BLC_ENABLE;
453c5420 2102
bf13e81b 2103 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2104
2105 I915_WRITE(pp_ctrl_reg, pp);
2106 POSTING_READ(pp_ctrl_reg);
f7d2323c 2107
773538e8 2108 pps_unlock(intel_dp);
e39b999a
VS		 2109
2110 intel_dp->last_backlight_off = jiffies;
f7d2323c 2111 edp_wait_backlight_off(intel_dp);
1250d107 2112}
f7d2323c 2113
1250d107
JN		 2114/* Disable backlight PP control and backlight PWM. */
2115void intel_edp_backlight_off(struct intel_dp *intel_dp)
2116{
2117 if (!is_edp(intel_dp))
2118 return;
2119
2120 DRM_DEBUG_KMS("\n");
f7d2323c 2121
1250d107 2122 _intel_edp_backlight_off(intel_dp);
f7d2323c 2123 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2124}
a4fc5ed6 2125
73580fb7
JN		 2126/*
2127 * Hook for controlling the panel power control backlight through the bl_power
2128 * sysfs attribute. Take care to handle multiple calls.
2129 */
2130static void intel_edp_backlight_power(struct intel_connector *connector,
2131 bool enable)
2132{
2133 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2134 bool is_enabled;
2135
773538e8 2136 pps_lock(intel_dp);
e39b999a 2137 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2138 pps_unlock(intel_dp);
73580fb7
JN		 2139
2140 if (is_enabled == enable)
2141 return;
2142
23ba9373
JN		 2143 DRM_DEBUG_KMS("panel power control backlight %s\n",
2144 enable ? "enable" : "disable");
73580fb7
JN		 2145
2146 if (enable)
2147 _intel_edp_backlight_on(intel_dp);
2148 else
2149 _intel_edp_backlight_off(intel_dp);
2150}
2151
2bd2ad64 2152static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2153{
da63a9f2
PZ		 2154 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2155 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2156 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2157 struct drm_i915_private *dev_priv = dev->dev_private;
2158 u32 dpa_ctl;
2159
2bd2ad64
DV		 2160 assert_pipe_disabled(dev_priv,
2161 to_intel_crtc(crtc)->pipe);
2162
d240f20f
JB		 2163 DRM_DEBUG_KMS("\n");
2164 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2165 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
2166 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2167
2168 /* We don't adjust intel_dp->DP while tearing down the link, to
2169 * facilitate link retraining (e.g. after hotplug). Hence clear all
2170 * enable bits here to ensure that we don't enable too much. */
2171 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
2172 intel_dp->DP |= DP_PLL_ENABLE;
2173 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2174 POSTING_READ(DP_A);
2175 udelay(200);
d240f20f
JB		 2176}
2177
2bd2ad64 2178static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2179{
da63a9f2
PZ		 2180 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2181 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2182 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2183 struct drm_i915_private *dev_priv = dev->dev_private;
2184 u32 dpa_ctl;
2185
2bd2ad64
DV		 2186 assert_pipe_disabled(dev_priv,
2187 to_intel_crtc(crtc)->pipe);
2188
d240f20f 2189 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2190 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
2191 "dp pll off, should be on\n");
2192 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2193
2194 /* We can't rely on the value tracked for the DP register in
2195 * intel_dp->DP because link_down must not change that (otherwise link
2196 * re-training will fail. */
298b0b39 2197 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 2198 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 2199 POSTING_READ(DP_A);
d240f20f
JB		 2200 udelay(200);
2201}
2202
c7ad3810 2203/* If the sink supports it, try to set the power state appropriately */
c19b0669 2204void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2205{
2206 int ret, i;
2207
2208 /* Should have a valid DPCD by this point */
2209 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2210 return;
2211
2212 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2213 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2214 DP_SET_POWER_D3);
c7ad3810
JB		 2215 } else {
2216 /*
2217 * When turning on, we need to retry for 1ms to give the sink
2218 * time to wake up.
2219 */
2220 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2221 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2222 DP_SET_POWER_D0);
c7ad3810
JB		 2223 if (ret == 1)
2224 break;
2225 msleep(1);
2226 }
2227 }
f9cac721
JN		 2228
2229 if (ret != 1)
2230 DRM_DEBUG_KMS("failed to %s sink power state\n",
2231 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2232}
2233
19d8fe15
DV		 2234static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2235 enum pipe *pipe)
d240f20f 2236{
19d8fe15 2237 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2238 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2239 struct drm_device *dev = encoder->base.dev;
2240 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2241 enum intel_display_power_domain power_domain;
2242 u32 tmp;
2243
2244 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 2245 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 2246 return false;
2247
2248 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2249
2250 if (!(tmp & DP_PORT_EN))
2251 return false;
2252
39e5fa88 2253 if (IS_GEN7(dev) && port == PORT_A) {
19d8fe15 2254 *pipe = PORT_TO_PIPE_CPT(tmp);
39e5fa88 2255 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
adc289d7 2256 enum pipe p;
19d8fe15 2257
adc289d7
VS		 2258 for_each_pipe(dev_priv, p) {
2259 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2260 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2261 *pipe = p;
19d8fe15
DV		 2262 return true;
2263 }
2264 }
19d8fe15 2265
4a0833ec
DV		 2266 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2267 intel_dp->output_reg);
39e5fa88
VS		 2268 } else if (IS_CHERRYVIEW(dev)) {
2269 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2270 } else {
2271 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2272 }
d240f20f 2273
19d8fe15
DV		 2274 return true;
2275}
d240f20f 2276
045ac3b5 2277static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2278 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2279{
2280 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2281 u32 tmp, flags = 0;
63000ef6
XZ		 2282 struct drm_device *dev = encoder->base.dev;
2283 struct drm_i915_private *dev_priv = dev->dev_private;
2284 enum port port = dp_to_dig_port(intel_dp)->port;
2285 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 2286 int dotclock;
045ac3b5 2287
9ed109a7 2288 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2289
2290 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2291
39e5fa88 2292 if (HAS_PCH_CPT(dev) && port != PORT_A) {
b81e34c2
VS		 2293 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2294
2295 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2296 flags |= DRM_MODE_FLAG_PHSYNC;
2297 else
2298 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2299
b81e34c2 2300 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2301 flags |= DRM_MODE_FLAG_PVSYNC;
2302 else
2303 flags |= DRM_MODE_FLAG_NVSYNC;
2304 } else {
39e5fa88 2305 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2306 flags |= DRM_MODE_FLAG_PHSYNC;
2307 else
2308 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2309
39e5fa88 2310 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2311 flags |= DRM_MODE_FLAG_PVSYNC;
2312 else
2313 flags |= DRM_MODE_FLAG_NVSYNC;
2314 }
045ac3b5 2315
2d112de7 2316 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2317
8c875fca
VS		 2318 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2319 tmp & DP_COLOR_RANGE_16_235)
2320 pipe_config->limited_color_range = true;
2321
eb14cb74
VS		 2322 pipe_config->has_dp_encoder = true;
2323
90a6b7b0
VS		 2324 pipe_config->lane_count =
2325 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2326
eb14cb74
VS		 2327 intel_dp_get_m_n(crtc, pipe_config);
2328
18442d08 2329 if (port == PORT_A) {
f1f644dc
JB		 2330 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2331 pipe_config->port_clock = 162000;
2332 else
2333 pipe_config->port_clock = 270000;
2334 }
18442d08
VS		 2335
2336 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2337 &pipe_config->dp_m_n);
2338
2339 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2340 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2341
2d112de7 2342 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2343
c6cd2ee2
JN		 2344 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2345 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2346 /*
2347 * This is a big fat ugly hack.
2348 *
2349 * Some machines in UEFI boot mode provide us a VBT that has 18
2350 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2351 * unknown we fail to light up. Yet the same BIOS boots up with
2352 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2353 * max, not what it tells us to use.
2354 *
2355 * Note: This will still be broken if the eDP panel is not lit
2356 * up by the BIOS, and thus we can't get the mode at module
2357 * load.
2358 */
2359 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2360 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2361 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2362 }
045ac3b5
JB		 2363}
2364
e8cb4558 2365static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2366{
e8cb4558 2367 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2368 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2369 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2370
6e3c9717 2371 if (crtc->config->has_audio)
495a5bb8 2372 intel_audio_codec_disable(encoder);
6cb49835 2373
b32c6f48
RV		 2374 if (HAS_PSR(dev) && !HAS_DDI(dev))
2375 intel_psr_disable(intel_dp);
2376
6cb49835
DV		 2377 /* Make sure the panel is off before trying to change the mode. But also
2378 * ensure that we have vdd while we switch off the panel. */
24f3e092 2379 intel_edp_panel_vdd_on(intel_dp);
4be73780 2380 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2381 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2382 intel_edp_panel_off(intel_dp);
3739850b 2383
08aff3fe
VS		 2384 /* disable the port before the pipe on g4x */
2385 if (INTEL_INFO(dev)->gen < 5)
3739850b 2386 intel_dp_link_down(intel_dp);
d240f20f
JB		 2387}
2388
08aff3fe 2389static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2390{
2bd2ad64 2391 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2392 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2393
49277c31 2394 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2395 if (port == PORT_A)
2396 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2397}
2398
2399static void vlv_post_disable_dp(struct intel_encoder *encoder)
2400{
2401 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2402
2403 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2404}
2405
a8f327fb
VS		 2406static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
2407 bool reset)
580d3811 2408{
a8f327fb
VS		 2409 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2410 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
2411 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2412 enum pipe pipe = crtc->pipe;
2413 uint32_t val;
580d3811 2414
a8f327fb
VS		 2415 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2416 if (reset)
2417 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2418 else
2419 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2420 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
580d3811 2421
a8f327fb
VS		 2422 if (crtc->config->lane_count > 2) {
2423 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2424 if (reset)
2425 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2426 else
2427 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2428 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2429 }
580d3811 2430
97fd4d5c 2431 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2432 val |= CHV_PCS_REQ_SOFTRESET_EN;
a8f327fb
VS		 2433 if (reset)
2434 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2435 else
2436 val |= DPIO_PCS_CLK_SOFT_RESET;
97fd4d5c 2437 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2438
a8f327fb 2439 if (crtc->config->lane_count > 2) {
e0fce78f
VS		 2440 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2441 val |= CHV_PCS_REQ_SOFTRESET_EN;
a8f327fb
VS		 2442 if (reset)
2443 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2444 else
2445 val |= DPIO_PCS_CLK_SOFT_RESET;
e0fce78f
VS		 2446 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2447 }
a8f327fb 2448}
97fd4d5c 2449
a8f327fb
VS		 2450static void chv_post_disable_dp(struct intel_encoder *encoder)
2451{
2452 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2453 struct drm_device *dev = encoder->base.dev;
2454 struct drm_i915_private *dev_priv = dev->dev_private;
97fd4d5c 2455
a8f327fb
VS		 2456 intel_dp_link_down(intel_dp);
2457
2458 mutex_lock(&dev_priv->sb_lock);
2459
2460 /* Assert data lane reset */
2461 chv_data_lane_soft_reset(encoder, true);
580d3811 2462
a580516d 2463 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2464}
2465
7b13b58a
VS		 2466static void
2467_intel_dp_set_link_train(struct intel_dp *intel_dp,
2468 uint32_t *DP,
2469 uint8_t dp_train_pat)
2470{
2471 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2472 struct drm_device *dev = intel_dig_port->base.base.dev;
2473 struct drm_i915_private *dev_priv = dev->dev_private;
2474 enum port port = intel_dig_port->port;
2475
2476 if (HAS_DDI(dev)) {
2477 uint32_t temp = I915_READ(DP_TP_CTL(port));
2478
2479 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2480 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2481 else
2482 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2483
2484 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2485 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2486 case DP_TRAINING_PATTERN_DISABLE:
2487 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2488
2489 break;
2490 case DP_TRAINING_PATTERN_1:
2491 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2492 break;
2493 case DP_TRAINING_PATTERN_2:
2494 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2495 break;
2496 case DP_TRAINING_PATTERN_3:
2497 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2498 break;
2499 }
2500 I915_WRITE(DP_TP_CTL(port), temp);
2501
39e5fa88
VS		 2502 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2503 (HAS_PCH_CPT(dev) && port != PORT_A)) {
7b13b58a
VS		 2504 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2505
2506 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2507 case DP_TRAINING_PATTERN_DISABLE:
2508 *DP |= DP_LINK_TRAIN_OFF_CPT;
2509 break;
2510 case DP_TRAINING_PATTERN_1:
2511 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2512 break;
2513 case DP_TRAINING_PATTERN_2:
2514 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2515 break;
2516 case DP_TRAINING_PATTERN_3:
2517 DRM_ERROR("DP training pattern 3 not supported\n");
2518 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2519 break;
2520 }
2521
2522 } else {
2523 if (IS_CHERRYVIEW(dev))
2524 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2525 else
2526 *DP &= ~DP_LINK_TRAIN_MASK;
2527
2528 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2529 case DP_TRAINING_PATTERN_DISABLE:
2530 *DP |= DP_LINK_TRAIN_OFF;
2531 break;
2532 case DP_TRAINING_PATTERN_1:
2533 *DP |= DP_LINK_TRAIN_PAT_1;
2534 break;
2535 case DP_TRAINING_PATTERN_2:
2536 *DP |= DP_LINK_TRAIN_PAT_2;
2537 break;
2538 case DP_TRAINING_PATTERN_3:
2539 if (IS_CHERRYVIEW(dev)) {
2540 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2541 } else {
2542 DRM_ERROR("DP training pattern 3 not supported\n");
2543 *DP |= DP_LINK_TRAIN_PAT_2;
2544 }
2545 break;
2546 }
2547 }
2548}
2549
2550static void intel_dp_enable_port(struct intel_dp *intel_dp)
2551{
2552 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2553 struct drm_i915_private *dev_priv = dev->dev_private;
2554
7b13b58a
VS		 2555 /* enable with pattern 1 (as per spec) */
2556 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2557 DP_TRAINING_PATTERN_1);
2558
2559 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2560 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2561
2562 /*
2563 * Magic for VLV/CHV. We _must_ first set up the register
2564 * without actually enabling the port, and then do another
2565 * write to enable the port. Otherwise link training will
2566 * fail when the power sequencer is freshly used for this port.
2567 */
2568 intel_dp->DP |= DP_PORT_EN;
2569
2570 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2571 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2572}
2573
e8cb4558 2574static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2575{
e8cb4558
DV		 2576 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2577 struct drm_device *dev = encoder->base.dev;
2578 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2579 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2580 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
d6fbdd15
VS		 2581 enum port port = dp_to_dig_port(intel_dp)->port;
2582 enum pipe pipe = crtc->pipe;
5d613501 2583
0c33d8d7
DV		 2584 if (WARN_ON(dp_reg & DP_PORT_EN))
2585 return;
5d613501 2586
093e3f13
VS		 2587 pps_lock(intel_dp);
2588
2589 if (IS_VALLEYVIEW(dev))
2590 vlv_init_panel_power_sequencer(intel_dp);
2591
7b13b58a 2592 intel_dp_enable_port(intel_dp);
093e3f13 2593
d6fbdd15
VS		 2594 if (port == PORT_A && IS_GEN5(dev_priv)) {
2595 /*
2596 * Underrun reporting for the other pipe was disabled in
2597 * g4x_pre_enable_dp(). The eDP PLL and port have now been
2598 * enabled, so it's now safe to re-enable underrun reporting.
2599 */
2600 intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
2601 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
2602 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
2603 }
2604
093e3f13
VS		 2605 edp_panel_vdd_on(intel_dp);
2606 edp_panel_on(intel_dp);
2607 edp_panel_vdd_off(intel_dp, true);
2608
2609 pps_unlock(intel_dp);
2610
e0fce78f
VS		 2611 if (IS_VALLEYVIEW(dev)) {
2612 unsigned int lane_mask = 0x0;
2613
2614 if (IS_CHERRYVIEW(dev))
2615 lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2616
9b6de0a1
VS		 2617 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2618 lane_mask);
e0fce78f 2619 }
61234fa5 2620
f01eca2e 2621 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2622 intel_dp_start_link_train(intel_dp);
3ab9c637 2623 intel_dp_stop_link_train(intel_dp);
c1dec79a 2624
6e3c9717 2625 if (crtc->config->has_audio) {
c1dec79a 2626 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
d6fbdd15 2627 pipe_name(pipe));
c1dec79a
JN		 2628 intel_audio_codec_enable(encoder);
2629 }
ab1f90f9 2630}
89b667f8 2631
ecff4f3b
JN		 2632static void g4x_enable_dp(struct intel_encoder *encoder)
2633{
828f5c6e
JN		 2634 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2635
ecff4f3b 2636 intel_enable_dp(encoder);
4be73780 2637 intel_edp_backlight_on(intel_dp);
ab1f90f9 2638}
89b667f8 2639
ab1f90f9
JN		 2640static void vlv_enable_dp(struct intel_encoder *encoder)
2641{
828f5c6e
JN		 2642 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2643
4be73780 2644 intel_edp_backlight_on(intel_dp);
b32c6f48 2645 intel_psr_enable(intel_dp);
d240f20f
JB		 2646}
2647
ecff4f3b 2648static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9 2649{
d6fbdd15 2650 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ab1f90f9 2651 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6fbdd15
VS		 2652 enum port port = dp_to_dig_port(intel_dp)->port;
2653 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
ab1f90f9 2654
8ac33ed3
DV		 2655 intel_dp_prepare(encoder);
2656
d6fbdd15
VS		 2657 if (port == PORT_A && IS_GEN5(dev_priv)) {
2658 /*
2659 * We get FIFO underruns on the other pipe when
2660 * enabling the CPU eDP PLL, and when enabling CPU
2661 * eDP port. We could potentially avoid the PLL
2662 * underrun with a vblank wait just prior to enabling
2663 * the PLL, but that doesn't appear to help the port
2664 * enable case. Just sweep it all under the rug.
2665 */
2666 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
2667 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
2668 }
2669
d41f1efb 2670 /* Only ilk+ has port A */
d6fbdd15 2671 if (port == PORT_A) {
d41f1efb 2672 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2673 ironlake_edp_pll_on(intel_dp);
d41f1efb 2674 }
ab1f90f9
JN		 2675}
2676
83b84597
VS		 2677static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2678{
2679 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2680 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2681 enum pipe pipe = intel_dp->pps_pipe;
2682 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2683
2684 edp_panel_vdd_off_sync(intel_dp);
2685
2686 /*
2687 * VLV seems to get confused when multiple power seqeuencers
2688 * have the same port selected (even if only one has power/vdd
2689 * enabled). The failure manifests as vlv_wait_port_ready() failing
2690 * CHV on the other hand doesn't seem to mind having the same port
2691 * selected in multiple power seqeuencers, but let's clear the
2692 * port select always when logically disconnecting a power sequencer
2693 * from a port.
2694 */
2695 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2696 pipe_name(pipe), port_name(intel_dig_port->port));
2697 I915_WRITE(pp_on_reg, 0);
2698 POSTING_READ(pp_on_reg);
2699
2700 intel_dp->pps_pipe = INVALID_PIPE;
2701}
2702
a4a5d2f8
VS		 2703static void vlv_steal_power_sequencer(struct drm_device *dev,
2704 enum pipe pipe)
2705{
2706 struct drm_i915_private *dev_priv = dev->dev_private;
2707 struct intel_encoder *encoder;
2708
2709 lockdep_assert_held(&dev_priv->pps_mutex);
2710
ac3c12e4
VS		 2711 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2712 return;
2713
a4a5d2f8
VS		 2714 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2715 base.head) {
2716 struct intel_dp *intel_dp;
773538e8 2717 enum port port;
a4a5d2f8
VS		 2718
2719 if (encoder->type != INTEL_OUTPUT_EDP)
2720 continue;
2721
2722 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2723 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2724
2725 if (intel_dp->pps_pipe != pipe)
2726 continue;
2727
2728 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2729 pipe_name(pipe), port_name(port));
a4a5d2f8 2730
e02f9a06 2731 WARN(encoder->base.crtc,
034e43c6
VS		 2732 "stealing pipe %c power sequencer from active eDP port %c\n",
2733 pipe_name(pipe), port_name(port));
a4a5d2f8 2734
a4a5d2f8 2735 /* make sure vdd is off before we steal it */
83b84597 2736 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2737 }
2738}
2739
2740static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2741{
2742 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2743 struct intel_encoder *encoder = &intel_dig_port->base;
2744 struct drm_device *dev = encoder->base.dev;
2745 struct drm_i915_private *dev_priv = dev->dev_private;
2746 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2747
2748 lockdep_assert_held(&dev_priv->pps_mutex);
2749
093e3f13
VS		 2750 if (!is_edp(intel_dp))
2751 return;
2752
a4a5d2f8
VS		 2753 if (intel_dp->pps_pipe == crtc->pipe)
2754 return;
2755
2756 /*
2757 * If another power sequencer was being used on this
2758 * port previously make sure to turn off vdd there while
2759 * we still have control of it.
2760 */
2761 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2762 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2763
2764 /*
2765 * We may be stealing the power
2766 * sequencer from another port.
2767 */
2768 vlv_steal_power_sequencer(dev, crtc->pipe);
2769
2770 /* now it's all ours */
2771 intel_dp->pps_pipe = crtc->pipe;
2772
2773 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2774 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2775
2776 /* init power sequencer on this pipe and port */
36b5f425
VS		 2777 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2778 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2779}
2780
ab1f90f9 2781static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2782{
2bd2ad64 2783 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2784 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2785 struct drm_device *dev = encoder->base.dev;
89b667f8 2786 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2787 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2788 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2789 int pipe = intel_crtc->pipe;
2790 u32 val;
a4fc5ed6 2791
a580516d 2792 mutex_lock(&dev_priv->sb_lock);
89b667f8 2793
ab3c759a 2794 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2795 val = 0;
2796 if (pipe)
2797 val |= (1<<21);
2798 else
2799 val &= ~(1<<21);
2800 val |= 0x001000c4;
ab3c759a
CML		 2801 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2802 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2803 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2804
a580516d 2805 mutex_unlock(&dev_priv->sb_lock);
ab1f90f9
JN		 2806
2807 intel_enable_dp(encoder);
89b667f8
JB		 2808}
2809
ecff4f3b 2810static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2811{
2812 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2813 struct drm_device *dev = encoder->base.dev;
2814 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2815 struct intel_crtc *intel_crtc =
2816 to_intel_crtc(encoder->base.crtc);
e4607fcf 2817 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2818 int pipe = intel_crtc->pipe;
89b667f8 2819
8ac33ed3
DV		 2820 intel_dp_prepare(encoder);
2821
89b667f8 2822 /* Program Tx lane resets to default */
a580516d 2823 mutex_lock(&dev_priv->sb_lock);
ab3c759a 2824 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2825 DPIO_PCS_TX_LANE2_RESET |
2826 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2827 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2828 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2829 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2830 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2831 DPIO_PCS_CLK_SOFT_RESET);
2832
2833 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2834 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2835 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2836 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
a580516d 2837 mutex_unlock(&dev_priv->sb_lock);
a4fc5ed6
KP		 2838}
2839
e4a1d846
CML		 2840static void chv_pre_enable_dp(struct intel_encoder *encoder)
2841{
2842 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2843 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2844 struct drm_device *dev = encoder->base.dev;
2845 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2846 struct intel_crtc *intel_crtc =
2847 to_intel_crtc(encoder->base.crtc);
2848 enum dpio_channel ch = vlv_dport_to_channel(dport);
2849 int pipe = intel_crtc->pipe;
2e523e98 2850 int data, i, stagger;
949c1d43 2851 u32 val;
e4a1d846 2852
a580516d 2853 mutex_lock(&dev_priv->sb_lock);
949c1d43 2854
570e2a74
VS		 2855 /* allow hardware to manage TX FIFO reset source */
2856 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2857 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2858 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2859
e0fce78f
VS		 2860 if (intel_crtc->config->lane_count > 2) {
2861 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2862 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2863 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2864 }
570e2a74 2865
949c1d43 2866 /* Program Tx lane latency optimal setting*/
e0fce78f 2867 for (i = 0; i < intel_crtc->config->lane_count; i++) {
e4a1d846 2868 /* Set the upar bit */
e0fce78f
VS		 2869 if (intel_crtc->config->lane_count == 1)
2870 data = 0x0;
2871 else
2872 data = (i == 1) ? 0x0 : 0x1;
e4a1d846
CML		 2873 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2874 data << DPIO_UPAR_SHIFT);
2875 }
2876
2877 /* Data lane stagger programming */
2e523e98
VS		 2878 if (intel_crtc->config->port_clock > 270000)
2879 stagger = 0x18;
2880 else if (intel_crtc->config->port_clock > 135000)
2881 stagger = 0xd;
2882 else if (intel_crtc->config->port_clock > 67500)
2883 stagger = 0x7;
2884 else if (intel_crtc->config->port_clock > 33750)
2885 stagger = 0x4;
2886 else
2887 stagger = 0x2;
2888
2889 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2890 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2891 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2892
e0fce78f
VS		 2893 if (intel_crtc->config->lane_count > 2) {
2894 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2895 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2896 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2897 }
2e523e98
VS		 2898
2899 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
2900 DPIO_LANESTAGGER_STRAP(stagger) |
2901 DPIO_LANESTAGGER_STRAP_OVRD |
2902 DPIO_TX1_STAGGER_MASK(0x1f) |
2903 DPIO_TX1_STAGGER_MULT(6) |
2904 DPIO_TX2_STAGGER_MULT(0));
2905
e0fce78f
VS		 2906 if (intel_crtc->config->lane_count > 2) {
2907 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
2908 DPIO_LANESTAGGER_STRAP(stagger) |
2909 DPIO_LANESTAGGER_STRAP_OVRD |
2910 DPIO_TX1_STAGGER_MASK(0x1f) |
2911 DPIO_TX1_STAGGER_MULT(7) |
2912 DPIO_TX2_STAGGER_MULT(5));
2913 }
e4a1d846 2914
a8f327fb
VS		 2915 /* Deassert data lane reset */
2916 chv_data_lane_soft_reset(encoder, false);
2917
a580516d 2918 mutex_unlock(&dev_priv->sb_lock);
e4a1d846 2919
e4a1d846 2920 intel_enable_dp(encoder);
b0b33846
VS		 2921
2922 /* Second common lane will stay alive on its own now */
2923 if (dport->release_cl2_override) {
2924 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
2925 dport->release_cl2_override = false;
2926 }
e4a1d846
CML		 2927}
2928
9197c88b
VS		 2929static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2930{
2931 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2932 struct drm_device *dev = encoder->base.dev;
2933 struct drm_i915_private *dev_priv = dev->dev_private;
2934 struct intel_crtc *intel_crtc =
2935 to_intel_crtc(encoder->base.crtc);
2936 enum dpio_channel ch = vlv_dport_to_channel(dport);
2937 enum pipe pipe = intel_crtc->pipe;
e0fce78f
VS		 2938 unsigned int lane_mask =
2939 intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
9197c88b
VS		 2940 u32 val;
2941
625695f8
VS		 2942 intel_dp_prepare(encoder);
2943
b0b33846
VS		 2944 /*
2945 * Must trick the second common lane into life.
2946 * Otherwise we can't even access the PLL.
2947 */
2948 if (ch == DPIO_CH0 && pipe == PIPE_B)
2949 dport->release_cl2_override =
2950 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
2951
e0fce78f
VS		 2952 chv_phy_powergate_lanes(encoder, true, lane_mask);
2953
a580516d 2954 mutex_lock(&dev_priv->sb_lock);
9197c88b 2955
a8f327fb
VS		 2956 /* Assert data lane reset */
2957 chv_data_lane_soft_reset(encoder, true);
2958
b9e5ac3c
VS		 2959 /* program left/right clock distribution */
2960 if (pipe != PIPE_B) {
2961 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2962 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2963 if (ch == DPIO_CH0)
2964 val |= CHV_BUFLEFTENA1_FORCE;
2965 if (ch == DPIO_CH1)
2966 val |= CHV_BUFRIGHTENA1_FORCE;
2967 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2968 } else {
2969 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2970 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2971 if (ch == DPIO_CH0)
2972 val |= CHV_BUFLEFTENA2_FORCE;
2973 if (ch == DPIO_CH1)
2974 val |= CHV_BUFRIGHTENA2_FORCE;
2975 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2976 }
2977
9197c88b
VS		 2978 /* program clock channel usage */
2979 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2980 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2981 if (pipe != PIPE_B)
2982 val &= ~CHV_PCS_USEDCLKCHANNEL;
2983 else
2984 val |= CHV_PCS_USEDCLKCHANNEL;
2985 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2986
e0fce78f
VS		 2987 if (intel_crtc->config->lane_count > 2) {
2988 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2989 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2990 if (pipe != PIPE_B)
2991 val &= ~CHV_PCS_USEDCLKCHANNEL;
2992 else
2993 val |= CHV_PCS_USEDCLKCHANNEL;
2994 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2995 }
9197c88b
VS		 2996
2997 /*
2998 * This a a bit weird since generally CL
2999 * matches the pipe, but here we need to
3000 * pick the CL based on the port.
3001 */
3002 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
3003 if (pipe != PIPE_B)
3004 val &= ~CHV_CMN_USEDCLKCHANNEL;
3005 else
3006 val |= CHV_CMN_USEDCLKCHANNEL;
3007 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
3008
a580516d 3009 mutex_unlock(&dev_priv->sb_lock);
9197c88b
VS		 3010}
3011
d6db995f
VS		 3012static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
3013{
3014 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3015 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
3016 u32 val;
3017
3018 mutex_lock(&dev_priv->sb_lock);
3019
3020 /* disable left/right clock distribution */
3021 if (pipe != PIPE_B) {
3022 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3023 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3024 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3025 } else {
3026 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3027 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3028 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3029 }
3030
3031 mutex_unlock(&dev_priv->sb_lock);
e0fce78f 3032
b0b33846
VS		 3033 /*
3034 * Leave the power down bit cleared for at least one
3035 * lane so that chv_powergate_phy_ch() will power
3036 * on something when the channel is otherwise unused.
3037 * When the port is off and the override is removed
3038 * the lanes power down anyway, so otherwise it doesn't
3039 * really matter what the state of power down bits is
3040 * after this.
3041 */
e0fce78f 3042 chv_phy_powergate_lanes(encoder, false, 0x0);
d6db995f
VS		 3043}
3044
a4fc5ed6 3045/*
df0c237d
JB		 3046 * Native read with retry for link status and receiver capability reads for
3047 * cases where the sink may still be asleep.
9d1a1031
JN		 3048 *
3049 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
3050 * supposed to retry 3 times per the spec.
a4fc5ed6 3051 */
9d1a1031
JN		 3052static ssize_t
3053intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
3054 void *buffer, size_t size)
a4fc5ed6 3055{
9d1a1031
JN		 3056 ssize_t ret;
3057 int i;
61da5fab 3058
f6a19066
VS		 3059 /*
3060 * Sometime we just get the same incorrect byte repeated
3061 * over the entire buffer. Doing just one throw away read
3062 * initially seems to "solve" it.
3063 */
3064 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
3065
61da5fab 3066 for (i = 0; i < 3; i++) {
9d1a1031
JN		 3067 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
3068 if (ret == size)
3069 return ret;
61da5fab
JB		 3070 msleep(1);
3071 }
a4fc5ed6 3072
9d1a1031 3073 return ret;
a4fc5ed6
KP		 3074}
3075
3076/*
3077 * Fetch AUX CH registers 0x202 - 0x207 which contain
3078 * link status information
3079 */
94223d04 3080bool
93f62dad 3081intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 3082{
9d1a1031
JN		 3083 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3084 DP_LANE0_1_STATUS,
3085 link_status,
3086 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 3087}
3088
1100244e 3089/* These are source-specific values. */
94223d04 3090uint8_t
1a2eb460 3091intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 3092{
30add22d 3093 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 3094 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 3095 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3096
9314726b
VK		 3097 if (IS_BROXTON(dev))
3098 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3099 else if (INTEL_INFO(dev)->gen >= 9) {
9e458034 3100 if (dev_priv->edp_low_vswing && port == PORT_A)
7ad14a29 3101 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 3102 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
7ad14a29 3103 } else if (IS_VALLEYVIEW(dev))
bd60018a 3104 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 3105 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 3106 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 3107 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 3108 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 3109 else
bd60018a 3110 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 3111}
3112
94223d04 3113uint8_t
1a2eb460
KP		 3114intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3115{
30add22d 3116 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 3117 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3118
5a9d1f1a
DL		 3119 if (INTEL_INFO(dev)->gen >= 9) {
3120 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3121 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3122 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3123 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3124 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3126 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 3127 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3128 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 3129 default:
3130 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3131 }
3132 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 3133 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3135 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3136 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3137 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3138 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3139 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3140 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 3141 default:
bd60018a 3142 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 3143 }
e2fa6fba
P		 3144 } else if (IS_VALLEYVIEW(dev)) {
3145 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3146 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3147 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3148 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3149 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3150 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3151 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3152 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 3153 default:
bd60018a 3154 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3155 }
bc7d38a4 3156 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 3157 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3158 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3159 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3160 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3161 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3162 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3163 default:
bd60018a 3164 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3165 }
3166 } else {
3167 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3168 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3169 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3170 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3171 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3172 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3173 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3174 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3175 default:
bd60018a 3176 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3177 }
a4fc5ed6
KP		 3178 }
3179}
3180
5829975c 3181static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba
P		 3182{
3183 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3184 struct drm_i915_private *dev_priv = dev->dev_private;
3185 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 3186 struct intel_crtc *intel_crtc =
3187 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 3188 unsigned long demph_reg_value, preemph_reg_value,
3189 uniqtranscale_reg_value;
3190 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 3191 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 3192 int pipe = intel_crtc->pipe;
e2fa6fba
P		 3193
3194 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3195 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3196 preemph_reg_value = 0x0004000;
3197 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3199 demph_reg_value = 0x2B405555;
3200 uniqtranscale_reg_value = 0x552AB83A;
3201 break;
bd60018a 3202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3203 demph_reg_value = 0x2B404040;
3204 uniqtranscale_reg_value = 0x5548B83A;
3205 break;
bd60018a 3206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3207 demph_reg_value = 0x2B245555;
3208 uniqtranscale_reg_value = 0x5560B83A;
3209 break;
bd60018a 3210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3211 demph_reg_value = 0x2B405555;
3212 uniqtranscale_reg_value = 0x5598DA3A;
3213 break;
3214 default:
3215 return 0;
3216 }
3217 break;
bd60018a 3218 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3219 preemph_reg_value = 0x0002000;
3220 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3221 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3222 demph_reg_value = 0x2B404040;
3223 uniqtranscale_reg_value = 0x5552B83A;
3224 break;
bd60018a 3225 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3226 demph_reg_value = 0x2B404848;
3227 uniqtranscale_reg_value = 0x5580B83A;
3228 break;
bd60018a 3229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3230 demph_reg_value = 0x2B404040;
3231 uniqtranscale_reg_value = 0x55ADDA3A;
3232 break;
3233 default:
3234 return 0;
3235 }
3236 break;
bd60018a 3237 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3238 preemph_reg_value = 0x0000000;
3239 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3240 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3241 demph_reg_value = 0x2B305555;
3242 uniqtranscale_reg_value = 0x5570B83A;
3243 break;
bd60018a 3244 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3245 demph_reg_value = 0x2B2B4040;
3246 uniqtranscale_reg_value = 0x55ADDA3A;
3247 break;
3248 default:
3249 return 0;
3250 }
3251 break;
bd60018a 3252 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3253 preemph_reg_value = 0x0006000;
3254 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3255 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3256 demph_reg_value = 0x1B405555;
3257 uniqtranscale_reg_value = 0x55ADDA3A;
3258 break;
3259 default:
3260 return 0;
3261 }
3262 break;
3263 default:
3264 return 0;
3265 }
3266
a580516d 3267 mutex_lock(&dev_priv->sb_lock);
ab3c759a
CML		 3268 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3269 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3270 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3271 uniqtranscale_reg_value);
ab3c759a
CML		 3272 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3273 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3274 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3275 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
a580516d 3276 mutex_unlock(&dev_priv->sb_lock);
e2fa6fba
P		 3277
3278 return 0;
3279}
3280
67fa24b4
VS		 3281static bool chv_need_uniq_trans_scale(uint8_t train_set)
3282{
3283 return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
3284 (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3285}
3286
5829975c 3287static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846
CML		 3288{
3289 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3290 struct drm_i915_private *dev_priv = dev->dev_private;
3291 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3292 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3293 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3294 uint8_t train_set = intel_dp->train_set[0];
3295 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3296 enum pipe pipe = intel_crtc->pipe;
3297 int i;
e4a1d846
CML		 3298
3299 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3300 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3301 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3302 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3303 deemph_reg_value = 128;
3304 margin_reg_value = 52;
3305 break;
bd60018a 3306 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3307 deemph_reg_value = 128;
3308 margin_reg_value = 77;
3309 break;
bd60018a 3310 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3311 deemph_reg_value = 128;
3312 margin_reg_value = 102;
3313 break;
bd60018a 3314 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3315 deemph_reg_value = 128;
3316 margin_reg_value = 154;
3317 /* FIXME extra to set for 1200 */
3318 break;
3319 default:
3320 return 0;
3321 }
3322 break;
bd60018a 3323 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3324 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3326 deemph_reg_value = 85;
3327 margin_reg_value = 78;
3328 break;
bd60018a 3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3330 deemph_reg_value = 85;
3331 margin_reg_value = 116;
3332 break;
bd60018a 3333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3334 deemph_reg_value = 85;
3335 margin_reg_value = 154;
3336 break;
3337 default:
3338 return 0;
3339 }
3340 break;
bd60018a 3341 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3342 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3343 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3344 deemph_reg_value = 64;
3345 margin_reg_value = 104;
3346 break;
bd60018a 3347 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3348 deemph_reg_value = 64;
3349 margin_reg_value = 154;
3350 break;
3351 default:
3352 return 0;
3353 }
3354 break;
bd60018a 3355 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3356 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3357 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3358 deemph_reg_value = 43;
3359 margin_reg_value = 154;
3360 break;
3361 default:
3362 return 0;
3363 }
3364 break;
3365 default:
3366 return 0;
3367 }
3368
a580516d 3369 mutex_lock(&dev_priv->sb_lock);
e4a1d846
CML		 3370
3371 /* Clear calc init */
1966e59e
VS		 3372 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3373 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3374 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3375 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3376 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3377
e0fce78f
VS		 3378 if (intel_crtc->config->lane_count > 2) {
3379 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3380 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3381 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3382 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3383 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3384 }
e4a1d846 3385
a02ef3c7
VS		 3386 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3387 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3388 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3389 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3390
e0fce78f
VS		 3391 if (intel_crtc->config->lane_count > 2) {
3392 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3393 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3394 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3395 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3396 }
a02ef3c7 3397
e4a1d846 3398 /* Program swing deemph */
e0fce78f 3399 for (i = 0; i < intel_crtc->config->lane_count; i++) {
f72df8db
VS		 3400 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3401 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3402 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3403 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3404 }
e4a1d846
CML		 3405
3406 /* Program swing margin */
e0fce78f 3407 for (i = 0; i < intel_crtc->config->lane_count; i++) {
f72df8db 3408 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
67fa24b4 3409
1fb44505
VS		 3410 val &= ~DPIO_SWING_MARGIN000_MASK;
3411 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
67fa24b4
VS		 3412
3413 /*
3414 * Supposedly this value shouldn't matter when unique transition
3415 * scale is disabled, but in fact it does matter. Let's just
3416 * always program the same value and hope it's OK.
3417 */
3418 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3419 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
3420
f72df8db
VS		 3421 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3422 }
e4a1d846 3423
67fa24b4
VS		 3424 /*
3425 * The document said it needs to set bit 27 for ch0 and bit 26
3426 * for ch1. Might be a typo in the doc.
3427 * For now, for this unique transition scale selection, set bit
3428 * 27 for ch0 and ch1.
3429 */
e0fce78f 3430 for (i = 0; i < intel_crtc->config->lane_count; i++) {
f72df8db 3431 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
67fa24b4 3432 if (chv_need_uniq_trans_scale(train_set))
f72df8db 3433 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
67fa24b4
VS		 3434 else
3435 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3436 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
e4a1d846
CML		 3437 }
3438
3439 /* Start swing calculation */
1966e59e
VS		 3440 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3441 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3442 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3443
e0fce78f
VS		 3444 if (intel_crtc->config->lane_count > 2) {
3445 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3446 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3447 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3448 }
e4a1d846 3449
a580516d 3450 mutex_unlock(&dev_priv->sb_lock);
e4a1d846
CML		 3451
3452 return 0;
3453}
3454
a4fc5ed6 3455static uint32_t
5829975c 3456gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3457{
3cf2efb1 3458 uint32_t signal_levels = 0;
a4fc5ed6 3459
3cf2efb1 3460 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3461 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3462 default:
3463 signal_levels |= DP_VOLTAGE_0_4;
3464 break;
bd60018a 3465 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3466 signal_levels |= DP_VOLTAGE_0_6;
3467 break;
bd60018a 3468 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3469 signal_levels |= DP_VOLTAGE_0_8;
3470 break;
bd60018a 3471 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3472 signal_levels |= DP_VOLTAGE_1_2;
3473 break;
3474 }
3cf2efb1 3475 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3476 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3477 default:
3478 signal_levels |= DP_PRE_EMPHASIS_0;
3479 break;
bd60018a 3480 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3481 signal_levels |= DP_PRE_EMPHASIS_3_5;
3482 break;
bd60018a 3483 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3484 signal_levels |= DP_PRE_EMPHASIS_6;
3485 break;
bd60018a 3486 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3487 signal_levels |= DP_PRE_EMPHASIS_9_5;
3488 break;
3489 }
3490 return signal_levels;
3491}
3492
e3421a18
ZW		 3493/* Gen6's DP voltage swing and pre-emphasis control */
3494static uint32_t
5829975c 3495gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3496{
3c5a62b5
YL		 3497 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3498 DP_TRAIN_PRE_EMPHASIS_MASK);
3499 switch (signal_levels) {
bd60018a
SJ		 3500 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3501 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3502 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3503 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3504 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3505 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3506 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3507 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3508 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3509 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3510 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3511 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3512 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3513 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3514 default:
3c5a62b5
YL		 3515 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3516 "0x%x\n", signal_levels);
3517 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3518 }
3519}
3520
1a2eb460
KP		 3521/* Gen7's DP voltage swing and pre-emphasis control */
3522static uint32_t
5829975c 3523gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3524{
3525 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3526 DP_TRAIN_PRE_EMPHASIS_MASK);
3527 switch (signal_levels) {
bd60018a 3528 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3529 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3530 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3531 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3532 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3533 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3534
bd60018a 3535 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3536 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3537 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3538 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3539
bd60018a 3540 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3541 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3542 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3543 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3544
3545 default:
3546 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3547 "0x%x\n", signal_levels);
3548 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3549 }
3550}
3551
94223d04 3552void
f4eb692e 3553intel_dp_set_signal_levels(struct intel_dp *intel_dp)
f0a3424e
PZ		 3554{
3555 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3556 enum port port = intel_dig_port->port;
f0a3424e 3557 struct drm_device *dev = intel_dig_port->base.base.dev;
b905a915 3558 struct drm_i915_private *dev_priv = to_i915(dev);
f8896f5d 3559 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3560 uint8_t train_set = intel_dp->train_set[0];
3561
f8896f5d
DW		 3562 if (HAS_DDI(dev)) {
3563 signal_levels = ddi_signal_levels(intel_dp);
3564
3565 if (IS_BROXTON(dev))
3566 signal_levels = 0;
3567 else
3568 mask = DDI_BUF_EMP_MASK;
e4a1d846 3569 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3570 signal_levels = chv_signal_levels(intel_dp);
e2fa6fba 3571 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3572 signal_levels = vlv_signal_levels(intel_dp);
bc7d38a4 3573 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3574 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3575 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3576 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3577 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3578 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3579 } else {
5829975c 3580 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3581 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3582 }
3583
96fb9f9b
VK		 3584 if (mask)
3585 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3586
3587 DRM_DEBUG_KMS("Using vswing level %d\n",
3588 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3589 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3590 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3591 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e 3592
f4eb692e 3593 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
b905a915
ACO		 3594
3595 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3596 POSTING_READ(intel_dp->output_reg);
f0a3424e
PZ		 3597}
3598
94223d04 3599void
e9c176d5
ACO		 3600intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3601 uint8_t dp_train_pat)
a4fc5ed6 3602{
174edf1f 3603 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3604 struct drm_i915_private *dev_priv =
3605 to_i915(intel_dig_port->base.base.dev);
a4fc5ed6 3606
f4eb692e 3607 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
47ea7542 3608
f4eb692e 3609 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
ea5b213a 3610 POSTING_READ(intel_dp->output_reg);
e9c176d5
ACO		 3611}
3612
94223d04 3613void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3ab9c637
ID		 3614{
3615 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3616 struct drm_device *dev = intel_dig_port->base.base.dev;
3617 struct drm_i915_private *dev_priv = dev->dev_private;
3618 enum port port = intel_dig_port->port;
3619 uint32_t val;
3620
3621 if (!HAS_DDI(dev))
3622 return;
3623
3624 val = I915_READ(DP_TP_CTL(port));
3625 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3626 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3627 I915_WRITE(DP_TP_CTL(port), val);
3628
3629 /*
3630 * On PORT_A we can have only eDP in SST mode. There the only reason
3631 * we need to set idle transmission mode is to work around a HW issue
3632 * where we enable the pipe while not in idle link-training mode.
3633 * In this case there is requirement to wait for a minimum number of
3634 * idle patterns to be sent.
3635 */
3636 if (port == PORT_A)
3637 return;
3638
3639 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3640 1))
3641 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3642}
3643
a4fc5ed6 3644static void
ea5b213a 3645intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3646{
da63a9f2 3647 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3648 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3649 enum port port = intel_dig_port->port;
da63a9f2 3650 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3651 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3652 uint32_t DP = intel_dp->DP;
a4fc5ed6 3653
bc76e320 3654 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3655 return;
3656
0c33d8d7 3657 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3658 return;
3659
28c97730 3660 DRM_DEBUG_KMS("\n");
32f9d658 3661
39e5fa88
VS		 3662 if ((IS_GEN7(dev) && port == PORT_A) ||
3663 (HAS_PCH_CPT(dev) && port != PORT_A)) {
e3421a18 3664 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3665 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3666 } else {
aad3d14d
VS		 3667 if (IS_CHERRYVIEW(dev))
3668 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3669 else
3670 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3671 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3672 }
1612c8bd 3673 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3674 POSTING_READ(intel_dp->output_reg);
5eb08b69 3675
1612c8bd
VS		 3676 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3677 I915_WRITE(intel_dp->output_reg, DP);
3678 POSTING_READ(intel_dp->output_reg);
3679
3680 /*
3681 * HW workaround for IBX, we need to move the port
3682 * to transcoder A after disabling it to allow the
3683 * matching HDMI port to be enabled on transcoder A.
3684 */
3685 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
0c241d5b
VS		 3686 /*
3687 * We get CPU/PCH FIFO underruns on the other pipe when
3688 * doing the workaround. Sweep them under the rug.
3689 */
3690 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3691 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3692
1612c8bd
VS		 3693 /* always enable with pattern 1 (as per spec) */
3694 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3695 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3696 I915_WRITE(intel_dp->output_reg, DP);
3697 POSTING_READ(intel_dp->output_reg);
3698
3699 DP &= ~DP_PORT_EN;
5bddd17f 3700 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3701 POSTING_READ(intel_dp->output_reg);
0c241d5b
VS		 3702
3703 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3704 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3705 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5bddd17f
EA		 3706 }
3707
f01eca2e 3708 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3709}
3710
26d61aad
KP		 3711static bool
3712intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3713{
a031d709
RV		 3714 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3715 struct drm_device *dev = dig_port->base.base.dev;
3716 struct drm_i915_private *dev_priv = dev->dev_private;
fc0f8e25 3717 uint8_t rev;
a031d709 3718
9d1a1031
JN		 3719 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3720 sizeof(intel_dp->dpcd)) < 0)
edb39244 3721 return false; /* aux transfer failed */
92fd8fd1 3722
a8e98153 3723 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3724
edb39244
AJ		 3725 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3726 return false; /* DPCD not present */
3727
2293bb5c
SK		 3728 /* Check if the panel supports PSR */
3729 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3730 if (is_edp(intel_dp)) {
9d1a1031
JN		 3731 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3732 intel_dp->psr_dpcd,
3733 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3734 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3735 dev_priv->psr.sink_support = true;
50003939 3736 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3737 }
474d1ec4
SJ		 3738
3739 if (INTEL_INFO(dev)->gen >= 9 &&
3740 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3741 uint8_t frame_sync_cap;
3742
3743 dev_priv->psr.sink_support = true;
3744 intel_dp_dpcd_read_wake(&intel_dp->aux,
3745 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3746 &frame_sync_cap, 1);
3747 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3748 /* PSR2 needs frame sync as well */
3749 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3750 DRM_DEBUG_KMS("PSR2 %s on sink",
3751 dev_priv->psr.psr2_support ? "supported" : "not supported");
3752 }
50003939
JN		 3753 }
3754
bc5133d5 3755 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
e588fa18 3756 yesno(intel_dp_source_supports_hbr2(intel_dp)),
742f491d 3757 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
06ea66b6 3758
fc0f8e25
SJ		 3759 /* Intermediate frequency support */
3760 if (is_edp(intel_dp) &&
3761 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3762 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3763 (rev >= 0x03)) { /* eDp v1.4 or higher */
94ca719e 3764 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3765 int i;
3766
fc0f8e25
SJ		 3767 intel_dp_dpcd_read_wake(&intel_dp->aux,
3768 DP_SUPPORTED_LINK_RATES,
94ca719e
VS		 3769 sink_rates,
3770 sizeof(sink_rates));
ea2d8a42 3771
94ca719e
VS		 3772 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3773 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3774
3775 if (val == 0)
3776 break;
3777
af77b974
SJ		 3778 /* Value read is in kHz while drm clock is saved in deca-kHz */
3779 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3780 }
94ca719e 3781 intel_dp->num_sink_rates = i;
fc0f8e25 3782 }
0336400e
VS		 3783
3784 intel_dp_print_rates(intel_dp);
3785
edb39244
AJ		 3786 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3787 DP_DWN_STRM_PORT_PRESENT))
3788 return true; /* native DP sink */
3789
3790 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3791 return true; /* no per-port downstream info */
3792
9d1a1031
JN		 3793 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3794 intel_dp->downstream_ports,
3795 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3796 return false; /* downstream port status fetch failed */
3797
3798 return true;
92fd8fd1
KP		 3799}
3800
0d198328
AJ		 3801static void
3802intel_dp_probe_oui(struct intel_dp *intel_dp)
3803{
3804 u8 buf[3];
3805
3806 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3807 return;
3808
9d1a1031 3809 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3810 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3811 buf[0], buf[1], buf[2]);
3812
9d1a1031 3813 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3814 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3815 buf[0], buf[1], buf[2]);
3816}
3817
0e32b39c
DA		 3818static bool
3819intel_dp_probe_mst(struct intel_dp *intel_dp)
3820{
3821 u8 buf[1];
3822
3823 if (!intel_dp->can_mst)
3824 return false;
3825
3826 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3827 return false;
3828
0e32b39c
DA		 3829 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3830 if (buf[0] & DP_MST_CAP) {
3831 DRM_DEBUG_KMS("Sink is MST capable\n");
3832 intel_dp->is_mst = true;
3833 } else {
3834 DRM_DEBUG_KMS("Sink is not MST capable\n");
3835 intel_dp->is_mst = false;
3836 }
3837 }
0e32b39c
DA		 3838
3839 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3840 return intel_dp->is_mst;
3841}
3842
e5a1cab5 3843static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
d2e216d0 3844{
082dcc7c
RV		 3845 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3846 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
ad9dc91b 3847 u8 buf;
e5a1cab5 3848 int ret = 0;
d2e216d0 3849
082dcc7c
RV		 3850 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3851 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3852 ret = -EIO;
3853 goto out;
4373f0f2
PZ		 3854 }
3855
082dcc7c 3856 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
e5a1cab5 3857 buf & ~DP_TEST_SINK_START) < 0) {
082dcc7c 3858 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3859 ret = -EIO;
3860 goto out;
3861 }
d2e216d0 3862
621d4c76 3863 intel_dp->sink_crc.started = false;
e5a1cab5 3864 out:
082dcc7c 3865 hsw_enable_ips(intel_crtc);
e5a1cab5 3866 return ret;
082dcc7c
RV		 3867}
3868
3869static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3870{
3871 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3872 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3873 u8 buf;
e5a1cab5
RV		 3874 int ret;
3875
621d4c76 3876 if (intel_dp->sink_crc.started) {
e5a1cab5
RV		 3877 ret = intel_dp_sink_crc_stop(intel_dp);
3878 if (ret)
3879 return ret;
3880 }
082dcc7c
RV		 3881
3882 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3883 return -EIO;
3884
3885 if (!(buf & DP_TEST_CRC_SUPPORTED))
3886 return -ENOTTY;
3887
621d4c76
RV		 3888 intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;
3889
082dcc7c
RV		 3890 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3891 return -EIO;
3892
3893 hsw_disable_ips(intel_crtc);
1dda5f93 3894
9d1a1031 3895 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
082dcc7c
RV		 3896 buf | DP_TEST_SINK_START) < 0) {
3897 hsw_enable_ips(intel_crtc);
3898 return -EIO;
4373f0f2
PZ		 3899 }
3900
621d4c76 3901 intel_dp->sink_crc.started = true;
082dcc7c
RV		 3902 return 0;
3903}
3904
3905int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3906{
3907 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3908 struct drm_device *dev = dig_port->base.base.dev;
3909 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3910 u8 buf;
621d4c76 3911 int count, ret;
082dcc7c 3912 int attempts = 6;
aabc95dc 3913 bool old_equal_new;
082dcc7c
RV		 3914
3915 ret = intel_dp_sink_crc_start(intel_dp);
3916 if (ret)
3917 return ret;
3918
ad9dc91b 3919 do {
621d4c76
RV		 3920 intel_wait_for_vblank(dev, intel_crtc->pipe);
3921
1dda5f93 3922 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 3923 DP_TEST_SINK_MISC, &buf) < 0) {
3924 ret = -EIO;
afe0d67e 3925 goto stop;
4373f0f2 3926 }
621d4c76 3927 count = buf & DP_TEST_COUNT_MASK;
aabc95dc 3928
621d4c76
RV		 3929 /*
3930 * Count might be reset during the loop. In this case
3931 * last known count needs to be reset as well.
3932 */
3933 if (count == 0)
3934 intel_dp->sink_crc.last_count = 0;
3935
3936 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3937 ret = -EIO;
3938 goto stop;
3939 }
aabc95dc
RV		 3940
3941 old_equal_new = (count == intel_dp->sink_crc.last_count &&
3942 !memcmp(intel_dp->sink_crc.last_crc, crc,
3943 6 * sizeof(u8)));
3944
3945 } while (--attempts && (count == 0 || old_equal_new));
621d4c76
RV		 3946
3947 intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;
3948 memcpy(intel_dp->sink_crc.last_crc, crc, 6 * sizeof(u8));
ad9dc91b
RV		 3949
3950 if (attempts == 0) {
aabc95dc
RV		 3951 if (old_equal_new) {
3952 DRM_DEBUG_KMS("Unreliable Sink CRC counter: Current returned CRC is identical to the previous one\n");
3953 } else {
3954 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3955 ret = -ETIMEDOUT;
3956 goto stop;
3957 }
ad9dc91b 3958 }
d2e216d0 3959
afe0d67e 3960stop:
082dcc7c 3961 intel_dp_sink_crc_stop(intel_dp);
4373f0f2 3962 return ret;
d2e216d0
RV		 3963}
3964
a60f0e38
JB		 3965static bool
3966intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3967{
9d1a1031
JN		 3968 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3969 DP_DEVICE_SERVICE_IRQ_VECTOR,
3970 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3971}
3972
0e32b39c
DA		 3973static bool
3974intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3975{
3976 int ret;
3977
3978 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3979 DP_SINK_COUNT_ESI,
3980 sink_irq_vector, 14);
3981 if (ret != 14)
3982 return false;
3983
3984 return true;
3985}
3986
c5d5ab7a
TP		 3987static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3988{
3989 uint8_t test_result = DP_TEST_ACK;
3990 return test_result;
3991}
3992
3993static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3994{
3995 uint8_t test_result = DP_TEST_NAK;
3996 return test_result;
3997}
3998
3999static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 4000{
c5d5ab7a 4001 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 4002 struct intel_connector *intel_connector = intel_dp->attached_connector;
4003 struct drm_connector *connector = &intel_connector->base;
4004
4005 if (intel_connector->detect_edid == NULL ||
ac6f2e29 4006 connector->edid_corrupt ||
559be30c
TP		 4007 intel_dp->aux.i2c_defer_count > 6) {
4008 /* Check EDID read for NACKs, DEFERs and corruption
4009 * (DP CTS 1.2 Core r1.1)
4010 * 4.2.2.4 : Failed EDID read, I2C_NAK
4011 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4012 * 4.2.2.6 : EDID corruption detected
4013 * Use failsafe mode for all cases
4014 */
4015 if (intel_dp->aux.i2c_nack_count > 0 ||
4016 intel_dp->aux.i2c_defer_count > 0)
4017 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4018 intel_dp->aux.i2c_nack_count,
4019 intel_dp->aux.i2c_defer_count);
4020 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4021 } else {
f79b468e
TS		 4022 struct edid *block = intel_connector->detect_edid;
4023
4024 /* We have to write the checksum
4025 * of the last block read
4026 */
4027 block += intel_connector->detect_edid->extensions;
4028
559be30c
TP		 4029 if (!drm_dp_dpcd_write(&intel_dp->aux,
4030 DP_TEST_EDID_CHECKSUM,
f79b468e 4031 &block->checksum,
5a1cc655 4032 1))
559be30c
TP		 4033 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4034
4035 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4036 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4037 }
4038
4039 /* Set test active flag here so userspace doesn't interrupt things */
4040 intel_dp->compliance_test_active = 1;
4041
c5d5ab7a
TP		 4042 return test_result;
4043}
4044
4045static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 4046{
c5d5ab7a
TP		 4047 uint8_t test_result = DP_TEST_NAK;
4048 return test_result;
4049}
4050
4051static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4052{
4053 uint8_t response = DP_TEST_NAK;
4054 uint8_t rxdata = 0;
4055 int status = 0;
4056
559be30c 4057 intel_dp->compliance_test_active = 0;
c5d5ab7a 4058 intel_dp->compliance_test_type = 0;
559be30c
TP		 4059 intel_dp->compliance_test_data = 0;
4060
c5d5ab7a
TP		 4061 intel_dp->aux.i2c_nack_count = 0;
4062 intel_dp->aux.i2c_defer_count = 0;
4063
4064 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4065 if (status <= 0) {
4066 DRM_DEBUG_KMS("Could not read test request from sink\n");
4067 goto update_status;
4068 }
4069
4070 switch (rxdata) {
4071 case DP_TEST_LINK_TRAINING:
4072 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4073 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4074 response = intel_dp_autotest_link_training(intel_dp);
4075 break;
4076 case DP_TEST_LINK_VIDEO_PATTERN:
4077 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4078 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4079 response = intel_dp_autotest_video_pattern(intel_dp);
4080 break;
4081 case DP_TEST_LINK_EDID_READ:
4082 DRM_DEBUG_KMS("EDID test requested\n");
4083 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4084 response = intel_dp_autotest_edid(intel_dp);
4085 break;
4086 case DP_TEST_LINK_PHY_TEST_PATTERN:
4087 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4088 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4089 response = intel_dp_autotest_phy_pattern(intel_dp);
4090 break;
4091 default:
4092 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4093 break;
4094 }
4095
4096update_status:
4097 status = drm_dp_dpcd_write(&intel_dp->aux,
4098 DP_TEST_RESPONSE,
4099 &response, 1);
4100 if (status <= 0)
4101 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 4102}
4103
0e32b39c
DA		 4104static int
4105intel_dp_check_mst_status(struct intel_dp *intel_dp)
4106{
4107 bool bret;
4108
4109 if (intel_dp->is_mst) {
4110 u8 esi[16] = { 0 };
4111 int ret = 0;
4112 int retry;
4113 bool handled;
4114 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4115go_again:
4116 if (bret == true) {
4117
4118 /* check link status - esi[10] = 0x200c */
90a6b7b0 4119 if (intel_dp->active_mst_links &&
901c2daf 4120 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
0e32b39c
DA		 4121 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4122 intel_dp_start_link_train(intel_dp);
0e32b39c
DA		 4123 intel_dp_stop_link_train(intel_dp);
4124 }
4125
6f34cc39 4126 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 4127 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4128
4129 if (handled) {
4130 for (retry = 0; retry < 3; retry++) {
4131 int wret;
4132 wret = drm_dp_dpcd_write(&intel_dp->aux,
4133 DP_SINK_COUNT_ESI+1,
4134 &esi[1], 3);
4135 if (wret == 3) {
4136 break;
4137 }
4138 }
4139
4140 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4141 if (bret == true) {
6f34cc39 4142 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 4143 goto go_again;
4144 }
4145 } else
4146 ret = 0;
4147
4148 return ret;
4149 } else {
4150 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4151 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4152 intel_dp->is_mst = false;
4153 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4154 /* send a hotplug event */
4155 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4156 }
4157 }
4158 return -EINVAL;
4159}
4160
a4fc5ed6
KP		 4161/*
4162 * According to DP spec
4163 * 5.1.2:
4164 * 1. Read DPCD
4165 * 2. Configure link according to Receiver Capabilities
4166 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4167 * 4. Check link status on receipt of hot-plug interrupt
4168 */
a5146200 4169static void
ea5b213a 4170intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4171{
5b215bcf 4172 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4173 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4174 u8 sink_irq_vector;
93f62dad 4175 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4176
5b215bcf
DA		 4177 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4178
e02f9a06 4179 if (!intel_encoder->base.crtc)
a4fc5ed6
KP		 4180 return;
4181
1a125d8a
ID		 4182 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4183 return;
4184
92fd8fd1 4185 /* Try to read receiver status if the link appears to be up */
93f62dad 4186 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4187 return;
4188 }
4189
92fd8fd1 4190 /* Now read the DPCD to see if it's actually running */
26d61aad 4191 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4192 return;
4193 }
4194
a60f0e38
JB		 4195 /* Try to read the source of the interrupt */
4196 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4197 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4198 /* Clear interrupt source */
9d1a1031
JN		 4199 drm_dp_dpcd_writeb(&intel_dp->aux,
4200 DP_DEVICE_SERVICE_IRQ_VECTOR,
4201 sink_irq_vector);
a60f0e38
JB		 4202
4203 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 4204 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 4205 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4206 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4207 }
4208
901c2daf 4209 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4210 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4211 intel_encoder->base.name);
33a34e4e 4212 intel_dp_start_link_train(intel_dp);
3ab9c637 4213 intel_dp_stop_link_train(intel_dp);
33a34e4e 4214 }
a4fc5ed6 4215}
a4fc5ed6 4216
caf9ab24 4217/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4218static enum drm_connector_status
26d61aad 4219intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4220{
caf9ab24 4221 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4222 uint8_t type;
4223
4224 if (!intel_dp_get_dpcd(intel_dp))
4225 return connector_status_disconnected;
4226
4227 /* if there's no downstream port, we're done */
4228 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4229 return connector_status_connected;
caf9ab24
AJ		 4230
4231 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4232 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4233 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4234 uint8_t reg;
9d1a1031
JN		 4235
4236 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4237 &reg, 1) < 0)
caf9ab24 4238 return connector_status_unknown;
9d1a1031 4239
23235177
AJ		 4240 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4241 : connector_status_disconnected;
caf9ab24
AJ		 4242 }
4243
4244 /* If no HPD, poke DDC gently */
0b99836f 4245 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4246 return connector_status_connected;
caf9ab24
AJ		 4247
4248 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4249 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4250 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4251 if (type == DP_DS_PORT_TYPE_VGA ||
4252 type == DP_DS_PORT_TYPE_NON_EDID)
4253 return connector_status_unknown;
4254 } else {
4255 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4256 DP_DWN_STRM_PORT_TYPE_MASK;
4257 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4258 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4259 return connector_status_unknown;
4260 }
caf9ab24
AJ		 4261
4262 /* Anything else is out of spec, warn and ignore */
4263 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4264 return connector_status_disconnected;
71ba9000
AJ		 4265}
4266
d410b56d
CW		 4267static enum drm_connector_status
4268edp_detect(struct intel_dp *intel_dp)
4269{
4270 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4271 enum drm_connector_status status;
4272
4273 status = intel_panel_detect(dev);
4274 if (status == connector_status_unknown)
4275 status = connector_status_connected;
4276
4277 return status;
4278}
4279
b93433cc
JN		 4280static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4281 struct intel_digital_port *port)
5eb08b69 4282{
b93433cc 4283 u32 bit;
01cb9ea6 4284
0df53b77
JN		 4285 switch (port->port) {
4286 case PORT_A:
4287 return true;
4288 case PORT_B:
4289 bit = SDE_PORTB_HOTPLUG;
4290 break;
4291 case PORT_C:
4292 bit = SDE_PORTC_HOTPLUG;
4293 break;
4294 case PORT_D:
4295 bit = SDE_PORTD_HOTPLUG;
4296 break;
4297 default:
4298 MISSING_CASE(port->port);
4299 return false;
4300 }
4301
4302 return I915_READ(SDEISR) & bit;
4303}
4304
4305static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4306 struct intel_digital_port *port)
4307{
4308 u32 bit;
4309
4310 switch (port->port) {
4311 case PORT_A:
4312 return true;
4313 case PORT_B:
4314 bit = SDE_PORTB_HOTPLUG_CPT;
4315 break;
4316 case PORT_C:
4317 bit = SDE_PORTC_HOTPLUG_CPT;
4318 break;
4319 case PORT_D:
4320 bit = SDE_PORTD_HOTPLUG_CPT;
4321 break;
a78695d3
JN		 4322 case PORT_E:
4323 bit = SDE_PORTE_HOTPLUG_SPT;
4324 break;
0df53b77
JN		 4325 default:
4326 MISSING_CASE(port->port);
4327 return false;
b93433cc 4328 }
1b469639 4329
b93433cc 4330 return I915_READ(SDEISR) & bit;
5eb08b69
ZW		 4331}
4332
7e66bcf2 4333static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
1d245987 4334 struct intel_digital_port *port)
a4fc5ed6 4335{
9642c81c 4336 u32 bit;
5eb08b69 4337
9642c81c
JN		 4338 switch (port->port) {
4339 case PORT_B:
4340 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4341 break;
4342 case PORT_C:
4343 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4344 break;
4345 case PORT_D:
4346 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4347 break;
4348 default:
4349 MISSING_CASE(port->port);
4350 return false;
4351 }
4352
4353 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4354}
4355
4356static bool vlv_digital_port_connected(struct drm_i915_private *dev_priv,
4357 struct intel_digital_port *port)
4358{
4359 u32 bit;
4360
4361 switch (port->port) {
4362 case PORT_B:
4363 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4364 break;
4365 case PORT_C:
4366 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4367 break;
4368 case PORT_D:
4369 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4370 break;
4371 default:
4372 MISSING_CASE(port->port);
4373 return false;
a4fc5ed6
KP		 4374 }
4375
1d245987 4376 return I915_READ(PORT_HOTPLUG_STAT) & bit;
2a592bec
DA		 4377}
4378
e464bfde 4379static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
e2ec35a5 4380 struct intel_digital_port *intel_dig_port)
e464bfde 4381{
e2ec35a5
SJ		 4382 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4383 enum port port;
e464bfde
JN		 4384 u32 bit;
4385
e2ec35a5
SJ		 4386 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4387 switch (port) {
e464bfde
JN		 4388 case PORT_A:
4389 bit = BXT_DE_PORT_HP_DDIA;
4390 break;
4391 case PORT_B:
4392 bit = BXT_DE_PORT_HP_DDIB;
4393 break;
4394 case PORT_C:
4395 bit = BXT_DE_PORT_HP_DDIC;
4396 break;
4397 default:
e2ec35a5 4398 MISSING_CASE(port);
e464bfde
JN		 4399 return false;
4400 }
4401
4402 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4403}
4404
7e66bcf2
JN		 4405/*
4406 * intel_digital_port_connected - is the specified port connected?
4407 * @dev_priv: i915 private structure
4408 * @port: the port to test
4409 *
4410 * Return %true if @port is connected, %false otherwise.
4411 */
237ed86c 4412bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
7e66bcf2
JN		 4413 struct intel_digital_port *port)
4414{
0df53b77 4415 if (HAS_PCH_IBX(dev_priv))
7e66bcf2 4416 return ibx_digital_port_connected(dev_priv, port);
0df53b77
JN		 4417 if (HAS_PCH_SPLIT(dev_priv))
4418 return cpt_digital_port_connected(dev_priv, port);
e464bfde
JN		 4419 else if (IS_BROXTON(dev_priv))
4420 return bxt_digital_port_connected(dev_priv, port);
9642c81c
JN		 4421 else if (IS_VALLEYVIEW(dev_priv))
4422 return vlv_digital_port_connected(dev_priv, port);
7e66bcf2
JN		 4423 else
4424 return g4x_digital_port_connected(dev_priv, port);
4425}
4426
b93433cc
JN		 4427static enum drm_connector_status
4428ironlake_dp_detect(struct intel_dp *intel_dp)
4429{
4430 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4431 struct drm_i915_private *dev_priv = dev->dev_private;
4432 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4433
7e66bcf2 4434 if (!intel_digital_port_connected(dev_priv, intel_dig_port))
b93433cc
JN		 4435 return connector_status_disconnected;
4436
4437 return intel_dp_detect_dpcd(intel_dp);
4438}
4439
2a592bec
DA		 4440static enum drm_connector_status
4441g4x_dp_detect(struct intel_dp *intel_dp)
4442{
4443 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4444 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2a592bec
DA		 4445
4446 /* Can't disconnect eDP, but you can close the lid... */
4447 if (is_edp(intel_dp)) {
4448 enum drm_connector_status status;
4449
4450 status = intel_panel_detect(dev);
4451 if (status == connector_status_unknown)
4452 status = connector_status_connected;
4453 return status;
4454 }
4455
7e66bcf2 4456 if (!intel_digital_port_connected(dev->dev_private, intel_dig_port))
a4fc5ed6
KP		 4457 return connector_status_disconnected;
4458
26d61aad 4459 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4460}
4461
8c241fef 4462static struct edid *
beb60608 4463intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4464{
beb60608 4465 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4466
9cd300e0
JN		 4467 /* use cached edid if we have one */
4468 if (intel_connector->edid) {
9cd300e0
JN		 4469 /* invalid edid */
4470 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4471 return NULL;
4472
55e9edeb 4473 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4474 } else
4475 return drm_get_edid(&intel_connector->base,
4476 &intel_dp->aux.ddc);
4477}
8c241fef 4478
beb60608
CW		 4479static void
4480intel_dp_set_edid(struct intel_dp *intel_dp)
4481{
4482 struct intel_connector *intel_connector = intel_dp->attached_connector;
4483 struct edid *edid;
8c241fef 4484
beb60608
CW		 4485 edid = intel_dp_get_edid(intel_dp);
4486 intel_connector->detect_edid = edid;
4487
4488 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4489 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4490 else
4491 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4492}
4493
beb60608
CW		 4494static void
4495intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4496{
beb60608 4497 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4498
beb60608
CW		 4499 kfree(intel_connector->detect_edid);
4500 intel_connector->detect_edid = NULL;
9cd300e0 4501
beb60608
CW		 4502 intel_dp->has_audio = false;
4503}
d6f24d0f 4504
beb60608
CW		 4505static enum intel_display_power_domain
4506intel_dp_power_get(struct intel_dp *dp)
4507{
4508 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4509 enum intel_display_power_domain power_domain;
4510
4511 power_domain = intel_display_port_power_domain(encoder);
4512 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4513
4514 return power_domain;
4515}
d6f24d0f 4516
beb60608
CW		 4517static void
4518intel_dp_power_put(struct intel_dp *dp,
4519 enum intel_display_power_domain power_domain)
4520{
4521 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4522 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4523}
4524
a9756bb5
ZW		 4525static enum drm_connector_status
4526intel_dp_detect(struct drm_connector *connector, bool force)
4527{
4528 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4529 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4530 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4531 struct drm_device *dev = connector->dev;
a9756bb5 4532 enum drm_connector_status status;
671dedd2 4533 enum intel_display_power_domain power_domain;
0e32b39c 4534 bool ret;
09b1eb13 4535 u8 sink_irq_vector;
a9756bb5 4536
164c8598 4537 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4538 connector->base.id, connector->name);
beb60608 4539 intel_dp_unset_edid(intel_dp);
164c8598 4540
0e32b39c
DA		 4541 if (intel_dp->is_mst) {
4542 /* MST devices are disconnected from a monitor POV */
4543 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4544 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4545 return connector_status_disconnected;
0e32b39c
DA		 4546 }
4547
beb60608 4548 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4549
d410b56d
CW		 4550 /* Can't disconnect eDP, but you can close the lid... */
4551 if (is_edp(intel_dp))
4552 status = edp_detect(intel_dp);
4553 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4554 status = ironlake_dp_detect(intel_dp);
4555 else
4556 status = g4x_dp_detect(intel_dp);
4557 if (status != connector_status_connected)
c8c8fb33 4558 goto out;
a9756bb5 4559
0d198328
AJ		 4560 intel_dp_probe_oui(intel_dp);
4561
0e32b39c
DA		 4562 ret = intel_dp_probe_mst(intel_dp);
4563 if (ret) {
4564 /* if we are in MST mode then this connector
4565 won't appear connected or have anything with EDID on it */
4566 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4567 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4568 status = connector_status_disconnected;
4569 goto out;
4570 }
4571
beb60608 4572 intel_dp_set_edid(intel_dp);
a9756bb5 4573
d63885da
PZ		 4574 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4575 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4576 status = connector_status_connected;
4577
09b1eb13
TP		 4578 /* Try to read the source of the interrupt */
4579 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4580 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4581 /* Clear interrupt source */
4582 drm_dp_dpcd_writeb(&intel_dp->aux,
4583 DP_DEVICE_SERVICE_IRQ_VECTOR,
4584 sink_irq_vector);
4585
4586 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4587 intel_dp_handle_test_request(intel_dp);
4588 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4589 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4590 }
4591
c8c8fb33 4592out:
beb60608 4593 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4594 return status;
a4fc5ed6
KP		 4595}
4596
beb60608
CW		 4597static void
4598intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4599{
df0e9248 4600 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4601 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4602 enum intel_display_power_domain power_domain;
a4fc5ed6 4603
beb60608
CW		 4604 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4605 connector->base.id, connector->name);
4606 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4607
beb60608
CW		 4608 if (connector->status != connector_status_connected)
4609 return;
671dedd2 4610
beb60608
CW		 4611 power_domain = intel_dp_power_get(intel_dp);
4612
4613 intel_dp_set_edid(intel_dp);
4614
4615 intel_dp_power_put(intel_dp, power_domain);
4616
4617 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4618 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4619}
4620
4621static int intel_dp_get_modes(struct drm_connector *connector)
4622{
4623 struct intel_connector *intel_connector = to_intel_connector(connector);
4624 struct edid *edid;
4625
4626 edid = intel_connector->detect_edid;
4627 if (edid) {
4628 int ret = intel_connector_update_modes(connector, edid);
4629 if (ret)
4630 return ret;
4631 }
32f9d658 4632
f8779fda 4633 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4634 if (is_edp(intel_attached_dp(connector)) &&
4635 intel_connector->panel.fixed_mode) {
f8779fda 4636 struct drm_display_mode *mode;
beb60608
CW		 4637
4638 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4639 intel_connector->panel.fixed_mode);
f8779fda 4640 if (mode) {
32f9d658
ZW		 4641 drm_mode_probed_add(connector, mode);
4642 return 1;
4643 }
4644 }
beb60608 4645
32f9d658 4646 return 0;
a4fc5ed6
KP		 4647}
4648
1aad7ac0
CW		 4649static bool
4650intel_dp_detect_audio(struct drm_connector *connector)
4651{
1aad7ac0 4652 bool has_audio = false;
beb60608 4653 struct edid *edid;
1aad7ac0 4654
beb60608
CW		 4655 edid = to_intel_connector(connector)->detect_edid;
4656 if (edid)
1aad7ac0 4657 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4658
1aad7ac0
CW		 4659 return has_audio;
4660}
4661
f684960e
CW		 4662static int
4663intel_dp_set_property(struct drm_connector *connector,
4664 struct drm_property *property,
4665 uint64_t val)
4666{
e953fd7b 4667 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4668 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4669 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4670 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4671 int ret;
4672
662595df 4673 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4674 if (ret)
4675 return ret;
4676
3f43c48d 4677 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4678 int i = val;
4679 bool has_audio;
4680
4681 if (i == intel_dp->force_audio)
f684960e
CW		 4682 return 0;
4683
1aad7ac0 4684 intel_dp->force_audio = i;
f684960e 4685
c3e5f67b 4686 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4687 has_audio = intel_dp_detect_audio(connector);
4688 else
c3e5f67b 4689 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4690
4691 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4692 return 0;
4693
1aad7ac0 4694 intel_dp->has_audio = has_audio;
f684960e
CW		 4695 goto done;
4696 }
4697
e953fd7b 4698 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 4699 bool old_auto = intel_dp->color_range_auto;
0f2a2a75 4700 bool old_range = intel_dp->limited_color_range;
ae4edb80 4701
55bc60db
VS		 4702 switch (val) {
4703 case INTEL_BROADCAST_RGB_AUTO:
4704 intel_dp->color_range_auto = true;
4705 break;
4706 case INTEL_BROADCAST_RGB_FULL:
4707 intel_dp->color_range_auto = false;
0f2a2a75 4708 intel_dp->limited_color_range = false;
55bc60db
VS		 4709 break;
4710 case INTEL_BROADCAST_RGB_LIMITED:
4711 intel_dp->color_range_auto = false;
0f2a2a75 4712 intel_dp->limited_color_range = true;
55bc60db
VS		 4713 break;
4714 default:
4715 return -EINVAL;
4716 }
ae4edb80
DV		 4717
4718 if (old_auto == intel_dp->color_range_auto &&
0f2a2a75 4719 old_range == intel_dp->limited_color_range)
ae4edb80
DV		 4720 return 0;
4721
e953fd7b
CW		 4722 goto done;
4723 }
4724
53b41837
YN		 4725 if (is_edp(intel_dp) &&
4726 property == connector->dev->mode_config.scaling_mode_property) {
4727 if (val == DRM_MODE_SCALE_NONE) {
4728 DRM_DEBUG_KMS("no scaling not supported\n");
4729 return -EINVAL;
4730 }
4731
4732 if (intel_connector->panel.fitting_mode == val) {
4733 /* the eDP scaling property is not changed */
4734 return 0;
4735 }
4736 intel_connector->panel.fitting_mode = val;
4737
4738 goto done;
4739 }
4740
f684960e
CW		 4741 return -EINVAL;
4742
4743done:
c0c36b94
CW		 4744 if (intel_encoder->base.crtc)
4745 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4746
4747 return 0;
4748}
4749
a4fc5ed6 4750static void
73845adf 4751intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4752{
1d508706 4753 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4754
10e972d3 4755 kfree(intel_connector->detect_edid);
beb60608 4756
9cd300e0
JN		 4757 if (!IS_ERR_OR_NULL(intel_connector->edid))
4758 kfree(intel_connector->edid);
4759
acd8db10
PZ		 4760 /* Can't call is_edp() since the encoder may have been destroyed
4761 * already. */
4762 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4763 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4764
a4fc5ed6 4765 drm_connector_cleanup(connector);
55f78c43 4766 kfree(connector);
a4fc5ed6
KP		 4767}
4768
00c09d70 4769void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4770{
da63a9f2
PZ		 4771 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4772 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4773
4f71d0cb 4774 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4775 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4776 if (is_edp(intel_dp)) {
4777 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4778 /*
4779 * vdd might still be enabled do to the delayed vdd off.
4780 * Make sure vdd is actually turned off here.
4781 */
773538e8 4782 pps_lock(intel_dp);
4be73780 4783 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4784 pps_unlock(intel_dp);
4785
01527b31
CT		 4786 if (intel_dp->edp_notifier.notifier_call) {
4787 unregister_reboot_notifier(&intel_dp->edp_notifier);
4788 intel_dp->edp_notifier.notifier_call = NULL;
4789 }
bd943159 4790 }
c8bd0e49 4791 drm_encoder_cleanup(encoder);
da63a9f2 4792 kfree(intel_dig_port);
24d05927
DV		 4793}
4794
07f9cd0b
ID		 4795static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4796{
4797 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4798
4799 if (!is_edp(intel_dp))
4800 return;
4801
951468f3
VS		 4802 /*
4803 * vdd might still be enabled do to the delayed vdd off.
4804 * Make sure vdd is actually turned off here.
4805 */
afa4e53a 4806 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4807 pps_lock(intel_dp);
07f9cd0b 4808 edp_panel_vdd_off_sync(intel_dp);
773538e8 4809 pps_unlock(intel_dp);
07f9cd0b
ID		 4810}
4811
49e6bc51
VS		 4812static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4813{
4814 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4815 struct drm_device *dev = intel_dig_port->base.base.dev;
4816 struct drm_i915_private *dev_priv = dev->dev_private;
4817 enum intel_display_power_domain power_domain;
4818
4819 lockdep_assert_held(&dev_priv->pps_mutex);
4820
4821 if (!edp_have_panel_vdd(intel_dp))
4822 return;
4823
4824 /*
4825 * The VDD bit needs a power domain reference, so if the bit is
4826 * already enabled when we boot or resume, grab this reference and
4827 * schedule a vdd off, so we don't hold on to the reference
4828 * indefinitely.
4829 */
4830 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4831 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4832 intel_display_power_get(dev_priv, power_domain);
4833
4834 edp_panel_vdd_schedule_off(intel_dp);
4835}
4836
6d93c0c4
ID		 4837static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4838{
49e6bc51
VS		 4839 struct intel_dp *intel_dp;
4840
4841 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4842 return;
4843
4844 intel_dp = enc_to_intel_dp(encoder);
4845
4846 pps_lock(intel_dp);
4847
4848 /*
4849 * Read out the current power sequencer assignment,
4850 * in case the BIOS did something with it.
4851 */
4852 if (IS_VALLEYVIEW(encoder->dev))
4853 vlv_initial_power_sequencer_setup(intel_dp);
4854
4855 intel_edp_panel_vdd_sanitize(intel_dp);
4856
4857 pps_unlock(intel_dp);
6d93c0c4
ID		 4858}
4859
a4fc5ed6 4860static const struct drm_connector_funcs intel_dp_connector_funcs = {
4d688a2a 4861 .dpms = drm_atomic_helper_connector_dpms,
a4fc5ed6 4862 .detect = intel_dp_detect,
beb60608 4863 .force = intel_dp_force,
a4fc5ed6 4864 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4865 .set_property = intel_dp_set_property,
2545e4a6 4866 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4867 .destroy = intel_dp_connector_destroy,
c6f95f27 4868 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4869 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4870};
4871
4872static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4873 .get_modes = intel_dp_get_modes,
4874 .mode_valid = intel_dp_mode_valid,
df0e9248 4875 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4876};
4877
a4fc5ed6 4878static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4879 .reset = intel_dp_encoder_reset,
24d05927 4880 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4881};
4882
b2c5c181 4883enum irqreturn
13cf5504
DA		 4884intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4885{
4886 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4887 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4888 struct drm_device *dev = intel_dig_port->base.base.dev;
4889 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4890 enum intel_display_power_domain power_domain;
b2c5c181 4891 enum irqreturn ret = IRQ_NONE;
1c767b33 4892
0e32b39c
DA		 4893 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4894 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4895
7a7f84cc
VS		 4896 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4897 /*
4898 * vdd off can generate a long pulse on eDP which
4899 * would require vdd on to handle it, and thus we
4900 * would end up in an endless cycle of
4901 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4902 */
4903 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4904 port_name(intel_dig_port->port));
a8b3d52f 4905 return IRQ_HANDLED;
7a7f84cc
VS		 4906 }
4907
26fbb774
VS		 4908 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4909 port_name(intel_dig_port->port),
0e32b39c 4910 long_hpd ? "long" : "short");
13cf5504 4911
1c767b33
ID		 4912 power_domain = intel_display_port_power_domain(intel_encoder);
4913 intel_display_power_get(dev_priv, power_domain);
4914
0e32b39c 4915 if (long_hpd) {
5fa836a9
MK		 4916 /* indicate that we need to restart link training */
4917 intel_dp->train_set_valid = false;
2a592bec 4918
7e66bcf2
JN		 4919 if (!intel_digital_port_connected(dev_priv, intel_dig_port))
4920 goto mst_fail;
0e32b39c
DA		 4921
4922 if (!intel_dp_get_dpcd(intel_dp)) {
4923 goto mst_fail;
4924 }
4925
4926 intel_dp_probe_oui(intel_dp);
4927
d14e7b6d
VS		 4928 if (!intel_dp_probe_mst(intel_dp)) {
4929 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4930 intel_dp_check_link_status(intel_dp);
4931 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c 4932 goto mst_fail;
d14e7b6d 4933 }
0e32b39c
DA		 4934 } else {
4935 if (intel_dp->is_mst) {
1c767b33 4936 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4937 goto mst_fail;
4938 }
4939
4940 if (!intel_dp->is_mst) {
5b215bcf 4941 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4942 intel_dp_check_link_status(intel_dp);
5b215bcf 4943 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4944 }
4945 }
b2c5c181
DV		 4946
4947 ret = IRQ_HANDLED;
4948
1c767b33 4949 goto put_power;
0e32b39c
DA		 4950mst_fail:
4951 /* if we were in MST mode, and device is not there get out of MST mode */
4952 if (intel_dp->is_mst) {
4953 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4954 intel_dp->is_mst = false;
4955 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4956 }
1c767b33
ID		 4957put_power:
4958 intel_display_power_put(dev_priv, power_domain);
4959
4960 return ret;
13cf5504
DA		 4961}
4962
e3421a18
ZW		 4963/* Return which DP Port should be selected for Transcoder DP control */
4964int
0206e353 4965intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4966{
4967 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4968 struct intel_encoder *intel_encoder;
4969 struct intel_dp *intel_dp;
e3421a18 4970
fa90ecef
PZ		 4971 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4972 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4973
fa90ecef
PZ		 4974 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4975 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4976 return intel_dp->output_reg;
e3421a18 4977 }
ea5b213a 4978
e3421a18
ZW		 4979 return -1;
4980}
4981
477ec328 4982/* check the VBT to see whether the eDP is on another port */
5d8a7752 4983bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4984{
4985 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4986 union child_device_config *p_child;
36e83a18 4987 int i;
5d8a7752 4988 static const short port_mapping[] = {
477ec328
RV		 4989 [PORT_B] = DVO_PORT_DPB,
4990 [PORT_C] = DVO_PORT_DPC,
4991 [PORT_D] = DVO_PORT_DPD,
4992 [PORT_E] = DVO_PORT_DPE,
5d8a7752 4993 };
36e83a18 4994
53ce81a7
VS		 4995 /*
4996 * eDP not supported on g4x. so bail out early just
4997 * for a bit extra safety in case the VBT is bonkers.
4998 */
4999 if (INTEL_INFO(dev)->gen < 5)
5000 return false;
5001
3b32a35b
VS		 5002 if (port == PORT_A)
5003 return true;
5004
41aa3448 5005 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 5006 return false;
5007
41aa3448
RV		 5008 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
5009 p_child = dev_priv->vbt.child_dev + i;
36e83a18 5010
5d8a7752 5011 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 5012 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
5013 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 5014 return true;
5015 }
5016 return false;
5017}
5018
0e32b39c 5019void
f684960e
CW		 5020intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5021{
53b41837
YN		 5022 struct intel_connector *intel_connector = to_intel_connector(connector);
5023
3f43c48d 5024 intel_attach_force_audio_property(connector);
e953fd7b 5025 intel_attach_broadcast_rgb_property(connector);
55bc60db 5026 intel_dp->color_range_auto = true;
53b41837
YN		 5027
5028 if (is_edp(intel_dp)) {
5029 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 5030 drm_object_attach_property(
5031 &connector->base,
53b41837 5032 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 5033 DRM_MODE_SCALE_ASPECT);
5034 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 5035 }
f684960e
CW		 5036}
5037
dada1a9f
ID		 5038static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5039{
5040 intel_dp->last_power_cycle = jiffies;
5041 intel_dp->last_power_on = jiffies;
5042 intel_dp->last_backlight_off = jiffies;
5043}
5044
67a54566
DV		 5045static void
5046intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 5047 struct intel_dp *intel_dp)
67a54566
DV		 5048{
5049 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 5050 struct edp_power_seq cur, vbt, spec,
5051 *final = &intel_dp->pps_delays;
b0a08bec
VK		 5052 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5053 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;
453c5420 5054
e39b999a
VS		 5055 lockdep_assert_held(&dev_priv->pps_mutex);
5056
81ddbc69
VS		 5057 /* already initialized? */
5058 if (final->t11_t12 != 0)
5059 return;
5060
b0a08bec
VK		 5061 if (IS_BROXTON(dev)) {
5062 /*
5063 * TODO: BXT has 2 sets of PPS registers.
5064 * Correct Register for Broxton need to be identified
5065 * using VBT. hardcoding for now
5066 */
5067 pp_ctrl_reg = BXT_PP_CONTROL(0);
5068 pp_on_reg = BXT_PP_ON_DELAYS(0);
5069 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5070 } else if (HAS_PCH_SPLIT(dev)) {
bf13e81b 5071 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 5072 pp_on_reg = PCH_PP_ON_DELAYS;
5073 pp_off_reg = PCH_PP_OFF_DELAYS;
5074 pp_div_reg = PCH_PP_DIVISOR;
5075 } else {
bf13e81b
JN		 5076 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5077
5078 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5079 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5080 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5081 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 5082 }
67a54566
DV		 5083
5084 /* Workaround: Need to write PP_CONTROL with the unlock key as
5085 * the very first thing. */
b0a08bec 5086 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 5087
453c5420
JB		 5088 pp_on = I915_READ(pp_on_reg);
5089 pp_off = I915_READ(pp_off_reg);
b0a08bec
VK		 5090 if (!IS_BROXTON(dev)) {
5091 I915_WRITE(pp_ctrl_reg, pp_ctl);
5092 pp_div = I915_READ(pp_div_reg);
5093 }
67a54566
DV		 5094
5095 /* Pull timing values out of registers */
5096 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5097 PANEL_POWER_UP_DELAY_SHIFT;
5098
5099 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5100 PANEL_LIGHT_ON_DELAY_SHIFT;
5101
5102 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5103 PANEL_LIGHT_OFF_DELAY_SHIFT;
5104
5105 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5106 PANEL_POWER_DOWN_DELAY_SHIFT;
5107
b0a08bec
VK		 5108 if (IS_BROXTON(dev)) {
5109 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5110 BXT_POWER_CYCLE_DELAY_SHIFT;
5111 if (tmp > 0)
5112 cur.t11_t12 = (tmp - 1) * 1000;
5113 else
5114 cur.t11_t12 = 0;
5115 } else {
5116 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 5117 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 5118 }
67a54566
DV		 5119
5120 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5121 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5122
41aa3448 5123 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 5124
5125 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5126 * our hw here, which are all in 100usec. */
5127 spec.t1_t3 = 210 * 10;
5128 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5129 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5130 spec.t10 = 500 * 10;
5131 /* This one is special and actually in units of 100ms, but zero
5132 * based in the hw (so we need to add 100 ms). But the sw vbt
5133 * table multiplies it with 1000 to make it in units of 100usec,
5134 * too. */
5135 spec.t11_t12 = (510 + 100) * 10;
5136
5137 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5138 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5139
5140 /* Use the max of the register settings and vbt. If both are
5141 * unset, fall back to the spec limits. */
36b5f425 5142#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 5143 spec.field : \
5144 max(cur.field, vbt.field))
5145 assign_final(t1_t3);
5146 assign_final(t8);
5147 assign_final(t9);
5148 assign_final(t10);
5149 assign_final(t11_t12);
5150#undef assign_final
5151
36b5f425 5152#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 5153 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5154 intel_dp->backlight_on_delay = get_delay(t8);
5155 intel_dp->backlight_off_delay = get_delay(t9);
5156 intel_dp->panel_power_down_delay = get_delay(t10);
5157 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5158#undef get_delay
5159
f30d26e4
JN		 5160 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5161 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5162 intel_dp->panel_power_cycle_delay);
5163
5164 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5165 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 5166}
5167
5168static void
5169intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 5170 struct intel_dp *intel_dp)
f30d26e4
JN		 5171{
5172 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 5173 u32 pp_on, pp_off, pp_div, port_sel = 0;
5174 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
b0a08bec 5175 int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;
ad933b56 5176 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 5177 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 5178
e39b999a 5179 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 5180
b0a08bec
VK		 5181 if (IS_BROXTON(dev)) {
5182 /*
5183 * TODO: BXT has 2 sets of PPS registers.
5184 * Correct Register for Broxton need to be identified
5185 * using VBT. hardcoding for now
5186 */
5187 pp_ctrl_reg = BXT_PP_CONTROL(0);
5188 pp_on_reg = BXT_PP_ON_DELAYS(0);
5189 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5190
5191 } else if (HAS_PCH_SPLIT(dev)) {
453c5420
JB		 5192 pp_on_reg = PCH_PP_ON_DELAYS;
5193 pp_off_reg = PCH_PP_OFF_DELAYS;
5194 pp_div_reg = PCH_PP_DIVISOR;
5195 } else {
bf13e81b
JN		 5196 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5197
5198 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5199 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5200 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 5201 }
5202
b2f19d1a
PZ		 5203 /*
5204 * And finally store the new values in the power sequencer. The
5205 * backlight delays are set to 1 because we do manual waits on them. For
5206 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5207 * we'll end up waiting for the backlight off delay twice: once when we
5208 * do the manual sleep, and once when we disable the panel and wait for
5209 * the PP_STATUS bit to become zero.
5210 */
f30d26e4 5211 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 5212 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5213 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5214 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5215 /* Compute the divisor for the pp clock, simply match the Bspec
5216 * formula. */
b0a08bec
VK		 5217 if (IS_BROXTON(dev)) {
5218 pp_div = I915_READ(pp_ctrl_reg);
5219 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5220 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5221 << BXT_POWER_CYCLE_DELAY_SHIFT);
5222 } else {
5223 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5224 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5225 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5226 }
67a54566
DV		 5227
5228 /* Haswell doesn't have any port selection bits for the panel
5229 * power sequencer any more. */
bc7d38a4 5230 if (IS_VALLEYVIEW(dev)) {
ad933b56 5231 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 5232 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 5233 if (port == PORT_A)
a24c144c 5234 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5235 else
a24c144c 5236 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5237 }
5238
453c5420
JB		 5239 pp_on |= port_sel;
5240
5241 I915_WRITE(pp_on_reg, pp_on);
5242 I915_WRITE(pp_off_reg, pp_off);
b0a08bec
VK		 5243 if (IS_BROXTON(dev))
5244 I915_WRITE(pp_ctrl_reg, pp_div);
5245 else
5246 I915_WRITE(pp_div_reg, pp_div);
67a54566 5247
67a54566 5248 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 5249 I915_READ(pp_on_reg),
5250 I915_READ(pp_off_reg),
b0a08bec
VK		 5251 IS_BROXTON(dev) ?
5252 (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
453c5420 5253 I915_READ(pp_div_reg));
f684960e
CW		 5254}
5255
b33a2815
VK		 5256/**
5257 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5258 * @dev: DRM device
5259 * @refresh_rate: RR to be programmed
5260 *
5261 * This function gets called when refresh rate (RR) has to be changed from
5262 * one frequency to another. Switches can be between high and low RR
5263 * supported by the panel or to any other RR based on media playback (in
5264 * this case, RR value needs to be passed from user space).
5265 *
5266 * The caller of this function needs to take a lock on dev_priv->drrs.
5267 */
96178eeb 5268static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 5269{
5270 struct drm_i915_private *dev_priv = dev->dev_private;
5271 struct intel_encoder *encoder;
96178eeb
VK		 5272 struct intel_digital_port *dig_port = NULL;
5273 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 5274 struct intel_crtc_state *config = NULL;
439d7ac0 5275 struct intel_crtc *intel_crtc = NULL;
96178eeb 5276 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5277
5278 if (refresh_rate <= 0) {
5279 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5280 return;
5281 }
5282
96178eeb
VK		 5283 if (intel_dp == NULL) {
5284 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5285 return;
5286 }
5287
1fcc9d1c 5288 /*
e4d59f6b
RV		 5289 * FIXME: This needs proper synchronization with psr state for some
5290 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5291 */
439d7ac0 5292
96178eeb
VK		 5293 dig_port = dp_to_dig_port(intel_dp);
5294 encoder = &dig_port->base;
723f9aab 5295 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5296
5297 if (!intel_crtc) {
5298 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5299 return;
5300 }
5301
6e3c9717 5302 config = intel_crtc->config;
439d7ac0 5303
96178eeb 5304 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5305 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5306 return;
5307 }
5308
96178eeb
VK		 5309 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5310 refresh_rate)
439d7ac0
PB		 5311 index = DRRS_LOW_RR;
5312
96178eeb 5313 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5314 DRM_DEBUG_KMS(
5315 "DRRS requested for previously set RR...ignoring\n");
5316 return;
5317 }
5318
5319 if (!intel_crtc->active) {
5320 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5321 return;
5322 }
5323
44395bfe 5324 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5325 switch (index) {
5326 case DRRS_HIGH_RR:
5327 intel_dp_set_m_n(intel_crtc, M1_N1);
5328 break;
5329 case DRRS_LOW_RR:
5330 intel_dp_set_m_n(intel_crtc, M2_N2);
5331 break;
5332 case DRRS_MAX_RR:
5333 default:
5334 DRM_ERROR("Unsupported refreshrate type\n");
5335 }
5336 } else if (INTEL_INFO(dev)->gen > 6) {
649636ef
VS		 5337 u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5338 u32 val;
a4c30b1d 5339
649636ef 5340 val = I915_READ(reg);
439d7ac0 5341 if (index > DRRS_HIGH_RR) {
6fa7aec1
VK		 5342 if (IS_VALLEYVIEW(dev))
5343 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5344 else
5345 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5346 } else {
6fa7aec1
VK		 5347 if (IS_VALLEYVIEW(dev))
5348 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5349 else
5350 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5351 }
5352 I915_WRITE(reg, val);
5353 }
5354
4e9ac947
VK		 5355 dev_priv->drrs.refresh_rate_type = index;
5356
5357 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5358}
5359
b33a2815
VK		 5360/**
5361 * intel_edp_drrs_enable - init drrs struct if supported
5362 * @intel_dp: DP struct
5363 *
5364 * Initializes frontbuffer_bits and drrs.dp
5365 */
c395578e
VK		 5366void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5367{
5368 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5369 struct drm_i915_private *dev_priv = dev->dev_private;
5370 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5371 struct drm_crtc *crtc = dig_port->base.base.crtc;
5372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5373
5374 if (!intel_crtc->config->has_drrs) {
5375 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5376 return;
5377 }
5378
5379 mutex_lock(&dev_priv->drrs.mutex);
5380 if (WARN_ON(dev_priv->drrs.dp)) {
5381 DRM_ERROR("DRRS already enabled\n");
5382 goto unlock;
5383 }
5384
5385 dev_priv->drrs.busy_frontbuffer_bits = 0;
5386
5387 dev_priv->drrs.dp = intel_dp;
5388
5389unlock:
5390 mutex_unlock(&dev_priv->drrs.mutex);
5391}
5392
b33a2815
VK		 5393/**
5394 * intel_edp_drrs_disable - Disable DRRS
5395 * @intel_dp: DP struct
5396 *
5397 */
c395578e
VK		 5398void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5399{
5400 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5401 struct drm_i915_private *dev_priv = dev->dev_private;
5402 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5403 struct drm_crtc *crtc = dig_port->base.base.crtc;
5404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5405
5406 if (!intel_crtc->config->has_drrs)
5407 return;
5408
5409 mutex_lock(&dev_priv->drrs.mutex);
5410 if (!dev_priv->drrs.dp) {
5411 mutex_unlock(&dev_priv->drrs.mutex);
5412 return;
5413 }
5414
5415 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5416 intel_dp_set_drrs_state(dev_priv->dev,
5417 intel_dp->attached_connector->panel.
5418 fixed_mode->vrefresh);
5419
5420 dev_priv->drrs.dp = NULL;
5421 mutex_unlock(&dev_priv->drrs.mutex);
5422
5423 cancel_delayed_work_sync(&dev_priv->drrs.work);
5424}
5425
4e9ac947
VK		 5426static void intel_edp_drrs_downclock_work(struct work_struct *work)
5427{
5428 struct drm_i915_private *dev_priv =
5429 container_of(work, typeof(*dev_priv), drrs.work.work);
5430 struct intel_dp *intel_dp;
5431
5432 mutex_lock(&dev_priv->drrs.mutex);
5433
5434 intel_dp = dev_priv->drrs.dp;
5435
5436 if (!intel_dp)
5437 goto unlock;
5438
439d7ac0 5439 /*
4e9ac947
VK		 5440 * The delayed work can race with an invalidate hence we need to
5441 * recheck.
439d7ac0
PB		 5442 */
5443
4e9ac947
VK		 5444 if (dev_priv->drrs.busy_frontbuffer_bits)
5445 goto unlock;
439d7ac0 5446
4e9ac947
VK		 5447 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5448 intel_dp_set_drrs_state(dev_priv->dev,
5449 intel_dp->attached_connector->panel.
5450 downclock_mode->vrefresh);
439d7ac0 5451
4e9ac947 5452unlock:
4e9ac947 5453 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5454}
5455
b33a2815 5456/**
0ddfd203 5457 * intel_edp_drrs_invalidate - Disable Idleness DRRS
b33a2815
VK		 5458 * @dev: DRM device
5459 * @frontbuffer_bits: frontbuffer plane tracking bits
5460 *
0ddfd203
R		 5461 * This function gets called everytime rendering on the given planes start.
5462 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5463 *
5464 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5465 */
a93fad0f
VK		 5466void intel_edp_drrs_invalidate(struct drm_device *dev,
5467 unsigned frontbuffer_bits)
5468{
5469 struct drm_i915_private *dev_priv = dev->dev_private;
5470 struct drm_crtc *crtc;
5471 enum pipe pipe;
5472
9da7d693 5473 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5474 return;
5475
88f933a8 5476 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5477
a93fad0f 5478 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5479 if (!dev_priv->drrs.dp) {
5480 mutex_unlock(&dev_priv->drrs.mutex);
5481 return;
5482 }
5483
a93fad0f
VK		 5484 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5485 pipe = to_intel_crtc(crtc)->pipe;
5486
c1d038c6
DV		 5487 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5488 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5489
0ddfd203 5490 /* invalidate means busy screen hence upclock */
c1d038c6 5491 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
a93fad0f
VK		 5492 intel_dp_set_drrs_state(dev_priv->dev,
5493 dev_priv->drrs.dp->attached_connector->panel.
5494 fixed_mode->vrefresh);
a93fad0f 5495
a93fad0f
VK		 5496 mutex_unlock(&dev_priv->drrs.mutex);
5497}
5498
b33a2815 5499/**
0ddfd203 5500 * intel_edp_drrs_flush - Restart Idleness DRRS
b33a2815
VK		 5501 * @dev: DRM device
5502 * @frontbuffer_bits: frontbuffer plane tracking bits
5503 *
0ddfd203
R		 5504 * This function gets called every time rendering on the given planes has
5505 * completed or flip on a crtc is completed. So DRRS should be upclocked
5506 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5507 * if no other planes are dirty.
b33a2815
VK		 5508 *
5509 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5510 */
a93fad0f
VK		 5511void intel_edp_drrs_flush(struct drm_device *dev,
5512 unsigned frontbuffer_bits)
5513{
5514 struct drm_i915_private *dev_priv = dev->dev_private;
5515 struct drm_crtc *crtc;
5516 enum pipe pipe;
5517
9da7d693 5518 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5519 return;
5520
88f933a8 5521 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5522
a93fad0f 5523 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5524 if (!dev_priv->drrs.dp) {
5525 mutex_unlock(&dev_priv->drrs.mutex);
5526 return;
5527 }
5528
a93fad0f
VK		 5529 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5530 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5531
5532 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5533 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5534
0ddfd203 5535 /* flush means busy screen hence upclock */
c1d038c6 5536 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
0ddfd203
R		 5537 intel_dp_set_drrs_state(dev_priv->dev,
5538 dev_priv->drrs.dp->attached_connector->panel.
5539 fixed_mode->vrefresh);
5540
5541 /*
5542 * flush also means no more activity hence schedule downclock, if all
5543 * other fbs are quiescent too
5544 */
5545 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5546 schedule_delayed_work(&dev_priv->drrs.work,
5547 msecs_to_jiffies(1000));
5548 mutex_unlock(&dev_priv->drrs.mutex);
5549}
5550
b33a2815
VK		 5551/**
5552 * DOC: Display Refresh Rate Switching (DRRS)
5553 *
5554 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5555 * which enables swtching between low and high refresh rates,
5556 * dynamically, based on the usage scenario. This feature is applicable
5557 * for internal panels.
5558 *
5559 * Indication that the panel supports DRRS is given by the panel EDID, which
5560 * would list multiple refresh rates for one resolution.
5561 *
5562 * DRRS is of 2 types - static and seamless.
5563 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5564 * (may appear as a blink on screen) and is used in dock-undock scenario.
5565 * Seamless DRRS involves changing RR without any visual effect to the user
5566 * and can be used during normal system usage. This is done by programming
5567 * certain registers.
5568 *
5569 * Support for static/seamless DRRS may be indicated in the VBT based on
5570 * inputs from the panel spec.
5571 *
5572 * DRRS saves power by switching to low RR based on usage scenarios.
5573 *
5574 * eDP DRRS:-
5575 * The implementation is based on frontbuffer tracking implementation.
5576 * When there is a disturbance on the screen triggered by user activity or a
5577 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5578 * When there is no movement on screen, after a timeout of 1 second, a switch
5579 * to low RR is made.
5580 * For integration with frontbuffer tracking code,
5581 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5582 *
5583 * DRRS can be further extended to support other internal panels and also
5584 * the scenario of video playback wherein RR is set based on the rate
5585 * requested by userspace.
5586 */
5587
5588/**
5589 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5590 * @intel_connector: eDP connector
5591 * @fixed_mode: preferred mode of panel
5592 *
5593 * This function is called only once at driver load to initialize basic
5594 * DRRS stuff.
5595 *
5596 * Returns:
5597 * Downclock mode if panel supports it, else return NULL.
5598 * DRRS support is determined by the presence of downclock mode (apart
5599 * from VBT setting).
5600 */
4f9db5b5 5601static struct drm_display_mode *
96178eeb
VK		 5602intel_dp_drrs_init(struct intel_connector *intel_connector,
5603 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5604{
5605 struct drm_connector *connector = &intel_connector->base;
96178eeb 5606 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5607 struct drm_i915_private *dev_priv = dev->dev_private;
5608 struct drm_display_mode *downclock_mode = NULL;
5609
9da7d693
DV		 5610 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5611 mutex_init(&dev_priv->drrs.mutex);
5612
4f9db5b5
PB		 5613 if (INTEL_INFO(dev)->gen <= 6) {
5614 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5615 return NULL;
5616 }
5617
5618 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5619 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5620 return NULL;
5621 }
5622
5623 downclock_mode = intel_find_panel_downclock
5624 (dev, fixed_mode, connector);
5625
5626 if (!downclock_mode) {
a1d26342 5627 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5628 return NULL;
5629 }
5630
96178eeb 5631 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5632
96178eeb 5633 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5634 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5635 return downclock_mode;
5636}
5637
ed92f0b2 5638static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5639 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5640{
5641 struct drm_connector *connector = &intel_connector->base;
5642 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5643 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5644 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5645 struct drm_i915_private *dev_priv = dev->dev_private;
5646 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5647 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5648 bool has_dpcd;
5649 struct drm_display_mode *scan;
5650 struct edid *edid;
6517d273 5651 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5652
5653 if (!is_edp(intel_dp))
5654 return true;
5655
49e6bc51
VS		 5656 pps_lock(intel_dp);
5657 intel_edp_panel_vdd_sanitize(intel_dp);
5658 pps_unlock(intel_dp);
63635217 5659
ed92f0b2 5660 /* Cache DPCD and EDID for edp. */
ed92f0b2 5661 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5662
5663 if (has_dpcd) {
5664 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5665 dev_priv->no_aux_handshake =
5666 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5667 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5668 } else {
5669 /* if this fails, presume the device is a ghost */
5670 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5671 return false;
5672 }
5673
5674 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5675 pps_lock(intel_dp);
36b5f425 5676 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5677 pps_unlock(intel_dp);
ed92f0b2 5678
060c8778 5679 mutex_lock(&dev->mode_config.mutex);
0b99836f 5680 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5681 if (edid) {
5682 if (drm_add_edid_modes(connector, edid)) {
5683 drm_mode_connector_update_edid_property(connector,
5684 edid);
5685 drm_edid_to_eld(connector, edid);
5686 } else {
5687 kfree(edid);
5688 edid = ERR_PTR(-EINVAL);
5689 }
5690 } else {
5691 edid = ERR_PTR(-ENOENT);
5692 }
5693 intel_connector->edid = edid;
5694
5695 /* prefer fixed mode from EDID if available */
5696 list_for_each_entry(scan, &connector->probed_modes, head) {
5697 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5698 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5699 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5700 intel_connector, fixed_mode);
ed92f0b2
PZ		 5701 break;
5702 }
5703 }
5704
5705 /* fallback to VBT if available for eDP */
5706 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5707 fixed_mode = drm_mode_duplicate(dev,
5708 dev_priv->vbt.lfp_lvds_vbt_mode);
5709 if (fixed_mode)
5710 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5711 }
060c8778 5712 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5713
01527b31
CT		 5714 if (IS_VALLEYVIEW(dev)) {
5715 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5716 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5717
5718 /*
5719 * Figure out the current pipe for the initial backlight setup.
5720 * If the current pipe isn't valid, try the PPS pipe, and if that
5721 * fails just assume pipe A.
5722 */
5723 if (IS_CHERRYVIEW(dev))
5724 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5725 else
5726 pipe = PORT_TO_PIPE(intel_dp->DP);
5727
5728 if (pipe != PIPE_A && pipe != PIPE_B)
5729 pipe = intel_dp->pps_pipe;
5730
5731 if (pipe != PIPE_A && pipe != PIPE_B)
5732 pipe = PIPE_A;
5733
5734 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5735 pipe_name(pipe));
01527b31
CT		 5736 }
5737
4f9db5b5 5738 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5507faeb 5739 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6517d273 5740 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5741
5742 return true;
5743}
5744
16c25533 5745bool
f0fec3f2
PZ		 5746intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5747 struct intel_connector *intel_connector)
a4fc5ed6 5748{
f0fec3f2
PZ		 5749 struct drm_connector *connector = &intel_connector->base;
5750 struct intel_dp *intel_dp = &intel_dig_port->dp;
5751 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5752 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5753 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5754 enum port port = intel_dig_port->port;
0b99836f 5755 int type;
a4fc5ed6 5756
a4a5d2f8
VS		 5757 intel_dp->pps_pipe = INVALID_PIPE;
5758
ec5b01dd 5759 /* intel_dp vfuncs */
b6b5e383
DL		 5760 if (INTEL_INFO(dev)->gen >= 9)
5761 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5762 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5763 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5764 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5765 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5766 else if (HAS_PCH_SPLIT(dev))
5767 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5768 else
5769 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5770
b9ca5fad
DL		 5771 if (INTEL_INFO(dev)->gen >= 9)
5772 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5773 else
5774 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5775
ad64217b
ACO		 5776 if (HAS_DDI(dev))
5777 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5778
0767935e
DV		 5779 /* Preserve the current hw state. */
5780 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5781 intel_dp->attached_connector = intel_connector;
3d3dc149 5782
3b32a35b 5783 if (intel_dp_is_edp(dev, port))
b329530c 5784 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5785 else
5786 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5787
f7d24902
ID		 5788 /*
5789 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5790 * for DP the encoder type can be set by the caller to
5791 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5792 */
5793 if (type == DRM_MODE_CONNECTOR_eDP)
5794 intel_encoder->type = INTEL_OUTPUT_EDP;
5795
c17ed5b5
VS		 5796 /* eDP only on port B and/or C on vlv/chv */
5797 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5798 port != PORT_B && port != PORT_C))
5799 return false;
5800
e7281eab
ID		 5801 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5802 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5803 port_name(port));
5804
b329530c 5805 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5806 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5807
a4fc5ed6
KP		 5808 connector->interlace_allowed = true;
5809 connector->doublescan_allowed = 0;
5810
f0fec3f2 5811 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5812 edp_panel_vdd_work);
a4fc5ed6 5813
df0e9248 5814 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5815 drm_connector_register(connector);
a4fc5ed6 5816
affa9354 5817 if (HAS_DDI(dev))
bcbc889b
PZ		 5818 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5819 else
5820 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5821 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5822
0b99836f 5823 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5824 switch (port) {
5825 case PORT_A:
1d843f9d 5826 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5827 break;
5828 case PORT_B:
1d843f9d 5829 intel_encoder->hpd_pin = HPD_PORT_B;
e87a005d 5830 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
cf1d5883 5831 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5832 break;
5833 case PORT_C:
1d843f9d 5834 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5835 break;
5836 case PORT_D:
1d843f9d 5837 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30 5838 break;
26951caf
XZ		 5839 case PORT_E:
5840 intel_encoder->hpd_pin = HPD_PORT_E;
5841 break;
ab9d7c30 5842 default:
ad1c0b19 5843 BUG();
5eb08b69
ZW		 5844 }
5845
dada1a9f 5846 if (is_edp(intel_dp)) {
773538e8 5847 pps_lock(intel_dp);
1e74a324
VS		 5848 intel_dp_init_panel_power_timestamps(intel_dp);
5849 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5850 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5851 else
36b5f425 5852 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5853 pps_unlock(intel_dp);
dada1a9f 5854 }
0095e6dc 5855
9d1a1031 5856 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5857
0e32b39c 5858 /* init MST on ports that can support it */
0c9b3715
JN		 5859 if (HAS_DP_MST(dev) &&
5860 (port == PORT_B || port == PORT_C || port == PORT_D))
5861 intel_dp_mst_encoder_init(intel_dig_port,
5862 intel_connector->base.base.id);
0e32b39c 5863
36b5f425 5864 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5865 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5866 if (is_edp(intel_dp)) {
5867 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5868 /*
5869 * vdd might still be enabled do to the delayed vdd off.
5870 * Make sure vdd is actually turned off here.
5871 */
773538e8 5872 pps_lock(intel_dp);
4be73780 5873 edp_panel_vdd_off_sync(intel_dp);
773538e8 5874 pps_unlock(intel_dp);
15b1d171 5875 }
34ea3d38 5876 drm_connector_unregister(connector);
b2f246a8 5877 drm_connector_cleanup(connector);
16c25533 5878 return false;
b2f246a8 5879 }
32f9d658 5880
f684960e
CW		 5881 intel_dp_add_properties(intel_dp, connector);
5882
a4fc5ed6
KP		 5883 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5884 * 0xd. Failure to do so will result in spurious interrupts being
5885 * generated on the port when a cable is not attached.
5886 */
5887 if (IS_G4X(dev) && !IS_GM45(dev)) {
5888 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5889 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5890 }
16c25533 5891
aa7471d2
JN		 5892 i915_debugfs_connector_add(connector);
5893
16c25533 5894 return true;
a4fc5ed6 5895}
f0fec3f2
PZ		 5896
5897void
5898intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5899{
13cf5504 5900 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5901 struct intel_digital_port *intel_dig_port;
5902 struct intel_encoder *intel_encoder;
5903 struct drm_encoder *encoder;
5904 struct intel_connector *intel_connector;
5905
b14c5679 5906 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5907 if (!intel_dig_port)
5908 return;
5909
08d9bc92 5910 intel_connector = intel_connector_alloc();
11aee0f6
SM		 5911 if (!intel_connector)
5912 goto err_connector_alloc;
f0fec3f2
PZ		 5913
5914 intel_encoder = &intel_dig_port->base;
5915 encoder = &intel_encoder->base;
5916
5917 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5918 DRM_MODE_ENCODER_TMDS);
5919
5bfe2ac0 5920 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5921 intel_encoder->disable = intel_disable_dp;
00c09d70 5922 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5923 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5924 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5925 if (IS_CHERRYVIEW(dev)) {
9197c88b 5926 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5927 intel_encoder->pre_enable = chv_pre_enable_dp;
5928 intel_encoder->enable = vlv_enable_dp;
580d3811 5929 intel_encoder->post_disable = chv_post_disable_dp;
d6db995f 5930 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
e4a1d846 5931 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5932 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5933 intel_encoder->pre_enable = vlv_pre_enable_dp;
5934 intel_encoder->enable = vlv_enable_dp;
49277c31 5935 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5936 } else {
ecff4f3b
JN		 5937 intel_encoder->pre_enable = g4x_pre_enable_dp;
5938 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5939 if (INTEL_INFO(dev)->gen >= 5)
5940 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5941 }
f0fec3f2 5942
174edf1f 5943 intel_dig_port->port = port;
f0fec3f2
PZ		 5944 intel_dig_port->dp.output_reg = output_reg;
5945
00c09d70 5946 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5947 if (IS_CHERRYVIEW(dev)) {
5948 if (port == PORT_D)
5949 intel_encoder->crtc_mask = 1 << 2;
5950 else
5951 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5952 } else {
5953 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5954 }
bc079e8b 5955 intel_encoder->cloneable = 0;
f0fec3f2 5956
13cf5504 5957 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 5958 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 5959
11aee0f6
SM		 5960 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5961 goto err_init_connector;
5962
5963 return;
5964
5965err_init_connector:
5966 drm_encoder_cleanup(encoder);
5967 kfree(intel_connector);
5968err_connector_alloc:
5969 kfree(intel_dig_port);
5970
5971 return;
f0fec3f2 5972}
0e32b39c
DA		 5973
5974void intel_dp_mst_suspend(struct drm_device *dev)
5975{
5976 struct drm_i915_private *dev_priv = dev->dev_private;
5977 int i;
5978
5979 /* disable MST */
5980 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5981 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 5982 if (!intel_dig_port)
5983 continue;
5984
5985 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5986 if (!intel_dig_port->dp.can_mst)
5987 continue;
5988 if (intel_dig_port->dp.is_mst)
5989 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5990 }
5991 }
5992}
5993
5994void intel_dp_mst_resume(struct drm_device *dev)
5995{
5996 struct drm_i915_private *dev_priv = dev->dev_private;
5997 int i;
5998
5999 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 6000 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 6001 if (!intel_dig_port)
6002 continue;
6003 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6004 int ret;
6005
6006 if (!intel_dig_port->dp.can_mst)
6007 continue;
6008
6009 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6010 if (ret != 0) {
6011 intel_dp_check_mst_status(&intel_dig_port->dp);
6012 }
6013 }
6014 }
6015}
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