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drm/i915: save some time when waiting the eDP timings
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 94
a4fc5ed6 95static int
ea5b213a 96intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 97{
7183dc29 98 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 99
100 switch (max_link_bw) {
101 case DP_LINK_BW_1_62:
102 case DP_LINK_BW_2_7:
103 break;
d4eead50
ID		 104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
105 max_link_bw = DP_LINK_BW_2_7;
106 break;
a4fc5ed6 107 default:
d4eead50
ID		 108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
109 max_link_bw);
a4fc5ed6
KP		 110 max_link_bw = DP_LINK_BW_1_62;
111 break;
112 }
113 return max_link_bw;
114}
115
cd9dde44
AJ		 116/*
117 * The units on the numbers in the next two are... bizarre. Examples will
118 * make it clearer; this one parallels an example in the eDP spec.
119 *
120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
121 *
122 * 270000 * 1 * 8 / 10 == 216000
123 *
124 * The actual data capacity of that configuration is 2.16Gbit/s, so the
125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
127 * 119000. At 18bpp that's 2142000 kilobits per second.
128 *
129 * Thus the strange-looking division by 10 in intel_dp_link_required, to
130 * get the result in decakilobits instead of kilobits.
131 */
132
a4fc5ed6 133static int
c898261c 134intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 135{
cd9dde44 136 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 137}
138
fe27d53e
DA		 139static int
140intel_dp_max_data_rate(int max_link_clock, int max_lanes)
141{
142 return (max_link_clock * max_lanes * 8) / 10;
143}
144
c19de8eb 145static enum drm_mode_status
a4fc5ed6
KP		 146intel_dp_mode_valid(struct drm_connector *connector,
147 struct drm_display_mode *mode)
148{
df0e9248 149 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 150 struct intel_connector *intel_connector = to_intel_connector(connector);
151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 152 int target_clock = mode->clock;
153 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 154
dd06f90e
JN		 155 if (is_edp(intel_dp) && fixed_mode) {
156 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 157 return MODE_PANEL;
158
dd06f90e 159 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 160 return MODE_PANEL;
03afc4a2
DV		 161
162 target_clock = fixed_mode->clock;
7de56f43
ZY		 163 }
164
36008365
DV		 165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
167
168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
169 mode_rate = intel_dp_link_required(target_clock, 18);
170
171 if (mode_rate > max_rate)
c4867936 172 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 173
174 if (mode->clock < 10000)
175 return MODE_CLOCK_LOW;
176
0af78a2b
DV		 177 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
178 return MODE_H_ILLEGAL;
179
a4fc5ed6
KP		 180 return MODE_OK;
181}
182
183static uint32_t
184pack_aux(uint8_t *src, int src_bytes)
185{
186 int i;
187 uint32_t v = 0;
188
189 if (src_bytes > 4)
190 src_bytes = 4;
191 for (i = 0; i < src_bytes; i++)
192 v |= ((uint32_t) src[i]) << ((3-i) * 8);
193 return v;
194}
195
196static void
197unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
198{
199 int i;
200 if (dst_bytes > 4)
201 dst_bytes = 4;
202 for (i = 0; i < dst_bytes; i++)
203 dst[i] = src >> ((3-i) * 8);
204}
205
fb0f8fbf
KP		 206/* hrawclock is 1/4 the FSB frequency */
207static int
208intel_hrawclk(struct drm_device *dev)
209{
210 struct drm_i915_private *dev_priv = dev->dev_private;
211 uint32_t clkcfg;
212
9473c8f4
VP		 213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
214 if (IS_VALLEYVIEW(dev))
215 return 200;
216
fb0f8fbf
KP		 217 clkcfg = I915_READ(CLKCFG);
218 switch (clkcfg & CLKCFG_FSB_MASK) {
219 case CLKCFG_FSB_400:
220 return 100;
221 case CLKCFG_FSB_533:
222 return 133;
223 case CLKCFG_FSB_667:
224 return 166;
225 case CLKCFG_FSB_800:
226 return 200;
227 case CLKCFG_FSB_1067:
228 return 266;
229 case CLKCFG_FSB_1333:
230 return 333;
231 /* these two are just a guess; one of them might be right */
232 case CLKCFG_FSB_1600:
233 case CLKCFG_FSB_1600_ALT:
234 return 400;
235 default:
236 return 133;
237 }
238}
239
bf13e81b
JN		 240static void
241intel_dp_init_panel_power_sequencer(struct drm_device *dev,
242 struct intel_dp *intel_dp,
243 struct edp_power_seq *out);
244static void
245intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
246 struct intel_dp *intel_dp,
247 struct edp_power_seq *out);
248
249static enum pipe
250vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
251{
252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 enum port port = intel_dig_port->port;
257 enum pipe pipe;
258
259 /* modeset should have pipe */
260 if (crtc)
261 return to_intel_crtc(crtc)->pipe;
262
263 /* init time, try to find a pipe with this port selected */
264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
266 PANEL_PORT_SELECT_MASK;
267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
268 return pipe;
269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
270 return pipe;
271 }
272
273 /* shrug */
274 return PIPE_A;
275}
276
277static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
278{
279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
280
281 if (HAS_PCH_SPLIT(dev))
282 return PCH_PP_CONTROL;
283 else
284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
285}
286
287static u32 _pp_stat_reg(struct intel_dp *intel_dp)
288{
289 struct drm_device *dev = intel_dp_to_dev(intel_dp);
290
291 if (HAS_PCH_SPLIT(dev))
292 return PCH_PP_STATUS;
293 else
294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
295}
296
ebf33b18
KP		 297static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
298{
30add22d 299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 300 struct drm_i915_private *dev_priv = dev->dev_private;
301
bf13e81b 302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 303}
304
305static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
306{
30add22d 307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 308 struct drm_i915_private *dev_priv = dev->dev_private;
309
bf13e81b 310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 311}
312
9b984dae
KP		 313static void
314intel_dp_check_edp(struct intel_dp *intel_dp)
315{
30add22d 316 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 317 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 318
9b984dae
KP		 319 if (!is_edp(intel_dp))
320 return;
453c5420 321
ebf33b18 322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 323 WARN(1, "eDP powered off while attempting aux channel communication.\n");
324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 325 I915_READ(_pp_stat_reg(intel_dp)),
326 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 327 }
328}
329
9ee32fea
DV		 330static uint32_t
331intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
332{
333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
334 struct drm_device *dev = intel_dig_port->base.base.dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 337 uint32_t status;
338 bool done;
339
ef04f00d 340#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 341 if (has_aux_irq)
b18ac466 342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 343 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 344 else
345 done = wait_for_atomic(C, 10) == 0;
346 if (!done)
347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
348 has_aux_irq);
349#undef C
350
351 return status;
352}
353
bc86625a
CW		 354static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
355 int index)
a4fc5ed6 356{
174edf1f
PZ		 357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
358 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 359 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 360
a4fc5ed6 361 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 364 *
365 * Note that PCH attached eDP panels should use a 125MHz input
366 * clock divider.
a4fc5ed6 367 */
a62d0834 368 if (IS_VALLEYVIEW(dev)) {
bc86625a 369 return index ? 0 : 100;
a62d0834 370 } else if (intel_dig_port->port == PORT_A) {
bc86625a
CW		 371 if (index)
372 return 0;
affa9354 373 if (HAS_DDI(dev))
bc86625a 374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 375 else if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 376 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 377 else
b84a1cf8 378 return 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
380 /* Workaround for non-ULT HSW */
bc86625a
CW		 381 switch (index) {
382 case 0: return 63;
383 case 1: return 72;
384 default: return 0;
385 }
2c55c336 386 } else if (HAS_PCH_SPLIT(dev)) {
bc86625a 387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 388 } else {
bc86625a 389 return index ? 0 :intel_hrawclk(dev) / 2;
2c55c336 390 }
b84a1cf8
RV		 391}
392
393static int
394intel_dp_aux_ch(struct intel_dp *intel_dp,
395 uint8_t *send, int send_bytes,
396 uint8_t *recv, int recv_size)
397{
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
402 uint32_t ch_data = ch_ctl + 4;
bc86625a 403 uint32_t aux_clock_divider;
b84a1cf8
RV		 404 int i, ret, recv_bytes;
405 uint32_t status;
bc86625a 406 int try, precharge, clock = 0;
4aeebd74 407 bool has_aux_irq = true;
a81a507d 408 uint32_t timeout;
b84a1cf8
RV		 409
410 /* dp aux is extremely sensitive to irq latency, hence request the
411 * lowest possible wakeup latency and so prevent the cpu from going into
412 * deep sleep states.
413 */
414 pm_qos_update_request(&dev_priv->pm_qos, 0);
415
416 intel_dp_check_edp(intel_dp);
5eb08b69 417
6b4e0a93
DV		 418 if (IS_GEN6(dev))
419 precharge = 3;
420 else
421 precharge = 5;
422
a81a507d
BW		 423 if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL)
424 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
425 else
426 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
427
c67a470b
PZ		 428 intel_aux_display_runtime_get(dev_priv);
429
11bee43e
JB		 430 /* Try to wait for any previous AUX channel activity */
431 for (try = 0; try < 3; try++) {
ef04f00d 432 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 433 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
434 break;
435 msleep(1);
436 }
437
438 if (try == 3) {
439 WARN(1, "dp_aux_ch not started status 0x%08x\n",
440 I915_READ(ch_ctl));
9ee32fea
DV		 441 ret = -EBUSY;
442 goto out;
4f7f7b7e
CW		 443 }
444
46a5ae9f
PZ		 445 /* Only 5 data registers! */
446 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
447 ret = -E2BIG;
448 goto out;
449 }
450
bc86625a
CW		 451 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
452 /* Must try at least 3 times according to DP spec */
453 for (try = 0; try < 5; try++) {
454 /* Load the send data into the aux channel data registers */
455 for (i = 0; i < send_bytes; i += 4)
456 I915_WRITE(ch_data + i,
457 pack_aux(send + i, send_bytes - i));
458
459 /* Send the command and wait for it to complete */
460 I915_WRITE(ch_ctl,
461 DP_AUX_CH_CTL_SEND_BUSY |
462 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
a81a507d 463 timeout |
bc86625a
CW		 464 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
465 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
466 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
467 DP_AUX_CH_CTL_DONE |
468 DP_AUX_CH_CTL_TIME_OUT_ERROR |
469 DP_AUX_CH_CTL_RECEIVE_ERROR);
470
471 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
472
473 /* Clear done status and any errors */
474 I915_WRITE(ch_ctl,
475 status |
476 DP_AUX_CH_CTL_DONE |
477 DP_AUX_CH_CTL_TIME_OUT_ERROR |
478 DP_AUX_CH_CTL_RECEIVE_ERROR);
479
480 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
481 DP_AUX_CH_CTL_RECEIVE_ERROR))
482 continue;
483 if (status & DP_AUX_CH_CTL_DONE)
484 break;
485 }
4f7f7b7e 486 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 487 break;
488 }
489
a4fc5ed6 490 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 492 ret = -EBUSY;
493 goto out;
a4fc5ed6
KP		 494 }
495
496 /* Check for timeout or receive error.
497 * Timeouts occur when the sink is not connected
498 */
a5b3da54 499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 501 ret = -EIO;
502 goto out;
a5b3da54 503 }
1ae8c0a5
KP		 504
505 /* Timeouts occur when the device isn't connected, so they're
506 * "normal" -- don't fill the kernel log with these */
a5b3da54 507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 509 ret = -ETIMEDOUT;
510 goto out;
a4fc5ed6
KP		 511 }
512
513 /* Unload any bytes sent back from the other side */
514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 516 if (recv_bytes > recv_size)
517 recv_bytes = recv_size;
0206e353 518
4f7f7b7e
CW		 519 for (i = 0; i < recv_bytes; i += 4)
520 unpack_aux(I915_READ(ch_data + i),
521 recv + i, recv_bytes - i);
a4fc5ed6 522
9ee32fea
DV		 523 ret = recv_bytes;
524out:
525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 526 intel_aux_display_runtime_put(dev_priv);
9ee32fea
DV		 527
528 return ret;
a4fc5ed6
KP		 529}
530
531/* Write data to the aux channel in native mode */
532static int
ea5b213a 533intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 534 uint16_t address, uint8_t *send, int send_bytes)
535{
536 int ret;
537 uint8_t msg[20];
538 int msg_bytes;
539 uint8_t ack;
540
46a5ae9f
PZ		 541 if (WARN_ON(send_bytes > 16))
542 return -E2BIG;
543
9b984dae 544 intel_dp_check_edp(intel_dp);
6b27f7f0 545 msg[0] = DP_AUX_NATIVE_WRITE << 4;
a4fc5ed6 546 msg[1] = address >> 8;
eebc863e 547 msg[2] = address & 0xff;
a4fc5ed6
KP		 548 msg[3] = send_bytes - 1;
549 memcpy(&msg[4], send, send_bytes);
550 msg_bytes = send_bytes + 4;
551 for (;;) {
ea5b213a 552 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 553 if (ret < 0)
554 return ret;
6b27f7f0
TR		 555 ack >>= 4;
556 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
a4fc5ed6 557 break;
6b27f7f0 558 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
a4fc5ed6
KP		 559 udelay(100);
560 else
a5b3da54 561 return -EIO;
a4fc5ed6
KP		 562 }
563 return send_bytes;
564}
565
566/* Write a single byte to the aux channel in native mode */
567static int
ea5b213a 568intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 569 uint16_t address, uint8_t byte)
570{
ea5b213a 571 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 572}
573
574/* read bytes from a native aux channel */
575static int
ea5b213a 576intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 577 uint16_t address, uint8_t *recv, int recv_bytes)
578{
579 uint8_t msg[4];
580 int msg_bytes;
581 uint8_t reply[20];
582 int reply_bytes;
583 uint8_t ack;
584 int ret;
585
46a5ae9f
PZ		 586 if (WARN_ON(recv_bytes > 19))
587 return -E2BIG;
588
9b984dae 589 intel_dp_check_edp(intel_dp);
6b27f7f0 590 msg[0] = DP_AUX_NATIVE_READ << 4;
a4fc5ed6
KP		 591 msg[1] = address >> 8;
592 msg[2] = address & 0xff;
593 msg[3] = recv_bytes - 1;
594
595 msg_bytes = 4;
596 reply_bytes = recv_bytes + 1;
597
598 for (;;) {
ea5b213a 599 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 600 reply, reply_bytes);
a5b3da54
KP		 601 if (ret == 0)
602 return -EPROTO;
603 if (ret < 0)
a4fc5ed6 604 return ret;
6b27f7f0
TR		 605 ack = reply[0] >> 4;
606 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
a4fc5ed6
KP		 607 memcpy(recv, reply + 1, ret - 1);
608 return ret - 1;
609 }
6b27f7f0 610 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
a4fc5ed6
KP		 611 udelay(100);
612 else
a5b3da54 613 return -EIO;
a4fc5ed6
KP		 614 }
615}
616
617static int
ab2c0672
DA		 618intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
619 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 620{
ab2c0672 621 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 622 struct intel_dp *intel_dp = container_of(adapter,
623 struct intel_dp,
624 adapter);
ab2c0672
DA		 625 uint16_t address = algo_data->address;
626 uint8_t msg[5];
627 uint8_t reply[2];
8316f337 628 unsigned retry;
ab2c0672
DA		 629 int msg_bytes;
630 int reply_bytes;
631 int ret;
632
8a5e6aeb 633 ironlake_edp_panel_vdd_on(intel_dp);
9b984dae 634 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 635 /* Set up the command byte */
636 if (mode & MODE_I2C_READ)
6b27f7f0 637 msg[0] = DP_AUX_I2C_READ << 4;
ab2c0672 638 else
6b27f7f0 639 msg[0] = DP_AUX_I2C_WRITE << 4;
ab2c0672
DA		 640
641 if (!(mode & MODE_I2C_STOP))
6b27f7f0 642 msg[0] |= DP_AUX_I2C_MOT << 4;
a4fc5ed6 643
ab2c0672
DA		 644 msg[1] = address >> 8;
645 msg[2] = address;
646
647 switch (mode) {
648 case MODE_I2C_WRITE:
649 msg[3] = 0;
650 msg[4] = write_byte;
651 msg_bytes = 5;
652 reply_bytes = 1;
653 break;
654 case MODE_I2C_READ:
655 msg[3] = 0;
656 msg_bytes = 4;
657 reply_bytes = 2;
658 break;
659 default:
660 msg_bytes = 3;
661 reply_bytes = 1;
662 break;
663 }
664
58c67ce9
JN		 665 /*
666 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
667 * required to retry at least seven times upon receiving AUX_DEFER
668 * before giving up the AUX transaction.
669 */
670 for (retry = 0; retry < 7; retry++) {
8316f337
DF		 671 ret = intel_dp_aux_ch(intel_dp,
672 msg, msg_bytes,
673 reply, reply_bytes);
ab2c0672 674 if (ret < 0) {
3ff99164 675 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
8a5e6aeb 676 goto out;
ab2c0672 677 }
8316f337 678
6b27f7f0
TR		 679 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
680 case DP_AUX_NATIVE_REPLY_ACK:
8316f337
DF		 681 /* I2C-over-AUX Reply field is only valid
682 * when paired with AUX ACK.
683 */
684 break;
6b27f7f0 685 case DP_AUX_NATIVE_REPLY_NACK:
8316f337 686 DRM_DEBUG_KMS("aux_ch native nack\n");
8a5e6aeb
PZ		 687 ret = -EREMOTEIO;
688 goto out;
6b27f7f0 689 case DP_AUX_NATIVE_REPLY_DEFER:
8d16f258
JN		 690 /*
691 * For now, just give more slack to branch devices. We
692 * could check the DPCD for I2C bit rate capabilities,
693 * and if available, adjust the interval. We could also
694 * be more careful with DP-to-Legacy adapters where a
695 * long legacy cable may force very low I2C bit rates.
696 */
697 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
698 DP_DWN_STRM_PORT_PRESENT)
699 usleep_range(500, 600);
700 else
701 usleep_range(300, 400);
8316f337
DF		 702 continue;
703 default:
704 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
705 reply[0]);
8a5e6aeb
PZ		 706 ret = -EREMOTEIO;
707 goto out;
8316f337
DF		 708 }
709
6b27f7f0
TR		 710 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
711 case DP_AUX_I2C_REPLY_ACK:
ab2c0672
DA		 712 if (mode == MODE_I2C_READ) {
713 *read_byte = reply[1];
714 }
8a5e6aeb
PZ		 715 ret = reply_bytes - 1;
716 goto out;
6b27f7f0 717 case DP_AUX_I2C_REPLY_NACK:
8316f337 718 DRM_DEBUG_KMS("aux_i2c nack\n");
8a5e6aeb
PZ		 719 ret = -EREMOTEIO;
720 goto out;
6b27f7f0 721 case DP_AUX_I2C_REPLY_DEFER:
8316f337 722 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 723 udelay(100);
724 break;
725 default:
8316f337 726 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
8a5e6aeb
PZ		 727 ret = -EREMOTEIO;
728 goto out;
ab2c0672
DA		 729 }
730 }
8316f337
DF		 731
732 DRM_ERROR("too many retries, giving up\n");
8a5e6aeb
PZ		 733 ret = -EREMOTEIO;
734
735out:
736 ironlake_edp_panel_vdd_off(intel_dp, false);
737 return ret;
a4fc5ed6
KP		 738}
739
740static int
ea5b213a 741intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 742 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 743{
0b5c541b
KP		 744 int ret;
745
d54e9d28 746 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 747 intel_dp->algo.running = false;
748 intel_dp->algo.address = 0;
749 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
750
0206e353 751 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 752 intel_dp->adapter.owner = THIS_MODULE;
753 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 754 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 755 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
756 intel_dp->adapter.algo_data = &intel_dp->algo;
5bdebb18 757 intel_dp->adapter.dev.parent = intel_connector->base.kdev;
ea5b213a 758
0b5c541b 759 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
0b5c541b 760 return ret;
a4fc5ed6
KP		 761}
762
c6bb3538
DV		 763static void
764intel_dp_set_clock(struct intel_encoder *encoder,
765 struct intel_crtc_config *pipe_config, int link_bw)
766{
767 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 768 const struct dp_link_dpll *divisor = NULL;
769 int i, count = 0;
c6bb3538
DV		 770
771 if (IS_G4X(dev)) {
9dd4ffdf
CML		 772 divisor = gen4_dpll;
773 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 774 } else if (IS_HASWELL(dev)) {
775 /* Haswell has special-purpose DP DDI clocks. */
776 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 777 divisor = pch_dpll;
778 count = ARRAY_SIZE(pch_dpll);
c6bb3538 779 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 780 divisor = vlv_dpll;
781 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 782 }
9dd4ffdf
CML		 783
784 if (divisor && count) {
785 for (i = 0; i < count; i++) {
786 if (link_bw == divisor[i].link_bw) {
787 pipe_config->dpll = divisor[i].dpll;
788 pipe_config->clock_set = true;
789 break;
790 }
791 }
c6bb3538
DV		 792 }
793}
794
00c09d70 795bool
5bfe2ac0
DV		 796intel_dp_compute_config(struct intel_encoder *encoder,
797 struct intel_crtc_config *pipe_config)
a4fc5ed6 798{
5bfe2ac0 799 struct drm_device *dev = encoder->base.dev;
36008365 800 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 801 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 802 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 803 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 804 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 805 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 806 int lane_count, clock;
397fe157 807 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 808 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 809 int bpp, mode_rate;
a4fc5ed6 810 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
ff9a6750 811 int link_avail, link_clock;
a4fc5ed6 812
bc7d38a4 813 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 814 pipe_config->has_pch_encoder = true;
815
03afc4a2 816 pipe_config->has_dp_encoder = true;
a4fc5ed6 817
dd06f90e
JN		 818 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
819 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
820 adjusted_mode);
2dd24552
JB		 821 if (!HAS_PCH_SPLIT(dev))
822 intel_gmch_panel_fitting(intel_crtc, pipe_config,
823 intel_connector->panel.fitting_mode);
824 else
b074cec8
JB		 825 intel_pch_panel_fitting(intel_crtc, pipe_config,
826 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 827 }
828
cb1793ce 829 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 830 return false;
831
083f9560
DV		 832 DRM_DEBUG_KMS("DP link computation with max lane count %i "
833 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 834 max_lane_count, bws[max_clock],
835 adjusted_mode->crtc_clock);
083f9560 836
36008365
DV		 837 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
838 * bpc in between. */
3e7ca985 839 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 840 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
841 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 842 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
843 dev_priv->vbt.edp_bpp);
6da7f10d 844 bpp = dev_priv->vbt.edp_bpp;
7984211e 845 }
657445fe 846
36008365 847 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 848 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
849 bpp);
36008365
DV		 850
851 for (clock = 0; clock <= max_clock; clock++) {
852 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
853 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
854 link_avail = intel_dp_max_data_rate(link_clock,
855 lane_count);
856
857 if (mode_rate <= link_avail) {
858 goto found;
859 }
860 }
861 }
862 }
c4867936 863
36008365 864 return false;
3685a8f3 865
36008365 866found:
55bc60db
VS		 867 if (intel_dp->color_range_auto) {
868 /*
869 * See:
870 * CEA-861-E - 5.1 Default Encoding Parameters
871 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
872 */
18316c8c 873 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 874 intel_dp->color_range = DP_COLOR_RANGE_16_235;
875 else
876 intel_dp->color_range = 0;
877 }
878
3685a8f3 879 if (intel_dp->color_range)
50f3b016 880 pipe_config->limited_color_range = true;
a4fc5ed6 881
36008365
DV		 882 intel_dp->link_bw = bws[clock];
883 intel_dp->lane_count = lane_count;
657445fe 884 pipe_config->pipe_bpp = bpp;
ff9a6750 885 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 886
36008365
DV		 887 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
888 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 889 pipe_config->port_clock, bpp);
36008365
DV		 890 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
891 mode_rate, link_avail);
a4fc5ed6 892
03afc4a2 893 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 894 adjusted_mode->crtc_clock,
895 pipe_config->port_clock,
03afc4a2 896 &pipe_config->dp_m_n);
9d1a455b 897
c6bb3538
DV		 898 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
899
03afc4a2 900 return true;
a4fc5ed6
KP		 901}
902
7c62a164 903static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 904{
7c62a164
DV		 905 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
906 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
907 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 908 struct drm_i915_private *dev_priv = dev->dev_private;
909 u32 dpa_ctl;
910
ff9a6750 911 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 912 dpa_ctl = I915_READ(DP_A);
913 dpa_ctl &= ~DP_PLL_FREQ_MASK;
914
ff9a6750 915 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 916 /* For a long time we've carried around a ILK-DevA w/a for the
917 * 160MHz clock. If we're really unlucky, it's still required.
918 */
919 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 920 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 921 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 922 } else {
923 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 924 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 925 }
1ce17038 926
ea9b6006
DV		 927 I915_WRITE(DP_A, dpa_ctl);
928
929 POSTING_READ(DP_A);
930 udelay(500);
931}
932
b934223d 933static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 934{
b934223d 935 struct drm_device *dev = encoder->base.dev;
417e822d 936 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 937 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 938 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 939 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
940 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 941
417e822d 942 /*
1a2eb460 943 * There are four kinds of DP registers:
417e822d
KP		 944 *
945 * IBX PCH
1a2eb460
KP		 946 * SNB CPU
947 * IVB CPU
417e822d
KP		 948 * CPT PCH
949 *
950 * IBX PCH and CPU are the same for almost everything,
951 * except that the CPU DP PLL is configured in this
952 * register
953 *
954 * CPT PCH is quite different, having many bits moved
955 * to the TRANS_DP_CTL register instead. That
956 * configuration happens (oddly) in ironlake_pch_enable
957 */
9c9e7927 958
417e822d
KP		 959 /* Preserve the BIOS-computed detected bit. This is
960 * supposed to be read-only.
961 */
962 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 963
417e822d 964 /* Handle DP bits in common between all three register formats */
417e822d 965 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 966 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 967
e0dac65e
WF		 968 if (intel_dp->has_audio) {
969 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 970 pipe_name(crtc->pipe));
ea5b213a 971 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 972 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 973 }
247d89f6 974
417e822d 975 /* Split out the IBX/CPU vs CPT settings */
32f9d658 976
bc7d38a4 977 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 978 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
979 intel_dp->DP |= DP_SYNC_HS_HIGH;
980 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
981 intel_dp->DP |= DP_SYNC_VS_HIGH;
982 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
983
6aba5b6c 984 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 985 intel_dp->DP |= DP_ENHANCED_FRAMING;
986
7c62a164 987 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 988 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 989 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 990 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 991
992 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
993 intel_dp->DP |= DP_SYNC_HS_HIGH;
994 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
995 intel_dp->DP |= DP_SYNC_VS_HIGH;
996 intel_dp->DP |= DP_LINK_TRAIN_OFF;
997
6aba5b6c 998 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 999 intel_dp->DP |= DP_ENHANCED_FRAMING;
1000
7c62a164 1001 if (crtc->pipe == 1)
417e822d 1002 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 1003 } else {
1004 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1005 }
ea9b6006 1006
bc7d38a4 1007 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 1008 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 1009}
1010
99ea7127
KP		 1011#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1012#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1013
1014#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1015#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1016
1017#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1018#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1019
1020static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1021 u32 mask,
1022 u32 value)
bd943159 1023{
30add22d 1024 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1025 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1026 u32 pp_stat_reg, pp_ctrl_reg;
1027
bf13e81b
JN		 1028 pp_stat_reg = _pp_stat_reg(intel_dp);
1029 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1030
99ea7127 1031 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1032 mask, value,
1033 I915_READ(pp_stat_reg),
1034 I915_READ(pp_ctrl_reg));
32ce697c 1035
453c5420 1036 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1037 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1038 I915_READ(pp_stat_reg),
1039 I915_READ(pp_ctrl_reg));
32ce697c 1040 }
54c136d4
CW		 1041
1042 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1043}
32ce697c 1044
99ea7127
KP		 1045static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1046{
1047 DRM_DEBUG_KMS("Wait for panel power on\n");
1048 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1049}
1050
99ea7127
KP		 1051static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1052{
1053 DRM_DEBUG_KMS("Wait for panel power off time\n");
1054 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1055}
1056
1057static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1058{
1059 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1060
1061 /* When we disable the VDD override bit last we have to do the manual
1062 * wait. */
1063 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1064 intel_dp->panel_power_cycle_delay);
1065
99ea7127
KP		 1066 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1067}
1068
dce56b3c
PZ		 1069static void ironlake_wait_backlight_on(struct intel_dp *intel_dp)
1070{
1071 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1072 intel_dp->backlight_on_delay);
1073}
1074
1075static void ironlake_edp_wait_backlight_off(struct intel_dp *intel_dp)
1076{
1077 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1078 intel_dp->backlight_off_delay);
1079}
99ea7127 1080
832dd3c1
KP		 1081/* Read the current pp_control value, unlocking the register if it
1082 * is locked
1083 */
1084
453c5420 1085static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1086{
453c5420
JB		 1087 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1088 struct drm_i915_private *dev_priv = dev->dev_private;
1089 u32 control;
832dd3c1 1090
bf13e81b 1091 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1092 control &= ~PANEL_UNLOCK_MASK;
1093 control |= PANEL_UNLOCK_REGS;
1094 return control;
bd943159
KP		 1095}
1096
82a4d9c0 1097void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1098{
30add22d 1099 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1100 struct drm_i915_private *dev_priv = dev->dev_private;
1101 u32 pp;
453c5420 1102 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1103
97af61f5
KP		 1104 if (!is_edp(intel_dp))
1105 return;
5d613501 1106
bd943159
KP		 1107 WARN(intel_dp->want_panel_vdd,
1108 "eDP VDD already requested on\n");
1109
1110 intel_dp->want_panel_vdd = true;
99ea7127 1111
b0665d57 1112 if (ironlake_edp_have_panel_vdd(intel_dp))
bd943159 1113 return;
b0665d57 1114
e9cb81a2
PZ		 1115 intel_runtime_pm_get(dev_priv);
1116
b0665d57 1117 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1118
99ea7127
KP		 1119 if (!ironlake_edp_have_panel_power(intel_dp))
1120 ironlake_wait_panel_power_cycle(intel_dp);
1121
453c5420 1122 pp = ironlake_get_pp_control(intel_dp);
5d613501 1123 pp |= EDP_FORCE_VDD;
ebf33b18 1124
bf13e81b
JN		 1125 pp_stat_reg = _pp_stat_reg(intel_dp);
1126 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1127
1128 I915_WRITE(pp_ctrl_reg, pp);
1129 POSTING_READ(pp_ctrl_reg);
1130 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1131 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1132 /*
1133 * If the panel wasn't on, delay before accessing aux channel
1134 */
1135 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1136 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1137 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1138 }
5d613501
JB		 1139}
1140
bd943159 1141static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1142{
30add22d 1143 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1144 struct drm_i915_private *dev_priv = dev->dev_private;
1145 u32 pp;
453c5420 1146 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1147
a0e99e68
DV		 1148 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1149
bd943159 1150 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
b0665d57
PZ		 1151 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1152
453c5420 1153 pp = ironlake_get_pp_control(intel_dp);
bd943159 1154 pp &= ~EDP_FORCE_VDD;
bd943159 1155
9f08ef59
PZ		 1156 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1157 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1158
1159 I915_WRITE(pp_ctrl_reg, pp);
1160 POSTING_READ(pp_ctrl_reg);
99ea7127 1161
453c5420
JB		 1162 /* Make sure sequencer is idle before allowing subsequent activity */
1163 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1164 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1165
1166 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1167 intel_dp->last_power_cycle = jiffies;
e9cb81a2
PZ		 1168
1169 intel_runtime_pm_put(dev_priv);
bd943159
KP		 1170 }
1171}
5d613501 1172
bd943159
KP		 1173static void ironlake_panel_vdd_work(struct work_struct *__work)
1174{
1175 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1176 struct intel_dp, panel_vdd_work);
30add22d 1177 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1178
627f7675 1179 mutex_lock(&dev->mode_config.mutex);
bd943159 1180 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1181 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1182}
1183
82a4d9c0 1184void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1185{
97af61f5
KP		 1186 if (!is_edp(intel_dp))
1187 return;
5d613501 1188
bd943159 1189 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1190
bd943159
KP		 1191 intel_dp->want_panel_vdd = false;
1192
1193 if (sync) {
1194 ironlake_panel_vdd_off_sync(intel_dp);
1195 } else {
1196 /*
1197 * Queue the timer to fire a long
1198 * time from now (relative to the power down delay)
1199 * to keep the panel power up across a sequence of operations
1200 */
1201 schedule_delayed_work(&intel_dp->panel_vdd_work,
1202 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1203 }
5d613501
JB		 1204}
1205
82a4d9c0 1206void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1207{
30add22d 1208 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1209 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1210 u32 pp;
453c5420 1211 u32 pp_ctrl_reg;
9934c132 1212
97af61f5 1213 if (!is_edp(intel_dp))
bd943159 1214 return;
99ea7127
KP		 1215
1216 DRM_DEBUG_KMS("Turn eDP power on\n");
1217
1218 if (ironlake_edp_have_panel_power(intel_dp)) {
1219 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1220 return;
99ea7127 1221 }
9934c132 1222
99ea7127 1223 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1224
bf13e81b 1225 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1226 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1227 if (IS_GEN5(dev)) {
1228 /* ILK workaround: disable reset around power sequence */
1229 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1230 I915_WRITE(pp_ctrl_reg, pp);
1231 POSTING_READ(pp_ctrl_reg);
05ce1a49 1232 }
37c6c9b0 1233
1c0ae80a 1234 pp |= POWER_TARGET_ON;
99ea7127
KP		 1235 if (!IS_GEN5(dev))
1236 pp |= PANEL_POWER_RESET;
1237
453c5420
JB		 1238 I915_WRITE(pp_ctrl_reg, pp);
1239 POSTING_READ(pp_ctrl_reg);
9934c132 1240
99ea7127 1241 ironlake_wait_panel_on(intel_dp);
dce56b3c 1242 intel_dp->last_power_on = jiffies;
9934c132 1243
05ce1a49
KP		 1244 if (IS_GEN5(dev)) {
1245 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1246 I915_WRITE(pp_ctrl_reg, pp);
1247 POSTING_READ(pp_ctrl_reg);
05ce1a49 1248 }
9934c132
JB		 1249}
1250
82a4d9c0 1251void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1252{
30add22d 1253 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1254 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1255 u32 pp;
453c5420 1256 u32 pp_ctrl_reg;
9934c132 1257
97af61f5
KP		 1258 if (!is_edp(intel_dp))
1259 return;
37c6c9b0 1260
99ea7127 1261 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1262
dce56b3c
PZ		 1263 ironlake_edp_wait_backlight_off(intel_dp);
1264
453c5420 1265 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1266 /* We need to switch off panel power _and_ force vdd, for otherwise some
1267 * panels get very unhappy and cease to work. */
dff392db 1268 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420 1269
bf13e81b 1270 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1271
1272 I915_WRITE(pp_ctrl_reg, pp);
1273 POSTING_READ(pp_ctrl_reg);
9934c132 1274
dce56b3c 1275 intel_dp->last_power_cycle = jiffies;
99ea7127 1276 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1277}
1278
d6c50ff8 1279void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1280{
da63a9f2
PZ		 1281 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1282 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1283 struct drm_i915_private *dev_priv = dev->dev_private;
1284 u32 pp;
453c5420 1285 u32 pp_ctrl_reg;
32f9d658 1286
f01eca2e
KP		 1287 if (!is_edp(intel_dp))
1288 return;
1289
28c97730 1290 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1291 /*
1292 * If we enable the backlight right away following a panel power
1293 * on, we may see slight flicker as the panel syncs with the eDP
1294 * link. So delay a bit to make sure the image is solid before
1295 * allowing it to appear.
1296 */
dce56b3c 1297 ironlake_wait_backlight_on(intel_dp);
453c5420 1298 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1299 pp |= EDP_BLC_ENABLE;
453c5420 1300
bf13e81b 1301 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1302
1303 I915_WRITE(pp_ctrl_reg, pp);
1304 POSTING_READ(pp_ctrl_reg);
035aa3de 1305
752aa88a 1306 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1307}
1308
d6c50ff8 1309void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1310{
30add22d 1311 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1312 struct drm_i915_private *dev_priv = dev->dev_private;
1313 u32 pp;
453c5420 1314 u32 pp_ctrl_reg;
32f9d658 1315
f01eca2e
KP		 1316 if (!is_edp(intel_dp))
1317 return;
1318
752aa88a 1319 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1320
28c97730 1321 DRM_DEBUG_KMS("\n");
453c5420 1322 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1323 pp &= ~EDP_BLC_ENABLE;
453c5420 1324
bf13e81b 1325 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1326
1327 I915_WRITE(pp_ctrl_reg, pp);
1328 POSTING_READ(pp_ctrl_reg);
dce56b3c 1329 intel_dp->last_backlight_off = jiffies;
32f9d658 1330}
a4fc5ed6 1331
2bd2ad64 1332static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1333{
da63a9f2
PZ		 1334 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1335 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1336 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1337 struct drm_i915_private *dev_priv = dev->dev_private;
1338 u32 dpa_ctl;
1339
2bd2ad64
DV		 1340 assert_pipe_disabled(dev_priv,
1341 to_intel_crtc(crtc)->pipe);
1342
d240f20f
JB		 1343 DRM_DEBUG_KMS("\n");
1344 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1345 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1346 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1347
1348 /* We don't adjust intel_dp->DP while tearing down the link, to
1349 * facilitate link retraining (e.g. after hotplug). Hence clear all
1350 * enable bits here to ensure that we don't enable too much. */
1351 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1352 intel_dp->DP |= DP_PLL_ENABLE;
1353 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1354 POSTING_READ(DP_A);
1355 udelay(200);
d240f20f
JB		 1356}
1357
2bd2ad64 1358static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1359{
da63a9f2
PZ		 1360 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1361 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1362 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1363 struct drm_i915_private *dev_priv = dev->dev_private;
1364 u32 dpa_ctl;
1365
2bd2ad64
DV		 1366 assert_pipe_disabled(dev_priv,
1367 to_intel_crtc(crtc)->pipe);
1368
d240f20f 1369 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1370 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1371 "dp pll off, should be on\n");
1372 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1373
1374 /* We can't rely on the value tracked for the DP register in
1375 * intel_dp->DP because link_down must not change that (otherwise link
1376 * re-training will fail. */
298b0b39 1377 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1378 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1379 POSTING_READ(DP_A);
d240f20f
JB		 1380 udelay(200);
1381}
1382
c7ad3810 1383/* If the sink supports it, try to set the power state appropriately */
c19b0669 1384void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1385{
1386 int ret, i;
1387
1388 /* Should have a valid DPCD by this point */
1389 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1390 return;
1391
1392 if (mode != DRM_MODE_DPMS_ON) {
1393 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1394 DP_SET_POWER_D3);
1395 if (ret != 1)
1396 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1397 } else {
1398 /*
1399 * When turning on, we need to retry for 1ms to give the sink
1400 * time to wake up.
1401 */
1402 for (i = 0; i < 3; i++) {
1403 ret = intel_dp_aux_native_write_1(intel_dp,
1404 DP_SET_POWER,
1405 DP_SET_POWER_D0);
1406 if (ret == 1)
1407 break;
1408 msleep(1);
1409 }
1410 }
1411}
1412
19d8fe15
DV		 1413static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1414 enum pipe *pipe)
d240f20f 1415{
19d8fe15 1416 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1417 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1418 struct drm_device *dev = encoder->base.dev;
1419 struct drm_i915_private *dev_priv = dev->dev_private;
1420 u32 tmp = I915_READ(intel_dp->output_reg);
1421
1422 if (!(tmp & DP_PORT_EN))
1423 return false;
1424
bc7d38a4 1425 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1426 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1427 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1428 *pipe = PORT_TO_PIPE(tmp);
1429 } else {
1430 u32 trans_sel;
1431 u32 trans_dp;
1432 int i;
1433
1434 switch (intel_dp->output_reg) {
1435 case PCH_DP_B:
1436 trans_sel = TRANS_DP_PORT_SEL_B;
1437 break;
1438 case PCH_DP_C:
1439 trans_sel = TRANS_DP_PORT_SEL_C;
1440 break;
1441 case PCH_DP_D:
1442 trans_sel = TRANS_DP_PORT_SEL_D;
1443 break;
1444 default:
1445 return true;
1446 }
1447
1448 for_each_pipe(i) {
1449 trans_dp = I915_READ(TRANS_DP_CTL(i));
1450 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1451 *pipe = i;
1452 return true;
1453 }
1454 }
19d8fe15 1455
4a0833ec
DV		 1456 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1457 intel_dp->output_reg);
1458 }
d240f20f 1459
19d8fe15
DV		 1460 return true;
1461}
d240f20f 1462
045ac3b5
JB		 1463static void intel_dp_get_config(struct intel_encoder *encoder,
1464 struct intel_crtc_config *pipe_config)
1465{
1466 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1467 u32 tmp, flags = 0;
63000ef6
XZ		 1468 struct drm_device *dev = encoder->base.dev;
1469 struct drm_i915_private *dev_priv = dev->dev_private;
1470 enum port port = dp_to_dig_port(intel_dp)->port;
1471 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1472 int dotclock;
045ac3b5 1473
63000ef6
XZ		 1474 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1475 tmp = I915_READ(intel_dp->output_reg);
1476 if (tmp & DP_SYNC_HS_HIGH)
1477 flags |= DRM_MODE_FLAG_PHSYNC;
1478 else
1479 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1480
63000ef6
XZ		 1481 if (tmp & DP_SYNC_VS_HIGH)
1482 flags |= DRM_MODE_FLAG_PVSYNC;
1483 else
1484 flags |= DRM_MODE_FLAG_NVSYNC;
1485 } else {
1486 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1487 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1488 flags |= DRM_MODE_FLAG_PHSYNC;
1489 else
1490 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1491
63000ef6
XZ		 1492 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1493 flags |= DRM_MODE_FLAG_PVSYNC;
1494 else
1495 flags |= DRM_MODE_FLAG_NVSYNC;
1496 }
045ac3b5
JB		 1497
1498 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1499
eb14cb74
VS		 1500 pipe_config->has_dp_encoder = true;
1501
1502 intel_dp_get_m_n(crtc, pipe_config);
1503
18442d08 1504 if (port == PORT_A) {
f1f644dc
JB		 1505 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1506 pipe_config->port_clock = 162000;
1507 else
1508 pipe_config->port_clock = 270000;
1509 }
18442d08
VS		 1510
1511 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1512 &pipe_config->dp_m_n);
1513
1514 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1515 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1516
241bfc38 1517 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1518
c6cd2ee2
JN		 1519 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1520 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1521 /*
1522 * This is a big fat ugly hack.
1523 *
1524 * Some machines in UEFI boot mode provide us a VBT that has 18
1525 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1526 * unknown we fail to light up. Yet the same BIOS boots up with
1527 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1528 * max, not what it tells us to use.
1529 *
1530 * Note: This will still be broken if the eDP panel is not lit
1531 * up by the BIOS, and thus we can't get the mode at module
1532 * load.
1533 */
1534 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1535 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1536 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1537 }
045ac3b5
JB		 1538}
1539
a031d709 1540static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1541{
a031d709
RV		 1542 struct drm_i915_private *dev_priv = dev->dev_private;
1543
1544 return dev_priv->psr.sink_support;
2293bb5c
SK		 1545}
1546
2b28bb1b
RV		 1547static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1548{
1549 struct drm_i915_private *dev_priv = dev->dev_private;
1550
18b5992c 1551 if (!HAS_PSR(dev))
2b28bb1b
RV		 1552 return false;
1553
18b5992c 1554 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1555}
1556
1557static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1558 struct edp_vsc_psr *vsc_psr)
1559{
1560 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1561 struct drm_device *dev = dig_port->base.base.dev;
1562 struct drm_i915_private *dev_priv = dev->dev_private;
1563 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1564 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1565 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1566 uint32_t *data = (uint32_t *) vsc_psr;
1567 unsigned int i;
1568
1569 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1570 the video DIP being updated before program video DIP data buffer
1571 registers for DIP being updated. */
1572 I915_WRITE(ctl_reg, 0);
1573 POSTING_READ(ctl_reg);
1574
1575 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1576 if (i < sizeof(struct edp_vsc_psr))
1577 I915_WRITE(data_reg + i, *data++);
1578 else
1579 I915_WRITE(data_reg + i, 0);
1580 }
1581
1582 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1583 POSTING_READ(ctl_reg);
1584}
1585
1586static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1587{
1588 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1589 struct drm_i915_private *dev_priv = dev->dev_private;
1590 struct edp_vsc_psr psr_vsc;
1591
1592 if (intel_dp->psr_setup_done)
1593 return;
1594
1595 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1596 memset(&psr_vsc, 0, sizeof(psr_vsc));
1597 psr_vsc.sdp_header.HB0 = 0;
1598 psr_vsc.sdp_header.HB1 = 0x7;
1599 psr_vsc.sdp_header.HB2 = 0x2;
1600 psr_vsc.sdp_header.HB3 = 0x8;
1601 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1602
1603 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1604 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1605 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1606
1607 intel_dp->psr_setup_done = true;
1608}
1609
1610static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1611{
1612 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1613 struct drm_i915_private *dev_priv = dev->dev_private;
bc86625a 1614 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
2b28bb1b
RV		 1615 int precharge = 0x3;
1616 int msg_size = 5; /* Header(4) + Message(1) */
1617
1618 /* Enable PSR in sink */
1619 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1620 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1621 DP_PSR_ENABLE &
1622 ~DP_PSR_MAIN_LINK_ACTIVE);
1623 else
1624 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1625 DP_PSR_ENABLE |
1626 DP_PSR_MAIN_LINK_ACTIVE);
1627
1628 /* Setup AUX registers */
18b5992c
BW		 1629 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1630 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1631 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1632 DP_AUX_CH_CTL_TIME_OUT_400us |
1633 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1634 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1635 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1636}
1637
1638static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1639{
1640 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642 uint32_t max_sleep_time = 0x1f;
1643 uint32_t idle_frames = 1;
1644 uint32_t val = 0x0;
ed8546ac 1645 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1646
1647 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1648 val |= EDP_PSR_LINK_STANDBY;
1649 val |= EDP_PSR_TP2_TP3_TIME_0us;
1650 val |= EDP_PSR_TP1_TIME_0us;
1651 val |= EDP_PSR_SKIP_AUX_EXIT;
1652 } else
1653 val |= EDP_PSR_LINK_DISABLE;
1654
18b5992c 1655 I915_WRITE(EDP_PSR_CTL(dev), val |
ed8546ac 1656 IS_BROADWELL(dev) ? 0 : link_entry_time |
2b28bb1b
RV		 1657 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1658 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1659 EDP_PSR_ENABLE);
1660}
1661
3f51e471
RV		 1662static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1663{
1664 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1665 struct drm_device *dev = dig_port->base.base.dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 struct drm_crtc *crtc = dig_port->base.base.crtc;
1668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1669 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1670 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1671
a031d709
RV		 1672 dev_priv->psr.source_ok = false;
1673
18b5992c 1674 if (!HAS_PSR(dev)) {
3f51e471 1675 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1676 return false;
1677 }
1678
1679 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1680 (dig_port->port != PORT_A)) {
1681 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1682 return false;
1683 }
1684
105b7c11
RV		 1685 if (!i915_enable_psr) {
1686 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1687 return false;
1688 }
1689
cd234b0b
CW		 1690 crtc = dig_port->base.base.crtc;
1691 if (crtc == NULL) {
1692 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1693 return false;
1694 }
1695
1696 intel_crtc = to_intel_crtc(crtc);
20ddf665 1697 if (!intel_crtc_active(crtc)) {
3f51e471 1698 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1699 return false;
1700 }
1701
cd234b0b 1702 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1703 if (obj->tiling_mode != I915_TILING_X ||
1704 obj->fence_reg == I915_FENCE_REG_NONE) {
1705 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1706 return false;
1707 }
1708
1709 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1710 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1711 return false;
1712 }
1713
1714 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1715 S3D_ENABLE) {
1716 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1717 return false;
1718 }
1719
ca73b4f0 1720 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1721 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1722 return false;
1723 }
1724
a031d709 1725 dev_priv->psr.source_ok = true;
3f51e471
RV		 1726 return true;
1727}
1728
3d739d92 1729static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1730{
1731 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1732
3f51e471
RV		 1733 if (!intel_edp_psr_match_conditions(intel_dp) ||
1734 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1735 return;
1736
1737 /* Setup PSR once */
1738 intel_edp_psr_setup(intel_dp);
1739
1740 /* Enable PSR on the panel */
1741 intel_edp_psr_enable_sink(intel_dp);
1742
1743 /* Enable PSR on the host */
1744 intel_edp_psr_enable_source(intel_dp);
1745}
1746
3d739d92
RV		 1747void intel_edp_psr_enable(struct intel_dp *intel_dp)
1748{
1749 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1750
1751 if (intel_edp_psr_match_conditions(intel_dp) &&
1752 !intel_edp_is_psr_enabled(dev))
1753 intel_edp_psr_do_enable(intel_dp);
1754}
1755
2b28bb1b
RV		 1756void intel_edp_psr_disable(struct intel_dp *intel_dp)
1757{
1758 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1759 struct drm_i915_private *dev_priv = dev->dev_private;
1760
1761 if (!intel_edp_is_psr_enabled(dev))
1762 return;
1763
18b5992c
BW		 1764 I915_WRITE(EDP_PSR_CTL(dev),
1765 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1766
1767 /* Wait till PSR is idle */
18b5992c 1768 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1769 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1770 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1771}
1772
3d739d92
RV		 1773void intel_edp_psr_update(struct drm_device *dev)
1774{
1775 struct intel_encoder *encoder;
1776 struct intel_dp *intel_dp = NULL;
1777
1778 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1779 if (encoder->type == INTEL_OUTPUT_EDP) {
1780 intel_dp = enc_to_intel_dp(&encoder->base);
1781
a031d709 1782 if (!is_edp_psr(dev))
3d739d92
RV		 1783 return;
1784
1785 if (!intel_edp_psr_match_conditions(intel_dp))
1786 intel_edp_psr_disable(intel_dp);
1787 else
1788 if (!intel_edp_is_psr_enabled(dev))
1789 intel_edp_psr_do_enable(intel_dp);
1790 }
1791}
1792
e8cb4558 1793static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1794{
e8cb4558 1795 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1796 enum port port = dp_to_dig_port(intel_dp)->port;
1797 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1798
1799 /* Make sure the panel is off before trying to change the mode. But also
1800 * ensure that we have vdd while we switch off the panel. */
21264c63 1801 ironlake_edp_backlight_off(intel_dp);
fdbc3b1f 1802 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
35a38556 1803 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1804
1805 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1806 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1807 intel_dp_link_down(intel_dp);
d240f20f
JB		 1808}
1809
2bd2ad64 1810static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1811{
2bd2ad64 1812 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1813 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1814 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1815
982a3866 1816 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1817 intel_dp_link_down(intel_dp);
b2634017
JB		 1818 if (!IS_VALLEYVIEW(dev))
1819 ironlake_edp_pll_off(intel_dp);
3739850b 1820 }
2bd2ad64
DV		 1821}
1822
e8cb4558 1823static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1824{
e8cb4558
DV		 1825 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1826 struct drm_device *dev = encoder->base.dev;
1827 struct drm_i915_private *dev_priv = dev->dev_private;
1828 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1829
0c33d8d7
DV		 1830 if (WARN_ON(dp_reg & DP_PORT_EN))
1831 return;
5d613501 1832
97af61f5 1833 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1834 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1835 intel_dp_start_link_train(intel_dp);
97af61f5 1836 ironlake_edp_panel_on(intel_dp);
bd943159 1837 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1838 intel_dp_complete_link_train(intel_dp);
3ab9c637 1839 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1840}
89b667f8 1841
ecff4f3b
JN		 1842static void g4x_enable_dp(struct intel_encoder *encoder)
1843{
828f5c6e
JN		 1844 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1845
ecff4f3b 1846 intel_enable_dp(encoder);
f01eca2e 1847 ironlake_edp_backlight_on(intel_dp);
ab1f90f9 1848}
89b667f8 1849
ab1f90f9
JN		 1850static void vlv_enable_dp(struct intel_encoder *encoder)
1851{
828f5c6e
JN		 1852 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1853
1854 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1855}
1856
ecff4f3b 1857static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1858{
1859 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1860 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1861
1862 if (dport->port == PORT_A)
1863 ironlake_edp_pll_on(intel_dp);
1864}
1865
1866static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1867{
2bd2ad64 1868 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1869 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1870 struct drm_device *dev = encoder->base.dev;
89b667f8 1871 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1872 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1873 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1874 int pipe = intel_crtc->pipe;
bf13e81b 1875 struct edp_power_seq power_seq;
ab1f90f9 1876 u32 val;
a4fc5ed6 1877
ab1f90f9 1878 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1879
ab3c759a 1880 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1881 val = 0;
1882 if (pipe)
1883 val |= (1<<21);
1884 else
1885 val &= ~(1<<21);
1886 val |= 0x001000c4;
ab3c759a
CML		 1887 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1888 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1889 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1890
ab1f90f9
JN		 1891 mutex_unlock(&dev_priv->dpio_lock);
1892
bf13e81b
JN		 1893 /* init power sequencer on this pipe and port */
1894 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1895 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1896 &power_seq);
1897
ab1f90f9
JN		 1898 intel_enable_dp(encoder);
1899
e4607fcf 1900 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1901}
1902
ecff4f3b 1903static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1904{
1905 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1906 struct drm_device *dev = encoder->base.dev;
1907 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1908 struct intel_crtc *intel_crtc =
1909 to_intel_crtc(encoder->base.crtc);
e4607fcf 1910 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1911 int pipe = intel_crtc->pipe;
89b667f8 1912
89b667f8 1913 /* Program Tx lane resets to default */
0980a60f 1914 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 1915 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1916 DPIO_PCS_TX_LANE2_RESET |
1917 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1918 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1919 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1920 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1921 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1922 DPIO_PCS_CLK_SOFT_RESET);
1923
1924 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1925 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1926 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1927 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 1928 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1929}
1930
1931/*
df0c237d
JB		 1932 * Native read with retry for link status and receiver capability reads for
1933 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1934 */
1935static bool
df0c237d
JB		 1936intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1937 uint8_t *recv, int recv_bytes)
a4fc5ed6 1938{
61da5fab
JB		 1939 int ret, i;
1940
df0c237d
JB		 1941 /*
1942 * Sinks are *supposed* to come up within 1ms from an off state,
1943 * but we're also supposed to retry 3 times per the spec.
1944 */
61da5fab 1945 for (i = 0; i < 3; i++) {
df0c237d
JB		 1946 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1947 recv_bytes);
1948 if (ret == recv_bytes)
61da5fab
JB		 1949 return true;
1950 msleep(1);
1951 }
a4fc5ed6 1952
61da5fab 1953 return false;
a4fc5ed6
KP		 1954}
1955
1956/*
1957 * Fetch AUX CH registers 0x202 - 0x207 which contain
1958 * link status information
1959 */
1960static bool
93f62dad 1961intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1962{
df0c237d
JB		 1963 return intel_dp_aux_native_read_retry(intel_dp,
1964 DP_LANE0_1_STATUS,
93f62dad 1965 link_status,
df0c237d 1966 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1967}
1968
a4fc5ed6
KP		 1969/*
1970 * These are source-specific values; current Intel hardware supports
1971 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1972 */
a4fc5ed6
KP		 1973
1974static uint8_t
1a2eb460 1975intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1976{
30add22d 1977 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1978 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1979
8f93f4f1 1980 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 1981 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1982 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1983 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1984 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1985 return DP_TRAIN_VOLTAGE_SWING_1200;
1986 else
1987 return DP_TRAIN_VOLTAGE_SWING_800;
1988}
1989
1990static uint8_t
1991intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1992{
30add22d 1993 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1994 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1995
8f93f4f1
PZ		 1996 if (IS_BROADWELL(dev)) {
1997 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1998 case DP_TRAIN_VOLTAGE_SWING_400:
1999 case DP_TRAIN_VOLTAGE_SWING_600:
2000 return DP_TRAIN_PRE_EMPHASIS_6;
2001 case DP_TRAIN_VOLTAGE_SWING_800:
2002 return DP_TRAIN_PRE_EMPHASIS_3_5;
2003 case DP_TRAIN_VOLTAGE_SWING_1200:
2004 default:
2005 return DP_TRAIN_PRE_EMPHASIS_0;
2006 }
2007 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2008 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2009 case DP_TRAIN_VOLTAGE_SWING_400:
2010 return DP_TRAIN_PRE_EMPHASIS_9_5;
2011 case DP_TRAIN_VOLTAGE_SWING_600:
2012 return DP_TRAIN_PRE_EMPHASIS_6;
2013 case DP_TRAIN_VOLTAGE_SWING_800:
2014 return DP_TRAIN_PRE_EMPHASIS_3_5;
2015 case DP_TRAIN_VOLTAGE_SWING_1200:
2016 default:
2017 return DP_TRAIN_PRE_EMPHASIS_0;
2018 }
e2fa6fba
P		 2019 } else if (IS_VALLEYVIEW(dev)) {
2020 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2021 case DP_TRAIN_VOLTAGE_SWING_400:
2022 return DP_TRAIN_PRE_EMPHASIS_9_5;
2023 case DP_TRAIN_VOLTAGE_SWING_600:
2024 return DP_TRAIN_PRE_EMPHASIS_6;
2025 case DP_TRAIN_VOLTAGE_SWING_800:
2026 return DP_TRAIN_PRE_EMPHASIS_3_5;
2027 case DP_TRAIN_VOLTAGE_SWING_1200:
2028 default:
2029 return DP_TRAIN_PRE_EMPHASIS_0;
2030 }
bc7d38a4 2031 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2032 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2033 case DP_TRAIN_VOLTAGE_SWING_400:
2034 return DP_TRAIN_PRE_EMPHASIS_6;
2035 case DP_TRAIN_VOLTAGE_SWING_600:
2036 case DP_TRAIN_VOLTAGE_SWING_800:
2037 return DP_TRAIN_PRE_EMPHASIS_3_5;
2038 default:
2039 return DP_TRAIN_PRE_EMPHASIS_0;
2040 }
2041 } else {
2042 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2043 case DP_TRAIN_VOLTAGE_SWING_400:
2044 return DP_TRAIN_PRE_EMPHASIS_6;
2045 case DP_TRAIN_VOLTAGE_SWING_600:
2046 return DP_TRAIN_PRE_EMPHASIS_6;
2047 case DP_TRAIN_VOLTAGE_SWING_800:
2048 return DP_TRAIN_PRE_EMPHASIS_3_5;
2049 case DP_TRAIN_VOLTAGE_SWING_1200:
2050 default:
2051 return DP_TRAIN_PRE_EMPHASIS_0;
2052 }
a4fc5ed6
KP		 2053 }
2054}
2055
e2fa6fba
P		 2056static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2057{
2058 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2059 struct drm_i915_private *dev_priv = dev->dev_private;
2060 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2061 struct intel_crtc *intel_crtc =
2062 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2063 unsigned long demph_reg_value, preemph_reg_value,
2064 uniqtranscale_reg_value;
2065 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2066 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2067 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2068
2069 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2070 case DP_TRAIN_PRE_EMPHASIS_0:
2071 preemph_reg_value = 0x0004000;
2072 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2073 case DP_TRAIN_VOLTAGE_SWING_400:
2074 demph_reg_value = 0x2B405555;
2075 uniqtranscale_reg_value = 0x552AB83A;
2076 break;
2077 case DP_TRAIN_VOLTAGE_SWING_600:
2078 demph_reg_value = 0x2B404040;
2079 uniqtranscale_reg_value = 0x5548B83A;
2080 break;
2081 case DP_TRAIN_VOLTAGE_SWING_800:
2082 demph_reg_value = 0x2B245555;
2083 uniqtranscale_reg_value = 0x5560B83A;
2084 break;
2085 case DP_TRAIN_VOLTAGE_SWING_1200:
2086 demph_reg_value = 0x2B405555;
2087 uniqtranscale_reg_value = 0x5598DA3A;
2088 break;
2089 default:
2090 return 0;
2091 }
2092 break;
2093 case DP_TRAIN_PRE_EMPHASIS_3_5:
2094 preemph_reg_value = 0x0002000;
2095 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2096 case DP_TRAIN_VOLTAGE_SWING_400:
2097 demph_reg_value = 0x2B404040;
2098 uniqtranscale_reg_value = 0x5552B83A;
2099 break;
2100 case DP_TRAIN_VOLTAGE_SWING_600:
2101 demph_reg_value = 0x2B404848;
2102 uniqtranscale_reg_value = 0x5580B83A;
2103 break;
2104 case DP_TRAIN_VOLTAGE_SWING_800:
2105 demph_reg_value = 0x2B404040;
2106 uniqtranscale_reg_value = 0x55ADDA3A;
2107 break;
2108 default:
2109 return 0;
2110 }
2111 break;
2112 case DP_TRAIN_PRE_EMPHASIS_6:
2113 preemph_reg_value = 0x0000000;
2114 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2115 case DP_TRAIN_VOLTAGE_SWING_400:
2116 demph_reg_value = 0x2B305555;
2117 uniqtranscale_reg_value = 0x5570B83A;
2118 break;
2119 case DP_TRAIN_VOLTAGE_SWING_600:
2120 demph_reg_value = 0x2B2B4040;
2121 uniqtranscale_reg_value = 0x55ADDA3A;
2122 break;
2123 default:
2124 return 0;
2125 }
2126 break;
2127 case DP_TRAIN_PRE_EMPHASIS_9_5:
2128 preemph_reg_value = 0x0006000;
2129 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2130 case DP_TRAIN_VOLTAGE_SWING_400:
2131 demph_reg_value = 0x1B405555;
2132 uniqtranscale_reg_value = 0x55ADDA3A;
2133 break;
2134 default:
2135 return 0;
2136 }
2137 break;
2138 default:
2139 return 0;
2140 }
2141
0980a60f 2142 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2143 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2144 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2145 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2146 uniqtranscale_reg_value);
ab3c759a
CML		 2147 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2148 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2149 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2150 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2151 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2152
2153 return 0;
2154}
2155
a4fc5ed6 2156static void
0301b3ac
JN		 2157intel_get_adjust_train(struct intel_dp *intel_dp,
2158 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2159{
2160 uint8_t v = 0;
2161 uint8_t p = 0;
2162 int lane;
1a2eb460
KP		 2163 uint8_t voltage_max;
2164 uint8_t preemph_max;
a4fc5ed6 2165
33a34e4e 2166 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2167 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2168 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2169
2170 if (this_v > v)
2171 v = this_v;
2172 if (this_p > p)
2173 p = this_p;
2174 }
2175
1a2eb460 2176 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2177 if (v >= voltage_max)
2178 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2179
1a2eb460
KP		 2180 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2181 if (p >= preemph_max)
2182 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2183
2184 for (lane = 0; lane < 4; lane++)
33a34e4e 2185 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2186}
2187
2188static uint32_t
f0a3424e 2189intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2190{
3cf2efb1 2191 uint32_t signal_levels = 0;
a4fc5ed6 2192
3cf2efb1 2193 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2194 case DP_TRAIN_VOLTAGE_SWING_400:
2195 default:
2196 signal_levels |= DP_VOLTAGE_0_4;
2197 break;
2198 case DP_TRAIN_VOLTAGE_SWING_600:
2199 signal_levels |= DP_VOLTAGE_0_6;
2200 break;
2201 case DP_TRAIN_VOLTAGE_SWING_800:
2202 signal_levels |= DP_VOLTAGE_0_8;
2203 break;
2204 case DP_TRAIN_VOLTAGE_SWING_1200:
2205 signal_levels |= DP_VOLTAGE_1_2;
2206 break;
2207 }
3cf2efb1 2208 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2209 case DP_TRAIN_PRE_EMPHASIS_0:
2210 default:
2211 signal_levels |= DP_PRE_EMPHASIS_0;
2212 break;
2213 case DP_TRAIN_PRE_EMPHASIS_3_5:
2214 signal_levels |= DP_PRE_EMPHASIS_3_5;
2215 break;
2216 case DP_TRAIN_PRE_EMPHASIS_6:
2217 signal_levels |= DP_PRE_EMPHASIS_6;
2218 break;
2219 case DP_TRAIN_PRE_EMPHASIS_9_5:
2220 signal_levels |= DP_PRE_EMPHASIS_9_5;
2221 break;
2222 }
2223 return signal_levels;
2224}
2225
e3421a18
ZW		 2226/* Gen6's DP voltage swing and pre-emphasis control */
2227static uint32_t
2228intel_gen6_edp_signal_levels(uint8_t train_set)
2229{
3c5a62b5
YL		 2230 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2231 DP_TRAIN_PRE_EMPHASIS_MASK);
2232 switch (signal_levels) {
e3421a18 2233 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2234 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2235 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2236 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2237 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2238 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2239 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2240 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2241 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2242 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2243 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2244 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2245 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2246 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2247 default:
3c5a62b5
YL		 2248 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2249 "0x%x\n", signal_levels);
2250 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2251 }
2252}
2253
1a2eb460
KP		 2254/* Gen7's DP voltage swing and pre-emphasis control */
2255static uint32_t
2256intel_gen7_edp_signal_levels(uint8_t train_set)
2257{
2258 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2259 DP_TRAIN_PRE_EMPHASIS_MASK);
2260 switch (signal_levels) {
2261 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2262 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2263 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2264 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2265 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2266 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2267
2268 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2269 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2270 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2271 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2272
2273 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2274 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2275 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2276 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2277
2278 default:
2279 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2280 "0x%x\n", signal_levels);
2281 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2282 }
2283}
2284
d6c0d722
PZ		 2285/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2286static uint32_t
f0a3424e 2287intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2288{
d6c0d722
PZ		 2289 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2290 DP_TRAIN_PRE_EMPHASIS_MASK);
2291 switch (signal_levels) {
2292 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2293 return DDI_BUF_EMP_400MV_0DB_HSW;
2294 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2295 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2296 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2297 return DDI_BUF_EMP_400MV_6DB_HSW;
2298 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2299 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2300
d6c0d722
PZ		 2301 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2302 return DDI_BUF_EMP_600MV_0DB_HSW;
2303 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2304 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2305 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2306 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2307
d6c0d722
PZ		 2308 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2309 return DDI_BUF_EMP_800MV_0DB_HSW;
2310 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2311 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2312 default:
2313 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2314 "0x%x\n", signal_levels);
2315 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2316 }
a4fc5ed6
KP		 2317}
2318
8f93f4f1
PZ		 2319static uint32_t
2320intel_bdw_signal_levels(uint8_t train_set)
2321{
2322 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2323 DP_TRAIN_PRE_EMPHASIS_MASK);
2324 switch (signal_levels) {
2325 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2326 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2327 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2328 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2329 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2330 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2331
2332 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2333 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2334 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2335 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2336 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2337 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2338
2339 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2340 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2341 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2342 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2343
2344 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2345 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2346
2347 default:
2348 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2349 "0x%x\n", signal_levels);
2350 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2351 }
2352}
2353
f0a3424e
PZ		 2354/* Properly updates "DP" with the correct signal levels. */
2355static void
2356intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2357{
2358 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2359 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2360 struct drm_device *dev = intel_dig_port->base.base.dev;
2361 uint32_t signal_levels, mask;
2362 uint8_t train_set = intel_dp->train_set[0];
2363
8f93f4f1
PZ		 2364 if (IS_BROADWELL(dev)) {
2365 signal_levels = intel_bdw_signal_levels(train_set);
2366 mask = DDI_BUF_EMP_MASK;
2367 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2368 signal_levels = intel_hsw_signal_levels(train_set);
2369 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2370 } else if (IS_VALLEYVIEW(dev)) {
2371 signal_levels = intel_vlv_signal_levels(intel_dp);
2372 mask = 0;
bc7d38a4 2373 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2374 signal_levels = intel_gen7_edp_signal_levels(train_set);
2375 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2376 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2377 signal_levels = intel_gen6_edp_signal_levels(train_set);
2378 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2379 } else {
2380 signal_levels = intel_gen4_signal_levels(train_set);
2381 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2382 }
2383
2384 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2385
2386 *DP = (*DP & ~mask) | signal_levels;
2387}
2388
a4fc5ed6 2389static bool
ea5b213a 2390intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2391 uint32_t *DP,
58e10eb9 2392 uint8_t dp_train_pat)
a4fc5ed6 2393{
174edf1f
PZ		 2394 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2395 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2396 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2397 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2398 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2399 int ret, len;
a4fc5ed6 2400
22b8bf17 2401 if (HAS_DDI(dev)) {
3ab9c637 2402 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2403
2404 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2405 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2406 else
2407 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2408
2409 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2410 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2411 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2412 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2413
2414 break;
2415 case DP_TRAINING_PATTERN_1:
2416 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2417 break;
2418 case DP_TRAINING_PATTERN_2:
2419 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2420 break;
2421 case DP_TRAINING_PATTERN_3:
2422 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2423 break;
2424 }
174edf1f 2425 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2426
bc7d38a4 2427 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2428 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2429
2430 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2431 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2432 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2433 break;
2434 case DP_TRAINING_PATTERN_1:
70aff66c 2435 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2436 break;
2437 case DP_TRAINING_PATTERN_2:
70aff66c 2438 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2439 break;
2440 case DP_TRAINING_PATTERN_3:
2441 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2442 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2443 break;
2444 }
2445
2446 } else {
70aff66c 2447 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2448
2449 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2450 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2451 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2452 break;
2453 case DP_TRAINING_PATTERN_1:
70aff66c 2454 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2455 break;
2456 case DP_TRAINING_PATTERN_2:
70aff66c 2457 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2458 break;
2459 case DP_TRAINING_PATTERN_3:
2460 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2461 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2462 break;
2463 }
2464 }
2465
70aff66c 2466 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2467 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2468
2cdfe6c8
JN		 2469 buf[0] = dp_train_pat;
2470 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2471 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2472 /* don't write DP_TRAINING_LANEx_SET on disable */
2473 len = 1;
2474 } else {
2475 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2476 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2477 len = intel_dp->lane_count + 1;
47ea7542 2478 }
a4fc5ed6 2479
2cdfe6c8
JN		 2480 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2481 buf, len);
2482
2483 return ret == len;
a4fc5ed6
KP		 2484}
2485
70aff66c
JN		 2486static bool
2487intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2488 uint8_t dp_train_pat)
2489{
953d22e8 2490 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2491 intel_dp_set_signal_levels(intel_dp, DP);
2492 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2493}
2494
2495static bool
2496intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2497 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2498{
2499 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2500 struct drm_device *dev = intel_dig_port->base.base.dev;
2501 struct drm_i915_private *dev_priv = dev->dev_private;
2502 int ret;
2503
2504 intel_get_adjust_train(intel_dp, link_status);
2505 intel_dp_set_signal_levels(intel_dp, DP);
2506
2507 I915_WRITE(intel_dp->output_reg, *DP);
2508 POSTING_READ(intel_dp->output_reg);
2509
2510 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2511 intel_dp->train_set,
2512 intel_dp->lane_count);
2513
2514 return ret == intel_dp->lane_count;
2515}
2516
3ab9c637
ID		 2517static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2518{
2519 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2520 struct drm_device *dev = intel_dig_port->base.base.dev;
2521 struct drm_i915_private *dev_priv = dev->dev_private;
2522 enum port port = intel_dig_port->port;
2523 uint32_t val;
2524
2525 if (!HAS_DDI(dev))
2526 return;
2527
2528 val = I915_READ(DP_TP_CTL(port));
2529 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2530 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2531 I915_WRITE(DP_TP_CTL(port), val);
2532
2533 /*
2534 * On PORT_A we can have only eDP in SST mode. There the only reason
2535 * we need to set idle transmission mode is to work around a HW issue
2536 * where we enable the pipe while not in idle link-training mode.
2537 * In this case there is requirement to wait for a minimum number of
2538 * idle patterns to be sent.
2539 */
2540 if (port == PORT_A)
2541 return;
2542
2543 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2544 1))
2545 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2546}
2547
33a34e4e 2548/* Enable corresponding port and start training pattern 1 */
c19b0669 2549void
33a34e4e 2550intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2551{
da63a9f2 2552 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2553 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2554 int i;
2555 uint8_t voltage;
cdb0e95b 2556 int voltage_tries, loop_tries;
ea5b213a 2557 uint32_t DP = intel_dp->DP;
6aba5b6c 2558 uint8_t link_config[2];
a4fc5ed6 2559
affa9354 2560 if (HAS_DDI(dev))
c19b0669
PZ		 2561 intel_ddi_prepare_link_retrain(encoder);
2562
3cf2efb1 2563 /* Write the link configuration data */
6aba5b6c
JN		 2564 link_config[0] = intel_dp->link_bw;
2565 link_config[1] = intel_dp->lane_count;
2566 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2567 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2568 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2569
2570 link_config[0] = 0;
2571 link_config[1] = DP_SET_ANSI_8B10B;
2572 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2573
2574 DP |= DP_PORT_EN;
1a2eb460 2575
70aff66c
JN		 2576 /* clock recovery */
2577 if (!intel_dp_reset_link_train(intel_dp, &DP,
2578 DP_TRAINING_PATTERN_1 |
2579 DP_LINK_SCRAMBLING_DISABLE)) {
2580 DRM_ERROR("failed to enable link training\n");
2581 return;
2582 }
2583
a4fc5ed6 2584 voltage = 0xff;
cdb0e95b
KP		 2585 voltage_tries = 0;
2586 loop_tries = 0;
a4fc5ed6 2587 for (;;) {
70aff66c 2588 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2589
a7c9655f 2590 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2591 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2592 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2593 break;
93f62dad 2594 }
a4fc5ed6 2595
01916270 2596 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2597 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2598 break;
2599 }
2600
2601 /* Check to see if we've tried the max voltage */
2602 for (i = 0; i < intel_dp->lane_count; i++)
2603 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2604 break;
3b4f819d 2605 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2606 ++loop_tries;
2607 if (loop_tries == 5) {
3def84b3 2608 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2609 break;
2610 }
70aff66c
JN		 2611 intel_dp_reset_link_train(intel_dp, &DP,
2612 DP_TRAINING_PATTERN_1 |
2613 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2614 voltage_tries = 0;
2615 continue;
2616 }
a4fc5ed6 2617
3cf2efb1 2618 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2619 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2620 ++voltage_tries;
b06fbda3 2621 if (voltage_tries == 5) {
3def84b3 2622 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2623 break;
2624 }
2625 } else
2626 voltage_tries = 0;
2627 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2628
70aff66c
JN		 2629 /* Update training set as requested by target */
2630 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2631 DRM_ERROR("failed to update link training\n");
2632 break;
2633 }
a4fc5ed6
KP		 2634 }
2635
33a34e4e
JB		 2636 intel_dp->DP = DP;
2637}
2638
c19b0669 2639void
33a34e4e
JB		 2640intel_dp_complete_link_train(struct intel_dp *intel_dp)
2641{
33a34e4e 2642 bool channel_eq = false;
37f80975 2643 int tries, cr_tries;
33a34e4e
JB		 2644 uint32_t DP = intel_dp->DP;
2645
a4fc5ed6 2646 /* channel equalization */
70aff66c
JN		 2647 if (!intel_dp_set_link_train(intel_dp, &DP,
2648 DP_TRAINING_PATTERN_2 |
2649 DP_LINK_SCRAMBLING_DISABLE)) {
2650 DRM_ERROR("failed to start channel equalization\n");
2651 return;
2652 }
2653
a4fc5ed6 2654 tries = 0;
37f80975 2655 cr_tries = 0;
a4fc5ed6
KP		 2656 channel_eq = false;
2657 for (;;) {
70aff66c 2658 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2659
37f80975
JB		 2660 if (cr_tries > 5) {
2661 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2662 break;
2663 }
2664
a7c9655f 2665 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2666 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2667 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2668 break;
70aff66c 2669 }
a4fc5ed6 2670
37f80975 2671 /* Make sure clock is still ok */
01916270 2672 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2673 intel_dp_start_link_train(intel_dp);
70aff66c
JN		 2674 intel_dp_set_link_train(intel_dp, &DP,
2675 DP_TRAINING_PATTERN_2 |
2676 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2677 cr_tries++;
2678 continue;
2679 }
2680
1ffdff13 2681 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2682 channel_eq = true;
2683 break;
2684 }
a4fc5ed6 2685
37f80975
JB		 2686 /* Try 5 times, then try clock recovery if that fails */
2687 if (tries > 5) {
2688 intel_dp_link_down(intel_dp);
2689 intel_dp_start_link_train(intel_dp);
70aff66c
JN		 2690 intel_dp_set_link_train(intel_dp, &DP,
2691 DP_TRAINING_PATTERN_2 |
2692 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2693 tries = 0;
2694 cr_tries++;
2695 continue;
2696 }
a4fc5ed6 2697
70aff66c
JN		 2698 /* Update training set as requested by target */
2699 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2700 DRM_ERROR("failed to update link training\n");
2701 break;
2702 }
3cf2efb1 2703 ++tries;
869184a6 2704 }
3cf2efb1 2705
3ab9c637
ID		 2706 intel_dp_set_idle_link_train(intel_dp);
2707
2708 intel_dp->DP = DP;
2709
d6c0d722 2710 if (channel_eq)
07f42258 2711 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2712
3ab9c637
ID		 2713}
2714
2715void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2716{
70aff66c 2717 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2718 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2719}
2720
2721static void
ea5b213a 2722intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2723{
da63a9f2 2724 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2725 enum port port = intel_dig_port->port;
da63a9f2 2726 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2727 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2728 struct intel_crtc *intel_crtc =
2729 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2730 uint32_t DP = intel_dp->DP;
a4fc5ed6 2731
c19b0669
PZ		 2732 /*
2733 * DDI code has a strict mode set sequence and we should try to respect
2734 * it, otherwise we might hang the machine in many different ways. So we
2735 * really should be disabling the port only on a complete crtc_disable
2736 * sequence. This function is just called under two conditions on DDI
2737 * code:
2738 * - Link train failed while doing crtc_enable, and on this case we
2739 * really should respect the mode set sequence and wait for a
2740 * crtc_disable.
2741 * - Someone turned the monitor off and intel_dp_check_link_status
2742 * called us. We don't need to disable the whole port on this case, so
2743 * when someone turns the monitor on again,
2744 * intel_ddi_prepare_link_retrain will take care of redoing the link
2745 * train.
2746 */
affa9354 2747 if (HAS_DDI(dev))
c19b0669
PZ		 2748 return;
2749
0c33d8d7 2750 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2751 return;
2752
28c97730 2753 DRM_DEBUG_KMS("\n");
32f9d658 2754
bc7d38a4 2755 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2756 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2757 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2758 } else {
2759 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2760 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2761 }
fe255d00 2762 POSTING_READ(intel_dp->output_reg);
5eb08b69 2763
ab527efc
DV		 2764 /* We don't really know why we're doing this */
2765 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2766
493a7081 2767 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2768 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2769 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2770
5bddd17f
EA		 2771 /* Hardware workaround: leaving our transcoder select
2772 * set to transcoder B while it's off will prevent the
2773 * corresponding HDMI output on transcoder A.
2774 *
2775 * Combine this with another hardware workaround:
2776 * transcoder select bit can only be cleared while the
2777 * port is enabled.
2778 */
2779 DP &= ~DP_PIPEB_SELECT;
2780 I915_WRITE(intel_dp->output_reg, DP);
2781
2782 /* Changes to enable or select take place the vblank
2783 * after being written.
2784 */
ff50afe9
DV		 2785 if (WARN_ON(crtc == NULL)) {
2786 /* We should never try to disable a port without a crtc
2787 * attached. For paranoia keep the code around for a
2788 * bit. */
31acbcc4
CW		 2789 POSTING_READ(intel_dp->output_reg);
2790 msleep(50);
2791 } else
ab527efc 2792 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2793 }
2794
832afda6 2795 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2796 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2797 POSTING_READ(intel_dp->output_reg);
f01eca2e 2798 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2799}
2800
26d61aad
KP		 2801static bool
2802intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2803{
a031d709
RV		 2804 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2805 struct drm_device *dev = dig_port->base.base.dev;
2806 struct drm_i915_private *dev_priv = dev->dev_private;
2807
577c7a50
DL		 2808 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2809
92fd8fd1 2810 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2811 sizeof(intel_dp->dpcd)) == 0)
2812 return false; /* aux transfer failed */
92fd8fd1 2813
577c7a50
DL		 2814 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2815 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2816 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2817
edb39244
AJ		 2818 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2819 return false; /* DPCD not present */
2820
2293bb5c
SK		 2821 /* Check if the panel supports PSR */
2822 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939
JN		 2823 if (is_edp(intel_dp)) {
2824 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2825 intel_dp->psr_dpcd,
2826 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2827 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2828 dev_priv->psr.sink_support = true;
50003939 2829 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2830 }
50003939
JN		 2831 }
2832
edb39244
AJ		 2833 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2834 DP_DWN_STRM_PORT_PRESENT))
2835 return true; /* native DP sink */
2836
2837 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2838 return true; /* no per-port downstream info */
2839
2840 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2841 intel_dp->downstream_ports,
2842 DP_MAX_DOWNSTREAM_PORTS) == 0)
2843 return false; /* downstream port status fetch failed */
2844
2845 return true;
92fd8fd1
KP		 2846}
2847
0d198328
AJ		 2848static void
2849intel_dp_probe_oui(struct intel_dp *intel_dp)
2850{
2851 u8 buf[3];
2852
2853 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2854 return;
2855
351cfc34
DV		 2856 ironlake_edp_panel_vdd_on(intel_dp);
2857
0d198328
AJ		 2858 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2859 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2860 buf[0], buf[1], buf[2]);
2861
2862 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2863 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2864 buf[0], buf[1], buf[2]);
351cfc34
DV		 2865
2866 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2867}
2868
a60f0e38
JB		 2869static bool
2870intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2871{
2872 int ret;
2873
2874 ret = intel_dp_aux_native_read_retry(intel_dp,
2875 DP_DEVICE_SERVICE_IRQ_VECTOR,
2876 sink_irq_vector, 1);
2877 if (!ret)
2878 return false;
2879
2880 return true;
2881}
2882
2883static void
2884intel_dp_handle_test_request(struct intel_dp *intel_dp)
2885{
2886 /* NAK by default */
9324cf7f 2887 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2888}
2889
a4fc5ed6
KP		 2890/*
2891 * According to DP spec
2892 * 5.1.2:
2893 * 1. Read DPCD
2894 * 2. Configure link according to Receiver Capabilities
2895 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2896 * 4. Check link status on receipt of hot-plug interrupt
2897 */
2898
00c09d70 2899void
ea5b213a 2900intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2901{
da63a9f2 2902 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2903 u8 sink_irq_vector;
93f62dad 2904 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2905
da63a9f2 2906 if (!intel_encoder->connectors_active)
d2b996ac 2907 return;
59cd09e1 2908
da63a9f2 2909 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2910 return;
2911
92fd8fd1 2912 /* Try to read receiver status if the link appears to be up */
93f62dad 2913 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 2914 return;
2915 }
2916
92fd8fd1 2917 /* Now read the DPCD to see if it's actually running */
26d61aad 2918 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2919 return;
2920 }
2921
a60f0e38
JB		 2922 /* Try to read the source of the interrupt */
2923 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2924 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2925 /* Clear interrupt source */
2926 intel_dp_aux_native_write_1(intel_dp,
2927 DP_DEVICE_SERVICE_IRQ_VECTOR,
2928 sink_irq_vector);
2929
2930 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2931 intel_dp_handle_test_request(intel_dp);
2932 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2933 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2934 }
2935
1ffdff13 2936 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2937 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2938 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2939 intel_dp_start_link_train(intel_dp);
2940 intel_dp_complete_link_train(intel_dp);
3ab9c637 2941 intel_dp_stop_link_train(intel_dp);
33a34e4e 2942 }
a4fc5ed6 2943}
a4fc5ed6 2944
caf9ab24 2945/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2946static enum drm_connector_status
26d61aad 2947intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2948{
caf9ab24 2949 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 2950 uint8_t type;
2951
2952 if (!intel_dp_get_dpcd(intel_dp))
2953 return connector_status_disconnected;
2954
2955 /* if there's no downstream port, we're done */
2956 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2957 return connector_status_connected;
caf9ab24
AJ		 2958
2959 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 2960 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2961 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 2962 uint8_t reg;
caf9ab24 2963 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2964 &reg, 1))
caf9ab24 2965 return connector_status_unknown;
23235177
AJ		 2966 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2967 : connector_status_disconnected;
caf9ab24
AJ		 2968 }
2969
2970 /* If no HPD, poke DDC gently */
2971 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2972 return connector_status_connected;
caf9ab24
AJ		 2973
2974 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 2975 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2976 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2977 if (type == DP_DS_PORT_TYPE_VGA ||
2978 type == DP_DS_PORT_TYPE_NON_EDID)
2979 return connector_status_unknown;
2980 } else {
2981 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2982 DP_DWN_STRM_PORT_TYPE_MASK;
2983 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2984 type == DP_DWN_STRM_PORT_TYPE_OTHER)
2985 return connector_status_unknown;
2986 }
caf9ab24
AJ		 2987
2988 /* Anything else is out of spec, warn and ignore */
2989 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2990 return connector_status_disconnected;
71ba9000
AJ		 2991}
2992
5eb08b69 2993static enum drm_connector_status
a9756bb5 2994ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2995{
30add22d 2996 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2997 struct drm_i915_private *dev_priv = dev->dev_private;
2998 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2999 enum drm_connector_status status;
3000
fe16d949
CW		 3001 /* Can't disconnect eDP, but you can close the lid... */
3002 if (is_edp(intel_dp)) {
30add22d 3003 status = intel_panel_detect(dev);
fe16d949
CW		 3004 if (status == connector_status_unknown)
3005 status = connector_status_connected;
3006 return status;
3007 }
01cb9ea6 3008
1b469639
DL		 3009 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3010 return connector_status_disconnected;
3011
26d61aad 3012 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3013}
3014
a4fc5ed6 3015static enum drm_connector_status
a9756bb5 3016g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3017{
30add22d 3018 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3019 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3020 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3021 uint32_t bit;
5eb08b69 3022
35aad75f
JB		 3023 /* Can't disconnect eDP, but you can close the lid... */
3024 if (is_edp(intel_dp)) {
3025 enum drm_connector_status status;
3026
3027 status = intel_panel_detect(dev);
3028 if (status == connector_status_unknown)
3029 status = connector_status_connected;
3030 return status;
3031 }
3032
232a6ee9
TP		 3033 if (IS_VALLEYVIEW(dev)) {
3034 switch (intel_dig_port->port) {
3035 case PORT_B:
3036 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3037 break;
3038 case PORT_C:
3039 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3040 break;
3041 case PORT_D:
3042 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3043 break;
3044 default:
3045 return connector_status_unknown;
3046 }
3047 } else {
3048 switch (intel_dig_port->port) {
3049 case PORT_B:
3050 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3051 break;
3052 case PORT_C:
3053 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3054 break;
3055 case PORT_D:
3056 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3057 break;
3058 default:
3059 return connector_status_unknown;
3060 }
a4fc5ed6
KP		 3061 }
3062
10f76a38 3063 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3064 return connector_status_disconnected;
3065
26d61aad 3066 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3067}
3068
8c241fef
KP		 3069static struct edid *
3070intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3071{
9cd300e0 3072 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3073
9cd300e0
JN		 3074 /* use cached edid if we have one */
3075 if (intel_connector->edid) {
9cd300e0
JN		 3076 /* invalid edid */
3077 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3078 return NULL;
3079
55e9edeb 3080 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3081 }
8c241fef 3082
9cd300e0 3083 return drm_get_edid(connector, adapter);
8c241fef
KP		 3084}
3085
3086static int
3087intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3088{
9cd300e0 3089 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3090
9cd300e0
JN		 3091 /* use cached edid if we have one */
3092 if (intel_connector->edid) {
3093 /* invalid edid */
3094 if (IS_ERR(intel_connector->edid))
3095 return 0;
3096
3097 return intel_connector_update_modes(connector,
3098 intel_connector->edid);
d6f24d0f
JB		 3099 }
3100
9cd300e0 3101 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3102}
3103
a9756bb5
ZW		 3104static enum drm_connector_status
3105intel_dp_detect(struct drm_connector *connector, bool force)
3106{
3107 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3108 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3109 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3110 struct drm_device *dev = connector->dev;
c8c8fb33 3111 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5
ZW		 3112 enum drm_connector_status status;
3113 struct edid *edid = NULL;
3114
c8c8fb33
PZ		 3115 intel_runtime_pm_get(dev_priv);
3116
164c8598
CW		 3117 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3118 connector->base.id, drm_get_connector_name(connector));
3119
a9756bb5
ZW		 3120 intel_dp->has_audio = false;
3121
3122 if (HAS_PCH_SPLIT(dev))
3123 status = ironlake_dp_detect(intel_dp);
3124 else
3125 status = g4x_dp_detect(intel_dp);
1b9be9d0 3126
a9756bb5 3127 if (status != connector_status_connected)
c8c8fb33 3128 goto out;
a9756bb5 3129
0d198328
AJ		 3130 intel_dp_probe_oui(intel_dp);
3131
c3e5f67b
DV		 3132 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3133 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3134 } else {
8c241fef 3135 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 3136 if (edid) {
3137 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3138 kfree(edid);
3139 }
a9756bb5
ZW		 3140 }
3141
d63885da
PZ		 3142 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3143 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3144 status = connector_status_connected;
3145
3146out:
3147 intel_runtime_pm_put(dev_priv);
3148 return status;
a4fc5ed6
KP		 3149}
3150
3151static int intel_dp_get_modes(struct drm_connector *connector)
3152{
df0e9248 3153 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 3154 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3155 struct drm_device *dev = connector->dev;
32f9d658 3156 int ret;
a4fc5ed6
KP		 3157
3158 /* We should parse the EDID data and find out if it has an audio sink
3159 */
3160
8c241fef 3161 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 3162 if (ret)
32f9d658
ZW		 3163 return ret;
3164
f8779fda 3165 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3166 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3167 struct drm_display_mode *mode;
dd06f90e
JN		 3168 mode = drm_mode_duplicate(dev,
3169 intel_connector->panel.fixed_mode);
f8779fda 3170 if (mode) {
32f9d658
ZW		 3171 drm_mode_probed_add(connector, mode);
3172 return 1;
3173 }
3174 }
3175 return 0;
a4fc5ed6
KP		 3176}
3177
1aad7ac0
CW		 3178static bool
3179intel_dp_detect_audio(struct drm_connector *connector)
3180{
3181 struct intel_dp *intel_dp = intel_attached_dp(connector);
3182 struct edid *edid;
3183 bool has_audio = false;
3184
8c241fef 3185 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 3186 if (edid) {
3187 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3188 kfree(edid);
3189 }
3190
3191 return has_audio;
3192}
3193
f684960e
CW		 3194static int
3195intel_dp_set_property(struct drm_connector *connector,
3196 struct drm_property *property,
3197 uint64_t val)
3198{
e953fd7b 3199 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3200 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3201 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3202 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3203 int ret;
3204
662595df 3205 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3206 if (ret)
3207 return ret;
3208
3f43c48d 3209 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3210 int i = val;
3211 bool has_audio;
3212
3213 if (i == intel_dp->force_audio)
f684960e
CW		 3214 return 0;
3215
1aad7ac0 3216 intel_dp->force_audio = i;
f684960e 3217
c3e5f67b 3218 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3219 has_audio = intel_dp_detect_audio(connector);
3220 else
c3e5f67b 3221 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3222
3223 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3224 return 0;
3225
1aad7ac0 3226 intel_dp->has_audio = has_audio;
f684960e
CW		 3227 goto done;
3228 }
3229
e953fd7b 3230 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3231 bool old_auto = intel_dp->color_range_auto;
3232 uint32_t old_range = intel_dp->color_range;
3233
55bc60db
VS		 3234 switch (val) {
3235 case INTEL_BROADCAST_RGB_AUTO:
3236 intel_dp->color_range_auto = true;
3237 break;
3238 case INTEL_BROADCAST_RGB_FULL:
3239 intel_dp->color_range_auto = false;
3240 intel_dp->color_range = 0;
3241 break;
3242 case INTEL_BROADCAST_RGB_LIMITED:
3243 intel_dp->color_range_auto = false;
3244 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3245 break;
3246 default:
3247 return -EINVAL;
3248 }
ae4edb80
DV		 3249
3250 if (old_auto == intel_dp->color_range_auto &&
3251 old_range == intel_dp->color_range)
3252 return 0;
3253
e953fd7b
CW		 3254 goto done;
3255 }
3256
53b41837
YN		 3257 if (is_edp(intel_dp) &&
3258 property == connector->dev->mode_config.scaling_mode_property) {
3259 if (val == DRM_MODE_SCALE_NONE) {
3260 DRM_DEBUG_KMS("no scaling not supported\n");
3261 return -EINVAL;
3262 }
3263
3264 if (intel_connector->panel.fitting_mode == val) {
3265 /* the eDP scaling property is not changed */
3266 return 0;
3267 }
3268 intel_connector->panel.fitting_mode = val;
3269
3270 goto done;
3271 }
3272
f684960e
CW		 3273 return -EINVAL;
3274
3275done:
c0c36b94
CW		 3276 if (intel_encoder->base.crtc)
3277 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3278
3279 return 0;
3280}
3281
a4fc5ed6 3282static void
73845adf 3283intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3284{
1d508706 3285 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3286
9cd300e0
JN		 3287 if (!IS_ERR_OR_NULL(intel_connector->edid))
3288 kfree(intel_connector->edid);
3289
acd8db10
PZ		 3290 /* Can't call is_edp() since the encoder may have been destroyed
3291 * already. */
3292 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3293 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3294
a4fc5ed6 3295 drm_connector_cleanup(connector);
55f78c43 3296 kfree(connector);
a4fc5ed6
KP		 3297}
3298
00c09d70 3299void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3300{
da63a9f2
PZ		 3301 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3302 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3303 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3304
3305 i2c_del_adapter(&intel_dp->adapter);
3306 drm_encoder_cleanup(encoder);
bd943159
KP		 3307 if (is_edp(intel_dp)) {
3308 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3309 mutex_lock(&dev->mode_config.mutex);
bd943159 3310 ironlake_panel_vdd_off_sync(intel_dp);
bd173813 3311 mutex_unlock(&dev->mode_config.mutex);
bd943159 3312 }
da63a9f2 3313 kfree(intel_dig_port);
24d05927
DV		 3314}
3315
a4fc5ed6 3316static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3317 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3318 .detect = intel_dp_detect,
3319 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3320 .set_property = intel_dp_set_property,
73845adf 3321 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3322};
3323
3324static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3325 .get_modes = intel_dp_get_modes,
3326 .mode_valid = intel_dp_mode_valid,
df0e9248 3327 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3328};
3329
a4fc5ed6 3330static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3331 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3332};
3333
995b6762 3334static void
21d40d37 3335intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3336{
fa90ecef 3337 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3338
885a5014 3339 intel_dp_check_link_status(intel_dp);
c8110e52 3340}
6207937d 3341
e3421a18
ZW		 3342/* Return which DP Port should be selected for Transcoder DP control */
3343int
0206e353 3344intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3345{
3346 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3347 struct intel_encoder *intel_encoder;
3348 struct intel_dp *intel_dp;
e3421a18 3349
fa90ecef
PZ		 3350 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3351 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3352
fa90ecef
PZ		 3353 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3354 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3355 return intel_dp->output_reg;
e3421a18 3356 }
ea5b213a 3357
e3421a18
ZW		 3358 return -1;
3359}
3360
36e83a18 3361/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3362bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3363{
3364 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3365 union child_device_config *p_child;
36e83a18 3366 int i;
5d8a7752
VS		 3367 static const short port_mapping[] = {
3368 [PORT_B] = PORT_IDPB,
3369 [PORT_C] = PORT_IDPC,
3370 [PORT_D] = PORT_IDPD,
3371 };
36e83a18 3372
3b32a35b
VS		 3373 if (port == PORT_A)
3374 return true;
3375
41aa3448 3376 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3377 return false;
3378
41aa3448
RV		 3379 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3380 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3381
5d8a7752 3382 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3383 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3384 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3385 return true;
3386 }
3387 return false;
3388}
3389
f684960e
CW		 3390static void
3391intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3392{
53b41837
YN		 3393 struct intel_connector *intel_connector = to_intel_connector(connector);
3394
3f43c48d 3395 intel_attach_force_audio_property(connector);
e953fd7b 3396 intel_attach_broadcast_rgb_property(connector);
55bc60db 3397 intel_dp->color_range_auto = true;
53b41837
YN		 3398
3399 if (is_edp(intel_dp)) {
3400 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3401 drm_object_attach_property(
3402 &connector->base,
53b41837 3403 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3404 DRM_MODE_SCALE_ASPECT);
3405 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3406 }
f684960e
CW		 3407}
3408
67a54566
DV		 3409static void
3410intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3411 struct intel_dp *intel_dp,
3412 struct edp_power_seq *out)
67a54566
DV		 3413{
3414 struct drm_i915_private *dev_priv = dev->dev_private;
3415 struct edp_power_seq cur, vbt, spec, final;
3416 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3417 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3418
3419 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3420 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3421 pp_on_reg = PCH_PP_ON_DELAYS;
3422 pp_off_reg = PCH_PP_OFF_DELAYS;
3423 pp_div_reg = PCH_PP_DIVISOR;
3424 } else {
bf13e81b
JN		 3425 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3426
3427 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3428 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3429 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3430 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3431 }
67a54566
DV		 3432
3433 /* Workaround: Need to write PP_CONTROL with the unlock key as
3434 * the very first thing. */
453c5420 3435 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3436 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3437
453c5420
JB		 3438 pp_on = I915_READ(pp_on_reg);
3439 pp_off = I915_READ(pp_off_reg);
3440 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3441
3442 /* Pull timing values out of registers */
3443 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3444 PANEL_POWER_UP_DELAY_SHIFT;
3445
3446 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3447 PANEL_LIGHT_ON_DELAY_SHIFT;
3448
3449 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3450 PANEL_LIGHT_OFF_DELAY_SHIFT;
3451
3452 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3453 PANEL_POWER_DOWN_DELAY_SHIFT;
3454
3455 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3456 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3457
3458 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3459 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3460
41aa3448 3461 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3462
3463 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3464 * our hw here, which are all in 100usec. */
3465 spec.t1_t3 = 210 * 10;
3466 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3467 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3468 spec.t10 = 500 * 10;
3469 /* This one is special and actually in units of 100ms, but zero
3470 * based in the hw (so we need to add 100 ms). But the sw vbt
3471 * table multiplies it with 1000 to make it in units of 100usec,
3472 * too. */
3473 spec.t11_t12 = (510 + 100) * 10;
3474
3475 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3476 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3477
3478 /* Use the max of the register settings and vbt. If both are
3479 * unset, fall back to the spec limits. */
3480#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3481 spec.field : \
3482 max(cur.field, vbt.field))
3483 assign_final(t1_t3);
3484 assign_final(t8);
3485 assign_final(t9);
3486 assign_final(t10);
3487 assign_final(t11_t12);
3488#undef assign_final
3489
3490#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3491 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3492 intel_dp->backlight_on_delay = get_delay(t8);
3493 intel_dp->backlight_off_delay = get_delay(t9);
3494 intel_dp->panel_power_down_delay = get_delay(t10);
3495 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3496#undef get_delay
3497
f30d26e4
JN		 3498 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3499 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3500 intel_dp->panel_power_cycle_delay);
3501
3502 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3503 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3504
3505 if (out)
3506 *out = final;
3507}
3508
3509static void
3510intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3511 struct intel_dp *intel_dp,
3512 struct edp_power_seq *seq)
3513{
3514 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3515 u32 pp_on, pp_off, pp_div, port_sel = 0;
3516 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3517 int pp_on_reg, pp_off_reg, pp_div_reg;
3518
3519 if (HAS_PCH_SPLIT(dev)) {
3520 pp_on_reg = PCH_PP_ON_DELAYS;
3521 pp_off_reg = PCH_PP_OFF_DELAYS;
3522 pp_div_reg = PCH_PP_DIVISOR;
3523 } else {
bf13e81b
JN		 3524 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3525
3526 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3527 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3528 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3529 }
3530
67a54566 3531 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 3532 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3533 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3534 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3535 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3536 /* Compute the divisor for the pp clock, simply match the Bspec
3537 * formula. */
453c5420 3538 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3539 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3540 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3541
3542 /* Haswell doesn't have any port selection bits for the panel
3543 * power sequencer any more. */
bc7d38a4 3544 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3545 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3546 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3547 else
3548 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3549 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3550 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3551 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3552 else
a24c144c 3553 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3554 }
3555
453c5420
JB		 3556 pp_on |= port_sel;
3557
3558 I915_WRITE(pp_on_reg, pp_on);
3559 I915_WRITE(pp_off_reg, pp_off);
3560 I915_WRITE(pp_div_reg, pp_div);
67a54566 3561
67a54566 3562 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3563 I915_READ(pp_on_reg),
3564 I915_READ(pp_off_reg),
3565 I915_READ(pp_div_reg));
f684960e
CW		 3566}
3567
ed92f0b2 3568static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3569 struct intel_connector *intel_connector,
3570 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3571{
3572 struct drm_connector *connector = &intel_connector->base;
3573 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3574 struct drm_device *dev = intel_dig_port->base.base.dev;
3575 struct drm_i915_private *dev_priv = dev->dev_private;
3576 struct drm_display_mode *fixed_mode = NULL;
ed92f0b2
PZ		 3577 bool has_dpcd;
3578 struct drm_display_mode *scan;
3579 struct edid *edid;
3580
3581 if (!is_edp(intel_dp))
3582 return true;
3583
ed92f0b2
PZ		 3584 /* Cache DPCD and EDID for edp. */
3585 ironlake_edp_panel_vdd_on(intel_dp);
3586 has_dpcd = intel_dp_get_dpcd(intel_dp);
3587 ironlake_edp_panel_vdd_off(intel_dp, false);
3588
3589 if (has_dpcd) {
3590 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3591 dev_priv->no_aux_handshake =
3592 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3593 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3594 } else {
3595 /* if this fails, presume the device is a ghost */
3596 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3597 return false;
3598 }
3599
3600 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3601 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3602
ed92f0b2
PZ		 3603 edid = drm_get_edid(connector, &intel_dp->adapter);
3604 if (edid) {
3605 if (drm_add_edid_modes(connector, edid)) {
3606 drm_mode_connector_update_edid_property(connector,
3607 edid);
3608 drm_edid_to_eld(connector, edid);
3609 } else {
3610 kfree(edid);
3611 edid = ERR_PTR(-EINVAL);
3612 }
3613 } else {
3614 edid = ERR_PTR(-ENOENT);
3615 }
3616 intel_connector->edid = edid;
3617
3618 /* prefer fixed mode from EDID if available */
3619 list_for_each_entry(scan, &connector->probed_modes, head) {
3620 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3621 fixed_mode = drm_mode_duplicate(dev, scan);
3622 break;
3623 }
3624 }
3625
3626 /* fallback to VBT if available for eDP */
3627 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3628 fixed_mode = drm_mode_duplicate(dev,
3629 dev_priv->vbt.lfp_lvds_vbt_mode);
3630 if (fixed_mode)
3631 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3632 }
3633
ed92f0b2
PZ		 3634 intel_panel_init(&intel_connector->panel, fixed_mode);
3635 intel_panel_setup_backlight(connector);
3636
3637 return true;
3638}
3639
16c25533 3640bool
f0fec3f2
PZ		 3641intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3642 struct intel_connector *intel_connector)
a4fc5ed6 3643{
f0fec3f2
PZ		 3644 struct drm_connector *connector = &intel_connector->base;
3645 struct intel_dp *intel_dp = &intel_dig_port->dp;
3646 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3647 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3648 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3649 enum port port = intel_dig_port->port;
0095e6dc 3650 struct edp_power_seq power_seq = { 0 };
5eb08b69 3651 const char *name = NULL;
b2a14755 3652 int type, error;
a4fc5ed6 3653
0767935e
DV		 3654 /* Preserve the current hw state. */
3655 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3656 intel_dp->attached_connector = intel_connector;
3d3dc149 3657
3b32a35b 3658 if (intel_dp_is_edp(dev, port))
b329530c 3659 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3660 else
3661 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3662
f7d24902
ID		 3663 /*
3664 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3665 * for DP the encoder type can be set by the caller to
3666 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3667 */
3668 if (type == DRM_MODE_CONNECTOR_eDP)
3669 intel_encoder->type = INTEL_OUTPUT_EDP;
3670
e7281eab
ID		 3671 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3672 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3673 port_name(port));
3674
b329530c 3675 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3676 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3677
a4fc5ed6
KP		 3678 connector->interlace_allowed = true;
3679 connector->doublescan_allowed = 0;
3680
f0fec3f2
PZ		 3681 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3682 ironlake_panel_vdd_work);
a4fc5ed6 3683
df0e9248 3684 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3685 drm_sysfs_connector_add(connector);
3686
affa9354 3687 if (HAS_DDI(dev))
bcbc889b
PZ		 3688 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3689 else
3690 intel_connector->get_hw_state = intel_connector_get_hw_state;
3691
9ed35ab1
PZ		 3692 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3693 if (HAS_DDI(dev)) {
3694 switch (intel_dig_port->port) {
3695 case PORT_A:
3696 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3697 break;
3698 case PORT_B:
3699 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3700 break;
3701 case PORT_C:
3702 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3703 break;
3704 case PORT_D:
3705 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3706 break;
3707 default:
3708 BUG();
3709 }
3710 }
e8cb4558 3711
a4fc5ed6 3712 /* Set up the DDC bus. */
ab9d7c30
PZ		 3713 switch (port) {
3714 case PORT_A:
1d843f9d 3715 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3716 name = "DPDDC-A";
3717 break;
3718 case PORT_B:
1d843f9d 3719 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3720 name = "DPDDC-B";
3721 break;
3722 case PORT_C:
1d843f9d 3723 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3724 name = "DPDDC-C";
3725 break;
3726 case PORT_D:
1d843f9d 3727 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3728 name = "DPDDC-D";
3729 break;
3730 default:
ad1c0b19 3731 BUG();
5eb08b69
ZW		 3732 }
3733
0095e6dc
PZ		 3734 if (is_edp(intel_dp))
3735 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3736
b2a14755
PZ		 3737 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3738 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3739 error, port_name(port));
c1f05264 3740
2b28bb1b
RV		 3741 intel_dp->psr_setup_done = false;
3742
0095e6dc 3743 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
15b1d171
PZ		 3744 i2c_del_adapter(&intel_dp->adapter);
3745 if (is_edp(intel_dp)) {
3746 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3747 mutex_lock(&dev->mode_config.mutex);
3748 ironlake_panel_vdd_off_sync(intel_dp);
3749 mutex_unlock(&dev->mode_config.mutex);
3750 }
b2f246a8
PZ		 3751 drm_sysfs_connector_remove(connector);
3752 drm_connector_cleanup(connector);
16c25533 3753 return false;
b2f246a8 3754 }
32f9d658 3755
f684960e
CW		 3756 intel_dp_add_properties(intel_dp, connector);
3757
a4fc5ed6
KP		 3758 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3759 * 0xd. Failure to do so will result in spurious interrupts being
3760 * generated on the port when a cable is not attached.
3761 */
3762 if (IS_G4X(dev) && !IS_GM45(dev)) {
3763 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3764 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3765 }
16c25533
PZ		 3766
3767 return true;
a4fc5ed6 3768}
f0fec3f2
PZ		 3769
3770void
3771intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3772{
3773 struct intel_digital_port *intel_dig_port;
3774 struct intel_encoder *intel_encoder;
3775 struct drm_encoder *encoder;
3776 struct intel_connector *intel_connector;
3777
b14c5679 3778 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3779 if (!intel_dig_port)
3780 return;
3781
b14c5679 3782 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3783 if (!intel_connector) {
3784 kfree(intel_dig_port);
3785 return;
3786 }
3787
3788 intel_encoder = &intel_dig_port->base;
3789 encoder = &intel_encoder->base;
3790
3791 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3792 DRM_MODE_ENCODER_TMDS);
3793
5bfe2ac0 3794 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3795 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3796 intel_encoder->disable = intel_disable_dp;
3797 intel_encoder->post_disable = intel_post_disable_dp;
3798 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3799 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3800 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3801 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3802 intel_encoder->pre_enable = vlv_pre_enable_dp;
3803 intel_encoder->enable = vlv_enable_dp;
3804 } else {
ecff4f3b
JN		 3805 intel_encoder->pre_enable = g4x_pre_enable_dp;
3806 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3807 }
f0fec3f2 3808
174edf1f 3809 intel_dig_port->port = port;
f0fec3f2
PZ		 3810 intel_dig_port->dp.output_reg = output_reg;
3811
00c09d70 3812 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3813 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3814 intel_encoder->cloneable = false;
3815 intel_encoder->hot_plug = intel_dp_hot_plug;
3816
15b1d171
PZ		 3817 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3818 drm_encoder_cleanup(encoder);
3819 kfree(intel_dig_port);
b2f246a8 3820 kfree(intel_connector);
15b1d171 3821 }
f0fec3f2 3822}
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