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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
01527b31 CT |
31 | #include <linux/notifier.h> |
32 | #include <linux/reboot.h> | |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_crtc_helper.h> | |
37 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 38 | #include "intel_drv.h" |
760285e7 | 39 | #include <drm/i915_drm.h> |
a4fc5ed6 | 40 | #include "i915_drv.h" |
a4fc5ed6 | 41 | |
a4fc5ed6 KP |
42 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
43 | ||
559be30c TP |
44 | /* Compliance test status bits */ |
45 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 | |
46 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
47 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
48 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
49 | ||
9dd4ffdf | 50 | struct dp_link_dpll { |
840b32b7 | 51 | int clock; |
9dd4ffdf CML |
52 | struct dpll dpll; |
53 | }; | |
54 | ||
55 | static const struct dp_link_dpll gen4_dpll[] = { | |
840b32b7 | 56 | { 162000, |
9dd4ffdf | 57 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
840b32b7 | 58 | { 270000, |
9dd4ffdf CML |
59 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
60 | }; | |
61 | ||
62 | static const struct dp_link_dpll pch_dpll[] = { | |
840b32b7 | 63 | { 162000, |
9dd4ffdf | 64 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
840b32b7 | 65 | { 270000, |
9dd4ffdf CML |
66 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
67 | }; | |
68 | ||
65ce4bf5 | 69 | static const struct dp_link_dpll vlv_dpll[] = { |
840b32b7 | 70 | { 162000, |
58f6e632 | 71 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
840b32b7 | 72 | { 270000, |
65ce4bf5 CML |
73 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
74 | }; | |
75 | ||
ef9348c8 CML |
76 | /* |
77 | * CHV supports eDP 1.4 that have more link rates. | |
78 | * Below only provides the fixed rate but exclude variable rate. | |
79 | */ | |
80 | static const struct dp_link_dpll chv_dpll[] = { | |
81 | /* | |
82 | * CHV requires to program fractional division for m2. | |
83 | * m2 is stored in fixed point format using formula below | |
84 | * (m2_int << 22) | m2_fraction | |
85 | */ | |
840b32b7 | 86 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
ef9348c8 | 87 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
840b32b7 | 88 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 | 89 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
840b32b7 | 90 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 CML |
91 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
92 | }; | |
637a9c63 | 93 | |
64987fc5 SJ |
94 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
95 | 324000, 432000, 540000 }; | |
637a9c63 | 96 | static const int skl_rates[] = { 162000, 216000, 270000, |
f4896f15 VS |
97 | 324000, 432000, 540000 }; |
98 | static const int default_rates[] = { 162000, 270000, 540000 }; | |
ef9348c8 | 99 | |
cfcb0fc9 JB |
100 | /** |
101 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
102 | * @intel_dp: DP struct | |
103 | * | |
104 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
105 | * will return true, and false otherwise. | |
106 | */ | |
107 | static bool is_edp(struct intel_dp *intel_dp) | |
108 | { | |
da63a9f2 PZ |
109 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
110 | ||
111 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
112 | } |
113 | ||
68b4d824 | 114 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 115 | { |
68b4d824 ID |
116 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
117 | ||
118 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
119 | } |
120 | ||
df0e9248 CW |
121 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
122 | { | |
fa90ecef | 123 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
124 | } |
125 | ||
ea5b213a | 126 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
1e0560e0 | 127 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 128 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
093e3f13 | 129 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
a8c3344e VS |
130 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
131 | enum pipe pipe); | |
f21a2198 | 132 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
a4fc5ed6 | 133 | |
ed4e9c1d VS |
134 | static int |
135 | intel_dp_max_link_bw(struct intel_dp *intel_dp) | |
a4fc5ed6 | 136 | { |
7183dc29 | 137 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
138 | |
139 | switch (max_link_bw) { | |
140 | case DP_LINK_BW_1_62: | |
141 | case DP_LINK_BW_2_7: | |
1db10e28 | 142 | case DP_LINK_BW_5_4: |
d4eead50 | 143 | break; |
a4fc5ed6 | 144 | default: |
d4eead50 ID |
145 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
146 | max_link_bw); | |
a4fc5ed6 KP |
147 | max_link_bw = DP_LINK_BW_1_62; |
148 | break; | |
149 | } | |
150 | return max_link_bw; | |
151 | } | |
152 | ||
eeb6324d PZ |
153 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
154 | { | |
155 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
eeb6324d PZ |
156 | u8 source_max, sink_max; |
157 | ||
ccb1a831 | 158 | source_max = intel_dig_port->max_lanes; |
eeb6324d PZ |
159 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
160 | ||
161 | return min(source_max, sink_max); | |
162 | } | |
163 | ||
cd9dde44 AJ |
164 | /* |
165 | * The units on the numbers in the next two are... bizarre. Examples will | |
166 | * make it clearer; this one parallels an example in the eDP spec. | |
167 | * | |
168 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
169 | * | |
170 | * 270000 * 1 * 8 / 10 == 216000 | |
171 | * | |
172 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
173 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
174 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
175 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
176 | * | |
177 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
178 | * get the result in decakilobits instead of kilobits. | |
179 | */ | |
180 | ||
a4fc5ed6 | 181 | static int |
c898261c | 182 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 183 | { |
cd9dde44 | 184 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
185 | } |
186 | ||
fe27d53e DA |
187 | static int |
188 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
189 | { | |
190 | return (max_link_clock * max_lanes * 8) / 10; | |
191 | } | |
192 | ||
c19de8eb | 193 | static enum drm_mode_status |
a4fc5ed6 KP |
194 | intel_dp_mode_valid(struct drm_connector *connector, |
195 | struct drm_display_mode *mode) | |
196 | { | |
df0e9248 | 197 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
198 | struct intel_connector *intel_connector = to_intel_connector(connector); |
199 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
200 | int target_clock = mode->clock; |
201 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
799487f5 | 202 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
a4fc5ed6 | 203 | |
dd06f90e JN |
204 | if (is_edp(intel_dp) && fixed_mode) { |
205 | if (mode->hdisplay > fixed_mode->hdisplay) | |
7de56f43 ZY |
206 | return MODE_PANEL; |
207 | ||
dd06f90e | 208 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 209 | return MODE_PANEL; |
03afc4a2 DV |
210 | |
211 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
212 | } |
213 | ||
50fec21a | 214 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
eeb6324d | 215 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 DV |
216 | |
217 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
218 | mode_rate = intel_dp_link_required(target_clock, 18); | |
219 | ||
799487f5 | 220 | if (mode_rate > max_rate || target_clock > max_dotclk) |
c4867936 | 221 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
222 | |
223 | if (mode->clock < 10000) | |
224 | return MODE_CLOCK_LOW; | |
225 | ||
0af78a2b DV |
226 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
227 | return MODE_H_ILLEGAL; | |
228 | ||
a4fc5ed6 KP |
229 | return MODE_OK; |
230 | } | |
231 | ||
a4f1289e | 232 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
a4fc5ed6 KP |
233 | { |
234 | int i; | |
235 | uint32_t v = 0; | |
236 | ||
237 | if (src_bytes > 4) | |
238 | src_bytes = 4; | |
239 | for (i = 0; i < src_bytes; i++) | |
240 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
241 | return v; | |
242 | } | |
243 | ||
c2af70e2 | 244 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
a4fc5ed6 KP |
245 | { |
246 | int i; | |
247 | if (dst_bytes > 4) | |
248 | dst_bytes = 4; | |
249 | for (i = 0; i < dst_bytes; i++) | |
250 | dst[i] = src >> ((3-i) * 8); | |
251 | } | |
252 | ||
bf13e81b JN |
253 | static void |
254 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
36b5f425 | 255 | struct intel_dp *intel_dp); |
bf13e81b JN |
256 | static void |
257 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
36b5f425 | 258 | struct intel_dp *intel_dp); |
bf13e81b | 259 | |
773538e8 VS |
260 | static void pps_lock(struct intel_dp *intel_dp) |
261 | { | |
262 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
263 | struct intel_encoder *encoder = &intel_dig_port->base; | |
264 | struct drm_device *dev = encoder->base.dev; | |
265 | struct drm_i915_private *dev_priv = dev->dev_private; | |
266 | enum intel_display_power_domain power_domain; | |
267 | ||
268 | /* | |
269 | * See vlv_power_sequencer_reset() why we need | |
270 | * a power domain reference here. | |
271 | */ | |
25f78f58 | 272 | power_domain = intel_display_port_aux_power_domain(encoder); |
773538e8 VS |
273 | intel_display_power_get(dev_priv, power_domain); |
274 | ||
275 | mutex_lock(&dev_priv->pps_mutex); | |
276 | } | |
277 | ||
278 | static void pps_unlock(struct intel_dp *intel_dp) | |
279 | { | |
280 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
281 | struct intel_encoder *encoder = &intel_dig_port->base; | |
282 | struct drm_device *dev = encoder->base.dev; | |
283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
284 | enum intel_display_power_domain power_domain; | |
285 | ||
286 | mutex_unlock(&dev_priv->pps_mutex); | |
287 | ||
25f78f58 | 288 | power_domain = intel_display_port_aux_power_domain(encoder); |
773538e8 VS |
289 | intel_display_power_put(dev_priv, power_domain); |
290 | } | |
291 | ||
961a0db0 VS |
292 | static void |
293 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) | |
294 | { | |
295 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
296 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
298 | enum pipe pipe = intel_dp->pps_pipe; | |
0047eedc VS |
299 | bool pll_enabled, release_cl_override = false; |
300 | enum dpio_phy phy = DPIO_PHY(pipe); | |
301 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); | |
961a0db0 VS |
302 | uint32_t DP; |
303 | ||
304 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, | |
305 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", | |
306 | pipe_name(pipe), port_name(intel_dig_port->port))) | |
307 | return; | |
308 | ||
309 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", | |
310 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
311 | ||
312 | /* Preserve the BIOS-computed detected bit. This is | |
313 | * supposed to be read-only. | |
314 | */ | |
315 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
316 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
317 | DP |= DP_PORT_WIDTH(1); | |
318 | DP |= DP_LINK_TRAIN_PAT_1; | |
319 | ||
320 | if (IS_CHERRYVIEW(dev)) | |
321 | DP |= DP_PIPE_SELECT_CHV(pipe); | |
322 | else if (pipe == PIPE_B) | |
323 | DP |= DP_PIPEB_SELECT; | |
324 | ||
d288f65f VS |
325 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
326 | ||
327 | /* | |
328 | * The DPLL for the pipe must be enabled for this to work. | |
329 | * So enable temporarily it if it's not already enabled. | |
330 | */ | |
0047eedc VS |
331 | if (!pll_enabled) { |
332 | release_cl_override = IS_CHERRYVIEW(dev) && | |
333 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); | |
334 | ||
3f36b937 TU |
335 | if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? |
336 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { | |
337 | DRM_ERROR("Failed to force on pll for pipe %c!\n", | |
338 | pipe_name(pipe)); | |
339 | return; | |
340 | } | |
0047eedc | 341 | } |
d288f65f | 342 | |
961a0db0 VS |
343 | /* |
344 | * Similar magic as in intel_dp_enable_port(). | |
345 | * We _must_ do this port enable + disable trick | |
346 | * to make this power seqeuencer lock onto the port. | |
347 | * Otherwise even VDD force bit won't work. | |
348 | */ | |
349 | I915_WRITE(intel_dp->output_reg, DP); | |
350 | POSTING_READ(intel_dp->output_reg); | |
351 | ||
352 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); | |
353 | POSTING_READ(intel_dp->output_reg); | |
354 | ||
355 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); | |
356 | POSTING_READ(intel_dp->output_reg); | |
d288f65f | 357 | |
0047eedc | 358 | if (!pll_enabled) { |
d288f65f | 359 | vlv_force_pll_off(dev, pipe); |
0047eedc VS |
360 | |
361 | if (release_cl_override) | |
362 | chv_phy_powergate_ch(dev_priv, phy, ch, false); | |
363 | } | |
961a0db0 VS |
364 | } |
365 | ||
bf13e81b JN |
366 | static enum pipe |
367 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
368 | { | |
369 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bf13e81b JN |
370 | struct drm_device *dev = intel_dig_port->base.base.dev; |
371 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4a5d2f8 VS |
372 | struct intel_encoder *encoder; |
373 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); | |
a8c3344e | 374 | enum pipe pipe; |
bf13e81b | 375 | |
e39b999a | 376 | lockdep_assert_held(&dev_priv->pps_mutex); |
bf13e81b | 377 | |
a8c3344e VS |
378 | /* We should never land here with regular DP ports */ |
379 | WARN_ON(!is_edp(intel_dp)); | |
380 | ||
a4a5d2f8 VS |
381 | if (intel_dp->pps_pipe != INVALID_PIPE) |
382 | return intel_dp->pps_pipe; | |
383 | ||
384 | /* | |
385 | * We don't have power sequencer currently. | |
386 | * Pick one that's not used by other ports. | |
387 | */ | |
19c8054c | 388 | for_each_intel_encoder(dev, encoder) { |
a4a5d2f8 VS |
389 | struct intel_dp *tmp; |
390 | ||
391 | if (encoder->type != INTEL_OUTPUT_EDP) | |
392 | continue; | |
393 | ||
394 | tmp = enc_to_intel_dp(&encoder->base); | |
395 | ||
396 | if (tmp->pps_pipe != INVALID_PIPE) | |
397 | pipes &= ~(1 << tmp->pps_pipe); | |
398 | } | |
399 | ||
400 | /* | |
401 | * Didn't find one. This should not happen since there | |
402 | * are two power sequencers and up to two eDP ports. | |
403 | */ | |
404 | if (WARN_ON(pipes == 0)) | |
a8c3344e VS |
405 | pipe = PIPE_A; |
406 | else | |
407 | pipe = ffs(pipes) - 1; | |
a4a5d2f8 | 408 | |
a8c3344e VS |
409 | vlv_steal_power_sequencer(dev, pipe); |
410 | intel_dp->pps_pipe = pipe; | |
a4a5d2f8 VS |
411 | |
412 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", | |
413 | pipe_name(intel_dp->pps_pipe), | |
414 | port_name(intel_dig_port->port)); | |
415 | ||
416 | /* init power sequencer on this pipe and port */ | |
36b5f425 VS |
417 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
418 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
a4a5d2f8 | 419 | |
961a0db0 VS |
420 | /* |
421 | * Even vdd force doesn't work until we've made | |
422 | * the power sequencer lock in on the port. | |
423 | */ | |
424 | vlv_power_sequencer_kick(intel_dp); | |
a4a5d2f8 VS |
425 | |
426 | return intel_dp->pps_pipe; | |
427 | } | |
428 | ||
6491ab27 VS |
429 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
430 | enum pipe pipe); | |
431 | ||
432 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, | |
433 | enum pipe pipe) | |
434 | { | |
435 | return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; | |
436 | } | |
437 | ||
438 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, | |
439 | enum pipe pipe) | |
440 | { | |
441 | return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; | |
442 | } | |
443 | ||
444 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, | |
445 | enum pipe pipe) | |
446 | { | |
447 | return true; | |
448 | } | |
bf13e81b | 449 | |
a4a5d2f8 | 450 | static enum pipe |
6491ab27 VS |
451 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
452 | enum port port, | |
453 | vlv_pipe_check pipe_check) | |
a4a5d2f8 VS |
454 | { |
455 | enum pipe pipe; | |
bf13e81b | 456 | |
bf13e81b JN |
457 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
458 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & | |
459 | PANEL_PORT_SELECT_MASK; | |
a4a5d2f8 VS |
460 | |
461 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) | |
462 | continue; | |
463 | ||
6491ab27 VS |
464 | if (!pipe_check(dev_priv, pipe)) |
465 | continue; | |
466 | ||
a4a5d2f8 | 467 | return pipe; |
bf13e81b JN |
468 | } |
469 | ||
a4a5d2f8 VS |
470 | return INVALID_PIPE; |
471 | } | |
472 | ||
473 | static void | |
474 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) | |
475 | { | |
476 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
477 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
478 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4a5d2f8 VS |
479 | enum port port = intel_dig_port->port; |
480 | ||
481 | lockdep_assert_held(&dev_priv->pps_mutex); | |
482 | ||
483 | /* try to find a pipe with this port selected */ | |
6491ab27 VS |
484 | /* first pick one where the panel is on */ |
485 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
486 | vlv_pipe_has_pp_on); | |
487 | /* didn't find one? pick one where vdd is on */ | |
488 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
489 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
490 | vlv_pipe_has_vdd_on); | |
491 | /* didn't find one? pick one with just the correct port */ | |
492 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
493 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
494 | vlv_pipe_any); | |
a4a5d2f8 VS |
495 | |
496 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ | |
497 | if (intel_dp->pps_pipe == INVALID_PIPE) { | |
498 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", | |
499 | port_name(port)); | |
500 | return; | |
bf13e81b JN |
501 | } |
502 | ||
a4a5d2f8 VS |
503 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
504 | port_name(port), pipe_name(intel_dp->pps_pipe)); | |
505 | ||
36b5f425 VS |
506 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
507 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
bf13e81b JN |
508 | } |
509 | ||
773538e8 VS |
510 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
511 | { | |
512 | struct drm_device *dev = dev_priv->dev; | |
513 | struct intel_encoder *encoder; | |
514 | ||
666a4537 | 515 | if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))) |
773538e8 VS |
516 | return; |
517 | ||
518 | /* | |
519 | * We can't grab pps_mutex here due to deadlock with power_domain | |
520 | * mutex when power_domain functions are called while holding pps_mutex. | |
521 | * That also means that in order to use pps_pipe the code needs to | |
522 | * hold both a power domain reference and pps_mutex, and the power domain | |
523 | * reference get/put must be done while _not_ holding pps_mutex. | |
524 | * pps_{lock,unlock}() do these steps in the correct order, so one | |
525 | * should use them always. | |
526 | */ | |
527 | ||
19c8054c | 528 | for_each_intel_encoder(dev, encoder) { |
773538e8 VS |
529 | struct intel_dp *intel_dp; |
530 | ||
531 | if (encoder->type != INTEL_OUTPUT_EDP) | |
532 | continue; | |
533 | ||
534 | intel_dp = enc_to_intel_dp(&encoder->base); | |
535 | intel_dp->pps_pipe = INVALID_PIPE; | |
536 | } | |
bf13e81b JN |
537 | } |
538 | ||
f0f59a00 VS |
539 | static i915_reg_t |
540 | _pp_ctrl_reg(struct intel_dp *intel_dp) | |
bf13e81b JN |
541 | { |
542 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
543 | ||
b0a08bec VK |
544 | if (IS_BROXTON(dev)) |
545 | return BXT_PP_CONTROL(0); | |
546 | else if (HAS_PCH_SPLIT(dev)) | |
bf13e81b JN |
547 | return PCH_PP_CONTROL; |
548 | else | |
549 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); | |
550 | } | |
551 | ||
f0f59a00 VS |
552 | static i915_reg_t |
553 | _pp_stat_reg(struct intel_dp *intel_dp) | |
bf13e81b JN |
554 | { |
555 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
556 | ||
b0a08bec VK |
557 | if (IS_BROXTON(dev)) |
558 | return BXT_PP_STATUS(0); | |
559 | else if (HAS_PCH_SPLIT(dev)) | |
bf13e81b JN |
560 | return PCH_PP_STATUS; |
561 | else | |
562 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); | |
563 | } | |
564 | ||
01527b31 CT |
565 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
566 | This function only applicable when panel PM state is not to be tracked */ | |
567 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, | |
568 | void *unused) | |
569 | { | |
570 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), | |
571 | edp_notifier); | |
572 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
573 | struct drm_i915_private *dev_priv = dev->dev_private; | |
01527b31 CT |
574 | |
575 | if (!is_edp(intel_dp) || code != SYS_RESTART) | |
576 | return 0; | |
577 | ||
773538e8 | 578 | pps_lock(intel_dp); |
e39b999a | 579 | |
666a4537 | 580 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e39b999a | 581 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
f0f59a00 | 582 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
649636ef | 583 | u32 pp_div; |
e39b999a | 584 | |
01527b31 CT |
585 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
586 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
587 | pp_div = I915_READ(pp_div_reg); | |
588 | pp_div &= PP_REFERENCE_DIVIDER_MASK; | |
589 | ||
590 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ | |
591 | I915_WRITE(pp_div_reg, pp_div | 0x1F); | |
592 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); | |
593 | msleep(intel_dp->panel_power_cycle_delay); | |
594 | } | |
595 | ||
773538e8 | 596 | pps_unlock(intel_dp); |
e39b999a | 597 | |
01527b31 CT |
598 | return 0; |
599 | } | |
600 | ||
4be73780 | 601 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 602 | { |
30add22d | 603 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
604 | struct drm_i915_private *dev_priv = dev->dev_private; |
605 | ||
e39b999a VS |
606 | lockdep_assert_held(&dev_priv->pps_mutex); |
607 | ||
666a4537 | 608 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
9a42356b VS |
609 | intel_dp->pps_pipe == INVALID_PIPE) |
610 | return false; | |
611 | ||
bf13e81b | 612 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
613 | } |
614 | ||
4be73780 | 615 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 616 | { |
30add22d | 617 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
618 | struct drm_i915_private *dev_priv = dev->dev_private; |
619 | ||
e39b999a VS |
620 | lockdep_assert_held(&dev_priv->pps_mutex); |
621 | ||
666a4537 | 622 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
9a42356b VS |
623 | intel_dp->pps_pipe == INVALID_PIPE) |
624 | return false; | |
625 | ||
773538e8 | 626 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
ebf33b18 KP |
627 | } |
628 | ||
9b984dae KP |
629 | static void |
630 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
631 | { | |
30add22d | 632 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9b984dae | 633 | struct drm_i915_private *dev_priv = dev->dev_private; |
ebf33b18 | 634 | |
9b984dae KP |
635 | if (!is_edp(intel_dp)) |
636 | return; | |
453c5420 | 637 | |
4be73780 | 638 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
639 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
640 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
641 | I915_READ(_pp_stat_reg(intel_dp)), |
642 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
643 | } |
644 | } | |
645 | ||
9ee32fea DV |
646 | static uint32_t |
647 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
648 | { | |
649 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
650 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
651 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 652 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
653 | uint32_t status; |
654 | bool done; | |
655 | ||
ef04f00d | 656 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 657 | if (has_aux_irq) |
b18ac466 | 658 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 659 | msecs_to_jiffies_timeout(10)); |
9ee32fea DV |
660 | else |
661 | done = wait_for_atomic(C, 10) == 0; | |
662 | if (!done) | |
663 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
664 | has_aux_irq); | |
665 | #undef C | |
666 | ||
667 | return status; | |
668 | } | |
669 | ||
6ffb1be7 | 670 | static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 671 | { |
174edf1f | 672 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
e7dc33f3 | 673 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
9ee32fea | 674 | |
a457f54b VS |
675 | if (index) |
676 | return 0; | |
677 | ||
ec5b01dd DL |
678 | /* |
679 | * The clock divider is based off the hrawclk, and would like to run at | |
a457f54b | 680 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
a4fc5ed6 | 681 | */ |
a457f54b | 682 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
ec5b01dd DL |
683 | } |
684 | ||
685 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
686 | { | |
687 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 688 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd DL |
689 | |
690 | if (index) | |
691 | return 0; | |
692 | ||
a457f54b VS |
693 | /* |
694 | * The clock divider is based off the cdclk or PCH rawclk, and would | |
695 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and | |
696 | * divide by 2000 and use that | |
697 | */ | |
e7dc33f3 | 698 | if (intel_dig_port->port == PORT_A) |
fce18c4c | 699 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
e7dc33f3 VS |
700 | else |
701 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); | |
ec5b01dd DL |
702 | } |
703 | ||
704 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
705 | { | |
706 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 707 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd | 708 | |
a457f54b | 709 | if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { |
2c55c336 | 710 | /* Workaround for non-ULT HSW */ |
bc86625a CW |
711 | switch (index) { |
712 | case 0: return 63; | |
713 | case 1: return 72; | |
714 | default: return 0; | |
715 | } | |
2c55c336 | 716 | } |
a457f54b VS |
717 | |
718 | return ilk_get_aux_clock_divider(intel_dp, index); | |
b84a1cf8 RV |
719 | } |
720 | ||
b6b5e383 DL |
721 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
722 | { | |
723 | /* | |
724 | * SKL doesn't need us to program the AUX clock divider (Hardware will | |
725 | * derive the clock from CDCLK automatically). We still implement the | |
726 | * get_aux_clock_divider vfunc to plug-in into the existing code. | |
727 | */ | |
728 | return index ? 0 : 1; | |
729 | } | |
730 | ||
6ffb1be7 VS |
731 | static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
732 | bool has_aux_irq, | |
733 | int send_bytes, | |
734 | uint32_t aux_clock_divider) | |
5ed12a19 DL |
735 | { |
736 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
737 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
738 | uint32_t precharge, timeout; | |
739 | ||
740 | if (IS_GEN6(dev)) | |
741 | precharge = 3; | |
742 | else | |
743 | precharge = 5; | |
744 | ||
f3c6a3a7 | 745 | if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A) |
5ed12a19 DL |
746 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
747 | else | |
748 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
749 | ||
750 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 751 | DP_AUX_CH_CTL_DONE | |
5ed12a19 | 752 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
788d4433 | 753 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 754 | timeout | |
788d4433 | 755 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
756 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
757 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 758 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
759 | } |
760 | ||
b9ca5fad DL |
761 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
762 | bool has_aux_irq, | |
763 | int send_bytes, | |
764 | uint32_t unused) | |
765 | { | |
766 | return DP_AUX_CH_CTL_SEND_BUSY | | |
767 | DP_AUX_CH_CTL_DONE | | |
768 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | | |
769 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
770 | DP_AUX_CH_CTL_TIME_OUT_1600us | | |
771 | DP_AUX_CH_CTL_RECEIVE_ERROR | | |
772 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
d4dcbdce | 773 | DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | |
b9ca5fad DL |
774 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
775 | } | |
776 | ||
b84a1cf8 RV |
777 | static int |
778 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
bd9f74a5 | 779 | const uint8_t *send, int send_bytes, |
b84a1cf8 RV |
780 | uint8_t *recv, int recv_size) |
781 | { | |
782 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
783 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
784 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 785 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
bc86625a | 786 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
787 | int i, ret, recv_bytes; |
788 | uint32_t status; | |
5ed12a19 | 789 | int try, clock = 0; |
4e6b788c | 790 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
884f19e9 JN |
791 | bool vdd; |
792 | ||
773538e8 | 793 | pps_lock(intel_dp); |
e39b999a | 794 | |
72c3500a VS |
795 | /* |
796 | * We will be called with VDD already enabled for dpcd/edid/oui reads. | |
797 | * In such cases we want to leave VDD enabled and it's up to upper layers | |
798 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off | |
799 | * ourselves. | |
800 | */ | |
1e0560e0 | 801 | vdd = edp_panel_vdd_on(intel_dp); |
b84a1cf8 RV |
802 | |
803 | /* dp aux is extremely sensitive to irq latency, hence request the | |
804 | * lowest possible wakeup latency and so prevent the cpu from going into | |
805 | * deep sleep states. | |
806 | */ | |
807 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
808 | ||
809 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 810 | |
11bee43e JB |
811 | /* Try to wait for any previous AUX channel activity */ |
812 | for (try = 0; try < 3; try++) { | |
ef04f00d | 813 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
814 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
815 | break; | |
816 | msleep(1); | |
817 | } | |
818 | ||
819 | if (try == 3) { | |
02196c77 MK |
820 | static u32 last_status = -1; |
821 | const u32 status = I915_READ(ch_ctl); | |
822 | ||
823 | if (status != last_status) { | |
824 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
825 | status); | |
826 | last_status = status; | |
827 | } | |
828 | ||
9ee32fea DV |
829 | ret = -EBUSY; |
830 | goto out; | |
4f7f7b7e CW |
831 | } |
832 | ||
46a5ae9f PZ |
833 | /* Only 5 data registers! */ |
834 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
835 | ret = -E2BIG; | |
836 | goto out; | |
837 | } | |
838 | ||
ec5b01dd | 839 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
153b1100 DL |
840 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
841 | has_aux_irq, | |
842 | send_bytes, | |
843 | aux_clock_divider); | |
5ed12a19 | 844 | |
bc86625a CW |
845 | /* Must try at least 3 times according to DP spec */ |
846 | for (try = 0; try < 5; try++) { | |
847 | /* Load the send data into the aux channel data registers */ | |
848 | for (i = 0; i < send_bytes; i += 4) | |
330e20ec | 849 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
a4f1289e RV |
850 | intel_dp_pack_aux(send + i, |
851 | send_bytes - i)); | |
bc86625a CW |
852 | |
853 | /* Send the command and wait for it to complete */ | |
5ed12a19 | 854 | I915_WRITE(ch_ctl, send_ctl); |
bc86625a CW |
855 | |
856 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
857 | ||
858 | /* Clear done status and any errors */ | |
859 | I915_WRITE(ch_ctl, | |
860 | status | | |
861 | DP_AUX_CH_CTL_DONE | | |
862 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
863 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
864 | ||
74ebf294 | 865 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
bc86625a | 866 | continue; |
74ebf294 TP |
867 | |
868 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 | |
869 | * 400us delay required for errors and timeouts | |
870 | * Timeout errors from the HW already meet this | |
871 | * requirement so skip to next iteration | |
872 | */ | |
873 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { | |
874 | usleep_range(400, 500); | |
bc86625a | 875 | continue; |
74ebf294 | 876 | } |
bc86625a | 877 | if (status & DP_AUX_CH_CTL_DONE) |
e058c945 | 878 | goto done; |
bc86625a | 879 | } |
a4fc5ed6 KP |
880 | } |
881 | ||
a4fc5ed6 | 882 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 883 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
884 | ret = -EBUSY; |
885 | goto out; | |
a4fc5ed6 KP |
886 | } |
887 | ||
e058c945 | 888 | done: |
a4fc5ed6 KP |
889 | /* Check for timeout or receive error. |
890 | * Timeouts occur when the sink is not connected | |
891 | */ | |
a5b3da54 | 892 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 893 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
894 | ret = -EIO; |
895 | goto out; | |
a5b3da54 | 896 | } |
1ae8c0a5 KP |
897 | |
898 | /* Timeouts occur when the device isn't connected, so they're | |
899 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 900 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 901 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
902 | ret = -ETIMEDOUT; |
903 | goto out; | |
a4fc5ed6 KP |
904 | } |
905 | ||
906 | /* Unload any bytes sent back from the other side */ | |
907 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
908 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
14e01889 RV |
909 | |
910 | /* | |
911 | * By BSpec: "Message sizes of 0 or >20 are not allowed." | |
912 | * We have no idea of what happened so we return -EBUSY so | |
913 | * drm layer takes care for the necessary retries. | |
914 | */ | |
915 | if (recv_bytes == 0 || recv_bytes > 20) { | |
916 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", | |
917 | recv_bytes); | |
918 | /* | |
919 | * FIXME: This patch was created on top of a series that | |
920 | * organize the retries at drm level. There EBUSY should | |
921 | * also take care for 1ms wait before retrying. | |
922 | * That aux retries re-org is still needed and after that is | |
923 | * merged we remove this sleep from here. | |
924 | */ | |
925 | usleep_range(1000, 1500); | |
926 | ret = -EBUSY; | |
927 | goto out; | |
928 | } | |
929 | ||
a4fc5ed6 KP |
930 | if (recv_bytes > recv_size) |
931 | recv_bytes = recv_size; | |
0206e353 | 932 | |
4f7f7b7e | 933 | for (i = 0; i < recv_bytes; i += 4) |
330e20ec | 934 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
a4f1289e | 935 | recv + i, recv_bytes - i); |
a4fc5ed6 | 936 | |
9ee32fea DV |
937 | ret = recv_bytes; |
938 | out: | |
939 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
940 | ||
884f19e9 JN |
941 | if (vdd) |
942 | edp_panel_vdd_off(intel_dp, false); | |
943 | ||
773538e8 | 944 | pps_unlock(intel_dp); |
e39b999a | 945 | |
9ee32fea | 946 | return ret; |
a4fc5ed6 KP |
947 | } |
948 | ||
a6c8aff0 JN |
949 | #define BARE_ADDRESS_SIZE 3 |
950 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
9d1a1031 JN |
951 | static ssize_t |
952 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 953 | { |
9d1a1031 JN |
954 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
955 | uint8_t txbuf[20], rxbuf[20]; | |
956 | size_t txsize, rxsize; | |
a4fc5ed6 | 957 | int ret; |
a4fc5ed6 | 958 | |
d2d9cbbd VS |
959 | txbuf[0] = (msg->request << 4) | |
960 | ((msg->address >> 16) & 0xf); | |
961 | txbuf[1] = (msg->address >> 8) & 0xff; | |
9d1a1031 JN |
962 | txbuf[2] = msg->address & 0xff; |
963 | txbuf[3] = msg->size - 1; | |
46a5ae9f | 964 | |
9d1a1031 JN |
965 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
966 | case DP_AUX_NATIVE_WRITE: | |
967 | case DP_AUX_I2C_WRITE: | |
c1e74122 | 968 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
a6c8aff0 | 969 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
a1ddefd8 | 970 | rxsize = 2; /* 0 or 1 data bytes */ |
f51a44b9 | 971 | |
9d1a1031 JN |
972 | if (WARN_ON(txsize > 20)) |
973 | return -E2BIG; | |
a4fc5ed6 | 974 | |
d81a67cc ID |
975 | if (msg->buffer) |
976 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); | |
977 | else | |
978 | WARN_ON(msg->size); | |
a4fc5ed6 | 979 | |
9d1a1031 JN |
980 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
981 | if (ret > 0) { | |
982 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 983 | |
a1ddefd8 JN |
984 | if (ret > 1) { |
985 | /* Number of bytes written in a short write. */ | |
986 | ret = clamp_t(int, rxbuf[1], 0, msg->size); | |
987 | } else { | |
988 | /* Return payload size. */ | |
989 | ret = msg->size; | |
990 | } | |
9d1a1031 JN |
991 | } |
992 | break; | |
46a5ae9f | 993 | |
9d1a1031 JN |
994 | case DP_AUX_NATIVE_READ: |
995 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 996 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 997 | rxsize = msg->size + 1; |
a4fc5ed6 | 998 | |
9d1a1031 JN |
999 | if (WARN_ON(rxsize > 20)) |
1000 | return -E2BIG; | |
a4fc5ed6 | 1001 | |
9d1a1031 JN |
1002 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1003 | if (ret > 0) { | |
1004 | msg->reply = rxbuf[0] >> 4; | |
1005 | /* | |
1006 | * Assume happy day, and copy the data. The caller is | |
1007 | * expected to check msg->reply before touching it. | |
1008 | * | |
1009 | * Return payload size. | |
1010 | */ | |
1011 | ret--; | |
1012 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 1013 | } |
9d1a1031 JN |
1014 | break; |
1015 | ||
1016 | default: | |
1017 | ret = -EINVAL; | |
1018 | break; | |
a4fc5ed6 | 1019 | } |
f51a44b9 | 1020 | |
9d1a1031 | 1021 | return ret; |
a4fc5ed6 KP |
1022 | } |
1023 | ||
f0f59a00 VS |
1024 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1025 | enum port port) | |
da00bdcf VS |
1026 | { |
1027 | switch (port) { | |
1028 | case PORT_B: | |
1029 | case PORT_C: | |
1030 | case PORT_D: | |
1031 | return DP_AUX_CH_CTL(port); | |
1032 | default: | |
1033 | MISSING_CASE(port); | |
1034 | return DP_AUX_CH_CTL(PORT_B); | |
1035 | } | |
1036 | } | |
1037 | ||
f0f59a00 VS |
1038 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
1039 | enum port port, int index) | |
330e20ec VS |
1040 | { |
1041 | switch (port) { | |
1042 | case PORT_B: | |
1043 | case PORT_C: | |
1044 | case PORT_D: | |
1045 | return DP_AUX_CH_DATA(port, index); | |
1046 | default: | |
1047 | MISSING_CASE(port); | |
1048 | return DP_AUX_CH_DATA(PORT_B, index); | |
1049 | } | |
1050 | } | |
1051 | ||
f0f59a00 VS |
1052 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1053 | enum port port) | |
da00bdcf VS |
1054 | { |
1055 | switch (port) { | |
1056 | case PORT_A: | |
1057 | return DP_AUX_CH_CTL(port); | |
1058 | case PORT_B: | |
1059 | case PORT_C: | |
1060 | case PORT_D: | |
1061 | return PCH_DP_AUX_CH_CTL(port); | |
1062 | default: | |
1063 | MISSING_CASE(port); | |
1064 | return DP_AUX_CH_CTL(PORT_A); | |
1065 | } | |
1066 | } | |
1067 | ||
f0f59a00 VS |
1068 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
1069 | enum port port, int index) | |
330e20ec VS |
1070 | { |
1071 | switch (port) { | |
1072 | case PORT_A: | |
1073 | return DP_AUX_CH_DATA(port, index); | |
1074 | case PORT_B: | |
1075 | case PORT_C: | |
1076 | case PORT_D: | |
1077 | return PCH_DP_AUX_CH_DATA(port, index); | |
1078 | default: | |
1079 | MISSING_CASE(port); | |
1080 | return DP_AUX_CH_DATA(PORT_A, index); | |
1081 | } | |
1082 | } | |
1083 | ||
da00bdcf VS |
1084 | /* |
1085 | * On SKL we don't have Aux for port E so we rely | |
1086 | * on VBT to set a proper alternate aux channel. | |
1087 | */ | |
1088 | static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv) | |
1089 | { | |
1090 | const struct ddi_vbt_port_info *info = | |
1091 | &dev_priv->vbt.ddi_port_info[PORT_E]; | |
1092 | ||
1093 | switch (info->alternate_aux_channel) { | |
1094 | case DP_AUX_A: | |
1095 | return PORT_A; | |
1096 | case DP_AUX_B: | |
1097 | return PORT_B; | |
1098 | case DP_AUX_C: | |
1099 | return PORT_C; | |
1100 | case DP_AUX_D: | |
1101 | return PORT_D; | |
1102 | default: | |
1103 | MISSING_CASE(info->alternate_aux_channel); | |
1104 | return PORT_A; | |
1105 | } | |
1106 | } | |
1107 | ||
f0f59a00 VS |
1108 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1109 | enum port port) | |
da00bdcf VS |
1110 | { |
1111 | if (port == PORT_E) | |
1112 | port = skl_porte_aux_port(dev_priv); | |
1113 | ||
1114 | switch (port) { | |
1115 | case PORT_A: | |
1116 | case PORT_B: | |
1117 | case PORT_C: | |
1118 | case PORT_D: | |
1119 | return DP_AUX_CH_CTL(port); | |
1120 | default: | |
1121 | MISSING_CASE(port); | |
1122 | return DP_AUX_CH_CTL(PORT_A); | |
1123 | } | |
1124 | } | |
1125 | ||
f0f59a00 VS |
1126 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
1127 | enum port port, int index) | |
330e20ec VS |
1128 | { |
1129 | if (port == PORT_E) | |
1130 | port = skl_porte_aux_port(dev_priv); | |
1131 | ||
1132 | switch (port) { | |
1133 | case PORT_A: | |
1134 | case PORT_B: | |
1135 | case PORT_C: | |
1136 | case PORT_D: | |
1137 | return DP_AUX_CH_DATA(port, index); | |
1138 | default: | |
1139 | MISSING_CASE(port); | |
1140 | return DP_AUX_CH_DATA(PORT_A, index); | |
1141 | } | |
1142 | } | |
1143 | ||
f0f59a00 VS |
1144 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1145 | enum port port) | |
330e20ec VS |
1146 | { |
1147 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1148 | return skl_aux_ctl_reg(dev_priv, port); | |
1149 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1150 | return ilk_aux_ctl_reg(dev_priv, port); | |
1151 | else | |
1152 | return g4x_aux_ctl_reg(dev_priv, port); | |
1153 | } | |
1154 | ||
f0f59a00 VS |
1155 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
1156 | enum port port, int index) | |
330e20ec VS |
1157 | { |
1158 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1159 | return skl_aux_data_reg(dev_priv, port, index); | |
1160 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1161 | return ilk_aux_data_reg(dev_priv, port, index); | |
1162 | else | |
1163 | return g4x_aux_data_reg(dev_priv, port, index); | |
1164 | } | |
1165 | ||
1166 | static void intel_aux_reg_init(struct intel_dp *intel_dp) | |
1167 | { | |
1168 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); | |
1169 | enum port port = dp_to_dig_port(intel_dp)->port; | |
1170 | int i; | |
1171 | ||
1172 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); | |
1173 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) | |
1174 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); | |
1175 | } | |
1176 | ||
9d1a1031 | 1177 | static void |
a121f4e5 VS |
1178 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
1179 | { | |
a121f4e5 VS |
1180 | kfree(intel_dp->aux.name); |
1181 | } | |
1182 | ||
1183 | static int | |
9d1a1031 JN |
1184 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
1185 | { | |
33ad6626 JN |
1186 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1187 | enum port port = intel_dig_port->port; | |
ab2c0672 DA |
1188 | int ret; |
1189 | ||
330e20ec | 1190 | intel_aux_reg_init(intel_dp); |
8316f337 | 1191 | |
a121f4e5 VS |
1192 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
1193 | if (!intel_dp->aux.name) | |
1194 | return -ENOMEM; | |
1195 | ||
4d32c0d8 | 1196 | intel_dp->aux.dev = connector->base.kdev; |
9d1a1031 | 1197 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
8316f337 | 1198 | |
a121f4e5 VS |
1199 | DRM_DEBUG_KMS("registering %s bus for %s\n", |
1200 | intel_dp->aux.name, | |
0b99836f | 1201 | connector->base.kdev->kobj.name); |
8316f337 | 1202 | |
4f71d0cb | 1203 | ret = drm_dp_aux_register(&intel_dp->aux); |
0b99836f | 1204 | if (ret < 0) { |
4f71d0cb | 1205 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
a121f4e5 VS |
1206 | intel_dp->aux.name, ret); |
1207 | kfree(intel_dp->aux.name); | |
1208 | return ret; | |
ab2c0672 | 1209 | } |
8a5e6aeb | 1210 | |
a121f4e5 | 1211 | return 0; |
a4fc5ed6 KP |
1212 | } |
1213 | ||
fc0f8e25 | 1214 | static int |
12f6a2e2 | 1215 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) |
fc0f8e25 | 1216 | { |
94ca719e VS |
1217 | if (intel_dp->num_sink_rates) { |
1218 | *sink_rates = intel_dp->sink_rates; | |
1219 | return intel_dp->num_sink_rates; | |
fc0f8e25 | 1220 | } |
12f6a2e2 VS |
1221 | |
1222 | *sink_rates = default_rates; | |
1223 | ||
1224 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; | |
fc0f8e25 SJ |
1225 | } |
1226 | ||
e588fa18 | 1227 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
ed63baaf | 1228 | { |
e588fa18 ACO |
1229 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1230 | struct drm_device *dev = dig_port->base.base.dev; | |
1231 | ||
ed63baaf | 1232 | /* WaDisableHBR2:skl */ |
e87a005d | 1233 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0)) |
ed63baaf TS |
1234 | return false; |
1235 | ||
1236 | if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || | |
1237 | (INTEL_INFO(dev)->gen >= 9)) | |
1238 | return true; | |
1239 | else | |
1240 | return false; | |
1241 | } | |
1242 | ||
a8f3ef61 | 1243 | static int |
e588fa18 | 1244 | intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) |
a8f3ef61 | 1245 | { |
e588fa18 ACO |
1246 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1247 | struct drm_device *dev = dig_port->base.base.dev; | |
af7080f5 TS |
1248 | int size; |
1249 | ||
64987fc5 SJ |
1250 | if (IS_BROXTON(dev)) { |
1251 | *source_rates = bxt_rates; | |
af7080f5 | 1252 | size = ARRAY_SIZE(bxt_rates); |
ef11bdb3 | 1253 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
637a9c63 | 1254 | *source_rates = skl_rates; |
af7080f5 TS |
1255 | size = ARRAY_SIZE(skl_rates); |
1256 | } else { | |
1257 | *source_rates = default_rates; | |
1258 | size = ARRAY_SIZE(default_rates); | |
a8f3ef61 | 1259 | } |
636280ba | 1260 | |
ed63baaf | 1261 | /* This depends on the fact that 5.4 is last value in the array */ |
e588fa18 | 1262 | if (!intel_dp_source_supports_hbr2(intel_dp)) |
af7080f5 | 1263 | size--; |
636280ba | 1264 | |
af7080f5 | 1265 | return size; |
a8f3ef61 SJ |
1266 | } |
1267 | ||
c6bb3538 DV |
1268 | static void |
1269 | intel_dp_set_clock(struct intel_encoder *encoder, | |
840b32b7 | 1270 | struct intel_crtc_state *pipe_config) |
c6bb3538 DV |
1271 | { |
1272 | struct drm_device *dev = encoder->base.dev; | |
9dd4ffdf CML |
1273 | const struct dp_link_dpll *divisor = NULL; |
1274 | int i, count = 0; | |
c6bb3538 DV |
1275 | |
1276 | if (IS_G4X(dev)) { | |
9dd4ffdf CML |
1277 | divisor = gen4_dpll; |
1278 | count = ARRAY_SIZE(gen4_dpll); | |
c6bb3538 | 1279 | } else if (HAS_PCH_SPLIT(dev)) { |
9dd4ffdf CML |
1280 | divisor = pch_dpll; |
1281 | count = ARRAY_SIZE(pch_dpll); | |
ef9348c8 CML |
1282 | } else if (IS_CHERRYVIEW(dev)) { |
1283 | divisor = chv_dpll; | |
1284 | count = ARRAY_SIZE(chv_dpll); | |
c6bb3538 | 1285 | } else if (IS_VALLEYVIEW(dev)) { |
65ce4bf5 CML |
1286 | divisor = vlv_dpll; |
1287 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 1288 | } |
9dd4ffdf CML |
1289 | |
1290 | if (divisor && count) { | |
1291 | for (i = 0; i < count; i++) { | |
840b32b7 | 1292 | if (pipe_config->port_clock == divisor[i].clock) { |
9dd4ffdf CML |
1293 | pipe_config->dpll = divisor[i].dpll; |
1294 | pipe_config->clock_set = true; | |
1295 | break; | |
1296 | } | |
1297 | } | |
c6bb3538 DV |
1298 | } |
1299 | } | |
1300 | ||
2ecae76a VS |
1301 | static int intersect_rates(const int *source_rates, int source_len, |
1302 | const int *sink_rates, int sink_len, | |
94ca719e | 1303 | int *common_rates) |
a8f3ef61 SJ |
1304 | { |
1305 | int i = 0, j = 0, k = 0; | |
1306 | ||
a8f3ef61 SJ |
1307 | while (i < source_len && j < sink_len) { |
1308 | if (source_rates[i] == sink_rates[j]) { | |
e6bda3e4 VS |
1309 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
1310 | return k; | |
94ca719e | 1311 | common_rates[k] = source_rates[i]; |
a8f3ef61 SJ |
1312 | ++k; |
1313 | ++i; | |
1314 | ++j; | |
1315 | } else if (source_rates[i] < sink_rates[j]) { | |
1316 | ++i; | |
1317 | } else { | |
1318 | ++j; | |
1319 | } | |
1320 | } | |
1321 | return k; | |
1322 | } | |
1323 | ||
94ca719e VS |
1324 | static int intel_dp_common_rates(struct intel_dp *intel_dp, |
1325 | int *common_rates) | |
2ecae76a | 1326 | { |
2ecae76a VS |
1327 | const int *source_rates, *sink_rates; |
1328 | int source_len, sink_len; | |
1329 | ||
1330 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); | |
e588fa18 | 1331 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
2ecae76a VS |
1332 | |
1333 | return intersect_rates(source_rates, source_len, | |
1334 | sink_rates, sink_len, | |
94ca719e | 1335 | common_rates); |
2ecae76a VS |
1336 | } |
1337 | ||
0336400e VS |
1338 | static void snprintf_int_array(char *str, size_t len, |
1339 | const int *array, int nelem) | |
1340 | { | |
1341 | int i; | |
1342 | ||
1343 | str[0] = '\0'; | |
1344 | ||
1345 | for (i = 0; i < nelem; i++) { | |
b2f505be | 1346 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
0336400e VS |
1347 | if (r >= len) |
1348 | return; | |
1349 | str += r; | |
1350 | len -= r; | |
1351 | } | |
1352 | } | |
1353 | ||
1354 | static void intel_dp_print_rates(struct intel_dp *intel_dp) | |
1355 | { | |
0336400e | 1356 | const int *source_rates, *sink_rates; |
94ca719e VS |
1357 | int source_len, sink_len, common_len; |
1358 | int common_rates[DP_MAX_SUPPORTED_RATES]; | |
0336400e VS |
1359 | char str[128]; /* FIXME: too big for stack? */ |
1360 | ||
1361 | if ((drm_debug & DRM_UT_KMS) == 0) | |
1362 | return; | |
1363 | ||
e588fa18 | 1364 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
0336400e VS |
1365 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
1366 | DRM_DEBUG_KMS("source rates: %s\n", str); | |
1367 | ||
1368 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); | |
1369 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); | |
1370 | DRM_DEBUG_KMS("sink rates: %s\n", str); | |
1371 | ||
94ca719e VS |
1372 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1373 | snprintf_int_array(str, sizeof(str), common_rates, common_len); | |
1374 | DRM_DEBUG_KMS("common rates: %s\n", str); | |
0336400e VS |
1375 | } |
1376 | ||
f4896f15 | 1377 | static int rate_to_index(int find, const int *rates) |
a8f3ef61 SJ |
1378 | { |
1379 | int i = 0; | |
1380 | ||
1381 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) | |
1382 | if (find == rates[i]) | |
1383 | break; | |
1384 | ||
1385 | return i; | |
1386 | } | |
1387 | ||
50fec21a VS |
1388 | int |
1389 | intel_dp_max_link_rate(struct intel_dp *intel_dp) | |
1390 | { | |
1391 | int rates[DP_MAX_SUPPORTED_RATES] = {}; | |
1392 | int len; | |
1393 | ||
94ca719e | 1394 | len = intel_dp_common_rates(intel_dp, rates); |
50fec21a VS |
1395 | if (WARN_ON(len <= 0)) |
1396 | return 162000; | |
1397 | ||
1398 | return rates[rate_to_index(0, rates) - 1]; | |
1399 | } | |
1400 | ||
ed4e9c1d VS |
1401 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1402 | { | |
94ca719e | 1403 | return rate_to_index(rate, intel_dp->sink_rates); |
ed4e9c1d VS |
1404 | } |
1405 | ||
94223d04 ACO |
1406 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1407 | uint8_t *link_bw, uint8_t *rate_select) | |
04a60f9f VS |
1408 | { |
1409 | if (intel_dp->num_sink_rates) { | |
1410 | *link_bw = 0; | |
1411 | *rate_select = | |
1412 | intel_dp_rate_select(intel_dp, port_clock); | |
1413 | } else { | |
1414 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); | |
1415 | *rate_select = 0; | |
1416 | } | |
1417 | } | |
1418 | ||
00c09d70 | 1419 | bool |
5bfe2ac0 | 1420 | intel_dp_compute_config(struct intel_encoder *encoder, |
5cec258b | 1421 | struct intel_crtc_state *pipe_config) |
a4fc5ed6 | 1422 | { |
5bfe2ac0 | 1423 | struct drm_device *dev = encoder->base.dev; |
36008365 | 1424 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 1425 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
5bfe2ac0 | 1426 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1427 | enum port port = dp_to_dig_port(intel_dp)->port; |
84556d58 | 1428 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
dd06f90e | 1429 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
a4fc5ed6 | 1430 | int lane_count, clock; |
56071a20 | 1431 | int min_lane_count = 1; |
eeb6324d | 1432 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
06ea66b6 | 1433 | /* Conveniently, the link BW constants become indices with a shift...*/ |
56071a20 | 1434 | int min_clock = 0; |
a8f3ef61 | 1435 | int max_clock; |
083f9560 | 1436 | int bpp, mode_rate; |
ff9a6750 | 1437 | int link_avail, link_clock; |
94ca719e VS |
1438 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
1439 | int common_len; | |
04a60f9f | 1440 | uint8_t link_bw, rate_select; |
a8f3ef61 | 1441 | |
94ca719e | 1442 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
a8f3ef61 SJ |
1443 | |
1444 | /* No common link rates between source and sink */ | |
94ca719e | 1445 | WARN_ON(common_len <= 0); |
a8f3ef61 | 1446 | |
94ca719e | 1447 | max_clock = common_len - 1; |
a4fc5ed6 | 1448 | |
bc7d38a4 | 1449 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
5bfe2ac0 DV |
1450 | pipe_config->has_pch_encoder = true; |
1451 | ||
03afc4a2 | 1452 | pipe_config->has_dp_encoder = true; |
f769cd24 | 1453 | pipe_config->has_drrs = false; |
9fcb1704 | 1454 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
a4fc5ed6 | 1455 | |
dd06f90e JN |
1456 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
1457 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
1458 | adjusted_mode); | |
a1b2278e CK |
1459 | |
1460 | if (INTEL_INFO(dev)->gen >= 9) { | |
1461 | int ret; | |
e435d6e5 | 1462 | ret = skl_update_scaler_crtc(pipe_config); |
a1b2278e CK |
1463 | if (ret) |
1464 | return ret; | |
1465 | } | |
1466 | ||
b5667627 | 1467 | if (HAS_GMCH_DISPLAY(dev)) |
2dd24552 JB |
1468 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
1469 | intel_connector->panel.fitting_mode); | |
1470 | else | |
b074cec8 JB |
1471 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
1472 | intel_connector->panel.fitting_mode); | |
0d3a1bee ZY |
1473 | } |
1474 | ||
cb1793ce | 1475 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
1476 | return false; |
1477 | ||
083f9560 | 1478 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
a8f3ef61 | 1479 | "max bw %d pixel clock %iKHz\n", |
94ca719e | 1480 | max_lane_count, common_rates[max_clock], |
241bfc38 | 1481 | adjusted_mode->crtc_clock); |
083f9560 | 1482 | |
36008365 DV |
1483 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1484 | * bpc in between. */ | |
3e7ca985 | 1485 | bpp = pipe_config->pipe_bpp; |
56071a20 | 1486 | if (is_edp(intel_dp)) { |
22ce5628 TS |
1487 | |
1488 | /* Get bpp from vbt only for panels that dont have bpp in edid */ | |
1489 | if (intel_connector->base.display_info.bpc == 0 && | |
6aa23e65 | 1490 | (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { |
56071a20 | 1491 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
6aa23e65 JN |
1492 | dev_priv->vbt.edp.bpp); |
1493 | bpp = dev_priv->vbt.edp.bpp; | |
56071a20 JN |
1494 | } |
1495 | ||
344c5bbc JN |
1496 | /* |
1497 | * Use the maximum clock and number of lanes the eDP panel | |
1498 | * advertizes being capable of. The panels are generally | |
1499 | * designed to support only a single clock and lane | |
1500 | * configuration, and typically these values correspond to the | |
1501 | * native resolution of the panel. | |
1502 | */ | |
1503 | min_lane_count = max_lane_count; | |
1504 | min_clock = max_clock; | |
7984211e | 1505 | } |
657445fe | 1506 | |
36008365 | 1507 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
1508 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1509 | bpp); | |
36008365 | 1510 | |
c6930992 | 1511 | for (clock = min_clock; clock <= max_clock; clock++) { |
a8f3ef61 SJ |
1512 | for (lane_count = min_lane_count; |
1513 | lane_count <= max_lane_count; | |
1514 | lane_count <<= 1) { | |
1515 | ||
94ca719e | 1516 | link_clock = common_rates[clock]; |
36008365 DV |
1517 | link_avail = intel_dp_max_data_rate(link_clock, |
1518 | lane_count); | |
1519 | ||
1520 | if (mode_rate <= link_avail) { | |
1521 | goto found; | |
1522 | } | |
1523 | } | |
1524 | } | |
1525 | } | |
c4867936 | 1526 | |
36008365 | 1527 | return false; |
3685a8f3 | 1528 | |
36008365 | 1529 | found: |
55bc60db VS |
1530 | if (intel_dp->color_range_auto) { |
1531 | /* | |
1532 | * See: | |
1533 | * CEA-861-E - 5.1 Default Encoding Parameters | |
1534 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
1535 | */ | |
0f2a2a75 VS |
1536 | pipe_config->limited_color_range = |
1537 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; | |
1538 | } else { | |
1539 | pipe_config->limited_color_range = | |
1540 | intel_dp->limited_color_range; | |
55bc60db VS |
1541 | } |
1542 | ||
90a6b7b0 | 1543 | pipe_config->lane_count = lane_count; |
a8f3ef61 | 1544 | |
657445fe | 1545 | pipe_config->pipe_bpp = bpp; |
94ca719e | 1546 | pipe_config->port_clock = common_rates[clock]; |
a4fc5ed6 | 1547 | |
04a60f9f VS |
1548 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
1549 | &link_bw, &rate_select); | |
1550 | ||
1551 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", | |
1552 | link_bw, rate_select, pipe_config->lane_count, | |
ff9a6750 | 1553 | pipe_config->port_clock, bpp); |
36008365 DV |
1554 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1555 | mode_rate, link_avail); | |
a4fc5ed6 | 1556 | |
03afc4a2 | 1557 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
1558 | adjusted_mode->crtc_clock, |
1559 | pipe_config->port_clock, | |
03afc4a2 | 1560 | &pipe_config->dp_m_n); |
9d1a455b | 1561 | |
439d7ac0 | 1562 | if (intel_connector->panel.downclock_mode != NULL && |
96178eeb | 1563 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
f769cd24 | 1564 | pipe_config->has_drrs = true; |
439d7ac0 PB |
1565 | intel_link_compute_m_n(bpp, lane_count, |
1566 | intel_connector->panel.downclock_mode->clock, | |
1567 | pipe_config->port_clock, | |
1568 | &pipe_config->dp_m2_n2); | |
1569 | } | |
1570 | ||
14d41b3b VS |
1571 | /* |
1572 | * DPLL0 VCO may need to be adjusted to get the correct | |
1573 | * clock for eDP. This will affect cdclk as well. | |
1574 | */ | |
1575 | if (is_edp(intel_dp) && | |
1576 | (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) { | |
1577 | int vco; | |
1578 | ||
1579 | switch (pipe_config->port_clock / 2) { | |
1580 | case 108000: | |
1581 | case 216000: | |
63911d72 | 1582 | vco = 8640000; |
14d41b3b VS |
1583 | break; |
1584 | default: | |
63911d72 | 1585 | vco = 8100000; |
14d41b3b VS |
1586 | break; |
1587 | } | |
1588 | ||
1589 | to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco; | |
1590 | } | |
1591 | ||
a3c988ea | 1592 | if (!HAS_DDI(dev)) |
840b32b7 | 1593 | intel_dp_set_clock(encoder, pipe_config); |
c6bb3538 | 1594 | |
03afc4a2 | 1595 | return true; |
a4fc5ed6 KP |
1596 | } |
1597 | ||
901c2daf VS |
1598 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
1599 | const struct intel_crtc_state *pipe_config) | |
1600 | { | |
1601 | intel_dp->link_rate = pipe_config->port_clock; | |
1602 | intel_dp->lane_count = pipe_config->lane_count; | |
1603 | } | |
1604 | ||
8ac33ed3 | 1605 | static void intel_dp_prepare(struct intel_encoder *encoder) |
a4fc5ed6 | 1606 | { |
b934223d | 1607 | struct drm_device *dev = encoder->base.dev; |
417e822d | 1608 | struct drm_i915_private *dev_priv = dev->dev_private; |
b934223d | 1609 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1610 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d | 1611 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
7c5f93b0 | 1612 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
a4fc5ed6 | 1613 | |
901c2daf VS |
1614 | intel_dp_set_link_params(intel_dp, crtc->config); |
1615 | ||
417e822d | 1616 | /* |
1a2eb460 | 1617 | * There are four kinds of DP registers: |
417e822d KP |
1618 | * |
1619 | * IBX PCH | |
1a2eb460 KP |
1620 | * SNB CPU |
1621 | * IVB CPU | |
417e822d KP |
1622 | * CPT PCH |
1623 | * | |
1624 | * IBX PCH and CPU are the same for almost everything, | |
1625 | * except that the CPU DP PLL is configured in this | |
1626 | * register | |
1627 | * | |
1628 | * CPT PCH is quite different, having many bits moved | |
1629 | * to the TRANS_DP_CTL register instead. That | |
1630 | * configuration happens (oddly) in ironlake_pch_enable | |
1631 | */ | |
9c9e7927 | 1632 | |
417e822d KP |
1633 | /* Preserve the BIOS-computed detected bit. This is |
1634 | * supposed to be read-only. | |
1635 | */ | |
1636 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 1637 | |
417e822d | 1638 | /* Handle DP bits in common between all three register formats */ |
417e822d | 1639 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
90a6b7b0 | 1640 | intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count); |
a4fc5ed6 | 1641 | |
417e822d | 1642 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 1643 | |
39e5fa88 | 1644 | if (IS_GEN7(dev) && port == PORT_A) { |
1a2eb460 KP |
1645 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1646 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1647 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1648 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1649 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
1650 | ||
6aba5b6c | 1651 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
1652 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1653 | ||
7c62a164 | 1654 | intel_dp->DP |= crtc->pipe << 29; |
39e5fa88 | 1655 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
e3ef4479 VS |
1656 | u32 trans_dp; |
1657 | ||
39e5fa88 | 1658 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3ef4479 VS |
1659 | |
1660 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
1661 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
1662 | trans_dp |= TRANS_DP_ENH_FRAMING; | |
1663 | else | |
1664 | trans_dp &= ~TRANS_DP_ENH_FRAMING; | |
1665 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); | |
39e5fa88 | 1666 | } else { |
0f2a2a75 | 1667 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
666a4537 | 1668 | !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range) |
0f2a2a75 | 1669 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
417e822d KP |
1670 | |
1671 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
1672 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1673 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1674 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1675 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
1676 | ||
6aba5b6c | 1677 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
1678 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1679 | ||
39e5fa88 | 1680 | if (IS_CHERRYVIEW(dev)) |
44f37d1f | 1681 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
39e5fa88 VS |
1682 | else if (crtc->pipe == PIPE_B) |
1683 | intel_dp->DP |= DP_PIPEB_SELECT; | |
32f9d658 | 1684 | } |
a4fc5ed6 KP |
1685 | } |
1686 | ||
ffd6749d PZ |
1687 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1688 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 1689 | |
1a5ef5b7 PZ |
1690 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1691 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 1692 | |
ffd6749d PZ |
1693 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1694 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 1695 | |
4be73780 | 1696 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
1697 | u32 mask, |
1698 | u32 value) | |
bd943159 | 1699 | { |
30add22d | 1700 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
99ea7127 | 1701 | struct drm_i915_private *dev_priv = dev->dev_private; |
f0f59a00 | 1702 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
453c5420 | 1703 | |
e39b999a VS |
1704 | lockdep_assert_held(&dev_priv->pps_mutex); |
1705 | ||
bf13e81b JN |
1706 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1707 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 1708 | |
99ea7127 | 1709 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
1710 | mask, value, |
1711 | I915_READ(pp_stat_reg), | |
1712 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1713 | |
3f177625 TU |
1714 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, |
1715 | 5 * USEC_PER_SEC, 10 * USEC_PER_MSEC)) | |
99ea7127 | 1716 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
1717 | I915_READ(pp_stat_reg), |
1718 | I915_READ(pp_ctrl_reg)); | |
54c136d4 CW |
1719 | |
1720 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 1721 | } |
32ce697c | 1722 | |
4be73780 | 1723 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
1724 | { |
1725 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 1726 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
1727 | } |
1728 | ||
4be73780 | 1729 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
1730 | { |
1731 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 1732 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
1733 | } |
1734 | ||
4be73780 | 1735 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 | 1736 | { |
d28d4731 AK |
1737 | ktime_t panel_power_on_time; |
1738 | s64 panel_power_off_duration; | |
1739 | ||
99ea7127 | 1740 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
dce56b3c | 1741 | |
d28d4731 AK |
1742 | /* take the difference of currrent time and panel power off time |
1743 | * and then make panel wait for t11_t12 if needed. */ | |
1744 | panel_power_on_time = ktime_get_boottime(); | |
1745 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); | |
1746 | ||
dce56b3c PZ |
1747 | /* When we disable the VDD override bit last we have to do the manual |
1748 | * wait. */ | |
d28d4731 AK |
1749 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
1750 | wait_remaining_ms_from_jiffies(jiffies, | |
1751 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); | |
dce56b3c | 1752 | |
4be73780 | 1753 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
1754 | } |
1755 | ||
4be73780 | 1756 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
1757 | { |
1758 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
1759 | intel_dp->backlight_on_delay); | |
1760 | } | |
1761 | ||
4be73780 | 1762 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
1763 | { |
1764 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
1765 | intel_dp->backlight_off_delay); | |
1766 | } | |
99ea7127 | 1767 | |
832dd3c1 KP |
1768 | /* Read the current pp_control value, unlocking the register if it |
1769 | * is locked | |
1770 | */ | |
1771 | ||
453c5420 | 1772 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 1773 | { |
453c5420 JB |
1774 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1775 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1776 | u32 control; | |
832dd3c1 | 1777 | |
e39b999a VS |
1778 | lockdep_assert_held(&dev_priv->pps_mutex); |
1779 | ||
bf13e81b | 1780 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
b0a08bec VK |
1781 | if (!IS_BROXTON(dev)) { |
1782 | control &= ~PANEL_UNLOCK_MASK; | |
1783 | control |= PANEL_UNLOCK_REGS; | |
1784 | } | |
832dd3c1 | 1785 | return control; |
bd943159 KP |
1786 | } |
1787 | ||
951468f3 VS |
1788 | /* |
1789 | * Must be paired with edp_panel_vdd_off(). | |
1790 | * Must hold pps_mutex around the whole on/off sequence. | |
1791 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
1792 | */ | |
1e0560e0 | 1793 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 1794 | { |
30add22d | 1795 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4e6e1a54 ID |
1796 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1797 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
5d613501 | 1798 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e6e1a54 | 1799 | enum intel_display_power_domain power_domain; |
5d613501 | 1800 | u32 pp; |
f0f59a00 | 1801 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 1802 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 1803 | |
e39b999a VS |
1804 | lockdep_assert_held(&dev_priv->pps_mutex); |
1805 | ||
97af61f5 | 1806 | if (!is_edp(intel_dp)) |
adddaaf4 | 1807 | return false; |
bd943159 | 1808 | |
2c623c11 | 1809 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
bd943159 | 1810 | intel_dp->want_panel_vdd = true; |
99ea7127 | 1811 | |
4be73780 | 1812 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 1813 | return need_to_disable; |
b0665d57 | 1814 | |
25f78f58 | 1815 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4e6e1a54 | 1816 | intel_display_power_get(dev_priv, power_domain); |
e9cb81a2 | 1817 | |
3936fcf4 VS |
1818 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
1819 | port_name(intel_dig_port->port)); | |
bd943159 | 1820 | |
4be73780 DV |
1821 | if (!edp_have_panel_power(intel_dp)) |
1822 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 1823 | |
453c5420 | 1824 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 1825 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 1826 | |
bf13e81b JN |
1827 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1828 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
1829 | |
1830 | I915_WRITE(pp_ctrl_reg, pp); | |
1831 | POSTING_READ(pp_ctrl_reg); | |
1832 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1833 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
1834 | /* |
1835 | * If the panel wasn't on, delay before accessing aux channel | |
1836 | */ | |
4be73780 | 1837 | if (!edp_have_panel_power(intel_dp)) { |
3936fcf4 VS |
1838 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
1839 | port_name(intel_dig_port->port)); | |
f01eca2e | 1840 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 1841 | } |
adddaaf4 JN |
1842 | |
1843 | return need_to_disable; | |
1844 | } | |
1845 | ||
951468f3 VS |
1846 | /* |
1847 | * Must be paired with intel_edp_panel_vdd_off() or | |
1848 | * intel_edp_panel_off(). | |
1849 | * Nested calls to these functions are not allowed since | |
1850 | * we drop the lock. Caller must use some higher level | |
1851 | * locking to prevent nested calls from other threads. | |
1852 | */ | |
b80d6c78 | 1853 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 | 1854 | { |
c695b6b6 | 1855 | bool vdd; |
adddaaf4 | 1856 | |
c695b6b6 VS |
1857 | if (!is_edp(intel_dp)) |
1858 | return; | |
1859 | ||
773538e8 | 1860 | pps_lock(intel_dp); |
c695b6b6 | 1861 | vdd = edp_panel_vdd_on(intel_dp); |
773538e8 | 1862 | pps_unlock(intel_dp); |
c695b6b6 | 1863 | |
e2c719b7 | 1864 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
3936fcf4 | 1865 | port_name(dp_to_dig_port(intel_dp)->port)); |
5d613501 JB |
1866 | } |
1867 | ||
4be73780 | 1868 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 1869 | { |
30add22d | 1870 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5d613501 | 1871 | struct drm_i915_private *dev_priv = dev->dev_private; |
be2c9196 VS |
1872 | struct intel_digital_port *intel_dig_port = |
1873 | dp_to_dig_port(intel_dp); | |
1874 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1875 | enum intel_display_power_domain power_domain; | |
5d613501 | 1876 | u32 pp; |
f0f59a00 | 1877 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
5d613501 | 1878 | |
e39b999a | 1879 | lockdep_assert_held(&dev_priv->pps_mutex); |
a0e99e68 | 1880 | |
15e899a0 | 1881 | WARN_ON(intel_dp->want_panel_vdd); |
4e6e1a54 | 1882 | |
15e899a0 | 1883 | if (!edp_have_panel_vdd(intel_dp)) |
be2c9196 | 1884 | return; |
b0665d57 | 1885 | |
3936fcf4 VS |
1886 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
1887 | port_name(intel_dig_port->port)); | |
bd943159 | 1888 | |
be2c9196 VS |
1889 | pp = ironlake_get_pp_control(intel_dp); |
1890 | pp &= ~EDP_FORCE_VDD; | |
453c5420 | 1891 | |
be2c9196 VS |
1892 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1893 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
99ea7127 | 1894 | |
be2c9196 VS |
1895 | I915_WRITE(pp_ctrl_reg, pp); |
1896 | POSTING_READ(pp_ctrl_reg); | |
90791a5c | 1897 | |
be2c9196 VS |
1898 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1899 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1900 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
e9cb81a2 | 1901 | |
be2c9196 | 1902 | if ((pp & POWER_TARGET_ON) == 0) |
d28d4731 | 1903 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
e9cb81a2 | 1904 | |
25f78f58 | 1905 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
be2c9196 | 1906 | intel_display_power_put(dev_priv, power_domain); |
bd943159 | 1907 | } |
5d613501 | 1908 | |
4be73780 | 1909 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
1910 | { |
1911 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
1912 | struct intel_dp, panel_vdd_work); | |
bd943159 | 1913 | |
773538e8 | 1914 | pps_lock(intel_dp); |
15e899a0 VS |
1915 | if (!intel_dp->want_panel_vdd) |
1916 | edp_panel_vdd_off_sync(intel_dp); | |
773538e8 | 1917 | pps_unlock(intel_dp); |
bd943159 KP |
1918 | } |
1919 | ||
aba86890 ID |
1920 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
1921 | { | |
1922 | unsigned long delay; | |
1923 | ||
1924 | /* | |
1925 | * Queue the timer to fire a long time from now (relative to the power | |
1926 | * down delay) to keep the panel power up across a sequence of | |
1927 | * operations. | |
1928 | */ | |
1929 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); | |
1930 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); | |
1931 | } | |
1932 | ||
951468f3 VS |
1933 | /* |
1934 | * Must be paired with edp_panel_vdd_on(). | |
1935 | * Must hold pps_mutex around the whole on/off sequence. | |
1936 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
1937 | */ | |
4be73780 | 1938 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 1939 | { |
e39b999a VS |
1940 | struct drm_i915_private *dev_priv = |
1941 | intel_dp_to_dev(intel_dp)->dev_private; | |
1942 | ||
1943 | lockdep_assert_held(&dev_priv->pps_mutex); | |
1944 | ||
97af61f5 KP |
1945 | if (!is_edp(intel_dp)) |
1946 | return; | |
5d613501 | 1947 | |
e2c719b7 | 1948 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
3936fcf4 | 1949 | port_name(dp_to_dig_port(intel_dp)->port)); |
f2e8b18a | 1950 | |
bd943159 KP |
1951 | intel_dp->want_panel_vdd = false; |
1952 | ||
aba86890 | 1953 | if (sync) |
4be73780 | 1954 | edp_panel_vdd_off_sync(intel_dp); |
aba86890 ID |
1955 | else |
1956 | edp_panel_vdd_schedule_off(intel_dp); | |
5d613501 JB |
1957 | } |
1958 | ||
9f0fb5be | 1959 | static void edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 1960 | { |
30add22d | 1961 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1962 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1963 | u32 pp; |
f0f59a00 | 1964 | i915_reg_t pp_ctrl_reg; |
9934c132 | 1965 | |
9f0fb5be VS |
1966 | lockdep_assert_held(&dev_priv->pps_mutex); |
1967 | ||
97af61f5 | 1968 | if (!is_edp(intel_dp)) |
bd943159 | 1969 | return; |
99ea7127 | 1970 | |
3936fcf4 VS |
1971 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
1972 | port_name(dp_to_dig_port(intel_dp)->port)); | |
e39b999a | 1973 | |
e7a89ace VS |
1974 | if (WARN(edp_have_panel_power(intel_dp), |
1975 | "eDP port %c panel power already on\n", | |
1976 | port_name(dp_to_dig_port(intel_dp)->port))) | |
9f0fb5be | 1977 | return; |
9934c132 | 1978 | |
4be73780 | 1979 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 1980 | |
bf13e81b | 1981 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 1982 | pp = ironlake_get_pp_control(intel_dp); |
05ce1a49 KP |
1983 | if (IS_GEN5(dev)) { |
1984 | /* ILK workaround: disable reset around power sequence */ | |
1985 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
1986 | I915_WRITE(pp_ctrl_reg, pp); |
1987 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1988 | } |
37c6c9b0 | 1989 | |
1c0ae80a | 1990 | pp |= POWER_TARGET_ON; |
99ea7127 KP |
1991 | if (!IS_GEN5(dev)) |
1992 | pp |= PANEL_POWER_RESET; | |
1993 | ||
453c5420 JB |
1994 | I915_WRITE(pp_ctrl_reg, pp); |
1995 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1996 | |
4be73780 | 1997 | wait_panel_on(intel_dp); |
dce56b3c | 1998 | intel_dp->last_power_on = jiffies; |
9934c132 | 1999 | |
05ce1a49 KP |
2000 | if (IS_GEN5(dev)) { |
2001 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
bf13e81b JN |
2002 | I915_WRITE(pp_ctrl_reg, pp); |
2003 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2004 | } |
9f0fb5be | 2005 | } |
e39b999a | 2006 | |
9f0fb5be VS |
2007 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
2008 | { | |
2009 | if (!is_edp(intel_dp)) | |
2010 | return; | |
2011 | ||
2012 | pps_lock(intel_dp); | |
2013 | edp_panel_on(intel_dp); | |
773538e8 | 2014 | pps_unlock(intel_dp); |
9934c132 JB |
2015 | } |
2016 | ||
9f0fb5be VS |
2017 | |
2018 | static void edp_panel_off(struct intel_dp *intel_dp) | |
9934c132 | 2019 | { |
4e6e1a54 ID |
2020 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2021 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
30add22d | 2022 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 2023 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e6e1a54 | 2024 | enum intel_display_power_domain power_domain; |
99ea7127 | 2025 | u32 pp; |
f0f59a00 | 2026 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2027 | |
9f0fb5be VS |
2028 | lockdep_assert_held(&dev_priv->pps_mutex); |
2029 | ||
97af61f5 KP |
2030 | if (!is_edp(intel_dp)) |
2031 | return; | |
37c6c9b0 | 2032 | |
3936fcf4 VS |
2033 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2034 | port_name(dp_to_dig_port(intel_dp)->port)); | |
37c6c9b0 | 2035 | |
3936fcf4 VS |
2036 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2037 | port_name(dp_to_dig_port(intel_dp)->port)); | |
24f3e092 | 2038 | |
453c5420 | 2039 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
2040 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2041 | * panels get very unhappy and cease to work. */ | |
b3064154 PJ |
2042 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
2043 | EDP_BLC_ENABLE); | |
453c5420 | 2044 | |
bf13e81b | 2045 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2046 | |
849e39f5 PZ |
2047 | intel_dp->want_panel_vdd = false; |
2048 | ||
453c5420 JB |
2049 | I915_WRITE(pp_ctrl_reg, pp); |
2050 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2051 | |
d28d4731 | 2052 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
4be73780 | 2053 | wait_panel_off(intel_dp); |
849e39f5 PZ |
2054 | |
2055 | /* We got a reference when we enabled the VDD. */ | |
25f78f58 | 2056 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4e6e1a54 | 2057 | intel_display_power_put(dev_priv, power_domain); |
9f0fb5be | 2058 | } |
e39b999a | 2059 | |
9f0fb5be VS |
2060 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2061 | { | |
2062 | if (!is_edp(intel_dp)) | |
2063 | return; | |
e39b999a | 2064 | |
9f0fb5be VS |
2065 | pps_lock(intel_dp); |
2066 | edp_panel_off(intel_dp); | |
773538e8 | 2067 | pps_unlock(intel_dp); |
9934c132 JB |
2068 | } |
2069 | ||
1250d107 JN |
2070 | /* Enable backlight in the panel power control. */ |
2071 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) | |
32f9d658 | 2072 | { |
da63a9f2 PZ |
2073 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2074 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
32f9d658 ZW |
2075 | struct drm_i915_private *dev_priv = dev->dev_private; |
2076 | u32 pp; | |
f0f59a00 | 2077 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2078 | |
01cb9ea6 JB |
2079 | /* |
2080 | * If we enable the backlight right away following a panel power | |
2081 | * on, we may see slight flicker as the panel syncs with the eDP | |
2082 | * link. So delay a bit to make sure the image is solid before | |
2083 | * allowing it to appear. | |
2084 | */ | |
4be73780 | 2085 | wait_backlight_on(intel_dp); |
e39b999a | 2086 | |
773538e8 | 2087 | pps_lock(intel_dp); |
e39b999a | 2088 | |
453c5420 | 2089 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2090 | pp |= EDP_BLC_ENABLE; |
453c5420 | 2091 | |
bf13e81b | 2092 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2093 | |
2094 | I915_WRITE(pp_ctrl_reg, pp); | |
2095 | POSTING_READ(pp_ctrl_reg); | |
e39b999a | 2096 | |
773538e8 | 2097 | pps_unlock(intel_dp); |
32f9d658 ZW |
2098 | } |
2099 | ||
1250d107 JN |
2100 | /* Enable backlight PWM and backlight PP control. */ |
2101 | void intel_edp_backlight_on(struct intel_dp *intel_dp) | |
2102 | { | |
2103 | if (!is_edp(intel_dp)) | |
2104 | return; | |
2105 | ||
2106 | DRM_DEBUG_KMS("\n"); | |
2107 | ||
2108 | intel_panel_enable_backlight(intel_dp->attached_connector); | |
2109 | _intel_edp_backlight_on(intel_dp); | |
2110 | } | |
2111 | ||
2112 | /* Disable backlight in the panel power control. */ | |
2113 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) | |
32f9d658 | 2114 | { |
30add22d | 2115 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
32f9d658 ZW |
2116 | struct drm_i915_private *dev_priv = dev->dev_private; |
2117 | u32 pp; | |
f0f59a00 | 2118 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2119 | |
f01eca2e KP |
2120 | if (!is_edp(intel_dp)) |
2121 | return; | |
2122 | ||
773538e8 | 2123 | pps_lock(intel_dp); |
e39b999a | 2124 | |
453c5420 | 2125 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2126 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 2127 | |
bf13e81b | 2128 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2129 | |
2130 | I915_WRITE(pp_ctrl_reg, pp); | |
2131 | POSTING_READ(pp_ctrl_reg); | |
f7d2323c | 2132 | |
773538e8 | 2133 | pps_unlock(intel_dp); |
e39b999a VS |
2134 | |
2135 | intel_dp->last_backlight_off = jiffies; | |
f7d2323c | 2136 | edp_wait_backlight_off(intel_dp); |
1250d107 | 2137 | } |
f7d2323c | 2138 | |
1250d107 JN |
2139 | /* Disable backlight PP control and backlight PWM. */ |
2140 | void intel_edp_backlight_off(struct intel_dp *intel_dp) | |
2141 | { | |
2142 | if (!is_edp(intel_dp)) | |
2143 | return; | |
2144 | ||
2145 | DRM_DEBUG_KMS("\n"); | |
f7d2323c | 2146 | |
1250d107 | 2147 | _intel_edp_backlight_off(intel_dp); |
f7d2323c | 2148 | intel_panel_disable_backlight(intel_dp->attached_connector); |
32f9d658 | 2149 | } |
a4fc5ed6 | 2150 | |
73580fb7 JN |
2151 | /* |
2152 | * Hook for controlling the panel power control backlight through the bl_power | |
2153 | * sysfs attribute. Take care to handle multiple calls. | |
2154 | */ | |
2155 | static void intel_edp_backlight_power(struct intel_connector *connector, | |
2156 | bool enable) | |
2157 | { | |
2158 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); | |
e39b999a VS |
2159 | bool is_enabled; |
2160 | ||
773538e8 | 2161 | pps_lock(intel_dp); |
e39b999a | 2162 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
773538e8 | 2163 | pps_unlock(intel_dp); |
73580fb7 JN |
2164 | |
2165 | if (is_enabled == enable) | |
2166 | return; | |
2167 | ||
23ba9373 JN |
2168 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2169 | enable ? "enable" : "disable"); | |
73580fb7 JN |
2170 | |
2171 | if (enable) | |
2172 | _intel_edp_backlight_on(intel_dp); | |
2173 | else | |
2174 | _intel_edp_backlight_off(intel_dp); | |
2175 | } | |
2176 | ||
64e1077a VS |
2177 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
2178 | { | |
2179 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2180 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
2181 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; | |
2182 | ||
2183 | I915_STATE_WARN(cur_state != state, | |
2184 | "DP port %c state assertion failure (expected %s, current %s)\n", | |
2185 | port_name(dig_port->port), | |
87ad3212 | 2186 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2187 | } |
2188 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) | |
2189 | ||
2190 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) | |
2191 | { | |
2192 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; | |
2193 | ||
2194 | I915_STATE_WARN(cur_state != state, | |
2195 | "eDP PLL state assertion failure (expected %s, current %s)\n", | |
87ad3212 | 2196 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2197 | } |
2198 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) | |
2199 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) | |
2200 | ||
2bd2ad64 | 2201 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
d240f20f | 2202 | { |
da63a9f2 | 2203 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
64e1077a VS |
2204 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2205 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
d240f20f | 2206 | |
64e1077a VS |
2207 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2208 | assert_dp_port_disabled(intel_dp); | |
2209 | assert_edp_pll_disabled(dev_priv); | |
2bd2ad64 | 2210 | |
abfce949 VS |
2211 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
2212 | crtc->config->port_clock); | |
2213 | ||
2214 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; | |
2215 | ||
2216 | if (crtc->config->port_clock == 162000) | |
2217 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; | |
2218 | else | |
2219 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
2220 | ||
2221 | I915_WRITE(DP_A, intel_dp->DP); | |
2222 | POSTING_READ(DP_A); | |
2223 | udelay(500); | |
2224 | ||
6b23f3e8 VS |
2225 | /* |
2226 | * [DevILK] Work around required when enabling DP PLL | |
2227 | * while a pipe is enabled going to FDI: | |
2228 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI | |
2229 | * 2. Program DP PLL enable | |
2230 | */ | |
2231 | if (IS_GEN5(dev_priv)) | |
2232 | intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe); | |
2233 | ||
0767935e | 2234 | intel_dp->DP |= DP_PLL_ENABLE; |
6fec7662 | 2235 | |
0767935e | 2236 | I915_WRITE(DP_A, intel_dp->DP); |
298b0b39 JB |
2237 | POSTING_READ(DP_A); |
2238 | udelay(200); | |
d240f20f JB |
2239 | } |
2240 | ||
2bd2ad64 | 2241 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 2242 | { |
da63a9f2 | 2243 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
64e1077a VS |
2244 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2245 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
d240f20f | 2246 | |
64e1077a VS |
2247 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2248 | assert_dp_port_disabled(intel_dp); | |
2249 | assert_edp_pll_enabled(dev_priv); | |
2bd2ad64 | 2250 | |
abfce949 VS |
2251 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
2252 | ||
6fec7662 | 2253 | intel_dp->DP &= ~DP_PLL_ENABLE; |
0767935e | 2254 | |
6fec7662 | 2255 | I915_WRITE(DP_A, intel_dp->DP); |
1af5fa1b | 2256 | POSTING_READ(DP_A); |
d240f20f JB |
2257 | udelay(200); |
2258 | } | |
2259 | ||
c7ad3810 | 2260 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 2261 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
2262 | { |
2263 | int ret, i; | |
2264 | ||
2265 | /* Should have a valid DPCD by this point */ | |
2266 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
2267 | return; | |
2268 | ||
2269 | if (mode != DRM_MODE_DPMS_ON) { | |
9d1a1031 JN |
2270 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2271 | DP_SET_POWER_D3); | |
c7ad3810 JB |
2272 | } else { |
2273 | /* | |
2274 | * When turning on, we need to retry for 1ms to give the sink | |
2275 | * time to wake up. | |
2276 | */ | |
2277 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
2278 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2279 | DP_SET_POWER_D0); | |
c7ad3810 JB |
2280 | if (ret == 1) |
2281 | break; | |
2282 | msleep(1); | |
2283 | } | |
2284 | } | |
f9cac721 JN |
2285 | |
2286 | if (ret != 1) | |
2287 | DRM_DEBUG_KMS("failed to %s sink power state\n", | |
2288 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); | |
c7ad3810 JB |
2289 | } |
2290 | ||
19d8fe15 DV |
2291 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2292 | enum pipe *pipe) | |
d240f20f | 2293 | { |
19d8fe15 | 2294 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 2295 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 DV |
2296 | struct drm_device *dev = encoder->base.dev; |
2297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d129bea ID |
2298 | enum intel_display_power_domain power_domain; |
2299 | u32 tmp; | |
6fa9a5ec | 2300 | bool ret; |
6d129bea ID |
2301 | |
2302 | power_domain = intel_display_port_power_domain(encoder); | |
6fa9a5ec | 2303 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
2304 | return false; |
2305 | ||
6fa9a5ec ID |
2306 | ret = false; |
2307 | ||
6d129bea | 2308 | tmp = I915_READ(intel_dp->output_reg); |
19d8fe15 DV |
2309 | |
2310 | if (!(tmp & DP_PORT_EN)) | |
6fa9a5ec | 2311 | goto out; |
19d8fe15 | 2312 | |
39e5fa88 | 2313 | if (IS_GEN7(dev) && port == PORT_A) { |
19d8fe15 | 2314 | *pipe = PORT_TO_PIPE_CPT(tmp); |
39e5fa88 | 2315 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
adc289d7 | 2316 | enum pipe p; |
19d8fe15 | 2317 | |
adc289d7 VS |
2318 | for_each_pipe(dev_priv, p) { |
2319 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); | |
2320 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { | |
2321 | *pipe = p; | |
6fa9a5ec ID |
2322 | ret = true; |
2323 | ||
2324 | goto out; | |
19d8fe15 DV |
2325 | } |
2326 | } | |
19d8fe15 | 2327 | |
4a0833ec | 2328 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
f0f59a00 | 2329 | i915_mmio_reg_offset(intel_dp->output_reg)); |
39e5fa88 VS |
2330 | } else if (IS_CHERRYVIEW(dev)) { |
2331 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); | |
2332 | } else { | |
2333 | *pipe = PORT_TO_PIPE(tmp); | |
4a0833ec | 2334 | } |
d240f20f | 2335 | |
6fa9a5ec ID |
2336 | ret = true; |
2337 | ||
2338 | out: | |
2339 | intel_display_power_put(dev_priv, power_domain); | |
2340 | ||
2341 | return ret; | |
19d8fe15 | 2342 | } |
d240f20f | 2343 | |
045ac3b5 | 2344 | static void intel_dp_get_config(struct intel_encoder *encoder, |
5cec258b | 2345 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
2346 | { |
2347 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 2348 | u32 tmp, flags = 0; |
63000ef6 XZ |
2349 | struct drm_device *dev = encoder->base.dev; |
2350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2351 | enum port port = dp_to_dig_port(intel_dp)->port; | |
2352 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
045ac3b5 | 2353 | |
9ed109a7 | 2354 | tmp = I915_READ(intel_dp->output_reg); |
9fcb1704 JN |
2355 | |
2356 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; | |
9ed109a7 | 2357 | |
39e5fa88 | 2358 | if (HAS_PCH_CPT(dev) && port != PORT_A) { |
b81e34c2 VS |
2359 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2360 | ||
2361 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
63000ef6 XZ |
2362 | flags |= DRM_MODE_FLAG_PHSYNC; |
2363 | else | |
2364 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2365 | |
b81e34c2 | 2366 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
63000ef6 XZ |
2367 | flags |= DRM_MODE_FLAG_PVSYNC; |
2368 | else | |
2369 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2370 | } else { | |
39e5fa88 | 2371 | if (tmp & DP_SYNC_HS_HIGH) |
63000ef6 XZ |
2372 | flags |= DRM_MODE_FLAG_PHSYNC; |
2373 | else | |
2374 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2375 | |
39e5fa88 | 2376 | if (tmp & DP_SYNC_VS_HIGH) |
63000ef6 XZ |
2377 | flags |= DRM_MODE_FLAG_PVSYNC; |
2378 | else | |
2379 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2380 | } | |
045ac3b5 | 2381 | |
2d112de7 | 2382 | pipe_config->base.adjusted_mode.flags |= flags; |
f1f644dc | 2383 | |
8c875fca | 2384 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
666a4537 | 2385 | !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235) |
8c875fca VS |
2386 | pipe_config->limited_color_range = true; |
2387 | ||
eb14cb74 VS |
2388 | pipe_config->has_dp_encoder = true; |
2389 | ||
90a6b7b0 VS |
2390 | pipe_config->lane_count = |
2391 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; | |
2392 | ||
eb14cb74 VS |
2393 | intel_dp_get_m_n(crtc, pipe_config); |
2394 | ||
18442d08 | 2395 | if (port == PORT_A) { |
b377e0df | 2396 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
f1f644dc JB |
2397 | pipe_config->port_clock = 162000; |
2398 | else | |
2399 | pipe_config->port_clock = 270000; | |
2400 | } | |
18442d08 | 2401 | |
e3b247da VS |
2402 | pipe_config->base.adjusted_mode.crtc_clock = |
2403 | intel_dotclock_calculate(pipe_config->port_clock, | |
2404 | &pipe_config->dp_m_n); | |
7f16e5c1 | 2405 | |
6aa23e65 JN |
2406 | if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
2407 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { | |
c6cd2ee2 JN |
2408 | /* |
2409 | * This is a big fat ugly hack. | |
2410 | * | |
2411 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2412 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2413 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2414 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2415 | * max, not what it tells us to use. | |
2416 | * | |
2417 | * Note: This will still be broken if the eDP panel is not lit | |
2418 | * up by the BIOS, and thus we can't get the mode at module | |
2419 | * load. | |
2420 | */ | |
2421 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
2422 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
2423 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
c6cd2ee2 | 2424 | } |
045ac3b5 JB |
2425 | } |
2426 | ||
e8cb4558 | 2427 | static void intel_disable_dp(struct intel_encoder *encoder) |
d240f20f | 2428 | { |
e8cb4558 | 2429 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2430 | struct drm_device *dev = encoder->base.dev; |
495a5bb8 JN |
2431 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2432 | ||
6e3c9717 | 2433 | if (crtc->config->has_audio) |
495a5bb8 | 2434 | intel_audio_codec_disable(encoder); |
6cb49835 | 2435 | |
b32c6f48 RV |
2436 | if (HAS_PSR(dev) && !HAS_DDI(dev)) |
2437 | intel_psr_disable(intel_dp); | |
2438 | ||
6cb49835 DV |
2439 | /* Make sure the panel is off before trying to change the mode. But also |
2440 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 2441 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 2442 | intel_edp_backlight_off(intel_dp); |
fdbc3b1f | 2443 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 2444 | intel_edp_panel_off(intel_dp); |
3739850b | 2445 | |
08aff3fe VS |
2446 | /* disable the port before the pipe on g4x */ |
2447 | if (INTEL_INFO(dev)->gen < 5) | |
3739850b | 2448 | intel_dp_link_down(intel_dp); |
d240f20f JB |
2449 | } |
2450 | ||
08aff3fe | 2451 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
d240f20f | 2452 | { |
2bd2ad64 | 2453 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2454 | enum port port = dp_to_dig_port(intel_dp)->port; |
2bd2ad64 | 2455 | |
49277c31 | 2456 | intel_dp_link_down(intel_dp); |
abfce949 VS |
2457 | |
2458 | /* Only ilk+ has port A */ | |
08aff3fe VS |
2459 | if (port == PORT_A) |
2460 | ironlake_edp_pll_off(intel_dp); | |
49277c31 VS |
2461 | } |
2462 | ||
2463 | static void vlv_post_disable_dp(struct intel_encoder *encoder) | |
2464 | { | |
2465 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2466 | ||
2467 | intel_dp_link_down(intel_dp); | |
2bd2ad64 DV |
2468 | } |
2469 | ||
a8f327fb VS |
2470 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
2471 | { | |
2472 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2473 | struct drm_device *dev = encoder->base.dev; | |
2474 | struct drm_i915_private *dev_priv = dev->dev_private; | |
97fd4d5c | 2475 | |
a8f327fb VS |
2476 | intel_dp_link_down(intel_dp); |
2477 | ||
2478 | mutex_lock(&dev_priv->sb_lock); | |
2479 | ||
2480 | /* Assert data lane reset */ | |
2481 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 2482 | |
a580516d | 2483 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
2484 | } |
2485 | ||
7b13b58a VS |
2486 | static void |
2487 | _intel_dp_set_link_train(struct intel_dp *intel_dp, | |
2488 | uint32_t *DP, | |
2489 | uint8_t dp_train_pat) | |
2490 | { | |
2491 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2492 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2493 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2494 | enum port port = intel_dig_port->port; | |
2495 | ||
2496 | if (HAS_DDI(dev)) { | |
2497 | uint32_t temp = I915_READ(DP_TP_CTL(port)); | |
2498 | ||
2499 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2500 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2501 | else | |
2502 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2503 | ||
2504 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2505 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2506 | case DP_TRAINING_PATTERN_DISABLE: | |
2507 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; | |
2508 | ||
2509 | break; | |
2510 | case DP_TRAINING_PATTERN_1: | |
2511 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2512 | break; | |
2513 | case DP_TRAINING_PATTERN_2: | |
2514 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2515 | break; | |
2516 | case DP_TRAINING_PATTERN_3: | |
2517 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2518 | break; | |
2519 | } | |
2520 | I915_WRITE(DP_TP_CTL(port), temp); | |
2521 | ||
39e5fa88 VS |
2522 | } else if ((IS_GEN7(dev) && port == PORT_A) || |
2523 | (HAS_PCH_CPT(dev) && port != PORT_A)) { | |
7b13b58a VS |
2524 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2525 | ||
2526 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2527 | case DP_TRAINING_PATTERN_DISABLE: | |
2528 | *DP |= DP_LINK_TRAIN_OFF_CPT; | |
2529 | break; | |
2530 | case DP_TRAINING_PATTERN_1: | |
2531 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; | |
2532 | break; | |
2533 | case DP_TRAINING_PATTERN_2: | |
2534 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2535 | break; | |
2536 | case DP_TRAINING_PATTERN_3: | |
2537 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
2538 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2539 | break; | |
2540 | } | |
2541 | ||
2542 | } else { | |
2543 | if (IS_CHERRYVIEW(dev)) | |
2544 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; | |
2545 | else | |
2546 | *DP &= ~DP_LINK_TRAIN_MASK; | |
2547 | ||
2548 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2549 | case DP_TRAINING_PATTERN_DISABLE: | |
2550 | *DP |= DP_LINK_TRAIN_OFF; | |
2551 | break; | |
2552 | case DP_TRAINING_PATTERN_1: | |
2553 | *DP |= DP_LINK_TRAIN_PAT_1; | |
2554 | break; | |
2555 | case DP_TRAINING_PATTERN_2: | |
2556 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2557 | break; | |
2558 | case DP_TRAINING_PATTERN_3: | |
2559 | if (IS_CHERRYVIEW(dev)) { | |
2560 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; | |
2561 | } else { | |
2562 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
2563 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2564 | } | |
2565 | break; | |
2566 | } | |
2567 | } | |
2568 | } | |
2569 | ||
2570 | static void intel_dp_enable_port(struct intel_dp *intel_dp) | |
2571 | { | |
2572 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
2573 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6fec7662 VS |
2574 | struct intel_crtc *crtc = |
2575 | to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc); | |
7b13b58a | 2576 | |
7b13b58a VS |
2577 | /* enable with pattern 1 (as per spec) */ |
2578 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, | |
2579 | DP_TRAINING_PATTERN_1); | |
2580 | ||
2581 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2582 | POSTING_READ(intel_dp->output_reg); | |
7b713f50 VS |
2583 | |
2584 | /* | |
2585 | * Magic for VLV/CHV. We _must_ first set up the register | |
2586 | * without actually enabling the port, and then do another | |
2587 | * write to enable the port. Otherwise link training will | |
2588 | * fail when the power sequencer is freshly used for this port. | |
2589 | */ | |
2590 | intel_dp->DP |= DP_PORT_EN; | |
6fec7662 VS |
2591 | if (crtc->config->has_audio) |
2592 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; | |
7b713f50 VS |
2593 | |
2594 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2595 | POSTING_READ(intel_dp->output_reg); | |
580d3811 VS |
2596 | } |
2597 | ||
e8cb4558 | 2598 | static void intel_enable_dp(struct intel_encoder *encoder) |
d240f20f | 2599 | { |
e8cb4558 DV |
2600 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2601 | struct drm_device *dev = encoder->base.dev; | |
2602 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1dec79a | 2603 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
e8cb4558 | 2604 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
d6fbdd15 | 2605 | enum pipe pipe = crtc->pipe; |
5d613501 | 2606 | |
0c33d8d7 DV |
2607 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2608 | return; | |
5d613501 | 2609 | |
093e3f13 VS |
2610 | pps_lock(intel_dp); |
2611 | ||
666a4537 | 2612 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
093e3f13 VS |
2613 | vlv_init_panel_power_sequencer(intel_dp); |
2614 | ||
7b13b58a | 2615 | intel_dp_enable_port(intel_dp); |
093e3f13 VS |
2616 | |
2617 | edp_panel_vdd_on(intel_dp); | |
2618 | edp_panel_on(intel_dp); | |
2619 | edp_panel_vdd_off(intel_dp, true); | |
2620 | ||
2621 | pps_unlock(intel_dp); | |
2622 | ||
666a4537 | 2623 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e0fce78f VS |
2624 | unsigned int lane_mask = 0x0; |
2625 | ||
2626 | if (IS_CHERRYVIEW(dev)) | |
2627 | lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count); | |
2628 | ||
9b6de0a1 VS |
2629 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2630 | lane_mask); | |
e0fce78f | 2631 | } |
61234fa5 | 2632 | |
f01eca2e | 2633 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 2634 | intel_dp_start_link_train(intel_dp); |
3ab9c637 | 2635 | intel_dp_stop_link_train(intel_dp); |
c1dec79a | 2636 | |
6e3c9717 | 2637 | if (crtc->config->has_audio) { |
c1dec79a | 2638 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
d6fbdd15 | 2639 | pipe_name(pipe)); |
c1dec79a JN |
2640 | intel_audio_codec_enable(encoder); |
2641 | } | |
ab1f90f9 | 2642 | } |
89b667f8 | 2643 | |
ecff4f3b JN |
2644 | static void g4x_enable_dp(struct intel_encoder *encoder) |
2645 | { | |
828f5c6e JN |
2646 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2647 | ||
ecff4f3b | 2648 | intel_enable_dp(encoder); |
4be73780 | 2649 | intel_edp_backlight_on(intel_dp); |
ab1f90f9 | 2650 | } |
89b667f8 | 2651 | |
ab1f90f9 JN |
2652 | static void vlv_enable_dp(struct intel_encoder *encoder) |
2653 | { | |
828f5c6e JN |
2654 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2655 | ||
4be73780 | 2656 | intel_edp_backlight_on(intel_dp); |
b32c6f48 | 2657 | intel_psr_enable(intel_dp); |
d240f20f JB |
2658 | } |
2659 | ||
ecff4f3b | 2660 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
ab1f90f9 JN |
2661 | { |
2662 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
d6fbdd15 | 2663 | enum port port = dp_to_dig_port(intel_dp)->port; |
ab1f90f9 | 2664 | |
8ac33ed3 DV |
2665 | intel_dp_prepare(encoder); |
2666 | ||
d41f1efb | 2667 | /* Only ilk+ has port A */ |
abfce949 | 2668 | if (port == PORT_A) |
ab1f90f9 JN |
2669 | ironlake_edp_pll_on(intel_dp); |
2670 | } | |
2671 | ||
83b84597 VS |
2672 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2673 | { | |
2674 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2675 | struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; | |
2676 | enum pipe pipe = intel_dp->pps_pipe; | |
f0f59a00 | 2677 | i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
83b84597 VS |
2678 | |
2679 | edp_panel_vdd_off_sync(intel_dp); | |
2680 | ||
2681 | /* | |
2682 | * VLV seems to get confused when multiple power seqeuencers | |
2683 | * have the same port selected (even if only one has power/vdd | |
2684 | * enabled). The failure manifests as vlv_wait_port_ready() failing | |
2685 | * CHV on the other hand doesn't seem to mind having the same port | |
2686 | * selected in multiple power seqeuencers, but let's clear the | |
2687 | * port select always when logically disconnecting a power sequencer | |
2688 | * from a port. | |
2689 | */ | |
2690 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", | |
2691 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
2692 | I915_WRITE(pp_on_reg, 0); | |
2693 | POSTING_READ(pp_on_reg); | |
2694 | ||
2695 | intel_dp->pps_pipe = INVALID_PIPE; | |
2696 | } | |
2697 | ||
a4a5d2f8 VS |
2698 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2699 | enum pipe pipe) | |
2700 | { | |
2701 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2702 | struct intel_encoder *encoder; | |
2703 | ||
2704 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2705 | ||
ac3c12e4 VS |
2706 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2707 | return; | |
2708 | ||
19c8054c | 2709 | for_each_intel_encoder(dev, encoder) { |
a4a5d2f8 | 2710 | struct intel_dp *intel_dp; |
773538e8 | 2711 | enum port port; |
a4a5d2f8 VS |
2712 | |
2713 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2714 | continue; | |
2715 | ||
2716 | intel_dp = enc_to_intel_dp(&encoder->base); | |
773538e8 | 2717 | port = dp_to_dig_port(intel_dp)->port; |
a4a5d2f8 VS |
2718 | |
2719 | if (intel_dp->pps_pipe != pipe) | |
2720 | continue; | |
2721 | ||
2722 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", | |
773538e8 | 2723 | pipe_name(pipe), port_name(port)); |
a4a5d2f8 | 2724 | |
e02f9a06 | 2725 | WARN(encoder->base.crtc, |
034e43c6 VS |
2726 | "stealing pipe %c power sequencer from active eDP port %c\n", |
2727 | pipe_name(pipe), port_name(port)); | |
a4a5d2f8 | 2728 | |
a4a5d2f8 | 2729 | /* make sure vdd is off before we steal it */ |
83b84597 | 2730 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2731 | } |
2732 | } | |
2733 | ||
2734 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) | |
2735 | { | |
2736 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2737 | struct intel_encoder *encoder = &intel_dig_port->base; | |
2738 | struct drm_device *dev = encoder->base.dev; | |
2739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2740 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
a4a5d2f8 VS |
2741 | |
2742 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2743 | ||
093e3f13 VS |
2744 | if (!is_edp(intel_dp)) |
2745 | return; | |
2746 | ||
a4a5d2f8 VS |
2747 | if (intel_dp->pps_pipe == crtc->pipe) |
2748 | return; | |
2749 | ||
2750 | /* | |
2751 | * If another power sequencer was being used on this | |
2752 | * port previously make sure to turn off vdd there while | |
2753 | * we still have control of it. | |
2754 | */ | |
2755 | if (intel_dp->pps_pipe != INVALID_PIPE) | |
83b84597 | 2756 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2757 | |
2758 | /* | |
2759 | * We may be stealing the power | |
2760 | * sequencer from another port. | |
2761 | */ | |
2762 | vlv_steal_power_sequencer(dev, crtc->pipe); | |
2763 | ||
2764 | /* now it's all ours */ | |
2765 | intel_dp->pps_pipe = crtc->pipe; | |
2766 | ||
2767 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", | |
2768 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); | |
2769 | ||
2770 | /* init power sequencer on this pipe and port */ | |
36b5f425 VS |
2771 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
2772 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
a4a5d2f8 VS |
2773 | } |
2774 | ||
ab1f90f9 | 2775 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
a4fc5ed6 | 2776 | { |
5f68c275 | 2777 | vlv_phy_pre_encoder_enable(encoder); |
ab1f90f9 JN |
2778 | |
2779 | intel_enable_dp(encoder); | |
89b667f8 JB |
2780 | } |
2781 | ||
ecff4f3b | 2782 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 | 2783 | { |
8ac33ed3 DV |
2784 | intel_dp_prepare(encoder); |
2785 | ||
6da2e616 | 2786 | vlv_phy_pre_pll_enable(encoder); |
a4fc5ed6 KP |
2787 | } |
2788 | ||
e4a1d846 CML |
2789 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
2790 | { | |
e7d2a717 | 2791 | chv_phy_pre_encoder_enable(encoder); |
e4a1d846 | 2792 | |
e4a1d846 | 2793 | intel_enable_dp(encoder); |
b0b33846 VS |
2794 | |
2795 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 2796 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
2797 | } |
2798 | ||
9197c88b VS |
2799 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
2800 | { | |
625695f8 VS |
2801 | intel_dp_prepare(encoder); |
2802 | ||
419b1b7a | 2803 | chv_phy_pre_pll_enable(encoder); |
9197c88b VS |
2804 | } |
2805 | ||
d6db995f VS |
2806 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder) |
2807 | { | |
204970b5 | 2808 | chv_phy_post_pll_disable(encoder); |
d6db995f VS |
2809 | } |
2810 | ||
a4fc5ed6 KP |
2811 | /* |
2812 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
2813 | * link status information | |
2814 | */ | |
94223d04 | 2815 | bool |
93f62dad | 2816 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 2817 | { |
9f085ebb L |
2818 | return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, |
2819 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
2820 | } |
2821 | ||
1100244e | 2822 | /* These are source-specific values. */ |
94223d04 | 2823 | uint8_t |
1a2eb460 | 2824 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 2825 | { |
30add22d | 2826 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
7ad14a29 | 2827 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc7d38a4 | 2828 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 2829 | |
9314726b VK |
2830 | if (IS_BROXTON(dev)) |
2831 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; | |
2832 | else if (INTEL_INFO(dev)->gen >= 9) { | |
06411f08 | 2833 | if (dev_priv->vbt.edp.low_vswing && port == PORT_A) |
7ad14a29 | 2834 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
5a9d1f1a | 2835 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
666a4537 | 2836 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
bd60018a | 2837 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
bc7d38a4 | 2838 | else if (IS_GEN7(dev) && port == PORT_A) |
bd60018a | 2839 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
bc7d38a4 | 2840 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
bd60018a | 2841 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
1a2eb460 | 2842 | else |
bd60018a | 2843 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
1a2eb460 KP |
2844 | } |
2845 | ||
94223d04 | 2846 | uint8_t |
1a2eb460 KP |
2847 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
2848 | { | |
30add22d | 2849 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 2850 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 2851 | |
5a9d1f1a DL |
2852 | if (INTEL_INFO(dev)->gen >= 9) { |
2853 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2854 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: | |
2855 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
2856 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2857 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2858 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2859 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
7ad14a29 SJ |
2860 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
2861 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
5a9d1f1a DL |
2862 | default: |
2863 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
2864 | } | |
2865 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
d6c0d722 | 2866 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
2867 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2868 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
2869 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2870 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2871 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2872 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
2873 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
d6c0d722 | 2874 | default: |
bd60018a | 2875 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
d6c0d722 | 2876 | } |
666a4537 | 2877 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e2fa6fba | 2878 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
2879 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2880 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
2881 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2882 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2883 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2884 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
2885 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
e2fa6fba | 2886 | default: |
bd60018a | 2887 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
e2fa6fba | 2888 | } |
bc7d38a4 | 2889 | } else if (IS_GEN7(dev) && port == PORT_A) { |
1a2eb460 | 2890 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
2891 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2892 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2893 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2894 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2895 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
1a2eb460 | 2896 | default: |
bd60018a | 2897 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 KP |
2898 | } |
2899 | } else { | |
2900 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
2901 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2902 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2903 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2904 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2905 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2906 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
2907 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
1a2eb460 | 2908 | default: |
bd60018a | 2909 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 | 2910 | } |
a4fc5ed6 KP |
2911 | } |
2912 | } | |
2913 | ||
5829975c | 2914 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
e2fa6fba | 2915 | { |
53d98725 | 2916 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
e2fa6fba P |
2917 | unsigned long demph_reg_value, preemph_reg_value, |
2918 | uniqtranscale_reg_value; | |
2919 | uint8_t train_set = intel_dp->train_set[0]; | |
e2fa6fba P |
2920 | |
2921 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 2922 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e2fa6fba P |
2923 | preemph_reg_value = 0x0004000; |
2924 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 2925 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
2926 | demph_reg_value = 0x2B405555; |
2927 | uniqtranscale_reg_value = 0x552AB83A; | |
2928 | break; | |
bd60018a | 2929 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
2930 | demph_reg_value = 0x2B404040; |
2931 | uniqtranscale_reg_value = 0x5548B83A; | |
2932 | break; | |
bd60018a | 2933 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
2934 | demph_reg_value = 0x2B245555; |
2935 | uniqtranscale_reg_value = 0x5560B83A; | |
2936 | break; | |
bd60018a | 2937 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e2fa6fba P |
2938 | demph_reg_value = 0x2B405555; |
2939 | uniqtranscale_reg_value = 0x5598DA3A; | |
2940 | break; | |
2941 | default: | |
2942 | return 0; | |
2943 | } | |
2944 | break; | |
bd60018a | 2945 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e2fa6fba P |
2946 | preemph_reg_value = 0x0002000; |
2947 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 2948 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
2949 | demph_reg_value = 0x2B404040; |
2950 | uniqtranscale_reg_value = 0x5552B83A; | |
2951 | break; | |
bd60018a | 2952 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
2953 | demph_reg_value = 0x2B404848; |
2954 | uniqtranscale_reg_value = 0x5580B83A; | |
2955 | break; | |
bd60018a | 2956 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
2957 | demph_reg_value = 0x2B404040; |
2958 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2959 | break; | |
2960 | default: | |
2961 | return 0; | |
2962 | } | |
2963 | break; | |
bd60018a | 2964 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e2fa6fba P |
2965 | preemph_reg_value = 0x0000000; |
2966 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 2967 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
2968 | demph_reg_value = 0x2B305555; |
2969 | uniqtranscale_reg_value = 0x5570B83A; | |
2970 | break; | |
bd60018a | 2971 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
2972 | demph_reg_value = 0x2B2B4040; |
2973 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2974 | break; | |
2975 | default: | |
2976 | return 0; | |
2977 | } | |
2978 | break; | |
bd60018a | 2979 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e2fa6fba P |
2980 | preemph_reg_value = 0x0006000; |
2981 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 2982 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
2983 | demph_reg_value = 0x1B405555; |
2984 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2985 | break; | |
2986 | default: | |
2987 | return 0; | |
2988 | } | |
2989 | break; | |
2990 | default: | |
2991 | return 0; | |
2992 | } | |
2993 | ||
53d98725 ACO |
2994 | vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, |
2995 | uniqtranscale_reg_value, 0); | |
e2fa6fba P |
2996 | |
2997 | return 0; | |
2998 | } | |
2999 | ||
5829975c | 3000 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
e4a1d846 | 3001 | { |
b7fa22d8 ACO |
3002 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3003 | u32 deemph_reg_value, margin_reg_value; | |
3004 | bool uniq_trans_scale = false; | |
e4a1d846 | 3005 | uint8_t train_set = intel_dp->train_set[0]; |
e4a1d846 CML |
3006 | |
3007 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3008 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e4a1d846 | 3009 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3010 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3011 | deemph_reg_value = 128; |
3012 | margin_reg_value = 52; | |
3013 | break; | |
bd60018a | 3014 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3015 | deemph_reg_value = 128; |
3016 | margin_reg_value = 77; | |
3017 | break; | |
bd60018a | 3018 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3019 | deemph_reg_value = 128; |
3020 | margin_reg_value = 102; | |
3021 | break; | |
bd60018a | 3022 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e4a1d846 CML |
3023 | deemph_reg_value = 128; |
3024 | margin_reg_value = 154; | |
b7fa22d8 | 3025 | uniq_trans_scale = true; |
e4a1d846 CML |
3026 | break; |
3027 | default: | |
3028 | return 0; | |
3029 | } | |
3030 | break; | |
bd60018a | 3031 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e4a1d846 | 3032 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3033 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3034 | deemph_reg_value = 85; |
3035 | margin_reg_value = 78; | |
3036 | break; | |
bd60018a | 3037 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3038 | deemph_reg_value = 85; |
3039 | margin_reg_value = 116; | |
3040 | break; | |
bd60018a | 3041 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3042 | deemph_reg_value = 85; |
3043 | margin_reg_value = 154; | |
3044 | break; | |
3045 | default: | |
3046 | return 0; | |
3047 | } | |
3048 | break; | |
bd60018a | 3049 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e4a1d846 | 3050 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3051 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3052 | deemph_reg_value = 64; |
3053 | margin_reg_value = 104; | |
3054 | break; | |
bd60018a | 3055 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3056 | deemph_reg_value = 64; |
3057 | margin_reg_value = 154; | |
3058 | break; | |
3059 | default: | |
3060 | return 0; | |
3061 | } | |
3062 | break; | |
bd60018a | 3063 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e4a1d846 | 3064 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3065 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3066 | deemph_reg_value = 43; |
3067 | margin_reg_value = 154; | |
3068 | break; | |
3069 | default: | |
3070 | return 0; | |
3071 | } | |
3072 | break; | |
3073 | default: | |
3074 | return 0; | |
3075 | } | |
3076 | ||
b7fa22d8 ACO |
3077 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
3078 | margin_reg_value, uniq_trans_scale); | |
e4a1d846 CML |
3079 | |
3080 | return 0; | |
3081 | } | |
3082 | ||
a4fc5ed6 | 3083 | static uint32_t |
5829975c | 3084 | gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 3085 | { |
3cf2efb1 | 3086 | uint32_t signal_levels = 0; |
a4fc5ed6 | 3087 | |
3cf2efb1 | 3088 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3089 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
a4fc5ed6 KP |
3090 | default: |
3091 | signal_levels |= DP_VOLTAGE_0_4; | |
3092 | break; | |
bd60018a | 3093 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
a4fc5ed6 KP |
3094 | signal_levels |= DP_VOLTAGE_0_6; |
3095 | break; | |
bd60018a | 3096 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
a4fc5ed6 KP |
3097 | signal_levels |= DP_VOLTAGE_0_8; |
3098 | break; | |
bd60018a | 3099 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
a4fc5ed6 KP |
3100 | signal_levels |= DP_VOLTAGE_1_2; |
3101 | break; | |
3102 | } | |
3cf2efb1 | 3103 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
bd60018a | 3104 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
a4fc5ed6 KP |
3105 | default: |
3106 | signal_levels |= DP_PRE_EMPHASIS_0; | |
3107 | break; | |
bd60018a | 3108 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
a4fc5ed6 KP |
3109 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3110 | break; | |
bd60018a | 3111 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
a4fc5ed6 KP |
3112 | signal_levels |= DP_PRE_EMPHASIS_6; |
3113 | break; | |
bd60018a | 3114 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
a4fc5ed6 KP |
3115 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3116 | break; | |
3117 | } | |
3118 | return signal_levels; | |
3119 | } | |
3120 | ||
e3421a18 ZW |
3121 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3122 | static uint32_t | |
5829975c | 3123 | gen6_edp_signal_levels(uint8_t train_set) |
e3421a18 | 3124 | { |
3c5a62b5 YL |
3125 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3126 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3127 | switch (signal_levels) { | |
bd60018a SJ |
3128 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3129 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3130 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
bd60018a | 3131 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3c5a62b5 | 3132 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
bd60018a SJ |
3133 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3134 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
3c5a62b5 | 3135 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
bd60018a SJ |
3136 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3137 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
3c5a62b5 | 3138 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
bd60018a SJ |
3139 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3140 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3141 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
e3421a18 | 3142 | default: |
3c5a62b5 YL |
3143 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3144 | "0x%x\n", signal_levels); | |
3145 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
3146 | } |
3147 | } | |
3148 | ||
1a2eb460 KP |
3149 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3150 | static uint32_t | |
5829975c | 3151 | gen7_edp_signal_levels(uint8_t train_set) |
1a2eb460 KP |
3152 | { |
3153 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
3154 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3155 | switch (signal_levels) { | |
bd60018a | 3156 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3157 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
bd60018a | 3158 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 | 3159 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
bd60018a | 3160 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
1a2eb460 KP |
3161 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3162 | ||
bd60018a | 3163 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3164 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
bd60018a | 3165 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3166 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3167 | ||
bd60018a | 3168 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3169 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
bd60018a | 3170 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3171 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3172 | ||
3173 | default: | |
3174 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
3175 | "0x%x\n", signal_levels); | |
3176 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
3177 | } | |
3178 | } | |
3179 | ||
94223d04 | 3180 | void |
f4eb692e | 3181 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
f0a3424e PZ |
3182 | { |
3183 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 3184 | enum port port = intel_dig_port->port; |
f0a3424e | 3185 | struct drm_device *dev = intel_dig_port->base.base.dev; |
b905a915 | 3186 | struct drm_i915_private *dev_priv = to_i915(dev); |
f8896f5d | 3187 | uint32_t signal_levels, mask = 0; |
f0a3424e PZ |
3188 | uint8_t train_set = intel_dp->train_set[0]; |
3189 | ||
f8896f5d DW |
3190 | if (HAS_DDI(dev)) { |
3191 | signal_levels = ddi_signal_levels(intel_dp); | |
3192 | ||
3193 | if (IS_BROXTON(dev)) | |
3194 | signal_levels = 0; | |
3195 | else | |
3196 | mask = DDI_BUF_EMP_MASK; | |
e4a1d846 | 3197 | } else if (IS_CHERRYVIEW(dev)) { |
5829975c | 3198 | signal_levels = chv_signal_levels(intel_dp); |
e2fa6fba | 3199 | } else if (IS_VALLEYVIEW(dev)) { |
5829975c | 3200 | signal_levels = vlv_signal_levels(intel_dp); |
bc7d38a4 | 3201 | } else if (IS_GEN7(dev) && port == PORT_A) { |
5829975c | 3202 | signal_levels = gen7_edp_signal_levels(train_set); |
f0a3424e | 3203 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
bc7d38a4 | 3204 | } else if (IS_GEN6(dev) && port == PORT_A) { |
5829975c | 3205 | signal_levels = gen6_edp_signal_levels(train_set); |
f0a3424e PZ |
3206 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3207 | } else { | |
5829975c | 3208 | signal_levels = gen4_signal_levels(train_set); |
f0a3424e PZ |
3209 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3210 | } | |
3211 | ||
96fb9f9b VK |
3212 | if (mask) |
3213 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
3214 | ||
3215 | DRM_DEBUG_KMS("Using vswing level %d\n", | |
3216 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); | |
3217 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", | |
3218 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
3219 | DP_TRAIN_PRE_EMPHASIS_SHIFT); | |
f0a3424e | 3220 | |
f4eb692e | 3221 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
b905a915 ACO |
3222 | |
3223 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
3224 | POSTING_READ(intel_dp->output_reg); | |
f0a3424e PZ |
3225 | } |
3226 | ||
94223d04 | 3227 | void |
e9c176d5 ACO |
3228 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
3229 | uint8_t dp_train_pat) | |
a4fc5ed6 | 3230 | { |
174edf1f | 3231 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
90a6b7b0 VS |
3232 | struct drm_i915_private *dev_priv = |
3233 | to_i915(intel_dig_port->base.base.dev); | |
a4fc5ed6 | 3234 | |
f4eb692e | 3235 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
47ea7542 | 3236 | |
f4eb692e | 3237 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
ea5b213a | 3238 | POSTING_READ(intel_dp->output_reg); |
e9c176d5 ACO |
3239 | } |
3240 | ||
94223d04 | 3241 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3ab9c637 ID |
3242 | { |
3243 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3244 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
3245 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3246 | enum port port = intel_dig_port->port; | |
3247 | uint32_t val; | |
3248 | ||
3249 | if (!HAS_DDI(dev)) | |
3250 | return; | |
3251 | ||
3252 | val = I915_READ(DP_TP_CTL(port)); | |
3253 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
3254 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
3255 | I915_WRITE(DP_TP_CTL(port), val); | |
3256 | ||
3257 | /* | |
3258 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
3259 | * we need to set idle transmission mode is to work around a HW issue | |
3260 | * where we enable the pipe while not in idle link-training mode. | |
3261 | * In this case there is requirement to wait for a minimum number of | |
3262 | * idle patterns to be sent. | |
3263 | */ | |
3264 | if (port == PORT_A) | |
3265 | return; | |
3266 | ||
3267 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), | |
3268 | 1)) | |
3269 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); | |
3270 | } | |
3271 | ||
a4fc5ed6 | 3272 | static void |
ea5b213a | 3273 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 3274 | { |
da63a9f2 | 3275 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1612c8bd | 3276 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
bc7d38a4 | 3277 | enum port port = intel_dig_port->port; |
da63a9f2 | 3278 | struct drm_device *dev = intel_dig_port->base.base.dev; |
a4fc5ed6 | 3279 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 3280 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 3281 | |
bc76e320 | 3282 | if (WARN_ON(HAS_DDI(dev))) |
c19b0669 PZ |
3283 | return; |
3284 | ||
0c33d8d7 | 3285 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
3286 | return; |
3287 | ||
28c97730 | 3288 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 3289 | |
39e5fa88 VS |
3290 | if ((IS_GEN7(dev) && port == PORT_A) || |
3291 | (HAS_PCH_CPT(dev) && port != PORT_A)) { | |
e3421a18 | 3292 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1612c8bd | 3293 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
e3421a18 | 3294 | } else { |
aad3d14d VS |
3295 | if (IS_CHERRYVIEW(dev)) |
3296 | DP &= ~DP_LINK_TRAIN_MASK_CHV; | |
3297 | else | |
3298 | DP &= ~DP_LINK_TRAIN_MASK; | |
1612c8bd | 3299 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
e3421a18 | 3300 | } |
1612c8bd | 3301 | I915_WRITE(intel_dp->output_reg, DP); |
fe255d00 | 3302 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 3303 | |
1612c8bd VS |
3304 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3305 | I915_WRITE(intel_dp->output_reg, DP); | |
3306 | POSTING_READ(intel_dp->output_reg); | |
3307 | ||
3308 | /* | |
3309 | * HW workaround for IBX, we need to move the port | |
3310 | * to transcoder A after disabling it to allow the | |
3311 | * matching HDMI port to be enabled on transcoder A. | |
3312 | */ | |
3313 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { | |
0c241d5b VS |
3314 | /* |
3315 | * We get CPU/PCH FIFO underruns on the other pipe when | |
3316 | * doing the workaround. Sweep them under the rug. | |
3317 | */ | |
3318 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3319 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3320 | ||
1612c8bd VS |
3321 | /* always enable with pattern 1 (as per spec) */ |
3322 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); | |
3323 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; | |
3324 | I915_WRITE(intel_dp->output_reg, DP); | |
3325 | POSTING_READ(intel_dp->output_reg); | |
3326 | ||
3327 | DP &= ~DP_PORT_EN; | |
5bddd17f | 3328 | I915_WRITE(intel_dp->output_reg, DP); |
0ca09685 | 3329 | POSTING_READ(intel_dp->output_reg); |
0c241d5b VS |
3330 | |
3331 | intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A); | |
3332 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
3333 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
5bddd17f EA |
3334 | } |
3335 | ||
f01eca2e | 3336 | msleep(intel_dp->panel_power_down_delay); |
6fec7662 VS |
3337 | |
3338 | intel_dp->DP = DP; | |
a4fc5ed6 KP |
3339 | } |
3340 | ||
26d61aad KP |
3341 | static bool |
3342 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 3343 | { |
a031d709 RV |
3344 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3345 | struct drm_device *dev = dig_port->base.base.dev; | |
3346 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3347 | ||
9f085ebb L |
3348 | if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3349 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 3350 | return false; /* aux transfer failed */ |
92fd8fd1 | 3351 | |
a8e98153 | 3352 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
577c7a50 | 3353 | |
edb39244 AJ |
3354 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
3355 | return false; /* DPCD not present */ | |
3356 | ||
9f085ebb L |
3357 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT, |
3358 | &intel_dp->sink_count, 1) < 0) | |
30d9aa42 SS |
3359 | return false; |
3360 | ||
3361 | /* | |
3362 | * Sink count can change between short pulse hpd hence | |
3363 | * a member variable in intel_dp will track any changes | |
3364 | * between short pulse interrupts. | |
3365 | */ | |
3366 | intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count); | |
3367 | ||
3368 | /* | |
3369 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that | |
3370 | * a dongle is present but no display. Unless we require to know | |
3371 | * if a dongle is present or not, we don't need to update | |
3372 | * downstream port information. So, an early return here saves | |
3373 | * time from performing other operations which are not required. | |
3374 | */ | |
1034ce70 | 3375 | if (!is_edp(intel_dp) && !intel_dp->sink_count) |
30d9aa42 SS |
3376 | return false; |
3377 | ||
2293bb5c SK |
3378 | /* Check if the panel supports PSR */ |
3379 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); | |
50003939 | 3380 | if (is_edp(intel_dp)) { |
9f085ebb L |
3381 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, |
3382 | intel_dp->psr_dpcd, | |
3383 | sizeof(intel_dp->psr_dpcd)); | |
a031d709 RV |
3384 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
3385 | dev_priv->psr.sink_support = true; | |
50003939 | 3386 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
a031d709 | 3387 | } |
474d1ec4 SJ |
3388 | |
3389 | if (INTEL_INFO(dev)->gen >= 9 && | |
3390 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { | |
3391 | uint8_t frame_sync_cap; | |
3392 | ||
3393 | dev_priv->psr.sink_support = true; | |
9f085ebb L |
3394 | drm_dp_dpcd_read(&intel_dp->aux, |
3395 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, | |
3396 | &frame_sync_cap, 1); | |
474d1ec4 SJ |
3397 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; |
3398 | /* PSR2 needs frame sync as well */ | |
3399 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; | |
3400 | DRM_DEBUG_KMS("PSR2 %s on sink", | |
3401 | dev_priv->psr.psr2_support ? "supported" : "not supported"); | |
3402 | } | |
86ee27b5 YA |
3403 | |
3404 | /* Read the eDP Display control capabilities registers */ | |
3405 | memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd)); | |
3406 | if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && | |
9a652cc0 | 3407 | (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, |
86ee27b5 YA |
3408 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == |
3409 | sizeof(intel_dp->edp_dpcd))) | |
3410 | DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), | |
3411 | intel_dp->edp_dpcd); | |
50003939 JN |
3412 | } |
3413 | ||
bc5133d5 | 3414 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
e588fa18 | 3415 | yesno(intel_dp_source_supports_hbr2(intel_dp)), |
742f491d | 3416 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); |
06ea66b6 | 3417 | |
fc0f8e25 | 3418 | /* Intermediate frequency support */ |
86ee27b5 | 3419 | if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */ |
94ca719e | 3420 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
ea2d8a42 VS |
3421 | int i; |
3422 | ||
9f085ebb L |
3423 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, |
3424 | sink_rates, sizeof(sink_rates)); | |
ea2d8a42 | 3425 | |
94ca719e VS |
3426 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
3427 | int val = le16_to_cpu(sink_rates[i]); | |
ea2d8a42 VS |
3428 | |
3429 | if (val == 0) | |
3430 | break; | |
3431 | ||
af77b974 SJ |
3432 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
3433 | intel_dp->sink_rates[i] = (val * 200) / 10; | |
ea2d8a42 | 3434 | } |
94ca719e | 3435 | intel_dp->num_sink_rates = i; |
fc0f8e25 | 3436 | } |
0336400e VS |
3437 | |
3438 | intel_dp_print_rates(intel_dp); | |
3439 | ||
edb39244 AJ |
3440 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
3441 | DP_DWN_STRM_PORT_PRESENT)) | |
3442 | return true; /* native DP sink */ | |
3443 | ||
3444 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
3445 | return true; /* no per-port downstream info */ | |
3446 | ||
9f085ebb L |
3447 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3448 | intel_dp->downstream_ports, | |
3449 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
3450 | return false; /* downstream port status fetch failed */ |
3451 | ||
3452 | return true; | |
92fd8fd1 KP |
3453 | } |
3454 | ||
0d198328 AJ |
3455 | static void |
3456 | intel_dp_probe_oui(struct intel_dp *intel_dp) | |
3457 | { | |
3458 | u8 buf[3]; | |
3459 | ||
3460 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
3461 | return; | |
3462 | ||
9f085ebb | 3463 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
0d198328 AJ |
3464 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
3465 | buf[0], buf[1], buf[2]); | |
3466 | ||
9f085ebb | 3467 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
0d198328 AJ |
3468 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
3469 | buf[0], buf[1], buf[2]); | |
3470 | } | |
3471 | ||
0e32b39c DA |
3472 | static bool |
3473 | intel_dp_probe_mst(struct intel_dp *intel_dp) | |
3474 | { | |
3475 | u8 buf[1]; | |
3476 | ||
7cc96139 NS |
3477 | if (!i915.enable_dp_mst) |
3478 | return false; | |
3479 | ||
0e32b39c DA |
3480 | if (!intel_dp->can_mst) |
3481 | return false; | |
3482 | ||
3483 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) | |
3484 | return false; | |
3485 | ||
9f085ebb | 3486 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
0e32b39c DA |
3487 | if (buf[0] & DP_MST_CAP) { |
3488 | DRM_DEBUG_KMS("Sink is MST capable\n"); | |
3489 | intel_dp->is_mst = true; | |
3490 | } else { | |
3491 | DRM_DEBUG_KMS("Sink is not MST capable\n"); | |
3492 | intel_dp->is_mst = false; | |
3493 | } | |
3494 | } | |
0e32b39c DA |
3495 | |
3496 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
3497 | return intel_dp->is_mst; | |
3498 | } | |
3499 | ||
e5a1cab5 | 3500 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
d2e216d0 | 3501 | { |
082dcc7c | 3502 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
d72f9d91 | 3503 | struct drm_device *dev = dig_port->base.base.dev; |
082dcc7c | 3504 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
ad9dc91b | 3505 | u8 buf; |
e5a1cab5 | 3506 | int ret = 0; |
c6297843 RV |
3507 | int count = 0; |
3508 | int attempts = 10; | |
d2e216d0 | 3509 | |
082dcc7c RV |
3510 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
3511 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); | |
e5a1cab5 RV |
3512 | ret = -EIO; |
3513 | goto out; | |
4373f0f2 PZ |
3514 | } |
3515 | ||
082dcc7c | 3516 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
e5a1cab5 | 3517 | buf & ~DP_TEST_SINK_START) < 0) { |
082dcc7c | 3518 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
e5a1cab5 RV |
3519 | ret = -EIO; |
3520 | goto out; | |
3521 | } | |
d2e216d0 | 3522 | |
c6297843 RV |
3523 | do { |
3524 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3525 | ||
3526 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
3527 | DP_TEST_SINK_MISC, &buf) < 0) { | |
3528 | ret = -EIO; | |
3529 | goto out; | |
3530 | } | |
3531 | count = buf & DP_TEST_COUNT_MASK; | |
3532 | } while (--attempts && count); | |
3533 | ||
3534 | if (attempts == 0) { | |
dc5a9037 | 3535 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
c6297843 RV |
3536 | ret = -ETIMEDOUT; |
3537 | } | |
3538 | ||
e5a1cab5 | 3539 | out: |
082dcc7c | 3540 | hsw_enable_ips(intel_crtc); |
e5a1cab5 | 3541 | return ret; |
082dcc7c RV |
3542 | } |
3543 | ||
3544 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) | |
3545 | { | |
3546 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
d72f9d91 | 3547 | struct drm_device *dev = dig_port->base.base.dev; |
082dcc7c RV |
3548 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3549 | u8 buf; | |
e5a1cab5 RV |
3550 | int ret; |
3551 | ||
082dcc7c RV |
3552 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
3553 | return -EIO; | |
3554 | ||
3555 | if (!(buf & DP_TEST_CRC_SUPPORTED)) | |
3556 | return -ENOTTY; | |
3557 | ||
3558 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) | |
3559 | return -EIO; | |
3560 | ||
6d8175da RV |
3561 | if (buf & DP_TEST_SINK_START) { |
3562 | ret = intel_dp_sink_crc_stop(intel_dp); | |
3563 | if (ret) | |
3564 | return ret; | |
3565 | } | |
3566 | ||
082dcc7c | 3567 | hsw_disable_ips(intel_crtc); |
1dda5f93 | 3568 | |
9d1a1031 | 3569 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
082dcc7c RV |
3570 | buf | DP_TEST_SINK_START) < 0) { |
3571 | hsw_enable_ips(intel_crtc); | |
3572 | return -EIO; | |
4373f0f2 PZ |
3573 | } |
3574 | ||
d72f9d91 | 3575 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
082dcc7c RV |
3576 | return 0; |
3577 | } | |
3578 | ||
3579 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) | |
3580 | { | |
3581 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
3582 | struct drm_device *dev = dig_port->base.base.dev; | |
3583 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); | |
3584 | u8 buf; | |
621d4c76 | 3585 | int count, ret; |
082dcc7c | 3586 | int attempts = 6; |
082dcc7c RV |
3587 | |
3588 | ret = intel_dp_sink_crc_start(intel_dp); | |
3589 | if (ret) | |
3590 | return ret; | |
3591 | ||
ad9dc91b | 3592 | do { |
621d4c76 RV |
3593 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3594 | ||
1dda5f93 | 3595 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4373f0f2 PZ |
3596 | DP_TEST_SINK_MISC, &buf) < 0) { |
3597 | ret = -EIO; | |
afe0d67e | 3598 | goto stop; |
4373f0f2 | 3599 | } |
621d4c76 | 3600 | count = buf & DP_TEST_COUNT_MASK; |
aabc95dc | 3601 | |
7e38eeff | 3602 | } while (--attempts && count == 0); |
ad9dc91b RV |
3603 | |
3604 | if (attempts == 0) { | |
7e38eeff RV |
3605 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
3606 | ret = -ETIMEDOUT; | |
3607 | goto stop; | |
3608 | } | |
3609 | ||
3610 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { | |
3611 | ret = -EIO; | |
3612 | goto stop; | |
ad9dc91b | 3613 | } |
d2e216d0 | 3614 | |
afe0d67e | 3615 | stop: |
082dcc7c | 3616 | intel_dp_sink_crc_stop(intel_dp); |
4373f0f2 | 3617 | return ret; |
d2e216d0 RV |
3618 | } |
3619 | ||
a60f0e38 JB |
3620 | static bool |
3621 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3622 | { | |
9f085ebb | 3623 | return drm_dp_dpcd_read(&intel_dp->aux, |
9d1a1031 JN |
3624 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
3625 | sink_irq_vector, 1) == 1; | |
a60f0e38 JB |
3626 | } |
3627 | ||
0e32b39c DA |
3628 | static bool |
3629 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3630 | { | |
3631 | int ret; | |
3632 | ||
9f085ebb | 3633 | ret = drm_dp_dpcd_read(&intel_dp->aux, |
0e32b39c DA |
3634 | DP_SINK_COUNT_ESI, |
3635 | sink_irq_vector, 14); | |
3636 | if (ret != 14) | |
3637 | return false; | |
3638 | ||
3639 | return true; | |
3640 | } | |
3641 | ||
c5d5ab7a TP |
3642 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
3643 | { | |
3644 | uint8_t test_result = DP_TEST_ACK; | |
3645 | return test_result; | |
3646 | } | |
3647 | ||
3648 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) | |
3649 | { | |
3650 | uint8_t test_result = DP_TEST_NAK; | |
3651 | return test_result; | |
3652 | } | |
3653 | ||
3654 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) | |
a60f0e38 | 3655 | { |
c5d5ab7a | 3656 | uint8_t test_result = DP_TEST_NAK; |
559be30c TP |
3657 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
3658 | struct drm_connector *connector = &intel_connector->base; | |
3659 | ||
3660 | if (intel_connector->detect_edid == NULL || | |
ac6f2e29 | 3661 | connector->edid_corrupt || |
559be30c TP |
3662 | intel_dp->aux.i2c_defer_count > 6) { |
3663 | /* Check EDID read for NACKs, DEFERs and corruption | |
3664 | * (DP CTS 1.2 Core r1.1) | |
3665 | * 4.2.2.4 : Failed EDID read, I2C_NAK | |
3666 | * 4.2.2.5 : Failed EDID read, I2C_DEFER | |
3667 | * 4.2.2.6 : EDID corruption detected | |
3668 | * Use failsafe mode for all cases | |
3669 | */ | |
3670 | if (intel_dp->aux.i2c_nack_count > 0 || | |
3671 | intel_dp->aux.i2c_defer_count > 0) | |
3672 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", | |
3673 | intel_dp->aux.i2c_nack_count, | |
3674 | intel_dp->aux.i2c_defer_count); | |
3675 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; | |
3676 | } else { | |
f79b468e TS |
3677 | struct edid *block = intel_connector->detect_edid; |
3678 | ||
3679 | /* We have to write the checksum | |
3680 | * of the last block read | |
3681 | */ | |
3682 | block += intel_connector->detect_edid->extensions; | |
3683 | ||
559be30c TP |
3684 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
3685 | DP_TEST_EDID_CHECKSUM, | |
f79b468e | 3686 | &block->checksum, |
5a1cc655 | 3687 | 1)) |
559be30c TP |
3688 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
3689 | ||
3690 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; | |
3691 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; | |
3692 | } | |
3693 | ||
3694 | /* Set test active flag here so userspace doesn't interrupt things */ | |
3695 | intel_dp->compliance_test_active = 1; | |
3696 | ||
c5d5ab7a TP |
3697 | return test_result; |
3698 | } | |
3699 | ||
3700 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) | |
a60f0e38 | 3701 | { |
c5d5ab7a TP |
3702 | uint8_t test_result = DP_TEST_NAK; |
3703 | return test_result; | |
3704 | } | |
3705 | ||
3706 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
3707 | { | |
3708 | uint8_t response = DP_TEST_NAK; | |
3709 | uint8_t rxdata = 0; | |
3710 | int status = 0; | |
3711 | ||
c5d5ab7a TP |
3712 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
3713 | if (status <= 0) { | |
3714 | DRM_DEBUG_KMS("Could not read test request from sink\n"); | |
3715 | goto update_status; | |
3716 | } | |
3717 | ||
3718 | switch (rxdata) { | |
3719 | case DP_TEST_LINK_TRAINING: | |
3720 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); | |
3721 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; | |
3722 | response = intel_dp_autotest_link_training(intel_dp); | |
3723 | break; | |
3724 | case DP_TEST_LINK_VIDEO_PATTERN: | |
3725 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); | |
3726 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; | |
3727 | response = intel_dp_autotest_video_pattern(intel_dp); | |
3728 | break; | |
3729 | case DP_TEST_LINK_EDID_READ: | |
3730 | DRM_DEBUG_KMS("EDID test requested\n"); | |
3731 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; | |
3732 | response = intel_dp_autotest_edid(intel_dp); | |
3733 | break; | |
3734 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
3735 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); | |
3736 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; | |
3737 | response = intel_dp_autotest_phy_pattern(intel_dp); | |
3738 | break; | |
3739 | default: | |
3740 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); | |
3741 | break; | |
3742 | } | |
3743 | ||
3744 | update_status: | |
3745 | status = drm_dp_dpcd_write(&intel_dp->aux, | |
3746 | DP_TEST_RESPONSE, | |
3747 | &response, 1); | |
3748 | if (status <= 0) | |
3749 | DRM_DEBUG_KMS("Could not write test response to sink\n"); | |
a60f0e38 JB |
3750 | } |
3751 | ||
0e32b39c DA |
3752 | static int |
3753 | intel_dp_check_mst_status(struct intel_dp *intel_dp) | |
3754 | { | |
3755 | bool bret; | |
3756 | ||
3757 | if (intel_dp->is_mst) { | |
3758 | u8 esi[16] = { 0 }; | |
3759 | int ret = 0; | |
3760 | int retry; | |
3761 | bool handled; | |
3762 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
3763 | go_again: | |
3764 | if (bret == true) { | |
3765 | ||
3766 | /* check link status - esi[10] = 0x200c */ | |
90a6b7b0 | 3767 | if (intel_dp->active_mst_links && |
901c2daf | 3768 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
0e32b39c DA |
3769 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
3770 | intel_dp_start_link_train(intel_dp); | |
0e32b39c DA |
3771 | intel_dp_stop_link_train(intel_dp); |
3772 | } | |
3773 | ||
6f34cc39 | 3774 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
0e32b39c DA |
3775 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
3776 | ||
3777 | if (handled) { | |
3778 | for (retry = 0; retry < 3; retry++) { | |
3779 | int wret; | |
3780 | wret = drm_dp_dpcd_write(&intel_dp->aux, | |
3781 | DP_SINK_COUNT_ESI+1, | |
3782 | &esi[1], 3); | |
3783 | if (wret == 3) { | |
3784 | break; | |
3785 | } | |
3786 | } | |
3787 | ||
3788 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
3789 | if (bret == true) { | |
6f34cc39 | 3790 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
0e32b39c DA |
3791 | goto go_again; |
3792 | } | |
3793 | } else | |
3794 | ret = 0; | |
3795 | ||
3796 | return ret; | |
3797 | } else { | |
3798 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3799 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); | |
3800 | intel_dp->is_mst = false; | |
3801 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
3802 | /* send a hotplug event */ | |
3803 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); | |
3804 | } | |
3805 | } | |
3806 | return -EINVAL; | |
3807 | } | |
3808 | ||
5c9114d0 SS |
3809 | static void |
3810 | intel_dp_check_link_status(struct intel_dp *intel_dp) | |
3811 | { | |
3812 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; | |
3813 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
3814 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
3815 | ||
3816 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
3817 | ||
3818 | if (!intel_dp_get_link_status(intel_dp, link_status)) { | |
3819 | DRM_ERROR("Failed to get link status\n"); | |
3820 | return; | |
3821 | } | |
3822 | ||
3823 | if (!intel_encoder->base.crtc) | |
3824 | return; | |
3825 | ||
3826 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) | |
3827 | return; | |
3828 | ||
3829 | /* if link training is requested we should perform it always */ | |
3830 | if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || | |
3831 | (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { | |
3832 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", | |
3833 | intel_encoder->base.name); | |
3834 | intel_dp_start_link_train(intel_dp); | |
3835 | intel_dp_stop_link_train(intel_dp); | |
3836 | } | |
3837 | } | |
3838 | ||
a4fc5ed6 KP |
3839 | /* |
3840 | * According to DP spec | |
3841 | * 5.1.2: | |
3842 | * 1. Read DPCD | |
3843 | * 2. Configure link according to Receiver Capabilities | |
3844 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
3845 | * 4. Check link status on receipt of hot-plug interrupt | |
39ff747b SS |
3846 | * |
3847 | * intel_dp_short_pulse - handles short pulse interrupts | |
3848 | * when full detection is not required. | |
3849 | * Returns %true if short pulse is handled and full detection | |
3850 | * is NOT required and %false otherwise. | |
a4fc5ed6 | 3851 | */ |
39ff747b | 3852 | static bool |
5c9114d0 | 3853 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
a4fc5ed6 | 3854 | { |
5b215bcf | 3855 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
a60f0e38 | 3856 | u8 sink_irq_vector; |
39ff747b SS |
3857 | u8 old_sink_count = intel_dp->sink_count; |
3858 | bool ret; | |
5b215bcf | 3859 | |
4df6960e SS |
3860 | /* |
3861 | * Clearing compliance test variables to allow capturing | |
3862 | * of values for next automated test request. | |
3863 | */ | |
3864 | intel_dp->compliance_test_active = 0; | |
3865 | intel_dp->compliance_test_type = 0; | |
3866 | intel_dp->compliance_test_data = 0; | |
3867 | ||
39ff747b SS |
3868 | /* |
3869 | * Now read the DPCD to see if it's actually running | |
3870 | * If the current value of sink count doesn't match with | |
3871 | * the value that was stored earlier or dpcd read failed | |
3872 | * we need to do full detection | |
3873 | */ | |
3874 | ret = intel_dp_get_dpcd(intel_dp); | |
3875 | ||
3876 | if ((old_sink_count != intel_dp->sink_count) || !ret) { | |
3877 | /* No need to proceed if we are going to do full detect */ | |
3878 | return false; | |
59cd09e1 JB |
3879 | } |
3880 | ||
a60f0e38 JB |
3881 | /* Try to read the source of the interrupt */ |
3882 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
3883 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
3884 | /* Clear interrupt source */ | |
9d1a1031 JN |
3885 | drm_dp_dpcd_writeb(&intel_dp->aux, |
3886 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
3887 | sink_irq_vector); | |
a60f0e38 JB |
3888 | |
3889 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
09b1eb13 | 3890 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
a60f0e38 JB |
3891 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
3892 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
3893 | } | |
3894 | ||
5c9114d0 SS |
3895 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
3896 | intel_dp_check_link_status(intel_dp); | |
3897 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
39ff747b SS |
3898 | |
3899 | return true; | |
a4fc5ed6 | 3900 | } |
a4fc5ed6 | 3901 | |
caf9ab24 | 3902 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 3903 | static enum drm_connector_status |
26d61aad | 3904 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 3905 | { |
caf9ab24 | 3906 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
3907 | uint8_t type; |
3908 | ||
3909 | if (!intel_dp_get_dpcd(intel_dp)) | |
3910 | return connector_status_disconnected; | |
3911 | ||
1034ce70 SS |
3912 | if (is_edp(intel_dp)) |
3913 | return connector_status_connected; | |
3914 | ||
caf9ab24 AJ |
3915 | /* if there's no downstream port, we're done */ |
3916 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) | |
26d61aad | 3917 | return connector_status_connected; |
caf9ab24 AJ |
3918 | |
3919 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
3920 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
3921 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
9d1a1031 | 3922 | |
30d9aa42 SS |
3923 | return intel_dp->sink_count ? |
3924 | connector_status_connected : connector_status_disconnected; | |
caf9ab24 AJ |
3925 | } |
3926 | ||
3927 | /* If no HPD, poke DDC gently */ | |
0b99836f | 3928 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 3929 | return connector_status_connected; |
caf9ab24 AJ |
3930 | |
3931 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
3932 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
3933 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
3934 | if (type == DP_DS_PORT_TYPE_VGA || | |
3935 | type == DP_DS_PORT_TYPE_NON_EDID) | |
3936 | return connector_status_unknown; | |
3937 | } else { | |
3938 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
3939 | DP_DWN_STRM_PORT_TYPE_MASK; | |
3940 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
3941 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
3942 | return connector_status_unknown; | |
3943 | } | |
caf9ab24 AJ |
3944 | |
3945 | /* Anything else is out of spec, warn and ignore */ | |
3946 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 3947 | return connector_status_disconnected; |
71ba9000 AJ |
3948 | } |
3949 | ||
d410b56d CW |
3950 | static enum drm_connector_status |
3951 | edp_detect(struct intel_dp *intel_dp) | |
3952 | { | |
3953 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
3954 | enum drm_connector_status status; | |
3955 | ||
3956 | status = intel_panel_detect(dev); | |
3957 | if (status == connector_status_unknown) | |
3958 | status = connector_status_connected; | |
3959 | ||
3960 | return status; | |
3961 | } | |
3962 | ||
b93433cc JN |
3963 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
3964 | struct intel_digital_port *port) | |
5eb08b69 | 3965 | { |
b93433cc | 3966 | u32 bit; |
01cb9ea6 | 3967 | |
0df53b77 JN |
3968 | switch (port->port) { |
3969 | case PORT_A: | |
3970 | return true; | |
3971 | case PORT_B: | |
3972 | bit = SDE_PORTB_HOTPLUG; | |
3973 | break; | |
3974 | case PORT_C: | |
3975 | bit = SDE_PORTC_HOTPLUG; | |
3976 | break; | |
3977 | case PORT_D: | |
3978 | bit = SDE_PORTD_HOTPLUG; | |
3979 | break; | |
3980 | default: | |
3981 | MISSING_CASE(port->port); | |
3982 | return false; | |
3983 | } | |
3984 | ||
3985 | return I915_READ(SDEISR) & bit; | |
3986 | } | |
3987 | ||
3988 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, | |
3989 | struct intel_digital_port *port) | |
3990 | { | |
3991 | u32 bit; | |
3992 | ||
3993 | switch (port->port) { | |
3994 | case PORT_A: | |
3995 | return true; | |
3996 | case PORT_B: | |
3997 | bit = SDE_PORTB_HOTPLUG_CPT; | |
3998 | break; | |
3999 | case PORT_C: | |
4000 | bit = SDE_PORTC_HOTPLUG_CPT; | |
4001 | break; | |
4002 | case PORT_D: | |
4003 | bit = SDE_PORTD_HOTPLUG_CPT; | |
4004 | break; | |
a78695d3 JN |
4005 | case PORT_E: |
4006 | bit = SDE_PORTE_HOTPLUG_SPT; | |
4007 | break; | |
0df53b77 JN |
4008 | default: |
4009 | MISSING_CASE(port->port); | |
4010 | return false; | |
b93433cc | 4011 | } |
1b469639 | 4012 | |
b93433cc | 4013 | return I915_READ(SDEISR) & bit; |
5eb08b69 ZW |
4014 | } |
4015 | ||
7e66bcf2 | 4016 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
1d245987 | 4017 | struct intel_digital_port *port) |
a4fc5ed6 | 4018 | { |
9642c81c | 4019 | u32 bit; |
5eb08b69 | 4020 | |
9642c81c JN |
4021 | switch (port->port) { |
4022 | case PORT_B: | |
4023 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; | |
4024 | break; | |
4025 | case PORT_C: | |
4026 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; | |
4027 | break; | |
4028 | case PORT_D: | |
4029 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | |
4030 | break; | |
4031 | default: | |
4032 | MISSING_CASE(port->port); | |
4033 | return false; | |
4034 | } | |
4035 | ||
4036 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
4037 | } | |
4038 | ||
0780cd36 VS |
4039 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
4040 | struct intel_digital_port *port) | |
9642c81c JN |
4041 | { |
4042 | u32 bit; | |
4043 | ||
4044 | switch (port->port) { | |
4045 | case PORT_B: | |
0780cd36 | 4046 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4047 | break; |
4048 | case PORT_C: | |
0780cd36 | 4049 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4050 | break; |
4051 | case PORT_D: | |
0780cd36 | 4052 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4053 | break; |
4054 | default: | |
4055 | MISSING_CASE(port->port); | |
4056 | return false; | |
a4fc5ed6 KP |
4057 | } |
4058 | ||
1d245987 | 4059 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
2a592bec DA |
4060 | } |
4061 | ||
e464bfde | 4062 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
e2ec35a5 | 4063 | struct intel_digital_port *intel_dig_port) |
e464bfde | 4064 | { |
e2ec35a5 SJ |
4065 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4066 | enum port port; | |
e464bfde JN |
4067 | u32 bit; |
4068 | ||
e2ec35a5 SJ |
4069 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
4070 | switch (port) { | |
e464bfde JN |
4071 | case PORT_A: |
4072 | bit = BXT_DE_PORT_HP_DDIA; | |
4073 | break; | |
4074 | case PORT_B: | |
4075 | bit = BXT_DE_PORT_HP_DDIB; | |
4076 | break; | |
4077 | case PORT_C: | |
4078 | bit = BXT_DE_PORT_HP_DDIC; | |
4079 | break; | |
4080 | default: | |
e2ec35a5 | 4081 | MISSING_CASE(port); |
e464bfde JN |
4082 | return false; |
4083 | } | |
4084 | ||
4085 | return I915_READ(GEN8_DE_PORT_ISR) & bit; | |
4086 | } | |
4087 | ||
7e66bcf2 JN |
4088 | /* |
4089 | * intel_digital_port_connected - is the specified port connected? | |
4090 | * @dev_priv: i915 private structure | |
4091 | * @port: the port to test | |
4092 | * | |
4093 | * Return %true if @port is connected, %false otherwise. | |
4094 | */ | |
237ed86c | 4095 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
7e66bcf2 JN |
4096 | struct intel_digital_port *port) |
4097 | { | |
0df53b77 | 4098 | if (HAS_PCH_IBX(dev_priv)) |
7e66bcf2 | 4099 | return ibx_digital_port_connected(dev_priv, port); |
22824fac | 4100 | else if (HAS_PCH_SPLIT(dev_priv)) |
0df53b77 | 4101 | return cpt_digital_port_connected(dev_priv, port); |
e464bfde JN |
4102 | else if (IS_BROXTON(dev_priv)) |
4103 | return bxt_digital_port_connected(dev_priv, port); | |
0780cd36 VS |
4104 | else if (IS_GM45(dev_priv)) |
4105 | return gm45_digital_port_connected(dev_priv, port); | |
7e66bcf2 JN |
4106 | else |
4107 | return g4x_digital_port_connected(dev_priv, port); | |
4108 | } | |
4109 | ||
8c241fef | 4110 | static struct edid * |
beb60608 | 4111 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 4112 | { |
beb60608 | 4113 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
d6f24d0f | 4114 | |
9cd300e0 JN |
4115 | /* use cached edid if we have one */ |
4116 | if (intel_connector->edid) { | |
9cd300e0 JN |
4117 | /* invalid edid */ |
4118 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
4119 | return NULL; |
4120 | ||
55e9edeb | 4121 | return drm_edid_duplicate(intel_connector->edid); |
beb60608 CW |
4122 | } else |
4123 | return drm_get_edid(&intel_connector->base, | |
4124 | &intel_dp->aux.ddc); | |
4125 | } | |
8c241fef | 4126 | |
beb60608 CW |
4127 | static void |
4128 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
4129 | { | |
4130 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
4131 | struct edid *edid; | |
8c241fef | 4132 | |
f21a2198 | 4133 | intel_dp_unset_edid(intel_dp); |
beb60608 CW |
4134 | edid = intel_dp_get_edid(intel_dp); |
4135 | intel_connector->detect_edid = edid; | |
4136 | ||
4137 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) | |
4138 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; | |
4139 | else | |
4140 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
8c241fef KP |
4141 | } |
4142 | ||
beb60608 CW |
4143 | static void |
4144 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 4145 | { |
beb60608 | 4146 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8c241fef | 4147 | |
beb60608 CW |
4148 | kfree(intel_connector->detect_edid); |
4149 | intel_connector->detect_edid = NULL; | |
9cd300e0 | 4150 | |
beb60608 CW |
4151 | intel_dp->has_audio = false; |
4152 | } | |
d6f24d0f | 4153 | |
f21a2198 SS |
4154 | static void |
4155 | intel_dp_long_pulse(struct intel_connector *intel_connector) | |
a9756bb5 | 4156 | { |
f21a2198 | 4157 | struct drm_connector *connector = &intel_connector->base; |
a9756bb5 | 4158 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
d63885da PZ |
4159 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4160 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 4161 | struct drm_device *dev = connector->dev; |
a9756bb5 | 4162 | enum drm_connector_status status; |
671dedd2 | 4163 | enum intel_display_power_domain power_domain; |
0e32b39c | 4164 | bool ret; |
09b1eb13 | 4165 | u8 sink_irq_vector; |
a9756bb5 | 4166 | |
25f78f58 VS |
4167 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4168 | intel_display_power_get(to_i915(dev), power_domain); | |
a9756bb5 | 4169 | |
d410b56d CW |
4170 | /* Can't disconnect eDP, but you can close the lid... */ |
4171 | if (is_edp(intel_dp)) | |
4172 | status = edp_detect(intel_dp); | |
c555a81d ACO |
4173 | else if (intel_digital_port_connected(to_i915(dev), |
4174 | dp_to_dig_port(intel_dp))) | |
4175 | status = intel_dp_detect_dpcd(intel_dp); | |
a9756bb5 | 4176 | else |
c555a81d ACO |
4177 | status = connector_status_disconnected; |
4178 | ||
4df6960e SS |
4179 | if (status != connector_status_connected) { |
4180 | intel_dp->compliance_test_active = 0; | |
4181 | intel_dp->compliance_test_type = 0; | |
4182 | intel_dp->compliance_test_data = 0; | |
4183 | ||
0e505a08 | 4184 | if (intel_dp->is_mst) { |
4185 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4186 | intel_dp->is_mst, | |
4187 | intel_dp->mst_mgr.mst_state); | |
4188 | intel_dp->is_mst = false; | |
4189 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4190 | intel_dp->is_mst); | |
4191 | } | |
4192 | ||
c8c8fb33 | 4193 | goto out; |
4df6960e | 4194 | } |
a9756bb5 | 4195 | |
f21a2198 SS |
4196 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4197 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
4198 | ||
0d198328 AJ |
4199 | intel_dp_probe_oui(intel_dp); |
4200 | ||
0e32b39c DA |
4201 | ret = intel_dp_probe_mst(intel_dp); |
4202 | if (ret) { | |
f21a2198 SS |
4203 | /* |
4204 | * If we are in MST mode then this connector | |
4205 | * won't appear connected or have anything | |
4206 | * with EDID on it | |
4207 | */ | |
0e32b39c DA |
4208 | status = connector_status_disconnected; |
4209 | goto out; | |
7d23e3c3 SS |
4210 | } else if (connector->status == connector_status_connected) { |
4211 | /* | |
4212 | * If display was connected already and is still connected | |
4213 | * check links status, there has been known issues of | |
4214 | * link loss triggerring long pulse!!!! | |
4215 | */ | |
4216 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); | |
4217 | intel_dp_check_link_status(intel_dp); | |
4218 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
4219 | goto out; | |
0e32b39c DA |
4220 | } |
4221 | ||
4df6960e SS |
4222 | /* |
4223 | * Clearing NACK and defer counts to get their exact values | |
4224 | * while reading EDID which are required by Compliance tests | |
4225 | * 4.2.2.4 and 4.2.2.5 | |
4226 | */ | |
4227 | intel_dp->aux.i2c_nack_count = 0; | |
4228 | intel_dp->aux.i2c_defer_count = 0; | |
4229 | ||
beb60608 | 4230 | intel_dp_set_edid(intel_dp); |
a9756bb5 | 4231 | |
c8c8fb33 | 4232 | status = connector_status_connected; |
7d23e3c3 | 4233 | intel_dp->detect_done = true; |
c8c8fb33 | 4234 | |
09b1eb13 TP |
4235 | /* Try to read the source of the interrupt */ |
4236 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
4237 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
4238 | /* Clear interrupt source */ | |
4239 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
4240 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4241 | sink_irq_vector); | |
4242 | ||
4243 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
4244 | intel_dp_handle_test_request(intel_dp); | |
4245 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
4246 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4247 | } | |
4248 | ||
c8c8fb33 | 4249 | out: |
0e505a08 | 4250 | if ((status != connector_status_connected) && |
4251 | (intel_dp->is_mst == false)) | |
f21a2198 | 4252 | intel_dp_unset_edid(intel_dp); |
7d23e3c3 | 4253 | |
25f78f58 | 4254 | intel_display_power_put(to_i915(dev), power_domain); |
f21a2198 SS |
4255 | return; |
4256 | } | |
4257 | ||
4258 | static enum drm_connector_status | |
4259 | intel_dp_detect(struct drm_connector *connector, bool force) | |
4260 | { | |
4261 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
4262 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4263 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
4264 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4265 | ||
4266 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4267 | connector->base.id, connector->name); | |
4268 | ||
4269 | if (intel_dp->is_mst) { | |
4270 | /* MST devices are disconnected from a monitor POV */ | |
4271 | intel_dp_unset_edid(intel_dp); | |
4272 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
4273 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
4274 | return connector_status_disconnected; | |
4275 | } | |
4276 | ||
7d23e3c3 SS |
4277 | /* If full detect is not performed yet, do a full detect */ |
4278 | if (!intel_dp->detect_done) | |
4279 | intel_dp_long_pulse(intel_dp->attached_connector); | |
4280 | ||
4281 | intel_dp->detect_done = false; | |
f21a2198 SS |
4282 | |
4283 | if (intel_connector->detect_edid) | |
4284 | return connector_status_connected; | |
4285 | else | |
4286 | return connector_status_disconnected; | |
a4fc5ed6 KP |
4287 | } |
4288 | ||
beb60608 CW |
4289 | static void |
4290 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 4291 | { |
df0e9248 | 4292 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
beb60608 | 4293 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
25f78f58 | 4294 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
671dedd2 | 4295 | enum intel_display_power_domain power_domain; |
a4fc5ed6 | 4296 | |
beb60608 CW |
4297 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4298 | connector->base.id, connector->name); | |
4299 | intel_dp_unset_edid(intel_dp); | |
a4fc5ed6 | 4300 | |
beb60608 CW |
4301 | if (connector->status != connector_status_connected) |
4302 | return; | |
671dedd2 | 4303 | |
25f78f58 VS |
4304 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4305 | intel_display_power_get(dev_priv, power_domain); | |
beb60608 CW |
4306 | |
4307 | intel_dp_set_edid(intel_dp); | |
4308 | ||
25f78f58 | 4309 | intel_display_power_put(dev_priv, power_domain); |
beb60608 CW |
4310 | |
4311 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
4312 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
4313 | } | |
4314 | ||
4315 | static int intel_dp_get_modes(struct drm_connector *connector) | |
4316 | { | |
4317 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4318 | struct edid *edid; | |
4319 | ||
4320 | edid = intel_connector->detect_edid; | |
4321 | if (edid) { | |
4322 | int ret = intel_connector_update_modes(connector, edid); | |
4323 | if (ret) | |
4324 | return ret; | |
4325 | } | |
32f9d658 | 4326 | |
f8779fda | 4327 | /* if eDP has no EDID, fall back to fixed mode */ |
beb60608 CW |
4328 | if (is_edp(intel_attached_dp(connector)) && |
4329 | intel_connector->panel.fixed_mode) { | |
f8779fda | 4330 | struct drm_display_mode *mode; |
beb60608 CW |
4331 | |
4332 | mode = drm_mode_duplicate(connector->dev, | |
dd06f90e | 4333 | intel_connector->panel.fixed_mode); |
f8779fda | 4334 | if (mode) { |
32f9d658 ZW |
4335 | drm_mode_probed_add(connector, mode); |
4336 | return 1; | |
4337 | } | |
4338 | } | |
beb60608 | 4339 | |
32f9d658 | 4340 | return 0; |
a4fc5ed6 KP |
4341 | } |
4342 | ||
1aad7ac0 CW |
4343 | static bool |
4344 | intel_dp_detect_audio(struct drm_connector *connector) | |
4345 | { | |
1aad7ac0 | 4346 | bool has_audio = false; |
beb60608 | 4347 | struct edid *edid; |
1aad7ac0 | 4348 | |
beb60608 CW |
4349 | edid = to_intel_connector(connector)->detect_edid; |
4350 | if (edid) | |
1aad7ac0 | 4351 | has_audio = drm_detect_monitor_audio(edid); |
671dedd2 | 4352 | |
1aad7ac0 CW |
4353 | return has_audio; |
4354 | } | |
4355 | ||
f684960e CW |
4356 | static int |
4357 | intel_dp_set_property(struct drm_connector *connector, | |
4358 | struct drm_property *property, | |
4359 | uint64_t val) | |
4360 | { | |
e953fd7b | 4361 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
53b41837 | 4362 | struct intel_connector *intel_connector = to_intel_connector(connector); |
da63a9f2 PZ |
4363 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
4364 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
f684960e CW |
4365 | int ret; |
4366 | ||
662595df | 4367 | ret = drm_object_property_set_value(&connector->base, property, val); |
f684960e CW |
4368 | if (ret) |
4369 | return ret; | |
4370 | ||
3f43c48d | 4371 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
4372 | int i = val; |
4373 | bool has_audio; | |
4374 | ||
4375 | if (i == intel_dp->force_audio) | |
f684960e CW |
4376 | return 0; |
4377 | ||
1aad7ac0 | 4378 | intel_dp->force_audio = i; |
f684960e | 4379 | |
c3e5f67b | 4380 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
4381 | has_audio = intel_dp_detect_audio(connector); |
4382 | else | |
c3e5f67b | 4383 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
4384 | |
4385 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
4386 | return 0; |
4387 | ||
1aad7ac0 | 4388 | intel_dp->has_audio = has_audio; |
f684960e CW |
4389 | goto done; |
4390 | } | |
4391 | ||
e953fd7b | 4392 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 | 4393 | bool old_auto = intel_dp->color_range_auto; |
0f2a2a75 | 4394 | bool old_range = intel_dp->limited_color_range; |
ae4edb80 | 4395 | |
55bc60db VS |
4396 | switch (val) { |
4397 | case INTEL_BROADCAST_RGB_AUTO: | |
4398 | intel_dp->color_range_auto = true; | |
4399 | break; | |
4400 | case INTEL_BROADCAST_RGB_FULL: | |
4401 | intel_dp->color_range_auto = false; | |
0f2a2a75 | 4402 | intel_dp->limited_color_range = false; |
55bc60db VS |
4403 | break; |
4404 | case INTEL_BROADCAST_RGB_LIMITED: | |
4405 | intel_dp->color_range_auto = false; | |
0f2a2a75 | 4406 | intel_dp->limited_color_range = true; |
55bc60db VS |
4407 | break; |
4408 | default: | |
4409 | return -EINVAL; | |
4410 | } | |
ae4edb80 DV |
4411 | |
4412 | if (old_auto == intel_dp->color_range_auto && | |
0f2a2a75 | 4413 | old_range == intel_dp->limited_color_range) |
ae4edb80 DV |
4414 | return 0; |
4415 | ||
e953fd7b CW |
4416 | goto done; |
4417 | } | |
4418 | ||
53b41837 YN |
4419 | if (is_edp(intel_dp) && |
4420 | property == connector->dev->mode_config.scaling_mode_property) { | |
4421 | if (val == DRM_MODE_SCALE_NONE) { | |
4422 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
4423 | return -EINVAL; | |
4424 | } | |
234126c6 VS |
4425 | if (HAS_GMCH_DISPLAY(dev_priv) && |
4426 | val == DRM_MODE_SCALE_CENTER) { | |
4427 | DRM_DEBUG_KMS("centering not supported\n"); | |
4428 | return -EINVAL; | |
4429 | } | |
53b41837 YN |
4430 | |
4431 | if (intel_connector->panel.fitting_mode == val) { | |
4432 | /* the eDP scaling property is not changed */ | |
4433 | return 0; | |
4434 | } | |
4435 | intel_connector->panel.fitting_mode = val; | |
4436 | ||
4437 | goto done; | |
4438 | } | |
4439 | ||
f684960e CW |
4440 | return -EINVAL; |
4441 | ||
4442 | done: | |
c0c36b94 CW |
4443 | if (intel_encoder->base.crtc) |
4444 | intel_crtc_restore_mode(intel_encoder->base.crtc); | |
f684960e CW |
4445 | |
4446 | return 0; | |
4447 | } | |
4448 | ||
c191eca1 CW |
4449 | static void |
4450 | intel_dp_connector_unregister(struct drm_connector *connector) | |
4451 | { | |
4452 | drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); | |
4453 | intel_connector_unregister(connector); | |
4454 | } | |
4455 | ||
a4fc5ed6 | 4456 | static void |
73845adf | 4457 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 4458 | { |
1d508706 | 4459 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 4460 | |
10e972d3 | 4461 | kfree(intel_connector->detect_edid); |
beb60608 | 4462 | |
9cd300e0 JN |
4463 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4464 | kfree(intel_connector->edid); | |
4465 | ||
c191eca1 CW |
4466 | intel_dp_aux_fini(intel_attached_dp(connector)); |
4467 | ||
acd8db10 PZ |
4468 | /* Can't call is_edp() since the encoder may have been destroyed |
4469 | * already. */ | |
4470 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
1d508706 | 4471 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 4472 | |
a4fc5ed6 | 4473 | drm_connector_cleanup(connector); |
55f78c43 | 4474 | kfree(connector); |
a4fc5ed6 KP |
4475 | } |
4476 | ||
00c09d70 | 4477 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 4478 | { |
da63a9f2 PZ |
4479 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4480 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
24d05927 | 4481 | |
0e32b39c | 4482 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
bd943159 KP |
4483 | if (is_edp(intel_dp)) { |
4484 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
951468f3 VS |
4485 | /* |
4486 | * vdd might still be enabled do to the delayed vdd off. | |
4487 | * Make sure vdd is actually turned off here. | |
4488 | */ | |
773538e8 | 4489 | pps_lock(intel_dp); |
4be73780 | 4490 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 VS |
4491 | pps_unlock(intel_dp); |
4492 | ||
01527b31 CT |
4493 | if (intel_dp->edp_notifier.notifier_call) { |
4494 | unregister_reboot_notifier(&intel_dp->edp_notifier); | |
4495 | intel_dp->edp_notifier.notifier_call = NULL; | |
4496 | } | |
bd943159 | 4497 | } |
c8bd0e49 | 4498 | drm_encoder_cleanup(encoder); |
da63a9f2 | 4499 | kfree(intel_dig_port); |
24d05927 DV |
4500 | } |
4501 | ||
bf93ba67 | 4502 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
07f9cd0b ID |
4503 | { |
4504 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
4505 | ||
4506 | if (!is_edp(intel_dp)) | |
4507 | return; | |
4508 | ||
951468f3 VS |
4509 | /* |
4510 | * vdd might still be enabled do to the delayed vdd off. | |
4511 | * Make sure vdd is actually turned off here. | |
4512 | */ | |
afa4e53a | 4513 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
773538e8 | 4514 | pps_lock(intel_dp); |
07f9cd0b | 4515 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 | 4516 | pps_unlock(intel_dp); |
07f9cd0b ID |
4517 | } |
4518 | ||
49e6bc51 VS |
4519 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
4520 | { | |
4521 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4522 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
4523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4524 | enum intel_display_power_domain power_domain; | |
4525 | ||
4526 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4527 | ||
4528 | if (!edp_have_panel_vdd(intel_dp)) | |
4529 | return; | |
4530 | ||
4531 | /* | |
4532 | * The VDD bit needs a power domain reference, so if the bit is | |
4533 | * already enabled when we boot or resume, grab this reference and | |
4534 | * schedule a vdd off, so we don't hold on to the reference | |
4535 | * indefinitely. | |
4536 | */ | |
4537 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); | |
25f78f58 | 4538 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
49e6bc51 VS |
4539 | intel_display_power_get(dev_priv, power_domain); |
4540 | ||
4541 | edp_panel_vdd_schedule_off(intel_dp); | |
4542 | } | |
4543 | ||
bf93ba67 | 4544 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
6d93c0c4 | 4545 | { |
49e6bc51 VS |
4546 | struct intel_dp *intel_dp; |
4547 | ||
4548 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) | |
4549 | return; | |
4550 | ||
4551 | intel_dp = enc_to_intel_dp(encoder); | |
4552 | ||
4553 | pps_lock(intel_dp); | |
4554 | ||
4555 | /* | |
4556 | * Read out the current power sequencer assignment, | |
4557 | * in case the BIOS did something with it. | |
4558 | */ | |
666a4537 | 4559 | if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev)) |
49e6bc51 VS |
4560 | vlv_initial_power_sequencer_setup(intel_dp); |
4561 | ||
4562 | intel_edp_panel_vdd_sanitize(intel_dp); | |
4563 | ||
4564 | pps_unlock(intel_dp); | |
6d93c0c4 ID |
4565 | } |
4566 | ||
a4fc5ed6 | 4567 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
4d688a2a | 4568 | .dpms = drm_atomic_helper_connector_dpms, |
a4fc5ed6 | 4569 | .detect = intel_dp_detect, |
beb60608 | 4570 | .force = intel_dp_force, |
a4fc5ed6 | 4571 | .fill_modes = drm_helper_probe_single_connector_modes, |
f684960e | 4572 | .set_property = intel_dp_set_property, |
2545e4a6 | 4573 | .atomic_get_property = intel_connector_atomic_get_property, |
c191eca1 | 4574 | .early_unregister = intel_dp_connector_unregister, |
73845adf | 4575 | .destroy = intel_dp_connector_destroy, |
c6f95f27 | 4576 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 4577 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
a4fc5ed6 KP |
4578 | }; |
4579 | ||
4580 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
4581 | .get_modes = intel_dp_get_modes, | |
4582 | .mode_valid = intel_dp_mode_valid, | |
a4fc5ed6 KP |
4583 | }; |
4584 | ||
a4fc5ed6 | 4585 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
6d93c0c4 | 4586 | .reset = intel_dp_encoder_reset, |
24d05927 | 4587 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
4588 | }; |
4589 | ||
b2c5c181 | 4590 | enum irqreturn |
13cf5504 DA |
4591 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
4592 | { | |
4593 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1c767b33 | 4594 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
0e32b39c DA |
4595 | struct drm_device *dev = intel_dig_port->base.base.dev; |
4596 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1c767b33 | 4597 | enum intel_display_power_domain power_domain; |
b2c5c181 | 4598 | enum irqreturn ret = IRQ_NONE; |
1c767b33 | 4599 | |
2540058f TI |
4600 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
4601 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) | |
0e32b39c | 4602 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
13cf5504 | 4603 | |
7a7f84cc VS |
4604 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
4605 | /* | |
4606 | * vdd off can generate a long pulse on eDP which | |
4607 | * would require vdd on to handle it, and thus we | |
4608 | * would end up in an endless cycle of | |
4609 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." | |
4610 | */ | |
4611 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", | |
4612 | port_name(intel_dig_port->port)); | |
a8b3d52f | 4613 | return IRQ_HANDLED; |
7a7f84cc VS |
4614 | } |
4615 | ||
26fbb774 VS |
4616 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
4617 | port_name(intel_dig_port->port), | |
0e32b39c | 4618 | long_hpd ? "long" : "short"); |
13cf5504 | 4619 | |
25f78f58 | 4620 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1c767b33 ID |
4621 | intel_display_power_get(dev_priv, power_domain); |
4622 | ||
0e32b39c | 4623 | if (long_hpd) { |
5fa836a9 MK |
4624 | /* indicate that we need to restart link training */ |
4625 | intel_dp->train_set_valid = false; | |
2a592bec | 4626 | |
7d23e3c3 SS |
4627 | intel_dp_long_pulse(intel_dp->attached_connector); |
4628 | if (intel_dp->is_mst) | |
4629 | ret = IRQ_HANDLED; | |
4630 | goto put_power; | |
0e32b39c | 4631 | |
0e32b39c DA |
4632 | } else { |
4633 | if (intel_dp->is_mst) { | |
7d23e3c3 SS |
4634 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { |
4635 | /* | |
4636 | * If we were in MST mode, and device is not | |
4637 | * there, get out of MST mode | |
4638 | */ | |
4639 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4640 | intel_dp->is_mst, intel_dp->mst_mgr.mst_state); | |
4641 | intel_dp->is_mst = false; | |
4642 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4643 | intel_dp->is_mst); | |
4644 | goto put_power; | |
4645 | } | |
0e32b39c DA |
4646 | } |
4647 | ||
39ff747b SS |
4648 | if (!intel_dp->is_mst) { |
4649 | if (!intel_dp_short_pulse(intel_dp)) { | |
4650 | intel_dp_long_pulse(intel_dp->attached_connector); | |
4651 | goto put_power; | |
4652 | } | |
4653 | } | |
0e32b39c | 4654 | } |
b2c5c181 DV |
4655 | |
4656 | ret = IRQ_HANDLED; | |
4657 | ||
1c767b33 ID |
4658 | put_power: |
4659 | intel_display_power_put(dev_priv, power_domain); | |
4660 | ||
4661 | return ret; | |
13cf5504 DA |
4662 | } |
4663 | ||
477ec328 | 4664 | /* check the VBT to see whether the eDP is on another port */ |
5d8a7752 | 4665 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
36e83a18 ZY |
4666 | { |
4667 | struct drm_i915_private *dev_priv = dev->dev_private; | |
36e83a18 | 4668 | |
53ce81a7 VS |
4669 | /* |
4670 | * eDP not supported on g4x. so bail out early just | |
4671 | * for a bit extra safety in case the VBT is bonkers. | |
4672 | */ | |
4673 | if (INTEL_INFO(dev)->gen < 5) | |
4674 | return false; | |
4675 | ||
3b32a35b VS |
4676 | if (port == PORT_A) |
4677 | return true; | |
4678 | ||
951d9efe | 4679 | return intel_bios_is_port_edp(dev_priv, port); |
36e83a18 ZY |
4680 | } |
4681 | ||
0e32b39c | 4682 | void |
f684960e CW |
4683 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
4684 | { | |
53b41837 YN |
4685 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4686 | ||
3f43c48d | 4687 | intel_attach_force_audio_property(connector); |
e953fd7b | 4688 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 4689 | intel_dp->color_range_auto = true; |
53b41837 YN |
4690 | |
4691 | if (is_edp(intel_dp)) { | |
4692 | drm_mode_create_scaling_mode_property(connector->dev); | |
6de6d846 RC |
4693 | drm_object_attach_property( |
4694 | &connector->base, | |
53b41837 | 4695 | connector->dev->mode_config.scaling_mode_property, |
8e740cd1 YN |
4696 | DRM_MODE_SCALE_ASPECT); |
4697 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
53b41837 | 4698 | } |
f684960e CW |
4699 | } |
4700 | ||
dada1a9f ID |
4701 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
4702 | { | |
d28d4731 | 4703 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
dada1a9f ID |
4704 | intel_dp->last_power_on = jiffies; |
4705 | intel_dp->last_backlight_off = jiffies; | |
4706 | } | |
4707 | ||
67a54566 DV |
4708 | static void |
4709 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
36b5f425 | 4710 | struct intel_dp *intel_dp) |
67a54566 DV |
4711 | { |
4712 | struct drm_i915_private *dev_priv = dev->dev_private; | |
36b5f425 VS |
4713 | struct edp_power_seq cur, vbt, spec, |
4714 | *final = &intel_dp->pps_delays; | |
b0a08bec | 4715 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
f0f59a00 | 4716 | i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
453c5420 | 4717 | |
e39b999a VS |
4718 | lockdep_assert_held(&dev_priv->pps_mutex); |
4719 | ||
81ddbc69 VS |
4720 | /* already initialized? */ |
4721 | if (final->t11_t12 != 0) | |
4722 | return; | |
4723 | ||
b0a08bec VK |
4724 | if (IS_BROXTON(dev)) { |
4725 | /* | |
4726 | * TODO: BXT has 2 sets of PPS registers. | |
4727 | * Correct Register for Broxton need to be identified | |
4728 | * using VBT. hardcoding for now | |
4729 | */ | |
4730 | pp_ctrl_reg = BXT_PP_CONTROL(0); | |
4731 | pp_on_reg = BXT_PP_ON_DELAYS(0); | |
4732 | pp_off_reg = BXT_PP_OFF_DELAYS(0); | |
4733 | } else if (HAS_PCH_SPLIT(dev)) { | |
bf13e81b | 4734 | pp_ctrl_reg = PCH_PP_CONTROL; |
453c5420 JB |
4735 | pp_on_reg = PCH_PP_ON_DELAYS; |
4736 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
4737 | pp_div_reg = PCH_PP_DIVISOR; | |
4738 | } else { | |
bf13e81b JN |
4739 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
4740 | ||
4741 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); | |
4742 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
4743 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
4744 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 | 4745 | } |
67a54566 DV |
4746 | |
4747 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
4748 | * the very first thing. */ | |
b0a08bec | 4749 | pp_ctl = ironlake_get_pp_control(intel_dp); |
67a54566 | 4750 | |
453c5420 JB |
4751 | pp_on = I915_READ(pp_on_reg); |
4752 | pp_off = I915_READ(pp_off_reg); | |
b0a08bec VK |
4753 | if (!IS_BROXTON(dev)) { |
4754 | I915_WRITE(pp_ctrl_reg, pp_ctl); | |
4755 | pp_div = I915_READ(pp_div_reg); | |
4756 | } | |
67a54566 DV |
4757 | |
4758 | /* Pull timing values out of registers */ | |
4759 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
4760 | PANEL_POWER_UP_DELAY_SHIFT; | |
4761 | ||
4762 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
4763 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
4764 | ||
4765 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
4766 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
4767 | ||
4768 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
4769 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
4770 | ||
b0a08bec VK |
4771 | if (IS_BROXTON(dev)) { |
4772 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> | |
4773 | BXT_POWER_CYCLE_DELAY_SHIFT; | |
4774 | if (tmp > 0) | |
4775 | cur.t11_t12 = (tmp - 1) * 1000; | |
4776 | else | |
4777 | cur.t11_t12 = 0; | |
4778 | } else { | |
4779 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
67a54566 | 4780 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
b0a08bec | 4781 | } |
67a54566 DV |
4782 | |
4783 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
4784 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
4785 | ||
6aa23e65 | 4786 | vbt = dev_priv->vbt.edp.pps; |
67a54566 DV |
4787 | |
4788 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
4789 | * our hw here, which are all in 100usec. */ | |
4790 | spec.t1_t3 = 210 * 10; | |
4791 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
4792 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
4793 | spec.t10 = 500 * 10; | |
4794 | /* This one is special and actually in units of 100ms, but zero | |
4795 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
4796 | * table multiplies it with 1000 to make it in units of 100usec, | |
4797 | * too. */ | |
4798 | spec.t11_t12 = (510 + 100) * 10; | |
4799 | ||
4800 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
4801 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
4802 | ||
4803 | /* Use the max of the register settings and vbt. If both are | |
4804 | * unset, fall back to the spec limits. */ | |
36b5f425 | 4805 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
67a54566 DV |
4806 | spec.field : \ |
4807 | max(cur.field, vbt.field)) | |
4808 | assign_final(t1_t3); | |
4809 | assign_final(t8); | |
4810 | assign_final(t9); | |
4811 | assign_final(t10); | |
4812 | assign_final(t11_t12); | |
4813 | #undef assign_final | |
4814 | ||
36b5f425 | 4815 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
67a54566 DV |
4816 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
4817 | intel_dp->backlight_on_delay = get_delay(t8); | |
4818 | intel_dp->backlight_off_delay = get_delay(t9); | |
4819 | intel_dp->panel_power_down_delay = get_delay(t10); | |
4820 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
4821 | #undef get_delay | |
4822 | ||
f30d26e4 JN |
4823 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
4824 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
4825 | intel_dp->panel_power_cycle_delay); | |
4826 | ||
4827 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
4828 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
f30d26e4 JN |
4829 | } |
4830 | ||
4831 | static void | |
4832 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
36b5f425 | 4833 | struct intel_dp *intel_dp) |
f30d26e4 JN |
4834 | { |
4835 | struct drm_i915_private *dev_priv = dev->dev_private; | |
453c5420 | 4836 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
e7dc33f3 | 4837 | int div = dev_priv->rawclk_freq / 1000; |
f0f59a00 | 4838 | i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg; |
ad933b56 | 4839 | enum port port = dp_to_dig_port(intel_dp)->port; |
36b5f425 | 4840 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
453c5420 | 4841 | |
e39b999a | 4842 | lockdep_assert_held(&dev_priv->pps_mutex); |
453c5420 | 4843 | |
b0a08bec VK |
4844 | if (IS_BROXTON(dev)) { |
4845 | /* | |
4846 | * TODO: BXT has 2 sets of PPS registers. | |
4847 | * Correct Register for Broxton need to be identified | |
4848 | * using VBT. hardcoding for now | |
4849 | */ | |
4850 | pp_ctrl_reg = BXT_PP_CONTROL(0); | |
4851 | pp_on_reg = BXT_PP_ON_DELAYS(0); | |
4852 | pp_off_reg = BXT_PP_OFF_DELAYS(0); | |
4853 | ||
4854 | } else if (HAS_PCH_SPLIT(dev)) { | |
453c5420 JB |
4855 | pp_on_reg = PCH_PP_ON_DELAYS; |
4856 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
4857 | pp_div_reg = PCH_PP_DIVISOR; | |
4858 | } else { | |
bf13e81b JN |
4859 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
4860 | ||
4861 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
4862 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
4863 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 JB |
4864 | } |
4865 | ||
b2f19d1a PZ |
4866 | /* |
4867 | * And finally store the new values in the power sequencer. The | |
4868 | * backlight delays are set to 1 because we do manual waits on them. For | |
4869 | * T8, even BSpec recommends doing it. For T9, if we don't do this, | |
4870 | * we'll end up waiting for the backlight off delay twice: once when we | |
4871 | * do the manual sleep, and once when we disable the panel and wait for | |
4872 | * the PP_STATUS bit to become zero. | |
4873 | */ | |
f30d26e4 | 4874 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
b2f19d1a PZ |
4875 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
4876 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 4877 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
4878 | /* Compute the divisor for the pp clock, simply match the Bspec |
4879 | * formula. */ | |
b0a08bec VK |
4880 | if (IS_BROXTON(dev)) { |
4881 | pp_div = I915_READ(pp_ctrl_reg); | |
4882 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; | |
4883 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) | |
4884 | << BXT_POWER_CYCLE_DELAY_SHIFT); | |
4885 | } else { | |
4886 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; | |
4887 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) | |
4888 | << PANEL_POWER_CYCLE_DELAY_SHIFT); | |
4889 | } | |
67a54566 DV |
4890 | |
4891 | /* Haswell doesn't have any port selection bits for the panel | |
4892 | * power sequencer any more. */ | |
666a4537 | 4893 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ad933b56 | 4894 | port_sel = PANEL_PORT_SELECT_VLV(port); |
bc7d38a4 | 4895 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
ad933b56 | 4896 | if (port == PORT_A) |
a24c144c | 4897 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 4898 | else |
a24c144c | 4899 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
4900 | } |
4901 | ||
453c5420 JB |
4902 | pp_on |= port_sel; |
4903 | ||
4904 | I915_WRITE(pp_on_reg, pp_on); | |
4905 | I915_WRITE(pp_off_reg, pp_off); | |
b0a08bec VK |
4906 | if (IS_BROXTON(dev)) |
4907 | I915_WRITE(pp_ctrl_reg, pp_div); | |
4908 | else | |
4909 | I915_WRITE(pp_div_reg, pp_div); | |
67a54566 | 4910 | |
67a54566 | 4911 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
453c5420 JB |
4912 | I915_READ(pp_on_reg), |
4913 | I915_READ(pp_off_reg), | |
b0a08bec VK |
4914 | IS_BROXTON(dev) ? |
4915 | (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) : | |
453c5420 | 4916 | I915_READ(pp_div_reg)); |
f684960e CW |
4917 | } |
4918 | ||
b33a2815 VK |
4919 | /** |
4920 | * intel_dp_set_drrs_state - program registers for RR switch to take effect | |
4921 | * @dev: DRM device | |
4922 | * @refresh_rate: RR to be programmed | |
4923 | * | |
4924 | * This function gets called when refresh rate (RR) has to be changed from | |
4925 | * one frequency to another. Switches can be between high and low RR | |
4926 | * supported by the panel or to any other RR based on media playback (in | |
4927 | * this case, RR value needs to be passed from user space). | |
4928 | * | |
4929 | * The caller of this function needs to take a lock on dev_priv->drrs. | |
4930 | */ | |
96178eeb | 4931 | static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
439d7ac0 PB |
4932 | { |
4933 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4934 | struct intel_encoder *encoder; | |
96178eeb VK |
4935 | struct intel_digital_port *dig_port = NULL; |
4936 | struct intel_dp *intel_dp = dev_priv->drrs.dp; | |
5cec258b | 4937 | struct intel_crtc_state *config = NULL; |
439d7ac0 | 4938 | struct intel_crtc *intel_crtc = NULL; |
96178eeb | 4939 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
439d7ac0 PB |
4940 | |
4941 | if (refresh_rate <= 0) { | |
4942 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); | |
4943 | return; | |
4944 | } | |
4945 | ||
96178eeb VK |
4946 | if (intel_dp == NULL) { |
4947 | DRM_DEBUG_KMS("DRRS not supported.\n"); | |
439d7ac0 PB |
4948 | return; |
4949 | } | |
4950 | ||
1fcc9d1c | 4951 | /* |
e4d59f6b RV |
4952 | * FIXME: This needs proper synchronization with psr state for some |
4953 | * platforms that cannot have PSR and DRRS enabled at the same time. | |
1fcc9d1c | 4954 | */ |
439d7ac0 | 4955 | |
96178eeb VK |
4956 | dig_port = dp_to_dig_port(intel_dp); |
4957 | encoder = &dig_port->base; | |
723f9aab | 4958 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
439d7ac0 PB |
4959 | |
4960 | if (!intel_crtc) { | |
4961 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); | |
4962 | return; | |
4963 | } | |
4964 | ||
6e3c9717 | 4965 | config = intel_crtc->config; |
439d7ac0 | 4966 | |
96178eeb | 4967 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
439d7ac0 PB |
4968 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
4969 | return; | |
4970 | } | |
4971 | ||
96178eeb VK |
4972 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
4973 | refresh_rate) | |
439d7ac0 PB |
4974 | index = DRRS_LOW_RR; |
4975 | ||
96178eeb | 4976 | if (index == dev_priv->drrs.refresh_rate_type) { |
439d7ac0 PB |
4977 | DRM_DEBUG_KMS( |
4978 | "DRRS requested for previously set RR...ignoring\n"); | |
4979 | return; | |
4980 | } | |
4981 | ||
4982 | if (!intel_crtc->active) { | |
4983 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); | |
4984 | return; | |
4985 | } | |
4986 | ||
44395bfe | 4987 | if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { |
a4c30b1d VK |
4988 | switch (index) { |
4989 | case DRRS_HIGH_RR: | |
4990 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
4991 | break; | |
4992 | case DRRS_LOW_RR: | |
4993 | intel_dp_set_m_n(intel_crtc, M2_N2); | |
4994 | break; | |
4995 | case DRRS_MAX_RR: | |
4996 | default: | |
4997 | DRM_ERROR("Unsupported refreshrate type\n"); | |
4998 | } | |
4999 | } else if (INTEL_INFO(dev)->gen > 6) { | |
f0f59a00 | 5000 | i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); |
649636ef | 5001 | u32 val; |
a4c30b1d | 5002 | |
649636ef | 5003 | val = I915_READ(reg); |
439d7ac0 | 5004 | if (index > DRRS_HIGH_RR) { |
666a4537 | 5005 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6fa7aec1 VK |
5006 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5007 | else | |
5008 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 5009 | } else { |
666a4537 | 5010 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6fa7aec1 VK |
5011 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5012 | else | |
5013 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 PB |
5014 | } |
5015 | I915_WRITE(reg, val); | |
5016 | } | |
5017 | ||
4e9ac947 VK |
5018 | dev_priv->drrs.refresh_rate_type = index; |
5019 | ||
5020 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); | |
5021 | } | |
5022 | ||
b33a2815 VK |
5023 | /** |
5024 | * intel_edp_drrs_enable - init drrs struct if supported | |
5025 | * @intel_dp: DP struct | |
5026 | * | |
5027 | * Initializes frontbuffer_bits and drrs.dp | |
5028 | */ | |
c395578e VK |
5029 | void intel_edp_drrs_enable(struct intel_dp *intel_dp) |
5030 | { | |
5031 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
5032 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5033 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
5034 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
5035 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5036 | ||
5037 | if (!intel_crtc->config->has_drrs) { | |
5038 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); | |
5039 | return; | |
5040 | } | |
5041 | ||
5042 | mutex_lock(&dev_priv->drrs.mutex); | |
5043 | if (WARN_ON(dev_priv->drrs.dp)) { | |
5044 | DRM_ERROR("DRRS already enabled\n"); | |
5045 | goto unlock; | |
5046 | } | |
5047 | ||
5048 | dev_priv->drrs.busy_frontbuffer_bits = 0; | |
5049 | ||
5050 | dev_priv->drrs.dp = intel_dp; | |
5051 | ||
5052 | unlock: | |
5053 | mutex_unlock(&dev_priv->drrs.mutex); | |
5054 | } | |
5055 | ||
b33a2815 VK |
5056 | /** |
5057 | * intel_edp_drrs_disable - Disable DRRS | |
5058 | * @intel_dp: DP struct | |
5059 | * | |
5060 | */ | |
c395578e VK |
5061 | void intel_edp_drrs_disable(struct intel_dp *intel_dp) |
5062 | { | |
5063 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
5064 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5065 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
5066 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
5067 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5068 | ||
5069 | if (!intel_crtc->config->has_drrs) | |
5070 | return; | |
5071 | ||
5072 | mutex_lock(&dev_priv->drrs.mutex); | |
5073 | if (!dev_priv->drrs.dp) { | |
5074 | mutex_unlock(&dev_priv->drrs.mutex); | |
5075 | return; | |
5076 | } | |
5077 | ||
5078 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) | |
5079 | intel_dp_set_drrs_state(dev_priv->dev, | |
5080 | intel_dp->attached_connector->panel. | |
5081 | fixed_mode->vrefresh); | |
5082 | ||
5083 | dev_priv->drrs.dp = NULL; | |
5084 | mutex_unlock(&dev_priv->drrs.mutex); | |
5085 | ||
5086 | cancel_delayed_work_sync(&dev_priv->drrs.work); | |
5087 | } | |
5088 | ||
4e9ac947 VK |
5089 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5090 | { | |
5091 | struct drm_i915_private *dev_priv = | |
5092 | container_of(work, typeof(*dev_priv), drrs.work.work); | |
5093 | struct intel_dp *intel_dp; | |
5094 | ||
5095 | mutex_lock(&dev_priv->drrs.mutex); | |
5096 | ||
5097 | intel_dp = dev_priv->drrs.dp; | |
5098 | ||
5099 | if (!intel_dp) | |
5100 | goto unlock; | |
5101 | ||
439d7ac0 | 5102 | /* |
4e9ac947 VK |
5103 | * The delayed work can race with an invalidate hence we need to |
5104 | * recheck. | |
439d7ac0 PB |
5105 | */ |
5106 | ||
4e9ac947 VK |
5107 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5108 | goto unlock; | |
439d7ac0 | 5109 | |
4e9ac947 VK |
5110 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) |
5111 | intel_dp_set_drrs_state(dev_priv->dev, | |
5112 | intel_dp->attached_connector->panel. | |
5113 | downclock_mode->vrefresh); | |
439d7ac0 | 5114 | |
4e9ac947 | 5115 | unlock: |
4e9ac947 | 5116 | mutex_unlock(&dev_priv->drrs.mutex); |
439d7ac0 PB |
5117 | } |
5118 | ||
b33a2815 | 5119 | /** |
0ddfd203 | 5120 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
b33a2815 VK |
5121 | * @dev: DRM device |
5122 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
5123 | * | |
0ddfd203 R |
5124 | * This function gets called everytime rendering on the given planes start. |
5125 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). | |
b33a2815 VK |
5126 | * |
5127 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5128 | */ | |
a93fad0f VK |
5129 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
5130 | unsigned frontbuffer_bits) | |
5131 | { | |
5132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5133 | struct drm_crtc *crtc; | |
5134 | enum pipe pipe; | |
5135 | ||
9da7d693 | 5136 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5137 | return; |
5138 | ||
88f933a8 | 5139 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5140 | |
a93fad0f | 5141 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5142 | if (!dev_priv->drrs.dp) { |
5143 | mutex_unlock(&dev_priv->drrs.mutex); | |
5144 | return; | |
5145 | } | |
5146 | ||
a93fad0f VK |
5147 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5148 | pipe = to_intel_crtc(crtc)->pipe; | |
5149 | ||
c1d038c6 DV |
5150 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5151 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; | |
5152 | ||
0ddfd203 | 5153 | /* invalidate means busy screen hence upclock */ |
c1d038c6 | 5154 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
a93fad0f VK |
5155 | intel_dp_set_drrs_state(dev_priv->dev, |
5156 | dev_priv->drrs.dp->attached_connector->panel. | |
5157 | fixed_mode->vrefresh); | |
a93fad0f | 5158 | |
a93fad0f VK |
5159 | mutex_unlock(&dev_priv->drrs.mutex); |
5160 | } | |
5161 | ||
b33a2815 | 5162 | /** |
0ddfd203 | 5163 | * intel_edp_drrs_flush - Restart Idleness DRRS |
b33a2815 VK |
5164 | * @dev: DRM device |
5165 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
5166 | * | |
0ddfd203 R |
5167 | * This function gets called every time rendering on the given planes has |
5168 | * completed or flip on a crtc is completed. So DRRS should be upclocked | |
5169 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, | |
5170 | * if no other planes are dirty. | |
b33a2815 VK |
5171 | * |
5172 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5173 | */ | |
a93fad0f VK |
5174 | void intel_edp_drrs_flush(struct drm_device *dev, |
5175 | unsigned frontbuffer_bits) | |
5176 | { | |
5177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5178 | struct drm_crtc *crtc; | |
5179 | enum pipe pipe; | |
5180 | ||
9da7d693 | 5181 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5182 | return; |
5183 | ||
88f933a8 | 5184 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5185 | |
a93fad0f | 5186 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5187 | if (!dev_priv->drrs.dp) { |
5188 | mutex_unlock(&dev_priv->drrs.mutex); | |
5189 | return; | |
5190 | } | |
5191 | ||
a93fad0f VK |
5192 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5193 | pipe = to_intel_crtc(crtc)->pipe; | |
c1d038c6 DV |
5194 | |
5195 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
a93fad0f VK |
5196 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5197 | ||
0ddfd203 | 5198 | /* flush means busy screen hence upclock */ |
c1d038c6 | 5199 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
0ddfd203 R |
5200 | intel_dp_set_drrs_state(dev_priv->dev, |
5201 | dev_priv->drrs.dp->attached_connector->panel. | |
5202 | fixed_mode->vrefresh); | |
5203 | ||
5204 | /* | |
5205 | * flush also means no more activity hence schedule downclock, if all | |
5206 | * other fbs are quiescent too | |
5207 | */ | |
5208 | if (!dev_priv->drrs.busy_frontbuffer_bits) | |
a93fad0f VK |
5209 | schedule_delayed_work(&dev_priv->drrs.work, |
5210 | msecs_to_jiffies(1000)); | |
5211 | mutex_unlock(&dev_priv->drrs.mutex); | |
5212 | } | |
5213 | ||
b33a2815 VK |
5214 | /** |
5215 | * DOC: Display Refresh Rate Switching (DRRS) | |
5216 | * | |
5217 | * Display Refresh Rate Switching (DRRS) is a power conservation feature | |
5218 | * which enables swtching between low and high refresh rates, | |
5219 | * dynamically, based on the usage scenario. This feature is applicable | |
5220 | * for internal panels. | |
5221 | * | |
5222 | * Indication that the panel supports DRRS is given by the panel EDID, which | |
5223 | * would list multiple refresh rates for one resolution. | |
5224 | * | |
5225 | * DRRS is of 2 types - static and seamless. | |
5226 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset | |
5227 | * (may appear as a blink on screen) and is used in dock-undock scenario. | |
5228 | * Seamless DRRS involves changing RR without any visual effect to the user | |
5229 | * and can be used during normal system usage. This is done by programming | |
5230 | * certain registers. | |
5231 | * | |
5232 | * Support for static/seamless DRRS may be indicated in the VBT based on | |
5233 | * inputs from the panel spec. | |
5234 | * | |
5235 | * DRRS saves power by switching to low RR based on usage scenarios. | |
5236 | * | |
2e7a5701 DV |
5237 | * The implementation is based on frontbuffer tracking implementation. When |
5238 | * there is a disturbance on the screen triggered by user activity or a periodic | |
5239 | * system activity, DRRS is disabled (RR is changed to high RR). When there is | |
5240 | * no movement on screen, after a timeout of 1 second, a switch to low RR is | |
5241 | * made. | |
5242 | * | |
5243 | * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() | |
5244 | * and intel_edp_drrs_flush() are called. | |
b33a2815 VK |
5245 | * |
5246 | * DRRS can be further extended to support other internal panels and also | |
5247 | * the scenario of video playback wherein RR is set based on the rate | |
5248 | * requested by userspace. | |
5249 | */ | |
5250 | ||
5251 | /** | |
5252 | * intel_dp_drrs_init - Init basic DRRS work and mutex. | |
5253 | * @intel_connector: eDP connector | |
5254 | * @fixed_mode: preferred mode of panel | |
5255 | * | |
5256 | * This function is called only once at driver load to initialize basic | |
5257 | * DRRS stuff. | |
5258 | * | |
5259 | * Returns: | |
5260 | * Downclock mode if panel supports it, else return NULL. | |
5261 | * DRRS support is determined by the presence of downclock mode (apart | |
5262 | * from VBT setting). | |
5263 | */ | |
4f9db5b5 | 5264 | static struct drm_display_mode * |
96178eeb VK |
5265 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5266 | struct drm_display_mode *fixed_mode) | |
4f9db5b5 PB |
5267 | { |
5268 | struct drm_connector *connector = &intel_connector->base; | |
96178eeb | 5269 | struct drm_device *dev = connector->dev; |
4f9db5b5 PB |
5270 | struct drm_i915_private *dev_priv = dev->dev_private; |
5271 | struct drm_display_mode *downclock_mode = NULL; | |
5272 | ||
9da7d693 DV |
5273 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5274 | mutex_init(&dev_priv->drrs.mutex); | |
5275 | ||
4f9db5b5 PB |
5276 | if (INTEL_INFO(dev)->gen <= 6) { |
5277 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); | |
5278 | return NULL; | |
5279 | } | |
5280 | ||
5281 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
4079b8d1 | 5282 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
4f9db5b5 PB |
5283 | return NULL; |
5284 | } | |
5285 | ||
5286 | downclock_mode = intel_find_panel_downclock | |
5287 | (dev, fixed_mode, connector); | |
5288 | ||
5289 | if (!downclock_mode) { | |
a1d26342 | 5290 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
4f9db5b5 PB |
5291 | return NULL; |
5292 | } | |
5293 | ||
96178eeb | 5294 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
4f9db5b5 | 5295 | |
96178eeb | 5296 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
4079b8d1 | 5297 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
4f9db5b5 PB |
5298 | return downclock_mode; |
5299 | } | |
5300 | ||
ed92f0b2 | 5301 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 5302 | struct intel_connector *intel_connector) |
ed92f0b2 PZ |
5303 | { |
5304 | struct drm_connector *connector = &intel_connector->base; | |
5305 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
63635217 PZ |
5306 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5307 | struct drm_device *dev = intel_encoder->base.dev; | |
ed92f0b2 PZ |
5308 | struct drm_i915_private *dev_priv = dev->dev_private; |
5309 | struct drm_display_mode *fixed_mode = NULL; | |
4f9db5b5 | 5310 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 PZ |
5311 | bool has_dpcd; |
5312 | struct drm_display_mode *scan; | |
5313 | struct edid *edid; | |
6517d273 | 5314 | enum pipe pipe = INVALID_PIPE; |
ed92f0b2 PZ |
5315 | |
5316 | if (!is_edp(intel_dp)) | |
5317 | return true; | |
5318 | ||
49e6bc51 VS |
5319 | pps_lock(intel_dp); |
5320 | intel_edp_panel_vdd_sanitize(intel_dp); | |
5321 | pps_unlock(intel_dp); | |
63635217 | 5322 | |
ed92f0b2 | 5323 | /* Cache DPCD and EDID for edp. */ |
ed92f0b2 | 5324 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
ed92f0b2 PZ |
5325 | |
5326 | if (has_dpcd) { | |
5327 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) | |
5328 | dev_priv->no_aux_handshake = | |
5329 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
5330 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
5331 | } else { | |
5332 | /* if this fails, presume the device is a ghost */ | |
5333 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
ed92f0b2 PZ |
5334 | return false; |
5335 | } | |
5336 | ||
5337 | /* We now know it's not a ghost, init power sequence regs. */ | |
773538e8 | 5338 | pps_lock(intel_dp); |
36b5f425 | 5339 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
773538e8 | 5340 | pps_unlock(intel_dp); |
ed92f0b2 | 5341 | |
060c8778 | 5342 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 5343 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
5344 | if (edid) { |
5345 | if (drm_add_edid_modes(connector, edid)) { | |
5346 | drm_mode_connector_update_edid_property(connector, | |
5347 | edid); | |
5348 | drm_edid_to_eld(connector, edid); | |
5349 | } else { | |
5350 | kfree(edid); | |
5351 | edid = ERR_PTR(-EINVAL); | |
5352 | } | |
5353 | } else { | |
5354 | edid = ERR_PTR(-ENOENT); | |
5355 | } | |
5356 | intel_connector->edid = edid; | |
5357 | ||
5358 | /* prefer fixed mode from EDID if available */ | |
5359 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
5360 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
5361 | fixed_mode = drm_mode_duplicate(dev, scan); | |
4f9db5b5 | 5362 | downclock_mode = intel_dp_drrs_init( |
4f9db5b5 | 5363 | intel_connector, fixed_mode); |
ed92f0b2 PZ |
5364 | break; |
5365 | } | |
5366 | } | |
5367 | ||
5368 | /* fallback to VBT if available for eDP */ | |
5369 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
5370 | fixed_mode = drm_mode_duplicate(dev, | |
5371 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
df457245 | 5372 | if (fixed_mode) { |
ed92f0b2 | 5373 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
df457245 VS |
5374 | connector->display_info.width_mm = fixed_mode->width_mm; |
5375 | connector->display_info.height_mm = fixed_mode->height_mm; | |
5376 | } | |
ed92f0b2 | 5377 | } |
060c8778 | 5378 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 5379 | |
666a4537 | 5380 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
01527b31 CT |
5381 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
5382 | register_reboot_notifier(&intel_dp->edp_notifier); | |
6517d273 VS |
5383 | |
5384 | /* | |
5385 | * Figure out the current pipe for the initial backlight setup. | |
5386 | * If the current pipe isn't valid, try the PPS pipe, and if that | |
5387 | * fails just assume pipe A. | |
5388 | */ | |
5389 | if (IS_CHERRYVIEW(dev)) | |
5390 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); | |
5391 | else | |
5392 | pipe = PORT_TO_PIPE(intel_dp->DP); | |
5393 | ||
5394 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5395 | pipe = intel_dp->pps_pipe; | |
5396 | ||
5397 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5398 | pipe = PIPE_A; | |
5399 | ||
5400 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", | |
5401 | pipe_name(pipe)); | |
01527b31 CT |
5402 | } |
5403 | ||
4f9db5b5 | 5404 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5507faeb | 5405 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
6517d273 | 5406 | intel_panel_setup_backlight(connector, pipe); |
ed92f0b2 PZ |
5407 | |
5408 | return true; | |
5409 | } | |
5410 | ||
16c25533 | 5411 | bool |
f0fec3f2 PZ |
5412 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5413 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 5414 | { |
f0fec3f2 PZ |
5415 | struct drm_connector *connector = &intel_connector->base; |
5416 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
5417 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
5418 | struct drm_device *dev = intel_encoder->base.dev; | |
a4fc5ed6 | 5419 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 5420 | enum port port = intel_dig_port->port; |
a121f4e5 | 5421 | int type, ret; |
a4fc5ed6 | 5422 | |
ccb1a831 VS |
5423 | if (WARN(intel_dig_port->max_lanes < 1, |
5424 | "Not enough lanes (%d) for DP on port %c\n", | |
5425 | intel_dig_port->max_lanes, port_name(port))) | |
5426 | return false; | |
5427 | ||
a4a5d2f8 VS |
5428 | intel_dp->pps_pipe = INVALID_PIPE; |
5429 | ||
ec5b01dd | 5430 | /* intel_dp vfuncs */ |
b6b5e383 DL |
5431 | if (INTEL_INFO(dev)->gen >= 9) |
5432 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; | |
ec5b01dd DL |
5433 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
5434 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; | |
5435 | else if (HAS_PCH_SPLIT(dev)) | |
5436 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; | |
5437 | else | |
6ffb1be7 | 5438 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; |
ec5b01dd | 5439 | |
b9ca5fad DL |
5440 | if (INTEL_INFO(dev)->gen >= 9) |
5441 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; | |
5442 | else | |
6ffb1be7 | 5443 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; |
153b1100 | 5444 | |
ad64217b ACO |
5445 | if (HAS_DDI(dev)) |
5446 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; | |
5447 | ||
0767935e DV |
5448 | /* Preserve the current hw state. */ |
5449 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 5450 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 5451 | |
3b32a35b | 5452 | if (intel_dp_is_edp(dev, port)) |
b329530c | 5453 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
5454 | else |
5455 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 5456 | |
f7d24902 ID |
5457 | /* |
5458 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
5459 | * for DP the encoder type can be set by the caller to | |
5460 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
5461 | */ | |
5462 | if (type == DRM_MODE_CONNECTOR_eDP) | |
5463 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
5464 | ||
c17ed5b5 | 5465 | /* eDP only on port B and/or C on vlv/chv */ |
666a4537 WB |
5466 | if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
5467 | is_edp(intel_dp) && port != PORT_B && port != PORT_C)) | |
c17ed5b5 VS |
5468 | return false; |
5469 | ||
e7281eab ID |
5470 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
5471 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
5472 | port_name(port)); | |
5473 | ||
b329530c | 5474 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
5475 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
5476 | ||
a4fc5ed6 KP |
5477 | connector->interlace_allowed = true; |
5478 | connector->doublescan_allowed = 0; | |
5479 | ||
f0fec3f2 | 5480 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 5481 | edp_panel_vdd_work); |
a4fc5ed6 | 5482 | |
df0e9248 | 5483 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
34ea3d38 | 5484 | drm_connector_register(connector); |
a4fc5ed6 | 5485 | |
affa9354 | 5486 | if (HAS_DDI(dev)) |
bcbc889b PZ |
5487 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
5488 | else | |
5489 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
5490 | ||
0b99836f | 5491 | /* Set up the hotplug pin. */ |
ab9d7c30 PZ |
5492 | switch (port) { |
5493 | case PORT_A: | |
1d843f9d | 5494 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
5495 | break; |
5496 | case PORT_B: | |
1d843f9d | 5497 | intel_encoder->hpd_pin = HPD_PORT_B; |
e87a005d | 5498 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
cf1d5883 | 5499 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
5500 | break; |
5501 | case PORT_C: | |
1d843f9d | 5502 | intel_encoder->hpd_pin = HPD_PORT_C; |
ab9d7c30 PZ |
5503 | break; |
5504 | case PORT_D: | |
1d843f9d | 5505 | intel_encoder->hpd_pin = HPD_PORT_D; |
ab9d7c30 | 5506 | break; |
26951caf XZ |
5507 | case PORT_E: |
5508 | intel_encoder->hpd_pin = HPD_PORT_E; | |
5509 | break; | |
ab9d7c30 | 5510 | default: |
ad1c0b19 | 5511 | BUG(); |
5eb08b69 ZW |
5512 | } |
5513 | ||
dada1a9f | 5514 | if (is_edp(intel_dp)) { |
773538e8 | 5515 | pps_lock(intel_dp); |
1e74a324 | 5516 | intel_dp_init_panel_power_timestamps(intel_dp); |
666a4537 | 5517 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
a4a5d2f8 | 5518 | vlv_initial_power_sequencer_setup(intel_dp); |
1e74a324 | 5519 | else |
36b5f425 | 5520 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
773538e8 | 5521 | pps_unlock(intel_dp); |
dada1a9f | 5522 | } |
0095e6dc | 5523 | |
a121f4e5 VS |
5524 | ret = intel_dp_aux_init(intel_dp, intel_connector); |
5525 | if (ret) | |
5526 | goto fail; | |
c1f05264 | 5527 | |
0e32b39c | 5528 | /* init MST on ports that can support it */ |
0c9b3715 JN |
5529 | if (HAS_DP_MST(dev) && |
5530 | (port == PORT_B || port == PORT_C || port == PORT_D)) | |
5531 | intel_dp_mst_encoder_init(intel_dig_port, | |
5532 | intel_connector->base.base.id); | |
0e32b39c | 5533 | |
36b5f425 | 5534 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
a121f4e5 VS |
5535 | intel_dp_aux_fini(intel_dp); |
5536 | intel_dp_mst_encoder_cleanup(intel_dig_port); | |
5537 | goto fail; | |
b2f246a8 | 5538 | } |
32f9d658 | 5539 | |
f684960e CW |
5540 | intel_dp_add_properties(intel_dp, connector); |
5541 | ||
a4fc5ed6 KP |
5542 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
5543 | * 0xd. Failure to do so will result in spurious interrupts being | |
5544 | * generated on the port when a cable is not attached. | |
5545 | */ | |
5546 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
5547 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
5548 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
5549 | } | |
16c25533 | 5550 | |
aa7471d2 JN |
5551 | i915_debugfs_connector_add(connector); |
5552 | ||
16c25533 | 5553 | return true; |
a121f4e5 VS |
5554 | |
5555 | fail: | |
5556 | if (is_edp(intel_dp)) { | |
5557 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
5558 | /* | |
5559 | * vdd might still be enabled do to the delayed vdd off. | |
5560 | * Make sure vdd is actually turned off here. | |
5561 | */ | |
5562 | pps_lock(intel_dp); | |
5563 | edp_panel_vdd_off_sync(intel_dp); | |
5564 | pps_unlock(intel_dp); | |
5565 | } | |
5566 | drm_connector_unregister(connector); | |
5567 | drm_connector_cleanup(connector); | |
5568 | ||
5569 | return false; | |
a4fc5ed6 | 5570 | } |
f0fec3f2 | 5571 | |
457c52d8 CW |
5572 | bool intel_dp_init(struct drm_device *dev, |
5573 | i915_reg_t output_reg, | |
5574 | enum port port) | |
f0fec3f2 | 5575 | { |
13cf5504 | 5576 | struct drm_i915_private *dev_priv = dev->dev_private; |
f0fec3f2 PZ |
5577 | struct intel_digital_port *intel_dig_port; |
5578 | struct intel_encoder *intel_encoder; | |
5579 | struct drm_encoder *encoder; | |
5580 | struct intel_connector *intel_connector; | |
5581 | ||
b14c5679 | 5582 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 | 5583 | if (!intel_dig_port) |
457c52d8 | 5584 | return false; |
f0fec3f2 | 5585 | |
08d9bc92 | 5586 | intel_connector = intel_connector_alloc(); |
11aee0f6 SM |
5587 | if (!intel_connector) |
5588 | goto err_connector_alloc; | |
f0fec3f2 PZ |
5589 | |
5590 | intel_encoder = &intel_dig_port->base; | |
5591 | encoder = &intel_encoder->base; | |
5592 | ||
893da0c9 | 5593 | if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
580d8ed5 | 5594 | DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port))) |
893da0c9 | 5595 | goto err_encoder_init; |
f0fec3f2 | 5596 | |
5bfe2ac0 | 5597 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 5598 | intel_encoder->disable = intel_disable_dp; |
00c09d70 | 5599 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 5600 | intel_encoder->get_config = intel_dp_get_config; |
07f9cd0b | 5601 | intel_encoder->suspend = intel_dp_encoder_suspend; |
e4a1d846 | 5602 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 5603 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
e4a1d846 CML |
5604 | intel_encoder->pre_enable = chv_pre_enable_dp; |
5605 | intel_encoder->enable = vlv_enable_dp; | |
580d3811 | 5606 | intel_encoder->post_disable = chv_post_disable_dp; |
d6db995f | 5607 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
e4a1d846 | 5608 | } else if (IS_VALLEYVIEW(dev)) { |
ecff4f3b | 5609 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
5610 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
5611 | intel_encoder->enable = vlv_enable_dp; | |
49277c31 | 5612 | intel_encoder->post_disable = vlv_post_disable_dp; |
ab1f90f9 | 5613 | } else { |
ecff4f3b JN |
5614 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
5615 | intel_encoder->enable = g4x_enable_dp; | |
08aff3fe VS |
5616 | if (INTEL_INFO(dev)->gen >= 5) |
5617 | intel_encoder->post_disable = ilk_post_disable_dp; | |
ab1f90f9 | 5618 | } |
f0fec3f2 | 5619 | |
174edf1f | 5620 | intel_dig_port->port = port; |
f0fec3f2 | 5621 | intel_dig_port->dp.output_reg = output_reg; |
ccb1a831 | 5622 | intel_dig_port->max_lanes = 4; |
f0fec3f2 | 5623 | |
00c09d70 | 5624 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
882ec384 VS |
5625 | if (IS_CHERRYVIEW(dev)) { |
5626 | if (port == PORT_D) | |
5627 | intel_encoder->crtc_mask = 1 << 2; | |
5628 | else | |
5629 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
5630 | } else { | |
5631 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
5632 | } | |
bc079e8b | 5633 | intel_encoder->cloneable = 0; |
f0fec3f2 | 5634 | |
13cf5504 | 5635 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
5fcece80 | 5636 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
13cf5504 | 5637 | |
11aee0f6 SM |
5638 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
5639 | goto err_init_connector; | |
5640 | ||
457c52d8 | 5641 | return true; |
11aee0f6 SM |
5642 | |
5643 | err_init_connector: | |
5644 | drm_encoder_cleanup(encoder); | |
893da0c9 | 5645 | err_encoder_init: |
11aee0f6 SM |
5646 | kfree(intel_connector); |
5647 | err_connector_alloc: | |
5648 | kfree(intel_dig_port); | |
457c52d8 | 5649 | return false; |
f0fec3f2 | 5650 | } |
0e32b39c DA |
5651 | |
5652 | void intel_dp_mst_suspend(struct drm_device *dev) | |
5653 | { | |
5654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5655 | int i; | |
5656 | ||
5657 | /* disable MST */ | |
5658 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 5659 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
0e32b39c DA |
5660 | if (!intel_dig_port) |
5661 | continue; | |
5662 | ||
5663 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
5664 | if (!intel_dig_port->dp.can_mst) | |
5665 | continue; | |
5666 | if (intel_dig_port->dp.is_mst) | |
5667 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); | |
5668 | } | |
5669 | } | |
5670 | } | |
5671 | ||
5672 | void intel_dp_mst_resume(struct drm_device *dev) | |
5673 | { | |
5674 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5675 | int i; | |
5676 | ||
5677 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 5678 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
0e32b39c DA |
5679 | if (!intel_dig_port) |
5680 | continue; | |
5681 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
5682 | int ret; | |
5683 | ||
5684 | if (!intel_dig_port->dp.can_mst) | |
5685 | continue; | |
5686 | ||
5687 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); | |
5688 | if (ret != 0) { | |
5689 | intel_dp_check_mst_status(&intel_dig_port->dp); | |
5690 | } | |
5691 | } | |
5692 | } | |
5693 | } |