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drm/i915: select the correct pipe when using TRANSCODER_EDP
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
50 return intel_dp->base.type == INTEL_OUTPUT_EDP;
51}
52
53/**
54 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
55 * @intel_dp: DP struct
56 *
57 * Returns true if the given DP struct corresponds to a PCH DP port attached
58 * to an eDP panel, false otherwise. Helpful for determining whether we
59 * may need FDI resources for a given DP output or not.
60 */
61static bool is_pch_edp(struct intel_dp *intel_dp)
62{
63 return intel_dp->is_pch_edp;
64}
65
1c95822a
AJ		 66/**
67 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
68 * @intel_dp: DP struct
69 *
70 * Returns true if the given DP struct corresponds to a CPU eDP port.
71 */
72static bool is_cpu_edp(struct intel_dp *intel_dp)
73{
74 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
75}
76
df0e9248
CW		 77static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
78{
79 return container_of(intel_attached_encoder(connector),
80 struct intel_dp, base);
81}
82
814948ad
JB		 83/**
84 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
85 * @encoder: DRM encoder
86 *
87 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
88 * by intel_display.c.
89 */
90bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
91{
92 struct intel_dp *intel_dp;
93
94 if (!encoder)
95 return false;
96
97 intel_dp = enc_to_intel_dp(encoder);
98
99 return is_pch_edp(intel_dp);
100}
101
ea5b213a 102static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 103
32f9d658 104void
0206e353 105intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 106 int *lane_num, int *link_bw)
32f9d658 107{
ea5b213a 108 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 109
ea5b213a 110 *lane_num = intel_dp->lane_count;
3b5c662e 111 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
32f9d658
ZW		 112}
113
94bf2ced
DV		 114int
115intel_edp_target_clock(struct intel_encoder *intel_encoder,
116 struct drm_display_mode *mode)
117{
118 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
dd06f90e 119 struct intel_connector *intel_connector = intel_dp->attached_connector;
94bf2ced 120
dd06f90e
JN		 121 if (intel_connector->panel.fixed_mode)
122 return intel_connector->panel.fixed_mode->clock;
94bf2ced
DV		 123 else
124 return mode->clock;
125}
126
a4fc5ed6 127static int
ea5b213a 128intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 129{
7183dc29 130 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 131
132 switch (max_link_bw) {
133 case DP_LINK_BW_1_62:
134 case DP_LINK_BW_2_7:
135 break;
136 default:
137 max_link_bw = DP_LINK_BW_1_62;
138 break;
139 }
140 return max_link_bw;
141}
142
143static int
144intel_dp_link_clock(uint8_t link_bw)
145{
146 if (link_bw == DP_LINK_BW_2_7)
147 return 270000;
148 else
149 return 162000;
150}
151
cd9dde44
AJ		 152/*
153 * The units on the numbers in the next two are... bizarre. Examples will
154 * make it clearer; this one parallels an example in the eDP spec.
155 *
156 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
157 *
158 * 270000 * 1 * 8 / 10 == 216000
159 *
160 * The actual data capacity of that configuration is 2.16Gbit/s, so the
161 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
162 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
163 * 119000. At 18bpp that's 2142000 kilobits per second.
164 *
165 * Thus the strange-looking division by 10 in intel_dp_link_required, to
166 * get the result in decakilobits instead of kilobits.
167 */
168
a4fc5ed6 169static int
c898261c 170intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 171{
cd9dde44 172 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 173}
174
fe27d53e
DA		 175static int
176intel_dp_max_data_rate(int max_link_clock, int max_lanes)
177{
178 return (max_link_clock * max_lanes * 8) / 10;
179}
180
c4867936
DV		 181static bool
182intel_dp_adjust_dithering(struct intel_dp *intel_dp,
183 struct drm_display_mode *mode,
cb1793ce 184 bool adjust_mode)
c4867936
DV		 185{
186 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
397fe157 187 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
c4867936
DV		 188 int max_rate, mode_rate;
189
190 mode_rate = intel_dp_link_required(mode->clock, 24);
191 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
192
193 if (mode_rate > max_rate) {
194 mode_rate = intel_dp_link_required(mode->clock, 18);
195 if (mode_rate > max_rate)
196 return false;
197
cb1793ce
DV		 198 if (adjust_mode)
199 mode->private_flags
c4867936
DV		 200 |= INTEL_MODE_DP_FORCE_6BPC;
201
202 return true;
203 }
204
205 return true;
206}
207
a4fc5ed6
KP		 208static int
209intel_dp_mode_valid(struct drm_connector *connector,
210 struct drm_display_mode *mode)
211{
df0e9248 212 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 213 struct intel_connector *intel_connector = to_intel_connector(connector);
214 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
a4fc5ed6 215
dd06f90e
JN		 216 if (is_edp(intel_dp) && fixed_mode) {
217 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 218 return MODE_PANEL;
219
dd06f90e 220 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43
ZY		 221 return MODE_PANEL;
222 }
223
cb1793ce 224 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 225 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 226
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
229
0af78a2b
DV		 230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
232
a4fc5ed6
KP		 233 return MODE_OK;
234}
235
236static uint32_t
237pack_aux(uint8_t *src, int src_bytes)
238{
239 int i;
240 uint32_t v = 0;
241
242 if (src_bytes > 4)
243 src_bytes = 4;
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
246 return v;
247}
248
249static void
250unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
251{
252 int i;
253 if (dst_bytes > 4)
254 dst_bytes = 4;
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
257}
258
fb0f8fbf
KP		 259/* hrawclock is 1/4 the FSB frequency */
260static int
261intel_hrawclk(struct drm_device *dev)
262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 uint32_t clkcfg;
265
9473c8f4
VP		 266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
268 return 200;
269
fb0f8fbf
KP		 270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
272 case CLKCFG_FSB_400:
273 return 100;
274 case CLKCFG_FSB_533:
275 return 133;
276 case CLKCFG_FSB_667:
277 return 166;
278 case CLKCFG_FSB_800:
279 return 200;
280 case CLKCFG_FSB_1067:
281 return 266;
282 case CLKCFG_FSB_1333:
283 return 333;
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
287 return 400;
288 default:
289 return 133;
290 }
291}
292
ebf33b18
KP		 293static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
294{
295 struct drm_device *dev = intel_dp->base.base.dev;
296 struct drm_i915_private *dev_priv = dev->dev_private;
297
298 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
299}
300
301static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
302{
303 struct drm_device *dev = intel_dp->base.base.dev;
304 struct drm_i915_private *dev_priv = dev->dev_private;
305
306 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
307}
308
9b984dae
KP		 309static void
310intel_dp_check_edp(struct intel_dp *intel_dp)
311{
312 struct drm_device *dev = intel_dp->base.base.dev;
313 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 314
9b984dae
KP		 315 if (!is_edp(intel_dp))
316 return;
ebf33b18 317 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 318 WARN(1, "eDP powered off while attempting aux channel communication.\n");
319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 320 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 321 I915_READ(PCH_PP_CONTROL));
322 }
323}
324
a4fc5ed6 325static int
ea5b213a 326intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 327 uint8_t *send, int send_bytes,
328 uint8_t *recv, int recv_size)
329{
ea5b213a 330 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 331 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 332 struct drm_i915_private *dev_priv = dev->dev_private;
333 uint32_t ch_ctl = output_reg + 0x10;
334 uint32_t ch_data = ch_ctl + 4;
335 int i;
336 int recv_bytes;
a4fc5ed6 337 uint32_t status;
fb0f8fbf 338 uint32_t aux_clock_divider;
6b4e0a93 339 int try, precharge;
a4fc5ed6 340
750eb99e
PZ		 341 if (IS_HASWELL(dev)) {
342 switch (intel_dp->port) {
343 case PORT_A:
344 ch_ctl = DPA_AUX_CH_CTL;
345 ch_data = DPA_AUX_CH_DATA1;
346 break;
347 case PORT_B:
348 ch_ctl = PCH_DPB_AUX_CH_CTL;
349 ch_data = PCH_DPB_AUX_CH_DATA1;
350 break;
351 case PORT_C:
352 ch_ctl = PCH_DPC_AUX_CH_CTL;
353 ch_data = PCH_DPC_AUX_CH_DATA1;
354 break;
355 case PORT_D:
356 ch_ctl = PCH_DPD_AUX_CH_CTL;
357 ch_data = PCH_DPD_AUX_CH_DATA1;
358 break;
359 default:
360 BUG();
361 }
362 }
363
9b984dae 364 intel_dp_check_edp(intel_dp);
a4fc5ed6 365 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 366 * and would like to run at 2MHz. So, take the
367 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 368 *
369 * Note that PCH attached eDP panels should use a 125MHz input
370 * clock divider.
a4fc5ed6 371 */
1c95822a 372 if (is_cpu_edp(intel_dp)) {
9473c8f4
VP		 373 if (IS_VALLEYVIEW(dev))
374 aux_clock_divider = 100;
375 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 376 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 377 else
378 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
379 } else if (HAS_PCH_SPLIT(dev))
6b3ec1c9 380 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
5eb08b69
ZW		 381 else
382 aux_clock_divider = intel_hrawclk(dev) / 2;
383
6b4e0a93
DV		 384 if (IS_GEN6(dev))
385 precharge = 3;
386 else
387 precharge = 5;
388
11bee43e
JB		 389 /* Try to wait for any previous AUX channel activity */
390 for (try = 0; try < 3; try++) {
391 status = I915_READ(ch_ctl);
392 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
393 break;
394 msleep(1);
395 }
396
397 if (try == 3) {
398 WARN(1, "dp_aux_ch not started status 0x%08x\n",
399 I915_READ(ch_ctl));
4f7f7b7e
CW		 400 return -EBUSY;
401 }
402
fb0f8fbf
KP		 403 /* Must try at least 3 times according to DP spec */
404 for (try = 0; try < 5; try++) {
405 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 406 for (i = 0; i < send_bytes; i += 4)
407 I915_WRITE(ch_data + i,
408 pack_aux(send + i, send_bytes - i));
0206e353 409
fb0f8fbf 410 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 411 I915_WRITE(ch_ctl,
412 DP_AUX_CH_CTL_SEND_BUSY |
413 DP_AUX_CH_CTL_TIME_OUT_400us |
414 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
415 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
416 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
417 DP_AUX_CH_CTL_DONE |
418 DP_AUX_CH_CTL_TIME_OUT_ERROR |
419 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 420 for (;;) {
fb0f8fbf
KP		 421 status = I915_READ(ch_ctl);
422 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
423 break;
4f7f7b7e 424 udelay(100);
fb0f8fbf 425 }
0206e353 426
fb0f8fbf 427 /* Clear done status and any errors */
4f7f7b7e
CW		 428 I915_WRITE(ch_ctl,
429 status |
430 DP_AUX_CH_CTL_DONE |
431 DP_AUX_CH_CTL_TIME_OUT_ERROR |
432 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 433
434 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
435 DP_AUX_CH_CTL_RECEIVE_ERROR))
436 continue;
4f7f7b7e 437 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 438 break;
439 }
440
a4fc5ed6 441 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 442 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 443 return -EBUSY;
a4fc5ed6
KP		 444 }
445
446 /* Check for timeout or receive error.
447 * Timeouts occur when the sink is not connected
448 */
a5b3da54 449 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 450 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 451 return -EIO;
452 }
1ae8c0a5
KP		 453
454 /* Timeouts occur when the device isn't connected, so they're
455 * "normal" -- don't fill the kernel log with these */
a5b3da54 456 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 457 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 458 return -ETIMEDOUT;
a4fc5ed6
KP		 459 }
460
461 /* Unload any bytes sent back from the other side */
462 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
463 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 464 if (recv_bytes > recv_size)
465 recv_bytes = recv_size;
0206e353 466
4f7f7b7e
CW		 467 for (i = 0; i < recv_bytes; i += 4)
468 unpack_aux(I915_READ(ch_data + i),
469 recv + i, recv_bytes - i);
a4fc5ed6
KP		 470
471 return recv_bytes;
472}
473
474/* Write data to the aux channel in native mode */
475static int
ea5b213a 476intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 477 uint16_t address, uint8_t *send, int send_bytes)
478{
479 int ret;
480 uint8_t msg[20];
481 int msg_bytes;
482 uint8_t ack;
483
9b984dae 484 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 485 if (send_bytes > 16)
486 return -1;
487 msg[0] = AUX_NATIVE_WRITE << 4;
488 msg[1] = address >> 8;
eebc863e 489 msg[2] = address & 0xff;
a4fc5ed6
KP		 490 msg[3] = send_bytes - 1;
491 memcpy(&msg[4], send, send_bytes);
492 msg_bytes = send_bytes + 4;
493 for (;;) {
ea5b213a 494 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 495 if (ret < 0)
496 return ret;
497 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
498 break;
499 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
500 udelay(100);
501 else
a5b3da54 502 return -EIO;
a4fc5ed6
KP		 503 }
504 return send_bytes;
505}
506
507/* Write a single byte to the aux channel in native mode */
508static int
ea5b213a 509intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 510 uint16_t address, uint8_t byte)
511{
ea5b213a 512 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 513}
514
515/* read bytes from a native aux channel */
516static int
ea5b213a 517intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 518 uint16_t address, uint8_t *recv, int recv_bytes)
519{
520 uint8_t msg[4];
521 int msg_bytes;
522 uint8_t reply[20];
523 int reply_bytes;
524 uint8_t ack;
525 int ret;
526
9b984dae 527 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 528 msg[0] = AUX_NATIVE_READ << 4;
529 msg[1] = address >> 8;
530 msg[2] = address & 0xff;
531 msg[3] = recv_bytes - 1;
532
533 msg_bytes = 4;
534 reply_bytes = recv_bytes + 1;
535
536 for (;;) {
ea5b213a 537 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 538 reply, reply_bytes);
a5b3da54
KP		 539 if (ret == 0)
540 return -EPROTO;
541 if (ret < 0)
a4fc5ed6
KP		 542 return ret;
543 ack = reply[0];
544 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
545 memcpy(recv, reply + 1, ret - 1);
546 return ret - 1;
547 }
548 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
549 udelay(100);
550 else
a5b3da54 551 return -EIO;
a4fc5ed6
KP		 552 }
553}
554
555static int
ab2c0672
DA		 556intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
557 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 558{
ab2c0672 559 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 560 struct intel_dp *intel_dp = container_of(adapter,
561 struct intel_dp,
562 adapter);
ab2c0672
DA		 563 uint16_t address = algo_data->address;
564 uint8_t msg[5];
565 uint8_t reply[2];
8316f337 566 unsigned retry;
ab2c0672
DA		 567 int msg_bytes;
568 int reply_bytes;
569 int ret;
570
9b984dae 571 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 572 /* Set up the command byte */
573 if (mode & MODE_I2C_READ)
574 msg[0] = AUX_I2C_READ << 4;
575 else
576 msg[0] = AUX_I2C_WRITE << 4;
577
578 if (!(mode & MODE_I2C_STOP))
579 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 580
ab2c0672
DA		 581 msg[1] = address >> 8;
582 msg[2] = address;
583
584 switch (mode) {
585 case MODE_I2C_WRITE:
586 msg[3] = 0;
587 msg[4] = write_byte;
588 msg_bytes = 5;
589 reply_bytes = 1;
590 break;
591 case MODE_I2C_READ:
592 msg[3] = 0;
593 msg_bytes = 4;
594 reply_bytes = 2;
595 break;
596 default:
597 msg_bytes = 3;
598 reply_bytes = 1;
599 break;
600 }
601
8316f337
DF		 602 for (retry = 0; retry < 5; retry++) {
603 ret = intel_dp_aux_ch(intel_dp,
604 msg, msg_bytes,
605 reply, reply_bytes);
ab2c0672 606 if (ret < 0) {
3ff99164 607 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 608 return ret;
609 }
8316f337
DF		 610
611 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
612 case AUX_NATIVE_REPLY_ACK:
613 /* I2C-over-AUX Reply field is only valid
614 * when paired with AUX ACK.
615 */
616 break;
617 case AUX_NATIVE_REPLY_NACK:
618 DRM_DEBUG_KMS("aux_ch native nack\n");
619 return -EREMOTEIO;
620 case AUX_NATIVE_REPLY_DEFER:
621 udelay(100);
622 continue;
623 default:
624 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
625 reply[0]);
626 return -EREMOTEIO;
627 }
628
ab2c0672
DA		 629 switch (reply[0] & AUX_I2C_REPLY_MASK) {
630 case AUX_I2C_REPLY_ACK:
631 if (mode == MODE_I2C_READ) {
632 *read_byte = reply[1];
633 }
634 return reply_bytes - 1;
635 case AUX_I2C_REPLY_NACK:
8316f337 636 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 637 return -EREMOTEIO;
638 case AUX_I2C_REPLY_DEFER:
8316f337 639 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 640 udelay(100);
641 break;
642 default:
8316f337 643 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 644 return -EREMOTEIO;
645 }
646 }
8316f337
DF		 647
648 DRM_ERROR("too many retries, giving up\n");
649 return -EREMOTEIO;
a4fc5ed6
KP		 650}
651
0b5c541b 652static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
bd943159 653static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0b5c541b 654
a4fc5ed6 655static int
ea5b213a 656intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 657 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 658{
0b5c541b
KP		 659 int ret;
660
d54e9d28 661 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 662 intel_dp->algo.running = false;
663 intel_dp->algo.address = 0;
664 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
665
0206e353 666 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 667 intel_dp->adapter.owner = THIS_MODULE;
668 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 669 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 670 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
671 intel_dp->adapter.algo_data = &intel_dp->algo;
672 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
673
0b5c541b
KP		 674 ironlake_edp_panel_vdd_on(intel_dp);
675 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 676 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 677 return ret;
a4fc5ed6
KP		 678}
679
680static bool
e811f5ae
LP		 681intel_dp_mode_fixup(struct drm_encoder *encoder,
682 const struct drm_display_mode *mode,
a4fc5ed6
KP		 683 struct drm_display_mode *adjusted_mode)
684{
0d3a1bee 685 struct drm_device *dev = encoder->dev;
ea5b213a 686 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
dd06f90e 687 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 688 int lane_count, clock;
397fe157 689 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 690 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 691 int bpp, mode_rate;
a4fc5ed6
KP		 692 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
693
dd06f90e
JN		 694 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
695 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
696 adjusted_mode);
1d8e1c75
CW		 697 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
698 mode, adjusted_mode);
0d3a1bee
ZY		 699 }
700
cb1793ce 701 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 702 return false;
703
083f9560
DV		 704 DRM_DEBUG_KMS("DP link computation with max lane count %i "
705 "max bw %02x pixel clock %iKHz\n",
71244653 706 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 707
cb1793ce 708 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 709 return false;
710
711 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 712 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 713
2514bc51
JB		 714 for (clock = 0; clock <= max_clock; clock++) {
715 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
fe27d53e 716 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 717
083f9560 718 if (mode_rate <= link_avail) {
ea5b213a
CW		 719 intel_dp->link_bw = bws[clock];
720 intel_dp->lane_count = lane_count;
721 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 722 DRM_DEBUG_KMS("DP link bw %02x lane "
723 "count %d clock %d bpp %d\n",
ea5b213a 724 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 725 adjusted_mode->clock, bpp);
726 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
727 mode_rate, link_avail);
a4fc5ed6
KP		 728 return true;
729 }
730 }
731 }
fe27d53e 732
a4fc5ed6
KP		 733 return false;
734}
735
736struct intel_dp_m_n {
737 uint32_t tu;
738 uint32_t gmch_m;
739 uint32_t gmch_n;
740 uint32_t link_m;
741 uint32_t link_n;
742};
743
744static void
745intel_reduce_ratio(uint32_t *num, uint32_t *den)
746{
747 while (*num > 0xffffff || *den > 0xffffff) {
748 *num >>= 1;
749 *den >>= 1;
750 }
751}
752
753static void
36e83a18 754intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 755 int nlanes,
756 int pixel_clock,
757 int link_clock,
758 struct intel_dp_m_n *m_n)
759{
760 m_n->tu = 64;
36e83a18 761 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 762 m_n->gmch_n = link_clock * nlanes;
763 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
764 m_n->link_m = pixel_clock;
765 m_n->link_n = link_clock;
766 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
767}
768
769void
770intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
771 struct drm_display_mode *adjusted_mode)
772{
773 struct drm_device *dev = crtc->dev;
6c2b7c12 774 struct intel_encoder *encoder;
a4fc5ed6
KP		 775 struct drm_i915_private *dev_priv = dev->dev_private;
776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 777 int lane_count = 4;
a4fc5ed6 778 struct intel_dp_m_n m_n;
9db4a9c7 779 int pipe = intel_crtc->pipe;
afe2fcf5 780 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
a4fc5ed6
KP		 781
782 /*
21d40d37 783 * Find the lane count in the intel_encoder private
a4fc5ed6 784 */
6c2b7c12
DV		 785 for_each_encoder_on_crtc(dev, crtc, encoder) {
786 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 787
9a10f401
KP		 788 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
789 intel_dp->base.type == INTEL_OUTPUT_EDP)
790 {
ea5b213a 791 lane_count = intel_dp->lane_count;
51190667 792 break;
a4fc5ed6
KP		 793 }
794 }
795
796 /*
797 * Compute the GMCH and Link ratios. The '3' here is
798 * the number of bytes_per_pixel post-LUT, which we always
799 * set up for 8-bits of R/G/B, or 3 bytes total.
800 */
858fa035 801 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 802 mode->clock, adjusted_mode->clock, &m_n);
803
1eb8dfec 804 if (IS_HASWELL(dev)) {
afe2fcf5
PZ		 805 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
806 TU_SIZE(m_n.tu) | m_n.gmch_m);
807 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
808 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
809 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
1eb8dfec 810 } else if (HAS_PCH_SPLIT(dev)) {
7346bfa0 811 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 812 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
813 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
814 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 815 } else if (IS_VALLEYVIEW(dev)) {
816 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
817 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
818 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
819 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 820 } else {
9db4a9c7 821 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
7346bfa0 822 TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 823 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
824 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
825 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 826 }
827}
828
247d89f6
PZ		 829void intel_dp_init_link_config(struct intel_dp *intel_dp)
830{
831 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
832 intel_dp->link_configuration[0] = intel_dp->link_bw;
833 intel_dp->link_configuration[1] = intel_dp->lane_count;
834 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
835 /*
836 * Check for DPCD version > 1.1 and enhanced framing support
837 */
838 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
839 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
840 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
841 }
842}
843
a4fc5ed6
KP		 844static void
845intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
846 struct drm_display_mode *adjusted_mode)
847{
e3421a18 848 struct drm_device *dev = encoder->dev;
417e822d 849 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 850 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 851 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
853
417e822d 854 /*
1a2eb460 855 * There are four kinds of DP registers:
417e822d
KP		 856 *
857 * IBX PCH
1a2eb460
KP		 858 * SNB CPU
859 * IVB CPU
417e822d
KP		 860 * CPT PCH
861 *
862 * IBX PCH and CPU are the same for almost everything,
863 * except that the CPU DP PLL is configured in this
864 * register
865 *
866 * CPT PCH is quite different, having many bits moved
867 * to the TRANS_DP_CTL register instead. That
868 * configuration happens (oddly) in ironlake_pch_enable
869 */
9c9e7927 870
417e822d
KP		 871 /* Preserve the BIOS-computed detected bit. This is
872 * supposed to be read-only.
873 */
874 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 875
417e822d 876 /* Handle DP bits in common between all three register formats */
417e822d 877 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 878
ea5b213a 879 switch (intel_dp->lane_count) {
a4fc5ed6 880 case 1:
ea5b213a 881 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 882 break;
883 case 2:
ea5b213a 884 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 885 break;
886 case 4:
ea5b213a 887 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 888 break;
889 }
e0dac65e
WF		 890 if (intel_dp->has_audio) {
891 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
892 pipe_name(intel_crtc->pipe));
ea5b213a 893 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 894 intel_write_eld(encoder, adjusted_mode);
895 }
247d89f6
PZ		 896
897 intel_dp_init_link_config(intel_dp);
a4fc5ed6 898
417e822d 899 /* Split out the IBX/CPU vs CPT settings */
32f9d658 900
19c03924 901 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 902 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
903 intel_dp->DP |= DP_SYNC_HS_HIGH;
904 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
905 intel_dp->DP |= DP_SYNC_VS_HIGH;
906 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
907
908 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
909 intel_dp->DP |= DP_ENHANCED_FRAMING;
910
911 intel_dp->DP |= intel_crtc->pipe << 29;
912
913 /* don't miss out required setting for eDP */
1a2eb460
KP		 914 if (adjusted_mode->clock < 200000)
915 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
916 else
917 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
918 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 919 intel_dp->DP |= intel_dp->color_range;
920
921 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
922 intel_dp->DP |= DP_SYNC_HS_HIGH;
923 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
924 intel_dp->DP |= DP_SYNC_VS_HIGH;
925 intel_dp->DP |= DP_LINK_TRAIN_OFF;
926
927 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
928 intel_dp->DP |= DP_ENHANCED_FRAMING;
929
930 if (intel_crtc->pipe == 1)
931 intel_dp->DP |= DP_PIPEB_SELECT;
932
933 if (is_cpu_edp(intel_dp)) {
934 /* don't miss out required setting for eDP */
417e822d
KP		 935 if (adjusted_mode->clock < 200000)
936 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
937 else
938 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
939 }
940 } else {
941 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 942 }
a4fc5ed6
KP		 943}
944
99ea7127
KP		 945#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
946#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
947
948#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
949#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
950
951#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
952#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
953
954static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
955 u32 mask,
956 u32 value)
bd943159 957{
99ea7127
KP		 958 struct drm_device *dev = intel_dp->base.base.dev;
959 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 960
99ea7127
KP		 961 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
962 mask, value,
963 I915_READ(PCH_PP_STATUS),
964 I915_READ(PCH_PP_CONTROL));
32ce697c 965
99ea7127
KP		 966 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
967 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
968 I915_READ(PCH_PP_STATUS),
969 I915_READ(PCH_PP_CONTROL));
32ce697c 970 }
99ea7127 971}
32ce697c 972
99ea7127
KP		 973static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
974{
975 DRM_DEBUG_KMS("Wait for panel power on\n");
976 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 977}
978
99ea7127
KP		 979static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
980{
981 DRM_DEBUG_KMS("Wait for panel power off time\n");
982 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
983}
984
985static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
986{
987 DRM_DEBUG_KMS("Wait for panel power cycle\n");
988 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
989}
990
991
832dd3c1
KP		 992/* Read the current pp_control value, unlocking the register if it
993 * is locked
994 */
995
996static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
997{
998 u32 control = I915_READ(PCH_PP_CONTROL);
999
1000 control &= ~PANEL_UNLOCK_MASK;
1001 control |= PANEL_UNLOCK_REGS;
1002 return control;
bd943159
KP		 1003}
1004
5d613501
JB		 1005static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1006{
1007 struct drm_device *dev = intel_dp->base.base.dev;
1008 struct drm_i915_private *dev_priv = dev->dev_private;
1009 u32 pp;
1010
97af61f5
KP		 1011 if (!is_edp(intel_dp))
1012 return;
f01eca2e 1013 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1014
bd943159
KP		 1015 WARN(intel_dp->want_panel_vdd,
1016 "eDP VDD already requested on\n");
1017
1018 intel_dp->want_panel_vdd = true;
99ea7127 1019
bd943159
KP		 1020 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1021 DRM_DEBUG_KMS("eDP VDD already on\n");
1022 return;
1023 }
1024
99ea7127
KP		 1025 if (!ironlake_edp_have_panel_power(intel_dp))
1026 ironlake_wait_panel_power_cycle(intel_dp);
1027
832dd3c1 1028 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1029 pp |= EDP_FORCE_VDD;
1030 I915_WRITE(PCH_PP_CONTROL, pp);
1031 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1032 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1033 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1034
1035 /*
1036 * If the panel wasn't on, delay before accessing aux channel
1037 */
1038 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1039 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1040 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1041 }
5d613501
JB		 1042}
1043
bd943159 1044static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1045{
1046 struct drm_device *dev = intel_dp->base.base.dev;
1047 struct drm_i915_private *dev_priv = dev->dev_private;
1048 u32 pp;
1049
bd943159 1050 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1051 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1052 pp &= ~EDP_FORCE_VDD;
1053 I915_WRITE(PCH_PP_CONTROL, pp);
1054 POSTING_READ(PCH_PP_CONTROL);
1055
1056 /* Make sure sequencer is idle before allowing subsequent activity */
1057 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1058 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1059
1060 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1061 }
1062}
5d613501 1063
bd943159
KP		 1064static void ironlake_panel_vdd_work(struct work_struct *__work)
1065{
1066 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1067 struct intel_dp, panel_vdd_work);
1068 struct drm_device *dev = intel_dp->base.base.dev;
1069
627f7675 1070 mutex_lock(&dev->mode_config.mutex);
bd943159 1071 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1072 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1073}
1074
1075static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1076{
97af61f5
KP		 1077 if (!is_edp(intel_dp))
1078 return;
5d613501 1079
bd943159
KP		 1080 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1081 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1082
bd943159
KP		 1083 intel_dp->want_panel_vdd = false;
1084
1085 if (sync) {
1086 ironlake_panel_vdd_off_sync(intel_dp);
1087 } else {
1088 /*
1089 * Queue the timer to fire a long
1090 * time from now (relative to the power down delay)
1091 * to keep the panel power up across a sequence of operations
1092 */
1093 schedule_delayed_work(&intel_dp->panel_vdd_work,
1094 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1095 }
5d613501
JB		 1096}
1097
86a3073e 1098static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1099{
01cb9ea6 1100 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1101 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1102 u32 pp;
9934c132 1103
97af61f5 1104 if (!is_edp(intel_dp))
bd943159 1105 return;
99ea7127
KP		 1106
1107 DRM_DEBUG_KMS("Turn eDP power on\n");
1108
1109 if (ironlake_edp_have_panel_power(intel_dp)) {
1110 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1111 return;
99ea7127 1112 }
9934c132 1113
99ea7127 1114 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1115
99ea7127 1116 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1117 if (IS_GEN5(dev)) {
1118 /* ILK workaround: disable reset around power sequence */
1119 pp &= ~PANEL_POWER_RESET;
1120 I915_WRITE(PCH_PP_CONTROL, pp);
1121 POSTING_READ(PCH_PP_CONTROL);
1122 }
37c6c9b0 1123
1c0ae80a 1124 pp |= POWER_TARGET_ON;
99ea7127
KP		 1125 if (!IS_GEN5(dev))
1126 pp |= PANEL_POWER_RESET;
1127
9934c132 1128 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1129 POSTING_READ(PCH_PP_CONTROL);
9934c132 1130
99ea7127 1131 ironlake_wait_panel_on(intel_dp);
9934c132 1132
05ce1a49
KP		 1133 if (IS_GEN5(dev)) {
1134 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1135 I915_WRITE(PCH_PP_CONTROL, pp);
1136 POSTING_READ(PCH_PP_CONTROL);
1137 }
9934c132
JB		 1138}
1139
99ea7127 1140static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1141{
99ea7127 1142 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1143 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1144 u32 pp;
9934c132 1145
97af61f5
KP		 1146 if (!is_edp(intel_dp))
1147 return;
37c6c9b0 1148
99ea7127 1149 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1150
6cb49835 1151 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1152
99ea7127 1153 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1154 /* We need to switch off panel power _and_ force vdd, for otherwise some
1155 * panels get very unhappy and cease to work. */
1156 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1157 I915_WRITE(PCH_PP_CONTROL, pp);
1158 POSTING_READ(PCH_PP_CONTROL);
9934c132 1159
35a38556
DV		 1160 intel_dp->want_panel_vdd = false;
1161
99ea7127 1162 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1163}
1164
86a3073e 1165static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1166{
f01eca2e 1167 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658 1168 struct drm_i915_private *dev_priv = dev->dev_private;
035aa3de 1169 int pipe = to_intel_crtc(intel_dp->base.base.crtc)->pipe;
32f9d658
ZW		 1170 u32 pp;
1171
f01eca2e
KP		 1172 if (!is_edp(intel_dp))
1173 return;
1174
28c97730 1175 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1176 /*
1177 * If we enable the backlight right away following a panel power
1178 * on, we may see slight flicker as the panel syncs with the eDP
1179 * link. So delay a bit to make sure the image is solid before
1180 * allowing it to appear.
1181 */
f01eca2e 1182 msleep(intel_dp->backlight_on_delay);
832dd3c1 1183 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1184 pp |= EDP_BLC_ENABLE;
1185 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1186 POSTING_READ(PCH_PP_CONTROL);
035aa3de
DV		 1187
1188 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1189}
1190
86a3073e 1191static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1192{
f01eca2e 1193 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1194 struct drm_i915_private *dev_priv = dev->dev_private;
1195 u32 pp;
1196
f01eca2e
KP		 1197 if (!is_edp(intel_dp))
1198 return;
1199
035aa3de
DV		 1200 intel_panel_disable_backlight(dev);
1201
28c97730 1202 DRM_DEBUG_KMS("\n");
832dd3c1 1203 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1204 pp &= ~EDP_BLC_ENABLE;
1205 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1206 POSTING_READ(PCH_PP_CONTROL);
1207 msleep(intel_dp->backlight_off_delay);
32f9d658 1208}
a4fc5ed6 1209
2bd2ad64 1210static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1211{
2bd2ad64
DV		 1212 struct drm_device *dev = intel_dp->base.base.dev;
1213 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1214 struct drm_i915_private *dev_priv = dev->dev_private;
1215 u32 dpa_ctl;
1216
2bd2ad64
DV		 1217 assert_pipe_disabled(dev_priv,
1218 to_intel_crtc(crtc)->pipe);
1219
d240f20f
JB		 1220 DRM_DEBUG_KMS("\n");
1221 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1222 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1223 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1224
1225 /* We don't adjust intel_dp->DP while tearing down the link, to
1226 * facilitate link retraining (e.g. after hotplug). Hence clear all
1227 * enable bits here to ensure that we don't enable too much. */
1228 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1229 intel_dp->DP |= DP_PLL_ENABLE;
1230 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1231 POSTING_READ(DP_A);
1232 udelay(200);
d240f20f
JB		 1233}
1234
2bd2ad64 1235static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1236{
2bd2ad64
DV		 1237 struct drm_device *dev = intel_dp->base.base.dev;
1238 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1239 struct drm_i915_private *dev_priv = dev->dev_private;
1240 u32 dpa_ctl;
1241
2bd2ad64
DV		 1242 assert_pipe_disabled(dev_priv,
1243 to_intel_crtc(crtc)->pipe);
1244
d240f20f 1245 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1246 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1247 "dp pll off, should be on\n");
1248 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1249
1250 /* We can't rely on the value tracked for the DP register in
1251 * intel_dp->DP because link_down must not change that (otherwise link
1252 * re-training will fail. */
298b0b39 1253 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1254 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1255 POSTING_READ(DP_A);
d240f20f
JB		 1256 udelay(200);
1257}
1258
c7ad3810 1259/* If the sink supports it, try to set the power state appropriately */
c19b0669 1260void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1261{
1262 int ret, i;
1263
1264 /* Should have a valid DPCD by this point */
1265 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1266 return;
1267
1268 if (mode != DRM_MODE_DPMS_ON) {
1269 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1270 DP_SET_POWER_D3);
1271 if (ret != 1)
1272 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1273 } else {
1274 /*
1275 * When turning on, we need to retry for 1ms to give the sink
1276 * time to wake up.
1277 */
1278 for (i = 0; i < 3; i++) {
1279 ret = intel_dp_aux_native_write_1(intel_dp,
1280 DP_SET_POWER,
1281 DP_SET_POWER_D0);
1282 if (ret == 1)
1283 break;
1284 msleep(1);
1285 }
1286 }
1287}
1288
19d8fe15
DV		 1289static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1290 enum pipe *pipe)
d240f20f 1291{
19d8fe15
DV		 1292 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1293 struct drm_device *dev = encoder->base.dev;
1294 struct drm_i915_private *dev_priv = dev->dev_private;
1295 u32 tmp = I915_READ(intel_dp->output_reg);
1296
1297 if (!(tmp & DP_PORT_EN))
1298 return false;
1299
1300 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1301 *pipe = PORT_TO_PIPE_CPT(tmp);
1302 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1303 *pipe = PORT_TO_PIPE(tmp);
1304 } else {
1305 u32 trans_sel;
1306 u32 trans_dp;
1307 int i;
1308
1309 switch (intel_dp->output_reg) {
1310 case PCH_DP_B:
1311 trans_sel = TRANS_DP_PORT_SEL_B;
1312 break;
1313 case PCH_DP_C:
1314 trans_sel = TRANS_DP_PORT_SEL_C;
1315 break;
1316 case PCH_DP_D:
1317 trans_sel = TRANS_DP_PORT_SEL_D;
1318 break;
1319 default:
1320 return true;
1321 }
1322
1323 for_each_pipe(i) {
1324 trans_dp = I915_READ(TRANS_DP_CTL(i));
1325 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1326 *pipe = i;
1327 return true;
1328 }
1329 }
1330 }
1331
1332 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
d240f20f 1333
19d8fe15
DV		 1334 return true;
1335}
1336
e8cb4558 1337static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1338{
e8cb4558 1339 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1340
1341 /* Make sure the panel is off before trying to change the mode. But also
1342 * ensure that we have vdd while we switch off the panel. */
1343 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1344 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1345 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1346 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1347
1348 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1349 if (!is_cpu_edp(intel_dp))
1350 intel_dp_link_down(intel_dp);
d240f20f
JB		 1351}
1352
2bd2ad64
DV		 1353static void intel_post_disable_dp(struct intel_encoder *encoder)
1354{
1355 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1356
3739850b
DV		 1357 if (is_cpu_edp(intel_dp)) {
1358 intel_dp_link_down(intel_dp);
2bd2ad64 1359 ironlake_edp_pll_off(intel_dp);
3739850b 1360 }
2bd2ad64
DV		 1361}
1362
e8cb4558 1363static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1364{
e8cb4558
DV		 1365 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1366 struct drm_device *dev = encoder->base.dev;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1369
0c33d8d7
DV		 1370 if (WARN_ON(dp_reg & DP_PORT_EN))
1371 return;
1372
97af61f5 1373 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1374 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
0c33d8d7
DV		 1375 intel_dp_start_link_train(intel_dp);
1376 ironlake_edp_panel_on(intel_dp);
1377 ironlake_edp_panel_vdd_off(intel_dp, true);
1378 intel_dp_complete_link_train(intel_dp);
f01eca2e 1379 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1380}
1381
2bd2ad64 1382static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1383{
2bd2ad64 1384 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0a91ca29 1385
2bd2ad64
DV		 1386 if (is_cpu_edp(intel_dp))
1387 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1388}
1389
1390/*
df0c237d
JB		 1391 * Native read with retry for link status and receiver capability reads for
1392 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1393 */
1394static bool
df0c237d
JB		 1395intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1396 uint8_t *recv, int recv_bytes)
a4fc5ed6 1397{
61da5fab
JB		 1398 int ret, i;
1399
df0c237d
JB		 1400 /*
1401 * Sinks are *supposed* to come up within 1ms from an off state,
1402 * but we're also supposed to retry 3 times per the spec.
1403 */
61da5fab 1404 for (i = 0; i < 3; i++) {
df0c237d
JB		 1405 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1406 recv_bytes);
1407 if (ret == recv_bytes)
61da5fab
JB		 1408 return true;
1409 msleep(1);
1410 }
a4fc5ed6 1411
61da5fab 1412 return false;
a4fc5ed6
KP		 1413}
1414
1415/*
1416 * Fetch AUX CH registers 0x202 - 0x207 which contain
1417 * link status information
1418 */
1419static bool
93f62dad 1420intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1421{
df0c237d
JB		 1422 return intel_dp_aux_native_read_retry(intel_dp,
1423 DP_LANE0_1_STATUS,
93f62dad 1424 link_status,
df0c237d 1425 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1426}
1427
a4fc5ed6
KP		 1428#if 0
1429static char *voltage_names[] = {
1430 "0.4V", "0.6V", "0.8V", "1.2V"
1431};
1432static char *pre_emph_names[] = {
1433 "0dB", "3.5dB", "6dB", "9.5dB"
1434};
1435static char *link_train_names[] = {
1436 "pattern 1", "pattern 2", "idle", "off"
1437};
1438#endif
1439
1440/*
1441 * These are source-specific values; current Intel hardware supports
1442 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1443 */
a4fc5ed6
KP		 1444
1445static uint8_t
1a2eb460 1446intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1447{
1a2eb460
KP		 1448 struct drm_device *dev = intel_dp->base.base.dev;
1449
1450 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1451 return DP_TRAIN_VOLTAGE_SWING_800;
1452 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1453 return DP_TRAIN_VOLTAGE_SWING_1200;
1454 else
1455 return DP_TRAIN_VOLTAGE_SWING_800;
1456}
1457
1458static uint8_t
1459intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1460{
1461 struct drm_device *dev = intel_dp->base.base.dev;
1462
d6c0d722
PZ		 1463 if (IS_HASWELL(dev)) {
1464 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1465 case DP_TRAIN_VOLTAGE_SWING_400:
1466 return DP_TRAIN_PRE_EMPHASIS_9_5;
1467 case DP_TRAIN_VOLTAGE_SWING_600:
1468 return DP_TRAIN_PRE_EMPHASIS_6;
1469 case DP_TRAIN_VOLTAGE_SWING_800:
1470 return DP_TRAIN_PRE_EMPHASIS_3_5;
1471 case DP_TRAIN_VOLTAGE_SWING_1200:
1472 default:
1473 return DP_TRAIN_PRE_EMPHASIS_0;
1474 }
1475 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1476 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1477 case DP_TRAIN_VOLTAGE_SWING_400:
1478 return DP_TRAIN_PRE_EMPHASIS_6;
1479 case DP_TRAIN_VOLTAGE_SWING_600:
1480 case DP_TRAIN_VOLTAGE_SWING_800:
1481 return DP_TRAIN_PRE_EMPHASIS_3_5;
1482 default:
1483 return DP_TRAIN_PRE_EMPHASIS_0;
1484 }
1485 } else {
1486 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1487 case DP_TRAIN_VOLTAGE_SWING_400:
1488 return DP_TRAIN_PRE_EMPHASIS_6;
1489 case DP_TRAIN_VOLTAGE_SWING_600:
1490 return DP_TRAIN_PRE_EMPHASIS_6;
1491 case DP_TRAIN_VOLTAGE_SWING_800:
1492 return DP_TRAIN_PRE_EMPHASIS_3_5;
1493 case DP_TRAIN_VOLTAGE_SWING_1200:
1494 default:
1495 return DP_TRAIN_PRE_EMPHASIS_0;
1496 }
a4fc5ed6
KP		 1497 }
1498}
1499
1500static void
93f62dad 1501intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1502{
1503 uint8_t v = 0;
1504 uint8_t p = 0;
1505 int lane;
1a2eb460
KP		 1506 uint8_t voltage_max;
1507 uint8_t preemph_max;
a4fc5ed6 1508
33a34e4e 1509 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1510 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1511 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1512
1513 if (this_v > v)
1514 v = this_v;
1515 if (this_p > p)
1516 p = this_p;
1517 }
1518
1a2eb460 1519 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1520 if (v >= voltage_max)
1521 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1522
1a2eb460
KP		 1523 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1524 if (p >= preemph_max)
1525 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1526
1527 for (lane = 0; lane < 4; lane++)
33a34e4e 1528 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1529}
1530
1531static uint32_t
93f62dad 1532intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1533{
3cf2efb1 1534 uint32_t signal_levels = 0;
a4fc5ed6 1535
3cf2efb1 1536 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1537 case DP_TRAIN_VOLTAGE_SWING_400:
1538 default:
1539 signal_levels |= DP_VOLTAGE_0_4;
1540 break;
1541 case DP_TRAIN_VOLTAGE_SWING_600:
1542 signal_levels |= DP_VOLTAGE_0_6;
1543 break;
1544 case DP_TRAIN_VOLTAGE_SWING_800:
1545 signal_levels |= DP_VOLTAGE_0_8;
1546 break;
1547 case DP_TRAIN_VOLTAGE_SWING_1200:
1548 signal_levels |= DP_VOLTAGE_1_2;
1549 break;
1550 }
3cf2efb1 1551 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1552 case DP_TRAIN_PRE_EMPHASIS_0:
1553 default:
1554 signal_levels |= DP_PRE_EMPHASIS_0;
1555 break;
1556 case DP_TRAIN_PRE_EMPHASIS_3_5:
1557 signal_levels |= DP_PRE_EMPHASIS_3_5;
1558 break;
1559 case DP_TRAIN_PRE_EMPHASIS_6:
1560 signal_levels |= DP_PRE_EMPHASIS_6;
1561 break;
1562 case DP_TRAIN_PRE_EMPHASIS_9_5:
1563 signal_levels |= DP_PRE_EMPHASIS_9_5;
1564 break;
1565 }
1566 return signal_levels;
1567}
1568
e3421a18
ZW		 1569/* Gen6's DP voltage swing and pre-emphasis control */
1570static uint32_t
1571intel_gen6_edp_signal_levels(uint8_t train_set)
1572{
3c5a62b5
YL		 1573 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1574 DP_TRAIN_PRE_EMPHASIS_MASK);
1575 switch (signal_levels) {
e3421a18 1576 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1577 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1578 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1579 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1580 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1581 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1582 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1583 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1584 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1585 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1586 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1587 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1588 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1589 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1590 default:
3c5a62b5
YL		 1591 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1592 "0x%x\n", signal_levels);
1593 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1594 }
1595}
1596
1a2eb460
KP		 1597/* Gen7's DP voltage swing and pre-emphasis control */
1598static uint32_t
1599intel_gen7_edp_signal_levels(uint8_t train_set)
1600{
1601 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1602 DP_TRAIN_PRE_EMPHASIS_MASK);
1603 switch (signal_levels) {
1604 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1605 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1606 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1607 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1608 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1609 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1610
1611 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1612 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1613 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1614 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1615
1616 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1617 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1618 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1619 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1620
1621 default:
1622 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1623 "0x%x\n", signal_levels);
1624 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1625 }
1626}
1627
d6c0d722
PZ		 1628/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1629static uint32_t
1630intel_dp_signal_levels_hsw(uint8_t train_set)
1631{
1632 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1633 DP_TRAIN_PRE_EMPHASIS_MASK);
1634 switch (signal_levels) {
1635 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1636 return DDI_BUF_EMP_400MV_0DB_HSW;
1637 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1638 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1639 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1640 return DDI_BUF_EMP_400MV_6DB_HSW;
1641 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1642 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1643
1644 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1645 return DDI_BUF_EMP_600MV_0DB_HSW;
1646 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1647 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1648 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1649 return DDI_BUF_EMP_600MV_6DB_HSW;
1650
1651 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1652 return DDI_BUF_EMP_800MV_0DB_HSW;
1653 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1654 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1655 default:
1656 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1657 "0x%x\n", signal_levels);
1658 return DDI_BUF_EMP_400MV_0DB_HSW;
1659 }
1660}
1661
a4fc5ed6 1662static bool
ea5b213a 1663intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1664 uint32_t dp_reg_value,
58e10eb9 1665 uint8_t dp_train_pat)
a4fc5ed6 1666{
4ef69c7a 1667 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1668 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1669 int ret;
d6c0d722 1670 uint32_t temp;
a4fc5ed6 1671
d6c0d722
PZ		 1672 if (IS_HASWELL(dev)) {
1673 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1674
1675 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1676 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1677 else
1678 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1679
1680 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1681 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1682 case DP_TRAINING_PATTERN_DISABLE:
1683 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1684 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1685
1686 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1687 DP_TP_STATUS_IDLE_DONE), 1))
1688 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1689
1690 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1691 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1692
1693 break;
1694 case DP_TRAINING_PATTERN_1:
1695 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1696 break;
1697 case DP_TRAINING_PATTERN_2:
1698 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1699 break;
1700 case DP_TRAINING_PATTERN_3:
1701 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1702 break;
1703 }
1704 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1705
1706 } else if (HAS_PCH_CPT(dev) &&
1707 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1708 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1709
1710 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1711 case DP_TRAINING_PATTERN_DISABLE:
1712 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1713 break;
1714 case DP_TRAINING_PATTERN_1:
1715 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1716 break;
1717 case DP_TRAINING_PATTERN_2:
1718 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1719 break;
1720 case DP_TRAINING_PATTERN_3:
1721 DRM_ERROR("DP training pattern 3 not supported\n");
1722 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1723 break;
1724 }
1725
1726 } else {
1727 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1728
1729 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1730 case DP_TRAINING_PATTERN_DISABLE:
1731 dp_reg_value |= DP_LINK_TRAIN_OFF;
1732 break;
1733 case DP_TRAINING_PATTERN_1:
1734 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1735 break;
1736 case DP_TRAINING_PATTERN_2:
1737 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1738 break;
1739 case DP_TRAINING_PATTERN_3:
1740 DRM_ERROR("DP training pattern 3 not supported\n");
1741 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1742 break;
1743 }
1744 }
1745
ea5b213a
CW		 1746 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1747 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1748
ea5b213a 1749 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1750 DP_TRAINING_PATTERN_SET,
1751 dp_train_pat);
1752
47ea7542
PZ		 1753 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1754 DP_TRAINING_PATTERN_DISABLE) {
1755 ret = intel_dp_aux_native_write(intel_dp,
1756 DP_TRAINING_LANE0_SET,
1757 intel_dp->train_set,
1758 intel_dp->lane_count);
1759 if (ret != intel_dp->lane_count)
1760 return false;
1761 }
a4fc5ed6
KP		 1762
1763 return true;
1764}
1765
33a34e4e 1766/* Enable corresponding port and start training pattern 1 */
c19b0669 1767void
33a34e4e 1768intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1769{
c19b0669
PZ		 1770 struct drm_encoder *encoder = &intel_dp->base.base;
1771 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1772 int i;
1773 uint8_t voltage;
1774 bool clock_recovery = false;
cdb0e95b 1775 int voltage_tries, loop_tries;
ea5b213a 1776 uint32_t DP = intel_dp->DP;
a4fc5ed6 1777
c19b0669
PZ		 1778 if (IS_HASWELL(dev))
1779 intel_ddi_prepare_link_retrain(encoder);
1780
3cf2efb1
CW		 1781 /* Write the link configuration data */
1782 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1783 intel_dp->link_configuration,
1784 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1785
1786 DP |= DP_PORT_EN;
1a2eb460 1787
33a34e4e 1788 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1789 voltage = 0xff;
cdb0e95b
KP		 1790 voltage_tries = 0;
1791 loop_tries = 0;
a4fc5ed6
KP		 1792 clock_recovery = false;
1793 for (;;) {
33a34e4e 1794 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1795 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1796 uint32_t signal_levels;
417e822d 1797
d6c0d722
PZ		 1798 if (IS_HASWELL(dev)) {
1799 signal_levels = intel_dp_signal_levels_hsw(
1800 intel_dp->train_set[0]);
1801 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1802 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1803 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1804 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1805 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1806 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1807 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1808 } else {
93f62dad 1809 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1810 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1811 }
d6c0d722
PZ		 1812 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1813 signal_levels);
a4fc5ed6 1814
a7c9655f 1815 /* Set training pattern 1 */
47ea7542 1816 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1817 DP_TRAINING_PATTERN_1 |
1818 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1819 break;
a4fc5ed6 1820
a7c9655f 1821 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 1822 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1823 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1824 break;
93f62dad 1825 }
a4fc5ed6 1826
01916270 1827 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 1828 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1829 clock_recovery = true;
1830 break;
1831 }
1832
1833 /* Check to see if we've tried the max voltage */
1834 for (i = 0; i < intel_dp->lane_count; i++)
1835 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1836 break;
0d710688 1837 if (i == intel_dp->lane_count && voltage_tries == 5) {
24773670 1838 if (++loop_tries == 5) {
cdb0e95b
KP		 1839 DRM_DEBUG_KMS("too many full retries, give up\n");
1840 break;
1841 }
1842 memset(intel_dp->train_set, 0, 4);
1843 voltage_tries = 0;
1844 continue;
1845 }
a4fc5ed6 1846
3cf2efb1 1847 /* Check to see if we've tried the same voltage 5 times */
24773670
CW		 1848 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
1849 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
cdb0e95b 1850 voltage_tries = 0;
24773670
CW		 1851 } else
1852 ++voltage_tries;
a4fc5ed6 1853
3cf2efb1 1854 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1855 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1856 }
1857
33a34e4e
JB		 1858 intel_dp->DP = DP;
1859}
1860
c19b0669 1861void
33a34e4e
JB		 1862intel_dp_complete_link_train(struct intel_dp *intel_dp)
1863{
4ef69c7a 1864 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e 1865 bool channel_eq = false;
37f80975 1866 int tries, cr_tries;
33a34e4e
JB		 1867 uint32_t DP = intel_dp->DP;
1868
a4fc5ed6
KP		 1869 /* channel equalization */
1870 tries = 0;
37f80975 1871 cr_tries = 0;
a4fc5ed6
KP		 1872 channel_eq = false;
1873 for (;;) {
33a34e4e 1874 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1875 uint32_t signal_levels;
93f62dad 1876 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1877
37f80975
JB		 1878 if (cr_tries > 5) {
1879 DRM_ERROR("failed to train DP, aborting\n");
1880 intel_dp_link_down(intel_dp);
1881 break;
1882 }
1883
d6c0d722
PZ		 1884 if (IS_HASWELL(dev)) {
1885 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1886 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1887 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1888 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1889 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1890 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1891 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1892 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1893 } else {
93f62dad 1894 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1895 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1896 }
1897
a4fc5ed6 1898 /* channel eq pattern */
47ea7542 1899 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1900 DP_TRAINING_PATTERN_2 |
1901 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1902 break;
1903
a7c9655f 1904 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 1905 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1906 break;
a4fc5ed6 1907
37f80975 1908 /* Make sure clock is still ok */
01916270 1909 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1910 intel_dp_start_link_train(intel_dp);
1911 cr_tries++;
1912 continue;
1913 }
1914
1ffdff13 1915 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 1916 channel_eq = true;
1917 break;
1918 }
a4fc5ed6 1919
37f80975
JB		 1920 /* Try 5 times, then try clock recovery if that fails */
1921 if (tries > 5) {
1922 intel_dp_link_down(intel_dp);
1923 intel_dp_start_link_train(intel_dp);
1924 tries = 0;
1925 cr_tries++;
1926 continue;
1927 }
a4fc5ed6 1928
3cf2efb1 1929 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1930 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1931 ++tries;
869184a6 1932 }
3cf2efb1 1933
d6c0d722
PZ		 1934 if (channel_eq)
1935 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1936
47ea7542 1937 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 1938}
1939
1940static void
ea5b213a 1941intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1942{
4ef69c7a 1943 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1944 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1945 uint32_t DP = intel_dp->DP;
a4fc5ed6 1946
c19b0669
PZ		 1947 /*
1948 * DDI code has a strict mode set sequence and we should try to respect
1949 * it, otherwise we might hang the machine in many different ways. So we
1950 * really should be disabling the port only on a complete crtc_disable
1951 * sequence. This function is just called under two conditions on DDI
1952 * code:
1953 * - Link train failed while doing crtc_enable, and on this case we
1954 * really should respect the mode set sequence and wait for a
1955 * crtc_disable.
1956 * - Someone turned the monitor off and intel_dp_check_link_status
1957 * called us. We don't need to disable the whole port on this case, so
1958 * when someone turns the monitor on again,
1959 * intel_ddi_prepare_link_retrain will take care of redoing the link
1960 * train.
1961 */
1962 if (IS_HASWELL(dev))
1963 return;
1964
0c33d8d7 1965 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 1966 return;
1967
28c97730 1968 DRM_DEBUG_KMS("\n");
32f9d658 1969
1a2eb460 1970 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1971 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1972 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1973 } else {
1974 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1975 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1976 }
fe255d00 1977 POSTING_READ(intel_dp->output_reg);
5eb08b69 1978
fe255d00 1979 msleep(17);
5eb08b69 1980
493a7081 1981 if (HAS_PCH_IBX(dev) &&
1b39d6f3 1982 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 1983 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1984
5bddd17f
EA		 1985 /* Hardware workaround: leaving our transcoder select
1986 * set to transcoder B while it's off will prevent the
1987 * corresponding HDMI output on transcoder A.
1988 *
1989 * Combine this with another hardware workaround:
1990 * transcoder select bit can only be cleared while the
1991 * port is enabled.
1992 */
1993 DP &= ~DP_PIPEB_SELECT;
1994 I915_WRITE(intel_dp->output_reg, DP);
1995
1996 /* Changes to enable or select take place the vblank
1997 * after being written.
1998 */
31acbcc4
CW		 1999 if (crtc == NULL) {
2000 /* We can arrive here never having been attached
2001 * to a CRTC, for instance, due to inheriting
2002 * random state from the BIOS.
2003 *
2004 * If the pipe is not running, play safe and
2005 * wait for the clocks to stabilise before
2006 * continuing.
2007 */
2008 POSTING_READ(intel_dp->output_reg);
2009 msleep(50);
2010 } else
2011 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 2012 }
2013
832afda6 2014 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2015 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2016 POSTING_READ(intel_dp->output_reg);
f01eca2e 2017 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2018}
2019
26d61aad
KP		 2020static bool
2021intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2022{
92fd8fd1 2023 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
b091cd92
AJ		 2024 sizeof(intel_dp->dpcd)) == 0)
2025 return false; /* aux transfer failed */
92fd8fd1 2026
b091cd92
AJ		 2027 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2028 return false; /* DPCD not present */
2029
2030 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2031 DP_DWN_STRM_PORT_PRESENT))
2032 return true; /* native DP sink */
2033
2034 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2035 return true; /* no per-port downstream info */
2036
2037 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2038 intel_dp->downstream_ports,
2039 DP_MAX_DOWNSTREAM_PORTS) == 0)
2040 return false; /* downstream port status fetch failed */
2041
2042 return true;
92fd8fd1
KP		 2043}
2044
0d198328
AJ		 2045static void
2046intel_dp_probe_oui(struct intel_dp *intel_dp)
2047{
2048 u8 buf[3];
2049
2050 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2051 return;
2052
351cfc34
DV		 2053 ironlake_edp_panel_vdd_on(intel_dp);
2054
0d198328
AJ		 2055 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2056 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2057 buf[0], buf[1], buf[2]);
2058
2059 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2060 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2061 buf[0], buf[1], buf[2]);
351cfc34
DV		 2062
2063 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2064}
2065
a60f0e38
JB		 2066static bool
2067intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2068{
2069 int ret;
2070
2071 ret = intel_dp_aux_native_read_retry(intel_dp,
2072 DP_DEVICE_SERVICE_IRQ_VECTOR,
2073 sink_irq_vector, 1);
2074 if (!ret)
2075 return false;
2076
2077 return true;
2078}
2079
2080static void
2081intel_dp_handle_test_request(struct intel_dp *intel_dp)
2082{
2083 /* NAK by default */
9324cf7f 2084 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2085}
2086
a4fc5ed6
KP		 2087/*
2088 * According to DP spec
2089 * 5.1.2:
2090 * 1. Read DPCD
2091 * 2. Configure link according to Receiver Capabilities
2092 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2093 * 4. Check link status on receipt of hot-plug interrupt
2094 */
2095
2096static void
ea5b213a 2097intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2098{
a60f0e38 2099 u8 sink_irq_vector;
93f62dad 2100 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2101
24e804ba 2102 if (!intel_dp->base.connectors_active)
d2b996ac 2103 return;
59cd09e1 2104
24e804ba 2105 if (WARN_ON(!intel_dp->base.base.crtc))
a4fc5ed6
KP		 2106 return;
2107
92fd8fd1 2108 /* Try to read receiver status if the link appears to be up */
93f62dad 2109 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2110 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2111 return;
2112 }
2113
92fd8fd1 2114 /* Now read the DPCD to see if it's actually running */
26d61aad 2115 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2116 intel_dp_link_down(intel_dp);
2117 return;
2118 }
2119
a60f0e38
JB		 2120 /* Try to read the source of the interrupt */
2121 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2122 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2123 /* Clear interrupt source */
2124 intel_dp_aux_native_write_1(intel_dp,
2125 DP_DEVICE_SERVICE_IRQ_VECTOR,
2126 sink_irq_vector);
2127
2128 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2129 intel_dp_handle_test_request(intel_dp);
2130 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2131 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2132 }
2133
1ffdff13 2134 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1
KP		 2135 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2136 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2137 intel_dp_start_link_train(intel_dp);
2138 intel_dp_complete_link_train(intel_dp);
2139 }
a4fc5ed6 2140}
a4fc5ed6 2141
07d3dc18 2142/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2143static enum drm_connector_status
26d61aad 2144intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2145{
07d3dc18
AJ		 2146 uint8_t *dpcd = intel_dp->dpcd;
2147 bool hpd;
2148 uint8_t type;
2149
2150 if (!intel_dp_get_dpcd(intel_dp))
2151 return connector_status_disconnected;
2152
2153 /* if there's no downstream port, we're done */
2154 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2155 return connector_status_connected;
2156
2157 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2158 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2159 if (hpd) {
da131a46 2160 uint8_t reg;
07d3dc18 2161 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
da131a46 2162 &reg, 1))
07d3dc18 2163 return connector_status_unknown;
da131a46
AJ		 2164 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2165 : connector_status_disconnected;
07d3dc18
AJ		 2166 }
2167
2168 /* If no HPD, poke DDC gently */
2169 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2170 return connector_status_connected;
07d3dc18
AJ		 2171
2172 /* Well we tried, say unknown for unreliable port types */
2173 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2174 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2175 return connector_status_unknown;
2176
2177 /* Anything else is out of spec, warn and ignore */
2178 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2179 return connector_status_disconnected;
71ba9000
AJ		 2180}
2181
5eb08b69 2182static enum drm_connector_status
a9756bb5 2183ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2184{
5eb08b69
ZW		 2185 enum drm_connector_status status;
2186
fe16d949
CW		 2187 /* Can't disconnect eDP, but you can close the lid... */
2188 if (is_edp(intel_dp)) {
2189 status = intel_panel_detect(intel_dp->base.base.dev);
2190 if (status == connector_status_unknown)
2191 status = connector_status_connected;
2192 return status;
2193 }
01cb9ea6 2194
26d61aad 2195 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2196}
2197
a4fc5ed6 2198static enum drm_connector_status
a9756bb5 2199g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2200{
4ef69c7a 2201 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2202 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2203 uint32_t bit;
5eb08b69 2204
ea5b213a 2205 switch (intel_dp->output_reg) {
a4fc5ed6 2206 case DP_B:
10f76a38 2207 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2208 break;
2209 case DP_C:
10f76a38 2210 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2211 break;
2212 case DP_D:
10f76a38 2213 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2214 break;
2215 default:
2216 return connector_status_unknown;
2217 }
2218
10f76a38 2219 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2220 return connector_status_disconnected;
2221
26d61aad 2222 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2223}
2224
8c241fef
KP		 2225static struct edid *
2226intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2227{
9cd300e0 2228 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2229
9cd300e0
JN		 2230 /* use cached edid if we have one */
2231 if (intel_connector->edid) {
2232 struct edid *edid;
2233 int size;
2234
2235 /* invalid edid */
2236 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2237 return NULL;
2238
9cd300e0 2239 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2240 edid = kmalloc(size, GFP_KERNEL);
2241 if (!edid)
2242 return NULL;
2243
9cd300e0 2244 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2245 return edid;
2246 }
8c241fef 2247
9cd300e0 2248 return drm_get_edid(connector, adapter);
8c241fef
KP		 2249}
2250
2251static int
2252intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2253{
9cd300e0 2254 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2255
9cd300e0
JN		 2256 /* use cached edid if we have one */
2257 if (intel_connector->edid) {
2258 /* invalid edid */
2259 if (IS_ERR(intel_connector->edid))
2260 return 0;
2261
2262 return intel_connector_update_modes(connector,
2263 intel_connector->edid);
d6f24d0f
JB		 2264 }
2265
9cd300e0 2266 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2267}
2268
2269
a9756bb5
ZW		 2270/**
2271 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2272 *
2273 * \return true if DP port is connected.
2274 * \return false if DP port is disconnected.
2275 */
2276static enum drm_connector_status
2277intel_dp_detect(struct drm_connector *connector, bool force)
2278{
2279 struct intel_dp *intel_dp = intel_attached_dp(connector);
2280 struct drm_device *dev = intel_dp->base.base.dev;
2281 enum drm_connector_status status;
2282 struct edid *edid = NULL;
2283
2284 intel_dp->has_audio = false;
2285
2286 if (HAS_PCH_SPLIT(dev))
2287 status = ironlake_dp_detect(intel_dp);
2288 else
2289 status = g4x_dp_detect(intel_dp);
1b9be9d0 2290
ac66ae83
AJ		 2291 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2292 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2293 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2294 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 2295
a9756bb5
ZW		 2296 if (status != connector_status_connected)
2297 return status;
2298
0d198328
AJ		 2299 intel_dp_probe_oui(intel_dp);
2300
c3e5f67b
DV		 2301 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2302 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2303 } else {
8c241fef 2304 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2305 if (edid) {
2306 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2307 kfree(edid);
2308 }
a9756bb5
ZW		 2309 }
2310
2311 return connector_status_connected;
a4fc5ed6
KP		 2312}
2313
2314static int intel_dp_get_modes(struct drm_connector *connector)
2315{
df0e9248 2316 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2317 struct intel_connector *intel_connector = to_intel_connector(connector);
4ef69c7a 2318 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658 2319 int ret;
a4fc5ed6
KP		 2320
2321 /* We should parse the EDID data and find out if it has an audio sink
2322 */
2323
8c241fef 2324 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2325 if (ret)
32f9d658
ZW		 2326 return ret;
2327
f8779fda 2328 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2329 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2330 struct drm_display_mode *mode;
dd06f90e
JN		 2331 mode = drm_mode_duplicate(dev,
2332 intel_connector->panel.fixed_mode);
f8779fda 2333 if (mode) {
32f9d658
ZW		 2334 drm_mode_probed_add(connector, mode);
2335 return 1;
2336 }
2337 }
2338 return 0;
a4fc5ed6
KP		 2339}
2340
1aad7ac0
CW		 2341static bool
2342intel_dp_detect_audio(struct drm_connector *connector)
2343{
2344 struct intel_dp *intel_dp = intel_attached_dp(connector);
2345 struct edid *edid;
2346 bool has_audio = false;
2347
8c241fef 2348 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2349 if (edid) {
2350 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2351 kfree(edid);
2352 }
2353
2354 return has_audio;
2355}
2356
f684960e
CW		 2357static int
2358intel_dp_set_property(struct drm_connector *connector,
2359 struct drm_property *property,
2360 uint64_t val)
2361{
e953fd7b 2362 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2363 struct intel_dp *intel_dp = intel_attached_dp(connector);
2364 int ret;
2365
2366 ret = drm_connector_property_set_value(connector, property, val);
2367 if (ret)
2368 return ret;
2369
3f43c48d 2370 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2371 int i = val;
2372 bool has_audio;
2373
2374 if (i == intel_dp->force_audio)
f684960e
CW		 2375 return 0;
2376
1aad7ac0 2377 intel_dp->force_audio = i;
f684960e 2378
c3e5f67b 2379 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2380 has_audio = intel_dp_detect_audio(connector);
2381 else
c3e5f67b 2382 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2383
2384 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2385 return 0;
2386
1aad7ac0 2387 intel_dp->has_audio = has_audio;
f684960e
CW		 2388 goto done;
2389 }
2390
e953fd7b
CW		 2391 if (property == dev_priv->broadcast_rgb_property) {
2392 if (val == !!intel_dp->color_range)
2393 return 0;
2394
2395 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2396 goto done;
2397 }
2398
f684960e
CW		 2399 return -EINVAL;
2400
2401done:
2402 if (intel_dp->base.base.crtc) {
2403 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a6778b3c
DV		 2404 intel_set_mode(crtc, &crtc->mode,
2405 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2406 }
2407
2408 return 0;
2409}
2410
a4fc5ed6 2411static void
0206e353 2412intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2413{
aaa6fd2a 2414 struct drm_device *dev = connector->dev;
be3cd5e3 2415 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2416 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2417
9cd300e0
JN		 2418 if (!IS_ERR_OR_NULL(intel_connector->edid))
2419 kfree(intel_connector->edid);
2420
1d508706 2421 if (is_edp(intel_dp)) {
aaa6fd2a 2422 intel_panel_destroy_backlight(dev);
1d508706
JN		 2423 intel_panel_fini(&intel_connector->panel);
2424 }
aaa6fd2a 2425
a4fc5ed6
KP		 2426 drm_sysfs_connector_remove(connector);
2427 drm_connector_cleanup(connector);
55f78c43 2428 kfree(connector);
a4fc5ed6
KP		 2429}
2430
24d05927
DV		 2431static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2432{
2433 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2434
2435 i2c_del_adapter(&intel_dp->adapter);
2436 drm_encoder_cleanup(encoder);
bd943159
KP		 2437 if (is_edp(intel_dp)) {
2438 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2439 ironlake_panel_vdd_off_sync(intel_dp);
2440 }
24d05927
DV		 2441 kfree(intel_dp);
2442}
2443
a4fc5ed6 2444static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2445 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2446 .mode_set = intel_dp_mode_set,
1f703855 2447 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2448};
2449
a7902ac5
PZ		 2450static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw = {
2451 .mode_fixup = intel_dp_mode_fixup,
2452 .mode_set = intel_ddi_mode_set,
2453 .disable = intel_encoder_noop,
2454};
2455
a4fc5ed6 2456static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2457 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2458 .detect = intel_dp_detect,
2459 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2460 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2461 .destroy = intel_dp_destroy,
2462};
2463
2464static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2465 .get_modes = intel_dp_get_modes,
2466 .mode_valid = intel_dp_mode_valid,
df0e9248 2467 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2468};
2469
a4fc5ed6 2470static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2471 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2472};
2473
995b6762 2474static void
21d40d37 2475intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2476{
ea5b213a 2477 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2478
885a5014 2479 intel_dp_check_link_status(intel_dp);
c8110e52 2480}
6207937d 2481
e3421a18
ZW		 2482/* Return which DP Port should be selected for Transcoder DP control */
2483int
0206e353 2484intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2485{
2486 struct drm_device *dev = crtc->dev;
6c2b7c12 2487 struct intel_encoder *encoder;
e3421a18 2488
6c2b7c12
DV		 2489 for_each_encoder_on_crtc(dev, crtc, encoder) {
2490 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
e3421a18 2491
417e822d
KP		 2492 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2493 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2494 return intel_dp->output_reg;
e3421a18 2495 }
ea5b213a 2496
e3421a18
ZW		 2497 return -1;
2498}
2499
36e83a18 2500/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2501bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2502{
2503 struct drm_i915_private *dev_priv = dev->dev_private;
2504 struct child_device_config *p_child;
2505 int i;
2506
2507 if (!dev_priv->child_dev_num)
2508 return false;
2509
2510 for (i = 0; i < dev_priv->child_dev_num; i++) {
2511 p_child = dev_priv->child_dev + i;
2512
2513 if (p_child->dvo_port == PORT_IDPD &&
2514 p_child->device_type == DEVICE_TYPE_eDP)
2515 return true;
2516 }
2517 return false;
2518}
2519
f684960e
CW		 2520static void
2521intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2522{
3f43c48d 2523 intel_attach_force_audio_property(connector);
e953fd7b 2524 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2525}
2526
67a54566
DV		 2527static void
2528intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2529 struct intel_dp *intel_dp)
2530{
2531 struct drm_i915_private *dev_priv = dev->dev_private;
2532 struct edp_power_seq cur, vbt, spec, final;
2533 u32 pp_on, pp_off, pp_div, pp;
2534
2535 /* Workaround: Need to write PP_CONTROL with the unlock key as
2536 * the very first thing. */
2537 pp = ironlake_get_pp_control(dev_priv);
2538 I915_WRITE(PCH_PP_CONTROL, pp);
2539
2540 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2541 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2542 pp_div = I915_READ(PCH_PP_DIVISOR);
2543
2544 /* Pull timing values out of registers */
2545 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2546 PANEL_POWER_UP_DELAY_SHIFT;
2547
2548 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2549 PANEL_LIGHT_ON_DELAY_SHIFT;
2550
2551 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2552 PANEL_LIGHT_OFF_DELAY_SHIFT;
2553
2554 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2555 PANEL_POWER_DOWN_DELAY_SHIFT;
2556
2557 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2558 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2559
2560 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2561 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2562
2563 vbt = dev_priv->edp.pps;
2564
2565 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2566 * our hw here, which are all in 100usec. */
2567 spec.t1_t3 = 210 * 10;
2568 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2569 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2570 spec.t10 = 500 * 10;
2571 /* This one is special and actually in units of 100ms, but zero
2572 * based in the hw (so we need to add 100 ms). But the sw vbt
2573 * table multiplies it with 1000 to make it in units of 100usec,
2574 * too. */
2575 spec.t11_t12 = (510 + 100) * 10;
2576
2577 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2578 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2579
2580 /* Use the max of the register settings and vbt. If both are
2581 * unset, fall back to the spec limits. */
2582#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2583 spec.field : \
2584 max(cur.field, vbt.field))
2585 assign_final(t1_t3);
2586 assign_final(t8);
2587 assign_final(t9);
2588 assign_final(t10);
2589 assign_final(t11_t12);
2590#undef assign_final
2591
2592#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2593 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2594 intel_dp->backlight_on_delay = get_delay(t8);
2595 intel_dp->backlight_off_delay = get_delay(t9);
2596 intel_dp->panel_power_down_delay = get_delay(t10);
2597 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2598#undef get_delay
2599
2600 /* And finally store the new values in the power sequencer. */
2601 pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2602 (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2603 pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2604 (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2605 /* Compute the divisor for the pp clock, simply match the Bspec
2606 * formula. */
2607 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2608 << PP_REFERENCE_DIVIDER_SHIFT;
2609 pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
2610 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2611
2612 /* Haswell doesn't have any port selection bits for the panel
2613 * power sequencer any more. */
2614 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2615 if (is_cpu_edp(intel_dp))
2616 pp_on |= PANEL_POWER_PORT_DP_A;
2617 else
2618 pp_on |= PANEL_POWER_PORT_DP_D;
2619 }
2620
2621 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2622 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2623 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2624
2625
2626 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2627 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2628 intel_dp->panel_power_cycle_delay);
2629
2630 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2631 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2632
2633 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2634 I915_READ(PCH_PP_ON_DELAYS),
2635 I915_READ(PCH_PP_OFF_DELAYS),
2636 I915_READ(PCH_PP_DIVISOR));
2637}
2638
a4fc5ed6 2639void
ab9d7c30 2640intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
a4fc5ed6
KP		 2641{
2642 struct drm_i915_private *dev_priv = dev->dev_private;
2643 struct drm_connector *connector;
ea5b213a 2644 struct intel_dp *intel_dp;
21d40d37 2645 struct intel_encoder *intel_encoder;
55f78c43 2646 struct intel_connector *intel_connector;
f8779fda 2647 struct drm_display_mode *fixed_mode = NULL;
5eb08b69 2648 const char *name = NULL;
b329530c 2649 int type;
a4fc5ed6 2650
ea5b213a
CW		 2651 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2652 if (!intel_dp)
a4fc5ed6
KP		 2653 return;
2654
3d3dc149 2655 intel_dp->output_reg = output_reg;
ab9d7c30 2656 intel_dp->port = port;
0767935e
DV		 2657 /* Preserve the current hw state. */
2658 intel_dp->DP = I915_READ(intel_dp->output_reg);
3d3dc149 2659
55f78c43
ZW		 2660 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2661 if (!intel_connector) {
ea5b213a 2662 kfree(intel_dp);
55f78c43
ZW		 2663 return;
2664 }
ea5b213a 2665 intel_encoder = &intel_dp->base;
dd06f90e 2666 intel_dp->attached_connector = intel_connector;
55f78c43 2667
ea5b213a 2668 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2669 if (intel_dpd_is_edp(dev))
ea5b213a 2670 intel_dp->is_pch_edp = true;
b329530c 2671
19c03924
GB		 2672 /*
2673 * FIXME : We need to initialize built-in panels before external panels.
2674 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2675 */
2676 if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2677 type = DRM_MODE_CONNECTOR_eDP;
2678 intel_encoder->type = INTEL_OUTPUT_EDP;
2679 } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2680 type = DRM_MODE_CONNECTOR_eDP;
2681 intel_encoder->type = INTEL_OUTPUT_EDP;
2682 } else {
2683 type = DRM_MODE_CONNECTOR_DisplayPort;
2684 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2685 }
2686
55f78c43 2687 connector = &intel_connector->base;
b329530c 2688 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2689 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2690
eb1f8e4f
DA		 2691 connector->polled = DRM_CONNECTOR_POLL_HPD;
2692
66a9278e 2693 intel_encoder->cloneable = false;
f8aed700 2694
66a9278e
DV		 2695 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2696 ironlake_panel_vdd_work);
6251ec0a 2697
27f8227b 2698 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2699
a4fc5ed6
KP		 2700 connector->interlace_allowed = true;
2701 connector->doublescan_allowed = 0;
2702
4ef69c7a 2703 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2704 DRM_MODE_ENCODER_TMDS);
a7902ac5
PZ		 2705
2706 if (IS_HASWELL(dev))
2707 drm_encoder_helper_add(&intel_encoder->base,
2708 &intel_dp_helper_funcs_hsw);
2709 else
2710 drm_encoder_helper_add(&intel_encoder->base,
2711 &intel_dp_helper_funcs);
a4fc5ed6 2712
df0e9248 2713 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2714 drm_sysfs_connector_add(connector);
2715
a7902ac5
PZ		 2716 if (IS_HASWELL(dev)) {
2717 intel_encoder->enable = intel_enable_ddi;
2718 intel_encoder->pre_enable = intel_ddi_pre_enable;
2719 intel_encoder->disable = intel_disable_ddi;
2720 intel_encoder->post_disable = intel_ddi_post_disable;
2721 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2722 } else {
2723 intel_encoder->enable = intel_enable_dp;
2724 intel_encoder->pre_enable = intel_pre_enable_dp;
2725 intel_encoder->disable = intel_disable_dp;
2726 intel_encoder->post_disable = intel_post_disable_dp;
2727 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2728 }
19d8fe15 2729 intel_connector->get_hw_state = intel_connector_get_hw_state;
e8cb4558 2730
a4fc5ed6 2731 /* Set up the DDC bus. */
ab9d7c30
PZ		 2732 switch (port) {
2733 case PORT_A:
2734 name = "DPDDC-A";
2735 break;
2736 case PORT_B:
2737 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2738 name = "DPDDC-B";
2739 break;
2740 case PORT_C:
2741 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2742 name = "DPDDC-C";
2743 break;
2744 case PORT_D:
2745 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2746 name = "DPDDC-D";
2747 break;
2748 default:
2749 WARN(1, "Invalid port %c\n", port_name(port));
2750 break;
5eb08b69
ZW		 2751 }
2752
67a54566
DV		 2753 if (is_edp(intel_dp))
2754 intel_dp_init_panel_power_sequencer(dev, intel_dp);
c1f05264
DA		 2755
2756 intel_dp_i2c_init(intel_dp, intel_connector, name);
2757
67a54566 2758 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 2759 if (is_edp(intel_dp)) {
2760 bool ret;
f8779fda 2761 struct drm_display_mode *scan;
c1f05264 2762 struct edid *edid;
5d613501
JB		 2763
2764 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2765 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2766 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2767
59f3e272 2768 if (ret) {
7183dc29
JB		 2769 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2770 dev_priv->no_aux_handshake =
2771 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2772 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2773 } else {
3d3dc149 2774 /* if this fails, presume the device is a ghost */
48898b03 2775 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2776 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2777 intel_dp_destroy(&intel_connector->base);
3d3dc149 2778 return;
89667383 2779 }
89667383 2780
d6f24d0f
JB		 2781 ironlake_edp_panel_vdd_on(intel_dp);
2782 edid = drm_get_edid(connector, &intel_dp->adapter);
2783 if (edid) {
9cd300e0
JN		 2784 if (drm_add_edid_modes(connector, edid)) {
2785 drm_mode_connector_update_edid_property(connector, edid);
2786 drm_edid_to_eld(connector, edid);
2787 } else {
2788 kfree(edid);
2789 edid = ERR_PTR(-EINVAL);
2790 }
2791 } else {
2792 edid = ERR_PTR(-ENOENT);
d6f24d0f 2793 }
9cd300e0 2794 intel_connector->edid = edid;
f8779fda
JN		 2795
2796 /* prefer fixed mode from EDID if available */
2797 list_for_each_entry(scan, &connector->probed_modes, head) {
2798 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2799 fixed_mode = drm_mode_duplicate(dev, scan);
2800 break;
2801 }
2802 }
2803
2804 /* fallback to VBT if available for eDP */
2805 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2806 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2807 if (fixed_mode)
2808 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2809 }
f8779fda 2810
d6f24d0f
JB		 2811 ironlake_edp_panel_vdd_off(intel_dp, false);
2812 }
552fb0b7 2813
21d40d37 2814 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2815
1d508706 2816 if (is_edp(intel_dp)) {
dd06f90e 2817 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 2818 intel_panel_setup_backlight(connector);
1d508706 2819 }
32f9d658 2820
f684960e
CW		 2821 intel_dp_add_properties(intel_dp, connector);
2822
a4fc5ed6
KP		 2823 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2824 * 0xd. Failure to do so will result in spurious interrupts being
2825 * generated on the port when a cable is not attached.
2826 */
2827 if (IS_G4X(dev) && !IS_GM45(dev)) {
2828 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2829 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2830 }
2831}
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