]>
Commit | Line | Data |
---|---|---|
a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
a4fc5ed6 | 37 | #include "i915_drv.h" |
a4fc5ed6 | 38 | |
a4fc5ed6 KP |
39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
40 | ||
9dd4ffdf CML |
41 | struct dp_link_dpll { |
42 | int link_bw; | |
43 | struct dpll dpll; | |
44 | }; | |
45 | ||
46 | static const struct dp_link_dpll gen4_dpll[] = { | |
47 | { DP_LINK_BW_1_62, | |
48 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, | |
49 | { DP_LINK_BW_2_7, | |
50 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } | |
51 | }; | |
52 | ||
53 | static const struct dp_link_dpll pch_dpll[] = { | |
54 | { DP_LINK_BW_1_62, | |
55 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, | |
56 | { DP_LINK_BW_2_7, | |
57 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } | |
58 | }; | |
59 | ||
65ce4bf5 CML |
60 | static const struct dp_link_dpll vlv_dpll[] = { |
61 | { DP_LINK_BW_1_62, | |
58f6e632 | 62 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
65ce4bf5 CML |
63 | { DP_LINK_BW_2_7, |
64 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } | |
65 | }; | |
66 | ||
cfcb0fc9 JB |
67 | /** |
68 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
69 | * @intel_dp: DP struct | |
70 | * | |
71 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
72 | * will return true, and false otherwise. | |
73 | */ | |
74 | static bool is_edp(struct intel_dp *intel_dp) | |
75 | { | |
da63a9f2 PZ |
76 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
77 | ||
78 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
79 | } |
80 | ||
68b4d824 | 81 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 82 | { |
68b4d824 ID |
83 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
84 | ||
85 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
86 | } |
87 | ||
df0e9248 CW |
88 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
89 | { | |
fa90ecef | 90 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
91 | } |
92 | ||
ea5b213a | 93 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
4be73780 DV |
94 | static void edp_panel_vdd_on(struct intel_dp *intel_dp); |
95 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); | |
a4fc5ed6 | 96 | |
a4fc5ed6 | 97 | static int |
ea5b213a | 98 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 99 | { |
7183dc29 | 100 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
06ea66b6 | 101 | struct drm_device *dev = intel_dp->attached_connector->base.dev; |
a4fc5ed6 KP |
102 | |
103 | switch (max_link_bw) { | |
104 | case DP_LINK_BW_1_62: | |
105 | case DP_LINK_BW_2_7: | |
106 | break; | |
d4eead50 | 107 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ |
06ea66b6 TP |
108 | if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) && |
109 | intel_dp->dpcd[DP_DPCD_REV] >= 0x12) | |
110 | max_link_bw = DP_LINK_BW_5_4; | |
111 | else | |
112 | max_link_bw = DP_LINK_BW_2_7; | |
d4eead50 | 113 | break; |
a4fc5ed6 | 114 | default: |
d4eead50 ID |
115 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
116 | max_link_bw); | |
a4fc5ed6 KP |
117 | max_link_bw = DP_LINK_BW_1_62; |
118 | break; | |
119 | } | |
120 | return max_link_bw; | |
121 | } | |
122 | ||
cd9dde44 AJ |
123 | /* |
124 | * The units on the numbers in the next two are... bizarre. Examples will | |
125 | * make it clearer; this one parallels an example in the eDP spec. | |
126 | * | |
127 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
128 | * | |
129 | * 270000 * 1 * 8 / 10 == 216000 | |
130 | * | |
131 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
132 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
133 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
134 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
135 | * | |
136 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
137 | * get the result in decakilobits instead of kilobits. | |
138 | */ | |
139 | ||
a4fc5ed6 | 140 | static int |
c898261c | 141 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 142 | { |
cd9dde44 | 143 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
144 | } |
145 | ||
fe27d53e DA |
146 | static int |
147 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
148 | { | |
149 | return (max_link_clock * max_lanes * 8) / 10; | |
150 | } | |
151 | ||
c19de8eb | 152 | static enum drm_mode_status |
a4fc5ed6 KP |
153 | intel_dp_mode_valid(struct drm_connector *connector, |
154 | struct drm_display_mode *mode) | |
155 | { | |
df0e9248 | 156 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
157 | struct intel_connector *intel_connector = to_intel_connector(connector); |
158 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
159 | int target_clock = mode->clock; |
160 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
a4fc5ed6 | 161 | |
dd06f90e JN |
162 | if (is_edp(intel_dp) && fixed_mode) { |
163 | if (mode->hdisplay > fixed_mode->hdisplay) | |
7de56f43 ZY |
164 | return MODE_PANEL; |
165 | ||
dd06f90e | 166 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 167 | return MODE_PANEL; |
03afc4a2 DV |
168 | |
169 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
170 | } |
171 | ||
36008365 DV |
172 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
173 | max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); | |
174 | ||
175 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
176 | mode_rate = intel_dp_link_required(target_clock, 18); | |
177 | ||
178 | if (mode_rate > max_rate) | |
c4867936 | 179 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
180 | |
181 | if (mode->clock < 10000) | |
182 | return MODE_CLOCK_LOW; | |
183 | ||
0af78a2b DV |
184 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
185 | return MODE_H_ILLEGAL; | |
186 | ||
a4fc5ed6 KP |
187 | return MODE_OK; |
188 | } | |
189 | ||
190 | static uint32_t | |
191 | pack_aux(uint8_t *src, int src_bytes) | |
192 | { | |
193 | int i; | |
194 | uint32_t v = 0; | |
195 | ||
196 | if (src_bytes > 4) | |
197 | src_bytes = 4; | |
198 | for (i = 0; i < src_bytes; i++) | |
199 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
200 | return v; | |
201 | } | |
202 | ||
203 | static void | |
204 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
205 | { | |
206 | int i; | |
207 | if (dst_bytes > 4) | |
208 | dst_bytes = 4; | |
209 | for (i = 0; i < dst_bytes; i++) | |
210 | dst[i] = src >> ((3-i) * 8); | |
211 | } | |
212 | ||
fb0f8fbf KP |
213 | /* hrawclock is 1/4 the FSB frequency */ |
214 | static int | |
215 | intel_hrawclk(struct drm_device *dev) | |
216 | { | |
217 | struct drm_i915_private *dev_priv = dev->dev_private; | |
218 | uint32_t clkcfg; | |
219 | ||
9473c8f4 VP |
220 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
221 | if (IS_VALLEYVIEW(dev)) | |
222 | return 200; | |
223 | ||
fb0f8fbf KP |
224 | clkcfg = I915_READ(CLKCFG); |
225 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
226 | case CLKCFG_FSB_400: | |
227 | return 100; | |
228 | case CLKCFG_FSB_533: | |
229 | return 133; | |
230 | case CLKCFG_FSB_667: | |
231 | return 166; | |
232 | case CLKCFG_FSB_800: | |
233 | return 200; | |
234 | case CLKCFG_FSB_1067: | |
235 | return 266; | |
236 | case CLKCFG_FSB_1333: | |
237 | return 333; | |
238 | /* these two are just a guess; one of them might be right */ | |
239 | case CLKCFG_FSB_1600: | |
240 | case CLKCFG_FSB_1600_ALT: | |
241 | return 400; | |
242 | default: | |
243 | return 133; | |
244 | } | |
245 | } | |
246 | ||
bf13e81b JN |
247 | static void |
248 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
249 | struct intel_dp *intel_dp, | |
250 | struct edp_power_seq *out); | |
251 | static void | |
252 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
253 | struct intel_dp *intel_dp, | |
254 | struct edp_power_seq *out); | |
255 | ||
256 | static enum pipe | |
257 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
258 | { | |
259 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
260 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
261 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
262 | struct drm_i915_private *dev_priv = dev->dev_private; | |
263 | enum port port = intel_dig_port->port; | |
264 | enum pipe pipe; | |
265 | ||
266 | /* modeset should have pipe */ | |
267 | if (crtc) | |
268 | return to_intel_crtc(crtc)->pipe; | |
269 | ||
270 | /* init time, try to find a pipe with this port selected */ | |
271 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { | |
272 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & | |
273 | PANEL_PORT_SELECT_MASK; | |
274 | if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) | |
275 | return pipe; | |
276 | if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) | |
277 | return pipe; | |
278 | } | |
279 | ||
280 | /* shrug */ | |
281 | return PIPE_A; | |
282 | } | |
283 | ||
284 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) | |
285 | { | |
286 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
287 | ||
288 | if (HAS_PCH_SPLIT(dev)) | |
289 | return PCH_PP_CONTROL; | |
290 | else | |
291 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); | |
292 | } | |
293 | ||
294 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) | |
295 | { | |
296 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
297 | ||
298 | if (HAS_PCH_SPLIT(dev)) | |
299 | return PCH_PP_STATUS; | |
300 | else | |
301 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); | |
302 | } | |
303 | ||
4be73780 | 304 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 305 | { |
30add22d | 306 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
307 | struct drm_i915_private *dev_priv = dev->dev_private; |
308 | ||
bf13e81b | 309 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
310 | } |
311 | ||
4be73780 | 312 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 313 | { |
30add22d | 314 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
315 | struct drm_i915_private *dev_priv = dev->dev_private; |
316 | ||
bf13e81b | 317 | return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; |
ebf33b18 KP |
318 | } |
319 | ||
9b984dae KP |
320 | static void |
321 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
322 | { | |
30add22d | 323 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9b984dae | 324 | struct drm_i915_private *dev_priv = dev->dev_private; |
ebf33b18 | 325 | |
9b984dae KP |
326 | if (!is_edp(intel_dp)) |
327 | return; | |
453c5420 | 328 | |
4be73780 | 329 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
330 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
331 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
332 | I915_READ(_pp_stat_reg(intel_dp)), |
333 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
334 | } |
335 | } | |
336 | ||
9ee32fea DV |
337 | static uint32_t |
338 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
339 | { | |
340 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
341 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9ed35ab1 | 343 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
344 | uint32_t status; |
345 | bool done; | |
346 | ||
ef04f00d | 347 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 348 | if (has_aux_irq) |
b18ac466 | 349 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 350 | msecs_to_jiffies_timeout(10)); |
9ee32fea DV |
351 | else |
352 | done = wait_for_atomic(C, 10) == 0; | |
353 | if (!done) | |
354 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
355 | has_aux_irq); | |
356 | #undef C | |
357 | ||
358 | return status; | |
359 | } | |
360 | ||
ec5b01dd | 361 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 362 | { |
174edf1f PZ |
363 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
364 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
9ee32fea | 365 | |
ec5b01dd DL |
366 | /* |
367 | * The clock divider is based off the hrawclk, and would like to run at | |
368 | * 2MHz. So, take the hrawclk value and divide by 2 and use that | |
a4fc5ed6 | 369 | */ |
ec5b01dd DL |
370 | return index ? 0 : intel_hrawclk(dev) / 2; |
371 | } | |
372 | ||
373 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
374 | { | |
375 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
376 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
377 | ||
378 | if (index) | |
379 | return 0; | |
380 | ||
381 | if (intel_dig_port->port == PORT_A) { | |
382 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
b84a1cf8 | 383 | return 200; /* SNB & IVB eDP input clock at 400Mhz */ |
e3421a18 | 384 | else |
b84a1cf8 | 385 | return 225; /* eDP input clock at 450Mhz */ |
ec5b01dd DL |
386 | } else { |
387 | return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); | |
388 | } | |
389 | } | |
390 | ||
391 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
392 | { | |
393 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
394 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
395 | struct drm_i915_private *dev_priv = dev->dev_private; | |
396 | ||
397 | if (intel_dig_port->port == PORT_A) { | |
398 | if (index) | |
399 | return 0; | |
400 | return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); | |
2c55c336 JN |
401 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
402 | /* Workaround for non-ULT HSW */ | |
bc86625a CW |
403 | switch (index) { |
404 | case 0: return 63; | |
405 | case 1: return 72; | |
406 | default: return 0; | |
407 | } | |
ec5b01dd | 408 | } else { |
bc86625a | 409 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
2c55c336 | 410 | } |
b84a1cf8 RV |
411 | } |
412 | ||
ec5b01dd DL |
413 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
414 | { | |
415 | return index ? 0 : 100; | |
416 | } | |
417 | ||
b84a1cf8 RV |
418 | static int |
419 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
420 | uint8_t *send, int send_bytes, | |
421 | uint8_t *recv, int recv_size) | |
422 | { | |
423 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
424 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
425 | struct drm_i915_private *dev_priv = dev->dev_private; | |
426 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; | |
427 | uint32_t ch_data = ch_ctl + 4; | |
bc86625a | 428 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
429 | int i, ret, recv_bytes; |
430 | uint32_t status; | |
bc86625a | 431 | int try, precharge, clock = 0; |
4aeebd74 | 432 | bool has_aux_irq = true; |
a81a507d | 433 | uint32_t timeout; |
b84a1cf8 RV |
434 | |
435 | /* dp aux is extremely sensitive to irq latency, hence request the | |
436 | * lowest possible wakeup latency and so prevent the cpu from going into | |
437 | * deep sleep states. | |
438 | */ | |
439 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
440 | ||
441 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 442 | |
6b4e0a93 DV |
443 | if (IS_GEN6(dev)) |
444 | precharge = 3; | |
445 | else | |
446 | precharge = 5; | |
447 | ||
a81a507d BW |
448 | if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL) |
449 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; | |
450 | else | |
451 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
452 | ||
c67a470b PZ |
453 | intel_aux_display_runtime_get(dev_priv); |
454 | ||
11bee43e JB |
455 | /* Try to wait for any previous AUX channel activity */ |
456 | for (try = 0; try < 3; try++) { | |
ef04f00d | 457 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
458 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
459 | break; | |
460 | msleep(1); | |
461 | } | |
462 | ||
463 | if (try == 3) { | |
464 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
465 | I915_READ(ch_ctl)); | |
9ee32fea DV |
466 | ret = -EBUSY; |
467 | goto out; | |
4f7f7b7e CW |
468 | } |
469 | ||
46a5ae9f PZ |
470 | /* Only 5 data registers! */ |
471 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
472 | ret = -E2BIG; | |
473 | goto out; | |
474 | } | |
475 | ||
ec5b01dd | 476 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
bc86625a CW |
477 | /* Must try at least 3 times according to DP spec */ |
478 | for (try = 0; try < 5; try++) { | |
479 | /* Load the send data into the aux channel data registers */ | |
480 | for (i = 0; i < send_bytes; i += 4) | |
481 | I915_WRITE(ch_data + i, | |
482 | pack_aux(send + i, send_bytes - i)); | |
483 | ||
484 | /* Send the command and wait for it to complete */ | |
485 | I915_WRITE(ch_ctl, | |
486 | DP_AUX_CH_CTL_SEND_BUSY | | |
487 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | | |
a81a507d | 488 | timeout | |
bc86625a CW |
489 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
490 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
491 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
492 | DP_AUX_CH_CTL_DONE | | |
493 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
494 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
495 | ||
496 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
497 | ||
498 | /* Clear done status and any errors */ | |
499 | I915_WRITE(ch_ctl, | |
500 | status | | |
501 | DP_AUX_CH_CTL_DONE | | |
502 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
503 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
504 | ||
505 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
506 | DP_AUX_CH_CTL_RECEIVE_ERROR)) | |
507 | continue; | |
508 | if (status & DP_AUX_CH_CTL_DONE) | |
509 | break; | |
510 | } | |
4f7f7b7e | 511 | if (status & DP_AUX_CH_CTL_DONE) |
a4fc5ed6 KP |
512 | break; |
513 | } | |
514 | ||
a4fc5ed6 | 515 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 516 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
517 | ret = -EBUSY; |
518 | goto out; | |
a4fc5ed6 KP |
519 | } |
520 | ||
521 | /* Check for timeout or receive error. | |
522 | * Timeouts occur when the sink is not connected | |
523 | */ | |
a5b3da54 | 524 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 525 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
526 | ret = -EIO; |
527 | goto out; | |
a5b3da54 | 528 | } |
1ae8c0a5 KP |
529 | |
530 | /* Timeouts occur when the device isn't connected, so they're | |
531 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 532 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 533 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
534 | ret = -ETIMEDOUT; |
535 | goto out; | |
a4fc5ed6 KP |
536 | } |
537 | ||
538 | /* Unload any bytes sent back from the other side */ | |
539 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
540 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
541 | if (recv_bytes > recv_size) |
542 | recv_bytes = recv_size; | |
0206e353 | 543 | |
4f7f7b7e CW |
544 | for (i = 0; i < recv_bytes; i += 4) |
545 | unpack_aux(I915_READ(ch_data + i), | |
546 | recv + i, recv_bytes - i); | |
a4fc5ed6 | 547 | |
9ee32fea DV |
548 | ret = recv_bytes; |
549 | out: | |
550 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
c67a470b | 551 | intel_aux_display_runtime_put(dev_priv); |
9ee32fea DV |
552 | |
553 | return ret; | |
a4fc5ed6 KP |
554 | } |
555 | ||
556 | /* Write data to the aux channel in native mode */ | |
557 | static int | |
ea5b213a | 558 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
559 | uint16_t address, uint8_t *send, int send_bytes) |
560 | { | |
561 | int ret; | |
562 | uint8_t msg[20]; | |
563 | int msg_bytes; | |
564 | uint8_t ack; | |
565 | ||
46a5ae9f PZ |
566 | if (WARN_ON(send_bytes > 16)) |
567 | return -E2BIG; | |
568 | ||
9b984dae | 569 | intel_dp_check_edp(intel_dp); |
6b27f7f0 | 570 | msg[0] = DP_AUX_NATIVE_WRITE << 4; |
a4fc5ed6 | 571 | msg[1] = address >> 8; |
eebc863e | 572 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
573 | msg[3] = send_bytes - 1; |
574 | memcpy(&msg[4], send, send_bytes); | |
575 | msg_bytes = send_bytes + 4; | |
576 | for (;;) { | |
ea5b213a | 577 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
578 | if (ret < 0) |
579 | return ret; | |
6b27f7f0 TR |
580 | ack >>= 4; |
581 | if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) | |
a4fc5ed6 | 582 | break; |
6b27f7f0 | 583 | else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) |
a4fc5ed6 KP |
584 | udelay(100); |
585 | else | |
a5b3da54 | 586 | return -EIO; |
a4fc5ed6 KP |
587 | } |
588 | return send_bytes; | |
589 | } | |
590 | ||
591 | /* Write a single byte to the aux channel in native mode */ | |
592 | static int | |
ea5b213a | 593 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
594 | uint16_t address, uint8_t byte) |
595 | { | |
ea5b213a | 596 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
597 | } |
598 | ||
599 | /* read bytes from a native aux channel */ | |
600 | static int | |
ea5b213a | 601 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
602 | uint16_t address, uint8_t *recv, int recv_bytes) |
603 | { | |
604 | uint8_t msg[4]; | |
605 | int msg_bytes; | |
606 | uint8_t reply[20]; | |
607 | int reply_bytes; | |
608 | uint8_t ack; | |
609 | int ret; | |
610 | ||
46a5ae9f PZ |
611 | if (WARN_ON(recv_bytes > 19)) |
612 | return -E2BIG; | |
613 | ||
9b984dae | 614 | intel_dp_check_edp(intel_dp); |
6b27f7f0 | 615 | msg[0] = DP_AUX_NATIVE_READ << 4; |
a4fc5ed6 KP |
616 | msg[1] = address >> 8; |
617 | msg[2] = address & 0xff; | |
618 | msg[3] = recv_bytes - 1; | |
619 | ||
620 | msg_bytes = 4; | |
621 | reply_bytes = recv_bytes + 1; | |
622 | ||
623 | for (;;) { | |
ea5b213a | 624 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 625 | reply, reply_bytes); |
a5b3da54 KP |
626 | if (ret == 0) |
627 | return -EPROTO; | |
628 | if (ret < 0) | |
a4fc5ed6 | 629 | return ret; |
6b27f7f0 TR |
630 | ack = reply[0] >> 4; |
631 | if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) { | |
a4fc5ed6 KP |
632 | memcpy(recv, reply + 1, ret - 1); |
633 | return ret - 1; | |
634 | } | |
6b27f7f0 | 635 | else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) |
a4fc5ed6 KP |
636 | udelay(100); |
637 | else | |
a5b3da54 | 638 | return -EIO; |
a4fc5ed6 KP |
639 | } |
640 | } | |
641 | ||
642 | static int | |
ab2c0672 DA |
643 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
644 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 645 | { |
ab2c0672 | 646 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
647 | struct intel_dp *intel_dp = container_of(adapter, |
648 | struct intel_dp, | |
649 | adapter); | |
ab2c0672 DA |
650 | uint16_t address = algo_data->address; |
651 | uint8_t msg[5]; | |
652 | uint8_t reply[2]; | |
8316f337 | 653 | unsigned retry; |
ab2c0672 DA |
654 | int msg_bytes; |
655 | int reply_bytes; | |
656 | int ret; | |
657 | ||
4be73780 | 658 | edp_panel_vdd_on(intel_dp); |
9b984dae | 659 | intel_dp_check_edp(intel_dp); |
ab2c0672 DA |
660 | /* Set up the command byte */ |
661 | if (mode & MODE_I2C_READ) | |
6b27f7f0 | 662 | msg[0] = DP_AUX_I2C_READ << 4; |
ab2c0672 | 663 | else |
6b27f7f0 | 664 | msg[0] = DP_AUX_I2C_WRITE << 4; |
ab2c0672 DA |
665 | |
666 | if (!(mode & MODE_I2C_STOP)) | |
6b27f7f0 | 667 | msg[0] |= DP_AUX_I2C_MOT << 4; |
a4fc5ed6 | 668 | |
ab2c0672 DA |
669 | msg[1] = address >> 8; |
670 | msg[2] = address; | |
671 | ||
672 | switch (mode) { | |
673 | case MODE_I2C_WRITE: | |
674 | msg[3] = 0; | |
675 | msg[4] = write_byte; | |
676 | msg_bytes = 5; | |
677 | reply_bytes = 1; | |
678 | break; | |
679 | case MODE_I2C_READ: | |
680 | msg[3] = 0; | |
681 | msg_bytes = 4; | |
682 | reply_bytes = 2; | |
683 | break; | |
684 | default: | |
685 | msg_bytes = 3; | |
686 | reply_bytes = 1; | |
687 | break; | |
688 | } | |
689 | ||
58c67ce9 JN |
690 | /* |
691 | * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is | |
692 | * required to retry at least seven times upon receiving AUX_DEFER | |
693 | * before giving up the AUX transaction. | |
694 | */ | |
695 | for (retry = 0; retry < 7; retry++) { | |
8316f337 DF |
696 | ret = intel_dp_aux_ch(intel_dp, |
697 | msg, msg_bytes, | |
698 | reply, reply_bytes); | |
ab2c0672 | 699 | if (ret < 0) { |
3ff99164 | 700 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
8a5e6aeb | 701 | goto out; |
ab2c0672 | 702 | } |
8316f337 | 703 | |
6b27f7f0 TR |
704 | switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) { |
705 | case DP_AUX_NATIVE_REPLY_ACK: | |
8316f337 DF |
706 | /* I2C-over-AUX Reply field is only valid |
707 | * when paired with AUX ACK. | |
708 | */ | |
709 | break; | |
6b27f7f0 | 710 | case DP_AUX_NATIVE_REPLY_NACK: |
8316f337 | 711 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
8a5e6aeb PZ |
712 | ret = -EREMOTEIO; |
713 | goto out; | |
6b27f7f0 | 714 | case DP_AUX_NATIVE_REPLY_DEFER: |
8d16f258 JN |
715 | /* |
716 | * For now, just give more slack to branch devices. We | |
717 | * could check the DPCD for I2C bit rate capabilities, | |
718 | * and if available, adjust the interval. We could also | |
719 | * be more careful with DP-to-Legacy adapters where a | |
720 | * long legacy cable may force very low I2C bit rates. | |
721 | */ | |
722 | if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
723 | DP_DWN_STRM_PORT_PRESENT) | |
724 | usleep_range(500, 600); | |
725 | else | |
726 | usleep_range(300, 400); | |
8316f337 DF |
727 | continue; |
728 | default: | |
729 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", | |
730 | reply[0]); | |
8a5e6aeb PZ |
731 | ret = -EREMOTEIO; |
732 | goto out; | |
8316f337 DF |
733 | } |
734 | ||
6b27f7f0 TR |
735 | switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) { |
736 | case DP_AUX_I2C_REPLY_ACK: | |
ab2c0672 DA |
737 | if (mode == MODE_I2C_READ) { |
738 | *read_byte = reply[1]; | |
739 | } | |
8a5e6aeb PZ |
740 | ret = reply_bytes - 1; |
741 | goto out; | |
6b27f7f0 | 742 | case DP_AUX_I2C_REPLY_NACK: |
8316f337 | 743 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
8a5e6aeb PZ |
744 | ret = -EREMOTEIO; |
745 | goto out; | |
6b27f7f0 | 746 | case DP_AUX_I2C_REPLY_DEFER: |
8316f337 | 747 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
ab2c0672 DA |
748 | udelay(100); |
749 | break; | |
750 | default: | |
8316f337 | 751 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
8a5e6aeb PZ |
752 | ret = -EREMOTEIO; |
753 | goto out; | |
ab2c0672 DA |
754 | } |
755 | } | |
8316f337 DF |
756 | |
757 | DRM_ERROR("too many retries, giving up\n"); | |
8a5e6aeb PZ |
758 | ret = -EREMOTEIO; |
759 | ||
760 | out: | |
4be73780 | 761 | edp_panel_vdd_off(intel_dp, false); |
8a5e6aeb | 762 | return ret; |
a4fc5ed6 KP |
763 | } |
764 | ||
765 | static int | |
ea5b213a | 766 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 767 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 768 | { |
0b5c541b KP |
769 | int ret; |
770 | ||
d54e9d28 | 771 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
772 | intel_dp->algo.running = false; |
773 | intel_dp->algo.address = 0; | |
774 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
775 | ||
0206e353 | 776 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
ea5b213a CW |
777 | intel_dp->adapter.owner = THIS_MODULE; |
778 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
0206e353 | 779 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
ea5b213a CW |
780 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
781 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
5bdebb18 | 782 | intel_dp->adapter.dev.parent = intel_connector->base.kdev; |
ea5b213a | 783 | |
0b5c541b | 784 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); |
0b5c541b | 785 | return ret; |
a4fc5ed6 KP |
786 | } |
787 | ||
c6bb3538 DV |
788 | static void |
789 | intel_dp_set_clock(struct intel_encoder *encoder, | |
790 | struct intel_crtc_config *pipe_config, int link_bw) | |
791 | { | |
792 | struct drm_device *dev = encoder->base.dev; | |
9dd4ffdf CML |
793 | const struct dp_link_dpll *divisor = NULL; |
794 | int i, count = 0; | |
c6bb3538 DV |
795 | |
796 | if (IS_G4X(dev)) { | |
9dd4ffdf CML |
797 | divisor = gen4_dpll; |
798 | count = ARRAY_SIZE(gen4_dpll); | |
c6bb3538 DV |
799 | } else if (IS_HASWELL(dev)) { |
800 | /* Haswell has special-purpose DP DDI clocks. */ | |
801 | } else if (HAS_PCH_SPLIT(dev)) { | |
9dd4ffdf CML |
802 | divisor = pch_dpll; |
803 | count = ARRAY_SIZE(pch_dpll); | |
c6bb3538 | 804 | } else if (IS_VALLEYVIEW(dev)) { |
65ce4bf5 CML |
805 | divisor = vlv_dpll; |
806 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 807 | } |
9dd4ffdf CML |
808 | |
809 | if (divisor && count) { | |
810 | for (i = 0; i < count; i++) { | |
811 | if (link_bw == divisor[i].link_bw) { | |
812 | pipe_config->dpll = divisor[i].dpll; | |
813 | pipe_config->clock_set = true; | |
814 | break; | |
815 | } | |
816 | } | |
c6bb3538 DV |
817 | } |
818 | } | |
819 | ||
00c09d70 | 820 | bool |
5bfe2ac0 DV |
821 | intel_dp_compute_config(struct intel_encoder *encoder, |
822 | struct intel_crtc_config *pipe_config) | |
a4fc5ed6 | 823 | { |
5bfe2ac0 | 824 | struct drm_device *dev = encoder->base.dev; |
36008365 | 825 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfe2ac0 | 826 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
5bfe2ac0 | 827 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 828 | enum port port = dp_to_dig_port(intel_dp)->port; |
2dd24552 | 829 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
dd06f90e | 830 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
a4fc5ed6 | 831 | int lane_count, clock; |
397fe157 | 832 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
06ea66b6 TP |
833 | /* Conveniently, the link BW constants become indices with a shift...*/ |
834 | int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; | |
083f9560 | 835 | int bpp, mode_rate; |
06ea66b6 | 836 | static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; |
ff9a6750 | 837 | int link_avail, link_clock; |
a4fc5ed6 | 838 | |
bc7d38a4 | 839 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
5bfe2ac0 DV |
840 | pipe_config->has_pch_encoder = true; |
841 | ||
03afc4a2 | 842 | pipe_config->has_dp_encoder = true; |
a4fc5ed6 | 843 | |
dd06f90e JN |
844 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
845 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
846 | adjusted_mode); | |
2dd24552 JB |
847 | if (!HAS_PCH_SPLIT(dev)) |
848 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
849 | intel_connector->panel.fitting_mode); | |
850 | else | |
b074cec8 JB |
851 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
852 | intel_connector->panel.fitting_mode); | |
0d3a1bee ZY |
853 | } |
854 | ||
cb1793ce | 855 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
856 | return false; |
857 | ||
083f9560 DV |
858 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
859 | "max bw %02x pixel clock %iKHz\n", | |
241bfc38 DL |
860 | max_lane_count, bws[max_clock], |
861 | adjusted_mode->crtc_clock); | |
083f9560 | 862 | |
36008365 DV |
863 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
864 | * bpc in between. */ | |
3e7ca985 | 865 | bpp = pipe_config->pipe_bpp; |
6da7f10d JN |
866 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
867 | dev_priv->vbt.edp_bpp < bpp) { | |
7984211e ID |
868 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
869 | dev_priv->vbt.edp_bpp); | |
6da7f10d | 870 | bpp = dev_priv->vbt.edp_bpp; |
7984211e | 871 | } |
657445fe | 872 | |
36008365 | 873 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
874 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
875 | bpp); | |
36008365 DV |
876 | |
877 | for (clock = 0; clock <= max_clock; clock++) { | |
878 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { | |
879 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); | |
880 | link_avail = intel_dp_max_data_rate(link_clock, | |
881 | lane_count); | |
882 | ||
883 | if (mode_rate <= link_avail) { | |
884 | goto found; | |
885 | } | |
886 | } | |
887 | } | |
888 | } | |
c4867936 | 889 | |
36008365 | 890 | return false; |
3685a8f3 | 891 | |
36008365 | 892 | found: |
55bc60db VS |
893 | if (intel_dp->color_range_auto) { |
894 | /* | |
895 | * See: | |
896 | * CEA-861-E - 5.1 Default Encoding Parameters | |
897 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
898 | */ | |
18316c8c | 899 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
55bc60db VS |
900 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
901 | else | |
902 | intel_dp->color_range = 0; | |
903 | } | |
904 | ||
3685a8f3 | 905 | if (intel_dp->color_range) |
50f3b016 | 906 | pipe_config->limited_color_range = true; |
a4fc5ed6 | 907 | |
36008365 DV |
908 | intel_dp->link_bw = bws[clock]; |
909 | intel_dp->lane_count = lane_count; | |
657445fe | 910 | pipe_config->pipe_bpp = bpp; |
ff9a6750 | 911 | pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
a4fc5ed6 | 912 | |
36008365 DV |
913 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
914 | intel_dp->link_bw, intel_dp->lane_count, | |
ff9a6750 | 915 | pipe_config->port_clock, bpp); |
36008365 DV |
916 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
917 | mode_rate, link_avail); | |
a4fc5ed6 | 918 | |
03afc4a2 | 919 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
920 | adjusted_mode->crtc_clock, |
921 | pipe_config->port_clock, | |
03afc4a2 | 922 | &pipe_config->dp_m_n); |
9d1a455b | 923 | |
c6bb3538 DV |
924 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); |
925 | ||
03afc4a2 | 926 | return true; |
a4fc5ed6 KP |
927 | } |
928 | ||
7c62a164 | 929 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
ea9b6006 | 930 | { |
7c62a164 DV |
931 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
932 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); | |
933 | struct drm_device *dev = crtc->base.dev; | |
ea9b6006 DV |
934 | struct drm_i915_private *dev_priv = dev->dev_private; |
935 | u32 dpa_ctl; | |
936 | ||
ff9a6750 | 937 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); |
ea9b6006 DV |
938 | dpa_ctl = I915_READ(DP_A); |
939 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
940 | ||
ff9a6750 | 941 | if (crtc->config.port_clock == 162000) { |
1ce17038 DV |
942 | /* For a long time we've carried around a ILK-DevA w/a for the |
943 | * 160MHz clock. If we're really unlucky, it's still required. | |
944 | */ | |
945 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); | |
ea9b6006 | 946 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
7c62a164 | 947 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
ea9b6006 DV |
948 | } else { |
949 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
7c62a164 | 950 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
ea9b6006 | 951 | } |
1ce17038 | 952 | |
ea9b6006 DV |
953 | I915_WRITE(DP_A, dpa_ctl); |
954 | ||
955 | POSTING_READ(DP_A); | |
956 | udelay(500); | |
957 | } | |
958 | ||
b934223d | 959 | static void intel_dp_mode_set(struct intel_encoder *encoder) |
a4fc5ed6 | 960 | { |
b934223d | 961 | struct drm_device *dev = encoder->base.dev; |
417e822d | 962 | struct drm_i915_private *dev_priv = dev->dev_private; |
b934223d | 963 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 964 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d DV |
965 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
966 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
a4fc5ed6 | 967 | |
417e822d | 968 | /* |
1a2eb460 | 969 | * There are four kinds of DP registers: |
417e822d KP |
970 | * |
971 | * IBX PCH | |
1a2eb460 KP |
972 | * SNB CPU |
973 | * IVB CPU | |
417e822d KP |
974 | * CPT PCH |
975 | * | |
976 | * IBX PCH and CPU are the same for almost everything, | |
977 | * except that the CPU DP PLL is configured in this | |
978 | * register | |
979 | * | |
980 | * CPT PCH is quite different, having many bits moved | |
981 | * to the TRANS_DP_CTL register instead. That | |
982 | * configuration happens (oddly) in ironlake_pch_enable | |
983 | */ | |
9c9e7927 | 984 | |
417e822d KP |
985 | /* Preserve the BIOS-computed detected bit. This is |
986 | * supposed to be read-only. | |
987 | */ | |
988 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 989 | |
417e822d | 990 | /* Handle DP bits in common between all three register formats */ |
417e822d | 991 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
17aa6be9 | 992 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
a4fc5ed6 | 993 | |
e0dac65e WF |
994 | if (intel_dp->has_audio) { |
995 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", | |
7c62a164 | 996 | pipe_name(crtc->pipe)); |
ea5b213a | 997 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
b934223d | 998 | intel_write_eld(&encoder->base, adjusted_mode); |
e0dac65e | 999 | } |
247d89f6 | 1000 | |
417e822d | 1001 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 1002 | |
bc7d38a4 | 1003 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
1a2eb460 KP |
1004 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1005 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1006 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1007 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1008 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
1009 | ||
6aba5b6c | 1010 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
1011 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1012 | ||
7c62a164 | 1013 | intel_dp->DP |= crtc->pipe << 29; |
bc7d38a4 | 1014 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
b2634017 | 1015 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) |
3685a8f3 | 1016 | intel_dp->DP |= intel_dp->color_range; |
417e822d KP |
1017 | |
1018 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
1019 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1020 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1021 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1022 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
1023 | ||
6aba5b6c | 1024 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
1025 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1026 | ||
7c62a164 | 1027 | if (crtc->pipe == 1) |
417e822d | 1028 | intel_dp->DP |= DP_PIPEB_SELECT; |
417e822d KP |
1029 | } else { |
1030 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
32f9d658 | 1031 | } |
ea9b6006 | 1032 | |
bc7d38a4 | 1033 | if (port == PORT_A && !IS_VALLEYVIEW(dev)) |
7c62a164 | 1034 | ironlake_set_pll_cpu_edp(intel_dp); |
a4fc5ed6 KP |
1035 | } |
1036 | ||
ffd6749d PZ |
1037 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1038 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 1039 | |
1a5ef5b7 PZ |
1040 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1041 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 1042 | |
ffd6749d PZ |
1043 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1044 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 1045 | |
4be73780 | 1046 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
1047 | u32 mask, |
1048 | u32 value) | |
bd943159 | 1049 | { |
30add22d | 1050 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
99ea7127 | 1051 | struct drm_i915_private *dev_priv = dev->dev_private; |
453c5420 JB |
1052 | u32 pp_stat_reg, pp_ctrl_reg; |
1053 | ||
bf13e81b JN |
1054 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1055 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 1056 | |
99ea7127 | 1057 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
1058 | mask, value, |
1059 | I915_READ(pp_stat_reg), | |
1060 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1061 | |
453c5420 | 1062 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
99ea7127 | 1063 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
1064 | I915_READ(pp_stat_reg), |
1065 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1066 | } |
54c136d4 CW |
1067 | |
1068 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 1069 | } |
32ce697c | 1070 | |
4be73780 | 1071 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
1072 | { |
1073 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 1074 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
1075 | } |
1076 | ||
4be73780 | 1077 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
1078 | { |
1079 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 1080 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
1081 | } |
1082 | ||
4be73780 | 1083 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 KP |
1084 | { |
1085 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); | |
dce56b3c PZ |
1086 | |
1087 | /* When we disable the VDD override bit last we have to do the manual | |
1088 | * wait. */ | |
1089 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, | |
1090 | intel_dp->panel_power_cycle_delay); | |
1091 | ||
4be73780 | 1092 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
1093 | } |
1094 | ||
4be73780 | 1095 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
1096 | { |
1097 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
1098 | intel_dp->backlight_on_delay); | |
1099 | } | |
1100 | ||
4be73780 | 1101 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
1102 | { |
1103 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
1104 | intel_dp->backlight_off_delay); | |
1105 | } | |
99ea7127 | 1106 | |
832dd3c1 KP |
1107 | /* Read the current pp_control value, unlocking the register if it |
1108 | * is locked | |
1109 | */ | |
1110 | ||
453c5420 | 1111 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 1112 | { |
453c5420 JB |
1113 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1115 | u32 control; | |
832dd3c1 | 1116 | |
bf13e81b | 1117 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
832dd3c1 KP |
1118 | control &= ~PANEL_UNLOCK_MASK; |
1119 | control |= PANEL_UNLOCK_REGS; | |
1120 | return control; | |
bd943159 KP |
1121 | } |
1122 | ||
4be73780 | 1123 | static void edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 1124 | { |
30add22d | 1125 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5d613501 JB |
1126 | struct drm_i915_private *dev_priv = dev->dev_private; |
1127 | u32 pp; | |
453c5420 | 1128 | u32 pp_stat_reg, pp_ctrl_reg; |
5d613501 | 1129 | |
97af61f5 KP |
1130 | if (!is_edp(intel_dp)) |
1131 | return; | |
5d613501 | 1132 | |
bd943159 KP |
1133 | WARN(intel_dp->want_panel_vdd, |
1134 | "eDP VDD already requested on\n"); | |
1135 | ||
1136 | intel_dp->want_panel_vdd = true; | |
99ea7127 | 1137 | |
4be73780 | 1138 | if (edp_have_panel_vdd(intel_dp)) |
bd943159 | 1139 | return; |
b0665d57 | 1140 | |
e9cb81a2 PZ |
1141 | intel_runtime_pm_get(dev_priv); |
1142 | ||
b0665d57 | 1143 | DRM_DEBUG_KMS("Turning eDP VDD on\n"); |
bd943159 | 1144 | |
4be73780 DV |
1145 | if (!edp_have_panel_power(intel_dp)) |
1146 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 1147 | |
453c5420 | 1148 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 1149 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 1150 | |
bf13e81b JN |
1151 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1152 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
1153 | |
1154 | I915_WRITE(pp_ctrl_reg, pp); | |
1155 | POSTING_READ(pp_ctrl_reg); | |
1156 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1157 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
1158 | /* |
1159 | * If the panel wasn't on, delay before accessing aux channel | |
1160 | */ | |
4be73780 | 1161 | if (!edp_have_panel_power(intel_dp)) { |
bd943159 | 1162 | DRM_DEBUG_KMS("eDP was not running\n"); |
f01eca2e | 1163 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 1164 | } |
5d613501 JB |
1165 | } |
1166 | ||
4be73780 | 1167 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 1168 | { |
30add22d | 1169 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5d613501 JB |
1170 | struct drm_i915_private *dev_priv = dev->dev_private; |
1171 | u32 pp; | |
453c5420 | 1172 | u32 pp_stat_reg, pp_ctrl_reg; |
5d613501 | 1173 | |
a0e99e68 DV |
1174 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
1175 | ||
4be73780 | 1176 | if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { |
b0665d57 PZ |
1177 | DRM_DEBUG_KMS("Turning eDP VDD off\n"); |
1178 | ||
453c5420 | 1179 | pp = ironlake_get_pp_control(intel_dp); |
bd943159 | 1180 | pp &= ~EDP_FORCE_VDD; |
bd943159 | 1181 | |
9f08ef59 PZ |
1182 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1183 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
453c5420 JB |
1184 | |
1185 | I915_WRITE(pp_ctrl_reg, pp); | |
1186 | POSTING_READ(pp_ctrl_reg); | |
99ea7127 | 1187 | |
453c5420 JB |
1188 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1189 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1190 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
90791a5c PZ |
1191 | |
1192 | if ((pp & POWER_TARGET_ON) == 0) | |
dce56b3c | 1193 | intel_dp->last_power_cycle = jiffies; |
e9cb81a2 PZ |
1194 | |
1195 | intel_runtime_pm_put(dev_priv); | |
bd943159 KP |
1196 | } |
1197 | } | |
5d613501 | 1198 | |
4be73780 | 1199 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
1200 | { |
1201 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
1202 | struct intel_dp, panel_vdd_work); | |
30add22d | 1203 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bd943159 | 1204 | |
627f7675 | 1205 | mutex_lock(&dev->mode_config.mutex); |
4be73780 | 1206 | edp_panel_vdd_off_sync(intel_dp); |
627f7675 | 1207 | mutex_unlock(&dev->mode_config.mutex); |
bd943159 KP |
1208 | } |
1209 | ||
4be73780 | 1210 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 1211 | { |
97af61f5 KP |
1212 | if (!is_edp(intel_dp)) |
1213 | return; | |
5d613501 | 1214 | |
bd943159 | 1215 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
f2e8b18a | 1216 | |
bd943159 KP |
1217 | intel_dp->want_panel_vdd = false; |
1218 | ||
1219 | if (sync) { | |
4be73780 | 1220 | edp_panel_vdd_off_sync(intel_dp); |
bd943159 KP |
1221 | } else { |
1222 | /* | |
1223 | * Queue the timer to fire a long | |
1224 | * time from now (relative to the power down delay) | |
1225 | * to keep the panel power up across a sequence of operations | |
1226 | */ | |
1227 | schedule_delayed_work(&intel_dp->panel_vdd_work, | |
1228 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
1229 | } | |
5d613501 JB |
1230 | } |
1231 | ||
4be73780 | 1232 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 1233 | { |
30add22d | 1234 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1235 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1236 | u32 pp; |
453c5420 | 1237 | u32 pp_ctrl_reg; |
9934c132 | 1238 | |
97af61f5 | 1239 | if (!is_edp(intel_dp)) |
bd943159 | 1240 | return; |
99ea7127 KP |
1241 | |
1242 | DRM_DEBUG_KMS("Turn eDP power on\n"); | |
1243 | ||
4be73780 | 1244 | if (edp_have_panel_power(intel_dp)) { |
99ea7127 | 1245 | DRM_DEBUG_KMS("eDP power already on\n"); |
7d639f35 | 1246 | return; |
99ea7127 | 1247 | } |
9934c132 | 1248 | |
4be73780 | 1249 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 1250 | |
bf13e81b | 1251 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 1252 | pp = ironlake_get_pp_control(intel_dp); |
05ce1a49 KP |
1253 | if (IS_GEN5(dev)) { |
1254 | /* ILK workaround: disable reset around power sequence */ | |
1255 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
1256 | I915_WRITE(pp_ctrl_reg, pp); |
1257 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1258 | } |
37c6c9b0 | 1259 | |
1c0ae80a | 1260 | pp |= POWER_TARGET_ON; |
99ea7127 KP |
1261 | if (!IS_GEN5(dev)) |
1262 | pp |= PANEL_POWER_RESET; | |
1263 | ||
453c5420 JB |
1264 | I915_WRITE(pp_ctrl_reg, pp); |
1265 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1266 | |
4be73780 | 1267 | wait_panel_on(intel_dp); |
dce56b3c | 1268 | intel_dp->last_power_on = jiffies; |
9934c132 | 1269 | |
05ce1a49 KP |
1270 | if (IS_GEN5(dev)) { |
1271 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
bf13e81b JN |
1272 | I915_WRITE(pp_ctrl_reg, pp); |
1273 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1274 | } |
9934c132 JB |
1275 | } |
1276 | ||
4be73780 | 1277 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
9934c132 | 1278 | { |
30add22d | 1279 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1280 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1281 | u32 pp; |
453c5420 | 1282 | u32 pp_ctrl_reg; |
9934c132 | 1283 | |
97af61f5 KP |
1284 | if (!is_edp(intel_dp)) |
1285 | return; | |
37c6c9b0 | 1286 | |
99ea7127 | 1287 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
37c6c9b0 | 1288 | |
4be73780 | 1289 | edp_wait_backlight_off(intel_dp); |
dce56b3c | 1290 | |
453c5420 | 1291 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
1292 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
1293 | * panels get very unhappy and cease to work. */ | |
dff392db | 1294 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE); |
453c5420 | 1295 | |
bf13e81b | 1296 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
1297 | |
1298 | I915_WRITE(pp_ctrl_reg, pp); | |
1299 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1300 | |
dce56b3c | 1301 | intel_dp->last_power_cycle = jiffies; |
4be73780 | 1302 | wait_panel_off(intel_dp); |
9934c132 JB |
1303 | } |
1304 | ||
4be73780 | 1305 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
32f9d658 | 1306 | { |
da63a9f2 PZ |
1307 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1308 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
32f9d658 ZW |
1309 | struct drm_i915_private *dev_priv = dev->dev_private; |
1310 | u32 pp; | |
453c5420 | 1311 | u32 pp_ctrl_reg; |
32f9d658 | 1312 | |
f01eca2e KP |
1313 | if (!is_edp(intel_dp)) |
1314 | return; | |
1315 | ||
28c97730 | 1316 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
1317 | /* |
1318 | * If we enable the backlight right away following a panel power | |
1319 | * on, we may see slight flicker as the panel syncs with the eDP | |
1320 | * link. So delay a bit to make sure the image is solid before | |
1321 | * allowing it to appear. | |
1322 | */ | |
4be73780 | 1323 | wait_backlight_on(intel_dp); |
453c5420 | 1324 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 1325 | pp |= EDP_BLC_ENABLE; |
453c5420 | 1326 | |
bf13e81b | 1327 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
1328 | |
1329 | I915_WRITE(pp_ctrl_reg, pp); | |
1330 | POSTING_READ(pp_ctrl_reg); | |
035aa3de | 1331 | |
752aa88a | 1332 | intel_panel_enable_backlight(intel_dp->attached_connector); |
32f9d658 ZW |
1333 | } |
1334 | ||
4be73780 | 1335 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
32f9d658 | 1336 | { |
30add22d | 1337 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
32f9d658 ZW |
1338 | struct drm_i915_private *dev_priv = dev->dev_private; |
1339 | u32 pp; | |
453c5420 | 1340 | u32 pp_ctrl_reg; |
32f9d658 | 1341 | |
f01eca2e KP |
1342 | if (!is_edp(intel_dp)) |
1343 | return; | |
1344 | ||
752aa88a | 1345 | intel_panel_disable_backlight(intel_dp->attached_connector); |
035aa3de | 1346 | |
28c97730 | 1347 | DRM_DEBUG_KMS("\n"); |
453c5420 | 1348 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 1349 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 1350 | |
bf13e81b | 1351 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
1352 | |
1353 | I915_WRITE(pp_ctrl_reg, pp); | |
1354 | POSTING_READ(pp_ctrl_reg); | |
dce56b3c | 1355 | intel_dp->last_backlight_off = jiffies; |
32f9d658 | 1356 | } |
a4fc5ed6 | 1357 | |
2bd2ad64 | 1358 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
d240f20f | 1359 | { |
da63a9f2 PZ |
1360 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1361 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
1362 | struct drm_device *dev = crtc->dev; | |
d240f20f JB |
1363 | struct drm_i915_private *dev_priv = dev->dev_private; |
1364 | u32 dpa_ctl; | |
1365 | ||
2bd2ad64 DV |
1366 | assert_pipe_disabled(dev_priv, |
1367 | to_intel_crtc(crtc)->pipe); | |
1368 | ||
d240f20f JB |
1369 | DRM_DEBUG_KMS("\n"); |
1370 | dpa_ctl = I915_READ(DP_A); | |
0767935e DV |
1371 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
1372 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); | |
1373 | ||
1374 | /* We don't adjust intel_dp->DP while tearing down the link, to | |
1375 | * facilitate link retraining (e.g. after hotplug). Hence clear all | |
1376 | * enable bits here to ensure that we don't enable too much. */ | |
1377 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); | |
1378 | intel_dp->DP |= DP_PLL_ENABLE; | |
1379 | I915_WRITE(DP_A, intel_dp->DP); | |
298b0b39 JB |
1380 | POSTING_READ(DP_A); |
1381 | udelay(200); | |
d240f20f JB |
1382 | } |
1383 | ||
2bd2ad64 | 1384 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 1385 | { |
da63a9f2 PZ |
1386 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1387 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
1388 | struct drm_device *dev = crtc->dev; | |
d240f20f JB |
1389 | struct drm_i915_private *dev_priv = dev->dev_private; |
1390 | u32 dpa_ctl; | |
1391 | ||
2bd2ad64 DV |
1392 | assert_pipe_disabled(dev_priv, |
1393 | to_intel_crtc(crtc)->pipe); | |
1394 | ||
d240f20f | 1395 | dpa_ctl = I915_READ(DP_A); |
0767935e DV |
1396 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
1397 | "dp pll off, should be on\n"); | |
1398 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); | |
1399 | ||
1400 | /* We can't rely on the value tracked for the DP register in | |
1401 | * intel_dp->DP because link_down must not change that (otherwise link | |
1402 | * re-training will fail. */ | |
298b0b39 | 1403 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 1404 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 1405 | POSTING_READ(DP_A); |
d240f20f JB |
1406 | udelay(200); |
1407 | } | |
1408 | ||
c7ad3810 | 1409 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 1410 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
1411 | { |
1412 | int ret, i; | |
1413 | ||
1414 | /* Should have a valid DPCD by this point */ | |
1415 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
1416 | return; | |
1417 | ||
1418 | if (mode != DRM_MODE_DPMS_ON) { | |
1419 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, | |
1420 | DP_SET_POWER_D3); | |
1421 | if (ret != 1) | |
1422 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
1423 | } else { | |
1424 | /* | |
1425 | * When turning on, we need to retry for 1ms to give the sink | |
1426 | * time to wake up. | |
1427 | */ | |
1428 | for (i = 0; i < 3; i++) { | |
1429 | ret = intel_dp_aux_native_write_1(intel_dp, | |
1430 | DP_SET_POWER, | |
1431 | DP_SET_POWER_D0); | |
1432 | if (ret == 1) | |
1433 | break; | |
1434 | msleep(1); | |
1435 | } | |
1436 | } | |
1437 | } | |
1438 | ||
19d8fe15 DV |
1439 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
1440 | enum pipe *pipe) | |
d240f20f | 1441 | { |
19d8fe15 | 1442 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1443 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 DV |
1444 | struct drm_device *dev = encoder->base.dev; |
1445 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1446 | u32 tmp = I915_READ(intel_dp->output_reg); | |
1447 | ||
1448 | if (!(tmp & DP_PORT_EN)) | |
1449 | return false; | |
1450 | ||
bc7d38a4 | 1451 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
19d8fe15 | 1452 | *pipe = PORT_TO_PIPE_CPT(tmp); |
bc7d38a4 | 1453 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
19d8fe15 DV |
1454 | *pipe = PORT_TO_PIPE(tmp); |
1455 | } else { | |
1456 | u32 trans_sel; | |
1457 | u32 trans_dp; | |
1458 | int i; | |
1459 | ||
1460 | switch (intel_dp->output_reg) { | |
1461 | case PCH_DP_B: | |
1462 | trans_sel = TRANS_DP_PORT_SEL_B; | |
1463 | break; | |
1464 | case PCH_DP_C: | |
1465 | trans_sel = TRANS_DP_PORT_SEL_C; | |
1466 | break; | |
1467 | case PCH_DP_D: | |
1468 | trans_sel = TRANS_DP_PORT_SEL_D; | |
1469 | break; | |
1470 | default: | |
1471 | return true; | |
1472 | } | |
1473 | ||
1474 | for_each_pipe(i) { | |
1475 | trans_dp = I915_READ(TRANS_DP_CTL(i)); | |
1476 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { | |
1477 | *pipe = i; | |
1478 | return true; | |
1479 | } | |
1480 | } | |
19d8fe15 | 1481 | |
4a0833ec DV |
1482 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
1483 | intel_dp->output_reg); | |
1484 | } | |
d240f20f | 1485 | |
19d8fe15 DV |
1486 | return true; |
1487 | } | |
d240f20f | 1488 | |
045ac3b5 JB |
1489 | static void intel_dp_get_config(struct intel_encoder *encoder, |
1490 | struct intel_crtc_config *pipe_config) | |
1491 | { | |
1492 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 1493 | u32 tmp, flags = 0; |
63000ef6 XZ |
1494 | struct drm_device *dev = encoder->base.dev; |
1495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1496 | enum port port = dp_to_dig_port(intel_dp)->port; | |
1497 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
18442d08 | 1498 | int dotclock; |
045ac3b5 | 1499 | |
63000ef6 XZ |
1500 | if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { |
1501 | tmp = I915_READ(intel_dp->output_reg); | |
1502 | if (tmp & DP_SYNC_HS_HIGH) | |
1503 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1504 | else | |
1505 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 1506 | |
63000ef6 XZ |
1507 | if (tmp & DP_SYNC_VS_HIGH) |
1508 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1509 | else | |
1510 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1511 | } else { | |
1512 | tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
1513 | if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
1514 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1515 | else | |
1516 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 1517 | |
63000ef6 XZ |
1518 | if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
1519 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1520 | else | |
1521 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1522 | } | |
045ac3b5 JB |
1523 | |
1524 | pipe_config->adjusted_mode.flags |= flags; | |
f1f644dc | 1525 | |
eb14cb74 VS |
1526 | pipe_config->has_dp_encoder = true; |
1527 | ||
1528 | intel_dp_get_m_n(crtc, pipe_config); | |
1529 | ||
18442d08 | 1530 | if (port == PORT_A) { |
f1f644dc JB |
1531 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
1532 | pipe_config->port_clock = 162000; | |
1533 | else | |
1534 | pipe_config->port_clock = 270000; | |
1535 | } | |
18442d08 VS |
1536 | |
1537 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, | |
1538 | &pipe_config->dp_m_n); | |
1539 | ||
1540 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) | |
1541 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
1542 | ||
241bfc38 | 1543 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
7f16e5c1 | 1544 | |
c6cd2ee2 JN |
1545 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
1546 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { | |
1547 | /* | |
1548 | * This is a big fat ugly hack. | |
1549 | * | |
1550 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
1551 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
1552 | * unknown we fail to light up. Yet the same BIOS boots up with | |
1553 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
1554 | * max, not what it tells us to use. | |
1555 | * | |
1556 | * Note: This will still be broken if the eDP panel is not lit | |
1557 | * up by the BIOS, and thus we can't get the mode at module | |
1558 | * load. | |
1559 | */ | |
1560 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
1561 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); | |
1562 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; | |
1563 | } | |
045ac3b5 JB |
1564 | } |
1565 | ||
a031d709 | 1566 | static bool is_edp_psr(struct drm_device *dev) |
2293bb5c | 1567 | { |
a031d709 RV |
1568 | struct drm_i915_private *dev_priv = dev->dev_private; |
1569 | ||
1570 | return dev_priv->psr.sink_support; | |
2293bb5c SK |
1571 | } |
1572 | ||
2b28bb1b RV |
1573 | static bool intel_edp_is_psr_enabled(struct drm_device *dev) |
1574 | { | |
1575 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1576 | ||
18b5992c | 1577 | if (!HAS_PSR(dev)) |
2b28bb1b RV |
1578 | return false; |
1579 | ||
18b5992c | 1580 | return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
2b28bb1b RV |
1581 | } |
1582 | ||
1583 | static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, | |
1584 | struct edp_vsc_psr *vsc_psr) | |
1585 | { | |
1586 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
1587 | struct drm_device *dev = dig_port->base.base.dev; | |
1588 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1589 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); | |
1590 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); | |
1591 | u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); | |
1592 | uint32_t *data = (uint32_t *) vsc_psr; | |
1593 | unsigned int i; | |
1594 | ||
1595 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable | |
1596 | the video DIP being updated before program video DIP data buffer | |
1597 | registers for DIP being updated. */ | |
1598 | I915_WRITE(ctl_reg, 0); | |
1599 | POSTING_READ(ctl_reg); | |
1600 | ||
1601 | for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { | |
1602 | if (i < sizeof(struct edp_vsc_psr)) | |
1603 | I915_WRITE(data_reg + i, *data++); | |
1604 | else | |
1605 | I915_WRITE(data_reg + i, 0); | |
1606 | } | |
1607 | ||
1608 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); | |
1609 | POSTING_READ(ctl_reg); | |
1610 | } | |
1611 | ||
1612 | static void intel_edp_psr_setup(struct intel_dp *intel_dp) | |
1613 | { | |
1614 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1615 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1616 | struct edp_vsc_psr psr_vsc; | |
1617 | ||
1618 | if (intel_dp->psr_setup_done) | |
1619 | return; | |
1620 | ||
1621 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ | |
1622 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
1623 | psr_vsc.sdp_header.HB0 = 0; | |
1624 | psr_vsc.sdp_header.HB1 = 0x7; | |
1625 | psr_vsc.sdp_header.HB2 = 0x2; | |
1626 | psr_vsc.sdp_header.HB3 = 0x8; | |
1627 | intel_edp_psr_write_vsc(intel_dp, &psr_vsc); | |
1628 | ||
1629 | /* Avoid continuous PSR exit by masking memup and hpd */ | |
18b5992c | 1630 | I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | |
0cc4b699 | 1631 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); |
2b28bb1b RV |
1632 | |
1633 | intel_dp->psr_setup_done = true; | |
1634 | } | |
1635 | ||
1636 | static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) | |
1637 | { | |
1638 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ec5b01dd | 1640 | uint32_t aux_clock_divider; |
2b28bb1b RV |
1641 | int precharge = 0x3; |
1642 | int msg_size = 5; /* Header(4) + Message(1) */ | |
1643 | ||
ec5b01dd DL |
1644 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
1645 | ||
2b28bb1b RV |
1646 | /* Enable PSR in sink */ |
1647 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) | |
1648 | intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, | |
1649 | DP_PSR_ENABLE & | |
1650 | ~DP_PSR_MAIN_LINK_ACTIVE); | |
1651 | else | |
1652 | intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, | |
1653 | DP_PSR_ENABLE | | |
1654 | DP_PSR_MAIN_LINK_ACTIVE); | |
1655 | ||
1656 | /* Setup AUX registers */ | |
18b5992c BW |
1657 | I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); |
1658 | I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); | |
1659 | I915_WRITE(EDP_PSR_AUX_CTL(dev), | |
2b28bb1b RV |
1660 | DP_AUX_CH_CTL_TIME_OUT_400us | |
1661 | (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
1662 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
1663 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); | |
1664 | } | |
1665 | ||
1666 | static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) | |
1667 | { | |
1668 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1669 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1670 | uint32_t max_sleep_time = 0x1f; | |
1671 | uint32_t idle_frames = 1; | |
1672 | uint32_t val = 0x0; | |
ed8546ac | 1673 | const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
2b28bb1b RV |
1674 | |
1675 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { | |
1676 | val |= EDP_PSR_LINK_STANDBY; | |
1677 | val |= EDP_PSR_TP2_TP3_TIME_0us; | |
1678 | val |= EDP_PSR_TP1_TIME_0us; | |
1679 | val |= EDP_PSR_SKIP_AUX_EXIT; | |
1680 | } else | |
1681 | val |= EDP_PSR_LINK_DISABLE; | |
1682 | ||
18b5992c | 1683 | I915_WRITE(EDP_PSR_CTL(dev), val | |
ed8546ac | 1684 | IS_BROADWELL(dev) ? 0 : link_entry_time | |
2b28bb1b RV |
1685 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | |
1686 | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | | |
1687 | EDP_PSR_ENABLE); | |
1688 | } | |
1689 | ||
3f51e471 RV |
1690 | static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) |
1691 | { | |
1692 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
1693 | struct drm_device *dev = dig_port->base.base.dev; | |
1694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1695 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
1696 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1697 | struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj; | |
1698 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; | |
1699 | ||
a031d709 RV |
1700 | dev_priv->psr.source_ok = false; |
1701 | ||
18b5992c | 1702 | if (!HAS_PSR(dev)) { |
3f51e471 | 1703 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); |
3f51e471 RV |
1704 | return false; |
1705 | } | |
1706 | ||
1707 | if ((intel_encoder->type != INTEL_OUTPUT_EDP) || | |
1708 | (dig_port->port != PORT_A)) { | |
1709 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); | |
3f51e471 RV |
1710 | return false; |
1711 | } | |
1712 | ||
105b7c11 RV |
1713 | if (!i915_enable_psr) { |
1714 | DRM_DEBUG_KMS("PSR disable by flag\n"); | |
105b7c11 RV |
1715 | return false; |
1716 | } | |
1717 | ||
cd234b0b CW |
1718 | crtc = dig_port->base.base.crtc; |
1719 | if (crtc == NULL) { | |
1720 | DRM_DEBUG_KMS("crtc not active for PSR\n"); | |
cd234b0b CW |
1721 | return false; |
1722 | } | |
1723 | ||
1724 | intel_crtc = to_intel_crtc(crtc); | |
20ddf665 | 1725 | if (!intel_crtc_active(crtc)) { |
3f51e471 | 1726 | DRM_DEBUG_KMS("crtc not active for PSR\n"); |
3f51e471 RV |
1727 | return false; |
1728 | } | |
1729 | ||
cd234b0b | 1730 | obj = to_intel_framebuffer(crtc->fb)->obj; |
3f51e471 RV |
1731 | if (obj->tiling_mode != I915_TILING_X || |
1732 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
1733 | DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); | |
3f51e471 RV |
1734 | return false; |
1735 | } | |
1736 | ||
1737 | if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { | |
1738 | DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); | |
3f51e471 RV |
1739 | return false; |
1740 | } | |
1741 | ||
1742 | if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & | |
1743 | S3D_ENABLE) { | |
1744 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); | |
3f51e471 RV |
1745 | return false; |
1746 | } | |
1747 | ||
ca73b4f0 | 1748 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
3f51e471 | 1749 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
3f51e471 RV |
1750 | return false; |
1751 | } | |
1752 | ||
a031d709 | 1753 | dev_priv->psr.source_ok = true; |
3f51e471 RV |
1754 | return true; |
1755 | } | |
1756 | ||
3d739d92 | 1757 | static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) |
2b28bb1b RV |
1758 | { |
1759 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1760 | ||
3f51e471 RV |
1761 | if (!intel_edp_psr_match_conditions(intel_dp) || |
1762 | intel_edp_is_psr_enabled(dev)) | |
2b28bb1b RV |
1763 | return; |
1764 | ||
1765 | /* Setup PSR once */ | |
1766 | intel_edp_psr_setup(intel_dp); | |
1767 | ||
1768 | /* Enable PSR on the panel */ | |
1769 | intel_edp_psr_enable_sink(intel_dp); | |
1770 | ||
1771 | /* Enable PSR on the host */ | |
1772 | intel_edp_psr_enable_source(intel_dp); | |
1773 | } | |
1774 | ||
3d739d92 RV |
1775 | void intel_edp_psr_enable(struct intel_dp *intel_dp) |
1776 | { | |
1777 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1778 | ||
1779 | if (intel_edp_psr_match_conditions(intel_dp) && | |
1780 | !intel_edp_is_psr_enabled(dev)) | |
1781 | intel_edp_psr_do_enable(intel_dp); | |
1782 | } | |
1783 | ||
2b28bb1b RV |
1784 | void intel_edp_psr_disable(struct intel_dp *intel_dp) |
1785 | { | |
1786 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1787 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1788 | ||
1789 | if (!intel_edp_is_psr_enabled(dev)) | |
1790 | return; | |
1791 | ||
18b5992c BW |
1792 | I915_WRITE(EDP_PSR_CTL(dev), |
1793 | I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); | |
2b28bb1b RV |
1794 | |
1795 | /* Wait till PSR is idle */ | |
18b5992c | 1796 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & |
2b28bb1b RV |
1797 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) |
1798 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); | |
1799 | } | |
1800 | ||
3d739d92 RV |
1801 | void intel_edp_psr_update(struct drm_device *dev) |
1802 | { | |
1803 | struct intel_encoder *encoder; | |
1804 | struct intel_dp *intel_dp = NULL; | |
1805 | ||
1806 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) | |
1807 | if (encoder->type == INTEL_OUTPUT_EDP) { | |
1808 | intel_dp = enc_to_intel_dp(&encoder->base); | |
1809 | ||
a031d709 | 1810 | if (!is_edp_psr(dev)) |
3d739d92 RV |
1811 | return; |
1812 | ||
1813 | if (!intel_edp_psr_match_conditions(intel_dp)) | |
1814 | intel_edp_psr_disable(intel_dp); | |
1815 | else | |
1816 | if (!intel_edp_is_psr_enabled(dev)) | |
1817 | intel_edp_psr_do_enable(intel_dp); | |
1818 | } | |
1819 | } | |
1820 | ||
e8cb4558 | 1821 | static void intel_disable_dp(struct intel_encoder *encoder) |
d240f20f | 1822 | { |
e8cb4558 | 1823 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 ID |
1824 | enum port port = dp_to_dig_port(intel_dp)->port; |
1825 | struct drm_device *dev = encoder->base.dev; | |
6cb49835 DV |
1826 | |
1827 | /* Make sure the panel is off before trying to change the mode. But also | |
1828 | * ensure that we have vdd while we switch off the panel. */ | |
4be73780 | 1829 | intel_edp_backlight_off(intel_dp); |
fdbc3b1f | 1830 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 1831 | intel_edp_panel_off(intel_dp); |
3739850b DV |
1832 | |
1833 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ | |
982a3866 | 1834 | if (!(port == PORT_A || IS_VALLEYVIEW(dev))) |
3739850b | 1835 | intel_dp_link_down(intel_dp); |
d240f20f JB |
1836 | } |
1837 | ||
2bd2ad64 | 1838 | static void intel_post_disable_dp(struct intel_encoder *encoder) |
d240f20f | 1839 | { |
2bd2ad64 | 1840 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 1841 | enum port port = dp_to_dig_port(intel_dp)->port; |
b2634017 | 1842 | struct drm_device *dev = encoder->base.dev; |
2bd2ad64 | 1843 | |
982a3866 | 1844 | if (port == PORT_A || IS_VALLEYVIEW(dev)) { |
3739850b | 1845 | intel_dp_link_down(intel_dp); |
b2634017 JB |
1846 | if (!IS_VALLEYVIEW(dev)) |
1847 | ironlake_edp_pll_off(intel_dp); | |
3739850b | 1848 | } |
2bd2ad64 DV |
1849 | } |
1850 | ||
e8cb4558 | 1851 | static void intel_enable_dp(struct intel_encoder *encoder) |
d240f20f | 1852 | { |
e8cb4558 DV |
1853 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1854 | struct drm_device *dev = encoder->base.dev; | |
1855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1856 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); | |
5d613501 | 1857 | |
0c33d8d7 DV |
1858 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
1859 | return; | |
5d613501 | 1860 | |
4be73780 | 1861 | edp_panel_vdd_on(intel_dp); |
f01eca2e | 1862 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 1863 | intel_dp_start_link_train(intel_dp); |
4be73780 DV |
1864 | intel_edp_panel_on(intel_dp); |
1865 | edp_panel_vdd_off(intel_dp, true); | |
33a34e4e | 1866 | intel_dp_complete_link_train(intel_dp); |
3ab9c637 | 1867 | intel_dp_stop_link_train(intel_dp); |
ab1f90f9 | 1868 | } |
89b667f8 | 1869 | |
ecff4f3b JN |
1870 | static void g4x_enable_dp(struct intel_encoder *encoder) |
1871 | { | |
828f5c6e JN |
1872 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1873 | ||
ecff4f3b | 1874 | intel_enable_dp(encoder); |
4be73780 | 1875 | intel_edp_backlight_on(intel_dp); |
ab1f90f9 | 1876 | } |
89b667f8 | 1877 | |
ab1f90f9 JN |
1878 | static void vlv_enable_dp(struct intel_encoder *encoder) |
1879 | { | |
828f5c6e JN |
1880 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1881 | ||
4be73780 | 1882 | intel_edp_backlight_on(intel_dp); |
d240f20f JB |
1883 | } |
1884 | ||
ecff4f3b | 1885 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
ab1f90f9 JN |
1886 | { |
1887 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
1888 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
1889 | ||
1890 | if (dport->port == PORT_A) | |
1891 | ironlake_edp_pll_on(intel_dp); | |
1892 | } | |
1893 | ||
1894 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) | |
a4fc5ed6 | 1895 | { |
2bd2ad64 | 1896 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1897 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
b2634017 | 1898 | struct drm_device *dev = encoder->base.dev; |
89b667f8 | 1899 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab1f90f9 | 1900 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
e4607fcf | 1901 | enum dpio_channel port = vlv_dport_to_channel(dport); |
ab1f90f9 | 1902 | int pipe = intel_crtc->pipe; |
bf13e81b | 1903 | struct edp_power_seq power_seq; |
ab1f90f9 | 1904 | u32 val; |
a4fc5ed6 | 1905 | |
ab1f90f9 | 1906 | mutex_lock(&dev_priv->dpio_lock); |
89b667f8 | 1907 | |
ab3c759a | 1908 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
ab1f90f9 JN |
1909 | val = 0; |
1910 | if (pipe) | |
1911 | val |= (1<<21); | |
1912 | else | |
1913 | val &= ~(1<<21); | |
1914 | val |= 0x001000c4; | |
ab3c759a CML |
1915 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
1916 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); | |
1917 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
89b667f8 | 1918 | |
ab1f90f9 JN |
1919 | mutex_unlock(&dev_priv->dpio_lock); |
1920 | ||
bf13e81b JN |
1921 | /* init power sequencer on this pipe and port */ |
1922 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); | |
1923 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, | |
1924 | &power_seq); | |
1925 | ||
ab1f90f9 JN |
1926 | intel_enable_dp(encoder); |
1927 | ||
e4607fcf | 1928 | vlv_wait_port_ready(dev_priv, dport); |
89b667f8 JB |
1929 | } |
1930 | ||
ecff4f3b | 1931 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1932 | { |
1933 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1934 | struct drm_device *dev = encoder->base.dev; | |
1935 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1936 | struct intel_crtc *intel_crtc = |
1937 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1938 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1939 | int pipe = intel_crtc->pipe; |
89b667f8 | 1940 | |
89b667f8 | 1941 | /* Program Tx lane resets to default */ |
0980a60f | 1942 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1943 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
1944 | DPIO_PCS_TX_LANE2_RESET | |
1945 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 1946 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
1947 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1948 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1949 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1950 | DPIO_PCS_CLK_SOFT_RESET); | |
1951 | ||
1952 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
1953 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1954 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
1955 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
0980a60f | 1956 | mutex_unlock(&dev_priv->dpio_lock); |
a4fc5ed6 KP |
1957 | } |
1958 | ||
1959 | /* | |
df0c237d JB |
1960 | * Native read with retry for link status and receiver capability reads for |
1961 | * cases where the sink may still be asleep. | |
a4fc5ed6 KP |
1962 | */ |
1963 | static bool | |
df0c237d JB |
1964 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
1965 | uint8_t *recv, int recv_bytes) | |
a4fc5ed6 | 1966 | { |
61da5fab JB |
1967 | int ret, i; |
1968 | ||
df0c237d JB |
1969 | /* |
1970 | * Sinks are *supposed* to come up within 1ms from an off state, | |
1971 | * but we're also supposed to retry 3 times per the spec. | |
1972 | */ | |
61da5fab | 1973 | for (i = 0; i < 3; i++) { |
df0c237d JB |
1974 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
1975 | recv_bytes); | |
1976 | if (ret == recv_bytes) | |
61da5fab JB |
1977 | return true; |
1978 | msleep(1); | |
1979 | } | |
a4fc5ed6 | 1980 | |
61da5fab | 1981 | return false; |
a4fc5ed6 KP |
1982 | } |
1983 | ||
1984 | /* | |
1985 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
1986 | * link status information | |
1987 | */ | |
1988 | static bool | |
93f62dad | 1989 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 1990 | { |
df0c237d JB |
1991 | return intel_dp_aux_native_read_retry(intel_dp, |
1992 | DP_LANE0_1_STATUS, | |
93f62dad | 1993 | link_status, |
df0c237d | 1994 | DP_LINK_STATUS_SIZE); |
a4fc5ed6 KP |
1995 | } |
1996 | ||
a4fc5ed6 KP |
1997 | /* |
1998 | * These are source-specific values; current Intel hardware supports | |
1999 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
2000 | */ | |
a4fc5ed6 KP |
2001 | |
2002 | static uint8_t | |
1a2eb460 | 2003 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 2004 | { |
30add22d | 2005 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 2006 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 2007 | |
8f93f4f1 | 2008 | if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev)) |
e2fa6fba | 2009 | return DP_TRAIN_VOLTAGE_SWING_1200; |
bc7d38a4 | 2010 | else if (IS_GEN7(dev) && port == PORT_A) |
1a2eb460 | 2011 | return DP_TRAIN_VOLTAGE_SWING_800; |
bc7d38a4 | 2012 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
1a2eb460 KP |
2013 | return DP_TRAIN_VOLTAGE_SWING_1200; |
2014 | else | |
2015 | return DP_TRAIN_VOLTAGE_SWING_800; | |
2016 | } | |
2017 | ||
2018 | static uint8_t | |
2019 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) | |
2020 | { | |
30add22d | 2021 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 2022 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 2023 | |
8f93f4f1 PZ |
2024 | if (IS_BROADWELL(dev)) { |
2025 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2026 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2027 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2028 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2029 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2030 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2031 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2032 | default: | |
2033 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2034 | } | |
2035 | } else if (IS_HASWELL(dev)) { | |
d6c0d722 PZ |
2036 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2037 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2038 | return DP_TRAIN_PRE_EMPHASIS_9_5; | |
2039 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2040 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2041 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2042 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2043 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2044 | default: | |
2045 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2046 | } | |
e2fa6fba P |
2047 | } else if (IS_VALLEYVIEW(dev)) { |
2048 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2049 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2050 | return DP_TRAIN_PRE_EMPHASIS_9_5; | |
2051 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2052 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2053 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2054 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2055 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2056 | default: | |
2057 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2058 | } | |
bc7d38a4 | 2059 | } else if (IS_GEN7(dev) && port == PORT_A) { |
1a2eb460 KP |
2060 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2061 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2062 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2063 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2064 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2065 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2066 | default: | |
2067 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2068 | } | |
2069 | } else { | |
2070 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2071 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2072 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2073 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2074 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2075 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2076 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2077 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2078 | default: | |
2079 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2080 | } | |
a4fc5ed6 KP |
2081 | } |
2082 | } | |
2083 | ||
e2fa6fba P |
2084 | static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) |
2085 | { | |
2086 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
2087 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2088 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
5e69f97f CML |
2089 | struct intel_crtc *intel_crtc = |
2090 | to_intel_crtc(dport->base.base.crtc); | |
e2fa6fba P |
2091 | unsigned long demph_reg_value, preemph_reg_value, |
2092 | uniqtranscale_reg_value; | |
2093 | uint8_t train_set = intel_dp->train_set[0]; | |
e4607fcf | 2094 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 2095 | int pipe = intel_crtc->pipe; |
e2fa6fba P |
2096 | |
2097 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
2098 | case DP_TRAIN_PRE_EMPHASIS_0: | |
2099 | preemph_reg_value = 0x0004000; | |
2100 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2101 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2102 | demph_reg_value = 0x2B405555; | |
2103 | uniqtranscale_reg_value = 0x552AB83A; | |
2104 | break; | |
2105 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2106 | demph_reg_value = 0x2B404040; | |
2107 | uniqtranscale_reg_value = 0x5548B83A; | |
2108 | break; | |
2109 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2110 | demph_reg_value = 0x2B245555; | |
2111 | uniqtranscale_reg_value = 0x5560B83A; | |
2112 | break; | |
2113 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2114 | demph_reg_value = 0x2B405555; | |
2115 | uniqtranscale_reg_value = 0x5598DA3A; | |
2116 | break; | |
2117 | default: | |
2118 | return 0; | |
2119 | } | |
2120 | break; | |
2121 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
2122 | preemph_reg_value = 0x0002000; | |
2123 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2124 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2125 | demph_reg_value = 0x2B404040; | |
2126 | uniqtranscale_reg_value = 0x5552B83A; | |
2127 | break; | |
2128 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2129 | demph_reg_value = 0x2B404848; | |
2130 | uniqtranscale_reg_value = 0x5580B83A; | |
2131 | break; | |
2132 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2133 | demph_reg_value = 0x2B404040; | |
2134 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2135 | break; | |
2136 | default: | |
2137 | return 0; | |
2138 | } | |
2139 | break; | |
2140 | case DP_TRAIN_PRE_EMPHASIS_6: | |
2141 | preemph_reg_value = 0x0000000; | |
2142 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2143 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2144 | demph_reg_value = 0x2B305555; | |
2145 | uniqtranscale_reg_value = 0x5570B83A; | |
2146 | break; | |
2147 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2148 | demph_reg_value = 0x2B2B4040; | |
2149 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2150 | break; | |
2151 | default: | |
2152 | return 0; | |
2153 | } | |
2154 | break; | |
2155 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
2156 | preemph_reg_value = 0x0006000; | |
2157 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2158 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2159 | demph_reg_value = 0x1B405555; | |
2160 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2161 | break; | |
2162 | default: | |
2163 | return 0; | |
2164 | } | |
2165 | break; | |
2166 | default: | |
2167 | return 0; | |
2168 | } | |
2169 | ||
0980a60f | 2170 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a CML |
2171 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
2172 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); | |
2173 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), | |
e2fa6fba | 2174 | uniqtranscale_reg_value); |
ab3c759a CML |
2175 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
2176 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
2177 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); | |
2178 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); | |
0980a60f | 2179 | mutex_unlock(&dev_priv->dpio_lock); |
e2fa6fba P |
2180 | |
2181 | return 0; | |
2182 | } | |
2183 | ||
a4fc5ed6 | 2184 | static void |
0301b3ac JN |
2185 | intel_get_adjust_train(struct intel_dp *intel_dp, |
2186 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) | |
a4fc5ed6 KP |
2187 | { |
2188 | uint8_t v = 0; | |
2189 | uint8_t p = 0; | |
2190 | int lane; | |
1a2eb460 KP |
2191 | uint8_t voltage_max; |
2192 | uint8_t preemph_max; | |
a4fc5ed6 | 2193 | |
33a34e4e | 2194 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
0f037bde DV |
2195 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
2196 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); | |
a4fc5ed6 KP |
2197 | |
2198 | if (this_v > v) | |
2199 | v = this_v; | |
2200 | if (this_p > p) | |
2201 | p = this_p; | |
2202 | } | |
2203 | ||
1a2eb460 | 2204 | voltage_max = intel_dp_voltage_max(intel_dp); |
417e822d KP |
2205 | if (v >= voltage_max) |
2206 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; | |
a4fc5ed6 | 2207 | |
1a2eb460 KP |
2208 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
2209 | if (p >= preemph_max) | |
2210 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
a4fc5ed6 KP |
2211 | |
2212 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 2213 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
2214 | } |
2215 | ||
2216 | static uint32_t | |
f0a3424e | 2217 | intel_gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 2218 | { |
3cf2efb1 | 2219 | uint32_t signal_levels = 0; |
a4fc5ed6 | 2220 | |
3cf2efb1 | 2221 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
2222 | case DP_TRAIN_VOLTAGE_SWING_400: |
2223 | default: | |
2224 | signal_levels |= DP_VOLTAGE_0_4; | |
2225 | break; | |
2226 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2227 | signal_levels |= DP_VOLTAGE_0_6; | |
2228 | break; | |
2229 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2230 | signal_levels |= DP_VOLTAGE_0_8; | |
2231 | break; | |
2232 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2233 | signal_levels |= DP_VOLTAGE_1_2; | |
2234 | break; | |
2235 | } | |
3cf2efb1 | 2236 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
2237 | case DP_TRAIN_PRE_EMPHASIS_0: |
2238 | default: | |
2239 | signal_levels |= DP_PRE_EMPHASIS_0; | |
2240 | break; | |
2241 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
2242 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
2243 | break; | |
2244 | case DP_TRAIN_PRE_EMPHASIS_6: | |
2245 | signal_levels |= DP_PRE_EMPHASIS_6; | |
2246 | break; | |
2247 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
2248 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
2249 | break; | |
2250 | } | |
2251 | return signal_levels; | |
2252 | } | |
2253 | ||
e3421a18 ZW |
2254 | /* Gen6's DP voltage swing and pre-emphasis control */ |
2255 | static uint32_t | |
2256 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
2257 | { | |
3c5a62b5 YL |
2258 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2259 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2260 | switch (signal_levels) { | |
e3421a18 | 2261 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
2262 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2263 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
2264 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2265 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 2266 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
2267 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
2268 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 2269 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
2270 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2271 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 2272 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
2273 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
2274 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 2275 | default: |
3c5a62b5 YL |
2276 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
2277 | "0x%x\n", signal_levels); | |
2278 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
2279 | } |
2280 | } | |
2281 | ||
1a2eb460 KP |
2282 | /* Gen7's DP voltage swing and pre-emphasis control */ |
2283 | static uint32_t | |
2284 | intel_gen7_edp_signal_levels(uint8_t train_set) | |
2285 | { | |
2286 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
2287 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2288 | switch (signal_levels) { | |
2289 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
2290 | return EDP_LINK_TRAIN_400MV_0DB_IVB; | |
2291 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2292 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; | |
2293 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
2294 | return EDP_LINK_TRAIN_400MV_6DB_IVB; | |
2295 | ||
2296 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: | |
2297 | return EDP_LINK_TRAIN_600MV_0DB_IVB; | |
2298 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2299 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; | |
2300 | ||
2301 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | |
2302 | return EDP_LINK_TRAIN_800MV_0DB_IVB; | |
2303 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2304 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; | |
2305 | ||
2306 | default: | |
2307 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
2308 | "0x%x\n", signal_levels); | |
2309 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
2310 | } | |
2311 | } | |
2312 | ||
d6c0d722 PZ |
2313 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
2314 | static uint32_t | |
f0a3424e | 2315 | intel_hsw_signal_levels(uint8_t train_set) |
a4fc5ed6 | 2316 | { |
d6c0d722 PZ |
2317 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2318 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2319 | switch (signal_levels) { | |
2320 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
2321 | return DDI_BUF_EMP_400MV_0DB_HSW; | |
2322 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2323 | return DDI_BUF_EMP_400MV_3_5DB_HSW; | |
2324 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
2325 | return DDI_BUF_EMP_400MV_6DB_HSW; | |
2326 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: | |
2327 | return DDI_BUF_EMP_400MV_9_5DB_HSW; | |
a4fc5ed6 | 2328 | |
d6c0d722 PZ |
2329 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2330 | return DDI_BUF_EMP_600MV_0DB_HSW; | |
2331 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2332 | return DDI_BUF_EMP_600MV_3_5DB_HSW; | |
2333 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: | |
2334 | return DDI_BUF_EMP_600MV_6DB_HSW; | |
a4fc5ed6 | 2335 | |
d6c0d722 PZ |
2336 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
2337 | return DDI_BUF_EMP_800MV_0DB_HSW; | |
2338 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2339 | return DDI_BUF_EMP_800MV_3_5DB_HSW; | |
2340 | default: | |
2341 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
2342 | "0x%x\n", signal_levels); | |
2343 | return DDI_BUF_EMP_400MV_0DB_HSW; | |
a4fc5ed6 | 2344 | } |
a4fc5ed6 KP |
2345 | } |
2346 | ||
8f93f4f1 PZ |
2347 | static uint32_t |
2348 | intel_bdw_signal_levels(uint8_t train_set) | |
2349 | { | |
2350 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
2351 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2352 | switch (signal_levels) { | |
2353 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
2354 | return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ | |
2355 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2356 | return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */ | |
2357 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
2358 | return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */ | |
2359 | ||
2360 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: | |
2361 | return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */ | |
2362 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2363 | return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */ | |
2364 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: | |
2365 | return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */ | |
2366 | ||
2367 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | |
2368 | return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */ | |
2369 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2370 | return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */ | |
2371 | ||
2372 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: | |
2373 | return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */ | |
2374 | ||
2375 | default: | |
2376 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
2377 | "0x%x\n", signal_levels); | |
2378 | return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ | |
2379 | } | |
2380 | } | |
2381 | ||
f0a3424e PZ |
2382 | /* Properly updates "DP" with the correct signal levels. */ |
2383 | static void | |
2384 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) | |
2385 | { | |
2386 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 2387 | enum port port = intel_dig_port->port; |
f0a3424e PZ |
2388 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2389 | uint32_t signal_levels, mask; | |
2390 | uint8_t train_set = intel_dp->train_set[0]; | |
2391 | ||
8f93f4f1 PZ |
2392 | if (IS_BROADWELL(dev)) { |
2393 | signal_levels = intel_bdw_signal_levels(train_set); | |
2394 | mask = DDI_BUF_EMP_MASK; | |
2395 | } else if (IS_HASWELL(dev)) { | |
f0a3424e PZ |
2396 | signal_levels = intel_hsw_signal_levels(train_set); |
2397 | mask = DDI_BUF_EMP_MASK; | |
e2fa6fba P |
2398 | } else if (IS_VALLEYVIEW(dev)) { |
2399 | signal_levels = intel_vlv_signal_levels(intel_dp); | |
2400 | mask = 0; | |
bc7d38a4 | 2401 | } else if (IS_GEN7(dev) && port == PORT_A) { |
f0a3424e PZ |
2402 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
2403 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; | |
bc7d38a4 | 2404 | } else if (IS_GEN6(dev) && port == PORT_A) { |
f0a3424e PZ |
2405 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
2406 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; | |
2407 | } else { | |
2408 | signal_levels = intel_gen4_signal_levels(train_set); | |
2409 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; | |
2410 | } | |
2411 | ||
2412 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
2413 | ||
2414 | *DP = (*DP & ~mask) | signal_levels; | |
2415 | } | |
2416 | ||
a4fc5ed6 | 2417 | static bool |
ea5b213a | 2418 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
70aff66c | 2419 | uint32_t *DP, |
58e10eb9 | 2420 | uint8_t dp_train_pat) |
a4fc5ed6 | 2421 | { |
174edf1f PZ |
2422 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2423 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
a4fc5ed6 | 2424 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 2425 | enum port port = intel_dig_port->port; |
2cdfe6c8 JN |
2426 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
2427 | int ret, len; | |
a4fc5ed6 | 2428 | |
22b8bf17 | 2429 | if (HAS_DDI(dev)) { |
3ab9c637 | 2430 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
d6c0d722 PZ |
2431 | |
2432 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2433 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2434 | else | |
2435 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2436 | ||
2437 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2438 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2439 | case DP_TRAINING_PATTERN_DISABLE: | |
d6c0d722 PZ |
2440 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
2441 | ||
2442 | break; | |
2443 | case DP_TRAINING_PATTERN_1: | |
2444 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2445 | break; | |
2446 | case DP_TRAINING_PATTERN_2: | |
2447 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2448 | break; | |
2449 | case DP_TRAINING_PATTERN_3: | |
2450 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2451 | break; | |
2452 | } | |
174edf1f | 2453 | I915_WRITE(DP_TP_CTL(port), temp); |
d6c0d722 | 2454 | |
bc7d38a4 | 2455 | } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
70aff66c | 2456 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
47ea7542 PZ |
2457 | |
2458 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2459 | case DP_TRAINING_PATTERN_DISABLE: | |
70aff66c | 2460 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
47ea7542 PZ |
2461 | break; |
2462 | case DP_TRAINING_PATTERN_1: | |
70aff66c | 2463 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
47ea7542 PZ |
2464 | break; |
2465 | case DP_TRAINING_PATTERN_2: | |
70aff66c | 2466 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
47ea7542 PZ |
2467 | break; |
2468 | case DP_TRAINING_PATTERN_3: | |
2469 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
70aff66c | 2470 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
47ea7542 PZ |
2471 | break; |
2472 | } | |
2473 | ||
2474 | } else { | |
70aff66c | 2475 | *DP &= ~DP_LINK_TRAIN_MASK; |
47ea7542 PZ |
2476 | |
2477 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2478 | case DP_TRAINING_PATTERN_DISABLE: | |
70aff66c | 2479 | *DP |= DP_LINK_TRAIN_OFF; |
47ea7542 PZ |
2480 | break; |
2481 | case DP_TRAINING_PATTERN_1: | |
70aff66c | 2482 | *DP |= DP_LINK_TRAIN_PAT_1; |
47ea7542 PZ |
2483 | break; |
2484 | case DP_TRAINING_PATTERN_2: | |
70aff66c | 2485 | *DP |= DP_LINK_TRAIN_PAT_2; |
47ea7542 PZ |
2486 | break; |
2487 | case DP_TRAINING_PATTERN_3: | |
2488 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
70aff66c | 2489 | *DP |= DP_LINK_TRAIN_PAT_2; |
47ea7542 PZ |
2490 | break; |
2491 | } | |
2492 | } | |
2493 | ||
70aff66c | 2494 | I915_WRITE(intel_dp->output_reg, *DP); |
ea5b213a | 2495 | POSTING_READ(intel_dp->output_reg); |
a4fc5ed6 | 2496 | |
2cdfe6c8 JN |
2497 | buf[0] = dp_train_pat; |
2498 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == | |
47ea7542 | 2499 | DP_TRAINING_PATTERN_DISABLE) { |
2cdfe6c8 JN |
2500 | /* don't write DP_TRAINING_LANEx_SET on disable */ |
2501 | len = 1; | |
2502 | } else { | |
2503 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ | |
2504 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); | |
2505 | len = intel_dp->lane_count + 1; | |
47ea7542 | 2506 | } |
a4fc5ed6 | 2507 | |
2cdfe6c8 JN |
2508 | ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET, |
2509 | buf, len); | |
2510 | ||
2511 | return ret == len; | |
a4fc5ed6 KP |
2512 | } |
2513 | ||
70aff66c JN |
2514 | static bool |
2515 | intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, | |
2516 | uint8_t dp_train_pat) | |
2517 | { | |
953d22e8 | 2518 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); |
70aff66c JN |
2519 | intel_dp_set_signal_levels(intel_dp, DP); |
2520 | return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); | |
2521 | } | |
2522 | ||
2523 | static bool | |
2524 | intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, | |
0301b3ac | 2525 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
70aff66c JN |
2526 | { |
2527 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2528 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2530 | int ret; | |
2531 | ||
2532 | intel_get_adjust_train(intel_dp, link_status); | |
2533 | intel_dp_set_signal_levels(intel_dp, DP); | |
2534 | ||
2535 | I915_WRITE(intel_dp->output_reg, *DP); | |
2536 | POSTING_READ(intel_dp->output_reg); | |
2537 | ||
2538 | ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET, | |
2539 | intel_dp->train_set, | |
2540 | intel_dp->lane_count); | |
2541 | ||
2542 | return ret == intel_dp->lane_count; | |
2543 | } | |
2544 | ||
3ab9c637 ID |
2545 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
2546 | { | |
2547 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2548 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2549 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2550 | enum port port = intel_dig_port->port; | |
2551 | uint32_t val; | |
2552 | ||
2553 | if (!HAS_DDI(dev)) | |
2554 | return; | |
2555 | ||
2556 | val = I915_READ(DP_TP_CTL(port)); | |
2557 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2558 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
2559 | I915_WRITE(DP_TP_CTL(port), val); | |
2560 | ||
2561 | /* | |
2562 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
2563 | * we need to set idle transmission mode is to work around a HW issue | |
2564 | * where we enable the pipe while not in idle link-training mode. | |
2565 | * In this case there is requirement to wait for a minimum number of | |
2566 | * idle patterns to be sent. | |
2567 | */ | |
2568 | if (port == PORT_A) | |
2569 | return; | |
2570 | ||
2571 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), | |
2572 | 1)) | |
2573 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); | |
2574 | } | |
2575 | ||
33a34e4e | 2576 | /* Enable corresponding port and start training pattern 1 */ |
c19b0669 | 2577 | void |
33a34e4e | 2578 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 2579 | { |
da63a9f2 | 2580 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
c19b0669 | 2581 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 KP |
2582 | int i; |
2583 | uint8_t voltage; | |
cdb0e95b | 2584 | int voltage_tries, loop_tries; |
ea5b213a | 2585 | uint32_t DP = intel_dp->DP; |
6aba5b6c | 2586 | uint8_t link_config[2]; |
a4fc5ed6 | 2587 | |
affa9354 | 2588 | if (HAS_DDI(dev)) |
c19b0669 PZ |
2589 | intel_ddi_prepare_link_retrain(encoder); |
2590 | ||
3cf2efb1 | 2591 | /* Write the link configuration data */ |
6aba5b6c JN |
2592 | link_config[0] = intel_dp->link_bw; |
2593 | link_config[1] = intel_dp->lane_count; | |
2594 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
2595 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; | |
2596 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2); | |
2597 | ||
2598 | link_config[0] = 0; | |
2599 | link_config[1] = DP_SET_ANSI_8B10B; | |
2600 | intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2); | |
a4fc5ed6 KP |
2601 | |
2602 | DP |= DP_PORT_EN; | |
1a2eb460 | 2603 | |
70aff66c JN |
2604 | /* clock recovery */ |
2605 | if (!intel_dp_reset_link_train(intel_dp, &DP, | |
2606 | DP_TRAINING_PATTERN_1 | | |
2607 | DP_LINK_SCRAMBLING_DISABLE)) { | |
2608 | DRM_ERROR("failed to enable link training\n"); | |
2609 | return; | |
2610 | } | |
2611 | ||
a4fc5ed6 | 2612 | voltage = 0xff; |
cdb0e95b KP |
2613 | voltage_tries = 0; |
2614 | loop_tries = 0; | |
a4fc5ed6 | 2615 | for (;;) { |
70aff66c | 2616 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
a4fc5ed6 | 2617 | |
a7c9655f | 2618 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
93f62dad KP |
2619 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2620 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 2621 | break; |
93f62dad | 2622 | } |
a4fc5ed6 | 2623 | |
01916270 | 2624 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
93f62dad | 2625 | DRM_DEBUG_KMS("clock recovery OK\n"); |
3cf2efb1 CW |
2626 | break; |
2627 | } | |
2628 | ||
2629 | /* Check to see if we've tried the max voltage */ | |
2630 | for (i = 0; i < intel_dp->lane_count; i++) | |
2631 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 2632 | break; |
3b4f819d | 2633 | if (i == intel_dp->lane_count) { |
b06fbda3 DV |
2634 | ++loop_tries; |
2635 | if (loop_tries == 5) { | |
3def84b3 | 2636 | DRM_ERROR("too many full retries, give up\n"); |
cdb0e95b KP |
2637 | break; |
2638 | } | |
70aff66c JN |
2639 | intel_dp_reset_link_train(intel_dp, &DP, |
2640 | DP_TRAINING_PATTERN_1 | | |
2641 | DP_LINK_SCRAMBLING_DISABLE); | |
cdb0e95b KP |
2642 | voltage_tries = 0; |
2643 | continue; | |
2644 | } | |
a4fc5ed6 | 2645 | |
3cf2efb1 | 2646 | /* Check to see if we've tried the same voltage 5 times */ |
b06fbda3 | 2647 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
24773670 | 2648 | ++voltage_tries; |
b06fbda3 | 2649 | if (voltage_tries == 5) { |
3def84b3 | 2650 | DRM_ERROR("too many voltage retries, give up\n"); |
b06fbda3 DV |
2651 | break; |
2652 | } | |
2653 | } else | |
2654 | voltage_tries = 0; | |
2655 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 2656 | |
70aff66c JN |
2657 | /* Update training set as requested by target */ |
2658 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { | |
2659 | DRM_ERROR("failed to update link training\n"); | |
2660 | break; | |
2661 | } | |
a4fc5ed6 KP |
2662 | } |
2663 | ||
33a34e4e JB |
2664 | intel_dp->DP = DP; |
2665 | } | |
2666 | ||
c19b0669 | 2667 | void |
33a34e4e JB |
2668 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
2669 | { | |
33a34e4e | 2670 | bool channel_eq = false; |
37f80975 | 2671 | int tries, cr_tries; |
33a34e4e | 2672 | uint32_t DP = intel_dp->DP; |
06ea66b6 TP |
2673 | uint32_t training_pattern = DP_TRAINING_PATTERN_2; |
2674 | ||
2675 | /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ | |
2676 | if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) | |
2677 | training_pattern = DP_TRAINING_PATTERN_3; | |
33a34e4e | 2678 | |
a4fc5ed6 | 2679 | /* channel equalization */ |
70aff66c | 2680 | if (!intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 2681 | training_pattern | |
70aff66c JN |
2682 | DP_LINK_SCRAMBLING_DISABLE)) { |
2683 | DRM_ERROR("failed to start channel equalization\n"); | |
2684 | return; | |
2685 | } | |
2686 | ||
a4fc5ed6 | 2687 | tries = 0; |
37f80975 | 2688 | cr_tries = 0; |
a4fc5ed6 KP |
2689 | channel_eq = false; |
2690 | for (;;) { | |
70aff66c | 2691 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
e3421a18 | 2692 | |
37f80975 JB |
2693 | if (cr_tries > 5) { |
2694 | DRM_ERROR("failed to train DP, aborting\n"); | |
37f80975 JB |
2695 | break; |
2696 | } | |
2697 | ||
a7c9655f | 2698 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
70aff66c JN |
2699 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2700 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 2701 | break; |
70aff66c | 2702 | } |
a4fc5ed6 | 2703 | |
37f80975 | 2704 | /* Make sure clock is still ok */ |
01916270 | 2705 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
37f80975 | 2706 | intel_dp_start_link_train(intel_dp); |
70aff66c | 2707 | intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 2708 | training_pattern | |
70aff66c | 2709 | DP_LINK_SCRAMBLING_DISABLE); |
37f80975 JB |
2710 | cr_tries++; |
2711 | continue; | |
2712 | } | |
2713 | ||
1ffdff13 | 2714 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
3cf2efb1 CW |
2715 | channel_eq = true; |
2716 | break; | |
2717 | } | |
a4fc5ed6 | 2718 | |
37f80975 JB |
2719 | /* Try 5 times, then try clock recovery if that fails */ |
2720 | if (tries > 5) { | |
2721 | intel_dp_link_down(intel_dp); | |
2722 | intel_dp_start_link_train(intel_dp); | |
70aff66c | 2723 | intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 2724 | training_pattern | |
70aff66c | 2725 | DP_LINK_SCRAMBLING_DISABLE); |
37f80975 JB |
2726 | tries = 0; |
2727 | cr_tries++; | |
2728 | continue; | |
2729 | } | |
a4fc5ed6 | 2730 | |
70aff66c JN |
2731 | /* Update training set as requested by target */ |
2732 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { | |
2733 | DRM_ERROR("failed to update link training\n"); | |
2734 | break; | |
2735 | } | |
3cf2efb1 | 2736 | ++tries; |
869184a6 | 2737 | } |
3cf2efb1 | 2738 | |
3ab9c637 ID |
2739 | intel_dp_set_idle_link_train(intel_dp); |
2740 | ||
2741 | intel_dp->DP = DP; | |
2742 | ||
d6c0d722 | 2743 | if (channel_eq) |
07f42258 | 2744 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
d6c0d722 | 2745 | |
3ab9c637 ID |
2746 | } |
2747 | ||
2748 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) | |
2749 | { | |
70aff66c | 2750 | intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
3ab9c637 | 2751 | DP_TRAINING_PATTERN_DISABLE); |
a4fc5ed6 KP |
2752 | } |
2753 | ||
2754 | static void | |
ea5b213a | 2755 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 2756 | { |
da63a9f2 | 2757 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
bc7d38a4 | 2758 | enum port port = intel_dig_port->port; |
da63a9f2 | 2759 | struct drm_device *dev = intel_dig_port->base.base.dev; |
a4fc5ed6 | 2760 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab527efc DV |
2761 | struct intel_crtc *intel_crtc = |
2762 | to_intel_crtc(intel_dig_port->base.base.crtc); | |
ea5b213a | 2763 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 2764 | |
c19b0669 PZ |
2765 | /* |
2766 | * DDI code has a strict mode set sequence and we should try to respect | |
2767 | * it, otherwise we might hang the machine in many different ways. So we | |
2768 | * really should be disabling the port only on a complete crtc_disable | |
2769 | * sequence. This function is just called under two conditions on DDI | |
2770 | * code: | |
2771 | * - Link train failed while doing crtc_enable, and on this case we | |
2772 | * really should respect the mode set sequence and wait for a | |
2773 | * crtc_disable. | |
2774 | * - Someone turned the monitor off and intel_dp_check_link_status | |
2775 | * called us. We don't need to disable the whole port on this case, so | |
2776 | * when someone turns the monitor on again, | |
2777 | * intel_ddi_prepare_link_retrain will take care of redoing the link | |
2778 | * train. | |
2779 | */ | |
affa9354 | 2780 | if (HAS_DDI(dev)) |
c19b0669 PZ |
2781 | return; |
2782 | ||
0c33d8d7 | 2783 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
2784 | return; |
2785 | ||
28c97730 | 2786 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 2787 | |
bc7d38a4 | 2788 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
e3421a18 | 2789 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 2790 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
2791 | } else { |
2792 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 2793 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 2794 | } |
fe255d00 | 2795 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 2796 | |
ab527efc DV |
2797 | /* We don't really know why we're doing this */ |
2798 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
5eb08b69 | 2799 | |
493a7081 | 2800 | if (HAS_PCH_IBX(dev) && |
1b39d6f3 | 2801 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
da63a9f2 | 2802 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
31acbcc4 | 2803 | |
5bddd17f EA |
2804 | /* Hardware workaround: leaving our transcoder select |
2805 | * set to transcoder B while it's off will prevent the | |
2806 | * corresponding HDMI output on transcoder A. | |
2807 | * | |
2808 | * Combine this with another hardware workaround: | |
2809 | * transcoder select bit can only be cleared while the | |
2810 | * port is enabled. | |
2811 | */ | |
2812 | DP &= ~DP_PIPEB_SELECT; | |
2813 | I915_WRITE(intel_dp->output_reg, DP); | |
2814 | ||
2815 | /* Changes to enable or select take place the vblank | |
2816 | * after being written. | |
2817 | */ | |
ff50afe9 DV |
2818 | if (WARN_ON(crtc == NULL)) { |
2819 | /* We should never try to disable a port without a crtc | |
2820 | * attached. For paranoia keep the code around for a | |
2821 | * bit. */ | |
31acbcc4 CW |
2822 | POSTING_READ(intel_dp->output_reg); |
2823 | msleep(50); | |
2824 | } else | |
ab527efc | 2825 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
5bddd17f EA |
2826 | } |
2827 | ||
832afda6 | 2828 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
ea5b213a CW |
2829 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
2830 | POSTING_READ(intel_dp->output_reg); | |
f01eca2e | 2831 | msleep(intel_dp->panel_power_down_delay); |
a4fc5ed6 KP |
2832 | } |
2833 | ||
26d61aad KP |
2834 | static bool |
2835 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 2836 | { |
a031d709 RV |
2837 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
2838 | struct drm_device *dev = dig_port->base.base.dev; | |
2839 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2840 | ||
577c7a50 DL |
2841 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
2842 | ||
92fd8fd1 | 2843 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
edb39244 AJ |
2844 | sizeof(intel_dp->dpcd)) == 0) |
2845 | return false; /* aux transfer failed */ | |
92fd8fd1 | 2846 | |
577c7a50 DL |
2847 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
2848 | 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); | |
2849 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); | |
2850 | ||
edb39244 AJ |
2851 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
2852 | return false; /* DPCD not present */ | |
2853 | ||
2293bb5c SK |
2854 | /* Check if the panel supports PSR */ |
2855 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); | |
50003939 JN |
2856 | if (is_edp(intel_dp)) { |
2857 | intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT, | |
2858 | intel_dp->psr_dpcd, | |
2859 | sizeof(intel_dp->psr_dpcd)); | |
a031d709 RV |
2860 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
2861 | dev_priv->psr.sink_support = true; | |
50003939 | 2862 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
a031d709 | 2863 | } |
50003939 JN |
2864 | } |
2865 | ||
06ea66b6 TP |
2866 | /* Training Pattern 3 support */ |
2867 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && | |
2868 | intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { | |
2869 | intel_dp->use_tps3 = true; | |
2870 | DRM_DEBUG_KMS("Displayport TPS3 supported"); | |
2871 | } else | |
2872 | intel_dp->use_tps3 = false; | |
2873 | ||
edb39244 AJ |
2874 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
2875 | DP_DWN_STRM_PORT_PRESENT)) | |
2876 | return true; /* native DP sink */ | |
2877 | ||
2878 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
2879 | return true; /* no per-port downstream info */ | |
2880 | ||
2881 | if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, | |
2882 | intel_dp->downstream_ports, | |
2883 | DP_MAX_DOWNSTREAM_PORTS) == 0) | |
2884 | return false; /* downstream port status fetch failed */ | |
2885 | ||
2886 | return true; | |
92fd8fd1 KP |
2887 | } |
2888 | ||
0d198328 AJ |
2889 | static void |
2890 | intel_dp_probe_oui(struct intel_dp *intel_dp) | |
2891 | { | |
2892 | u8 buf[3]; | |
2893 | ||
2894 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
2895 | return; | |
2896 | ||
4be73780 | 2897 | edp_panel_vdd_on(intel_dp); |
351cfc34 | 2898 | |
0d198328 AJ |
2899 | if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) |
2900 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", | |
2901 | buf[0], buf[1], buf[2]); | |
2902 | ||
2903 | if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) | |
2904 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", | |
2905 | buf[0], buf[1], buf[2]); | |
351cfc34 | 2906 | |
4be73780 | 2907 | edp_panel_vdd_off(intel_dp, false); |
0d198328 AJ |
2908 | } |
2909 | ||
a60f0e38 JB |
2910 | static bool |
2911 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
2912 | { | |
2913 | int ret; | |
2914 | ||
2915 | ret = intel_dp_aux_native_read_retry(intel_dp, | |
2916 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
2917 | sink_irq_vector, 1); | |
2918 | if (!ret) | |
2919 | return false; | |
2920 | ||
2921 | return true; | |
2922 | } | |
2923 | ||
2924 | static void | |
2925 | intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
2926 | { | |
2927 | /* NAK by default */ | |
9324cf7f | 2928 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); |
a60f0e38 JB |
2929 | } |
2930 | ||
a4fc5ed6 KP |
2931 | /* |
2932 | * According to DP spec | |
2933 | * 5.1.2: | |
2934 | * 1. Read DPCD | |
2935 | * 2. Configure link according to Receiver Capabilities | |
2936 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
2937 | * 4. Check link status on receipt of hot-plug interrupt | |
2938 | */ | |
2939 | ||
00c09d70 | 2940 | void |
ea5b213a | 2941 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 2942 | { |
da63a9f2 | 2943 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
a60f0e38 | 2944 | u8 sink_irq_vector; |
93f62dad | 2945 | u8 link_status[DP_LINK_STATUS_SIZE]; |
a60f0e38 | 2946 | |
da63a9f2 | 2947 | if (!intel_encoder->connectors_active) |
d2b996ac | 2948 | return; |
59cd09e1 | 2949 | |
da63a9f2 | 2950 | if (WARN_ON(!intel_encoder->base.crtc)) |
a4fc5ed6 KP |
2951 | return; |
2952 | ||
92fd8fd1 | 2953 | /* Try to read receiver status if the link appears to be up */ |
93f62dad | 2954 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
a4fc5ed6 KP |
2955 | return; |
2956 | } | |
2957 | ||
92fd8fd1 | 2958 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 2959 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
2960 | return; |
2961 | } | |
2962 | ||
a60f0e38 JB |
2963 | /* Try to read the source of the interrupt */ |
2964 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
2965 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
2966 | /* Clear interrupt source */ | |
2967 | intel_dp_aux_native_write_1(intel_dp, | |
2968 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
2969 | sink_irq_vector); | |
2970 | ||
2971 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
2972 | intel_dp_handle_test_request(intel_dp); | |
2973 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
2974 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
2975 | } | |
2976 | ||
1ffdff13 | 2977 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
92fd8fd1 | 2978 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
da63a9f2 | 2979 | drm_get_encoder_name(&intel_encoder->base)); |
33a34e4e JB |
2980 | intel_dp_start_link_train(intel_dp); |
2981 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 | 2982 | intel_dp_stop_link_train(intel_dp); |
33a34e4e | 2983 | } |
a4fc5ed6 | 2984 | } |
a4fc5ed6 | 2985 | |
caf9ab24 | 2986 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 2987 | static enum drm_connector_status |
26d61aad | 2988 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 2989 | { |
caf9ab24 | 2990 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
2991 | uint8_t type; |
2992 | ||
2993 | if (!intel_dp_get_dpcd(intel_dp)) | |
2994 | return connector_status_disconnected; | |
2995 | ||
2996 | /* if there's no downstream port, we're done */ | |
2997 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) | |
26d61aad | 2998 | return connector_status_connected; |
caf9ab24 AJ |
2999 | |
3000 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
3001 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
3002 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
23235177 | 3003 | uint8_t reg; |
caf9ab24 | 3004 | if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, |
23235177 | 3005 | ®, 1)) |
caf9ab24 | 3006 | return connector_status_unknown; |
23235177 AJ |
3007 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
3008 | : connector_status_disconnected; | |
caf9ab24 AJ |
3009 | } |
3010 | ||
3011 | /* If no HPD, poke DDC gently */ | |
3012 | if (drm_probe_ddc(&intel_dp->adapter)) | |
26d61aad | 3013 | return connector_status_connected; |
caf9ab24 AJ |
3014 | |
3015 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
3016 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
3017 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
3018 | if (type == DP_DS_PORT_TYPE_VGA || | |
3019 | type == DP_DS_PORT_TYPE_NON_EDID) | |
3020 | return connector_status_unknown; | |
3021 | } else { | |
3022 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
3023 | DP_DWN_STRM_PORT_TYPE_MASK; | |
3024 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
3025 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
3026 | return connector_status_unknown; | |
3027 | } | |
caf9ab24 AJ |
3028 | |
3029 | /* Anything else is out of spec, warn and ignore */ | |
3030 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 3031 | return connector_status_disconnected; |
71ba9000 AJ |
3032 | } |
3033 | ||
5eb08b69 | 3034 | static enum drm_connector_status |
a9756bb5 | 3035 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 3036 | { |
30add22d | 3037 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1b469639 DL |
3038 | struct drm_i915_private *dev_priv = dev->dev_private; |
3039 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
5eb08b69 ZW |
3040 | enum drm_connector_status status; |
3041 | ||
fe16d949 CW |
3042 | /* Can't disconnect eDP, but you can close the lid... */ |
3043 | if (is_edp(intel_dp)) { | |
30add22d | 3044 | status = intel_panel_detect(dev); |
fe16d949 CW |
3045 | if (status == connector_status_unknown) |
3046 | status = connector_status_connected; | |
3047 | return status; | |
3048 | } | |
01cb9ea6 | 3049 | |
1b469639 DL |
3050 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
3051 | return connector_status_disconnected; | |
3052 | ||
26d61aad | 3053 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
3054 | } |
3055 | ||
a4fc5ed6 | 3056 | static enum drm_connector_status |
a9756bb5 | 3057 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 3058 | { |
30add22d | 3059 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
a4fc5ed6 | 3060 | struct drm_i915_private *dev_priv = dev->dev_private; |
34f2be46 | 3061 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
10f76a38 | 3062 | uint32_t bit; |
5eb08b69 | 3063 | |
35aad75f JB |
3064 | /* Can't disconnect eDP, but you can close the lid... */ |
3065 | if (is_edp(intel_dp)) { | |
3066 | enum drm_connector_status status; | |
3067 | ||
3068 | status = intel_panel_detect(dev); | |
3069 | if (status == connector_status_unknown) | |
3070 | status = connector_status_connected; | |
3071 | return status; | |
3072 | } | |
3073 | ||
232a6ee9 TP |
3074 | if (IS_VALLEYVIEW(dev)) { |
3075 | switch (intel_dig_port->port) { | |
3076 | case PORT_B: | |
3077 | bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; | |
3078 | break; | |
3079 | case PORT_C: | |
3080 | bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; | |
3081 | break; | |
3082 | case PORT_D: | |
3083 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; | |
3084 | break; | |
3085 | default: | |
3086 | return connector_status_unknown; | |
3087 | } | |
3088 | } else { | |
3089 | switch (intel_dig_port->port) { | |
3090 | case PORT_B: | |
3091 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; | |
3092 | break; | |
3093 | case PORT_C: | |
3094 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; | |
3095 | break; | |
3096 | case PORT_D: | |
3097 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | |
3098 | break; | |
3099 | default: | |
3100 | return connector_status_unknown; | |
3101 | } | |
a4fc5ed6 KP |
3102 | } |
3103 | ||
10f76a38 | 3104 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
a4fc5ed6 KP |
3105 | return connector_status_disconnected; |
3106 | ||
26d61aad | 3107 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
3108 | } |
3109 | ||
8c241fef KP |
3110 | static struct edid * |
3111 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
3112 | { | |
9cd300e0 | 3113 | struct intel_connector *intel_connector = to_intel_connector(connector); |
d6f24d0f | 3114 | |
9cd300e0 JN |
3115 | /* use cached edid if we have one */ |
3116 | if (intel_connector->edid) { | |
9cd300e0 JN |
3117 | /* invalid edid */ |
3118 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
3119 | return NULL; |
3120 | ||
55e9edeb | 3121 | return drm_edid_duplicate(intel_connector->edid); |
d6f24d0f | 3122 | } |
8c241fef | 3123 | |
9cd300e0 | 3124 | return drm_get_edid(connector, adapter); |
8c241fef KP |
3125 | } |
3126 | ||
3127 | static int | |
3128 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) | |
3129 | { | |
9cd300e0 | 3130 | struct intel_connector *intel_connector = to_intel_connector(connector); |
8c241fef | 3131 | |
9cd300e0 JN |
3132 | /* use cached edid if we have one */ |
3133 | if (intel_connector->edid) { | |
3134 | /* invalid edid */ | |
3135 | if (IS_ERR(intel_connector->edid)) | |
3136 | return 0; | |
3137 | ||
3138 | return intel_connector_update_modes(connector, | |
3139 | intel_connector->edid); | |
d6f24d0f JB |
3140 | } |
3141 | ||
9cd300e0 | 3142 | return intel_ddc_get_modes(connector, adapter); |
8c241fef KP |
3143 | } |
3144 | ||
a9756bb5 ZW |
3145 | static enum drm_connector_status |
3146 | intel_dp_detect(struct drm_connector *connector, bool force) | |
3147 | { | |
3148 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
d63885da PZ |
3149 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3150 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 3151 | struct drm_device *dev = connector->dev; |
c8c8fb33 | 3152 | struct drm_i915_private *dev_priv = dev->dev_private; |
a9756bb5 ZW |
3153 | enum drm_connector_status status; |
3154 | struct edid *edid = NULL; | |
3155 | ||
c8c8fb33 PZ |
3156 | intel_runtime_pm_get(dev_priv); |
3157 | ||
164c8598 CW |
3158 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
3159 | connector->base.id, drm_get_connector_name(connector)); | |
3160 | ||
a9756bb5 ZW |
3161 | intel_dp->has_audio = false; |
3162 | ||
3163 | if (HAS_PCH_SPLIT(dev)) | |
3164 | status = ironlake_dp_detect(intel_dp); | |
3165 | else | |
3166 | status = g4x_dp_detect(intel_dp); | |
1b9be9d0 | 3167 | |
a9756bb5 | 3168 | if (status != connector_status_connected) |
c8c8fb33 | 3169 | goto out; |
a9756bb5 | 3170 | |
0d198328 AJ |
3171 | intel_dp_probe_oui(intel_dp); |
3172 | ||
c3e5f67b DV |
3173 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
3174 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); | |
f684960e | 3175 | } else { |
8c241fef | 3176 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
f684960e CW |
3177 | if (edid) { |
3178 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
f684960e CW |
3179 | kfree(edid); |
3180 | } | |
a9756bb5 ZW |
3181 | } |
3182 | ||
d63885da PZ |
3183 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
3184 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
c8c8fb33 PZ |
3185 | status = connector_status_connected; |
3186 | ||
3187 | out: | |
3188 | intel_runtime_pm_put(dev_priv); | |
3189 | return status; | |
a4fc5ed6 KP |
3190 | } |
3191 | ||
3192 | static int intel_dp_get_modes(struct drm_connector *connector) | |
3193 | { | |
df0e9248 | 3194 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e | 3195 | struct intel_connector *intel_connector = to_intel_connector(connector); |
fa90ecef | 3196 | struct drm_device *dev = connector->dev; |
32f9d658 | 3197 | int ret; |
a4fc5ed6 KP |
3198 | |
3199 | /* We should parse the EDID data and find out if it has an audio sink | |
3200 | */ | |
3201 | ||
8c241fef | 3202 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
f8779fda | 3203 | if (ret) |
32f9d658 ZW |
3204 | return ret; |
3205 | ||
f8779fda | 3206 | /* if eDP has no EDID, fall back to fixed mode */ |
dd06f90e | 3207 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
f8779fda | 3208 | struct drm_display_mode *mode; |
dd06f90e JN |
3209 | mode = drm_mode_duplicate(dev, |
3210 | intel_connector->panel.fixed_mode); | |
f8779fda | 3211 | if (mode) { |
32f9d658 ZW |
3212 | drm_mode_probed_add(connector, mode); |
3213 | return 1; | |
3214 | } | |
3215 | } | |
3216 | return 0; | |
a4fc5ed6 KP |
3217 | } |
3218 | ||
1aad7ac0 CW |
3219 | static bool |
3220 | intel_dp_detect_audio(struct drm_connector *connector) | |
3221 | { | |
3222 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
3223 | struct edid *edid; | |
3224 | bool has_audio = false; | |
3225 | ||
8c241fef | 3226 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
1aad7ac0 CW |
3227 | if (edid) { |
3228 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
3229 | kfree(edid); |
3230 | } | |
3231 | ||
3232 | return has_audio; | |
3233 | } | |
3234 | ||
f684960e CW |
3235 | static int |
3236 | intel_dp_set_property(struct drm_connector *connector, | |
3237 | struct drm_property *property, | |
3238 | uint64_t val) | |
3239 | { | |
e953fd7b | 3240 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
53b41837 | 3241 | struct intel_connector *intel_connector = to_intel_connector(connector); |
da63a9f2 PZ |
3242 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
3243 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
f684960e CW |
3244 | int ret; |
3245 | ||
662595df | 3246 | ret = drm_object_property_set_value(&connector->base, property, val); |
f684960e CW |
3247 | if (ret) |
3248 | return ret; | |
3249 | ||
3f43c48d | 3250 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
3251 | int i = val; |
3252 | bool has_audio; | |
3253 | ||
3254 | if (i == intel_dp->force_audio) | |
f684960e CW |
3255 | return 0; |
3256 | ||
1aad7ac0 | 3257 | intel_dp->force_audio = i; |
f684960e | 3258 | |
c3e5f67b | 3259 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
3260 | has_audio = intel_dp_detect_audio(connector); |
3261 | else | |
c3e5f67b | 3262 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
3263 | |
3264 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
3265 | return 0; |
3266 | ||
1aad7ac0 | 3267 | intel_dp->has_audio = has_audio; |
f684960e CW |
3268 | goto done; |
3269 | } | |
3270 | ||
e953fd7b | 3271 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
3272 | bool old_auto = intel_dp->color_range_auto; |
3273 | uint32_t old_range = intel_dp->color_range; | |
3274 | ||
55bc60db VS |
3275 | switch (val) { |
3276 | case INTEL_BROADCAST_RGB_AUTO: | |
3277 | intel_dp->color_range_auto = true; | |
3278 | break; | |
3279 | case INTEL_BROADCAST_RGB_FULL: | |
3280 | intel_dp->color_range_auto = false; | |
3281 | intel_dp->color_range = 0; | |
3282 | break; | |
3283 | case INTEL_BROADCAST_RGB_LIMITED: | |
3284 | intel_dp->color_range_auto = false; | |
3285 | intel_dp->color_range = DP_COLOR_RANGE_16_235; | |
3286 | break; | |
3287 | default: | |
3288 | return -EINVAL; | |
3289 | } | |
ae4edb80 DV |
3290 | |
3291 | if (old_auto == intel_dp->color_range_auto && | |
3292 | old_range == intel_dp->color_range) | |
3293 | return 0; | |
3294 | ||
e953fd7b CW |
3295 | goto done; |
3296 | } | |
3297 | ||
53b41837 YN |
3298 | if (is_edp(intel_dp) && |
3299 | property == connector->dev->mode_config.scaling_mode_property) { | |
3300 | if (val == DRM_MODE_SCALE_NONE) { | |
3301 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
3302 | return -EINVAL; | |
3303 | } | |
3304 | ||
3305 | if (intel_connector->panel.fitting_mode == val) { | |
3306 | /* the eDP scaling property is not changed */ | |
3307 | return 0; | |
3308 | } | |
3309 | intel_connector->panel.fitting_mode = val; | |
3310 | ||
3311 | goto done; | |
3312 | } | |
3313 | ||
f684960e CW |
3314 | return -EINVAL; |
3315 | ||
3316 | done: | |
c0c36b94 CW |
3317 | if (intel_encoder->base.crtc) |
3318 | intel_crtc_restore_mode(intel_encoder->base.crtc); | |
f684960e CW |
3319 | |
3320 | return 0; | |
3321 | } | |
3322 | ||
a4fc5ed6 | 3323 | static void |
73845adf | 3324 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 3325 | { |
1d508706 | 3326 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 3327 | |
9cd300e0 JN |
3328 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
3329 | kfree(intel_connector->edid); | |
3330 | ||
acd8db10 PZ |
3331 | /* Can't call is_edp() since the encoder may have been destroyed |
3332 | * already. */ | |
3333 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
1d508706 | 3334 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 3335 | |
a4fc5ed6 | 3336 | drm_connector_cleanup(connector); |
55f78c43 | 3337 | kfree(connector); |
a4fc5ed6 KP |
3338 | } |
3339 | ||
00c09d70 | 3340 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 3341 | { |
da63a9f2 PZ |
3342 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
3343 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
bd173813 | 3344 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
24d05927 DV |
3345 | |
3346 | i2c_del_adapter(&intel_dp->adapter); | |
3347 | drm_encoder_cleanup(encoder); | |
bd943159 KP |
3348 | if (is_edp(intel_dp)) { |
3349 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
bd173813 | 3350 | mutex_lock(&dev->mode_config.mutex); |
4be73780 | 3351 | edp_panel_vdd_off_sync(intel_dp); |
bd173813 | 3352 | mutex_unlock(&dev->mode_config.mutex); |
bd943159 | 3353 | } |
da63a9f2 | 3354 | kfree(intel_dig_port); |
24d05927 DV |
3355 | } |
3356 | ||
a4fc5ed6 | 3357 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
2bd2ad64 | 3358 | .dpms = intel_connector_dpms, |
a4fc5ed6 KP |
3359 | .detect = intel_dp_detect, |
3360 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 3361 | .set_property = intel_dp_set_property, |
73845adf | 3362 | .destroy = intel_dp_connector_destroy, |
a4fc5ed6 KP |
3363 | }; |
3364 | ||
3365 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
3366 | .get_modes = intel_dp_get_modes, | |
3367 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 3368 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
3369 | }; |
3370 | ||
a4fc5ed6 | 3371 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 3372 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
3373 | }; |
3374 | ||
995b6762 | 3375 | static void |
21d40d37 | 3376 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 3377 | { |
fa90ecef | 3378 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
c8110e52 | 3379 | |
885a5014 | 3380 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 3381 | } |
6207937d | 3382 | |
e3421a18 ZW |
3383 | /* Return which DP Port should be selected for Transcoder DP control */ |
3384 | int | |
0206e353 | 3385 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
e3421a18 ZW |
3386 | { |
3387 | struct drm_device *dev = crtc->dev; | |
fa90ecef PZ |
3388 | struct intel_encoder *intel_encoder; |
3389 | struct intel_dp *intel_dp; | |
e3421a18 | 3390 | |
fa90ecef PZ |
3391 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
3392 | intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
e3421a18 | 3393 | |
fa90ecef PZ |
3394 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
3395 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
ea5b213a | 3396 | return intel_dp->output_reg; |
e3421a18 | 3397 | } |
ea5b213a | 3398 | |
e3421a18 ZW |
3399 | return -1; |
3400 | } | |
3401 | ||
36e83a18 | 3402 | /* check the VBT to see whether the eDP is on DP-D port */ |
5d8a7752 | 3403 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
36e83a18 ZY |
3404 | { |
3405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
768f69c9 | 3406 | union child_device_config *p_child; |
36e83a18 | 3407 | int i; |
5d8a7752 VS |
3408 | static const short port_mapping[] = { |
3409 | [PORT_B] = PORT_IDPB, | |
3410 | [PORT_C] = PORT_IDPC, | |
3411 | [PORT_D] = PORT_IDPD, | |
3412 | }; | |
36e83a18 | 3413 | |
3b32a35b VS |
3414 | if (port == PORT_A) |
3415 | return true; | |
3416 | ||
41aa3448 | 3417 | if (!dev_priv->vbt.child_dev_num) |
36e83a18 ZY |
3418 | return false; |
3419 | ||
41aa3448 RV |
3420 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
3421 | p_child = dev_priv->vbt.child_dev + i; | |
36e83a18 | 3422 | |
5d8a7752 | 3423 | if (p_child->common.dvo_port == port_mapping[port] && |
f02586df VS |
3424 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
3425 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) | |
36e83a18 ZY |
3426 | return true; |
3427 | } | |
3428 | return false; | |
3429 | } | |
3430 | ||
f684960e CW |
3431 | static void |
3432 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
3433 | { | |
53b41837 YN |
3434 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3435 | ||
3f43c48d | 3436 | intel_attach_force_audio_property(connector); |
e953fd7b | 3437 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 3438 | intel_dp->color_range_auto = true; |
53b41837 YN |
3439 | |
3440 | if (is_edp(intel_dp)) { | |
3441 | drm_mode_create_scaling_mode_property(connector->dev); | |
6de6d846 RC |
3442 | drm_object_attach_property( |
3443 | &connector->base, | |
53b41837 | 3444 | connector->dev->mode_config.scaling_mode_property, |
8e740cd1 YN |
3445 | DRM_MODE_SCALE_ASPECT); |
3446 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
53b41837 | 3447 | } |
f684960e CW |
3448 | } |
3449 | ||
67a54566 DV |
3450 | static void |
3451 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
f30d26e4 JN |
3452 | struct intel_dp *intel_dp, |
3453 | struct edp_power_seq *out) | |
67a54566 DV |
3454 | { |
3455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3456 | struct edp_power_seq cur, vbt, spec, final; | |
3457 | u32 pp_on, pp_off, pp_div, pp; | |
bf13e81b | 3458 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
453c5420 JB |
3459 | |
3460 | if (HAS_PCH_SPLIT(dev)) { | |
bf13e81b | 3461 | pp_ctrl_reg = PCH_PP_CONTROL; |
453c5420 JB |
3462 | pp_on_reg = PCH_PP_ON_DELAYS; |
3463 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
3464 | pp_div_reg = PCH_PP_DIVISOR; | |
3465 | } else { | |
bf13e81b JN |
3466 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
3467 | ||
3468 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); | |
3469 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
3470 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
3471 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 | 3472 | } |
67a54566 DV |
3473 | |
3474 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
3475 | * the very first thing. */ | |
453c5420 | 3476 | pp = ironlake_get_pp_control(intel_dp); |
bf13e81b | 3477 | I915_WRITE(pp_ctrl_reg, pp); |
67a54566 | 3478 | |
453c5420 JB |
3479 | pp_on = I915_READ(pp_on_reg); |
3480 | pp_off = I915_READ(pp_off_reg); | |
3481 | pp_div = I915_READ(pp_div_reg); | |
67a54566 DV |
3482 | |
3483 | /* Pull timing values out of registers */ | |
3484 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
3485 | PANEL_POWER_UP_DELAY_SHIFT; | |
3486 | ||
3487 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
3488 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
3489 | ||
3490 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
3491 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
3492 | ||
3493 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
3494 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
3495 | ||
3496 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
3497 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
3498 | ||
3499 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
3500 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
3501 | ||
41aa3448 | 3502 | vbt = dev_priv->vbt.edp_pps; |
67a54566 DV |
3503 | |
3504 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
3505 | * our hw here, which are all in 100usec. */ | |
3506 | spec.t1_t3 = 210 * 10; | |
3507 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
3508 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
3509 | spec.t10 = 500 * 10; | |
3510 | /* This one is special and actually in units of 100ms, but zero | |
3511 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
3512 | * table multiplies it with 1000 to make it in units of 100usec, | |
3513 | * too. */ | |
3514 | spec.t11_t12 = (510 + 100) * 10; | |
3515 | ||
3516 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
3517 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
3518 | ||
3519 | /* Use the max of the register settings and vbt. If both are | |
3520 | * unset, fall back to the spec limits. */ | |
3521 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ | |
3522 | spec.field : \ | |
3523 | max(cur.field, vbt.field)) | |
3524 | assign_final(t1_t3); | |
3525 | assign_final(t8); | |
3526 | assign_final(t9); | |
3527 | assign_final(t10); | |
3528 | assign_final(t11_t12); | |
3529 | #undef assign_final | |
3530 | ||
3531 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) | |
3532 | intel_dp->panel_power_up_delay = get_delay(t1_t3); | |
3533 | intel_dp->backlight_on_delay = get_delay(t8); | |
3534 | intel_dp->backlight_off_delay = get_delay(t9); | |
3535 | intel_dp->panel_power_down_delay = get_delay(t10); | |
3536 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
3537 | #undef get_delay | |
3538 | ||
f30d26e4 JN |
3539 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
3540 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
3541 | intel_dp->panel_power_cycle_delay); | |
3542 | ||
3543 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
3544 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
3545 | ||
3546 | if (out) | |
3547 | *out = final; | |
3548 | } | |
3549 | ||
3550 | static void | |
3551 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
3552 | struct intel_dp *intel_dp, | |
3553 | struct edp_power_seq *seq) | |
3554 | { | |
3555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
453c5420 JB |
3556 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
3557 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); | |
3558 | int pp_on_reg, pp_off_reg, pp_div_reg; | |
3559 | ||
3560 | if (HAS_PCH_SPLIT(dev)) { | |
3561 | pp_on_reg = PCH_PP_ON_DELAYS; | |
3562 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
3563 | pp_div_reg = PCH_PP_DIVISOR; | |
3564 | } else { | |
bf13e81b JN |
3565 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
3566 | ||
3567 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
3568 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
3569 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 JB |
3570 | } |
3571 | ||
b2f19d1a PZ |
3572 | /* |
3573 | * And finally store the new values in the power sequencer. The | |
3574 | * backlight delays are set to 1 because we do manual waits on them. For | |
3575 | * T8, even BSpec recommends doing it. For T9, if we don't do this, | |
3576 | * we'll end up waiting for the backlight off delay twice: once when we | |
3577 | * do the manual sleep, and once when we disable the panel and wait for | |
3578 | * the PP_STATUS bit to become zero. | |
3579 | */ | |
f30d26e4 | 3580 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
b2f19d1a PZ |
3581 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
3582 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 3583 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
3584 | /* Compute the divisor for the pp clock, simply match the Bspec |
3585 | * formula. */ | |
453c5420 | 3586 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
f30d26e4 | 3587 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
67a54566 DV |
3588 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
3589 | ||
3590 | /* Haswell doesn't have any port selection bits for the panel | |
3591 | * power sequencer any more. */ | |
bc7d38a4 | 3592 | if (IS_VALLEYVIEW(dev)) { |
bf13e81b JN |
3593 | if (dp_to_dig_port(intel_dp)->port == PORT_B) |
3594 | port_sel = PANEL_PORT_SELECT_DPB_VLV; | |
3595 | else | |
3596 | port_sel = PANEL_PORT_SELECT_DPC_VLV; | |
bc7d38a4 ID |
3597 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
3598 | if (dp_to_dig_port(intel_dp)->port == PORT_A) | |
a24c144c | 3599 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 3600 | else |
a24c144c | 3601 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
3602 | } |
3603 | ||
453c5420 JB |
3604 | pp_on |= port_sel; |
3605 | ||
3606 | I915_WRITE(pp_on_reg, pp_on); | |
3607 | I915_WRITE(pp_off_reg, pp_off); | |
3608 | I915_WRITE(pp_div_reg, pp_div); | |
67a54566 | 3609 | |
67a54566 | 3610 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
453c5420 JB |
3611 | I915_READ(pp_on_reg), |
3612 | I915_READ(pp_off_reg), | |
3613 | I915_READ(pp_div_reg)); | |
f684960e CW |
3614 | } |
3615 | ||
ed92f0b2 | 3616 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
0095e6dc PZ |
3617 | struct intel_connector *intel_connector, |
3618 | struct edp_power_seq *power_seq) | |
ed92f0b2 PZ |
3619 | { |
3620 | struct drm_connector *connector = &intel_connector->base; | |
3621 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3622 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
3623 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3624 | struct drm_display_mode *fixed_mode = NULL; | |
ed92f0b2 PZ |
3625 | bool has_dpcd; |
3626 | struct drm_display_mode *scan; | |
3627 | struct edid *edid; | |
3628 | ||
3629 | if (!is_edp(intel_dp)) | |
3630 | return true; | |
3631 | ||
ed92f0b2 | 3632 | /* Cache DPCD and EDID for edp. */ |
4be73780 | 3633 | edp_panel_vdd_on(intel_dp); |
ed92f0b2 | 3634 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
4be73780 | 3635 | edp_panel_vdd_off(intel_dp, false); |
ed92f0b2 PZ |
3636 | |
3637 | if (has_dpcd) { | |
3638 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) | |
3639 | dev_priv->no_aux_handshake = | |
3640 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
3641 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
3642 | } else { | |
3643 | /* if this fails, presume the device is a ghost */ | |
3644 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
ed92f0b2 PZ |
3645 | return false; |
3646 | } | |
3647 | ||
3648 | /* We now know it's not a ghost, init power sequence regs. */ | |
0095e6dc | 3649 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); |
ed92f0b2 | 3650 | |
ed92f0b2 PZ |
3651 | edid = drm_get_edid(connector, &intel_dp->adapter); |
3652 | if (edid) { | |
3653 | if (drm_add_edid_modes(connector, edid)) { | |
3654 | drm_mode_connector_update_edid_property(connector, | |
3655 | edid); | |
3656 | drm_edid_to_eld(connector, edid); | |
3657 | } else { | |
3658 | kfree(edid); | |
3659 | edid = ERR_PTR(-EINVAL); | |
3660 | } | |
3661 | } else { | |
3662 | edid = ERR_PTR(-ENOENT); | |
3663 | } | |
3664 | intel_connector->edid = edid; | |
3665 | ||
3666 | /* prefer fixed mode from EDID if available */ | |
3667 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
3668 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
3669 | fixed_mode = drm_mode_duplicate(dev, scan); | |
3670 | break; | |
3671 | } | |
3672 | } | |
3673 | ||
3674 | /* fallback to VBT if available for eDP */ | |
3675 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
3676 | fixed_mode = drm_mode_duplicate(dev, | |
3677 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
3678 | if (fixed_mode) | |
3679 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
3680 | } | |
3681 | ||
ed92f0b2 PZ |
3682 | intel_panel_init(&intel_connector->panel, fixed_mode); |
3683 | intel_panel_setup_backlight(connector); | |
3684 | ||
3685 | return true; | |
3686 | } | |
3687 | ||
16c25533 | 3688 | bool |
f0fec3f2 PZ |
3689 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
3690 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 3691 | { |
f0fec3f2 PZ |
3692 | struct drm_connector *connector = &intel_connector->base; |
3693 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
3694 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
3695 | struct drm_device *dev = intel_encoder->base.dev; | |
a4fc5ed6 | 3696 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 3697 | enum port port = intel_dig_port->port; |
0095e6dc | 3698 | struct edp_power_seq power_seq = { 0 }; |
5eb08b69 | 3699 | const char *name = NULL; |
b2a14755 | 3700 | int type, error; |
a4fc5ed6 | 3701 | |
ec5b01dd DL |
3702 | /* intel_dp vfuncs */ |
3703 | if (IS_VALLEYVIEW(dev)) | |
3704 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; | |
3705 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
3706 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; | |
3707 | else if (HAS_PCH_SPLIT(dev)) | |
3708 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; | |
3709 | else | |
3710 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; | |
3711 | ||
0767935e DV |
3712 | /* Preserve the current hw state. */ |
3713 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 3714 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 3715 | |
3b32a35b | 3716 | if (intel_dp_is_edp(dev, port)) |
b329530c | 3717 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
3718 | else |
3719 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 3720 | |
f7d24902 ID |
3721 | /* |
3722 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
3723 | * for DP the encoder type can be set by the caller to | |
3724 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
3725 | */ | |
3726 | if (type == DRM_MODE_CONNECTOR_eDP) | |
3727 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
3728 | ||
e7281eab ID |
3729 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
3730 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
3731 | port_name(port)); | |
3732 | ||
b329530c | 3733 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
3734 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
3735 | ||
a4fc5ed6 KP |
3736 | connector->interlace_allowed = true; |
3737 | connector->doublescan_allowed = 0; | |
3738 | ||
f0fec3f2 | 3739 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 3740 | edp_panel_vdd_work); |
a4fc5ed6 | 3741 | |
df0e9248 | 3742 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
3743 | drm_sysfs_connector_add(connector); |
3744 | ||
affa9354 | 3745 | if (HAS_DDI(dev)) |
bcbc889b PZ |
3746 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
3747 | else | |
3748 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
3749 | ||
9ed35ab1 PZ |
3750 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
3751 | if (HAS_DDI(dev)) { | |
3752 | switch (intel_dig_port->port) { | |
3753 | case PORT_A: | |
3754 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; | |
3755 | break; | |
3756 | case PORT_B: | |
3757 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; | |
3758 | break; | |
3759 | case PORT_C: | |
3760 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; | |
3761 | break; | |
3762 | case PORT_D: | |
3763 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; | |
3764 | break; | |
3765 | default: | |
3766 | BUG(); | |
3767 | } | |
3768 | } | |
e8cb4558 | 3769 | |
a4fc5ed6 | 3770 | /* Set up the DDC bus. */ |
ab9d7c30 PZ |
3771 | switch (port) { |
3772 | case PORT_A: | |
1d843f9d | 3773 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
3774 | name = "DPDDC-A"; |
3775 | break; | |
3776 | case PORT_B: | |
1d843f9d | 3777 | intel_encoder->hpd_pin = HPD_PORT_B; |
ab9d7c30 PZ |
3778 | name = "DPDDC-B"; |
3779 | break; | |
3780 | case PORT_C: | |
1d843f9d | 3781 | intel_encoder->hpd_pin = HPD_PORT_C; |
ab9d7c30 PZ |
3782 | name = "DPDDC-C"; |
3783 | break; | |
3784 | case PORT_D: | |
1d843f9d | 3785 | intel_encoder->hpd_pin = HPD_PORT_D; |
ab9d7c30 PZ |
3786 | name = "DPDDC-D"; |
3787 | break; | |
3788 | default: | |
ad1c0b19 | 3789 | BUG(); |
5eb08b69 ZW |
3790 | } |
3791 | ||
0095e6dc PZ |
3792 | if (is_edp(intel_dp)) |
3793 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); | |
3794 | ||
b2a14755 PZ |
3795 | error = intel_dp_i2c_init(intel_dp, intel_connector, name); |
3796 | WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n", | |
3797 | error, port_name(port)); | |
c1f05264 | 3798 | |
2b28bb1b RV |
3799 | intel_dp->psr_setup_done = false; |
3800 | ||
0095e6dc | 3801 | if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { |
15b1d171 PZ |
3802 | i2c_del_adapter(&intel_dp->adapter); |
3803 | if (is_edp(intel_dp)) { | |
3804 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
3805 | mutex_lock(&dev->mode_config.mutex); | |
4be73780 | 3806 | edp_panel_vdd_off_sync(intel_dp); |
15b1d171 PZ |
3807 | mutex_unlock(&dev->mode_config.mutex); |
3808 | } | |
b2f246a8 PZ |
3809 | drm_sysfs_connector_remove(connector); |
3810 | drm_connector_cleanup(connector); | |
16c25533 | 3811 | return false; |
b2f246a8 | 3812 | } |
32f9d658 | 3813 | |
f684960e CW |
3814 | intel_dp_add_properties(intel_dp, connector); |
3815 | ||
a4fc5ed6 KP |
3816 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
3817 | * 0xd. Failure to do so will result in spurious interrupts being | |
3818 | * generated on the port when a cable is not attached. | |
3819 | */ | |
3820 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
3821 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
3822 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
3823 | } | |
16c25533 PZ |
3824 | |
3825 | return true; | |
a4fc5ed6 | 3826 | } |
f0fec3f2 PZ |
3827 | |
3828 | void | |
3829 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) | |
3830 | { | |
3831 | struct intel_digital_port *intel_dig_port; | |
3832 | struct intel_encoder *intel_encoder; | |
3833 | struct drm_encoder *encoder; | |
3834 | struct intel_connector *intel_connector; | |
3835 | ||
b14c5679 | 3836 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 PZ |
3837 | if (!intel_dig_port) |
3838 | return; | |
3839 | ||
b14c5679 | 3840 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
f0fec3f2 PZ |
3841 | if (!intel_connector) { |
3842 | kfree(intel_dig_port); | |
3843 | return; | |
3844 | } | |
3845 | ||
3846 | intel_encoder = &intel_dig_port->base; | |
3847 | encoder = &intel_encoder->base; | |
3848 | ||
3849 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, | |
3850 | DRM_MODE_ENCODER_TMDS); | |
3851 | ||
5bfe2ac0 | 3852 | intel_encoder->compute_config = intel_dp_compute_config; |
b934223d | 3853 | intel_encoder->mode_set = intel_dp_mode_set; |
00c09d70 PZ |
3854 | intel_encoder->disable = intel_disable_dp; |
3855 | intel_encoder->post_disable = intel_post_disable_dp; | |
3856 | intel_encoder->get_hw_state = intel_dp_get_hw_state; | |
045ac3b5 | 3857 | intel_encoder->get_config = intel_dp_get_config; |
ab1f90f9 | 3858 | if (IS_VALLEYVIEW(dev)) { |
ecff4f3b | 3859 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
3860 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
3861 | intel_encoder->enable = vlv_enable_dp; | |
3862 | } else { | |
ecff4f3b JN |
3863 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
3864 | intel_encoder->enable = g4x_enable_dp; | |
ab1f90f9 | 3865 | } |
f0fec3f2 | 3866 | |
174edf1f | 3867 | intel_dig_port->port = port; |
f0fec3f2 PZ |
3868 | intel_dig_port->dp.output_reg = output_reg; |
3869 | ||
00c09d70 | 3870 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
f0fec3f2 PZ |
3871 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
3872 | intel_encoder->cloneable = false; | |
3873 | intel_encoder->hot_plug = intel_dp_hot_plug; | |
3874 | ||
15b1d171 PZ |
3875 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { |
3876 | drm_encoder_cleanup(encoder); | |
3877 | kfree(intel_dig_port); | |
b2f246a8 | 3878 | kfree(intel_connector); |
15b1d171 | 3879 | } |
f0fec3f2 | 3880 | } |