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drm/i915/lvds: Restore initial HW state during encoder enabling
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf 50struct dp_link_dpll {
840b32b7 51 int clock;
9dd4ffdf
CML		 52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
840b32b7 56 { 162000,
9dd4ffdf 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
840b32b7 58 { 270000,
9dd4ffdf
CML		 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
840b32b7 63 { 162000,
9dd4ffdf 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
840b32b7 65 { 270000,
9dd4ffdf
CML		 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5 69static const struct dp_link_dpll vlv_dpll[] = {
840b32b7 70 { 162000,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
840b32b7 72 { 270000,
65ce4bf5
CML		 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
840b32b7 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
ef9348c8 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
840b32b7 88 { 270000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
840b32b7 90 { 540000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8
CML		 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15
VS		 97 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 99
cfcb0fc9
JB		 100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
da63a9f2
PZ		 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 112}
113
68b4d824 114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 115{
68b4d824
ID		 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 119}
120
df0e9248
CW		 121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
fa90ecef 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 124}
125
ea5b213a 126static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
f21a2198 132static void intel_dp_unset_edid(struct intel_dp *intel_dp);
a4fc5ed6 133
ed4e9c1d
VS		 134static int
135intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 136{
7183dc29 137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 138
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
141 case DP_LINK_BW_2_7:
1db10e28 142 case DP_LINK_BW_5_4:
d4eead50 143 break;
a4fc5ed6 144 default:
d4eead50
ID		 145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
146 max_link_bw);
a4fc5ed6
KP		 147 max_link_bw = DP_LINK_BW_1_62;
148 break;
149 }
150 return max_link_bw;
151}
152
eeb6324d
PZ		 153static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
154{
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
eeb6324d
PZ		 156 u8 source_max, sink_max;
157
ccb1a831 158 source_max = intel_dig_port->max_lanes;
eeb6324d
PZ		 159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
160
161 return min(source_max, sink_max);
162}
163
cd9dde44
AJ		 164/*
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
167 *
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
169 *
170 * 270000 * 1 * 8 / 10 == 216000
171 *
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
176 *
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
179 */
180
a4fc5ed6 181static int
c898261c 182intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 183{
cd9dde44 184 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 185}
186
fe27d53e
DA		 187static int
188intel_dp_max_data_rate(int max_link_clock, int max_lanes)
189{
190 return (max_link_clock * max_lanes * 8) / 10;
191}
192
c19de8eb 193static enum drm_mode_status
a4fc5ed6
KP		 194intel_dp_mode_valid(struct drm_connector *connector,
195 struct drm_display_mode *mode)
196{
df0e9248 197 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 198 struct intel_connector *intel_connector = to_intel_connector(connector);
199 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 200 int target_clock = mode->clock;
201 int max_rate, mode_rate, max_lanes, max_link_clock;
799487f5 202 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
a4fc5ed6 203
dd06f90e
JN		 204 if (is_edp(intel_dp) && fixed_mode) {
205 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 206 return MODE_PANEL;
207
dd06f90e 208 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 209 return MODE_PANEL;
03afc4a2
DV		 210
211 target_clock = fixed_mode->clock;
7de56f43
ZY		 212 }
213
50fec21a 214 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 215 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 216
217 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
218 mode_rate = intel_dp_link_required(target_clock, 18);
219
799487f5 220 if (mode_rate > max_rate || target_clock > max_dotclk)
c4867936 221 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 222
223 if (mode->clock < 10000)
224 return MODE_CLOCK_LOW;
225
0af78a2b
DV		 226 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
227 return MODE_H_ILLEGAL;
228
a4fc5ed6
KP		 229 return MODE_OK;
230}
231
a4f1289e 232uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 233{
234 int i;
235 uint32_t v = 0;
236
237 if (src_bytes > 4)
238 src_bytes = 4;
239 for (i = 0; i < src_bytes; i++)
240 v |= ((uint32_t) src[i]) << ((3-i) * 8);
241 return v;
242}
243
c2af70e2 244static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 245{
246 int i;
247 if (dst_bytes > 4)
248 dst_bytes = 4;
249 for (i = 0; i < dst_bytes; i++)
250 dst[i] = src >> ((3-i) * 8);
251}
252
bf13e81b
JN		 253static void
254intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 255 struct intel_dp *intel_dp);
bf13e81b
JN		 256static void
257intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 258 struct intel_dp *intel_dp);
bf13e81b 259
773538e8
VS		 260static void pps_lock(struct intel_dp *intel_dp)
261{
262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
263 struct intel_encoder *encoder = &intel_dig_port->base;
264 struct drm_device *dev = encoder->base.dev;
fac5e23e 265 struct drm_i915_private *dev_priv = to_i915(dev);
773538e8
VS		 266 enum intel_display_power_domain power_domain;
267
268 /*
269 * See vlv_power_sequencer_reset() why we need
270 * a power domain reference here.
271 */
25f78f58 272 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 273 intel_display_power_get(dev_priv, power_domain);
274
275 mutex_lock(&dev_priv->pps_mutex);
276}
277
278static void pps_unlock(struct intel_dp *intel_dp)
279{
280 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
281 struct intel_encoder *encoder = &intel_dig_port->base;
282 struct drm_device *dev = encoder->base.dev;
fac5e23e 283 struct drm_i915_private *dev_priv = to_i915(dev);
773538e8
VS		 284 enum intel_display_power_domain power_domain;
285
286 mutex_unlock(&dev_priv->pps_mutex);
287
25f78f58 288 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 289 intel_display_power_put(dev_priv, power_domain);
290}
291
961a0db0
VS		 292static void
293vlv_power_sequencer_kick(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 297 struct drm_i915_private *dev_priv = to_i915(dev);
961a0db0 298 enum pipe pipe = intel_dp->pps_pipe;
0047eedc
VS		 299 bool pll_enabled, release_cl_override = false;
300 enum dpio_phy phy = DPIO_PHY(pipe);
301 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
961a0db0
VS		 302 uint32_t DP;
303
304 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
305 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
306 pipe_name(pipe), port_name(intel_dig_port->port)))
307 return;
308
309 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
310 pipe_name(pipe), port_name(intel_dig_port->port));
311
312 /* Preserve the BIOS-computed detected bit. This is
313 * supposed to be read-only.
314 */
315 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
316 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
317 DP |= DP_PORT_WIDTH(1);
318 DP |= DP_LINK_TRAIN_PAT_1;
319
320 if (IS_CHERRYVIEW(dev))
321 DP |= DP_PIPE_SELECT_CHV(pipe);
322 else if (pipe == PIPE_B)
323 DP |= DP_PIPEB_SELECT;
324
d288f65f
VS		 325 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
326
327 /*
328 * The DPLL for the pipe must be enabled for this to work.
329 * So enable temporarily it if it's not already enabled.
330 */
0047eedc
VS		 331 if (!pll_enabled) {
332 release_cl_override = IS_CHERRYVIEW(dev) &&
333 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
334
3f36b937
TU		 335 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
336 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
337 DRM_ERROR("Failed to force on pll for pipe %c!\n",
338 pipe_name(pipe));
339 return;
340 }
0047eedc 341 }
d288f65f 342
961a0db0
VS		 343 /*
344 * Similar magic as in intel_dp_enable_port().
345 * We _must_ do this port enable + disable trick
346 * to make this power seqeuencer lock onto the port.
347 * Otherwise even VDD force bit won't work.
348 */
349 I915_WRITE(intel_dp->output_reg, DP);
350 POSTING_READ(intel_dp->output_reg);
351
352 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
353 POSTING_READ(intel_dp->output_reg);
354
355 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
356 POSTING_READ(intel_dp->output_reg);
d288f65f 357
0047eedc 358 if (!pll_enabled) {
d288f65f 359 vlv_force_pll_off(dev, pipe);
0047eedc
VS		 360
361 if (release_cl_override)
362 chv_phy_powergate_ch(dev_priv, phy, ch, false);
363 }
961a0db0
VS		 364}
365
bf13e81b
JN		 366static enum pipe
367vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
368{
369 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b 370 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 371 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8
VS		 372 struct intel_encoder *encoder;
373 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 374 enum pipe pipe;
bf13e81b 375
e39b999a 376 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 377
a8c3344e
VS		 378 /* We should never land here with regular DP ports */
379 WARN_ON(!is_edp(intel_dp));
380
a4a5d2f8
VS		 381 if (intel_dp->pps_pipe != INVALID_PIPE)
382 return intel_dp->pps_pipe;
383
384 /*
385 * We don't have power sequencer currently.
386 * Pick one that's not used by other ports.
387 */
19c8054c 388 for_each_intel_encoder(dev, encoder) {
a4a5d2f8
VS		 389 struct intel_dp *tmp;
390
391 if (encoder->type != INTEL_OUTPUT_EDP)
392 continue;
393
394 tmp = enc_to_intel_dp(&encoder->base);
395
396 if (tmp->pps_pipe != INVALID_PIPE)
397 pipes &= ~(1 << tmp->pps_pipe);
398 }
399
400 /*
401 * Didn't find one. This should not happen since there
402 * are two power sequencers and up to two eDP ports.
403 */
404 if (WARN_ON(pipes == 0))
a8c3344e
VS		 405 pipe = PIPE_A;
406 else
407 pipe = ffs(pipes) - 1;
a4a5d2f8 408
a8c3344e
VS		 409 vlv_steal_power_sequencer(dev, pipe);
410 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 411
412 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
413 pipe_name(intel_dp->pps_pipe),
414 port_name(intel_dig_port->port));
415
416 /* init power sequencer on this pipe and port */
36b5f425
VS		 417 intel_dp_init_panel_power_sequencer(dev, intel_dp);
418 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 419
961a0db0
VS		 420 /*
421 * Even vdd force doesn't work until we've made
422 * the power sequencer lock in on the port.
423 */
424 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 425
426 return intel_dp->pps_pipe;
427}
428
78597996
ID		 429static int
430bxt_power_sequencer_idx(struct intel_dp *intel_dp)
431{
432 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
433 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 434 struct drm_i915_private *dev_priv = to_i915(dev);
78597996
ID		 435
436 lockdep_assert_held(&dev_priv->pps_mutex);
437
438 /* We should never land here with regular DP ports */
439 WARN_ON(!is_edp(intel_dp));
440
441 /*
442 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
443 * mapping needs to be retrieved from VBT, for now just hard-code to
444 * use instance #0 always.
445 */
446 if (!intel_dp->pps_reset)
447 return 0;
448
449 intel_dp->pps_reset = false;
450
451 /*
452 * Only the HW needs to be reprogrammed, the SW state is fixed and
453 * has been setup during connector init.
454 */
455 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
456
457 return 0;
458}
459
6491ab27
VS		 460typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
461 enum pipe pipe);
462
463static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
464 enum pipe pipe)
465{
44cb734c 466 return I915_READ(PP_STATUS(pipe)) & PP_ON;
6491ab27
VS		 467}
468
469static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
470 enum pipe pipe)
471{
44cb734c 472 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
6491ab27
VS		 473}
474
475static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
476 enum pipe pipe)
477{
478 return true;
479}
bf13e81b 480
a4a5d2f8 481static enum pipe
6491ab27
VS		 482vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
483 enum port port,
484 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 485{
486 enum pipe pipe;
bf13e81b 487
bf13e81b 488 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
44cb734c 489 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
bf13e81b 490 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 491
492 if (port_sel != PANEL_PORT_SELECT_VLV(port))
493 continue;
494
6491ab27
VS		 495 if (!pipe_check(dev_priv, pipe))
496 continue;
497
a4a5d2f8 498 return pipe;
bf13e81b
JN		 499 }
500
a4a5d2f8
VS		 501 return INVALID_PIPE;
502}
503
504static void
505vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
506{
507 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
508 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 509 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8
VS		 510 enum port port = intel_dig_port->port;
511
512 lockdep_assert_held(&dev_priv->pps_mutex);
513
514 /* try to find a pipe with this port selected */
6491ab27
VS		 515 /* first pick one where the panel is on */
516 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
517 vlv_pipe_has_pp_on);
518 /* didn't find one? pick one where vdd is on */
519 if (intel_dp->pps_pipe == INVALID_PIPE)
520 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
521 vlv_pipe_has_vdd_on);
522 /* didn't find one? pick one with just the correct port */
523 if (intel_dp->pps_pipe == INVALID_PIPE)
524 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
525 vlv_pipe_any);
a4a5d2f8
VS		 526
527 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
528 if (intel_dp->pps_pipe == INVALID_PIPE) {
529 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
530 port_name(port));
531 return;
bf13e81b
JN		 532 }
533
a4a5d2f8
VS		 534 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
535 port_name(port), pipe_name(intel_dp->pps_pipe));
536
36b5f425
VS		 537 intel_dp_init_panel_power_sequencer(dev, intel_dp);
538 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 539}
540
78597996 541void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
773538e8 542{
91c8a326 543 struct drm_device *dev = &dev_priv->drm;
773538e8
VS		 544 struct intel_encoder *encoder;
545
78597996
ID		 546 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
547 !IS_BROXTON(dev)))
773538e8
VS		 548 return;
549
550 /*
551 * We can't grab pps_mutex here due to deadlock with power_domain
552 * mutex when power_domain functions are called while holding pps_mutex.
553 * That also means that in order to use pps_pipe the code needs to
554 * hold both a power domain reference and pps_mutex, and the power domain
555 * reference get/put must be done while _not_ holding pps_mutex.
556 * pps_{lock,unlock}() do these steps in the correct order, so one
557 * should use them always.
558 */
559
19c8054c 560 for_each_intel_encoder(dev, encoder) {
773538e8
VS		 561 struct intel_dp *intel_dp;
562
563 if (encoder->type != INTEL_OUTPUT_EDP)
564 continue;
565
566 intel_dp = enc_to_intel_dp(&encoder->base);
78597996
ID		 567 if (IS_BROXTON(dev))
568 intel_dp->pps_reset = true;
569 else
570 intel_dp->pps_pipe = INVALID_PIPE;
773538e8 571 }
bf13e81b
JN		 572}
573
8e8232d5
ID		 574struct pps_registers {
575 i915_reg_t pp_ctrl;
576 i915_reg_t pp_stat;
577 i915_reg_t pp_on;
578 i915_reg_t pp_off;
579 i915_reg_t pp_div;
580};
581
582static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
583 struct intel_dp *intel_dp,
584 struct pps_registers *regs)
585{
44cb734c
ID		 586 int pps_idx = 0;
587
8e8232d5
ID		 588 memset(regs, 0, sizeof(*regs));
589
44cb734c
ID		 590 if (IS_BROXTON(dev_priv))
591 pps_idx = bxt_power_sequencer_idx(intel_dp);
592 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
593 pps_idx = vlv_power_sequencer_pipe(intel_dp);
8e8232d5 594
44cb734c
ID		 595 regs->pp_ctrl = PP_CONTROL(pps_idx);
596 regs->pp_stat = PP_STATUS(pps_idx);
597 regs->pp_on = PP_ON_DELAYS(pps_idx);
598 regs->pp_off = PP_OFF_DELAYS(pps_idx);
599 if (!IS_BROXTON(dev_priv))
600 regs->pp_div = PP_DIVISOR(pps_idx);
8e8232d5
ID		 601}
602
f0f59a00
VS		 603static i915_reg_t
604_pp_ctrl_reg(struct intel_dp *intel_dp)
bf13e81b 605{
8e8232d5 606 struct pps_registers regs;
bf13e81b 607
8e8232d5
ID		 608 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
609 &regs);
610
611 return regs.pp_ctrl;
bf13e81b
JN		 612}
613
f0f59a00
VS		 614static i915_reg_t
615_pp_stat_reg(struct intel_dp *intel_dp)
bf13e81b 616{
8e8232d5 617 struct pps_registers regs;
bf13e81b 618
8e8232d5
ID		 619 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
620 &regs);
621
622 return regs.pp_stat;
bf13e81b
JN		 623}
624
01527b31
CT		 625/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
626 This function only applicable when panel PM state is not to be tracked */
627static int edp_notify_handler(struct notifier_block *this, unsigned long code,
628 void *unused)
629{
630 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
631 edp_notifier);
632 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 633 struct drm_i915_private *dev_priv = to_i915(dev);
01527b31
CT		 634
635 if (!is_edp(intel_dp) || code != SYS_RESTART)
636 return 0;
637
773538e8 638 pps_lock(intel_dp);
e39b999a 639
666a4537 640 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e39b999a 641 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
f0f59a00 642 i915_reg_t pp_ctrl_reg, pp_div_reg;
649636ef 643 u32 pp_div;
e39b999a 644
44cb734c
ID		 645 pp_ctrl_reg = PP_CONTROL(pipe);
646 pp_div_reg = PP_DIVISOR(pipe);
01527b31
CT		 647 pp_div = I915_READ(pp_div_reg);
648 pp_div &= PP_REFERENCE_DIVIDER_MASK;
649
650 /* 0x1F write to PP_DIV_REG sets max cycle delay */
651 I915_WRITE(pp_div_reg, pp_div | 0x1F);
652 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
653 msleep(intel_dp->panel_power_cycle_delay);
654 }
655
773538e8 656 pps_unlock(intel_dp);
e39b999a 657
01527b31
CT		 658 return 0;
659}
660
4be73780 661static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 662{
30add22d 663 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 664 struct drm_i915_private *dev_priv = to_i915(dev);
ebf33b18 665
e39b999a
VS		 666 lockdep_assert_held(&dev_priv->pps_mutex);
667
666a4537 668 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 669 intel_dp->pps_pipe == INVALID_PIPE)
670 return false;
671
bf13e81b 672 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 673}
674
4be73780 675static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 676{
30add22d 677 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 678 struct drm_i915_private *dev_priv = to_i915(dev);
ebf33b18 679
e39b999a
VS		 680 lockdep_assert_held(&dev_priv->pps_mutex);
681
666a4537 682 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 683 intel_dp->pps_pipe == INVALID_PIPE)
684 return false;
685
773538e8 686 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 687}
688
9b984dae
KP		 689static void
690intel_dp_check_edp(struct intel_dp *intel_dp)
691{
30add22d 692 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 693 struct drm_i915_private *dev_priv = to_i915(dev);
ebf33b18 694
9b984dae
KP		 695 if (!is_edp(intel_dp))
696 return;
453c5420 697
4be73780 698 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 699 WARN(1, "eDP powered off while attempting aux channel communication.\n");
700 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 701 I915_READ(_pp_stat_reg(intel_dp)),
702 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 703 }
704}
705
9ee32fea
DV		 706static uint32_t
707intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
708{
709 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
710 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 711 struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00 712 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 713 uint32_t status;
714 bool done;
715
ef04f00d 716#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 717 if (has_aux_irq)
b18ac466 718 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 719 msecs_to_jiffies_timeout(10));
9ee32fea 720 else
713a6b66 721 done = wait_for(C, 10) == 0;
9ee32fea
DV		 722 if (!done)
723 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
724 has_aux_irq);
725#undef C
726
727 return status;
728}
729
6ffb1be7 730static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 731{
174edf1f 732 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
e7dc33f3 733 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
9ee32fea 734
a457f54b
VS		 735 if (index)
736 return 0;
737
ec5b01dd
DL		 738 /*
739 * The clock divider is based off the hrawclk, and would like to run at
a457f54b 740 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
a4fc5ed6 741 */
a457f54b 742 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 743}
744
745static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
746{
747 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 748 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd
DL		 749
750 if (index)
751 return 0;
752
a457f54b
VS		 753 /*
754 * The clock divider is based off the cdclk or PCH rawclk, and would
755 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
756 * divide by 2000 and use that
757 */
e7dc33f3 758 if (intel_dig_port->port == PORT_A)
fce18c4c 759 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
e7dc33f3
VS		 760 else
761 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 762}
763
764static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
765{
766 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 767 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd 768
a457f54b 769 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
2c55c336 770 /* Workaround for non-ULT HSW */
bc86625a
CW		 771 switch (index) {
772 case 0: return 63;
773 case 1: return 72;
774 default: return 0;
775 }
2c55c336 776 }
a457f54b
VS		 777
778 return ilk_get_aux_clock_divider(intel_dp, index);
b84a1cf8
RV		 779}
780
b6b5e383
DL		 781static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
782{
783 /*
784 * SKL doesn't need us to program the AUX clock divider (Hardware will
785 * derive the clock from CDCLK automatically). We still implement the
786 * get_aux_clock_divider vfunc to plug-in into the existing code.
787 */
788 return index ? 0 : 1;
789}
790
6ffb1be7
VS		 791static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
792 bool has_aux_irq,
793 int send_bytes,
794 uint32_t aux_clock_divider)
5ed12a19
DL		 795{
796 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
797 struct drm_device *dev = intel_dig_port->base.base.dev;
798 uint32_t precharge, timeout;
799
800 if (IS_GEN6(dev))
801 precharge = 3;
802 else
803 precharge = 5;
804
f3c6a3a7 805 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
5ed12a19
DL		 806 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
807 else
808 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
809
810 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 811 DP_AUX_CH_CTL_DONE |
5ed12a19 812 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 813 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 814 timeout |
788d4433 815 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 816 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
817 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 818 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 819}
820
b9ca5fad
DL		 821static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
822 bool has_aux_irq,
823 int send_bytes,
824 uint32_t unused)
825{
826 return DP_AUX_CH_CTL_SEND_BUSY |
827 DP_AUX_CH_CTL_DONE |
828 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
829 DP_AUX_CH_CTL_TIME_OUT_ERROR |
830 DP_AUX_CH_CTL_TIME_OUT_1600us |
831 DP_AUX_CH_CTL_RECEIVE_ERROR |
832 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
d4dcbdce 833 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
b9ca5fad
DL		 834 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
835}
836
b84a1cf8
RV		 837static int
838intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 839 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 840 uint8_t *recv, int recv_size)
841{
842 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
843 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 844 struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00 845 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
bc86625a 846 uint32_t aux_clock_divider;
b84a1cf8
RV		 847 int i, ret, recv_bytes;
848 uint32_t status;
5ed12a19 849 int try, clock = 0;
4e6b788c 850 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 851 bool vdd;
852
773538e8 853 pps_lock(intel_dp);
e39b999a 854
72c3500a
VS		 855 /*
856 * We will be called with VDD already enabled for dpcd/edid/oui reads.
857 * In such cases we want to leave VDD enabled and it's up to upper layers
858 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
859 * ourselves.
860 */
1e0560e0 861 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 862
863 /* dp aux is extremely sensitive to irq latency, hence request the
864 * lowest possible wakeup latency and so prevent the cpu from going into
865 * deep sleep states.
866 */
867 pm_qos_update_request(&dev_priv->pm_qos, 0);
868
869 intel_dp_check_edp(intel_dp);
5eb08b69 870
11bee43e
JB		 871 /* Try to wait for any previous AUX channel activity */
872 for (try = 0; try < 3; try++) {
ef04f00d 873 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 874 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
875 break;
876 msleep(1);
877 }
878
879 if (try == 3) {
02196c77
MK		 880 static u32 last_status = -1;
881 const u32 status = I915_READ(ch_ctl);
882
883 if (status != last_status) {
884 WARN(1, "dp_aux_ch not started status 0x%08x\n",
885 status);
886 last_status = status;
887 }
888
9ee32fea
DV		 889 ret = -EBUSY;
890 goto out;
4f7f7b7e
CW		 891 }
892
46a5ae9f
PZ		 893 /* Only 5 data registers! */
894 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
895 ret = -E2BIG;
896 goto out;
897 }
898
ec5b01dd 899 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 900 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
901 has_aux_irq,
902 send_bytes,
903 aux_clock_divider);
5ed12a19 904
bc86625a
CW		 905 /* Must try at least 3 times according to DP spec */
906 for (try = 0; try < 5; try++) {
907 /* Load the send data into the aux channel data registers */
908 for (i = 0; i < send_bytes; i += 4)
330e20ec 909 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
a4f1289e
RV		 910 intel_dp_pack_aux(send + i,
911 send_bytes - i));
bc86625a
CW		 912
913 /* Send the command and wait for it to complete */
5ed12a19 914 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 915
916 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
917
918 /* Clear done status and any errors */
919 I915_WRITE(ch_ctl,
920 status |
921 DP_AUX_CH_CTL_DONE |
922 DP_AUX_CH_CTL_TIME_OUT_ERROR |
923 DP_AUX_CH_CTL_RECEIVE_ERROR);
924
74ebf294 925 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 926 continue;
74ebf294
TP		 927
928 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
929 * 400us delay required for errors and timeouts
930 * Timeout errors from the HW already meet this
931 * requirement so skip to next iteration
932 */
933 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
934 usleep_range(400, 500);
bc86625a 935 continue;
74ebf294 936 }
bc86625a 937 if (status & DP_AUX_CH_CTL_DONE)
e058c945 938 goto done;
bc86625a 939 }
a4fc5ed6
KP		 940 }
941
a4fc5ed6 942 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 943 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 944 ret = -EBUSY;
945 goto out;
a4fc5ed6
KP		 946 }
947
e058c945 948done:
a4fc5ed6
KP		 949 /* Check for timeout or receive error.
950 * Timeouts occur when the sink is not connected
951 */
a5b3da54 952 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 953 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 954 ret = -EIO;
955 goto out;
a5b3da54 956 }
1ae8c0a5
KP		 957
958 /* Timeouts occur when the device isn't connected, so they're
959 * "normal" -- don't fill the kernel log with these */
a5b3da54 960 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 961 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 962 ret = -ETIMEDOUT;
963 goto out;
a4fc5ed6
KP		 964 }
965
966 /* Unload any bytes sent back from the other side */
967 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
968 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
14e01889
RV		 969
970 /*
971 * By BSpec: "Message sizes of 0 or >20 are not allowed."
972 * We have no idea of what happened so we return -EBUSY so
973 * drm layer takes care for the necessary retries.
974 */
975 if (recv_bytes == 0 || recv_bytes > 20) {
976 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
977 recv_bytes);
978 /*
979 * FIXME: This patch was created on top of a series that
980 * organize the retries at drm level. There EBUSY should
981 * also take care for 1ms wait before retrying.
982 * That aux retries re-org is still needed and after that is
983 * merged we remove this sleep from here.
984 */
985 usleep_range(1000, 1500);
986 ret = -EBUSY;
987 goto out;
988 }
989
a4fc5ed6
KP		 990 if (recv_bytes > recv_size)
991 recv_bytes = recv_size;
0206e353 992
4f7f7b7e 993 for (i = 0; i < recv_bytes; i += 4)
330e20ec 994 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
a4f1289e 995 recv + i, recv_bytes - i);
a4fc5ed6 996
9ee32fea
DV		 997 ret = recv_bytes;
998out:
999 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1000
884f19e9
JN		 1001 if (vdd)
1002 edp_panel_vdd_off(intel_dp, false);
1003
773538e8 1004 pps_unlock(intel_dp);
e39b999a 1005
9ee32fea 1006 return ret;
a4fc5ed6
KP		 1007}
1008
a6c8aff0
JN		 1009#define BARE_ADDRESS_SIZE 3
1010#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 1011static ssize_t
1012intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 1013{
9d1a1031
JN		 1014 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1015 uint8_t txbuf[20], rxbuf[20];
1016 size_t txsize, rxsize;
a4fc5ed6 1017 int ret;
a4fc5ed6 1018
d2d9cbbd
VS		 1019 txbuf[0] = (msg->request << 4) |
1020 ((msg->address >> 16) & 0xf);
1021 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 1022 txbuf[2] = msg->address & 0xff;
1023 txbuf[3] = msg->size - 1;
46a5ae9f 1024
9d1a1031
JN		 1025 switch (msg->request & ~DP_AUX_I2C_MOT) {
1026 case DP_AUX_NATIVE_WRITE:
1027 case DP_AUX_I2C_WRITE:
c1e74122 1028 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
a6c8aff0 1029 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 1030 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 1031
9d1a1031
JN		 1032 if (WARN_ON(txsize > 20))
1033 return -E2BIG;
a4fc5ed6 1034
dd788090
VS		 1035 WARN_ON(!msg->buffer != !msg->size);
1036
d81a67cc
ID		 1037 if (msg->buffer)
1038 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 1039
9d1a1031
JN		 1040 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1041 if (ret > 0) {
1042 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 1043
a1ddefd8
JN		 1044 if (ret > 1) {
1045 /* Number of bytes written in a short write. */
1046 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1047 } else {
1048 /* Return payload size. */
1049 ret = msg->size;
1050 }
9d1a1031
JN		 1051 }
1052 break;
46a5ae9f 1053
9d1a1031
JN		 1054 case DP_AUX_NATIVE_READ:
1055 case DP_AUX_I2C_READ:
a6c8aff0 1056 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 1057 rxsize = msg->size + 1;
a4fc5ed6 1058
9d1a1031
JN		 1059 if (WARN_ON(rxsize > 20))
1060 return -E2BIG;
a4fc5ed6 1061
9d1a1031
JN		 1062 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1063 if (ret > 0) {
1064 msg->reply = rxbuf[0] >> 4;
1065 /*
1066 * Assume happy day, and copy the data. The caller is
1067 * expected to check msg->reply before touching it.
1068 *
1069 * Return payload size.
1070 */
1071 ret--;
1072 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1073 }
9d1a1031
JN		 1074 break;
1075
1076 default:
1077 ret = -EINVAL;
1078 break;
a4fc5ed6 1079 }
f51a44b9 1080
9d1a1031 1081 return ret;
a4fc5ed6
KP		 1082}
1083
f0f59a00
VS		 1084static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1085 enum port port)
da00bdcf
VS		 1086{
1087 switch (port) {
1088 case PORT_B:
1089 case PORT_C:
1090 case PORT_D:
1091 return DP_AUX_CH_CTL(port);
1092 default:
1093 MISSING_CASE(port);
1094 return DP_AUX_CH_CTL(PORT_B);
1095 }
1096}
1097
f0f59a00
VS		 1098static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1099 enum port port, int index)
330e20ec
VS		 1100{
1101 switch (port) {
1102 case PORT_B:
1103 case PORT_C:
1104 case PORT_D:
1105 return DP_AUX_CH_DATA(port, index);
1106 default:
1107 MISSING_CASE(port);
1108 return DP_AUX_CH_DATA(PORT_B, index);
1109 }
1110}
1111
f0f59a00
VS		 1112static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1113 enum port port)
da00bdcf
VS		 1114{
1115 switch (port) {
1116 case PORT_A:
1117 return DP_AUX_CH_CTL(port);
1118 case PORT_B:
1119 case PORT_C:
1120 case PORT_D:
1121 return PCH_DP_AUX_CH_CTL(port);
1122 default:
1123 MISSING_CASE(port);
1124 return DP_AUX_CH_CTL(PORT_A);
1125 }
1126}
1127
f0f59a00
VS		 1128static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1129 enum port port, int index)
330e20ec
VS		 1130{
1131 switch (port) {
1132 case PORT_A:
1133 return DP_AUX_CH_DATA(port, index);
1134 case PORT_B:
1135 case PORT_C:
1136 case PORT_D:
1137 return PCH_DP_AUX_CH_DATA(port, index);
1138 default:
1139 MISSING_CASE(port);
1140 return DP_AUX_CH_DATA(PORT_A, index);
1141 }
1142}
1143
da00bdcf
VS		 1144/*
1145 * On SKL we don't have Aux for port E so we rely
1146 * on VBT to set a proper alternate aux channel.
1147 */
1148static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1149{
1150 const struct ddi_vbt_port_info *info =
1151 &dev_priv->vbt.ddi_port_info[PORT_E];
1152
1153 switch (info->alternate_aux_channel) {
1154 case DP_AUX_A:
1155 return PORT_A;
1156 case DP_AUX_B:
1157 return PORT_B;
1158 case DP_AUX_C:
1159 return PORT_C;
1160 case DP_AUX_D:
1161 return PORT_D;
1162 default:
1163 MISSING_CASE(info->alternate_aux_channel);
1164 return PORT_A;
1165 }
1166}
1167
f0f59a00
VS		 1168static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1169 enum port port)
da00bdcf
VS		 1170{
1171 if (port == PORT_E)
1172 port = skl_porte_aux_port(dev_priv);
1173
1174 switch (port) {
1175 case PORT_A:
1176 case PORT_B:
1177 case PORT_C:
1178 case PORT_D:
1179 return DP_AUX_CH_CTL(port);
1180 default:
1181 MISSING_CASE(port);
1182 return DP_AUX_CH_CTL(PORT_A);
1183 }
1184}
1185
f0f59a00
VS		 1186static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1187 enum port port, int index)
330e20ec
VS		 1188{
1189 if (port == PORT_E)
1190 port = skl_porte_aux_port(dev_priv);
1191
1192 switch (port) {
1193 case PORT_A:
1194 case PORT_B:
1195 case PORT_C:
1196 case PORT_D:
1197 return DP_AUX_CH_DATA(port, index);
1198 default:
1199 MISSING_CASE(port);
1200 return DP_AUX_CH_DATA(PORT_A, index);
1201 }
1202}
1203
f0f59a00
VS		 1204static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1205 enum port port)
330e20ec
VS		 1206{
1207 if (INTEL_INFO(dev_priv)->gen >= 9)
1208 return skl_aux_ctl_reg(dev_priv, port);
1209 else if (HAS_PCH_SPLIT(dev_priv))
1210 return ilk_aux_ctl_reg(dev_priv, port);
1211 else
1212 return g4x_aux_ctl_reg(dev_priv, port);
1213}
1214
f0f59a00
VS		 1215static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1216 enum port port, int index)
330e20ec
VS		 1217{
1218 if (INTEL_INFO(dev_priv)->gen >= 9)
1219 return skl_aux_data_reg(dev_priv, port, index);
1220 else if (HAS_PCH_SPLIT(dev_priv))
1221 return ilk_aux_data_reg(dev_priv, port, index);
1222 else
1223 return g4x_aux_data_reg(dev_priv, port, index);
1224}
1225
1226static void intel_aux_reg_init(struct intel_dp *intel_dp)
1227{
1228 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1229 enum port port = dp_to_dig_port(intel_dp)->port;
1230 int i;
1231
1232 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1233 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1234 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1235}
1236
9d1a1031 1237static void
a121f4e5
VS		 1238intel_dp_aux_fini(struct intel_dp *intel_dp)
1239{
a121f4e5
VS		 1240 kfree(intel_dp->aux.name);
1241}
1242
7a418e34 1243static void
9d1a1031
JN		 1244intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1245{
33ad6626
JN		 1246 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1247 enum port port = intel_dig_port->port;
ab2c0672 1248
330e20ec 1249 intel_aux_reg_init(intel_dp);
7a418e34 1250 drm_dp_aux_init(&intel_dp->aux);
8316f337 1251
7a418e34 1252 /* Failure to allocate our preferred name is not critical */
a121f4e5 1253 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
9d1a1031 1254 intel_dp->aux.transfer = intel_dp_aux_transfer;
a4fc5ed6
KP		 1255}
1256
fc0f8e25 1257static int
12f6a2e2 1258intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1259{
94ca719e
VS		 1260 if (intel_dp->num_sink_rates) {
1261 *sink_rates = intel_dp->sink_rates;
1262 return intel_dp->num_sink_rates;
fc0f8e25 1263 }
12f6a2e2
VS		 1264
1265 *sink_rates = default_rates;
1266
1267 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1268}
1269
e588fa18 1270bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
ed63baaf 1271{
e588fa18
ACO		 1272 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1273 struct drm_device *dev = dig_port->base.base.dev;
1274
ed63baaf 1275 /* WaDisableHBR2:skl */
e87a005d 1276 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
ed63baaf
TS		 1277 return false;
1278
1279 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1280 (INTEL_INFO(dev)->gen >= 9))
1281 return true;
1282 else
1283 return false;
1284}
1285
a8f3ef61 1286static int
e588fa18 1287intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
a8f3ef61 1288{
e588fa18
ACO		 1289 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1290 struct drm_device *dev = dig_port->base.base.dev;
af7080f5
TS		 1291 int size;
1292
64987fc5
SJ		 1293 if (IS_BROXTON(dev)) {
1294 *source_rates = bxt_rates;
af7080f5 1295 size = ARRAY_SIZE(bxt_rates);
ef11bdb3 1296 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
637a9c63 1297 *source_rates = skl_rates;
af7080f5
TS		 1298 size = ARRAY_SIZE(skl_rates);
1299 } else {
1300 *source_rates = default_rates;
1301 size = ARRAY_SIZE(default_rates);
a8f3ef61 1302 }
636280ba 1303
ed63baaf 1304 /* This depends on the fact that 5.4 is last value in the array */
e588fa18 1305 if (!intel_dp_source_supports_hbr2(intel_dp))
af7080f5 1306 size--;
636280ba 1307
af7080f5 1308 return size;
a8f3ef61
SJ		 1309}
1310
c6bb3538
DV		 1311static void
1312intel_dp_set_clock(struct intel_encoder *encoder,
840b32b7 1313 struct intel_crtc_state *pipe_config)
c6bb3538
DV		 1314{
1315 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1316 const struct dp_link_dpll *divisor = NULL;
1317 int i, count = 0;
c6bb3538
DV		 1318
1319 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1320 divisor = gen4_dpll;
1321 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1322 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1323 divisor = pch_dpll;
1324 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1325 } else if (IS_CHERRYVIEW(dev)) {
1326 divisor = chv_dpll;
1327 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1328 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1329 divisor = vlv_dpll;
1330 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1331 }
9dd4ffdf
CML		 1332
1333 if (divisor && count) {
1334 for (i = 0; i < count; i++) {
840b32b7 1335 if (pipe_config->port_clock == divisor[i].clock) {
9dd4ffdf
CML		 1336 pipe_config->dpll = divisor[i].dpll;
1337 pipe_config->clock_set = true;
1338 break;
1339 }
1340 }
c6bb3538
DV		 1341 }
1342}
1343
2ecae76a
VS		 1344static int intersect_rates(const int *source_rates, int source_len,
1345 const int *sink_rates, int sink_len,
94ca719e 1346 int *common_rates)
a8f3ef61
SJ		 1347{
1348 int i = 0, j = 0, k = 0;
1349
a8f3ef61
SJ		 1350 while (i < source_len && j < sink_len) {
1351 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1352 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1353 return k;
94ca719e 1354 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1355 ++k;
1356 ++i;
1357 ++j;
1358 } else if (source_rates[i] < sink_rates[j]) {
1359 ++i;
1360 } else {
1361 ++j;
1362 }
1363 }
1364 return k;
1365}
1366
94ca719e
VS		 1367static int intel_dp_common_rates(struct intel_dp *intel_dp,
1368 int *common_rates)
2ecae76a 1369{
2ecae76a
VS		 1370 const int *source_rates, *sink_rates;
1371 int source_len, sink_len;
1372
1373 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
e588fa18 1374 source_len = intel_dp_source_rates(intel_dp, &source_rates);
2ecae76a
VS		 1375
1376 return intersect_rates(source_rates, source_len,
1377 sink_rates, sink_len,
94ca719e 1378 common_rates);
2ecae76a
VS		 1379}
1380
0336400e
VS		 1381static void snprintf_int_array(char *str, size_t len,
1382 const int *array, int nelem)
1383{
1384 int i;
1385
1386 str[0] = '\0';
1387
1388 for (i = 0; i < nelem; i++) {
b2f505be 1389 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1390 if (r >= len)
1391 return;
1392 str += r;
1393 len -= r;
1394 }
1395}
1396
1397static void intel_dp_print_rates(struct intel_dp *intel_dp)
1398{
0336400e 1399 const int *source_rates, *sink_rates;
94ca719e
VS		 1400 int source_len, sink_len, common_len;
1401 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1402 char str[128]; /* FIXME: too big for stack? */
1403
1404 if ((drm_debug & DRM_UT_KMS) == 0)
1405 return;
1406
e588fa18 1407 source_len = intel_dp_source_rates(intel_dp, &source_rates);
0336400e
VS		 1408 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1409 DRM_DEBUG_KMS("source rates: %s\n", str);
1410
1411 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1412 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1413 DRM_DEBUG_KMS("sink rates: %s\n", str);
1414
94ca719e
VS		 1415 common_len = intel_dp_common_rates(intel_dp, common_rates);
1416 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1417 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1418}
1419
f4896f15 1420static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1421{
1422 int i = 0;
1423
1424 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1425 if (find == rates[i])
1426 break;
1427
1428 return i;
1429}
1430
50fec21a
VS		 1431int
1432intel_dp_max_link_rate(struct intel_dp *intel_dp)
1433{
1434 int rates[DP_MAX_SUPPORTED_RATES] = {};
1435 int len;
1436
94ca719e 1437 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1438 if (WARN_ON(len <= 0))
1439 return 162000;
1440
1354f734 1441 return rates[len - 1];
50fec21a
VS		 1442}
1443
ed4e9c1d
VS		 1444int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1445{
94ca719e 1446 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1447}
1448
94223d04
ACO		 1449void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1450 uint8_t *link_bw, uint8_t *rate_select)
04a60f9f
VS		 1451{
1452 if (intel_dp->num_sink_rates) {
1453 *link_bw = 0;
1454 *rate_select =
1455 intel_dp_rate_select(intel_dp, port_clock);
1456 } else {
1457 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1458 *rate_select = 0;
1459 }
1460}
1461
00c09d70 1462bool
5bfe2ac0 1463intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1464 struct intel_crtc_state *pipe_config)
a4fc5ed6 1465{
5bfe2ac0 1466 struct drm_device *dev = encoder->base.dev;
fac5e23e 1467 struct drm_i915_private *dev_priv = to_i915(dev);
2d112de7 1468 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1469 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1470 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1471 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1472 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1473 int lane_count, clock;
56071a20 1474 int min_lane_count = 1;
eeb6324d 1475 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1476 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1477 int min_clock = 0;
a8f3ef61 1478 int max_clock;
083f9560 1479 int bpp, mode_rate;
ff9a6750 1480 int link_avail, link_clock;
94ca719e
VS		 1481 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1482 int common_len;
04a60f9f 1483 uint8_t link_bw, rate_select;
a8f3ef61 1484
94ca719e 1485 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1486
1487 /* No common link rates between source and sink */
94ca719e 1488 WARN_ON(common_len <= 0);
a8f3ef61 1489
94ca719e 1490 max_clock = common_len - 1;
a4fc5ed6 1491
bc7d38a4 1492 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1493 pipe_config->has_pch_encoder = true;
1494
f769cd24 1495 pipe_config->has_drrs = false;
9fcb1704 1496 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1497
dd06f90e
JN		 1498 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1499 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1500 adjusted_mode);
a1b2278e
CK		 1501
1502 if (INTEL_INFO(dev)->gen >= 9) {
1503 int ret;
e435d6e5 1504 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1505 if (ret)
1506 return ret;
1507 }
1508
b5667627 1509 if (HAS_GMCH_DISPLAY(dev))
2dd24552
JB		 1510 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1511 intel_connector->panel.fitting_mode);
1512 else
b074cec8
JB		 1513 intel_pch_panel_fitting(intel_crtc, pipe_config,
1514 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1515 }
1516
cb1793ce 1517 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1518 return false;
1519
083f9560 1520 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1521 "max bw %d pixel clock %iKHz\n",
94ca719e 1522 max_lane_count, common_rates[max_clock],
241bfc38 1523 adjusted_mode->crtc_clock);
083f9560 1524
36008365
DV		 1525 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1526 * bpc in between. */
3e7ca985 1527 bpp = pipe_config->pipe_bpp;
56071a20 1528 if (is_edp(intel_dp)) {
22ce5628
TS		 1529
1530 /* Get bpp from vbt only for panels that dont have bpp in edid */
1531 if (intel_connector->base.display_info.bpc == 0 &&
6aa23e65 1532 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
56071a20 1533 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
6aa23e65
JN		 1534 dev_priv->vbt.edp.bpp);
1535 bpp = dev_priv->vbt.edp.bpp;
56071a20
JN		 1536 }
1537
344c5bbc
JN		 1538 /*
1539 * Use the maximum clock and number of lanes the eDP panel
1540 * advertizes being capable of. The panels are generally
1541 * designed to support only a single clock and lane
1542 * configuration, and typically these values correspond to the
1543 * native resolution of the panel.
1544 */
1545 min_lane_count = max_lane_count;
1546 min_clock = max_clock;
7984211e 1547 }
657445fe 1548
36008365 1549 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1550 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1551 bpp);
36008365 1552
c6930992 1553 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1554 for (lane_count = min_lane_count;
1555 lane_count <= max_lane_count;
1556 lane_count <<= 1) {
1557
94ca719e 1558 link_clock = common_rates[clock];
36008365
DV		 1559 link_avail = intel_dp_max_data_rate(link_clock,
1560 lane_count);
1561
1562 if (mode_rate <= link_avail) {
1563 goto found;
1564 }
1565 }
1566 }
1567 }
c4867936 1568
36008365 1569 return false;
3685a8f3 1570
36008365 1571found:
55bc60db
VS		 1572 if (intel_dp->color_range_auto) {
1573 /*
1574 * See:
1575 * CEA-861-E - 5.1 Default Encoding Parameters
1576 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1577 */
0f2a2a75
VS		 1578 pipe_config->limited_color_range =
1579 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1580 } else {
1581 pipe_config->limited_color_range =
1582 intel_dp->limited_color_range;
55bc60db
VS		 1583 }
1584
90a6b7b0 1585 pipe_config->lane_count = lane_count;
a8f3ef61 1586
657445fe 1587 pipe_config->pipe_bpp = bpp;
94ca719e 1588 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1589
04a60f9f
VS		 1590 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1591 &link_bw, &rate_select);
1592
1593 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1594 link_bw, rate_select, pipe_config->lane_count,
ff9a6750 1595 pipe_config->port_clock, bpp);
36008365
DV		 1596 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1597 mode_rate, link_avail);
a4fc5ed6 1598
03afc4a2 1599 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1600 adjusted_mode->crtc_clock,
1601 pipe_config->port_clock,
03afc4a2 1602 &pipe_config->dp_m_n);
9d1a455b 1603
439d7ac0 1604 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1605 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1606 pipe_config->has_drrs = true;
439d7ac0
PB		 1607 intel_link_compute_m_n(bpp, lane_count,
1608 intel_connector->panel.downclock_mode->clock,
1609 pipe_config->port_clock,
1610 &pipe_config->dp_m2_n2);
1611 }
1612
14d41b3b
VS		 1613 /*
1614 * DPLL0 VCO may need to be adjusted to get the correct
1615 * clock for eDP. This will affect cdclk as well.
1616 */
1617 if (is_edp(intel_dp) &&
1618 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1619 int vco;
1620
1621 switch (pipe_config->port_clock / 2) {
1622 case 108000:
1623 case 216000:
63911d72 1624 vco = 8640000;
14d41b3b
VS		 1625 break;
1626 default:
63911d72 1627 vco = 8100000;
14d41b3b
VS		 1628 break;
1629 }
1630
1631 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1632 }
1633
a3c988ea 1634 if (!HAS_DDI(dev))
840b32b7 1635 intel_dp_set_clock(encoder, pipe_config);
c6bb3538 1636
03afc4a2 1637 return true;
a4fc5ed6
KP		 1638}
1639
901c2daf
VS		 1640void intel_dp_set_link_params(struct intel_dp *intel_dp,
1641 const struct intel_crtc_state *pipe_config)
1642{
1643 intel_dp->link_rate = pipe_config->port_clock;
1644 intel_dp->lane_count = pipe_config->lane_count;
64ee2fd2 1645 intel_dp->link_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST);
901c2daf
VS		 1646}
1647
8ac33ed3 1648static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1649{
b934223d 1650 struct drm_device *dev = encoder->base.dev;
fac5e23e 1651 struct drm_i915_private *dev_priv = to_i915(dev);
b934223d 1652 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1653 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1654 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
7c5f93b0 1655 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1656
901c2daf
VS		 1657 intel_dp_set_link_params(intel_dp, crtc->config);
1658
417e822d 1659 /*
1a2eb460 1660 * There are four kinds of DP registers:
417e822d
KP		 1661 *
1662 * IBX PCH
1a2eb460
KP		 1663 * SNB CPU
1664 * IVB CPU
417e822d
KP		 1665 * CPT PCH
1666 *
1667 * IBX PCH and CPU are the same for almost everything,
1668 * except that the CPU DP PLL is configured in this
1669 * register
1670 *
1671 * CPT PCH is quite different, having many bits moved
1672 * to the TRANS_DP_CTL register instead. That
1673 * configuration happens (oddly) in ironlake_pch_enable
1674 */
9c9e7927 1675
417e822d
KP		 1676 /* Preserve the BIOS-computed detected bit. This is
1677 * supposed to be read-only.
1678 */
1679 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1680
417e822d 1681 /* Handle DP bits in common between all three register formats */
417e822d 1682 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
90a6b7b0 1683 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
a4fc5ed6 1684
417e822d 1685 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1686
39e5fa88 1687 if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1688 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1689 intel_dp->DP |= DP_SYNC_HS_HIGH;
1690 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1691 intel_dp->DP |= DP_SYNC_VS_HIGH;
1692 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1693
6aba5b6c 1694 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1695 intel_dp->DP |= DP_ENHANCED_FRAMING;
1696
7c62a164 1697 intel_dp->DP |= crtc->pipe << 29;
39e5fa88 1698 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
e3ef4479
VS		 1699 u32 trans_dp;
1700
39e5fa88 1701 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1702
1703 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1704 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1705 trans_dp |= TRANS_DP_ENH_FRAMING;
1706 else
1707 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1708 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1709 } else {
0f2a2a75 1710 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 1711 !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
0f2a2a75 1712 intel_dp->DP |= DP_COLOR_RANGE_16_235;
417e822d
KP		 1713
1714 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1715 intel_dp->DP |= DP_SYNC_HS_HIGH;
1716 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1717 intel_dp->DP |= DP_SYNC_VS_HIGH;
1718 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1719
6aba5b6c 1720 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1721 intel_dp->DP |= DP_ENHANCED_FRAMING;
1722
39e5fa88 1723 if (IS_CHERRYVIEW(dev))
44f37d1f 1724 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1725 else if (crtc->pipe == PIPE_B)
1726 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1727 }
a4fc5ed6
KP		 1728}
1729
ffd6749d
PZ		 1730#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1731#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1732
1a5ef5b7
PZ		 1733#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1734#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1735
ffd6749d
PZ		 1736#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1737#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1738
de9c1b6b
ID		 1739static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1740 struct intel_dp *intel_dp);
1741
4be73780 1742static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1743 u32 mask,
1744 u32 value)
bd943159 1745{
30add22d 1746 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 1747 struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00 1748 i915_reg_t pp_stat_reg, pp_ctrl_reg;
453c5420 1749
e39b999a
VS		 1750 lockdep_assert_held(&dev_priv->pps_mutex);
1751
de9c1b6b
ID		 1752 intel_pps_verify_state(dev_priv, intel_dp);
1753
bf13e81b
JN		 1754 pp_stat_reg = _pp_stat_reg(intel_dp);
1755 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1756
99ea7127 1757 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1758 mask, value,
1759 I915_READ(pp_stat_reg),
1760 I915_READ(pp_ctrl_reg));
32ce697c 1761
9036ff06
CW		 1762 if (intel_wait_for_register(dev_priv,
1763 pp_stat_reg, mask, value,
1764 5000))
99ea7127 1765 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1766 I915_READ(pp_stat_reg),
1767 I915_READ(pp_ctrl_reg));
54c136d4
CW		 1768
1769 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1770}
32ce697c 1771
4be73780 1772static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1773{
1774 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1775 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1776}
1777
4be73780 1778static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1779{
1780 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1781 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1782}
1783
4be73780 1784static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127 1785{
d28d4731
AK		 1786 ktime_t panel_power_on_time;
1787 s64 panel_power_off_duration;
1788
99ea7127 1789 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c 1790
d28d4731
AK		 1791 /* take the difference of currrent time and panel power off time
1792 * and then make panel wait for t11_t12 if needed. */
1793 panel_power_on_time = ktime_get_boottime();
1794 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1795
dce56b3c
PZ		 1796 /* When we disable the VDD override bit last we have to do the manual
1797 * wait. */
d28d4731
AK		 1798 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1799 wait_remaining_ms_from_jiffies(jiffies,
1800 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
dce56b3c 1801
4be73780 1802 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1803}
1804
4be73780 1805static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1806{
1807 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1808 intel_dp->backlight_on_delay);
1809}
1810
4be73780 1811static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1812{
1813 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1814 intel_dp->backlight_off_delay);
1815}
99ea7127 1816
832dd3c1
KP		 1817/* Read the current pp_control value, unlocking the register if it
1818 * is locked
1819 */
1820
453c5420 1821static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1822{
453c5420 1823 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 1824 struct drm_i915_private *dev_priv = to_i915(dev);
453c5420 1825 u32 control;
832dd3c1 1826
e39b999a
VS		 1827 lockdep_assert_held(&dev_priv->pps_mutex);
1828
bf13e81b 1829 control = I915_READ(_pp_ctrl_reg(intel_dp));
b0a08bec
VK		 1830 if (!IS_BROXTON(dev)) {
1831 control &= ~PANEL_UNLOCK_MASK;
1832 control |= PANEL_UNLOCK_REGS;
1833 }
832dd3c1 1834 return control;
bd943159
KP		 1835}
1836
951468f3
VS		 1837/*
1838 * Must be paired with edp_panel_vdd_off().
1839 * Must hold pps_mutex around the whole on/off sequence.
1840 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1841 */
1e0560e0 1842static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1843{
30add22d 1844 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1845 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1846 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fac5e23e 1847 struct drm_i915_private *dev_priv = to_i915(dev);
4e6e1a54 1848 enum intel_display_power_domain power_domain;
5d613501 1849 u32 pp;
f0f59a00 1850 i915_reg_t pp_stat_reg, pp_ctrl_reg;
adddaaf4 1851 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1852
e39b999a
VS		 1853 lockdep_assert_held(&dev_priv->pps_mutex);
1854
97af61f5 1855 if (!is_edp(intel_dp))
adddaaf4 1856 return false;
bd943159 1857
2c623c11 1858 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1859 intel_dp->want_panel_vdd = true;
99ea7127 1860
4be73780 1861 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1862 return need_to_disable;
b0665d57 1863
25f78f58 1864 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 1865 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1866
3936fcf4
VS		 1867 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1868 port_name(intel_dig_port->port));
bd943159 1869
4be73780
DV		 1870 if (!edp_have_panel_power(intel_dp))
1871 wait_panel_power_cycle(intel_dp);
99ea7127 1872
453c5420 1873 pp = ironlake_get_pp_control(intel_dp);
5d613501 1874 pp |= EDP_FORCE_VDD;
ebf33b18 1875
bf13e81b
JN		 1876 pp_stat_reg = _pp_stat_reg(intel_dp);
1877 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1878
1879 I915_WRITE(pp_ctrl_reg, pp);
1880 POSTING_READ(pp_ctrl_reg);
1881 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1882 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1883 /*
1884 * If the panel wasn't on, delay before accessing aux channel
1885 */
4be73780 1886 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1887 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1888 port_name(intel_dig_port->port));
f01eca2e 1889 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1890 }
adddaaf4
JN		 1891
1892 return need_to_disable;
1893}
1894
951468f3
VS		 1895/*
1896 * Must be paired with intel_edp_panel_vdd_off() or
1897 * intel_edp_panel_off().
1898 * Nested calls to these functions are not allowed since
1899 * we drop the lock. Caller must use some higher level
1900 * locking to prevent nested calls from other threads.
1901 */
b80d6c78 1902void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1903{
c695b6b6 1904 bool vdd;
adddaaf4 1905
c695b6b6
VS		 1906 if (!is_edp(intel_dp))
1907 return;
1908
773538e8 1909 pps_lock(intel_dp);
c695b6b6 1910 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1911 pps_unlock(intel_dp);
c695b6b6 1912
e2c719b7 1913 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1914 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1915}
1916
4be73780 1917static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1918{
30add22d 1919 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 1920 struct drm_i915_private *dev_priv = to_i915(dev);
be2c9196
VS		 1921 struct intel_digital_port *intel_dig_port =
1922 dp_to_dig_port(intel_dp);
1923 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1924 enum intel_display_power_domain power_domain;
5d613501 1925 u32 pp;
f0f59a00 1926 i915_reg_t pp_stat_reg, pp_ctrl_reg;
5d613501 1927
e39b999a 1928 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1929
15e899a0 1930 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1931
15e899a0 1932 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1933 return;
b0665d57 1934
3936fcf4
VS		 1935 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1936 port_name(intel_dig_port->port));
bd943159 1937
be2c9196
VS		 1938 pp = ironlake_get_pp_control(intel_dp);
1939 pp &= ~EDP_FORCE_VDD;
453c5420 1940
be2c9196
VS		 1941 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1942 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1943
be2c9196
VS		 1944 I915_WRITE(pp_ctrl_reg, pp);
1945 POSTING_READ(pp_ctrl_reg);
90791a5c 1946
be2c9196
VS		 1947 /* Make sure sequencer is idle before allowing subsequent activity */
1948 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1949 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1950
5a162e22 1951 if ((pp & PANEL_POWER_ON) == 0)
d28d4731 1952 intel_dp->panel_power_off_time = ktime_get_boottime();
e9cb81a2 1953
25f78f58 1954 power_domain = intel_display_port_aux_power_domain(intel_encoder);
be2c9196 1955 intel_display_power_put(dev_priv, power_domain);
bd943159 1956}
5d613501 1957
4be73780 1958static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1959{
1960 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1961 struct intel_dp, panel_vdd_work);
bd943159 1962
773538e8 1963 pps_lock(intel_dp);
15e899a0
VS		 1964 if (!intel_dp->want_panel_vdd)
1965 edp_panel_vdd_off_sync(intel_dp);
773538e8 1966 pps_unlock(intel_dp);
bd943159
KP		 1967}
1968
aba86890
ID		 1969static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1970{
1971 unsigned long delay;
1972
1973 /*
1974 * Queue the timer to fire a long time from now (relative to the power
1975 * down delay) to keep the panel power up across a sequence of
1976 * operations.
1977 */
1978 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1979 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1980}
1981
951468f3
VS		 1982/*
1983 * Must be paired with edp_panel_vdd_on().
1984 * Must hold pps_mutex around the whole on/off sequence.
1985 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1986 */
4be73780 1987static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1988{
fac5e23e 1989 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
e39b999a
VS		 1990
1991 lockdep_assert_held(&dev_priv->pps_mutex);
1992
97af61f5
KP		 1993 if (!is_edp(intel_dp))
1994 return;
5d613501 1995
e2c719b7 1996 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1997 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1998
bd943159
KP		 1999 intel_dp->want_panel_vdd = false;
2000
aba86890 2001 if (sync)
4be73780 2002 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 2003 else
2004 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 2005}
2006
9f0fb5be 2007static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 2008{
30add22d 2009 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2010 struct drm_i915_private *dev_priv = to_i915(dev);
99ea7127 2011 u32 pp;
f0f59a00 2012 i915_reg_t pp_ctrl_reg;
9934c132 2013
9f0fb5be
VS		 2014 lockdep_assert_held(&dev_priv->pps_mutex);
2015
97af61f5 2016 if (!is_edp(intel_dp))
bd943159 2017 return;
99ea7127 2018
3936fcf4
VS		 2019 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2020 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 2021
e7a89ace
VS		 2022 if (WARN(edp_have_panel_power(intel_dp),
2023 "eDP port %c panel power already on\n",
2024 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 2025 return;
9934c132 2026
4be73780 2027 wait_panel_power_cycle(intel_dp);
37c6c9b0 2028
bf13e81b 2029 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2030 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 2031 if (IS_GEN5(dev)) {
2032 /* ILK workaround: disable reset around power sequence */
2033 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 2034 I915_WRITE(pp_ctrl_reg, pp);
2035 POSTING_READ(pp_ctrl_reg);
05ce1a49 2036 }
37c6c9b0 2037
5a162e22 2038 pp |= PANEL_POWER_ON;
99ea7127
KP		 2039 if (!IS_GEN5(dev))
2040 pp |= PANEL_POWER_RESET;
2041
453c5420
JB		 2042 I915_WRITE(pp_ctrl_reg, pp);
2043 POSTING_READ(pp_ctrl_reg);
9934c132 2044
4be73780 2045 wait_panel_on(intel_dp);
dce56b3c 2046 intel_dp->last_power_on = jiffies;
9934c132 2047
05ce1a49
KP		 2048 if (IS_GEN5(dev)) {
2049 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 2050 I915_WRITE(pp_ctrl_reg, pp);
2051 POSTING_READ(pp_ctrl_reg);
05ce1a49 2052 }
9f0fb5be 2053}
e39b999a 2054
9f0fb5be
VS		 2055void intel_edp_panel_on(struct intel_dp *intel_dp)
2056{
2057 if (!is_edp(intel_dp))
2058 return;
2059
2060 pps_lock(intel_dp);
2061 edp_panel_on(intel_dp);
773538e8 2062 pps_unlock(intel_dp);
9934c132
JB		 2063}
2064
9f0fb5be
VS		 2065
2066static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 2067{
4e6e1a54
ID		 2068 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2069 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 2070 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2071 struct drm_i915_private *dev_priv = to_i915(dev);
4e6e1a54 2072 enum intel_display_power_domain power_domain;
99ea7127 2073 u32 pp;
f0f59a00 2074 i915_reg_t pp_ctrl_reg;
9934c132 2075
9f0fb5be
VS		 2076 lockdep_assert_held(&dev_priv->pps_mutex);
2077
97af61f5
KP		 2078 if (!is_edp(intel_dp))
2079 return;
37c6c9b0 2080
3936fcf4
VS		 2081 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2082 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 2083
3936fcf4
VS		 2084 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2085 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 2086
453c5420 2087 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 2088 /* We need to switch off panel power _and_ force vdd, for otherwise some
2089 * panels get very unhappy and cease to work. */
5a162e22 2090 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
b3064154 2091 EDP_BLC_ENABLE);
453c5420 2092
bf13e81b 2093 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2094
849e39f5
PZ		 2095 intel_dp->want_panel_vdd = false;
2096
453c5420
JB		 2097 I915_WRITE(pp_ctrl_reg, pp);
2098 POSTING_READ(pp_ctrl_reg);
9934c132 2099
d28d4731 2100 intel_dp->panel_power_off_time = ktime_get_boottime();
4be73780 2101 wait_panel_off(intel_dp);
849e39f5
PZ		 2102
2103 /* We got a reference when we enabled the VDD. */
25f78f58 2104 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 2105 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 2106}
e39b999a 2107
9f0fb5be
VS		 2108void intel_edp_panel_off(struct intel_dp *intel_dp)
2109{
2110 if (!is_edp(intel_dp))
2111 return;
e39b999a 2112
9f0fb5be
VS		 2113 pps_lock(intel_dp);
2114 edp_panel_off(intel_dp);
773538e8 2115 pps_unlock(intel_dp);
9934c132
JB		 2116}
2117
1250d107
JN		 2118/* Enable backlight in the panel power control. */
2119static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2120{
da63a9f2
PZ		 2121 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2122 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 2123 struct drm_i915_private *dev_priv = to_i915(dev);
32f9d658 2124 u32 pp;
f0f59a00 2125 i915_reg_t pp_ctrl_reg;
32f9d658 2126
01cb9ea6
JB		 2127 /*
2128 * If we enable the backlight right away following a panel power
2129 * on, we may see slight flicker as the panel syncs with the eDP
2130 * link. So delay a bit to make sure the image is solid before
2131 * allowing it to appear.
2132 */
4be73780 2133 wait_backlight_on(intel_dp);
e39b999a 2134
773538e8 2135 pps_lock(intel_dp);
e39b999a 2136
453c5420 2137 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2138 pp |= EDP_BLC_ENABLE;
453c5420 2139
bf13e81b 2140 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2141
2142 I915_WRITE(pp_ctrl_reg, pp);
2143 POSTING_READ(pp_ctrl_reg);
e39b999a 2144
773538e8 2145 pps_unlock(intel_dp);
32f9d658
ZW		 2146}
2147
1250d107
JN		 2148/* Enable backlight PWM and backlight PP control. */
2149void intel_edp_backlight_on(struct intel_dp *intel_dp)
2150{
2151 if (!is_edp(intel_dp))
2152 return;
2153
2154 DRM_DEBUG_KMS("\n");
2155
2156 intel_panel_enable_backlight(intel_dp->attached_connector);
2157 _intel_edp_backlight_on(intel_dp);
2158}
2159
2160/* Disable backlight in the panel power control. */
2161static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2162{
30add22d 2163 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2164 struct drm_i915_private *dev_priv = to_i915(dev);
32f9d658 2165 u32 pp;
f0f59a00 2166 i915_reg_t pp_ctrl_reg;
32f9d658 2167
f01eca2e
KP		 2168 if (!is_edp(intel_dp))
2169 return;
2170
773538e8 2171 pps_lock(intel_dp);
e39b999a 2172
453c5420 2173 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2174 pp &= ~EDP_BLC_ENABLE;
453c5420 2175
bf13e81b 2176 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2177
2178 I915_WRITE(pp_ctrl_reg, pp);
2179 POSTING_READ(pp_ctrl_reg);
f7d2323c 2180
773538e8 2181 pps_unlock(intel_dp);
e39b999a
VS		 2182
2183 intel_dp->last_backlight_off = jiffies;
f7d2323c 2184 edp_wait_backlight_off(intel_dp);
1250d107 2185}
f7d2323c 2186
1250d107
JN		 2187/* Disable backlight PP control and backlight PWM. */
2188void intel_edp_backlight_off(struct intel_dp *intel_dp)
2189{
2190 if (!is_edp(intel_dp))
2191 return;
2192
2193 DRM_DEBUG_KMS("\n");
f7d2323c 2194
1250d107 2195 _intel_edp_backlight_off(intel_dp);
f7d2323c 2196 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2197}
a4fc5ed6 2198
73580fb7
JN		 2199/*
2200 * Hook for controlling the panel power control backlight through the bl_power
2201 * sysfs attribute. Take care to handle multiple calls.
2202 */
2203static void intel_edp_backlight_power(struct intel_connector *connector,
2204 bool enable)
2205{
2206 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2207 bool is_enabled;
2208
773538e8 2209 pps_lock(intel_dp);
e39b999a 2210 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2211 pps_unlock(intel_dp);
73580fb7
JN		 2212
2213 if (is_enabled == enable)
2214 return;
2215
23ba9373
JN		 2216 DRM_DEBUG_KMS("panel power control backlight %s\n",
2217 enable ? "enable" : "disable");
73580fb7
JN		 2218
2219 if (enable)
2220 _intel_edp_backlight_on(intel_dp);
2221 else
2222 _intel_edp_backlight_off(intel_dp);
2223}
2224
64e1077a
VS		 2225static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2226{
2227 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2228 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2229 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2230
2231 I915_STATE_WARN(cur_state != state,
2232 "DP port %c state assertion failure (expected %s, current %s)\n",
2233 port_name(dig_port->port),
87ad3212 2234 onoff(state), onoff(cur_state));
64e1077a
VS		 2235}
2236#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2237
2238static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2239{
2240 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2241
2242 I915_STATE_WARN(cur_state != state,
2243 "eDP PLL state assertion failure (expected %s, current %s)\n",
87ad3212 2244 onoff(state), onoff(cur_state));
64e1077a
VS		 2245}
2246#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2247#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2248
2bd2ad64 2249static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2250{
da63a9f2 2251 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2252 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2253 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2254
64e1077a
VS		 2255 assert_pipe_disabled(dev_priv, crtc->pipe);
2256 assert_dp_port_disabled(intel_dp);
2257 assert_edp_pll_disabled(dev_priv);
2bd2ad64 2258
abfce949
VS		 2259 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2260 crtc->config->port_clock);
2261
2262 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2263
2264 if (crtc->config->port_clock == 162000)
2265 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2266 else
2267 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2268
2269 I915_WRITE(DP_A, intel_dp->DP);
2270 POSTING_READ(DP_A);
2271 udelay(500);
2272
6b23f3e8
VS		 2273 /*
2274 * [DevILK] Work around required when enabling DP PLL
2275 * while a pipe is enabled going to FDI:
2276 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2277 * 2. Program DP PLL enable
2278 */
2279 if (IS_GEN5(dev_priv))
91c8a326 2280 intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe);
6b23f3e8 2281
0767935e 2282 intel_dp->DP |= DP_PLL_ENABLE;
6fec7662 2283
0767935e 2284 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2285 POSTING_READ(DP_A);
2286 udelay(200);
d240f20f
JB		 2287}
2288
2bd2ad64 2289static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2290{
da63a9f2 2291 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2292 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2293 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2294
64e1077a
VS		 2295 assert_pipe_disabled(dev_priv, crtc->pipe);
2296 assert_dp_port_disabled(intel_dp);
2297 assert_edp_pll_enabled(dev_priv);
2bd2ad64 2298
abfce949
VS		 2299 DRM_DEBUG_KMS("disabling eDP PLL\n");
2300
6fec7662 2301 intel_dp->DP &= ~DP_PLL_ENABLE;
0767935e 2302
6fec7662 2303 I915_WRITE(DP_A, intel_dp->DP);
1af5fa1b 2304 POSTING_READ(DP_A);
d240f20f
JB		 2305 udelay(200);
2306}
2307
c7ad3810 2308/* If the sink supports it, try to set the power state appropriately */
c19b0669 2309void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2310{
2311 int ret, i;
2312
2313 /* Should have a valid DPCD by this point */
2314 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2315 return;
2316
2317 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2318 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2319 DP_SET_POWER_D3);
c7ad3810
JB		 2320 } else {
2321 /*
2322 * When turning on, we need to retry for 1ms to give the sink
2323 * time to wake up.
2324 */
2325 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2326 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2327 DP_SET_POWER_D0);
c7ad3810
JB		 2328 if (ret == 1)
2329 break;
2330 msleep(1);
2331 }
2332 }
f9cac721
JN		 2333
2334 if (ret != 1)
2335 DRM_DEBUG_KMS("failed to %s sink power state\n",
2336 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2337}
2338
19d8fe15
DV		 2339static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2340 enum pipe *pipe)
d240f20f 2341{
19d8fe15 2342 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2343 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15 2344 struct drm_device *dev = encoder->base.dev;
fac5e23e 2345 struct drm_i915_private *dev_priv = to_i915(dev);
6d129bea
ID		 2346 enum intel_display_power_domain power_domain;
2347 u32 tmp;
6fa9a5ec 2348 bool ret;
6d129bea
ID		 2349
2350 power_domain = intel_display_port_power_domain(encoder);
6fa9a5ec 2351 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 2352 return false;
2353
6fa9a5ec
ID		 2354 ret = false;
2355
6d129bea 2356 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2357
2358 if (!(tmp & DP_PORT_EN))
6fa9a5ec 2359 goto out;
19d8fe15 2360
39e5fa88 2361 if (IS_GEN7(dev) && port == PORT_A) {
19d8fe15 2362 *pipe = PORT_TO_PIPE_CPT(tmp);
39e5fa88 2363 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
adc289d7 2364 enum pipe p;
19d8fe15 2365
adc289d7
VS		 2366 for_each_pipe(dev_priv, p) {
2367 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2368 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2369 *pipe = p;
6fa9a5ec
ID		 2370 ret = true;
2371
2372 goto out;
19d8fe15
DV		 2373 }
2374 }
19d8fe15 2375
4a0833ec 2376 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
f0f59a00 2377 i915_mmio_reg_offset(intel_dp->output_reg));
39e5fa88
VS		 2378 } else if (IS_CHERRYVIEW(dev)) {
2379 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2380 } else {
2381 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2382 }
d240f20f 2383
6fa9a5ec
ID		 2384 ret = true;
2385
2386out:
2387 intel_display_power_put(dev_priv, power_domain);
2388
2389 return ret;
19d8fe15 2390}
d240f20f 2391
045ac3b5 2392static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2393 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2394{
2395 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2396 u32 tmp, flags = 0;
63000ef6 2397 struct drm_device *dev = encoder->base.dev;
fac5e23e 2398 struct drm_i915_private *dev_priv = to_i915(dev);
63000ef6
XZ		 2399 enum port port = dp_to_dig_port(intel_dp)->port;
2400 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 2401
9ed109a7 2402 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2403
2404 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2405
39e5fa88 2406 if (HAS_PCH_CPT(dev) && port != PORT_A) {
b81e34c2
VS		 2407 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2408
2409 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2410 flags |= DRM_MODE_FLAG_PHSYNC;
2411 else
2412 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2413
b81e34c2 2414 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2415 flags |= DRM_MODE_FLAG_PVSYNC;
2416 else
2417 flags |= DRM_MODE_FLAG_NVSYNC;
2418 } else {
39e5fa88 2419 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2420 flags |= DRM_MODE_FLAG_PHSYNC;
2421 else
2422 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2423
39e5fa88 2424 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2425 flags |= DRM_MODE_FLAG_PVSYNC;
2426 else
2427 flags |= DRM_MODE_FLAG_NVSYNC;
2428 }
045ac3b5 2429
2d112de7 2430 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2431
8c875fca 2432 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 2433 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
8c875fca
VS		 2434 pipe_config->limited_color_range = true;
2435
90a6b7b0
VS		 2436 pipe_config->lane_count =
2437 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2438
eb14cb74
VS		 2439 intel_dp_get_m_n(crtc, pipe_config);
2440
18442d08 2441 if (port == PORT_A) {
b377e0df 2442 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
f1f644dc
JB		 2443 pipe_config->port_clock = 162000;
2444 else
2445 pipe_config->port_clock = 270000;
2446 }
18442d08 2447
e3b247da
VS		 2448 pipe_config->base.adjusted_mode.crtc_clock =
2449 intel_dotclock_calculate(pipe_config->port_clock,
2450 &pipe_config->dp_m_n);
7f16e5c1 2451
6aa23e65
JN		 2452 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2453 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
c6cd2ee2
JN		 2454 /*
2455 * This is a big fat ugly hack.
2456 *
2457 * Some machines in UEFI boot mode provide us a VBT that has 18
2458 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2459 * unknown we fail to light up. Yet the same BIOS boots up with
2460 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2461 * max, not what it tells us to use.
2462 *
2463 * Note: This will still be broken if the eDP panel is not lit
2464 * up by the BIOS, and thus we can't get the mode at module
2465 * load.
2466 */
2467 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2468 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2469 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
c6cd2ee2 2470 }
045ac3b5
JB		 2471}
2472
e8cb4558 2473static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2474{
e8cb4558 2475 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2476 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2477 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2478
6e3c9717 2479 if (crtc->config->has_audio)
495a5bb8 2480 intel_audio_codec_disable(encoder);
6cb49835 2481
b32c6f48
RV		 2482 if (HAS_PSR(dev) && !HAS_DDI(dev))
2483 intel_psr_disable(intel_dp);
2484
6cb49835
DV		 2485 /* Make sure the panel is off before trying to change the mode. But also
2486 * ensure that we have vdd while we switch off the panel. */
24f3e092 2487 intel_edp_panel_vdd_on(intel_dp);
4be73780 2488 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2489 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2490 intel_edp_panel_off(intel_dp);
3739850b 2491
08aff3fe
VS		 2492 /* disable the port before the pipe on g4x */
2493 if (INTEL_INFO(dev)->gen < 5)
3739850b 2494 intel_dp_link_down(intel_dp);
d240f20f
JB		 2495}
2496
08aff3fe 2497static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2498{
2bd2ad64 2499 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2500 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2501
49277c31 2502 intel_dp_link_down(intel_dp);
abfce949
VS		 2503
2504 /* Only ilk+ has port A */
08aff3fe
VS		 2505 if (port == PORT_A)
2506 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2507}
2508
2509static void vlv_post_disable_dp(struct intel_encoder *encoder)
2510{
2511 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2512
2513 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2514}
2515
a8f327fb
VS		 2516static void chv_post_disable_dp(struct intel_encoder *encoder)
2517{
2518 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2519 struct drm_device *dev = encoder->base.dev;
fac5e23e 2520 struct drm_i915_private *dev_priv = to_i915(dev);
97fd4d5c 2521
a8f327fb
VS		 2522 intel_dp_link_down(intel_dp);
2523
2524 mutex_lock(&dev_priv->sb_lock);
2525
2526 /* Assert data lane reset */
2527 chv_data_lane_soft_reset(encoder, true);
580d3811 2528
a580516d 2529 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2530}
2531
7b13b58a
VS		 2532static void
2533_intel_dp_set_link_train(struct intel_dp *intel_dp,
2534 uint32_t *DP,
2535 uint8_t dp_train_pat)
2536{
2537 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2538 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 2539 struct drm_i915_private *dev_priv = to_i915(dev);
7b13b58a
VS		 2540 enum port port = intel_dig_port->port;
2541
2542 if (HAS_DDI(dev)) {
2543 uint32_t temp = I915_READ(DP_TP_CTL(port));
2544
2545 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2546 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2547 else
2548 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2549
2550 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2551 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2552 case DP_TRAINING_PATTERN_DISABLE:
2553 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2554
2555 break;
2556 case DP_TRAINING_PATTERN_1:
2557 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2558 break;
2559 case DP_TRAINING_PATTERN_2:
2560 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2561 break;
2562 case DP_TRAINING_PATTERN_3:
2563 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2564 break;
2565 }
2566 I915_WRITE(DP_TP_CTL(port), temp);
2567
39e5fa88
VS		 2568 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2569 (HAS_PCH_CPT(dev) && port != PORT_A)) {
7b13b58a
VS		 2570 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2571
2572 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2573 case DP_TRAINING_PATTERN_DISABLE:
2574 *DP |= DP_LINK_TRAIN_OFF_CPT;
2575 break;
2576 case DP_TRAINING_PATTERN_1:
2577 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2578 break;
2579 case DP_TRAINING_PATTERN_2:
2580 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2581 break;
2582 case DP_TRAINING_PATTERN_3:
2583 DRM_ERROR("DP training pattern 3 not supported\n");
2584 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2585 break;
2586 }
2587
2588 } else {
2589 if (IS_CHERRYVIEW(dev))
2590 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2591 else
2592 *DP &= ~DP_LINK_TRAIN_MASK;
2593
2594 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2595 case DP_TRAINING_PATTERN_DISABLE:
2596 *DP |= DP_LINK_TRAIN_OFF;
2597 break;
2598 case DP_TRAINING_PATTERN_1:
2599 *DP |= DP_LINK_TRAIN_PAT_1;
2600 break;
2601 case DP_TRAINING_PATTERN_2:
2602 *DP |= DP_LINK_TRAIN_PAT_2;
2603 break;
2604 case DP_TRAINING_PATTERN_3:
2605 if (IS_CHERRYVIEW(dev)) {
2606 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2607 } else {
2608 DRM_ERROR("DP training pattern 3 not supported\n");
2609 *DP |= DP_LINK_TRAIN_PAT_2;
2610 }
2611 break;
2612 }
2613 }
2614}
2615
2616static void intel_dp_enable_port(struct intel_dp *intel_dp)
2617{
2618 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2619 struct drm_i915_private *dev_priv = to_i915(dev);
6fec7662
VS		 2620 struct intel_crtc *crtc =
2621 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
7b13b58a 2622
7b13b58a
VS		 2623 /* enable with pattern 1 (as per spec) */
2624 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2625 DP_TRAINING_PATTERN_1);
2626
2627 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2628 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2629
2630 /*
2631 * Magic for VLV/CHV. We _must_ first set up the register
2632 * without actually enabling the port, and then do another
2633 * write to enable the port. Otherwise link training will
2634 * fail when the power sequencer is freshly used for this port.
2635 */
2636 intel_dp->DP |= DP_PORT_EN;
6fec7662
VS		 2637 if (crtc->config->has_audio)
2638 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
7b713f50
VS		 2639
2640 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2641 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2642}
2643
e8cb4558 2644static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2645{
e8cb4558
DV		 2646 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2647 struct drm_device *dev = encoder->base.dev;
fac5e23e 2648 struct drm_i915_private *dev_priv = to_i915(dev);
c1dec79a 2649 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2650 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
d6fbdd15 2651 enum pipe pipe = crtc->pipe;
5d613501 2652
0c33d8d7
DV		 2653 if (WARN_ON(dp_reg & DP_PORT_EN))
2654 return;
5d613501 2655
093e3f13
VS		 2656 pps_lock(intel_dp);
2657
666a4537 2658 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
093e3f13
VS		 2659 vlv_init_panel_power_sequencer(intel_dp);
2660
7b13b58a 2661 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2662
2663 edp_panel_vdd_on(intel_dp);
2664 edp_panel_on(intel_dp);
2665 edp_panel_vdd_off(intel_dp, true);
2666
2667 pps_unlock(intel_dp);
2668
666a4537 2669 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e0fce78f
VS		 2670 unsigned int lane_mask = 0x0;
2671
2672 if (IS_CHERRYVIEW(dev))
2673 lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2674
9b6de0a1
VS		 2675 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2676 lane_mask);
e0fce78f 2677 }
61234fa5 2678
f01eca2e 2679 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2680 intel_dp_start_link_train(intel_dp);
3ab9c637 2681 intel_dp_stop_link_train(intel_dp);
c1dec79a 2682
6e3c9717 2683 if (crtc->config->has_audio) {
c1dec79a 2684 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
d6fbdd15 2685 pipe_name(pipe));
c1dec79a
JN		 2686 intel_audio_codec_enable(encoder);
2687 }
ab1f90f9 2688}
89b667f8 2689
ecff4f3b
JN		 2690static void g4x_enable_dp(struct intel_encoder *encoder)
2691{
828f5c6e
JN		 2692 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2693
ecff4f3b 2694 intel_enable_dp(encoder);
4be73780 2695 intel_edp_backlight_on(intel_dp);
ab1f90f9 2696}
89b667f8 2697
ab1f90f9
JN		 2698static void vlv_enable_dp(struct intel_encoder *encoder)
2699{
828f5c6e
JN		 2700 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2701
4be73780 2702 intel_edp_backlight_on(intel_dp);
b32c6f48 2703 intel_psr_enable(intel_dp);
d240f20f
JB		 2704}
2705
ecff4f3b 2706static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2707{
2708 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6fbdd15 2709 enum port port = dp_to_dig_port(intel_dp)->port;
ab1f90f9 2710
8ac33ed3
DV		 2711 intel_dp_prepare(encoder);
2712
d41f1efb 2713 /* Only ilk+ has port A */
abfce949 2714 if (port == PORT_A)
ab1f90f9
JN		 2715 ironlake_edp_pll_on(intel_dp);
2716}
2717
83b84597
VS		 2718static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2719{
2720 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
fac5e23e 2721 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
83b84597 2722 enum pipe pipe = intel_dp->pps_pipe;
44cb734c 2723 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
83b84597
VS		 2724
2725 edp_panel_vdd_off_sync(intel_dp);
2726
2727 /*
2728 * VLV seems to get confused when multiple power seqeuencers
2729 * have the same port selected (even if only one has power/vdd
2730 * enabled). The failure manifests as vlv_wait_port_ready() failing
2731 * CHV on the other hand doesn't seem to mind having the same port
2732 * selected in multiple power seqeuencers, but let's clear the
2733 * port select always when logically disconnecting a power sequencer
2734 * from a port.
2735 */
2736 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2737 pipe_name(pipe), port_name(intel_dig_port->port));
2738 I915_WRITE(pp_on_reg, 0);
2739 POSTING_READ(pp_on_reg);
2740
2741 intel_dp->pps_pipe = INVALID_PIPE;
2742}
2743
a4a5d2f8
VS		 2744static void vlv_steal_power_sequencer(struct drm_device *dev,
2745 enum pipe pipe)
2746{
fac5e23e 2747 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8
VS		 2748 struct intel_encoder *encoder;
2749
2750 lockdep_assert_held(&dev_priv->pps_mutex);
2751
ac3c12e4
VS		 2752 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2753 return;
2754
19c8054c 2755 for_each_intel_encoder(dev, encoder) {
a4a5d2f8 2756 struct intel_dp *intel_dp;
773538e8 2757 enum port port;
a4a5d2f8
VS		 2758
2759 if (encoder->type != INTEL_OUTPUT_EDP)
2760 continue;
2761
2762 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2763 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2764
2765 if (intel_dp->pps_pipe != pipe)
2766 continue;
2767
2768 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2769 pipe_name(pipe), port_name(port));
a4a5d2f8 2770
e02f9a06 2771 WARN(encoder->base.crtc,
034e43c6
VS		 2772 "stealing pipe %c power sequencer from active eDP port %c\n",
2773 pipe_name(pipe), port_name(port));
a4a5d2f8 2774
a4a5d2f8 2775 /* make sure vdd is off before we steal it */
83b84597 2776 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2777 }
2778}
2779
2780static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2781{
2782 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2783 struct intel_encoder *encoder = &intel_dig_port->base;
2784 struct drm_device *dev = encoder->base.dev;
fac5e23e 2785 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8 2786 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2787
2788 lockdep_assert_held(&dev_priv->pps_mutex);
2789
093e3f13
VS		 2790 if (!is_edp(intel_dp))
2791 return;
2792
a4a5d2f8
VS		 2793 if (intel_dp->pps_pipe == crtc->pipe)
2794 return;
2795
2796 /*
2797 * If another power sequencer was being used on this
2798 * port previously make sure to turn off vdd there while
2799 * we still have control of it.
2800 */
2801 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2802 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2803
2804 /*
2805 * We may be stealing the power
2806 * sequencer from another port.
2807 */
2808 vlv_steal_power_sequencer(dev, crtc->pipe);
2809
2810 /* now it's all ours */
2811 intel_dp->pps_pipe = crtc->pipe;
2812
2813 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2814 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2815
2816 /* init power sequencer on this pipe and port */
36b5f425
VS		 2817 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2818 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2819}
2820
ab1f90f9 2821static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2822{
5f68c275 2823 vlv_phy_pre_encoder_enable(encoder);
ab1f90f9
JN		 2824
2825 intel_enable_dp(encoder);
89b667f8
JB		 2826}
2827
ecff4f3b 2828static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8 2829{
8ac33ed3
DV		 2830 intel_dp_prepare(encoder);
2831
6da2e616 2832 vlv_phy_pre_pll_enable(encoder);
a4fc5ed6
KP		 2833}
2834
e4a1d846
CML		 2835static void chv_pre_enable_dp(struct intel_encoder *encoder)
2836{
e7d2a717 2837 chv_phy_pre_encoder_enable(encoder);
e4a1d846 2838
e4a1d846 2839 intel_enable_dp(encoder);
b0b33846
VS		 2840
2841 /* Second common lane will stay alive on its own now */
e7d2a717 2842 chv_phy_release_cl2_override(encoder);
e4a1d846
CML		 2843}
2844
9197c88b
VS		 2845static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2846{
625695f8
VS		 2847 intel_dp_prepare(encoder);
2848
419b1b7a 2849 chv_phy_pre_pll_enable(encoder);
9197c88b
VS		 2850}
2851
d6db995f
VS		 2852static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
2853{
204970b5 2854 chv_phy_post_pll_disable(encoder);
d6db995f
VS		 2855}
2856
a4fc5ed6
KP		 2857/*
2858 * Fetch AUX CH registers 0x202 - 0x207 which contain
2859 * link status information
2860 */
94223d04 2861bool
93f62dad 2862intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2863{
9f085ebb
L		 2864 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2865 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2866}
2867
1100244e 2868/* These are source-specific values. */
94223d04 2869uint8_t
1a2eb460 2870intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2871{
30add22d 2872 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2873 struct drm_i915_private *dev_priv = to_i915(dev);
bc7d38a4 2874 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2875
9314726b
VK		 2876 if (IS_BROXTON(dev))
2877 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2878 else if (INTEL_INFO(dev)->gen >= 9) {
06411f08 2879 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
7ad14a29 2880 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2881 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
666a4537 2882 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
bd60018a 2883 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2884 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2885 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2886 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2887 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2888 else
bd60018a 2889 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2890}
2891
94223d04 2892uint8_t
1a2eb460
KP		 2893intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2894{
30add22d 2895 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2896 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2897
5a9d1f1a
DL		 2898 if (INTEL_INFO(dev)->gen >= 9) {
2899 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2900 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2901 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2902 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2903 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2904 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2905 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 2906 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2907 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 2908 default:
2909 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2910 }
2911 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2912 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2913 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2914 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2915 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2916 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2917 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2918 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2919 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2920 default:
bd60018a 2921 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2922 }
666a4537 2923 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e2fa6fba 2924 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2925 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2926 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2927 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2928 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2930 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2931 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2932 default:
bd60018a 2933 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2934 }
bc7d38a4 2935 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2936 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2938 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2940 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2941 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2942 default:
bd60018a 2943 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2944 }
2945 } else {
2946 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2947 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2948 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2949 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2950 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2951 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2952 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2953 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2954 default:
bd60018a 2955 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2956 }
a4fc5ed6
KP		 2957 }
2958}
2959
5829975c 2960static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba 2961{
53d98725 2962 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
e2fa6fba
P		 2963 unsigned long demph_reg_value, preemph_reg_value,
2964 uniqtranscale_reg_value;
2965 uint8_t train_set = intel_dp->train_set[0];
e2fa6fba
P		 2966
2967 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2968 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2969 preemph_reg_value = 0x0004000;
2970 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2971 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2972 demph_reg_value = 0x2B405555;
2973 uniqtranscale_reg_value = 0x552AB83A;
2974 break;
bd60018a 2975 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2976 demph_reg_value = 0x2B404040;
2977 uniqtranscale_reg_value = 0x5548B83A;
2978 break;
bd60018a 2979 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2980 demph_reg_value = 0x2B245555;
2981 uniqtranscale_reg_value = 0x5560B83A;
2982 break;
bd60018a 2983 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2984 demph_reg_value = 0x2B405555;
2985 uniqtranscale_reg_value = 0x5598DA3A;
2986 break;
2987 default:
2988 return 0;
2989 }
2990 break;
bd60018a 2991 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2992 preemph_reg_value = 0x0002000;
2993 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2994 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2995 demph_reg_value = 0x2B404040;
2996 uniqtranscale_reg_value = 0x5552B83A;
2997 break;
bd60018a 2998 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2999 demph_reg_value = 0x2B404848;
3000 uniqtranscale_reg_value = 0x5580B83A;
3001 break;
bd60018a 3002 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3003 demph_reg_value = 0x2B404040;
3004 uniqtranscale_reg_value = 0x55ADDA3A;
3005 break;
3006 default:
3007 return 0;
3008 }
3009 break;
bd60018a 3010 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3011 preemph_reg_value = 0x0000000;
3012 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3014 demph_reg_value = 0x2B305555;
3015 uniqtranscale_reg_value = 0x5570B83A;
3016 break;
bd60018a 3017 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3018 demph_reg_value = 0x2B2B4040;
3019 uniqtranscale_reg_value = 0x55ADDA3A;
3020 break;
3021 default:
3022 return 0;
3023 }
3024 break;
bd60018a 3025 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3026 preemph_reg_value = 0x0006000;
3027 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3028 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3029 demph_reg_value = 0x1B405555;
3030 uniqtranscale_reg_value = 0x55ADDA3A;
3031 break;
3032 default:
3033 return 0;
3034 }
3035 break;
3036 default:
3037 return 0;
3038 }
3039
53d98725
ACO		 3040 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3041 uniqtranscale_reg_value, 0);
e2fa6fba
P		 3042
3043 return 0;
3044}
3045
5829975c 3046static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846 3047{
b7fa22d8
ACO		 3048 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3049 u32 deemph_reg_value, margin_reg_value;
3050 bool uniq_trans_scale = false;
e4a1d846 3051 uint8_t train_set = intel_dp->train_set[0];
e4a1d846
CML		 3052
3053 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3054 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3055 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3056 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3057 deemph_reg_value = 128;
3058 margin_reg_value = 52;
3059 break;
bd60018a 3060 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3061 deemph_reg_value = 128;
3062 margin_reg_value = 77;
3063 break;
bd60018a 3064 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3065 deemph_reg_value = 128;
3066 margin_reg_value = 102;
3067 break;
bd60018a 3068 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3069 deemph_reg_value = 128;
3070 margin_reg_value = 154;
b7fa22d8 3071 uniq_trans_scale = true;
e4a1d846
CML		 3072 break;
3073 default:
3074 return 0;
3075 }
3076 break;
bd60018a 3077 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3078 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3079 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3080 deemph_reg_value = 85;
3081 margin_reg_value = 78;
3082 break;
bd60018a 3083 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3084 deemph_reg_value = 85;
3085 margin_reg_value = 116;
3086 break;
bd60018a 3087 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3088 deemph_reg_value = 85;
3089 margin_reg_value = 154;
3090 break;
3091 default:
3092 return 0;
3093 }
3094 break;
bd60018a 3095 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3096 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3098 deemph_reg_value = 64;
3099 margin_reg_value = 104;
3100 break;
bd60018a 3101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3102 deemph_reg_value = 64;
3103 margin_reg_value = 154;
3104 break;
3105 default:
3106 return 0;
3107 }
3108 break;
bd60018a 3109 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3110 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3111 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3112 deemph_reg_value = 43;
3113 margin_reg_value = 154;
3114 break;
3115 default:
3116 return 0;
3117 }
3118 break;
3119 default:
3120 return 0;
3121 }
3122
b7fa22d8
ACO		 3123 chv_set_phy_signal_level(encoder, deemph_reg_value,
3124 margin_reg_value, uniq_trans_scale);
e4a1d846
CML		 3125
3126 return 0;
3127}
3128
a4fc5ed6 3129static uint32_t
5829975c 3130gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3131{
3cf2efb1 3132 uint32_t signal_levels = 0;
a4fc5ed6 3133
3cf2efb1 3134 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3136 default:
3137 signal_levels |= DP_VOLTAGE_0_4;
3138 break;
bd60018a 3139 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3140 signal_levels |= DP_VOLTAGE_0_6;
3141 break;
bd60018a 3142 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3143 signal_levels |= DP_VOLTAGE_0_8;
3144 break;
bd60018a 3145 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3146 signal_levels |= DP_VOLTAGE_1_2;
3147 break;
3148 }
3cf2efb1 3149 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3150 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3151 default:
3152 signal_levels |= DP_PRE_EMPHASIS_0;
3153 break;
bd60018a 3154 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3155 signal_levels |= DP_PRE_EMPHASIS_3_5;
3156 break;
bd60018a 3157 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3158 signal_levels |= DP_PRE_EMPHASIS_6;
3159 break;
bd60018a 3160 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3161 signal_levels |= DP_PRE_EMPHASIS_9_5;
3162 break;
3163 }
3164 return signal_levels;
3165}
3166
e3421a18
ZW		 3167/* Gen6's DP voltage swing and pre-emphasis control */
3168static uint32_t
5829975c 3169gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3170{
3c5a62b5
YL		 3171 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3172 DP_TRAIN_PRE_EMPHASIS_MASK);
3173 switch (signal_levels) {
bd60018a
SJ		 3174 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3175 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3176 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3178 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3179 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3180 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3181 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3182 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3183 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3184 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3187 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3188 default:
3c5a62b5
YL		 3189 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3190 "0x%x\n", signal_levels);
3191 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3192 }
3193}
3194
1a2eb460
KP		 3195/* Gen7's DP voltage swing and pre-emphasis control */
3196static uint32_t
5829975c 3197gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3198{
3199 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3200 DP_TRAIN_PRE_EMPHASIS_MASK);
3201 switch (signal_levels) {
bd60018a 3202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3203 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3205 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3206 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3207 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3208
bd60018a 3209 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3210 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3211 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3212 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3213
bd60018a 3214 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3215 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3217 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3218
3219 default:
3220 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3221 "0x%x\n", signal_levels);
3222 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3223 }
3224}
3225
94223d04 3226void
f4eb692e 3227intel_dp_set_signal_levels(struct intel_dp *intel_dp)
f0a3424e
PZ		 3228{
3229 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3230 enum port port = intel_dig_port->port;
f0a3424e 3231 struct drm_device *dev = intel_dig_port->base.base.dev;
b905a915 3232 struct drm_i915_private *dev_priv = to_i915(dev);
f8896f5d 3233 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3234 uint8_t train_set = intel_dp->train_set[0];
3235
f8896f5d
DW		 3236 if (HAS_DDI(dev)) {
3237 signal_levels = ddi_signal_levels(intel_dp);
3238
3239 if (IS_BROXTON(dev))
3240 signal_levels = 0;
3241 else
3242 mask = DDI_BUF_EMP_MASK;
e4a1d846 3243 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3244 signal_levels = chv_signal_levels(intel_dp);
e2fa6fba 3245 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3246 signal_levels = vlv_signal_levels(intel_dp);
bc7d38a4 3247 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3248 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3249 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3250 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3251 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3252 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3253 } else {
5829975c 3254 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3255 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3256 }
3257
96fb9f9b
VK		 3258 if (mask)
3259 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3260
3261 DRM_DEBUG_KMS("Using vswing level %d\n",
3262 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3263 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3264 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3265 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e 3266
f4eb692e 3267 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
b905a915
ACO		 3268
3269 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3270 POSTING_READ(intel_dp->output_reg);
f0a3424e
PZ		 3271}
3272
94223d04 3273void
e9c176d5
ACO		 3274intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3275 uint8_t dp_train_pat)
a4fc5ed6 3276{
174edf1f 3277 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3278 struct drm_i915_private *dev_priv =
3279 to_i915(intel_dig_port->base.base.dev);
a4fc5ed6 3280
f4eb692e 3281 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
47ea7542 3282
f4eb692e 3283 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
ea5b213a 3284 POSTING_READ(intel_dp->output_reg);
e9c176d5
ACO		 3285}
3286
94223d04 3287void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3ab9c637
ID		 3288{
3289 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3290 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 3291 struct drm_i915_private *dev_priv = to_i915(dev);
3ab9c637
ID		 3292 enum port port = intel_dig_port->port;
3293 uint32_t val;
3294
3295 if (!HAS_DDI(dev))
3296 return;
3297
3298 val = I915_READ(DP_TP_CTL(port));
3299 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3300 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3301 I915_WRITE(DP_TP_CTL(port), val);
3302
3303 /*
3304 * On PORT_A we can have only eDP in SST mode. There the only reason
3305 * we need to set idle transmission mode is to work around a HW issue
3306 * where we enable the pipe while not in idle link-training mode.
3307 * In this case there is requirement to wait for a minimum number of
3308 * idle patterns to be sent.
3309 */
3310 if (port == PORT_A)
3311 return;
3312
a767017f
CW		 3313 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3314 DP_TP_STATUS_IDLE_DONE,
3315 DP_TP_STATUS_IDLE_DONE,
3316 1))
3ab9c637
ID		 3317 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3318}
3319
a4fc5ed6 3320static void
ea5b213a 3321intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3322{
da63a9f2 3323 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3324 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3325 enum port port = intel_dig_port->port;
da63a9f2 3326 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 3327 struct drm_i915_private *dev_priv = to_i915(dev);
ea5b213a 3328 uint32_t DP = intel_dp->DP;
a4fc5ed6 3329
bc76e320 3330 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3331 return;
3332
0c33d8d7 3333 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3334 return;
3335
28c97730 3336 DRM_DEBUG_KMS("\n");
32f9d658 3337
39e5fa88
VS		 3338 if ((IS_GEN7(dev) && port == PORT_A) ||
3339 (HAS_PCH_CPT(dev) && port != PORT_A)) {
e3421a18 3340 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3341 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3342 } else {
aad3d14d
VS		 3343 if (IS_CHERRYVIEW(dev))
3344 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3345 else
3346 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3347 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3348 }
1612c8bd 3349 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3350 POSTING_READ(intel_dp->output_reg);
5eb08b69 3351
1612c8bd
VS		 3352 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3353 I915_WRITE(intel_dp->output_reg, DP);
3354 POSTING_READ(intel_dp->output_reg);
3355
3356 /*
3357 * HW workaround for IBX, we need to move the port
3358 * to transcoder A after disabling it to allow the
3359 * matching HDMI port to be enabled on transcoder A.
3360 */
3361 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
0c241d5b
VS		 3362 /*
3363 * We get CPU/PCH FIFO underruns on the other pipe when
3364 * doing the workaround. Sweep them under the rug.
3365 */
3366 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3367 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3368
1612c8bd
VS		 3369 /* always enable with pattern 1 (as per spec) */
3370 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3371 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3372 I915_WRITE(intel_dp->output_reg, DP);
3373 POSTING_READ(intel_dp->output_reg);
3374
3375 DP &= ~DP_PORT_EN;
5bddd17f 3376 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3377 POSTING_READ(intel_dp->output_reg);
0c241d5b 3378
91c8a326 3379 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
0c241d5b
VS		 3380 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3381 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5bddd17f
EA		 3382 }
3383
f01eca2e 3384 msleep(intel_dp->panel_power_down_delay);
6fec7662
VS		 3385
3386 intel_dp->DP = DP;
a4fc5ed6
KP		 3387}
3388
26d61aad 3389static bool
fe5a66f9 3390intel_dp_read_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3391{
9f085ebb
L		 3392 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3393 sizeof(intel_dp->dpcd)) < 0)
edb39244 3394 return false; /* aux transfer failed */
92fd8fd1 3395
a8e98153 3396 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3397
fe5a66f9
VS		 3398 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3399}
edb39244 3400
fe5a66f9
VS		 3401static bool
3402intel_edp_init_dpcd(struct intel_dp *intel_dp)
3403{
3404 struct drm_i915_private *dev_priv =
3405 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
30d9aa42 3406
fe5a66f9
VS		 3407 /* this function is meant to be called only once */
3408 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
30d9aa42 3409
fe5a66f9 3410 if (!intel_dp_read_dpcd(intel_dp))
30d9aa42
SS		 3411 return false;
3412
fe5a66f9
VS		 3413 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3414 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3415 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
474d1ec4 3416
fe5a66f9
VS		 3417 /* Check if the panel supports PSR */
3418 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3419 intel_dp->psr_dpcd,
3420 sizeof(intel_dp->psr_dpcd));
3421 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3422 dev_priv->psr.sink_support = true;
3423 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3424 }
86ee27b5 3425
fe5a66f9
VS		 3426 if (INTEL_GEN(dev_priv) >= 9 &&
3427 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3428 uint8_t frame_sync_cap;
3429
3430 dev_priv->psr.sink_support = true;
3431 drm_dp_dpcd_read(&intel_dp->aux,
3432 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3433 &frame_sync_cap, 1);
3434 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3435 /* PSR2 needs frame sync as well */
3436 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3437 DRM_DEBUG_KMS("PSR2 %s on sink",
3438 dev_priv->psr.psr2_support ? "supported" : "not supported");
50003939
JN		 3439 }
3440
fe5a66f9
VS		 3441 /* Read the eDP Display control capabilities registers */
3442 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3443 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3444 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd) ==
3445 sizeof(intel_dp->edp_dpcd)))
3446 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3447 intel_dp->edp_dpcd);
06ea66b6 3448
fc0f8e25 3449 /* Intermediate frequency support */
fe5a66f9 3450 if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
94ca719e 3451 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3452 int i;
3453
9f085ebb
L		 3454 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3455 sink_rates, sizeof(sink_rates));
ea2d8a42 3456
94ca719e
VS		 3457 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3458 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3459
3460 if (val == 0)
3461 break;
3462
af77b974
SJ		 3463 /* Value read is in kHz while drm clock is saved in deca-kHz */
3464 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3465 }
94ca719e 3466 intel_dp->num_sink_rates = i;
fc0f8e25 3467 }
0336400e 3468
fe5a66f9
VS		 3469 return true;
3470}
3471
3472
3473static bool
3474intel_dp_get_dpcd(struct intel_dp *intel_dp)
3475{
3476 if (!intel_dp_read_dpcd(intel_dp))
3477 return false;
3478
3479 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3480 &intel_dp->sink_count, 1) < 0)
3481 return false;
3482
3483 /*
3484 * Sink count can change between short pulse hpd hence
3485 * a member variable in intel_dp will track any changes
3486 * between short pulse interrupts.
3487 */
3488 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3489
3490 /*
3491 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3492 * a dongle is present but no display. Unless we require to know
3493 * if a dongle is present or not, we don't need to update
3494 * downstream port information. So, an early return here saves
3495 * time from performing other operations which are not required.
3496 */
3497 if (!is_edp(intel_dp) && !intel_dp->sink_count)
3498 return false;
0336400e 3499
edb39244
AJ		 3500 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3501 DP_DWN_STRM_PORT_PRESENT))
3502 return true; /* native DP sink */
3503
3504 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3505 return true; /* no per-port downstream info */
3506
9f085ebb
L		 3507 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3508 intel_dp->downstream_ports,
3509 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3510 return false; /* downstream port status fetch failed */
3511
3512 return true;
92fd8fd1
KP		 3513}
3514
0d198328
AJ		 3515static void
3516intel_dp_probe_oui(struct intel_dp *intel_dp)
3517{
3518 u8 buf[3];
3519
3520 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3521 return;
3522
9f085ebb 3523 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3524 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3525 buf[0], buf[1], buf[2]);
3526
9f085ebb 3527 if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3528 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3529 buf[0], buf[1], buf[2]);
3530}
3531
0e32b39c 3532static bool
c4e3170a 3533intel_dp_can_mst(struct intel_dp *intel_dp)
0e32b39c
DA		 3534{
3535 u8 buf[1];
3536
7cc96139
NS		 3537 if (!i915.enable_dp_mst)
3538 return false;
3539
0e32b39c
DA		 3540 if (!intel_dp->can_mst)
3541 return false;
3542
3543 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3544 return false;
3545
c4e3170a
VS		 3546 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3547 return false;
0e32b39c 3548
c4e3170a
VS		 3549 return buf[0] & DP_MST_CAP;
3550}
3551
3552static void
3553intel_dp_configure_mst(struct intel_dp *intel_dp)
3554{
3555 if (!i915.enable_dp_mst)
3556 return;
3557
3558 if (!intel_dp->can_mst)
3559 return;
3560
3561 intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3562
3563 if (intel_dp->is_mst)
3564 DRM_DEBUG_KMS("Sink is MST capable\n");
3565 else
3566 DRM_DEBUG_KMS("Sink is not MST capable\n");
3567
3568 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3569 intel_dp->is_mst);
0e32b39c
DA		 3570}
3571
e5a1cab5 3572static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
d2e216d0 3573{
082dcc7c 3574 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3575 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c 3576 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
ad9dc91b 3577 u8 buf;
e5a1cab5 3578 int ret = 0;
c6297843
RV		 3579 int count = 0;
3580 int attempts = 10;
d2e216d0 3581
082dcc7c
RV		 3582 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3583 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3584 ret = -EIO;
3585 goto out;
4373f0f2
PZ		 3586 }
3587
082dcc7c 3588 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
e5a1cab5 3589 buf & ~DP_TEST_SINK_START) < 0) {
082dcc7c 3590 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3591 ret = -EIO;
3592 goto out;
3593 }
d2e216d0 3594
c6297843
RV		 3595 do {
3596 intel_wait_for_vblank(dev, intel_crtc->pipe);
3597
3598 if (drm_dp_dpcd_readb(&intel_dp->aux,
3599 DP_TEST_SINK_MISC, &buf) < 0) {
3600 ret = -EIO;
3601 goto out;
3602 }
3603 count = buf & DP_TEST_COUNT_MASK;
3604 } while (--attempts && count);
3605
3606 if (attempts == 0) {
dc5a9037 3607 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
c6297843
RV		 3608 ret = -ETIMEDOUT;
3609 }
3610
e5a1cab5 3611 out:
082dcc7c 3612 hsw_enable_ips(intel_crtc);
e5a1cab5 3613 return ret;
082dcc7c
RV		 3614}
3615
3616static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3617{
3618 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3619 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c
RV		 3620 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3621 u8 buf;
e5a1cab5
RV		 3622 int ret;
3623
082dcc7c
RV		 3624 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3625 return -EIO;
3626
3627 if (!(buf & DP_TEST_CRC_SUPPORTED))
3628 return -ENOTTY;
3629
3630 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3631 return -EIO;
3632
6d8175da
RV		 3633 if (buf & DP_TEST_SINK_START) {
3634 ret = intel_dp_sink_crc_stop(intel_dp);
3635 if (ret)
3636 return ret;
3637 }
3638
082dcc7c 3639 hsw_disable_ips(intel_crtc);
1dda5f93 3640
9d1a1031 3641 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
082dcc7c
RV		 3642 buf | DP_TEST_SINK_START) < 0) {
3643 hsw_enable_ips(intel_crtc);
3644 return -EIO;
4373f0f2
PZ		 3645 }
3646
d72f9d91 3647 intel_wait_for_vblank(dev, intel_crtc->pipe);
082dcc7c
RV		 3648 return 0;
3649}
3650
3651int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3652{
3653 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3654 struct drm_device *dev = dig_port->base.base.dev;
3655 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3656 u8 buf;
621d4c76 3657 int count, ret;
082dcc7c 3658 int attempts = 6;
082dcc7c
RV		 3659
3660 ret = intel_dp_sink_crc_start(intel_dp);
3661 if (ret)
3662 return ret;
3663
ad9dc91b 3664 do {
621d4c76
RV		 3665 intel_wait_for_vblank(dev, intel_crtc->pipe);
3666
1dda5f93 3667 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 3668 DP_TEST_SINK_MISC, &buf) < 0) {
3669 ret = -EIO;
afe0d67e 3670 goto stop;
4373f0f2 3671 }
621d4c76 3672 count = buf & DP_TEST_COUNT_MASK;
aabc95dc 3673
7e38eeff 3674 } while (--attempts && count == 0);
ad9dc91b
RV		 3675
3676 if (attempts == 0) {
7e38eeff
RV		 3677 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3678 ret = -ETIMEDOUT;
3679 goto stop;
3680 }
3681
3682 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3683 ret = -EIO;
3684 goto stop;
ad9dc91b 3685 }
d2e216d0 3686
afe0d67e 3687stop:
082dcc7c 3688 intel_dp_sink_crc_stop(intel_dp);
4373f0f2 3689 return ret;
d2e216d0
RV		 3690}
3691
a60f0e38
JB		 3692static bool
3693intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3694{
9f085ebb 3695 return drm_dp_dpcd_read(&intel_dp->aux,
9d1a1031
JN		 3696 DP_DEVICE_SERVICE_IRQ_VECTOR,
3697 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3698}
3699
0e32b39c
DA		 3700static bool
3701intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3702{
3703 int ret;
3704
9f085ebb 3705 ret = drm_dp_dpcd_read(&intel_dp->aux,
0e32b39c
DA		 3706 DP_SINK_COUNT_ESI,
3707 sink_irq_vector, 14);
3708 if (ret != 14)
3709 return false;
3710
3711 return true;
3712}
3713
c5d5ab7a
TP		 3714static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3715{
3716 uint8_t test_result = DP_TEST_ACK;
3717 return test_result;
3718}
3719
3720static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3721{
3722 uint8_t test_result = DP_TEST_NAK;
3723 return test_result;
3724}
3725
3726static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 3727{
c5d5ab7a 3728 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 3729 struct intel_connector *intel_connector = intel_dp->attached_connector;
3730 struct drm_connector *connector = &intel_connector->base;
3731
3732 if (intel_connector->detect_edid == NULL ||
ac6f2e29 3733 connector->edid_corrupt ||
559be30c
TP		 3734 intel_dp->aux.i2c_defer_count > 6) {
3735 /* Check EDID read for NACKs, DEFERs and corruption
3736 * (DP CTS 1.2 Core r1.1)
3737 * 4.2.2.4 : Failed EDID read, I2C_NAK
3738 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3739 * 4.2.2.6 : EDID corruption detected
3740 * Use failsafe mode for all cases
3741 */
3742 if (intel_dp->aux.i2c_nack_count > 0 ||
3743 intel_dp->aux.i2c_defer_count > 0)
3744 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3745 intel_dp->aux.i2c_nack_count,
3746 intel_dp->aux.i2c_defer_count);
3747 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3748 } else {
f79b468e
TS		 3749 struct edid *block = intel_connector->detect_edid;
3750
3751 /* We have to write the checksum
3752 * of the last block read
3753 */
3754 block += intel_connector->detect_edid->extensions;
3755
559be30c
TP		 3756 if (!drm_dp_dpcd_write(&intel_dp->aux,
3757 DP_TEST_EDID_CHECKSUM,
f79b468e 3758 &block->checksum,
5a1cc655 3759 1))
559be30c
TP		 3760 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3761
3762 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3763 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3764 }
3765
3766 /* Set test active flag here so userspace doesn't interrupt things */
3767 intel_dp->compliance_test_active = 1;
3768
c5d5ab7a
TP		 3769 return test_result;
3770}
3771
3772static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 3773{
c5d5ab7a
TP		 3774 uint8_t test_result = DP_TEST_NAK;
3775 return test_result;
3776}
3777
3778static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3779{
3780 uint8_t response = DP_TEST_NAK;
3781 uint8_t rxdata = 0;
3782 int status = 0;
3783
c5d5ab7a
TP		 3784 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3785 if (status <= 0) {
3786 DRM_DEBUG_KMS("Could not read test request from sink\n");
3787 goto update_status;
3788 }
3789
3790 switch (rxdata) {
3791 case DP_TEST_LINK_TRAINING:
3792 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3793 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3794 response = intel_dp_autotest_link_training(intel_dp);
3795 break;
3796 case DP_TEST_LINK_VIDEO_PATTERN:
3797 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3798 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3799 response = intel_dp_autotest_video_pattern(intel_dp);
3800 break;
3801 case DP_TEST_LINK_EDID_READ:
3802 DRM_DEBUG_KMS("EDID test requested\n");
3803 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3804 response = intel_dp_autotest_edid(intel_dp);
3805 break;
3806 case DP_TEST_LINK_PHY_TEST_PATTERN:
3807 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3808 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3809 response = intel_dp_autotest_phy_pattern(intel_dp);
3810 break;
3811 default:
3812 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3813 break;
3814 }
3815
3816update_status:
3817 status = drm_dp_dpcd_write(&intel_dp->aux,
3818 DP_TEST_RESPONSE,
3819 &response, 1);
3820 if (status <= 0)
3821 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 3822}
3823
0e32b39c
DA		 3824static int
3825intel_dp_check_mst_status(struct intel_dp *intel_dp)
3826{
3827 bool bret;
3828
3829 if (intel_dp->is_mst) {
3830 u8 esi[16] = { 0 };
3831 int ret = 0;
3832 int retry;
3833 bool handled;
3834 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3835go_again:
3836 if (bret == true) {
3837
3838 /* check link status - esi[10] = 0x200c */
19e0b4ca 3839 if (intel_dp->active_mst_links &&
901c2daf 3840 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
0e32b39c
DA		 3841 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3842 intel_dp_start_link_train(intel_dp);
0e32b39c
DA		 3843 intel_dp_stop_link_train(intel_dp);
3844 }
3845
6f34cc39 3846 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 3847 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3848
3849 if (handled) {
3850 for (retry = 0; retry < 3; retry++) {
3851 int wret;
3852 wret = drm_dp_dpcd_write(&intel_dp->aux,
3853 DP_SINK_COUNT_ESI+1,
3854 &esi[1], 3);
3855 if (wret == 3) {
3856 break;
3857 }
3858 }
3859
3860 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3861 if (bret == true) {
6f34cc39 3862 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 3863 goto go_again;
3864 }
3865 } else
3866 ret = 0;
3867
3868 return ret;
3869 } else {
3870 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3871 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3872 intel_dp->is_mst = false;
3873 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3874 /* send a hotplug event */
3875 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3876 }
3877 }
3878 return -EINVAL;
3879}
3880
5c9114d0
SS		 3881static void
3882intel_dp_check_link_status(struct intel_dp *intel_dp)
3883{
3884 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3885 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3886 u8 link_status[DP_LINK_STATUS_SIZE];
3887
3888 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3889
3890 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3891 DRM_ERROR("Failed to get link status\n");
3892 return;
3893 }
3894
3895 if (!intel_encoder->base.crtc)
3896 return;
3897
3898 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3899 return;
3900
3901 /* if link training is requested we should perform it always */
3902 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
3903 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
3904 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3905 intel_encoder->base.name);
3906 intel_dp_start_link_train(intel_dp);
3907 intel_dp_stop_link_train(intel_dp);
3908 }
3909}
3910
a4fc5ed6
KP		 3911/*
3912 * According to DP spec
3913 * 5.1.2:
3914 * 1. Read DPCD
3915 * 2. Configure link according to Receiver Capabilities
3916 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3917 * 4. Check link status on receipt of hot-plug interrupt
39ff747b
SS		 3918 *
3919 * intel_dp_short_pulse - handles short pulse interrupts
3920 * when full detection is not required.
3921 * Returns %true if short pulse is handled and full detection
3922 * is NOT required and %false otherwise.
a4fc5ed6 3923 */
39ff747b 3924static bool
5c9114d0 3925intel_dp_short_pulse(struct intel_dp *intel_dp)
a4fc5ed6 3926{
5b215bcf 3927 struct drm_device *dev = intel_dp_to_dev(intel_dp);
65fbb4e7 3928 u8 sink_irq_vector = 0;
39ff747b
SS		 3929 u8 old_sink_count = intel_dp->sink_count;
3930 bool ret;
5b215bcf 3931
4df6960e
SS		 3932 /*
3933 * Clearing compliance test variables to allow capturing
3934 * of values for next automated test request.
3935 */
3936 intel_dp->compliance_test_active = 0;
3937 intel_dp->compliance_test_type = 0;
3938 intel_dp->compliance_test_data = 0;
3939
39ff747b
SS		 3940 /*
3941 * Now read the DPCD to see if it's actually running
3942 * If the current value of sink count doesn't match with
3943 * the value that was stored earlier or dpcd read failed
3944 * we need to do full detection
3945 */
3946 ret = intel_dp_get_dpcd(intel_dp);
3947
3948 if ((old_sink_count != intel_dp->sink_count) || !ret) {
3949 /* No need to proceed if we are going to do full detect */
3950 return false;
59cd09e1
JB		 3951 }
3952
a60f0e38
JB		 3953 /* Try to read the source of the interrupt */
3954 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
65fbb4e7
VS		 3955 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
3956 sink_irq_vector != 0) {
a60f0e38 3957 /* Clear interrupt source */
9d1a1031
JN		 3958 drm_dp_dpcd_writeb(&intel_dp->aux,
3959 DP_DEVICE_SERVICE_IRQ_VECTOR,
3960 sink_irq_vector);
a60f0e38
JB		 3961
3962 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 3963 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 3964 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3965 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3966 }
3967
5c9114d0
SS		 3968 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3969 intel_dp_check_link_status(intel_dp);
3970 drm_modeset_unlock(&dev->mode_config.connection_mutex);
39ff747b
SS		 3971
3972 return true;
a4fc5ed6 3973}
a4fc5ed6 3974
caf9ab24 3975/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3976static enum drm_connector_status
26d61aad 3977intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3978{
caf9ab24 3979 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3980 uint8_t type;
3981
3982 if (!intel_dp_get_dpcd(intel_dp))
3983 return connector_status_disconnected;
3984
1034ce70
SS		 3985 if (is_edp(intel_dp))
3986 return connector_status_connected;
3987
caf9ab24
AJ		 3988 /* if there's no downstream port, we're done */
3989 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3990 return connector_status_connected;
caf9ab24
AJ		 3991
3992 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3993 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3994 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
9d1a1031 3995
30d9aa42
SS		 3996 return intel_dp->sink_count ?
3997 connector_status_connected : connector_status_disconnected;
caf9ab24
AJ		 3998 }
3999
c4e3170a
VS		 4000 if (intel_dp_can_mst(intel_dp))
4001 return connector_status_connected;
4002
caf9ab24 4003 /* If no HPD, poke DDC gently */
0b99836f 4004 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4005 return connector_status_connected;
caf9ab24
AJ		 4006
4007 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4008 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4009 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4010 if (type == DP_DS_PORT_TYPE_VGA ||
4011 type == DP_DS_PORT_TYPE_NON_EDID)
4012 return connector_status_unknown;
4013 } else {
4014 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4015 DP_DWN_STRM_PORT_TYPE_MASK;
4016 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4017 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4018 return connector_status_unknown;
4019 }
caf9ab24
AJ		 4020
4021 /* Anything else is out of spec, warn and ignore */
4022 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4023 return connector_status_disconnected;
71ba9000
AJ		 4024}
4025
d410b56d
CW		 4026static enum drm_connector_status
4027edp_detect(struct intel_dp *intel_dp)
4028{
4029 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4030 enum drm_connector_status status;
4031
4032 status = intel_panel_detect(dev);
4033 if (status == connector_status_unknown)
4034 status = connector_status_connected;
4035
4036 return status;
4037}
4038
b93433cc
JN		 4039static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4040 struct intel_digital_port *port)
5eb08b69 4041{
b93433cc 4042 u32 bit;
01cb9ea6 4043
0df53b77
JN		 4044 switch (port->port) {
4045 case PORT_A:
4046 return true;
4047 case PORT_B:
4048 bit = SDE_PORTB_HOTPLUG;
4049 break;
4050 case PORT_C:
4051 bit = SDE_PORTC_HOTPLUG;
4052 break;
4053 case PORT_D:
4054 bit = SDE_PORTD_HOTPLUG;
4055 break;
4056 default:
4057 MISSING_CASE(port->port);
4058 return false;
4059 }
4060
4061 return I915_READ(SDEISR) & bit;
4062}
4063
4064static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4065 struct intel_digital_port *port)
4066{
4067 u32 bit;
4068
4069 switch (port->port) {
4070 case PORT_A:
4071 return true;
4072 case PORT_B:
4073 bit = SDE_PORTB_HOTPLUG_CPT;
4074 break;
4075 case PORT_C:
4076 bit = SDE_PORTC_HOTPLUG_CPT;
4077 break;
4078 case PORT_D:
4079 bit = SDE_PORTD_HOTPLUG_CPT;
4080 break;
a78695d3
JN		 4081 case PORT_E:
4082 bit = SDE_PORTE_HOTPLUG_SPT;
4083 break;
0df53b77
JN		 4084 default:
4085 MISSING_CASE(port->port);
4086 return false;
b93433cc 4087 }
1b469639 4088
b93433cc 4089 return I915_READ(SDEISR) & bit;
5eb08b69
ZW		 4090}
4091
7e66bcf2 4092static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
1d245987 4093 struct intel_digital_port *port)
a4fc5ed6 4094{
9642c81c 4095 u32 bit;
5eb08b69 4096
9642c81c
JN		 4097 switch (port->port) {
4098 case PORT_B:
4099 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4100 break;
4101 case PORT_C:
4102 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4103 break;
4104 case PORT_D:
4105 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4106 break;
4107 default:
4108 MISSING_CASE(port->port);
4109 return false;
4110 }
4111
4112 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4113}
4114
0780cd36
VS		 4115static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4116 struct intel_digital_port *port)
9642c81c
JN		 4117{
4118 u32 bit;
4119
4120 switch (port->port) {
4121 case PORT_B:
0780cd36 4122 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4123 break;
4124 case PORT_C:
0780cd36 4125 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4126 break;
4127 case PORT_D:
0780cd36 4128 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4129 break;
4130 default:
4131 MISSING_CASE(port->port);
4132 return false;
a4fc5ed6
KP		 4133 }
4134
1d245987 4135 return I915_READ(PORT_HOTPLUG_STAT) & bit;
2a592bec
DA		 4136}
4137
e464bfde 4138static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
e2ec35a5 4139 struct intel_digital_port *intel_dig_port)
e464bfde 4140{
e2ec35a5
SJ		 4141 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4142 enum port port;
e464bfde
JN		 4143 u32 bit;
4144
e2ec35a5
SJ		 4145 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4146 switch (port) {
e464bfde
JN		 4147 case PORT_A:
4148 bit = BXT_DE_PORT_HP_DDIA;
4149 break;
4150 case PORT_B:
4151 bit = BXT_DE_PORT_HP_DDIB;
4152 break;
4153 case PORT_C:
4154 bit = BXT_DE_PORT_HP_DDIC;
4155 break;
4156 default:
e2ec35a5 4157 MISSING_CASE(port);
e464bfde
JN		 4158 return false;
4159 }
4160
4161 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4162}
4163
7e66bcf2
JN		 4164/*
4165 * intel_digital_port_connected - is the specified port connected?
4166 * @dev_priv: i915 private structure
4167 * @port: the port to test
4168 *
4169 * Return %true if @port is connected, %false otherwise.
4170 */
237ed86c 4171bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
7e66bcf2
JN		 4172 struct intel_digital_port *port)
4173{
0df53b77 4174 if (HAS_PCH_IBX(dev_priv))
7e66bcf2 4175 return ibx_digital_port_connected(dev_priv, port);
22824fac 4176 else if (HAS_PCH_SPLIT(dev_priv))
0df53b77 4177 return cpt_digital_port_connected(dev_priv, port);
e464bfde
JN		 4178 else if (IS_BROXTON(dev_priv))
4179 return bxt_digital_port_connected(dev_priv, port);
0780cd36
VS		 4180 else if (IS_GM45(dev_priv))
4181 return gm45_digital_port_connected(dev_priv, port);
7e66bcf2
JN		 4182 else
4183 return g4x_digital_port_connected(dev_priv, port);
4184}
4185
8c241fef 4186static struct edid *
beb60608 4187intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4188{
beb60608 4189 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4190
9cd300e0
JN		 4191 /* use cached edid if we have one */
4192 if (intel_connector->edid) {
9cd300e0
JN		 4193 /* invalid edid */
4194 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4195 return NULL;
4196
55e9edeb 4197 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4198 } else
4199 return drm_get_edid(&intel_connector->base,
4200 &intel_dp->aux.ddc);
4201}
8c241fef 4202
beb60608
CW		 4203static void
4204intel_dp_set_edid(struct intel_dp *intel_dp)
4205{
4206 struct intel_connector *intel_connector = intel_dp->attached_connector;
4207 struct edid *edid;
8c241fef 4208
f21a2198 4209 intel_dp_unset_edid(intel_dp);
beb60608
CW		 4210 edid = intel_dp_get_edid(intel_dp);
4211 intel_connector->detect_edid = edid;
4212
4213 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4214 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4215 else
4216 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4217}
4218
beb60608
CW		 4219static void
4220intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4221{
beb60608 4222 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4223
beb60608
CW		 4224 kfree(intel_connector->detect_edid);
4225 intel_connector->detect_edid = NULL;
9cd300e0 4226
beb60608
CW		 4227 intel_dp->has_audio = false;
4228}
d6f24d0f 4229
f21a2198
SS		 4230static void
4231intel_dp_long_pulse(struct intel_connector *intel_connector)
a9756bb5 4232{
f21a2198 4233 struct drm_connector *connector = &intel_connector->base;
a9756bb5 4234 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4235 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4236 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4237 struct drm_device *dev = connector->dev;
a9756bb5 4238 enum drm_connector_status status;
671dedd2 4239 enum intel_display_power_domain power_domain;
65fbb4e7 4240 u8 sink_irq_vector = 0;
a9756bb5 4241
25f78f58
VS		 4242 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4243 intel_display_power_get(to_i915(dev), power_domain);
a9756bb5 4244
d410b56d
CW		 4245 /* Can't disconnect eDP, but you can close the lid... */
4246 if (is_edp(intel_dp))
4247 status = edp_detect(intel_dp);
c555a81d
ACO		 4248 else if (intel_digital_port_connected(to_i915(dev),
4249 dp_to_dig_port(intel_dp)))
4250 status = intel_dp_detect_dpcd(intel_dp);
a9756bb5 4251 else
c555a81d
ACO		 4252 status = connector_status_disconnected;
4253
4df6960e
SS		 4254 if (status != connector_status_connected) {
4255 intel_dp->compliance_test_active = 0;
4256 intel_dp->compliance_test_type = 0;
4257 intel_dp->compliance_test_data = 0;
4258
0e505a08 4259 if (intel_dp->is_mst) {
4260 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4261 intel_dp->is_mst,
4262 intel_dp->mst_mgr.mst_state);
4263 intel_dp->is_mst = false;
4264 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4265 intel_dp->is_mst);
4266 }
4267
c8c8fb33 4268 goto out;
4df6960e 4269 }
a9756bb5 4270
f21a2198 4271 if (intel_encoder->type != INTEL_OUTPUT_EDP)
cca0502b 4272 intel_encoder->type = INTEL_OUTPUT_DP;
f21a2198 4273
fe5a66f9
VS		 4274 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4275 yesno(intel_dp_source_supports_hbr2(intel_dp)),
4276 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4277
4278 intel_dp_print_rates(intel_dp);
4279
0d198328
AJ		 4280 intel_dp_probe_oui(intel_dp);
4281
c4e3170a
VS		 4282 intel_dp_configure_mst(intel_dp);
4283
4284 if (intel_dp->is_mst) {
f21a2198
SS		 4285 /*
4286 * If we are in MST mode then this connector
4287 * won't appear connected or have anything
4288 * with EDID on it
4289 */
0e32b39c
DA		 4290 status = connector_status_disconnected;
4291 goto out;
7d23e3c3
SS		 4292 } else if (connector->status == connector_status_connected) {
4293 /*
4294 * If display was connected already and is still connected
4295 * check links status, there has been known issues of
4296 * link loss triggerring long pulse!!!!
4297 */
4298 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4299 intel_dp_check_link_status(intel_dp);
4300 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4301 goto out;
0e32b39c
DA		 4302 }
4303
4df6960e
SS		 4304 /*
4305 * Clearing NACK and defer counts to get their exact values
4306 * while reading EDID which are required by Compliance tests
4307 * 4.2.2.4 and 4.2.2.5
4308 */
4309 intel_dp->aux.i2c_nack_count = 0;
4310 intel_dp->aux.i2c_defer_count = 0;
4311
beb60608 4312 intel_dp_set_edid(intel_dp);
a9756bb5 4313
c8c8fb33 4314 status = connector_status_connected;
7d23e3c3 4315 intel_dp->detect_done = true;
c8c8fb33 4316
09b1eb13
TP		 4317 /* Try to read the source of the interrupt */
4318 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
65fbb4e7
VS		 4319 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4320 sink_irq_vector != 0) {
09b1eb13
TP		 4321 /* Clear interrupt source */
4322 drm_dp_dpcd_writeb(&intel_dp->aux,
4323 DP_DEVICE_SERVICE_IRQ_VECTOR,
4324 sink_irq_vector);
4325
4326 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4327 intel_dp_handle_test_request(intel_dp);
4328 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4329 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4330 }
4331
c8c8fb33 4332out:
0e505a08 4333 if ((status != connector_status_connected) &&
4334 (intel_dp->is_mst == false))
f21a2198 4335 intel_dp_unset_edid(intel_dp);
7d23e3c3 4336
25f78f58 4337 intel_display_power_put(to_i915(dev), power_domain);
f21a2198
SS		 4338 return;
4339}
4340
4341static enum drm_connector_status
4342intel_dp_detect(struct drm_connector *connector, bool force)
4343{
4344 struct intel_dp *intel_dp = intel_attached_dp(connector);
4345 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4346 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4347 struct intel_connector *intel_connector = to_intel_connector(connector);
4348
4349 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4350 connector->base.id, connector->name);
4351
4352 if (intel_dp->is_mst) {
4353 /* MST devices are disconnected from a monitor POV */
4354 intel_dp_unset_edid(intel_dp);
4355 if (intel_encoder->type != INTEL_OUTPUT_EDP)
cca0502b 4356 intel_encoder->type = INTEL_OUTPUT_DP;
f21a2198
SS		 4357 return connector_status_disconnected;
4358 }
4359
7d23e3c3
SS		 4360 /* If full detect is not performed yet, do a full detect */
4361 if (!intel_dp->detect_done)
4362 intel_dp_long_pulse(intel_dp->attached_connector);
4363
4364 intel_dp->detect_done = false;
f21a2198 4365
1b7f2c8b 4366 if (is_edp(intel_dp) || intel_connector->detect_edid)
f21a2198
SS		 4367 return connector_status_connected;
4368 else
4369 return connector_status_disconnected;
a4fc5ed6
KP		 4370}
4371
beb60608
CW		 4372static void
4373intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4374{
df0e9248 4375 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4376 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
25f78f58 4377 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
671dedd2 4378 enum intel_display_power_domain power_domain;
a4fc5ed6 4379
beb60608
CW		 4380 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4381 connector->base.id, connector->name);
4382 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4383
beb60608
CW		 4384 if (connector->status != connector_status_connected)
4385 return;
671dedd2 4386
25f78f58
VS		 4387 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4388 intel_display_power_get(dev_priv, power_domain);
beb60608
CW		 4389
4390 intel_dp_set_edid(intel_dp);
4391
25f78f58 4392 intel_display_power_put(dev_priv, power_domain);
beb60608
CW		 4393
4394 if (intel_encoder->type != INTEL_OUTPUT_EDP)
cca0502b 4395 intel_encoder->type = INTEL_OUTPUT_DP;
beb60608
CW		 4396}
4397
4398static int intel_dp_get_modes(struct drm_connector *connector)
4399{
4400 struct intel_connector *intel_connector = to_intel_connector(connector);
4401 struct edid *edid;
4402
4403 edid = intel_connector->detect_edid;
4404 if (edid) {
4405 int ret = intel_connector_update_modes(connector, edid);
4406 if (ret)
4407 return ret;
4408 }
32f9d658 4409
f8779fda 4410 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4411 if (is_edp(intel_attached_dp(connector)) &&
4412 intel_connector->panel.fixed_mode) {
f8779fda 4413 struct drm_display_mode *mode;
beb60608
CW		 4414
4415 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4416 intel_connector->panel.fixed_mode);
f8779fda 4417 if (mode) {
32f9d658
ZW		 4418 drm_mode_probed_add(connector, mode);
4419 return 1;
4420 }
4421 }
beb60608 4422
32f9d658 4423 return 0;
a4fc5ed6
KP		 4424}
4425
1aad7ac0
CW		 4426static bool
4427intel_dp_detect_audio(struct drm_connector *connector)
4428{
1aad7ac0 4429 bool has_audio = false;
beb60608 4430 struct edid *edid;
1aad7ac0 4431
beb60608
CW		 4432 edid = to_intel_connector(connector)->detect_edid;
4433 if (edid)
1aad7ac0 4434 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4435
1aad7ac0
CW		 4436 return has_audio;
4437}
4438
f684960e
CW		 4439static int
4440intel_dp_set_property(struct drm_connector *connector,
4441 struct drm_property *property,
4442 uint64_t val)
4443{
fac5e23e 4444 struct drm_i915_private *dev_priv = to_i915(connector->dev);
53b41837 4445 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4446 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4447 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4448 int ret;
4449
662595df 4450 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4451 if (ret)
4452 return ret;
4453
3f43c48d 4454 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4455 int i = val;
4456 bool has_audio;
4457
4458 if (i == intel_dp->force_audio)
f684960e
CW		 4459 return 0;
4460
1aad7ac0 4461 intel_dp->force_audio = i;
f684960e 4462
c3e5f67b 4463 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4464 has_audio = intel_dp_detect_audio(connector);
4465 else
c3e5f67b 4466 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4467
4468 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4469 return 0;
4470
1aad7ac0 4471 intel_dp->has_audio = has_audio;
f684960e
CW		 4472 goto done;
4473 }
4474
e953fd7b 4475 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 4476 bool old_auto = intel_dp->color_range_auto;
0f2a2a75 4477 bool old_range = intel_dp->limited_color_range;
ae4edb80 4478
55bc60db
VS		 4479 switch (val) {
4480 case INTEL_BROADCAST_RGB_AUTO:
4481 intel_dp->color_range_auto = true;
4482 break;
4483 case INTEL_BROADCAST_RGB_FULL:
4484 intel_dp->color_range_auto = false;
0f2a2a75 4485 intel_dp->limited_color_range = false;
55bc60db
VS		 4486 break;
4487 case INTEL_BROADCAST_RGB_LIMITED:
4488 intel_dp->color_range_auto = false;
0f2a2a75 4489 intel_dp->limited_color_range = true;
55bc60db
VS		 4490 break;
4491 default:
4492 return -EINVAL;
4493 }
ae4edb80
DV		 4494
4495 if (old_auto == intel_dp->color_range_auto &&
0f2a2a75 4496 old_range == intel_dp->limited_color_range)
ae4edb80
DV		 4497 return 0;
4498
e953fd7b
CW		 4499 goto done;
4500 }
4501
53b41837
YN		 4502 if (is_edp(intel_dp) &&
4503 property == connector->dev->mode_config.scaling_mode_property) {
4504 if (val == DRM_MODE_SCALE_NONE) {
4505 DRM_DEBUG_KMS("no scaling not supported\n");
4506 return -EINVAL;
4507 }
234126c6
VS		 4508 if (HAS_GMCH_DISPLAY(dev_priv) &&
4509 val == DRM_MODE_SCALE_CENTER) {
4510 DRM_DEBUG_KMS("centering not supported\n");
4511 return -EINVAL;
4512 }
53b41837
YN		 4513
4514 if (intel_connector->panel.fitting_mode == val) {
4515 /* the eDP scaling property is not changed */
4516 return 0;
4517 }
4518 intel_connector->panel.fitting_mode = val;
4519
4520 goto done;
4521 }
4522
f684960e
CW		 4523 return -EINVAL;
4524
4525done:
c0c36b94
CW		 4526 if (intel_encoder->base.crtc)
4527 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4528
4529 return 0;
4530}
4531
7a418e34
CW		 4532static int
4533intel_dp_connector_register(struct drm_connector *connector)
4534{
4535 struct intel_dp *intel_dp = intel_attached_dp(connector);
1ebaa0b9
CW		 4536 int ret;
4537
4538 ret = intel_connector_register(connector);
4539 if (ret)
4540 return ret;
7a418e34
CW		 4541
4542 i915_debugfs_connector_add(connector);
4543
4544 DRM_DEBUG_KMS("registering %s bus for %s\n",
4545 intel_dp->aux.name, connector->kdev->kobj.name);
4546
4547 intel_dp->aux.dev = connector->kdev;
4548 return drm_dp_aux_register(&intel_dp->aux);
4549}
4550
c191eca1
CW		 4551static void
4552intel_dp_connector_unregister(struct drm_connector *connector)
4553{
4554 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4555 intel_connector_unregister(connector);
4556}
4557
a4fc5ed6 4558static void
73845adf 4559intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4560{
1d508706 4561 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4562
10e972d3 4563 kfree(intel_connector->detect_edid);
beb60608 4564
9cd300e0
JN		 4565 if (!IS_ERR_OR_NULL(intel_connector->edid))
4566 kfree(intel_connector->edid);
4567
acd8db10
PZ		 4568 /* Can't call is_edp() since the encoder may have been destroyed
4569 * already. */
4570 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4571 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4572
a4fc5ed6 4573 drm_connector_cleanup(connector);
55f78c43 4574 kfree(connector);
a4fc5ed6
KP		 4575}
4576
00c09d70 4577void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4578{
da63a9f2
PZ		 4579 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4580 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4581
0e32b39c 4582 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4583 if (is_edp(intel_dp)) {
4584 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4585 /*
4586 * vdd might still be enabled do to the delayed vdd off.
4587 * Make sure vdd is actually turned off here.
4588 */
773538e8 4589 pps_lock(intel_dp);
4be73780 4590 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4591 pps_unlock(intel_dp);
4592
01527b31
CT		 4593 if (intel_dp->edp_notifier.notifier_call) {
4594 unregister_reboot_notifier(&intel_dp->edp_notifier);
4595 intel_dp->edp_notifier.notifier_call = NULL;
4596 }
bd943159 4597 }
99681886
CW		 4598
4599 intel_dp_aux_fini(intel_dp);
4600
c8bd0e49 4601 drm_encoder_cleanup(encoder);
da63a9f2 4602 kfree(intel_dig_port);
24d05927
DV		 4603}
4604
bf93ba67 4605void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
07f9cd0b
ID		 4606{
4607 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4608
4609 if (!is_edp(intel_dp))
4610 return;
4611
951468f3
VS		 4612 /*
4613 * vdd might still be enabled do to the delayed vdd off.
4614 * Make sure vdd is actually turned off here.
4615 */
afa4e53a 4616 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4617 pps_lock(intel_dp);
07f9cd0b 4618 edp_panel_vdd_off_sync(intel_dp);
773538e8 4619 pps_unlock(intel_dp);
07f9cd0b
ID		 4620}
4621
49e6bc51
VS		 4622static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4623{
4624 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4625 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 4626 struct drm_i915_private *dev_priv = to_i915(dev);
49e6bc51
VS		 4627 enum intel_display_power_domain power_domain;
4628
4629 lockdep_assert_held(&dev_priv->pps_mutex);
4630
4631 if (!edp_have_panel_vdd(intel_dp))
4632 return;
4633
4634 /*
4635 * The VDD bit needs a power domain reference, so if the bit is
4636 * already enabled when we boot or resume, grab this reference and
4637 * schedule a vdd off, so we don't hold on to the reference
4638 * indefinitely.
4639 */
4640 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
25f78f58 4641 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
49e6bc51
VS		 4642 intel_display_power_get(dev_priv, power_domain);
4643
4644 edp_panel_vdd_schedule_off(intel_dp);
4645}
4646
bf93ba67 4647void intel_dp_encoder_reset(struct drm_encoder *encoder)
6d93c0c4 4648{
64989ca4
VS		 4649 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4650 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4651
4652 if (!HAS_DDI(dev_priv))
4653 intel_dp->DP = I915_READ(intel_dp->output_reg);
49e6bc51
VS		 4654
4655 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4656 return;
4657
49e6bc51
VS		 4658 pps_lock(intel_dp);
4659
4660 /*
4661 * Read out the current power sequencer assignment,
4662 * in case the BIOS did something with it.
4663 */
666a4537 4664 if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
49e6bc51
VS		 4665 vlv_initial_power_sequencer_setup(intel_dp);
4666
4667 intel_edp_panel_vdd_sanitize(intel_dp);
4668
4669 pps_unlock(intel_dp);
6d93c0c4
ID		 4670}
4671
a4fc5ed6 4672static const struct drm_connector_funcs intel_dp_connector_funcs = {
4d688a2a 4673 .dpms = drm_atomic_helper_connector_dpms,
a4fc5ed6 4674 .detect = intel_dp_detect,
beb60608 4675 .force = intel_dp_force,
a4fc5ed6 4676 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4677 .set_property = intel_dp_set_property,
2545e4a6 4678 .atomic_get_property = intel_connector_atomic_get_property,
7a418e34 4679 .late_register = intel_dp_connector_register,
c191eca1 4680 .early_unregister = intel_dp_connector_unregister,
73845adf 4681 .destroy = intel_dp_connector_destroy,
c6f95f27 4682 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4683 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4684};
4685
4686static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4687 .get_modes = intel_dp_get_modes,
4688 .mode_valid = intel_dp_mode_valid,
a4fc5ed6
KP		 4689};
4690
a4fc5ed6 4691static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4692 .reset = intel_dp_encoder_reset,
24d05927 4693 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4694};
4695
b2c5c181 4696enum irqreturn
13cf5504
DA		 4697intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4698{
4699 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4700 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c 4701 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 4702 struct drm_i915_private *dev_priv = to_i915(dev);
1c767b33 4703 enum intel_display_power_domain power_domain;
b2c5c181 4704 enum irqreturn ret = IRQ_NONE;
1c767b33 4705
2540058f
TI		 4706 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4707 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
cca0502b 4708 intel_dig_port->base.type = INTEL_OUTPUT_DP;
13cf5504 4709
7a7f84cc
VS		 4710 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4711 /*
4712 * vdd off can generate a long pulse on eDP which
4713 * would require vdd on to handle it, and thus we
4714 * would end up in an endless cycle of
4715 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4716 */
4717 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4718 port_name(intel_dig_port->port));
a8b3d52f 4719 return IRQ_HANDLED;
7a7f84cc
VS		 4720 }
4721
26fbb774
VS		 4722 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4723 port_name(intel_dig_port->port),
0e32b39c 4724 long_hpd ? "long" : "short");
13cf5504 4725
25f78f58 4726 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1c767b33
ID		 4727 intel_display_power_get(dev_priv, power_domain);
4728
0e32b39c 4729 if (long_hpd) {
7d23e3c3
SS		 4730 intel_dp_long_pulse(intel_dp->attached_connector);
4731 if (intel_dp->is_mst)
4732 ret = IRQ_HANDLED;
4733 goto put_power;
0e32b39c 4734
0e32b39c
DA		 4735 } else {
4736 if (intel_dp->is_mst) {
7d23e3c3
SS		 4737 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4738 /*
4739 * If we were in MST mode, and device is not
4740 * there, get out of MST mode
4741 */
4742 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4743 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4744 intel_dp->is_mst = false;
4745 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4746 intel_dp->is_mst);
4747 goto put_power;
4748 }
0e32b39c
DA		 4749 }
4750
39ff747b
SS		 4751 if (!intel_dp->is_mst) {
4752 if (!intel_dp_short_pulse(intel_dp)) {
4753 intel_dp_long_pulse(intel_dp->attached_connector);
4754 goto put_power;
4755 }
4756 }
0e32b39c 4757 }
b2c5c181
DV		 4758
4759 ret = IRQ_HANDLED;
4760
1c767b33
ID		 4761put_power:
4762 intel_display_power_put(dev_priv, power_domain);
4763
4764 return ret;
13cf5504
DA		 4765}
4766
477ec328 4767/* check the VBT to see whether the eDP is on another port */
5d8a7752 4768bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18 4769{
fac5e23e 4770 struct drm_i915_private *dev_priv = to_i915(dev);
36e83a18 4771
53ce81a7
VS		 4772 /*
4773 * eDP not supported on g4x. so bail out early just
4774 * for a bit extra safety in case the VBT is bonkers.
4775 */
4776 if (INTEL_INFO(dev)->gen < 5)
4777 return false;
4778
3b32a35b
VS		 4779 if (port == PORT_A)
4780 return true;
4781
951d9efe 4782 return intel_bios_is_port_edp(dev_priv, port);
36e83a18
ZY		 4783}
4784
0e32b39c 4785void
f684960e
CW		 4786intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4787{
53b41837
YN		 4788 struct intel_connector *intel_connector = to_intel_connector(connector);
4789
3f43c48d 4790 intel_attach_force_audio_property(connector);
e953fd7b 4791 intel_attach_broadcast_rgb_property(connector);
55bc60db 4792 intel_dp->color_range_auto = true;
53b41837
YN		 4793
4794 if (is_edp(intel_dp)) {
4795 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4796 drm_object_attach_property(
4797 &connector->base,
53b41837 4798 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4799 DRM_MODE_SCALE_ASPECT);
4800 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4801 }
f684960e
CW		 4802}
4803
dada1a9f
ID		 4804static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4805{
d28d4731 4806 intel_dp->panel_power_off_time = ktime_get_boottime();
dada1a9f
ID		 4807 intel_dp->last_power_on = jiffies;
4808 intel_dp->last_backlight_off = jiffies;
4809}
4810
67a54566 4811static void
54648618
ID		 4812intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
4813 struct intel_dp *intel_dp, struct edp_power_seq *seq)
67a54566 4814{
b0a08bec 4815 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
8e8232d5 4816 struct pps_registers regs;
453c5420 4817
8e8232d5 4818 intel_pps_get_registers(dev_priv, intel_dp, &regs);
67a54566
DV		 4819
4820 /* Workaround: Need to write PP_CONTROL with the unlock key as
4821 * the very first thing. */
b0a08bec 4822 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 4823
8e8232d5
ID		 4824 pp_on = I915_READ(regs.pp_on);
4825 pp_off = I915_READ(regs.pp_off);
54648618 4826 if (!IS_BROXTON(dev_priv)) {
8e8232d5
ID		 4827 I915_WRITE(regs.pp_ctrl, pp_ctl);
4828 pp_div = I915_READ(regs.pp_div);
b0a08bec 4829 }
67a54566
DV		 4830
4831 /* Pull timing values out of registers */
54648618
ID		 4832 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4833 PANEL_POWER_UP_DELAY_SHIFT;
67a54566 4834
54648618
ID		 4835 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4836 PANEL_LIGHT_ON_DELAY_SHIFT;
67a54566 4837
54648618
ID		 4838 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4839 PANEL_LIGHT_OFF_DELAY_SHIFT;
67a54566 4840
54648618
ID		 4841 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4842 PANEL_POWER_DOWN_DELAY_SHIFT;
67a54566 4843
54648618 4844 if (IS_BROXTON(dev_priv)) {
b0a08bec
VK		 4845 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4846 BXT_POWER_CYCLE_DELAY_SHIFT;
4847 if (tmp > 0)
54648618 4848 seq->t11_t12 = (tmp - 1) * 1000;
b0a08bec 4849 else
54648618 4850 seq->t11_t12 = 0;
b0a08bec 4851 } else {
54648618 4852 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 4853 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 4854 }
54648618
ID		 4855}
4856
de9c1b6b
ID		 4857static void
4858intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
4859{
4860 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4861 state_name,
4862 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
4863}
4864
4865static void
4866intel_pps_verify_state(struct drm_i915_private *dev_priv,
4867 struct intel_dp *intel_dp)
4868{
4869 struct edp_power_seq hw;
4870 struct edp_power_seq *sw = &intel_dp->pps_delays;
4871
4872 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
4873
4874 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
4875 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
4876 DRM_ERROR("PPS state mismatch\n");
4877 intel_pps_dump_state("sw", sw);
4878 intel_pps_dump_state("hw", &hw);
4879 }
4880}
4881
54648618
ID		 4882static void
4883intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4884 struct intel_dp *intel_dp)
4885{
fac5e23e 4886 struct drm_i915_private *dev_priv = to_i915(dev);
54648618
ID		 4887 struct edp_power_seq cur, vbt, spec,
4888 *final = &intel_dp->pps_delays;
4889
4890 lockdep_assert_held(&dev_priv->pps_mutex);
4891
4892 /* already initialized? */
4893 if (final->t11_t12 != 0)
4894 return;
4895
4896 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
67a54566 4897
de9c1b6b 4898 intel_pps_dump_state("cur", &cur);
67a54566 4899
6aa23e65 4900 vbt = dev_priv->vbt.edp.pps;
67a54566
DV		 4901
4902 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4903 * our hw here, which are all in 100usec. */
4904 spec.t1_t3 = 210 * 10;
4905 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4906 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4907 spec.t10 = 500 * 10;
4908 /* This one is special and actually in units of 100ms, but zero
4909 * based in the hw (so we need to add 100 ms). But the sw vbt
4910 * table multiplies it with 1000 to make it in units of 100usec,
4911 * too. */
4912 spec.t11_t12 = (510 + 100) * 10;
4913
de9c1b6b 4914 intel_pps_dump_state("vbt", &vbt);
67a54566
DV		 4915
4916 /* Use the max of the register settings and vbt. If both are
4917 * unset, fall back to the spec limits. */
36b5f425 4918#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4919 spec.field : \
4920 max(cur.field, vbt.field))
4921 assign_final(t1_t3);
4922 assign_final(t8);
4923 assign_final(t9);
4924 assign_final(t10);
4925 assign_final(t11_t12);
4926#undef assign_final
4927
36b5f425 4928#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4929 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4930 intel_dp->backlight_on_delay = get_delay(t8);
4931 intel_dp->backlight_off_delay = get_delay(t9);
4932 intel_dp->panel_power_down_delay = get_delay(t10);
4933 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4934#undef get_delay
4935
f30d26e4
JN		 4936 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4937 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4938 intel_dp->panel_power_cycle_delay);
4939
4940 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4941 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
de9c1b6b
ID		 4942
4943 /*
4944 * We override the HW backlight delays to 1 because we do manual waits
4945 * on them. For T8, even BSpec recommends doing it. For T9, if we
4946 * don't do this, we'll end up waiting for the backlight off delay
4947 * twice: once when we do the manual sleep, and once when we disable
4948 * the panel and wait for the PP_STATUS bit to become zero.
4949 */
4950 final->t8 = 1;
4951 final->t9 = 1;
f30d26e4
JN		 4952}
4953
4954static void
4955intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4956 struct intel_dp *intel_dp)
f30d26e4 4957{
fac5e23e 4958 struct drm_i915_private *dev_priv = to_i915(dev);
453c5420 4959 u32 pp_on, pp_off, pp_div, port_sel = 0;
e7dc33f3 4960 int div = dev_priv->rawclk_freq / 1000;
8e8232d5 4961 struct pps_registers regs;
ad933b56 4962 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4963 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4964
e39b999a 4965 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 4966
8e8232d5 4967 intel_pps_get_registers(dev_priv, intel_dp, &regs);
453c5420 4968
f30d26e4 4969 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
de9c1b6b
ID		 4970 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
4971 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4972 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4973 /* Compute the divisor for the pp clock, simply match the Bspec
4974 * formula. */
b0a08bec 4975 if (IS_BROXTON(dev)) {
8e8232d5 4976 pp_div = I915_READ(regs.pp_ctrl);
b0a08bec
VK		 4977 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
4978 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
4979 << BXT_POWER_CYCLE_DELAY_SHIFT);
4980 } else {
4981 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4982 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4983 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4984 }
67a54566
DV		 4985
4986 /* Haswell doesn't have any port selection bits for the panel
4987 * power sequencer any more. */
666a4537 4988 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
ad933b56 4989 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4990 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4991 if (port == PORT_A)
a24c144c 4992 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4993 else
a24c144c 4994 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4995 }
4996
453c5420
JB		 4997 pp_on |= port_sel;
4998
8e8232d5
ID		 4999 I915_WRITE(regs.pp_on, pp_on);
5000 I915_WRITE(regs.pp_off, pp_off);
b0a08bec 5001 if (IS_BROXTON(dev))
8e8232d5 5002 I915_WRITE(regs.pp_ctrl, pp_div);
b0a08bec 5003 else
8e8232d5 5004 I915_WRITE(regs.pp_div, pp_div);
67a54566 5005
67a54566 5006 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
8e8232d5
ID		 5007 I915_READ(regs.pp_on),
5008 I915_READ(regs.pp_off),
b0a08bec 5009 IS_BROXTON(dev) ?
8e8232d5
ID		 5010 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5011 I915_READ(regs.pp_div));
f684960e
CW		 5012}
5013
b33a2815
VK		 5014/**
5015 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5016 * @dev: DRM device
5017 * @refresh_rate: RR to be programmed
5018 *
5019 * This function gets called when refresh rate (RR) has to be changed from
5020 * one frequency to another. Switches can be between high and low RR
5021 * supported by the panel or to any other RR based on media playback (in
5022 * this case, RR value needs to be passed from user space).
5023 *
5024 * The caller of this function needs to take a lock on dev_priv->drrs.
5025 */
96178eeb 5026static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0 5027{
fac5e23e 5028 struct drm_i915_private *dev_priv = to_i915(dev);
439d7ac0 5029 struct intel_encoder *encoder;
96178eeb
VK		 5030 struct intel_digital_port *dig_port = NULL;
5031 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 5032 struct intel_crtc_state *config = NULL;
439d7ac0 5033 struct intel_crtc *intel_crtc = NULL;
96178eeb 5034 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5035
5036 if (refresh_rate <= 0) {
5037 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5038 return;
5039 }
5040
96178eeb
VK		 5041 if (intel_dp == NULL) {
5042 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5043 return;
5044 }
5045
1fcc9d1c 5046 /*
e4d59f6b
RV		 5047 * FIXME: This needs proper synchronization with psr state for some
5048 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5049 */
439d7ac0 5050
96178eeb
VK		 5051 dig_port = dp_to_dig_port(intel_dp);
5052 encoder = &dig_port->base;
723f9aab 5053 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5054
5055 if (!intel_crtc) {
5056 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5057 return;
5058 }
5059
6e3c9717 5060 config = intel_crtc->config;
439d7ac0 5061
96178eeb 5062 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5063 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5064 return;
5065 }
5066
96178eeb
VK		 5067 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5068 refresh_rate)
439d7ac0
PB		 5069 index = DRRS_LOW_RR;
5070
96178eeb 5071 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5072 DRM_DEBUG_KMS(
5073 "DRRS requested for previously set RR...ignoring\n");
5074 return;
5075 }
5076
5077 if (!intel_crtc->active) {
5078 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5079 return;
5080 }
5081
44395bfe 5082 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5083 switch (index) {
5084 case DRRS_HIGH_RR:
5085 intel_dp_set_m_n(intel_crtc, M1_N1);
5086 break;
5087 case DRRS_LOW_RR:
5088 intel_dp_set_m_n(intel_crtc, M2_N2);
5089 break;
5090 case DRRS_MAX_RR:
5091 default:
5092 DRM_ERROR("Unsupported refreshrate type\n");
5093 }
5094 } else if (INTEL_INFO(dev)->gen > 6) {
f0f59a00 5095 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
649636ef 5096 u32 val;
a4c30b1d 5097
649636ef 5098 val = I915_READ(reg);
439d7ac0 5099 if (index > DRRS_HIGH_RR) {
666a4537 5100 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6fa7aec1
VK		 5101 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5102 else
5103 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5104 } else {
666a4537 5105 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6fa7aec1
VK		 5106 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5107 else
5108 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5109 }
5110 I915_WRITE(reg, val);
5111 }
5112
4e9ac947
VK		 5113 dev_priv->drrs.refresh_rate_type = index;
5114
5115 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5116}
5117
b33a2815
VK		 5118/**
5119 * intel_edp_drrs_enable - init drrs struct if supported
5120 * @intel_dp: DP struct
5121 *
5122 * Initializes frontbuffer_bits and drrs.dp
5123 */
c395578e
VK		 5124void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5125{
5126 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 5127 struct drm_i915_private *dev_priv = to_i915(dev);
c395578e
VK		 5128 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5129 struct drm_crtc *crtc = dig_port->base.base.crtc;
5130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5131
5132 if (!intel_crtc->config->has_drrs) {
5133 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5134 return;
5135 }
5136
5137 mutex_lock(&dev_priv->drrs.mutex);
5138 if (WARN_ON(dev_priv->drrs.dp)) {
5139 DRM_ERROR("DRRS already enabled\n");
5140 goto unlock;
5141 }
5142
5143 dev_priv->drrs.busy_frontbuffer_bits = 0;
5144
5145 dev_priv->drrs.dp = intel_dp;
5146
5147unlock:
5148 mutex_unlock(&dev_priv->drrs.mutex);
5149}
5150
b33a2815
VK		 5151/**
5152 * intel_edp_drrs_disable - Disable DRRS
5153 * @intel_dp: DP struct
5154 *
5155 */
c395578e
VK		 5156void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5157{
5158 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 5159 struct drm_i915_private *dev_priv = to_i915(dev);
c395578e
VK		 5160 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5161 struct drm_crtc *crtc = dig_port->base.base.crtc;
5162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5163
5164 if (!intel_crtc->config->has_drrs)
5165 return;
5166
5167 mutex_lock(&dev_priv->drrs.mutex);
5168 if (!dev_priv->drrs.dp) {
5169 mutex_unlock(&dev_priv->drrs.mutex);
5170 return;
5171 }
5172
5173 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
91c8a326
CW		 5174 intel_dp_set_drrs_state(&dev_priv->drm,
5175 intel_dp->attached_connector->panel.
5176 fixed_mode->vrefresh);
c395578e
VK		 5177
5178 dev_priv->drrs.dp = NULL;
5179 mutex_unlock(&dev_priv->drrs.mutex);
5180
5181 cancel_delayed_work_sync(&dev_priv->drrs.work);
5182}
5183
4e9ac947
VK		 5184static void intel_edp_drrs_downclock_work(struct work_struct *work)
5185{
5186 struct drm_i915_private *dev_priv =
5187 container_of(work, typeof(*dev_priv), drrs.work.work);
5188 struct intel_dp *intel_dp;
5189
5190 mutex_lock(&dev_priv->drrs.mutex);
5191
5192 intel_dp = dev_priv->drrs.dp;
5193
5194 if (!intel_dp)
5195 goto unlock;
5196
439d7ac0 5197 /*
4e9ac947
VK		 5198 * The delayed work can race with an invalidate hence we need to
5199 * recheck.
439d7ac0
PB		 5200 */
5201
4e9ac947
VK		 5202 if (dev_priv->drrs.busy_frontbuffer_bits)
5203 goto unlock;
439d7ac0 5204
4e9ac947 5205 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
91c8a326
CW		 5206 intel_dp_set_drrs_state(&dev_priv->drm,
5207 intel_dp->attached_connector->panel.
5208 downclock_mode->vrefresh);
439d7ac0 5209
4e9ac947 5210unlock:
4e9ac947 5211 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5212}
5213
b33a2815 5214/**
0ddfd203 5215 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5748b6a1 5216 * @dev_priv: i915 device
b33a2815
VK		 5217 * @frontbuffer_bits: frontbuffer plane tracking bits
5218 *
0ddfd203
R		 5219 * This function gets called everytime rendering on the given planes start.
5220 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5221 *
5222 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5223 */
5748b6a1
CW		 5224void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5225 unsigned int frontbuffer_bits)
a93fad0f 5226{
a93fad0f
VK		 5227 struct drm_crtc *crtc;
5228 enum pipe pipe;
5229
9da7d693 5230 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5231 return;
5232
88f933a8 5233 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5234
a93fad0f 5235 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5236 if (!dev_priv->drrs.dp) {
5237 mutex_unlock(&dev_priv->drrs.mutex);
5238 return;
5239 }
5240
a93fad0f
VK		 5241 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5242 pipe = to_intel_crtc(crtc)->pipe;
5243
c1d038c6
DV		 5244 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5245 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5246
0ddfd203 5247 /* invalidate means busy screen hence upclock */
c1d038c6 5248 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
91c8a326
CW		 5249 intel_dp_set_drrs_state(&dev_priv->drm,
5250 dev_priv->drrs.dp->attached_connector->panel.
5251 fixed_mode->vrefresh);
a93fad0f 5252
a93fad0f
VK		 5253 mutex_unlock(&dev_priv->drrs.mutex);
5254}
5255
b33a2815 5256/**
0ddfd203 5257 * intel_edp_drrs_flush - Restart Idleness DRRS
5748b6a1 5258 * @dev_priv: i915 device
b33a2815
VK		 5259 * @frontbuffer_bits: frontbuffer plane tracking bits
5260 *
0ddfd203
R		 5261 * This function gets called every time rendering on the given planes has
5262 * completed or flip on a crtc is completed. So DRRS should be upclocked
5263 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5264 * if no other planes are dirty.
b33a2815
VK		 5265 *
5266 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5267 */
5748b6a1
CW		 5268void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5269 unsigned int frontbuffer_bits)
a93fad0f 5270{
a93fad0f
VK		 5271 struct drm_crtc *crtc;
5272 enum pipe pipe;
5273
9da7d693 5274 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5275 return;
5276
88f933a8 5277 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5278
a93fad0f 5279 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5280 if (!dev_priv->drrs.dp) {
5281 mutex_unlock(&dev_priv->drrs.mutex);
5282 return;
5283 }
5284
a93fad0f
VK		 5285 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5286 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5287
5288 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5289 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5290
0ddfd203 5291 /* flush means busy screen hence upclock */
c1d038c6 5292 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
91c8a326
CW		 5293 intel_dp_set_drrs_state(&dev_priv->drm,
5294 dev_priv->drrs.dp->attached_connector->panel.
5295 fixed_mode->vrefresh);
0ddfd203
R		 5296
5297 /*
5298 * flush also means no more activity hence schedule downclock, if all
5299 * other fbs are quiescent too
5300 */
5301 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5302 schedule_delayed_work(&dev_priv->drrs.work,
5303 msecs_to_jiffies(1000));
5304 mutex_unlock(&dev_priv->drrs.mutex);
5305}
5306
b33a2815
VK		 5307/**
5308 * DOC: Display Refresh Rate Switching (DRRS)
5309 *
5310 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5311 * which enables swtching between low and high refresh rates,
5312 * dynamically, based on the usage scenario. This feature is applicable
5313 * for internal panels.
5314 *
5315 * Indication that the panel supports DRRS is given by the panel EDID, which
5316 * would list multiple refresh rates for one resolution.
5317 *
5318 * DRRS is of 2 types - static and seamless.
5319 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5320 * (may appear as a blink on screen) and is used in dock-undock scenario.
5321 * Seamless DRRS involves changing RR without any visual effect to the user
5322 * and can be used during normal system usage. This is done by programming
5323 * certain registers.
5324 *
5325 * Support for static/seamless DRRS may be indicated in the VBT based on
5326 * inputs from the panel spec.
5327 *
5328 * DRRS saves power by switching to low RR based on usage scenarios.
5329 *
2e7a5701
DV		 5330 * The implementation is based on frontbuffer tracking implementation. When
5331 * there is a disturbance on the screen triggered by user activity or a periodic
5332 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5333 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5334 * made.
5335 *
5336 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5337 * and intel_edp_drrs_flush() are called.
b33a2815
VK		 5338 *
5339 * DRRS can be further extended to support other internal panels and also
5340 * the scenario of video playback wherein RR is set based on the rate
5341 * requested by userspace.
5342 */
5343
5344/**
5345 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5346 * @intel_connector: eDP connector
5347 * @fixed_mode: preferred mode of panel
5348 *
5349 * This function is called only once at driver load to initialize basic
5350 * DRRS stuff.
5351 *
5352 * Returns:
5353 * Downclock mode if panel supports it, else return NULL.
5354 * DRRS support is determined by the presence of downclock mode (apart
5355 * from VBT setting).
5356 */
4f9db5b5 5357static struct drm_display_mode *
96178eeb
VK		 5358intel_dp_drrs_init(struct intel_connector *intel_connector,
5359 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5360{
5361 struct drm_connector *connector = &intel_connector->base;
96178eeb 5362 struct drm_device *dev = connector->dev;
fac5e23e 5363 struct drm_i915_private *dev_priv = to_i915(dev);
4f9db5b5
PB		 5364 struct drm_display_mode *downclock_mode = NULL;
5365
9da7d693
DV		 5366 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5367 mutex_init(&dev_priv->drrs.mutex);
5368
4f9db5b5
PB		 5369 if (INTEL_INFO(dev)->gen <= 6) {
5370 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5371 return NULL;
5372 }
5373
5374 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5375 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5376 return NULL;
5377 }
5378
5379 downclock_mode = intel_find_panel_downclock
5380 (dev, fixed_mode, connector);
5381
5382 if (!downclock_mode) {
a1d26342 5383 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5384 return NULL;
5385 }
5386
96178eeb 5387 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5388
96178eeb 5389 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5390 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5391 return downclock_mode;
5392}
5393
ed92f0b2 5394static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5395 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5396{
5397 struct drm_connector *connector = &intel_connector->base;
5398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5399 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5400 struct drm_device *dev = intel_encoder->base.dev;
fac5e23e 5401 struct drm_i915_private *dev_priv = to_i915(dev);
ed92f0b2 5402 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5403 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5404 bool has_dpcd;
5405 struct drm_display_mode *scan;
5406 struct edid *edid;
6517d273 5407 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5408
5409 if (!is_edp(intel_dp))
5410 return true;
5411
97a824e1
ID		 5412 /*
5413 * On IBX/CPT we may get here with LVDS already registered. Since the
5414 * driver uses the only internal power sequencer available for both
5415 * eDP and LVDS bail out early in this case to prevent interfering
5416 * with an already powered-on LVDS power sequencer.
5417 */
5418 if (intel_get_lvds_encoder(dev)) {
5419 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5420 DRM_INFO("LVDS was detected, not registering eDP\n");
5421
5422 return false;
5423 }
5424
49e6bc51 5425 pps_lock(intel_dp);
b4d06ede
ID		 5426
5427 intel_dp_init_panel_power_timestamps(intel_dp);
5428
5429 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5430 vlv_initial_power_sequencer_setup(intel_dp);
5431 } else {
5432 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5433 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5434 }
5435
49e6bc51 5436 intel_edp_panel_vdd_sanitize(intel_dp);
b4d06ede 5437
49e6bc51 5438 pps_unlock(intel_dp);
63635217 5439
ed92f0b2 5440 /* Cache DPCD and EDID for edp. */
fe5a66f9 5441 has_dpcd = intel_edp_init_dpcd(intel_dp);
ed92f0b2 5442
fe5a66f9 5443 if (!has_dpcd) {
ed92f0b2
PZ		 5444 /* if this fails, presume the device is a ghost */
5445 DRM_INFO("failed to retrieve link info, disabling eDP\n");
b4d06ede 5446 goto out_vdd_off;
ed92f0b2
PZ		 5447 }
5448
060c8778 5449 mutex_lock(&dev->mode_config.mutex);
0b99836f 5450 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5451 if (edid) {
5452 if (drm_add_edid_modes(connector, edid)) {
5453 drm_mode_connector_update_edid_property(connector,
5454 edid);
5455 drm_edid_to_eld(connector, edid);
5456 } else {
5457 kfree(edid);
5458 edid = ERR_PTR(-EINVAL);
5459 }
5460 } else {
5461 edid = ERR_PTR(-ENOENT);
5462 }
5463 intel_connector->edid = edid;
5464
5465 /* prefer fixed mode from EDID if available */
5466 list_for_each_entry(scan, &connector->probed_modes, head) {
5467 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5468 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5469 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5470 intel_connector, fixed_mode);
ed92f0b2
PZ		 5471 break;
5472 }
5473 }
5474
5475 /* fallback to VBT if available for eDP */
5476 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5477 fixed_mode = drm_mode_duplicate(dev,
5478 dev_priv->vbt.lfp_lvds_vbt_mode);
df457245 5479 if (fixed_mode) {
ed92f0b2 5480 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
df457245
VS		 5481 connector->display_info.width_mm = fixed_mode->width_mm;
5482 connector->display_info.height_mm = fixed_mode->height_mm;
5483 }
ed92f0b2 5484 }
060c8778 5485 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5486
666a4537 5487 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
01527b31
CT		 5488 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5489 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5490
5491 /*
5492 * Figure out the current pipe for the initial backlight setup.
5493 * If the current pipe isn't valid, try the PPS pipe, and if that
5494 * fails just assume pipe A.
5495 */
5496 if (IS_CHERRYVIEW(dev))
5497 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5498 else
5499 pipe = PORT_TO_PIPE(intel_dp->DP);
5500
5501 if (pipe != PIPE_A && pipe != PIPE_B)
5502 pipe = intel_dp->pps_pipe;
5503
5504 if (pipe != PIPE_A && pipe != PIPE_B)
5505 pipe = PIPE_A;
5506
5507 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5508 pipe_name(pipe));
01527b31
CT		 5509 }
5510
4f9db5b5 5511 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5507faeb 5512 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6517d273 5513 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5514
5515 return true;
b4d06ede
ID		 5516
5517out_vdd_off:
5518 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5519 /*
5520 * vdd might still be enabled do to the delayed vdd off.
5521 * Make sure vdd is actually turned off here.
5522 */
5523 pps_lock(intel_dp);
5524 edp_panel_vdd_off_sync(intel_dp);
5525 pps_unlock(intel_dp);
5526
5527 return false;
ed92f0b2
PZ		 5528}
5529
16c25533 5530bool
f0fec3f2
PZ		 5531intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5532 struct intel_connector *intel_connector)
a4fc5ed6 5533{
f0fec3f2
PZ		 5534 struct drm_connector *connector = &intel_connector->base;
5535 struct intel_dp *intel_dp = &intel_dig_port->dp;
5536 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5537 struct drm_device *dev = intel_encoder->base.dev;
fac5e23e 5538 struct drm_i915_private *dev_priv = to_i915(dev);
174edf1f 5539 enum port port = intel_dig_port->port;
7a418e34 5540 int type;
a4fc5ed6 5541
ccb1a831
VS		 5542 if (WARN(intel_dig_port->max_lanes < 1,
5543 "Not enough lanes (%d) for DP on port %c\n",
5544 intel_dig_port->max_lanes, port_name(port)))
5545 return false;
5546
a4a5d2f8
VS		 5547 intel_dp->pps_pipe = INVALID_PIPE;
5548
ec5b01dd 5549 /* intel_dp vfuncs */
b6b5e383
DL		 5550 if (INTEL_INFO(dev)->gen >= 9)
5551 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
ec5b01dd
DL		 5552 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5553 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5554 else if (HAS_PCH_SPLIT(dev))
5555 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5556 else
6ffb1be7 5557 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
ec5b01dd 5558
b9ca5fad
DL		 5559 if (INTEL_INFO(dev)->gen >= 9)
5560 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5561 else
6ffb1be7 5562 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
153b1100 5563
ad64217b
ACO		 5564 if (HAS_DDI(dev))
5565 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5566
0767935e
DV		 5567 /* Preserve the current hw state. */
5568 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5569 intel_dp->attached_connector = intel_connector;
3d3dc149 5570
3b32a35b 5571 if (intel_dp_is_edp(dev, port))
b329530c 5572 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5573 else
5574 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5575
f7d24902
ID		 5576 /*
5577 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5578 * for DP the encoder type can be set by the caller to
5579 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5580 */
5581 if (type == DRM_MODE_CONNECTOR_eDP)
5582 intel_encoder->type = INTEL_OUTPUT_EDP;
5583
c17ed5b5 5584 /* eDP only on port B and/or C on vlv/chv */
666a4537
WB		 5585 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5586 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
c17ed5b5
VS		 5587 return false;
5588
e7281eab
ID		 5589 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5590 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5591 port_name(port));
5592
b329530c 5593 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5594 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5595
a4fc5ed6
KP		 5596 connector->interlace_allowed = true;
5597 connector->doublescan_allowed = 0;
5598
7a418e34
CW		 5599 intel_dp_aux_init(intel_dp, intel_connector);
5600
f0fec3f2 5601 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5602 edp_panel_vdd_work);
a4fc5ed6 5603
df0e9248 5604 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6 5605
affa9354 5606 if (HAS_DDI(dev))
bcbc889b
PZ		 5607 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5608 else
5609 intel_connector->get_hw_state = intel_connector_get_hw_state;
5610
0b99836f 5611 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5612 switch (port) {
5613 case PORT_A:
1d843f9d 5614 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5615 break;
5616 case PORT_B:
1d843f9d 5617 intel_encoder->hpd_pin = HPD_PORT_B;
e87a005d 5618 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
cf1d5883 5619 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5620 break;
5621 case PORT_C:
1d843f9d 5622 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5623 break;
5624 case PORT_D:
1d843f9d 5625 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30 5626 break;
26951caf
XZ		 5627 case PORT_E:
5628 intel_encoder->hpd_pin = HPD_PORT_E;
5629 break;
ab9d7c30 5630 default:
ad1c0b19 5631 BUG();
5eb08b69
ZW		 5632 }
5633
0e32b39c 5634 /* init MST on ports that can support it */
f8e58ddf 5635 if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
0c9b3715
JN		 5636 (port == PORT_B || port == PORT_C || port == PORT_D))
5637 intel_dp_mst_encoder_init(intel_dig_port,
5638 intel_connector->base.base.id);
0e32b39c 5639
36b5f425 5640 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
a121f4e5
VS		 5641 intel_dp_aux_fini(intel_dp);
5642 intel_dp_mst_encoder_cleanup(intel_dig_port);
5643 goto fail;
b2f246a8 5644 }
32f9d658 5645
f684960e
CW		 5646 intel_dp_add_properties(intel_dp, connector);
5647
a4fc5ed6
KP		 5648 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5649 * 0xd. Failure to do so will result in spurious interrupts being
5650 * generated on the port when a cable is not attached.
5651 */
5652 if (IS_G4X(dev) && !IS_GM45(dev)) {
5653 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5654 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5655 }
16c25533
PZ		 5656
5657 return true;
a121f4e5
VS		 5658
5659fail:
a121f4e5
VS		 5660 drm_connector_cleanup(connector);
5661
5662 return false;
a4fc5ed6 5663}
f0fec3f2 5664
457c52d8
CW		 5665bool intel_dp_init(struct drm_device *dev,
5666 i915_reg_t output_reg,
5667 enum port port)
f0fec3f2 5668{
fac5e23e 5669 struct drm_i915_private *dev_priv = to_i915(dev);
f0fec3f2
PZ		 5670 struct intel_digital_port *intel_dig_port;
5671 struct intel_encoder *intel_encoder;
5672 struct drm_encoder *encoder;
5673 struct intel_connector *intel_connector;
5674
b14c5679 5675 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2 5676 if (!intel_dig_port)
457c52d8 5677 return false;
f0fec3f2 5678
08d9bc92 5679 intel_connector = intel_connector_alloc();
11aee0f6
SM		 5680 if (!intel_connector)
5681 goto err_connector_alloc;
f0fec3f2
PZ		 5682
5683 intel_encoder = &intel_dig_port->base;
5684 encoder = &intel_encoder->base;
5685
893da0c9 5686 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
580d8ed5 5687 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
893da0c9 5688 goto err_encoder_init;
f0fec3f2 5689
5bfe2ac0 5690 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5691 intel_encoder->disable = intel_disable_dp;
00c09d70 5692 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5693 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5694 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5695 if (IS_CHERRYVIEW(dev)) {
9197c88b 5696 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5697 intel_encoder->pre_enable = chv_pre_enable_dp;
5698 intel_encoder->enable = vlv_enable_dp;
580d3811 5699 intel_encoder->post_disable = chv_post_disable_dp;
d6db995f 5700 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
e4a1d846 5701 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5702 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5703 intel_encoder->pre_enable = vlv_pre_enable_dp;
5704 intel_encoder->enable = vlv_enable_dp;
49277c31 5705 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5706 } else {
ecff4f3b
JN		 5707 intel_encoder->pre_enable = g4x_pre_enable_dp;
5708 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5709 if (INTEL_INFO(dev)->gen >= 5)
5710 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5711 }
f0fec3f2 5712
174edf1f 5713 intel_dig_port->port = port;
f0fec3f2 5714 intel_dig_port->dp.output_reg = output_reg;
ccb1a831 5715 intel_dig_port->max_lanes = 4;
f0fec3f2 5716
cca0502b 5717 intel_encoder->type = INTEL_OUTPUT_DP;
882ec384
VS		 5718 if (IS_CHERRYVIEW(dev)) {
5719 if (port == PORT_D)
5720 intel_encoder->crtc_mask = 1 << 2;
5721 else
5722 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5723 } else {
5724 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5725 }
bc079e8b 5726 intel_encoder->cloneable = 0;
f0fec3f2 5727
13cf5504 5728 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 5729 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 5730
11aee0f6
SM		 5731 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5732 goto err_init_connector;
5733
457c52d8 5734 return true;
11aee0f6
SM		 5735
5736err_init_connector:
5737 drm_encoder_cleanup(encoder);
893da0c9 5738err_encoder_init:
11aee0f6
SM		 5739 kfree(intel_connector);
5740err_connector_alloc:
5741 kfree(intel_dig_port);
457c52d8 5742 return false;
f0fec3f2 5743}
0e32b39c
DA		 5744
5745void intel_dp_mst_suspend(struct drm_device *dev)
5746{
fac5e23e 5747 struct drm_i915_private *dev_priv = to_i915(dev);
0e32b39c
DA		 5748 int i;
5749
5750 /* disable MST */
5751 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5752 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5aa56969
VS		 5753
5754 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
0e32b39c
DA		 5755 continue;
5756
5aa56969
VS		 5757 if (intel_dig_port->dp.is_mst)
5758 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
0e32b39c
DA		 5759 }
5760}
5761
5762void intel_dp_mst_resume(struct drm_device *dev)
5763{
fac5e23e 5764 struct drm_i915_private *dev_priv = to_i915(dev);
0e32b39c
DA		 5765 int i;
5766
5767 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5768 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5aa56969 5769 int ret;
0e32b39c 5770
5aa56969
VS		 5771 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5772 continue;
0e32b39c 5773
5aa56969
VS		 5774 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5775 if (ret)
5776 intel_dp_check_mst_status(&intel_dig_port->dp);
0e32b39c
DA		 5777 }
5778}
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