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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
a4fc5ed6 KP |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "drm_crtc_helper.h" | |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
ab2c0672 | 37 | #include "drm_dp_helper.h" |
a4fc5ed6 | 38 | |
ae266c98 | 39 | |
a4fc5ed6 KP |
40 | #define DP_LINK_STATUS_SIZE 6 |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) | |
42 | ||
43 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
44 | ||
ea5b213a CW |
45 | struct intel_dp { |
46 | struct intel_encoder base; | |
a4fc5ed6 KP |
47 | uint32_t output_reg; |
48 | uint32_t DP; | |
49 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
a4fc5ed6 | 50 | bool has_audio; |
f684960e | 51 | int force_audio; |
e953fd7b | 52 | uint32_t color_range; |
d2b996ac | 53 | int dpms_mode; |
a4fc5ed6 KP |
54 | uint8_t link_bw; |
55 | uint8_t lane_count; | |
9de88e6e | 56 | uint8_t dpcd[8]; |
a4fc5ed6 KP |
57 | struct i2c_adapter adapter; |
58 | struct i2c_algo_dp_aux_data algo; | |
f0917379 | 59 | bool is_pch_edp; |
33a34e4e JB |
60 | uint8_t train_set[4]; |
61 | uint8_t link_status[DP_LINK_STATUS_SIZE]; | |
f01eca2e KP |
62 | int panel_power_up_delay; |
63 | int panel_power_down_delay; | |
64 | int panel_power_cycle_delay; | |
65 | int backlight_on_delay; | |
66 | int backlight_off_delay; | |
a4fc5ed6 KP |
67 | }; |
68 | ||
cfcb0fc9 JB |
69 | /** |
70 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
71 | * @intel_dp: DP struct | |
72 | * | |
73 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
74 | * will return true, and false otherwise. | |
75 | */ | |
76 | static bool is_edp(struct intel_dp *intel_dp) | |
77 | { | |
78 | return intel_dp->base.type == INTEL_OUTPUT_EDP; | |
79 | } | |
80 | ||
81 | /** | |
82 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? | |
83 | * @intel_dp: DP struct | |
84 | * | |
85 | * Returns true if the given DP struct corresponds to a PCH DP port attached | |
86 | * to an eDP panel, false otherwise. Helpful for determining whether we | |
87 | * may need FDI resources for a given DP output or not. | |
88 | */ | |
89 | static bool is_pch_edp(struct intel_dp *intel_dp) | |
90 | { | |
91 | return intel_dp->is_pch_edp; | |
92 | } | |
93 | ||
ea5b213a CW |
94 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
95 | { | |
4ef69c7a | 96 | return container_of(encoder, struct intel_dp, base.base); |
ea5b213a | 97 | } |
a4fc5ed6 | 98 | |
df0e9248 CW |
99 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
100 | { | |
101 | return container_of(intel_attached_encoder(connector), | |
102 | struct intel_dp, base); | |
103 | } | |
104 | ||
814948ad JB |
105 | /** |
106 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? | |
107 | * @encoder: DRM encoder | |
108 | * | |
109 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed | |
110 | * by intel_display.c. | |
111 | */ | |
112 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) | |
113 | { | |
114 | struct intel_dp *intel_dp; | |
115 | ||
116 | if (!encoder) | |
117 | return false; | |
118 | ||
119 | intel_dp = enc_to_intel_dp(encoder); | |
120 | ||
121 | return is_pch_edp(intel_dp); | |
122 | } | |
123 | ||
33a34e4e JB |
124 | static void intel_dp_start_link_train(struct intel_dp *intel_dp); |
125 | static void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
ea5b213a | 126 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
a4fc5ed6 | 127 | |
32f9d658 | 128 | void |
21d40d37 | 129 | intel_edp_link_config (struct intel_encoder *intel_encoder, |
ea5b213a | 130 | int *lane_num, int *link_bw) |
32f9d658 | 131 | { |
ea5b213a | 132 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
32f9d658 | 133 | |
ea5b213a CW |
134 | *lane_num = intel_dp->lane_count; |
135 | if (intel_dp->link_bw == DP_LINK_BW_1_62) | |
32f9d658 | 136 | *link_bw = 162000; |
ea5b213a | 137 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
32f9d658 ZW |
138 | *link_bw = 270000; |
139 | } | |
140 | ||
a4fc5ed6 | 141 | static int |
ea5b213a | 142 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
a4fc5ed6 | 143 | { |
a4fc5ed6 KP |
144 | int max_lane_count = 4; |
145 | ||
7183dc29 JB |
146 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
147 | max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; | |
a4fc5ed6 KP |
148 | switch (max_lane_count) { |
149 | case 1: case 2: case 4: | |
150 | break; | |
151 | default: | |
152 | max_lane_count = 4; | |
153 | } | |
154 | } | |
155 | return max_lane_count; | |
156 | } | |
157 | ||
158 | static int | |
ea5b213a | 159 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 160 | { |
7183dc29 | 161 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
162 | |
163 | switch (max_link_bw) { | |
164 | case DP_LINK_BW_1_62: | |
165 | case DP_LINK_BW_2_7: | |
166 | break; | |
167 | default: | |
168 | max_link_bw = DP_LINK_BW_1_62; | |
169 | break; | |
170 | } | |
171 | return max_link_bw; | |
172 | } | |
173 | ||
174 | static int | |
175 | intel_dp_link_clock(uint8_t link_bw) | |
176 | { | |
177 | if (link_bw == DP_LINK_BW_2_7) | |
178 | return 270000; | |
179 | else | |
180 | return 162000; | |
181 | } | |
182 | ||
183 | /* I think this is a fiction */ | |
184 | static int | |
ea5b213a | 185 | intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) |
a4fc5ed6 | 186 | { |
89c61432 JB |
187 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
188 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
189 | int bpp = 24; | |
885a5fb5 | 190 | |
89c61432 JB |
191 | if (intel_crtc) |
192 | bpp = intel_crtc->bpp; | |
193 | ||
194 | return (pixel_clock * bpp + 7) / 8; | |
a4fc5ed6 KP |
195 | } |
196 | ||
fe27d53e DA |
197 | static int |
198 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
199 | { | |
200 | return (max_link_clock * max_lanes * 8) / 10; | |
201 | } | |
202 | ||
a4fc5ed6 KP |
203 | static int |
204 | intel_dp_mode_valid(struct drm_connector *connector, | |
205 | struct drm_display_mode *mode) | |
206 | { | |
df0e9248 | 207 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
7de56f43 ZY |
208 | struct drm_device *dev = connector->dev; |
209 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a CW |
210 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
211 | int max_lanes = intel_dp_max_lane_count(intel_dp); | |
a4fc5ed6 | 212 | |
4d926461 | 213 | if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { |
7de56f43 ZY |
214 | if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) |
215 | return MODE_PANEL; | |
216 | ||
217 | if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay) | |
218 | return MODE_PANEL; | |
219 | } | |
220 | ||
25985edc | 221 | /* only refuse the mode on non eDP since we have seen some weird eDP panels |
fe27d53e | 222 | which are outside spec tolerances but somehow work by magic */ |
cfcb0fc9 | 223 | if (!is_edp(intel_dp) && |
ea5b213a | 224 | (intel_dp_link_required(connector->dev, intel_dp, mode->clock) |
fe27d53e | 225 | > intel_dp_max_data_rate(max_link_clock, max_lanes))) |
a4fc5ed6 KP |
226 | return MODE_CLOCK_HIGH; |
227 | ||
228 | if (mode->clock < 10000) | |
229 | return MODE_CLOCK_LOW; | |
230 | ||
231 | return MODE_OK; | |
232 | } | |
233 | ||
234 | static uint32_t | |
235 | pack_aux(uint8_t *src, int src_bytes) | |
236 | { | |
237 | int i; | |
238 | uint32_t v = 0; | |
239 | ||
240 | if (src_bytes > 4) | |
241 | src_bytes = 4; | |
242 | for (i = 0; i < src_bytes; i++) | |
243 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
244 | return v; | |
245 | } | |
246 | ||
247 | static void | |
248 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
249 | { | |
250 | int i; | |
251 | if (dst_bytes > 4) | |
252 | dst_bytes = 4; | |
253 | for (i = 0; i < dst_bytes; i++) | |
254 | dst[i] = src >> ((3-i) * 8); | |
255 | } | |
256 | ||
fb0f8fbf KP |
257 | /* hrawclock is 1/4 the FSB frequency */ |
258 | static int | |
259 | intel_hrawclk(struct drm_device *dev) | |
260 | { | |
261 | struct drm_i915_private *dev_priv = dev->dev_private; | |
262 | uint32_t clkcfg; | |
263 | ||
264 | clkcfg = I915_READ(CLKCFG); | |
265 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
266 | case CLKCFG_FSB_400: | |
267 | return 100; | |
268 | case CLKCFG_FSB_533: | |
269 | return 133; | |
270 | case CLKCFG_FSB_667: | |
271 | return 166; | |
272 | case CLKCFG_FSB_800: | |
273 | return 200; | |
274 | case CLKCFG_FSB_1067: | |
275 | return 266; | |
276 | case CLKCFG_FSB_1333: | |
277 | return 333; | |
278 | /* these two are just a guess; one of them might be right */ | |
279 | case CLKCFG_FSB_1600: | |
280 | case CLKCFG_FSB_1600_ALT: | |
281 | return 400; | |
282 | default: | |
283 | return 133; | |
284 | } | |
285 | } | |
286 | ||
9b984dae KP |
287 | static void |
288 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
289 | { | |
290 | struct drm_device *dev = intel_dp->base.base.dev; | |
291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
292 | u32 pp_status, pp_control; | |
293 | if (!is_edp(intel_dp)) | |
294 | return; | |
295 | pp_status = I915_READ(PCH_PP_STATUS); | |
296 | pp_control = I915_READ(PCH_PP_CONTROL); | |
297 | if ((pp_status & PP_ON) == 0 && (pp_control & EDP_FORCE_VDD) == 0) { | |
298 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); | |
299 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
300 | pp_status, | |
301 | I915_READ(PCH_PP_CONTROL)); | |
302 | } | |
303 | } | |
304 | ||
a4fc5ed6 | 305 | static int |
ea5b213a | 306 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
307 | uint8_t *send, int send_bytes, |
308 | uint8_t *recv, int recv_size) | |
309 | { | |
ea5b213a | 310 | uint32_t output_reg = intel_dp->output_reg; |
4ef69c7a | 311 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 KP |
312 | struct drm_i915_private *dev_priv = dev->dev_private; |
313 | uint32_t ch_ctl = output_reg + 0x10; | |
314 | uint32_t ch_data = ch_ctl + 4; | |
315 | int i; | |
316 | int recv_bytes; | |
a4fc5ed6 | 317 | uint32_t status; |
fb0f8fbf | 318 | uint32_t aux_clock_divider; |
e3421a18 | 319 | int try, precharge; |
a4fc5ed6 | 320 | |
9b984dae | 321 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 | 322 | /* The clock divider is based off the hrawclk, |
fb0f8fbf KP |
323 | * and would like to run at 2MHz. So, take the |
324 | * hrawclk value and divide by 2 and use that | |
6176b8f9 JB |
325 | * |
326 | * Note that PCH attached eDP panels should use a 125MHz input | |
327 | * clock divider. | |
a4fc5ed6 | 328 | */ |
cfcb0fc9 | 329 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
e3421a18 ZW |
330 | if (IS_GEN6(dev)) |
331 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ | |
332 | else | |
333 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
334 | } else if (HAS_PCH_SPLIT(dev)) | |
f2b115e6 | 335 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
5eb08b69 ZW |
336 | else |
337 | aux_clock_divider = intel_hrawclk(dev) / 2; | |
338 | ||
e3421a18 ZW |
339 | if (IS_GEN6(dev)) |
340 | precharge = 3; | |
341 | else | |
342 | precharge = 5; | |
343 | ||
11bee43e JB |
344 | /* Try to wait for any previous AUX channel activity */ |
345 | for (try = 0; try < 3; try++) { | |
346 | status = I915_READ(ch_ctl); | |
347 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
348 | break; | |
349 | msleep(1); | |
350 | } | |
351 | ||
352 | if (try == 3) { | |
353 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
354 | I915_READ(ch_ctl)); | |
4f7f7b7e CW |
355 | return -EBUSY; |
356 | } | |
357 | ||
fb0f8fbf KP |
358 | /* Must try at least 3 times according to DP spec */ |
359 | for (try = 0; try < 5; try++) { | |
360 | /* Load the send data into the aux channel data registers */ | |
4f7f7b7e CW |
361 | for (i = 0; i < send_bytes; i += 4) |
362 | I915_WRITE(ch_data + i, | |
363 | pack_aux(send + i, send_bytes - i)); | |
fb0f8fbf KP |
364 | |
365 | /* Send the command and wait for it to complete */ | |
4f7f7b7e CW |
366 | I915_WRITE(ch_ctl, |
367 | DP_AUX_CH_CTL_SEND_BUSY | | |
368 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
369 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
370 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
371 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
372 | DP_AUX_CH_CTL_DONE | | |
373 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
374 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
fb0f8fbf | 375 | for (;;) { |
fb0f8fbf KP |
376 | status = I915_READ(ch_ctl); |
377 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
378 | break; | |
4f7f7b7e | 379 | udelay(100); |
fb0f8fbf KP |
380 | } |
381 | ||
382 | /* Clear done status and any errors */ | |
4f7f7b7e CW |
383 | I915_WRITE(ch_ctl, |
384 | status | | |
385 | DP_AUX_CH_CTL_DONE | | |
386 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
387 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
388 | if (status & DP_AUX_CH_CTL_DONE) | |
a4fc5ed6 KP |
389 | break; |
390 | } | |
391 | ||
a4fc5ed6 | 392 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 393 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
a5b3da54 | 394 | return -EBUSY; |
a4fc5ed6 KP |
395 | } |
396 | ||
397 | /* Check for timeout or receive error. | |
398 | * Timeouts occur when the sink is not connected | |
399 | */ | |
a5b3da54 | 400 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 401 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
a5b3da54 KP |
402 | return -EIO; |
403 | } | |
1ae8c0a5 KP |
404 | |
405 | /* Timeouts occur when the device isn't connected, so they're | |
406 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 407 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 408 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
a5b3da54 | 409 | return -ETIMEDOUT; |
a4fc5ed6 KP |
410 | } |
411 | ||
412 | /* Unload any bytes sent back from the other side */ | |
413 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
414 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
415 | if (recv_bytes > recv_size) |
416 | recv_bytes = recv_size; | |
417 | ||
4f7f7b7e CW |
418 | for (i = 0; i < recv_bytes; i += 4) |
419 | unpack_aux(I915_READ(ch_data + i), | |
420 | recv + i, recv_bytes - i); | |
a4fc5ed6 KP |
421 | |
422 | return recv_bytes; | |
423 | } | |
424 | ||
425 | /* Write data to the aux channel in native mode */ | |
426 | static int | |
ea5b213a | 427 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
428 | uint16_t address, uint8_t *send, int send_bytes) |
429 | { | |
430 | int ret; | |
431 | uint8_t msg[20]; | |
432 | int msg_bytes; | |
433 | uint8_t ack; | |
434 | ||
9b984dae | 435 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
436 | if (send_bytes > 16) |
437 | return -1; | |
438 | msg[0] = AUX_NATIVE_WRITE << 4; | |
439 | msg[1] = address >> 8; | |
eebc863e | 440 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
441 | msg[3] = send_bytes - 1; |
442 | memcpy(&msg[4], send, send_bytes); | |
443 | msg_bytes = send_bytes + 4; | |
444 | for (;;) { | |
ea5b213a | 445 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
446 | if (ret < 0) |
447 | return ret; | |
448 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
449 | break; | |
450 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
451 | udelay(100); | |
452 | else | |
a5b3da54 | 453 | return -EIO; |
a4fc5ed6 KP |
454 | } |
455 | return send_bytes; | |
456 | } | |
457 | ||
458 | /* Write a single byte to the aux channel in native mode */ | |
459 | static int | |
ea5b213a | 460 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
461 | uint16_t address, uint8_t byte) |
462 | { | |
ea5b213a | 463 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
464 | } |
465 | ||
466 | /* read bytes from a native aux channel */ | |
467 | static int | |
ea5b213a | 468 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
469 | uint16_t address, uint8_t *recv, int recv_bytes) |
470 | { | |
471 | uint8_t msg[4]; | |
472 | int msg_bytes; | |
473 | uint8_t reply[20]; | |
474 | int reply_bytes; | |
475 | uint8_t ack; | |
476 | int ret; | |
477 | ||
9b984dae | 478 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
479 | msg[0] = AUX_NATIVE_READ << 4; |
480 | msg[1] = address >> 8; | |
481 | msg[2] = address & 0xff; | |
482 | msg[3] = recv_bytes - 1; | |
483 | ||
484 | msg_bytes = 4; | |
485 | reply_bytes = recv_bytes + 1; | |
486 | ||
487 | for (;;) { | |
ea5b213a | 488 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 489 | reply, reply_bytes); |
a5b3da54 KP |
490 | if (ret == 0) |
491 | return -EPROTO; | |
492 | if (ret < 0) | |
a4fc5ed6 KP |
493 | return ret; |
494 | ack = reply[0]; | |
495 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
496 | memcpy(recv, reply + 1, ret - 1); | |
497 | return ret - 1; | |
498 | } | |
499 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
500 | udelay(100); | |
501 | else | |
a5b3da54 | 502 | return -EIO; |
a4fc5ed6 KP |
503 | } |
504 | } | |
505 | ||
506 | static int | |
ab2c0672 DA |
507 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
508 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 509 | { |
ab2c0672 | 510 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
511 | struct intel_dp *intel_dp = container_of(adapter, |
512 | struct intel_dp, | |
513 | adapter); | |
ab2c0672 DA |
514 | uint16_t address = algo_data->address; |
515 | uint8_t msg[5]; | |
516 | uint8_t reply[2]; | |
8316f337 | 517 | unsigned retry; |
ab2c0672 DA |
518 | int msg_bytes; |
519 | int reply_bytes; | |
520 | int ret; | |
521 | ||
9b984dae | 522 | intel_dp_check_edp(intel_dp); |
ab2c0672 DA |
523 | /* Set up the command byte */ |
524 | if (mode & MODE_I2C_READ) | |
525 | msg[0] = AUX_I2C_READ << 4; | |
526 | else | |
527 | msg[0] = AUX_I2C_WRITE << 4; | |
528 | ||
529 | if (!(mode & MODE_I2C_STOP)) | |
530 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 531 | |
ab2c0672 DA |
532 | msg[1] = address >> 8; |
533 | msg[2] = address; | |
534 | ||
535 | switch (mode) { | |
536 | case MODE_I2C_WRITE: | |
537 | msg[3] = 0; | |
538 | msg[4] = write_byte; | |
539 | msg_bytes = 5; | |
540 | reply_bytes = 1; | |
541 | break; | |
542 | case MODE_I2C_READ: | |
543 | msg[3] = 0; | |
544 | msg_bytes = 4; | |
545 | reply_bytes = 2; | |
546 | break; | |
547 | default: | |
548 | msg_bytes = 3; | |
549 | reply_bytes = 1; | |
550 | break; | |
551 | } | |
552 | ||
8316f337 DF |
553 | for (retry = 0; retry < 5; retry++) { |
554 | ret = intel_dp_aux_ch(intel_dp, | |
555 | msg, msg_bytes, | |
556 | reply, reply_bytes); | |
ab2c0672 | 557 | if (ret < 0) { |
3ff99164 | 558 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
559 | return ret; |
560 | } | |
8316f337 DF |
561 | |
562 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { | |
563 | case AUX_NATIVE_REPLY_ACK: | |
564 | /* I2C-over-AUX Reply field is only valid | |
565 | * when paired with AUX ACK. | |
566 | */ | |
567 | break; | |
568 | case AUX_NATIVE_REPLY_NACK: | |
569 | DRM_DEBUG_KMS("aux_ch native nack\n"); | |
570 | return -EREMOTEIO; | |
571 | case AUX_NATIVE_REPLY_DEFER: | |
572 | udelay(100); | |
573 | continue; | |
574 | default: | |
575 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", | |
576 | reply[0]); | |
577 | return -EREMOTEIO; | |
578 | } | |
579 | ||
ab2c0672 DA |
580 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
581 | case AUX_I2C_REPLY_ACK: | |
582 | if (mode == MODE_I2C_READ) { | |
583 | *read_byte = reply[1]; | |
584 | } | |
585 | return reply_bytes - 1; | |
586 | case AUX_I2C_REPLY_NACK: | |
8316f337 | 587 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
ab2c0672 DA |
588 | return -EREMOTEIO; |
589 | case AUX_I2C_REPLY_DEFER: | |
8316f337 | 590 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
ab2c0672 DA |
591 | udelay(100); |
592 | break; | |
593 | default: | |
8316f337 | 594 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
ab2c0672 DA |
595 | return -EREMOTEIO; |
596 | } | |
597 | } | |
8316f337 DF |
598 | |
599 | DRM_ERROR("too many retries, giving up\n"); | |
600 | return -EREMOTEIO; | |
a4fc5ed6 KP |
601 | } |
602 | ||
0b5c541b KP |
603 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
604 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp); | |
605 | ||
a4fc5ed6 | 606 | static int |
ea5b213a | 607 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 608 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 609 | { |
0b5c541b KP |
610 | int ret; |
611 | ||
d54e9d28 | 612 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
613 | intel_dp->algo.running = false; |
614 | intel_dp->algo.address = 0; | |
615 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
616 | ||
617 | memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); | |
618 | intel_dp->adapter.owner = THIS_MODULE; | |
619 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
620 | strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); | |
621 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; | |
622 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
623 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
624 | ||
0b5c541b KP |
625 | ironlake_edp_panel_vdd_on(intel_dp); |
626 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); | |
627 | ironlake_edp_panel_vdd_off(intel_dp); | |
628 | return ret; | |
a4fc5ed6 KP |
629 | } |
630 | ||
631 | static bool | |
632 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
633 | struct drm_display_mode *adjusted_mode) | |
634 | { | |
0d3a1bee ZY |
635 | struct drm_device *dev = encoder->dev; |
636 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 637 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4fc5ed6 | 638 | int lane_count, clock; |
ea5b213a CW |
639 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
640 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; | |
a4fc5ed6 KP |
641 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
642 | ||
4d926461 | 643 | if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { |
1d8e1c75 CW |
644 | intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); |
645 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, | |
646 | mode, adjusted_mode); | |
0d3a1bee ZY |
647 | /* |
648 | * the mode->clock is used to calculate the Data&Link M/N | |
649 | * of the pipe. For the eDP the fixed clock should be used. | |
650 | */ | |
651 | mode->clock = dev_priv->panel_fixed_mode->clock; | |
652 | } | |
653 | ||
a4fc5ed6 KP |
654 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
655 | for (clock = 0; clock <= max_clock; clock++) { | |
fe27d53e | 656 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
a4fc5ed6 | 657 | |
ea5b213a | 658 | if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) |
885a5fb5 | 659 | <= link_avail) { |
ea5b213a CW |
660 | intel_dp->link_bw = bws[clock]; |
661 | intel_dp->lane_count = lane_count; | |
662 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
28c97730 ZY |
663 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
664 | "count %d clock %d\n", | |
ea5b213a | 665 | intel_dp->link_bw, intel_dp->lane_count, |
a4fc5ed6 KP |
666 | adjusted_mode->clock); |
667 | return true; | |
668 | } | |
669 | } | |
670 | } | |
fe27d53e | 671 | |
3cf2efb1 CW |
672 | if (is_edp(intel_dp)) { |
673 | /* okay we failed just pick the highest */ | |
674 | intel_dp->lane_count = max_lane_count; | |
675 | intel_dp->link_bw = bws[max_clock]; | |
676 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
677 | DRM_DEBUG_KMS("Force picking display port link bw %02x lane " | |
678 | "count %d clock %d\n", | |
679 | intel_dp->link_bw, intel_dp->lane_count, | |
680 | adjusted_mode->clock); | |
681 | ||
682 | return true; | |
683 | } | |
684 | ||
a4fc5ed6 KP |
685 | return false; |
686 | } | |
687 | ||
688 | struct intel_dp_m_n { | |
689 | uint32_t tu; | |
690 | uint32_t gmch_m; | |
691 | uint32_t gmch_n; | |
692 | uint32_t link_m; | |
693 | uint32_t link_n; | |
694 | }; | |
695 | ||
696 | static void | |
697 | intel_reduce_ratio(uint32_t *num, uint32_t *den) | |
698 | { | |
699 | while (*num > 0xffffff || *den > 0xffffff) { | |
700 | *num >>= 1; | |
701 | *den >>= 1; | |
702 | } | |
703 | } | |
704 | ||
705 | static void | |
36e83a18 | 706 | intel_dp_compute_m_n(int bpp, |
a4fc5ed6 KP |
707 | int nlanes, |
708 | int pixel_clock, | |
709 | int link_clock, | |
710 | struct intel_dp_m_n *m_n) | |
711 | { | |
712 | m_n->tu = 64; | |
36e83a18 | 713 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
a4fc5ed6 KP |
714 | m_n->gmch_n = link_clock * nlanes; |
715 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
716 | m_n->link_m = pixel_clock; | |
717 | m_n->link_n = link_clock; | |
718 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
719 | } | |
720 | ||
721 | void | |
722 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
723 | struct drm_display_mode *adjusted_mode) | |
724 | { | |
725 | struct drm_device *dev = crtc->dev; | |
726 | struct drm_mode_config *mode_config = &dev->mode_config; | |
55f78c43 | 727 | struct drm_encoder *encoder; |
a4fc5ed6 KP |
728 | struct drm_i915_private *dev_priv = dev->dev_private; |
729 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
858fa035 | 730 | int lane_count = 4; |
a4fc5ed6 | 731 | struct intel_dp_m_n m_n; |
9db4a9c7 | 732 | int pipe = intel_crtc->pipe; |
a4fc5ed6 KP |
733 | |
734 | /* | |
21d40d37 | 735 | * Find the lane count in the intel_encoder private |
a4fc5ed6 | 736 | */ |
55f78c43 | 737 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
ea5b213a | 738 | struct intel_dp *intel_dp; |
a4fc5ed6 | 739 | |
d8201ab6 | 740 | if (encoder->crtc != crtc) |
a4fc5ed6 KP |
741 | continue; |
742 | ||
ea5b213a CW |
743 | intel_dp = enc_to_intel_dp(encoder); |
744 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
745 | lane_count = intel_dp->lane_count; | |
51190667 JB |
746 | break; |
747 | } else if (is_edp(intel_dp)) { | |
748 | lane_count = dev_priv->edp.lanes; | |
a4fc5ed6 KP |
749 | break; |
750 | } | |
751 | } | |
752 | ||
753 | /* | |
754 | * Compute the GMCH and Link ratios. The '3' here is | |
755 | * the number of bytes_per_pixel post-LUT, which we always | |
756 | * set up for 8-bits of R/G/B, or 3 bytes total. | |
757 | */ | |
858fa035 | 758 | intel_dp_compute_m_n(intel_crtc->bpp, lane_count, |
a4fc5ed6 KP |
759 | mode->clock, adjusted_mode->clock, &m_n); |
760 | ||
c619eed4 | 761 | if (HAS_PCH_SPLIT(dev)) { |
9db4a9c7 JB |
762 | I915_WRITE(TRANSDATA_M1(pipe), |
763 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
764 | m_n.gmch_m); | |
765 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); | |
766 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); | |
767 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); | |
a4fc5ed6 | 768 | } else { |
9db4a9c7 JB |
769 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
770 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
771 | m_n.gmch_m); | |
772 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); | |
773 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); | |
774 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); | |
a4fc5ed6 KP |
775 | } |
776 | } | |
777 | ||
f01eca2e KP |
778 | static void ironlake_edp_pll_on(struct drm_encoder *encoder); |
779 | static void ironlake_edp_pll_off(struct drm_encoder *encoder); | |
780 | ||
a4fc5ed6 KP |
781 | static void |
782 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
783 | struct drm_display_mode *adjusted_mode) | |
784 | { | |
e3421a18 | 785 | struct drm_device *dev = encoder->dev; |
ea5b213a | 786 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4ef69c7a | 787 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
a4fc5ed6 KP |
788 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
789 | ||
f01eca2e KP |
790 | /* Turn on the eDP PLL if needed */ |
791 | if (is_edp(intel_dp)) { | |
792 | if (!is_pch_edp(intel_dp)) | |
793 | ironlake_edp_pll_on(encoder); | |
794 | else | |
795 | ironlake_edp_pll_off(encoder); | |
796 | } | |
797 | ||
e953fd7b CW |
798 | intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
799 | intel_dp->DP |= intel_dp->color_range; | |
9c9e7927 AJ |
800 | |
801 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
ea5b213a | 802 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
9c9e7927 | 803 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
ea5b213a | 804 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
a4fc5ed6 | 805 | |
cfcb0fc9 | 806 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
ea5b213a | 807 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3421a18 | 808 | else |
ea5b213a | 809 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
a4fc5ed6 | 810 | |
ea5b213a | 811 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 812 | case 1: |
ea5b213a | 813 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
814 | break; |
815 | case 2: | |
ea5b213a | 816 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
817 | break; |
818 | case 4: | |
ea5b213a | 819 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
820 | break; |
821 | } | |
ea5b213a CW |
822 | if (intel_dp->has_audio) |
823 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; | |
a4fc5ed6 | 824 | |
ea5b213a CW |
825 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
826 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
827 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
a2cab1b2 | 828 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
a4fc5ed6 KP |
829 | |
830 | /* | |
9962c925 | 831 | * Check for DPCD version > 1.1 and enhanced framing support |
a4fc5ed6 | 832 | */ |
7183dc29 JB |
833 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
834 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { | |
ea5b213a CW |
835 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
836 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
a4fc5ed6 KP |
837 | } |
838 | ||
e3421a18 ZW |
839 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ |
840 | if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) | |
ea5b213a | 841 | intel_dp->DP |= DP_PIPEB_SELECT; |
32f9d658 | 842 | |
895692be | 843 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
32f9d658 | 844 | /* don't miss out required setting for eDP */ |
ea5b213a | 845 | intel_dp->DP |= DP_PLL_ENABLE; |
32f9d658 | 846 | if (adjusted_mode->clock < 200000) |
ea5b213a | 847 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
32f9d658 | 848 | else |
ea5b213a | 849 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
32f9d658 | 850 | } |
a4fc5ed6 KP |
851 | } |
852 | ||
5d613501 JB |
853 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
854 | { | |
855 | struct drm_device *dev = intel_dp->base.base.dev; | |
856 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f01eca2e | 857 | u32 pp, pp_status; |
5d613501 | 858 | |
97af61f5 KP |
859 | if (!is_edp(intel_dp)) |
860 | return; | |
f01eca2e | 861 | DRM_DEBUG_KMS("Turn eDP VDD on\n"); |
5d613501 JB |
862 | /* |
863 | * If the panel wasn't on, make sure there's not a currently | |
864 | * active PP sequence before enabling AUX VDD. | |
865 | */ | |
f01eca2e | 866 | pp_status = I915_READ(PCH_PP_STATUS); |
5d613501 JB |
867 | |
868 | pp = I915_READ(PCH_PP_CONTROL); | |
1c0ae80a KP |
869 | pp &= ~PANEL_UNLOCK_MASK; |
870 | pp |= PANEL_UNLOCK_REGS; | |
5d613501 JB |
871 | pp |= EDP_FORCE_VDD; |
872 | I915_WRITE(PCH_PP_CONTROL, pp); | |
873 | POSTING_READ(PCH_PP_CONTROL); | |
f01eca2e KP |
874 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
875 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); | |
876 | if (!(pp_status & PP_ON)) { | |
877 | msleep(intel_dp->panel_power_up_delay); | |
878 | DRM_DEBUG_KMS("eDP VDD was not on\n"); | |
879 | } | |
5d613501 JB |
880 | } |
881 | ||
882 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp) | |
883 | { | |
884 | struct drm_device *dev = intel_dp->base.base.dev; | |
885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
886 | u32 pp; | |
887 | ||
97af61f5 KP |
888 | if (!is_edp(intel_dp)) |
889 | return; | |
f01eca2e | 890 | DRM_DEBUG_KMS("Turn eDP VDD off\n"); |
5d613501 | 891 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
892 | pp &= ~PANEL_UNLOCK_MASK; |
893 | pp |= PANEL_UNLOCK_REGS; | |
5d613501 JB |
894 | pp &= ~EDP_FORCE_VDD; |
895 | I915_WRITE(PCH_PP_CONTROL, pp); | |
896 | POSTING_READ(PCH_PP_CONTROL); | |
897 | ||
898 | /* Make sure sequencer is idle before allowing subsequent activity */ | |
f01eca2e KP |
899 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
900 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); | |
901 | msleep(intel_dp->panel_power_cycle_delay); | |
5d613501 JB |
902 | } |
903 | ||
7eaf5547 | 904 | /* Returns true if the panel was already on when called */ |
01cb9ea6 | 905 | static bool ironlake_edp_panel_on (struct intel_dp *intel_dp) |
9934c132 | 906 | { |
01cb9ea6 | 907 | struct drm_device *dev = intel_dp->base.base.dev; |
9934c132 | 908 | struct drm_i915_private *dev_priv = dev->dev_private; |
01cb9ea6 | 909 | u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE; |
9934c132 | 910 | |
97af61f5 | 911 | if (!is_edp(intel_dp)) |
f01eca2e | 912 | return true; |
913d8d11 | 913 | if (I915_READ(PCH_PP_STATUS) & PP_ON) |
7eaf5547 | 914 | return true; |
9934c132 JB |
915 | |
916 | pp = I915_READ(PCH_PP_CONTROL); | |
1c0ae80a KP |
917 | pp &= ~PANEL_UNLOCK_MASK; |
918 | pp |= PANEL_UNLOCK_REGS; | |
37c6c9b0 JB |
919 | |
920 | /* ILK workaround: disable reset around power sequence */ | |
921 | pp &= ~PANEL_POWER_RESET; | |
922 | I915_WRITE(PCH_PP_CONTROL, pp); | |
923 | POSTING_READ(PCH_PP_CONTROL); | |
924 | ||
1c0ae80a | 925 | pp |= POWER_TARGET_ON; |
9934c132 | 926 | I915_WRITE(PCH_PP_CONTROL, pp); |
01cb9ea6 | 927 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 | 928 | |
01cb9ea6 JB |
929 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, |
930 | 5000)) | |
913d8d11 CW |
931 | DRM_ERROR("panel on wait timed out: 0x%08x\n", |
932 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 933 | |
37c6c9b0 | 934 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 935 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 936 | POSTING_READ(PCH_PP_CONTROL); |
7eaf5547 JB |
937 | |
938 | return false; | |
9934c132 JB |
939 | } |
940 | ||
f01eca2e | 941 | static void ironlake_edp_panel_off(struct drm_encoder *encoder) |
9934c132 | 942 | { |
f01eca2e KP |
943 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
944 | struct drm_device *dev = encoder->dev; | |
9934c132 | 945 | struct drm_i915_private *dev_priv = dev->dev_private; |
01cb9ea6 JB |
946 | u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | |
947 | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK; | |
9934c132 | 948 | |
97af61f5 KP |
949 | if (!is_edp(intel_dp)) |
950 | return; | |
9934c132 | 951 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
952 | pp &= ~PANEL_UNLOCK_MASK; |
953 | pp |= PANEL_UNLOCK_REGS; | |
37c6c9b0 JB |
954 | |
955 | /* ILK workaround: disable reset around power sequence */ | |
956 | pp &= ~PANEL_POWER_RESET; | |
957 | I915_WRITE(PCH_PP_CONTROL, pp); | |
958 | POSTING_READ(PCH_PP_CONTROL); | |
959 | ||
9934c132 JB |
960 | pp &= ~POWER_TARGET_ON; |
961 | I915_WRITE(PCH_PP_CONTROL, pp); | |
01cb9ea6 | 962 | POSTING_READ(PCH_PP_CONTROL); |
f01eca2e | 963 | msleep(intel_dp->panel_power_cycle_delay); |
9934c132 | 964 | |
01cb9ea6 | 965 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000)) |
913d8d11 CW |
966 | DRM_ERROR("panel off wait timed out: 0x%08x\n", |
967 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 968 | |
3969c9c9 | 969 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 970 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 971 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 JB |
972 | } |
973 | ||
f01eca2e | 974 | static void ironlake_edp_backlight_on (struct intel_dp *intel_dp) |
32f9d658 | 975 | { |
f01eca2e | 976 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
977 | struct drm_i915_private *dev_priv = dev->dev_private; |
978 | u32 pp; | |
979 | ||
f01eca2e KP |
980 | if (!is_edp(intel_dp)) |
981 | return; | |
982 | ||
28c97730 | 983 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
984 | /* |
985 | * If we enable the backlight right away following a panel power | |
986 | * on, we may see slight flicker as the panel syncs with the eDP | |
987 | * link. So delay a bit to make sure the image is solid before | |
988 | * allowing it to appear. | |
989 | */ | |
f01eca2e | 990 | msleep(intel_dp->backlight_on_delay); |
32f9d658 | 991 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
992 | pp &= ~PANEL_UNLOCK_MASK; |
993 | pp |= PANEL_UNLOCK_REGS; | |
32f9d658 ZW |
994 | pp |= EDP_BLC_ENABLE; |
995 | I915_WRITE(PCH_PP_CONTROL, pp); | |
f01eca2e | 996 | POSTING_READ(PCH_PP_CONTROL); |
32f9d658 ZW |
997 | } |
998 | ||
f01eca2e | 999 | static void ironlake_edp_backlight_off (struct intel_dp *intel_dp) |
32f9d658 | 1000 | { |
f01eca2e | 1001 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1002 | struct drm_i915_private *dev_priv = dev->dev_private; |
1003 | u32 pp; | |
1004 | ||
f01eca2e KP |
1005 | if (!is_edp(intel_dp)) |
1006 | return; | |
1007 | ||
28c97730 | 1008 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1009 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
1010 | pp &= ~PANEL_UNLOCK_MASK; |
1011 | pp |= PANEL_UNLOCK_REGS; | |
32f9d658 ZW |
1012 | pp &= ~EDP_BLC_ENABLE; |
1013 | I915_WRITE(PCH_PP_CONTROL, pp); | |
f01eca2e KP |
1014 | POSTING_READ(PCH_PP_CONTROL); |
1015 | msleep(intel_dp->backlight_off_delay); | |
32f9d658 | 1016 | } |
a4fc5ed6 | 1017 | |
d240f20f JB |
1018 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
1019 | { | |
1020 | struct drm_device *dev = encoder->dev; | |
1021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1022 | u32 dpa_ctl; | |
1023 | ||
1024 | DRM_DEBUG_KMS("\n"); | |
1025 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 1026 | dpa_ctl |= DP_PLL_ENABLE; |
d240f20f | 1027 | I915_WRITE(DP_A, dpa_ctl); |
298b0b39 JB |
1028 | POSTING_READ(DP_A); |
1029 | udelay(200); | |
d240f20f JB |
1030 | } |
1031 | ||
1032 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) | |
1033 | { | |
1034 | struct drm_device *dev = encoder->dev; | |
1035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1036 | u32 dpa_ctl; | |
1037 | ||
1038 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 1039 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 1040 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 1041 | POSTING_READ(DP_A); |
d240f20f JB |
1042 | udelay(200); |
1043 | } | |
1044 | ||
c7ad3810 JB |
1045 | /* If the sink supports it, try to set the power state appropriately */ |
1046 | static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) | |
1047 | { | |
1048 | int ret, i; | |
1049 | ||
1050 | /* Should have a valid DPCD by this point */ | |
1051 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
1052 | return; | |
1053 | ||
1054 | if (mode != DRM_MODE_DPMS_ON) { | |
1055 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, | |
1056 | DP_SET_POWER_D3); | |
1057 | if (ret != 1) | |
1058 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
1059 | } else { | |
1060 | /* | |
1061 | * When turning on, we need to retry for 1ms to give the sink | |
1062 | * time to wake up. | |
1063 | */ | |
1064 | for (i = 0; i < 3; i++) { | |
1065 | ret = intel_dp_aux_native_write_1(intel_dp, | |
1066 | DP_SET_POWER, | |
1067 | DP_SET_POWER_D0); | |
1068 | if (ret == 1) | |
1069 | break; | |
1070 | msleep(1); | |
1071 | } | |
1072 | } | |
1073 | } | |
1074 | ||
d240f20f JB |
1075 | static void intel_dp_prepare(struct drm_encoder *encoder) |
1076 | { | |
1077 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
d240f20f | 1078 | |
c7ad3810 | 1079 | /* Wake up the sink first */ |
f58ff854 | 1080 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1081 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
f58ff854 | 1082 | ironlake_edp_panel_vdd_off(intel_dp); |
c7ad3810 | 1083 | |
f01eca2e KP |
1084 | /* Make sure the panel is off before trying to |
1085 | * change the mode | |
1086 | */ | |
1087 | ironlake_edp_backlight_off(intel_dp); | |
736085bc | 1088 | intel_dp_link_down(intel_dp); |
f01eca2e | 1089 | ironlake_edp_panel_off(encoder); |
d240f20f JB |
1090 | } |
1091 | ||
1092 | static void intel_dp_commit(struct drm_encoder *encoder) | |
1093 | { | |
1094 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
d240f20f | 1095 | |
97af61f5 | 1096 | ironlake_edp_panel_vdd_on(intel_dp); |
f01eca2e | 1097 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 1098 | intel_dp_start_link_train(intel_dp); |
97af61f5 KP |
1099 | ironlake_edp_panel_on(intel_dp); |
1100 | ironlake_edp_panel_vdd_off(intel_dp); | |
33a34e4e | 1101 | intel_dp_complete_link_train(intel_dp); |
f01eca2e | 1102 | ironlake_edp_backlight_on(intel_dp); |
d2b996ac KP |
1103 | |
1104 | intel_dp->dpms_mode = DRM_MODE_DPMS_ON; | |
d240f20f JB |
1105 | } |
1106 | ||
a4fc5ed6 KP |
1107 | static void |
1108 | intel_dp_dpms(struct drm_encoder *encoder, int mode) | |
1109 | { | |
ea5b213a | 1110 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
55f78c43 | 1111 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 | 1112 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1113 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
a4fc5ed6 KP |
1114 | |
1115 | if (mode != DRM_MODE_DPMS_ON) { | |
245e2708 | 1116 | ironlake_edp_panel_vdd_on(intel_dp); |
01cb9ea6 | 1117 | if (is_edp(intel_dp)) |
f01eca2e | 1118 | ironlake_edp_backlight_off(intel_dp); |
c7ad3810 | 1119 | intel_dp_sink_dpms(intel_dp, mode); |
736085bc | 1120 | intel_dp_link_down(intel_dp); |
f01eca2e | 1121 | ironlake_edp_panel_off(encoder); |
01cb9ea6 | 1122 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) |
d240f20f | 1123 | ironlake_edp_pll_off(encoder); |
245e2708 | 1124 | ironlake_edp_panel_vdd_off(intel_dp); |
a4fc5ed6 | 1125 | } else { |
97af61f5 | 1126 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1127 | intel_dp_sink_dpms(intel_dp, mode); |
32f9d658 | 1128 | if (!(dp_reg & DP_PORT_EN)) { |
01cb9ea6 | 1129 | intel_dp_start_link_train(intel_dp); |
97af61f5 KP |
1130 | ironlake_edp_panel_on(intel_dp); |
1131 | ironlake_edp_panel_vdd_off(intel_dp); | |
33a34e4e | 1132 | intel_dp_complete_link_train(intel_dp); |
f01eca2e | 1133 | ironlake_edp_backlight_on(intel_dp); |
bee7eb2d KP |
1134 | } else |
1135 | ironlake_edp_panel_vdd_off(intel_dp); | |
a4fc5ed6 | 1136 | } |
d2b996ac | 1137 | intel_dp->dpms_mode = mode; |
a4fc5ed6 KP |
1138 | } |
1139 | ||
1140 | /* | |
df0c237d JB |
1141 | * Native read with retry for link status and receiver capability reads for |
1142 | * cases where the sink may still be asleep. | |
a4fc5ed6 KP |
1143 | */ |
1144 | static bool | |
df0c237d JB |
1145 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
1146 | uint8_t *recv, int recv_bytes) | |
a4fc5ed6 | 1147 | { |
61da5fab JB |
1148 | int ret, i; |
1149 | ||
df0c237d JB |
1150 | /* |
1151 | * Sinks are *supposed* to come up within 1ms from an off state, | |
1152 | * but we're also supposed to retry 3 times per the spec. | |
1153 | */ | |
61da5fab | 1154 | for (i = 0; i < 3; i++) { |
df0c237d JB |
1155 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
1156 | recv_bytes); | |
1157 | if (ret == recv_bytes) | |
61da5fab JB |
1158 | return true; |
1159 | msleep(1); | |
1160 | } | |
a4fc5ed6 | 1161 | |
61da5fab | 1162 | return false; |
a4fc5ed6 KP |
1163 | } |
1164 | ||
1165 | /* | |
1166 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
1167 | * link status information | |
1168 | */ | |
1169 | static bool | |
33a34e4e | 1170 | intel_dp_get_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1171 | { |
df0c237d JB |
1172 | return intel_dp_aux_native_read_retry(intel_dp, |
1173 | DP_LANE0_1_STATUS, | |
1174 | intel_dp->link_status, | |
1175 | DP_LINK_STATUS_SIZE); | |
a4fc5ed6 KP |
1176 | } |
1177 | ||
1178 | static uint8_t | |
1179 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1180 | int r) | |
1181 | { | |
1182 | return link_status[r - DP_LANE0_1_STATUS]; | |
1183 | } | |
1184 | ||
a4fc5ed6 KP |
1185 | static uint8_t |
1186 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1187 | int lane) | |
1188 | { | |
1189 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
1190 | int s = ((lane & 1) ? | |
1191 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
1192 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
1193 | uint8_t l = intel_dp_link_status(link_status, i); | |
1194 | ||
1195 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
1196 | } | |
1197 | ||
1198 | static uint8_t | |
1199 | intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1200 | int lane) | |
1201 | { | |
1202 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
1203 | int s = ((lane & 1) ? | |
1204 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
1205 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
1206 | uint8_t l = intel_dp_link_status(link_status, i); | |
1207 | ||
1208 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
1209 | } | |
1210 | ||
1211 | ||
1212 | #if 0 | |
1213 | static char *voltage_names[] = { | |
1214 | "0.4V", "0.6V", "0.8V", "1.2V" | |
1215 | }; | |
1216 | static char *pre_emph_names[] = { | |
1217 | "0dB", "3.5dB", "6dB", "9.5dB" | |
1218 | }; | |
1219 | static char *link_train_names[] = { | |
1220 | "pattern 1", "pattern 2", "idle", "off" | |
1221 | }; | |
1222 | #endif | |
1223 | ||
1224 | /* | |
1225 | * These are source-specific values; current Intel hardware supports | |
1226 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1227 | */ | |
1228 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 | |
1229 | ||
1230 | static uint8_t | |
1231 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) | |
1232 | { | |
1233 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1234 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1235 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1236 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1237 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1238 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1239 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1240 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1241 | default: | |
1242 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1243 | } | |
1244 | } | |
1245 | ||
1246 | static void | |
33a34e4e | 1247 | intel_get_adjust_train(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1248 | { |
1249 | uint8_t v = 0; | |
1250 | uint8_t p = 0; | |
1251 | int lane; | |
1252 | ||
33a34e4e JB |
1253 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1254 | uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane); | |
1255 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1256 | |
1257 | if (this_v > v) | |
1258 | v = this_v; | |
1259 | if (this_p > p) | |
1260 | p = this_p; | |
1261 | } | |
1262 | ||
1263 | if (v >= I830_DP_VOLTAGE_MAX) | |
1264 | v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; | |
1265 | ||
1266 | if (p >= intel_dp_pre_emphasis_max(v)) | |
1267 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
1268 | ||
1269 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 1270 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
1271 | } |
1272 | ||
1273 | static uint32_t | |
3cf2efb1 | 1274 | intel_dp_signal_levels(uint8_t train_set, int lane_count) |
a4fc5ed6 | 1275 | { |
3cf2efb1 | 1276 | uint32_t signal_levels = 0; |
a4fc5ed6 | 1277 | |
3cf2efb1 | 1278 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
1279 | case DP_TRAIN_VOLTAGE_SWING_400: |
1280 | default: | |
1281 | signal_levels |= DP_VOLTAGE_0_4; | |
1282 | break; | |
1283 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1284 | signal_levels |= DP_VOLTAGE_0_6; | |
1285 | break; | |
1286 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1287 | signal_levels |= DP_VOLTAGE_0_8; | |
1288 | break; | |
1289 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1290 | signal_levels |= DP_VOLTAGE_1_2; | |
1291 | break; | |
1292 | } | |
3cf2efb1 | 1293 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
1294 | case DP_TRAIN_PRE_EMPHASIS_0: |
1295 | default: | |
1296 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1297 | break; | |
1298 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1299 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1300 | break; | |
1301 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1302 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1303 | break; | |
1304 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1305 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1306 | break; | |
1307 | } | |
1308 | return signal_levels; | |
1309 | } | |
1310 | ||
e3421a18 ZW |
1311 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1312 | static uint32_t | |
1313 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1314 | { | |
3c5a62b5 YL |
1315 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1316 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1317 | switch (signal_levels) { | |
e3421a18 | 1318 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1319 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
1320 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
1321 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1322 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 1323 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
1324 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
1325 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 1326 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
1327 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
1328 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 1329 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1330 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
1331 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 1332 | default: |
3c5a62b5 YL |
1333 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
1334 | "0x%x\n", signal_levels); | |
1335 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
1336 | } |
1337 | } | |
1338 | ||
a4fc5ed6 KP |
1339 | static uint8_t |
1340 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1341 | int lane) | |
1342 | { | |
1343 | int i = DP_LANE0_1_STATUS + (lane >> 1); | |
1344 | int s = (lane & 1) * 4; | |
1345 | uint8_t l = intel_dp_link_status(link_status, i); | |
1346 | ||
1347 | return (l >> s) & 0xf; | |
1348 | } | |
1349 | ||
1350 | /* Check for clock recovery is done on all channels */ | |
1351 | static bool | |
1352 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1353 | { | |
1354 | int lane; | |
1355 | uint8_t lane_status; | |
1356 | ||
1357 | for (lane = 0; lane < lane_count; lane++) { | |
1358 | lane_status = intel_get_lane_status(link_status, lane); | |
1359 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
1360 | return false; | |
1361 | } | |
1362 | return true; | |
1363 | } | |
1364 | ||
1365 | /* Check to see if channel eq is done on all channels */ | |
1366 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ | |
1367 | DP_LANE_CHANNEL_EQ_DONE|\ | |
1368 | DP_LANE_SYMBOL_LOCKED) | |
1369 | static bool | |
33a34e4e | 1370 | intel_channel_eq_ok(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1371 | { |
1372 | uint8_t lane_align; | |
1373 | uint8_t lane_status; | |
1374 | int lane; | |
1375 | ||
33a34e4e | 1376 | lane_align = intel_dp_link_status(intel_dp->link_status, |
a4fc5ed6 KP |
1377 | DP_LANE_ALIGN_STATUS_UPDATED); |
1378 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
1379 | return false; | |
33a34e4e JB |
1380 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1381 | lane_status = intel_get_lane_status(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1382 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
1383 | return false; | |
1384 | } | |
1385 | return true; | |
1386 | } | |
1387 | ||
1388 | static bool | |
ea5b213a | 1389 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 | 1390 | uint32_t dp_reg_value, |
58e10eb9 | 1391 | uint8_t dp_train_pat) |
a4fc5ed6 | 1392 | { |
4ef69c7a | 1393 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1394 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1395 | int ret; |
1396 | ||
ea5b213a CW |
1397 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1398 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1399 | |
ea5b213a | 1400 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1401 | DP_TRAINING_PATTERN_SET, |
1402 | dp_train_pat); | |
1403 | ||
ea5b213a | 1404 | ret = intel_dp_aux_native_write(intel_dp, |
58e10eb9 CW |
1405 | DP_TRAINING_LANE0_SET, |
1406 | intel_dp->train_set, 4); | |
a4fc5ed6 KP |
1407 | if (ret != 4) |
1408 | return false; | |
1409 | ||
1410 | return true; | |
1411 | } | |
1412 | ||
33a34e4e | 1413 | /* Enable corresponding port and start training pattern 1 */ |
a4fc5ed6 | 1414 | static void |
33a34e4e | 1415 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1416 | { |
4ef69c7a | 1417 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1418 | struct drm_i915_private *dev_priv = dev->dev_private; |
58e10eb9 | 1419 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); |
a4fc5ed6 KP |
1420 | int i; |
1421 | uint8_t voltage; | |
1422 | bool clock_recovery = false; | |
a4fc5ed6 | 1423 | int tries; |
e3421a18 | 1424 | u32 reg; |
ea5b213a | 1425 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1426 | |
e8519464 AJ |
1427 | /* |
1428 | * On CPT we have to enable the port in training pattern 1, which | |
1429 | * will happen below in intel_dp_set_link_train. Otherwise, enable | |
1430 | * the port and wait for it to become active. | |
1431 | */ | |
1432 | if (!HAS_PCH_CPT(dev)) { | |
1433 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
1434 | POSTING_READ(intel_dp->output_reg); | |
1435 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1436 | } | |
a4fc5ed6 | 1437 | |
3cf2efb1 CW |
1438 | /* Write the link configuration data */ |
1439 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, | |
1440 | intel_dp->link_configuration, | |
1441 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
1442 | |
1443 | DP |= DP_PORT_EN; | |
cfcb0fc9 | 1444 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1445 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1446 | else | |
1447 | DP &= ~DP_LINK_TRAIN_MASK; | |
33a34e4e | 1448 | memset(intel_dp->train_set, 0, 4); |
a4fc5ed6 KP |
1449 | voltage = 0xff; |
1450 | tries = 0; | |
1451 | clock_recovery = false; | |
1452 | for (;;) { | |
33a34e4e | 1453 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 | 1454 | uint32_t signal_levels; |
cfcb0fc9 | 1455 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
33a34e4e | 1456 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1457 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1458 | } else { | |
3cf2efb1 | 1459 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1460 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1461 | } | |
a4fc5ed6 | 1462 | |
cfcb0fc9 | 1463 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1464 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
1465 | else | |
1466 | reg = DP | DP_LINK_TRAIN_PAT_1; | |
1467 | ||
ea5b213a | 1468 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1469 | DP_TRAINING_PATTERN_1 | |
1470 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 | 1471 | break; |
a4fc5ed6 KP |
1472 | /* Set training pattern 1 */ |
1473 | ||
3cf2efb1 CW |
1474 | udelay(100); |
1475 | if (!intel_dp_get_link_status(intel_dp)) | |
a4fc5ed6 | 1476 | break; |
a4fc5ed6 | 1477 | |
3cf2efb1 CW |
1478 | if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { |
1479 | clock_recovery = true; | |
1480 | break; | |
1481 | } | |
1482 | ||
1483 | /* Check to see if we've tried the max voltage */ | |
1484 | for (i = 0; i < intel_dp->lane_count; i++) | |
1485 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 1486 | break; |
3cf2efb1 CW |
1487 | if (i == intel_dp->lane_count) |
1488 | break; | |
a4fc5ed6 | 1489 | |
3cf2efb1 CW |
1490 | /* Check to see if we've tried the same voltage 5 times */ |
1491 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { | |
1492 | ++tries; | |
1493 | if (tries == 5) | |
a4fc5ed6 | 1494 | break; |
3cf2efb1 CW |
1495 | } else |
1496 | tries = 0; | |
1497 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 1498 | |
3cf2efb1 CW |
1499 | /* Compute new intel_dp->train_set as requested by target */ |
1500 | intel_get_adjust_train(intel_dp); | |
a4fc5ed6 KP |
1501 | } |
1502 | ||
33a34e4e JB |
1503 | intel_dp->DP = DP; |
1504 | } | |
1505 | ||
1506 | static void | |
1507 | intel_dp_complete_link_train(struct intel_dp *intel_dp) | |
1508 | { | |
4ef69c7a | 1509 | struct drm_device *dev = intel_dp->base.base.dev; |
33a34e4e JB |
1510 | struct drm_i915_private *dev_priv = dev->dev_private; |
1511 | bool channel_eq = false; | |
37f80975 | 1512 | int tries, cr_tries; |
33a34e4e JB |
1513 | u32 reg; |
1514 | uint32_t DP = intel_dp->DP; | |
1515 | ||
a4fc5ed6 KP |
1516 | /* channel equalization */ |
1517 | tries = 0; | |
37f80975 | 1518 | cr_tries = 0; |
a4fc5ed6 KP |
1519 | channel_eq = false; |
1520 | for (;;) { | |
33a34e4e | 1521 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 ZW |
1522 | uint32_t signal_levels; |
1523 | ||
37f80975 JB |
1524 | if (cr_tries > 5) { |
1525 | DRM_ERROR("failed to train DP, aborting\n"); | |
1526 | intel_dp_link_down(intel_dp); | |
1527 | break; | |
1528 | } | |
1529 | ||
cfcb0fc9 | 1530 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
33a34e4e | 1531 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1532 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1533 | } else { | |
3cf2efb1 | 1534 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1535 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1536 | } | |
1537 | ||
cfcb0fc9 | 1538 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1539 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
1540 | else | |
1541 | reg = DP | DP_LINK_TRAIN_PAT_2; | |
a4fc5ed6 KP |
1542 | |
1543 | /* channel eq pattern */ | |
ea5b213a | 1544 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1545 | DP_TRAINING_PATTERN_2 | |
1546 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 KP |
1547 | break; |
1548 | ||
3cf2efb1 CW |
1549 | udelay(400); |
1550 | if (!intel_dp_get_link_status(intel_dp)) | |
a4fc5ed6 | 1551 | break; |
a4fc5ed6 | 1552 | |
37f80975 JB |
1553 | /* Make sure clock is still ok */ |
1554 | if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { | |
1555 | intel_dp_start_link_train(intel_dp); | |
1556 | cr_tries++; | |
1557 | continue; | |
1558 | } | |
1559 | ||
3cf2efb1 CW |
1560 | if (intel_channel_eq_ok(intel_dp)) { |
1561 | channel_eq = true; | |
1562 | break; | |
1563 | } | |
a4fc5ed6 | 1564 | |
37f80975 JB |
1565 | /* Try 5 times, then try clock recovery if that fails */ |
1566 | if (tries > 5) { | |
1567 | intel_dp_link_down(intel_dp); | |
1568 | intel_dp_start_link_train(intel_dp); | |
1569 | tries = 0; | |
1570 | cr_tries++; | |
1571 | continue; | |
1572 | } | |
a4fc5ed6 | 1573 | |
3cf2efb1 CW |
1574 | /* Compute new intel_dp->train_set as requested by target */ |
1575 | intel_get_adjust_train(intel_dp); | |
1576 | ++tries; | |
869184a6 | 1577 | } |
3cf2efb1 | 1578 | |
cfcb0fc9 | 1579 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1580 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
1581 | else | |
1582 | reg = DP | DP_LINK_TRAIN_OFF; | |
1583 | ||
ea5b213a CW |
1584 | I915_WRITE(intel_dp->output_reg, reg); |
1585 | POSTING_READ(intel_dp->output_reg); | |
1586 | intel_dp_aux_native_write_1(intel_dp, | |
a4fc5ed6 KP |
1587 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
1588 | } | |
1589 | ||
1590 | static void | |
ea5b213a | 1591 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 1592 | { |
4ef69c7a | 1593 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1594 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1595 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1596 | |
1b39d6f3 CW |
1597 | if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) |
1598 | return; | |
1599 | ||
28c97730 | 1600 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1601 | |
cfcb0fc9 | 1602 | if (is_edp(intel_dp)) { |
32f9d658 | 1603 | DP &= ~DP_PLL_ENABLE; |
ea5b213a CW |
1604 | I915_WRITE(intel_dp->output_reg, DP); |
1605 | POSTING_READ(intel_dp->output_reg); | |
32f9d658 ZW |
1606 | udelay(100); |
1607 | } | |
1608 | ||
cfcb0fc9 | 1609 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) { |
e3421a18 | 1610 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 1611 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
1612 | } else { |
1613 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 1614 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 1615 | } |
fe255d00 | 1616 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 1617 | |
fe255d00 | 1618 | msleep(17); |
5eb08b69 | 1619 | |
cfcb0fc9 | 1620 | if (is_edp(intel_dp)) |
32f9d658 | 1621 | DP |= DP_LINK_TRAIN_OFF; |
5bddd17f | 1622 | |
1b39d6f3 CW |
1623 | if (!HAS_PCH_CPT(dev) && |
1624 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { | |
31acbcc4 CW |
1625 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
1626 | ||
5bddd17f EA |
1627 | /* Hardware workaround: leaving our transcoder select |
1628 | * set to transcoder B while it's off will prevent the | |
1629 | * corresponding HDMI output on transcoder A. | |
1630 | * | |
1631 | * Combine this with another hardware workaround: | |
1632 | * transcoder select bit can only be cleared while the | |
1633 | * port is enabled. | |
1634 | */ | |
1635 | DP &= ~DP_PIPEB_SELECT; | |
1636 | I915_WRITE(intel_dp->output_reg, DP); | |
1637 | ||
1638 | /* Changes to enable or select take place the vblank | |
1639 | * after being written. | |
1640 | */ | |
31acbcc4 CW |
1641 | if (crtc == NULL) { |
1642 | /* We can arrive here never having been attached | |
1643 | * to a CRTC, for instance, due to inheriting | |
1644 | * random state from the BIOS. | |
1645 | * | |
1646 | * If the pipe is not running, play safe and | |
1647 | * wait for the clocks to stabilise before | |
1648 | * continuing. | |
1649 | */ | |
1650 | POSTING_READ(intel_dp->output_reg); | |
1651 | msleep(50); | |
1652 | } else | |
1653 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
5bddd17f EA |
1654 | } |
1655 | ||
ea5b213a CW |
1656 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
1657 | POSTING_READ(intel_dp->output_reg); | |
f01eca2e | 1658 | msleep(intel_dp->panel_power_down_delay); |
a4fc5ed6 KP |
1659 | } |
1660 | ||
26d61aad KP |
1661 | static bool |
1662 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 1663 | { |
92fd8fd1 KP |
1664 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
1665 | sizeof (intel_dp->dpcd)) && | |
1666 | (intel_dp->dpcd[DP_DPCD_REV] != 0)) { | |
26d61aad | 1667 | return true; |
92fd8fd1 KP |
1668 | } |
1669 | ||
26d61aad | 1670 | return false; |
92fd8fd1 KP |
1671 | } |
1672 | ||
a4fc5ed6 KP |
1673 | /* |
1674 | * According to DP spec | |
1675 | * 5.1.2: | |
1676 | * 1. Read DPCD | |
1677 | * 2. Configure link according to Receiver Capabilities | |
1678 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
1679 | * 4. Check link status on receipt of hot-plug interrupt | |
1680 | */ | |
1681 | ||
1682 | static void | |
ea5b213a | 1683 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1684 | { |
d2b996ac KP |
1685 | if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON) |
1686 | return; | |
59cd09e1 | 1687 | |
4ef69c7a | 1688 | if (!intel_dp->base.base.crtc) |
a4fc5ed6 KP |
1689 | return; |
1690 | ||
92fd8fd1 | 1691 | /* Try to read receiver status if the link appears to be up */ |
33a34e4e | 1692 | if (!intel_dp_get_link_status(intel_dp)) { |
ea5b213a | 1693 | intel_dp_link_down(intel_dp); |
a4fc5ed6 KP |
1694 | return; |
1695 | } | |
1696 | ||
92fd8fd1 | 1697 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 1698 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
1699 | intel_dp_link_down(intel_dp); |
1700 | return; | |
1701 | } | |
1702 | ||
33a34e4e | 1703 | if (!intel_channel_eq_ok(intel_dp)) { |
92fd8fd1 KP |
1704 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
1705 | drm_get_encoder_name(&intel_dp->base.base)); | |
33a34e4e JB |
1706 | intel_dp_start_link_train(intel_dp); |
1707 | intel_dp_complete_link_train(intel_dp); | |
1708 | } | |
a4fc5ed6 | 1709 | } |
a4fc5ed6 | 1710 | |
71ba9000 | 1711 | static enum drm_connector_status |
26d61aad | 1712 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 1713 | { |
26d61aad KP |
1714 | if (intel_dp_get_dpcd(intel_dp)) |
1715 | return connector_status_connected; | |
1716 | return connector_status_disconnected; | |
71ba9000 AJ |
1717 | } |
1718 | ||
5eb08b69 | 1719 | static enum drm_connector_status |
a9756bb5 | 1720 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 1721 | { |
5eb08b69 ZW |
1722 | enum drm_connector_status status; |
1723 | ||
fe16d949 CW |
1724 | /* Can't disconnect eDP, but you can close the lid... */ |
1725 | if (is_edp(intel_dp)) { | |
1726 | status = intel_panel_detect(intel_dp->base.base.dev); | |
1727 | if (status == connector_status_unknown) | |
1728 | status = connector_status_connected; | |
1729 | return status; | |
1730 | } | |
01cb9ea6 | 1731 | |
26d61aad | 1732 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
1733 | } |
1734 | ||
a4fc5ed6 | 1735 | static enum drm_connector_status |
a9756bb5 | 1736 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 1737 | { |
4ef69c7a | 1738 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1739 | struct drm_i915_private *dev_priv = dev->dev_private; |
a9756bb5 | 1740 | uint32_t temp, bit; |
5eb08b69 | 1741 | |
ea5b213a | 1742 | switch (intel_dp->output_reg) { |
a4fc5ed6 KP |
1743 | case DP_B: |
1744 | bit = DPB_HOTPLUG_INT_STATUS; | |
1745 | break; | |
1746 | case DP_C: | |
1747 | bit = DPC_HOTPLUG_INT_STATUS; | |
1748 | break; | |
1749 | case DP_D: | |
1750 | bit = DPD_HOTPLUG_INT_STATUS; | |
1751 | break; | |
1752 | default: | |
1753 | return connector_status_unknown; | |
1754 | } | |
1755 | ||
1756 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
1757 | ||
1758 | if ((temp & bit) == 0) | |
1759 | return connector_status_disconnected; | |
1760 | ||
26d61aad | 1761 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
1762 | } |
1763 | ||
8c241fef KP |
1764 | static struct edid * |
1765 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
1766 | { | |
1767 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1768 | struct edid *edid; | |
1769 | ||
1770 | ironlake_edp_panel_vdd_on(intel_dp); | |
1771 | edid = drm_get_edid(connector, adapter); | |
1772 | ironlake_edp_panel_vdd_off(intel_dp); | |
1773 | return edid; | |
1774 | } | |
1775 | ||
1776 | static int | |
1777 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) | |
1778 | { | |
1779 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1780 | int ret; | |
1781 | ||
1782 | ironlake_edp_panel_vdd_on(intel_dp); | |
1783 | ret = intel_ddc_get_modes(connector, adapter); | |
1784 | ironlake_edp_panel_vdd_off(intel_dp); | |
1785 | return ret; | |
1786 | } | |
1787 | ||
1788 | ||
a9756bb5 ZW |
1789 | /** |
1790 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. | |
1791 | * | |
1792 | * \return true if DP port is connected. | |
1793 | * \return false if DP port is disconnected. | |
1794 | */ | |
1795 | static enum drm_connector_status | |
1796 | intel_dp_detect(struct drm_connector *connector, bool force) | |
1797 | { | |
1798 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1799 | struct drm_device *dev = intel_dp->base.base.dev; | |
1800 | enum drm_connector_status status; | |
1801 | struct edid *edid = NULL; | |
1802 | ||
1803 | intel_dp->has_audio = false; | |
1804 | ||
1805 | if (HAS_PCH_SPLIT(dev)) | |
1806 | status = ironlake_dp_detect(intel_dp); | |
1807 | else | |
1808 | status = g4x_dp_detect(intel_dp); | |
1b9be9d0 | 1809 | |
ac66ae83 AJ |
1810 | DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", |
1811 | intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], | |
1812 | intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], | |
1813 | intel_dp->dpcd[6], intel_dp->dpcd[7]); | |
1b9be9d0 | 1814 | |
a9756bb5 ZW |
1815 | if (status != connector_status_connected) |
1816 | return status; | |
1817 | ||
f684960e CW |
1818 | if (intel_dp->force_audio) { |
1819 | intel_dp->has_audio = intel_dp->force_audio > 0; | |
1820 | } else { | |
8c241fef | 1821 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
f684960e CW |
1822 | if (edid) { |
1823 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
1824 | connector->display_info.raw_edid = NULL; | |
1825 | kfree(edid); | |
1826 | } | |
a9756bb5 ZW |
1827 | } |
1828 | ||
1829 | return connector_status_connected; | |
a4fc5ed6 KP |
1830 | } |
1831 | ||
1832 | static int intel_dp_get_modes(struct drm_connector *connector) | |
1833 | { | |
df0e9248 | 1834 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4ef69c7a | 1835 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1836 | struct drm_i915_private *dev_priv = dev->dev_private; |
1837 | int ret; | |
a4fc5ed6 KP |
1838 | |
1839 | /* We should parse the EDID data and find out if it has an audio sink | |
1840 | */ | |
1841 | ||
8c241fef | 1842 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
b9efc480 | 1843 | if (ret) { |
4d926461 | 1844 | if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) { |
b9efc480 ZY |
1845 | struct drm_display_mode *newmode; |
1846 | list_for_each_entry(newmode, &connector->probed_modes, | |
1847 | head) { | |
1848 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
1849 | dev_priv->panel_fixed_mode = | |
1850 | drm_mode_duplicate(dev, newmode); | |
1851 | break; | |
1852 | } | |
1853 | } | |
1854 | } | |
1855 | ||
32f9d658 | 1856 | return ret; |
b9efc480 | 1857 | } |
32f9d658 ZW |
1858 | |
1859 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ | |
4d926461 | 1860 | if (is_edp(intel_dp)) { |
47f0eb22 KP |
1861 | /* initialize panel mode from VBT if available for eDP */ |
1862 | if (dev_priv->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) { | |
1863 | dev_priv->panel_fixed_mode = | |
1864 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); | |
1865 | if (dev_priv->panel_fixed_mode) { | |
1866 | dev_priv->panel_fixed_mode->type |= | |
1867 | DRM_MODE_TYPE_PREFERRED; | |
1868 | } | |
1869 | } | |
1870 | if (dev_priv->panel_fixed_mode) { | |
32f9d658 ZW |
1871 | struct drm_display_mode *mode; |
1872 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); | |
1873 | drm_mode_probed_add(connector, mode); | |
1874 | return 1; | |
1875 | } | |
1876 | } | |
1877 | return 0; | |
a4fc5ed6 KP |
1878 | } |
1879 | ||
1aad7ac0 CW |
1880 | static bool |
1881 | intel_dp_detect_audio(struct drm_connector *connector) | |
1882 | { | |
1883 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1884 | struct edid *edid; | |
1885 | bool has_audio = false; | |
1886 | ||
8c241fef | 1887 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
1aad7ac0 CW |
1888 | if (edid) { |
1889 | has_audio = drm_detect_monitor_audio(edid); | |
1890 | ||
1891 | connector->display_info.raw_edid = NULL; | |
1892 | kfree(edid); | |
1893 | } | |
1894 | ||
1895 | return has_audio; | |
1896 | } | |
1897 | ||
f684960e CW |
1898 | static int |
1899 | intel_dp_set_property(struct drm_connector *connector, | |
1900 | struct drm_property *property, | |
1901 | uint64_t val) | |
1902 | { | |
e953fd7b | 1903 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
f684960e CW |
1904 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
1905 | int ret; | |
1906 | ||
1907 | ret = drm_connector_property_set_value(connector, property, val); | |
1908 | if (ret) | |
1909 | return ret; | |
1910 | ||
3f43c48d | 1911 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
1912 | int i = val; |
1913 | bool has_audio; | |
1914 | ||
1915 | if (i == intel_dp->force_audio) | |
f684960e CW |
1916 | return 0; |
1917 | ||
1aad7ac0 | 1918 | intel_dp->force_audio = i; |
f684960e | 1919 | |
1aad7ac0 CW |
1920 | if (i == 0) |
1921 | has_audio = intel_dp_detect_audio(connector); | |
1922 | else | |
1923 | has_audio = i > 0; | |
1924 | ||
1925 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
1926 | return 0; |
1927 | ||
1aad7ac0 | 1928 | intel_dp->has_audio = has_audio; |
f684960e CW |
1929 | goto done; |
1930 | } | |
1931 | ||
e953fd7b CW |
1932 | if (property == dev_priv->broadcast_rgb_property) { |
1933 | if (val == !!intel_dp->color_range) | |
1934 | return 0; | |
1935 | ||
1936 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; | |
1937 | goto done; | |
1938 | } | |
1939 | ||
f684960e CW |
1940 | return -EINVAL; |
1941 | ||
1942 | done: | |
1943 | if (intel_dp->base.base.crtc) { | |
1944 | struct drm_crtc *crtc = intel_dp->base.base.crtc; | |
1945 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
1946 | crtc->x, crtc->y, | |
1947 | crtc->fb); | |
1948 | } | |
1949 | ||
1950 | return 0; | |
1951 | } | |
1952 | ||
a4fc5ed6 KP |
1953 | static void |
1954 | intel_dp_destroy (struct drm_connector *connector) | |
1955 | { | |
aaa6fd2a MG |
1956 | struct drm_device *dev = connector->dev; |
1957 | ||
1958 | if (intel_dpd_is_edp(dev)) | |
1959 | intel_panel_destroy_backlight(dev); | |
1960 | ||
a4fc5ed6 KP |
1961 | drm_sysfs_connector_remove(connector); |
1962 | drm_connector_cleanup(connector); | |
55f78c43 | 1963 | kfree(connector); |
a4fc5ed6 KP |
1964 | } |
1965 | ||
24d05927 DV |
1966 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
1967 | { | |
1968 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1969 | ||
1970 | i2c_del_adapter(&intel_dp->adapter); | |
1971 | drm_encoder_cleanup(encoder); | |
1972 | kfree(intel_dp); | |
1973 | } | |
1974 | ||
a4fc5ed6 KP |
1975 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
1976 | .dpms = intel_dp_dpms, | |
1977 | .mode_fixup = intel_dp_mode_fixup, | |
d240f20f | 1978 | .prepare = intel_dp_prepare, |
a4fc5ed6 | 1979 | .mode_set = intel_dp_mode_set, |
d240f20f | 1980 | .commit = intel_dp_commit, |
a4fc5ed6 KP |
1981 | }; |
1982 | ||
1983 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
1984 | .dpms = drm_helper_connector_dpms, | |
a4fc5ed6 KP |
1985 | .detect = intel_dp_detect, |
1986 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 1987 | .set_property = intel_dp_set_property, |
a4fc5ed6 KP |
1988 | .destroy = intel_dp_destroy, |
1989 | }; | |
1990 | ||
1991 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
1992 | .get_modes = intel_dp_get_modes, | |
1993 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 1994 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
1995 | }; |
1996 | ||
a4fc5ed6 | 1997 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 1998 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
1999 | }; |
2000 | ||
995b6762 | 2001 | static void |
21d40d37 | 2002 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 2003 | { |
ea5b213a | 2004 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
c8110e52 | 2005 | |
885a5014 | 2006 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 2007 | } |
6207937d | 2008 | |
e3421a18 ZW |
2009 | /* Return which DP Port should be selected for Transcoder DP control */ |
2010 | int | |
2011 | intel_trans_dp_port_sel (struct drm_crtc *crtc) | |
2012 | { | |
2013 | struct drm_device *dev = crtc->dev; | |
2014 | struct drm_mode_config *mode_config = &dev->mode_config; | |
2015 | struct drm_encoder *encoder; | |
e3421a18 ZW |
2016 | |
2017 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a CW |
2018 | struct intel_dp *intel_dp; |
2019 | ||
d8201ab6 | 2020 | if (encoder->crtc != crtc) |
e3421a18 ZW |
2021 | continue; |
2022 | ||
ea5b213a CW |
2023 | intel_dp = enc_to_intel_dp(encoder); |
2024 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) | |
2025 | return intel_dp->output_reg; | |
e3421a18 | 2026 | } |
ea5b213a | 2027 | |
e3421a18 ZW |
2028 | return -1; |
2029 | } | |
2030 | ||
36e83a18 | 2031 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 2032 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
2033 | { |
2034 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2035 | struct child_device_config *p_child; | |
2036 | int i; | |
2037 | ||
2038 | if (!dev_priv->child_dev_num) | |
2039 | return false; | |
2040 | ||
2041 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
2042 | p_child = dev_priv->child_dev + i; | |
2043 | ||
2044 | if (p_child->dvo_port == PORT_IDPD && | |
2045 | p_child->device_type == DEVICE_TYPE_eDP) | |
2046 | return true; | |
2047 | } | |
2048 | return false; | |
2049 | } | |
2050 | ||
f684960e CW |
2051 | static void |
2052 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
2053 | { | |
3f43c48d | 2054 | intel_attach_force_audio_property(connector); |
e953fd7b | 2055 | intel_attach_broadcast_rgb_property(connector); |
f684960e CW |
2056 | } |
2057 | ||
a4fc5ed6 KP |
2058 | void |
2059 | intel_dp_init(struct drm_device *dev, int output_reg) | |
2060 | { | |
2061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2062 | struct drm_connector *connector; | |
ea5b213a | 2063 | struct intel_dp *intel_dp; |
21d40d37 | 2064 | struct intel_encoder *intel_encoder; |
55f78c43 | 2065 | struct intel_connector *intel_connector; |
5eb08b69 | 2066 | const char *name = NULL; |
b329530c | 2067 | int type; |
a4fc5ed6 | 2068 | |
ea5b213a CW |
2069 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
2070 | if (!intel_dp) | |
a4fc5ed6 KP |
2071 | return; |
2072 | ||
3d3dc149 | 2073 | intel_dp->output_reg = output_reg; |
d2b996ac | 2074 | intel_dp->dpms_mode = -1; |
3d3dc149 | 2075 | |
55f78c43 ZW |
2076 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
2077 | if (!intel_connector) { | |
ea5b213a | 2078 | kfree(intel_dp); |
55f78c43 ZW |
2079 | return; |
2080 | } | |
ea5b213a | 2081 | intel_encoder = &intel_dp->base; |
55f78c43 | 2082 | |
ea5b213a | 2083 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
b329530c | 2084 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 2085 | intel_dp->is_pch_edp = true; |
b329530c | 2086 | |
cfcb0fc9 | 2087 | if (output_reg == DP_A || is_pch_edp(intel_dp)) { |
b329530c AJ |
2088 | type = DRM_MODE_CONNECTOR_eDP; |
2089 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
2090 | } else { | |
2091 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
2092 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
2093 | } | |
2094 | ||
55f78c43 | 2095 | connector = &intel_connector->base; |
b329530c | 2096 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
2097 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
2098 | ||
eb1f8e4f DA |
2099 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
2100 | ||
652af9d7 | 2101 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
21d40d37 | 2102 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
652af9d7 | 2103 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
21d40d37 | 2104 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
652af9d7 | 2105 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
21d40d37 | 2106 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
f8aed700 | 2107 | |
cfcb0fc9 | 2108 | if (is_edp(intel_dp)) |
21d40d37 | 2109 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
6251ec0a | 2110 | |
21d40d37 | 2111 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
a4fc5ed6 KP |
2112 | connector->interlace_allowed = true; |
2113 | connector->doublescan_allowed = 0; | |
2114 | ||
4ef69c7a | 2115 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
a4fc5ed6 | 2116 | DRM_MODE_ENCODER_TMDS); |
4ef69c7a | 2117 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
a4fc5ed6 | 2118 | |
df0e9248 | 2119 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
2120 | drm_sysfs_connector_add(connector); |
2121 | ||
2122 | /* Set up the DDC bus. */ | |
5eb08b69 | 2123 | switch (output_reg) { |
32f9d658 ZW |
2124 | case DP_A: |
2125 | name = "DPDDC-A"; | |
2126 | break; | |
5eb08b69 ZW |
2127 | case DP_B: |
2128 | case PCH_DP_B: | |
b01f2c3a JB |
2129 | dev_priv->hotplug_supported_mask |= |
2130 | HDMIB_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2131 | name = "DPDDC-B"; |
2132 | break; | |
2133 | case DP_C: | |
2134 | case PCH_DP_C: | |
b01f2c3a JB |
2135 | dev_priv->hotplug_supported_mask |= |
2136 | HDMIC_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2137 | name = "DPDDC-C"; |
2138 | break; | |
2139 | case DP_D: | |
2140 | case PCH_DP_D: | |
b01f2c3a JB |
2141 | dev_priv->hotplug_supported_mask |= |
2142 | HDMID_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2143 | name = "DPDDC-D"; |
2144 | break; | |
2145 | } | |
2146 | ||
89667383 JB |
2147 | /* Cache some DPCD data in the eDP case */ |
2148 | if (is_edp(intel_dp)) { | |
59f3e272 | 2149 | bool ret; |
f01eca2e KP |
2150 | struct edp_power_seq cur, vbt; |
2151 | u32 pp_on, pp_off, pp_div; | |
5d613501 JB |
2152 | |
2153 | pp_on = I915_READ(PCH_PP_ON_DELAYS); | |
f01eca2e | 2154 | pp_off = I915_READ(PCH_PP_OFF_DELAYS); |
5d613501 | 2155 | pp_div = I915_READ(PCH_PP_DIVISOR); |
89667383 | 2156 | |
f01eca2e KP |
2157 | /* Pull timing values out of registers */ |
2158 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
2159 | PANEL_POWER_UP_DELAY_SHIFT; | |
2160 | ||
2161 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
2162 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
2163 | ||
2164 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
2165 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
2166 | ||
2167 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
2168 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
2169 | ||
2170 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
2171 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
2172 | ||
2173 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2174 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
2175 | ||
2176 | vbt = dev_priv->edp.pps; | |
2177 | ||
2178 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2179 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
2180 | ||
2181 | #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10) | |
2182 | ||
2183 | intel_dp->panel_power_up_delay = get_delay(t1_t3); | |
2184 | intel_dp->backlight_on_delay = get_delay(t8); | |
2185 | intel_dp->backlight_off_delay = get_delay(t9); | |
2186 | intel_dp->panel_power_down_delay = get_delay(t10); | |
2187 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
2188 | ||
2189 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", | |
2190 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
2191 | intel_dp->panel_power_cycle_delay); | |
2192 | ||
2193 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
2194 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
5d613501 JB |
2195 | |
2196 | ironlake_edp_panel_vdd_on(intel_dp); | |
59f3e272 | 2197 | ret = intel_dp_get_dpcd(intel_dp); |
3d3dc149 | 2198 | ironlake_edp_panel_vdd_off(intel_dp); |
59f3e272 | 2199 | if (ret) { |
7183dc29 JB |
2200 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
2201 | dev_priv->no_aux_handshake = | |
2202 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
89667383 JB |
2203 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
2204 | } else { | |
3d3dc149 | 2205 | /* if this fails, presume the device is a ghost */ |
48898b03 | 2206 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
3d3dc149 | 2207 | intel_dp_encoder_destroy(&intel_dp->base.base); |
48898b03 | 2208 | intel_dp_destroy(&intel_connector->base); |
3d3dc149 | 2209 | return; |
89667383 | 2210 | } |
89667383 JB |
2211 | } |
2212 | ||
552fb0b7 KP |
2213 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
2214 | ||
21d40d37 | 2215 | intel_encoder->hot_plug = intel_dp_hot_plug; |
a4fc5ed6 | 2216 | |
4d926461 | 2217 | if (is_edp(intel_dp)) { |
aaa6fd2a MG |
2218 | dev_priv->int_edp_connector = connector; |
2219 | intel_panel_setup_backlight(dev); | |
32f9d658 ZW |
2220 | } |
2221 | ||
f684960e CW |
2222 | intel_dp_add_properties(intel_dp, connector); |
2223 | ||
a4fc5ed6 KP |
2224 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
2225 | * 0xd. Failure to do so will result in spurious interrupts being | |
2226 | * generated on the port when a cable is not attached. | |
2227 | */ | |
2228 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
2229 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
2230 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2231 | } | |
2232 | } |