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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
a4fc5ed6 KP |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "drm_crtc_helper.h" | |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
ab2c0672 | 37 | #include "drm_dp_helper.h" |
a4fc5ed6 | 38 | |
ae266c98 | 39 | |
a4fc5ed6 KP |
40 | #define DP_LINK_STATUS_SIZE 6 |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) | |
42 | ||
43 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
44 | ||
ea5b213a CW |
45 | struct intel_dp { |
46 | struct intel_encoder base; | |
a4fc5ed6 KP |
47 | uint32_t output_reg; |
48 | uint32_t DP; | |
49 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
a4fc5ed6 | 50 | bool has_audio; |
f684960e | 51 | int force_audio; |
e953fd7b | 52 | uint32_t color_range; |
a4fc5ed6 KP |
53 | uint8_t link_bw; |
54 | uint8_t lane_count; | |
9de88e6e | 55 | uint8_t dpcd[8]; |
a4fc5ed6 KP |
56 | struct i2c_adapter adapter; |
57 | struct i2c_algo_dp_aux_data algo; | |
f0917379 | 58 | bool is_pch_edp; |
33a34e4e JB |
59 | uint8_t train_set[4]; |
60 | uint8_t link_status[DP_LINK_STATUS_SIZE]; | |
a4fc5ed6 KP |
61 | }; |
62 | ||
cfcb0fc9 JB |
63 | /** |
64 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
65 | * @intel_dp: DP struct | |
66 | * | |
67 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
68 | * will return true, and false otherwise. | |
69 | */ | |
70 | static bool is_edp(struct intel_dp *intel_dp) | |
71 | { | |
72 | return intel_dp->base.type == INTEL_OUTPUT_EDP; | |
73 | } | |
74 | ||
75 | /** | |
76 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? | |
77 | * @intel_dp: DP struct | |
78 | * | |
79 | * Returns true if the given DP struct corresponds to a PCH DP port attached | |
80 | * to an eDP panel, false otherwise. Helpful for determining whether we | |
81 | * may need FDI resources for a given DP output or not. | |
82 | */ | |
83 | static bool is_pch_edp(struct intel_dp *intel_dp) | |
84 | { | |
85 | return intel_dp->is_pch_edp; | |
86 | } | |
87 | ||
ea5b213a CW |
88 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
89 | { | |
4ef69c7a | 90 | return container_of(encoder, struct intel_dp, base.base); |
ea5b213a | 91 | } |
a4fc5ed6 | 92 | |
df0e9248 CW |
93 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
94 | { | |
95 | return container_of(intel_attached_encoder(connector), | |
96 | struct intel_dp, base); | |
97 | } | |
98 | ||
814948ad JB |
99 | /** |
100 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? | |
101 | * @encoder: DRM encoder | |
102 | * | |
103 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed | |
104 | * by intel_display.c. | |
105 | */ | |
106 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) | |
107 | { | |
108 | struct intel_dp *intel_dp; | |
109 | ||
110 | if (!encoder) | |
111 | return false; | |
112 | ||
113 | intel_dp = enc_to_intel_dp(encoder); | |
114 | ||
115 | return is_pch_edp(intel_dp); | |
116 | } | |
117 | ||
33a34e4e JB |
118 | static void intel_dp_start_link_train(struct intel_dp *intel_dp); |
119 | static void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
ea5b213a | 120 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
a4fc5ed6 | 121 | |
32f9d658 | 122 | void |
21d40d37 | 123 | intel_edp_link_config (struct intel_encoder *intel_encoder, |
ea5b213a | 124 | int *lane_num, int *link_bw) |
32f9d658 | 125 | { |
ea5b213a | 126 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
32f9d658 | 127 | |
ea5b213a CW |
128 | *lane_num = intel_dp->lane_count; |
129 | if (intel_dp->link_bw == DP_LINK_BW_1_62) | |
32f9d658 | 130 | *link_bw = 162000; |
ea5b213a | 131 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
32f9d658 ZW |
132 | *link_bw = 270000; |
133 | } | |
134 | ||
a4fc5ed6 | 135 | static int |
ea5b213a | 136 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
a4fc5ed6 | 137 | { |
a4fc5ed6 KP |
138 | int max_lane_count = 4; |
139 | ||
7183dc29 JB |
140 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
141 | max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; | |
a4fc5ed6 KP |
142 | switch (max_lane_count) { |
143 | case 1: case 2: case 4: | |
144 | break; | |
145 | default: | |
146 | max_lane_count = 4; | |
147 | } | |
148 | } | |
149 | return max_lane_count; | |
150 | } | |
151 | ||
152 | static int | |
ea5b213a | 153 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 154 | { |
7183dc29 | 155 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
156 | |
157 | switch (max_link_bw) { | |
158 | case DP_LINK_BW_1_62: | |
159 | case DP_LINK_BW_2_7: | |
160 | break; | |
161 | default: | |
162 | max_link_bw = DP_LINK_BW_1_62; | |
163 | break; | |
164 | } | |
165 | return max_link_bw; | |
166 | } | |
167 | ||
168 | static int | |
169 | intel_dp_link_clock(uint8_t link_bw) | |
170 | { | |
171 | if (link_bw == DP_LINK_BW_2_7) | |
172 | return 270000; | |
173 | else | |
174 | return 162000; | |
175 | } | |
176 | ||
177 | /* I think this is a fiction */ | |
178 | static int | |
ea5b213a | 179 | intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) |
a4fc5ed6 | 180 | { |
885a5fb5 ZW |
181 | struct drm_i915_private *dev_priv = dev->dev_private; |
182 | ||
4d926461 | 183 | if (is_edp(intel_dp)) |
5ceb0f9b | 184 | return (pixel_clock * dev_priv->edp.bpp + 7) / 8; |
885a5fb5 ZW |
185 | else |
186 | return pixel_clock * 3; | |
a4fc5ed6 KP |
187 | } |
188 | ||
fe27d53e DA |
189 | static int |
190 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
191 | { | |
192 | return (max_link_clock * max_lanes * 8) / 10; | |
193 | } | |
194 | ||
a4fc5ed6 KP |
195 | static int |
196 | intel_dp_mode_valid(struct drm_connector *connector, | |
197 | struct drm_display_mode *mode) | |
198 | { | |
df0e9248 | 199 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
7de56f43 ZY |
200 | struct drm_device *dev = connector->dev; |
201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a CW |
202 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
203 | int max_lanes = intel_dp_max_lane_count(intel_dp); | |
a4fc5ed6 | 204 | |
4d926461 | 205 | if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { |
7de56f43 ZY |
206 | if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) |
207 | return MODE_PANEL; | |
208 | ||
209 | if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay) | |
210 | return MODE_PANEL; | |
211 | } | |
212 | ||
25985edc | 213 | /* only refuse the mode on non eDP since we have seen some weird eDP panels |
fe27d53e | 214 | which are outside spec tolerances but somehow work by magic */ |
cfcb0fc9 | 215 | if (!is_edp(intel_dp) && |
ea5b213a | 216 | (intel_dp_link_required(connector->dev, intel_dp, mode->clock) |
fe27d53e | 217 | > intel_dp_max_data_rate(max_link_clock, max_lanes))) |
a4fc5ed6 KP |
218 | return MODE_CLOCK_HIGH; |
219 | ||
220 | if (mode->clock < 10000) | |
221 | return MODE_CLOCK_LOW; | |
222 | ||
223 | return MODE_OK; | |
224 | } | |
225 | ||
226 | static uint32_t | |
227 | pack_aux(uint8_t *src, int src_bytes) | |
228 | { | |
229 | int i; | |
230 | uint32_t v = 0; | |
231 | ||
232 | if (src_bytes > 4) | |
233 | src_bytes = 4; | |
234 | for (i = 0; i < src_bytes; i++) | |
235 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
236 | return v; | |
237 | } | |
238 | ||
239 | static void | |
240 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
241 | { | |
242 | int i; | |
243 | if (dst_bytes > 4) | |
244 | dst_bytes = 4; | |
245 | for (i = 0; i < dst_bytes; i++) | |
246 | dst[i] = src >> ((3-i) * 8); | |
247 | } | |
248 | ||
fb0f8fbf KP |
249 | /* hrawclock is 1/4 the FSB frequency */ |
250 | static int | |
251 | intel_hrawclk(struct drm_device *dev) | |
252 | { | |
253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
254 | uint32_t clkcfg; | |
255 | ||
256 | clkcfg = I915_READ(CLKCFG); | |
257 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
258 | case CLKCFG_FSB_400: | |
259 | return 100; | |
260 | case CLKCFG_FSB_533: | |
261 | return 133; | |
262 | case CLKCFG_FSB_667: | |
263 | return 166; | |
264 | case CLKCFG_FSB_800: | |
265 | return 200; | |
266 | case CLKCFG_FSB_1067: | |
267 | return 266; | |
268 | case CLKCFG_FSB_1333: | |
269 | return 333; | |
270 | /* these two are just a guess; one of them might be right */ | |
271 | case CLKCFG_FSB_1600: | |
272 | case CLKCFG_FSB_1600_ALT: | |
273 | return 400; | |
274 | default: | |
275 | return 133; | |
276 | } | |
277 | } | |
278 | ||
a4fc5ed6 | 279 | static int |
ea5b213a | 280 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
281 | uint8_t *send, int send_bytes, |
282 | uint8_t *recv, int recv_size) | |
283 | { | |
ea5b213a | 284 | uint32_t output_reg = intel_dp->output_reg; |
4ef69c7a | 285 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 KP |
286 | struct drm_i915_private *dev_priv = dev->dev_private; |
287 | uint32_t ch_ctl = output_reg + 0x10; | |
288 | uint32_t ch_data = ch_ctl + 4; | |
289 | int i; | |
290 | int recv_bytes; | |
a4fc5ed6 | 291 | uint32_t status; |
fb0f8fbf | 292 | uint32_t aux_clock_divider; |
e3421a18 | 293 | int try, precharge; |
a4fc5ed6 KP |
294 | |
295 | /* The clock divider is based off the hrawclk, | |
fb0f8fbf KP |
296 | * and would like to run at 2MHz. So, take the |
297 | * hrawclk value and divide by 2 and use that | |
6176b8f9 JB |
298 | * |
299 | * Note that PCH attached eDP panels should use a 125MHz input | |
300 | * clock divider. | |
a4fc5ed6 | 301 | */ |
cfcb0fc9 | 302 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
e3421a18 ZW |
303 | if (IS_GEN6(dev)) |
304 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ | |
305 | else | |
306 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
307 | } else if (HAS_PCH_SPLIT(dev)) | |
f2b115e6 | 308 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
5eb08b69 ZW |
309 | else |
310 | aux_clock_divider = intel_hrawclk(dev) / 2; | |
311 | ||
e3421a18 ZW |
312 | if (IS_GEN6(dev)) |
313 | precharge = 3; | |
314 | else | |
315 | precharge = 5; | |
316 | ||
4f7f7b7e CW |
317 | if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { |
318 | DRM_ERROR("dp_aux_ch not started status 0x%08x\n", | |
319 | I915_READ(ch_ctl)); | |
320 | return -EBUSY; | |
321 | } | |
322 | ||
fb0f8fbf KP |
323 | /* Must try at least 3 times according to DP spec */ |
324 | for (try = 0; try < 5; try++) { | |
325 | /* Load the send data into the aux channel data registers */ | |
4f7f7b7e CW |
326 | for (i = 0; i < send_bytes; i += 4) |
327 | I915_WRITE(ch_data + i, | |
328 | pack_aux(send + i, send_bytes - i)); | |
fb0f8fbf KP |
329 | |
330 | /* Send the command and wait for it to complete */ | |
4f7f7b7e CW |
331 | I915_WRITE(ch_ctl, |
332 | DP_AUX_CH_CTL_SEND_BUSY | | |
333 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
334 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
335 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
336 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
337 | DP_AUX_CH_CTL_DONE | | |
338 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
339 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
fb0f8fbf | 340 | for (;;) { |
fb0f8fbf KP |
341 | status = I915_READ(ch_ctl); |
342 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
343 | break; | |
4f7f7b7e | 344 | udelay(100); |
fb0f8fbf KP |
345 | } |
346 | ||
347 | /* Clear done status and any errors */ | |
4f7f7b7e CW |
348 | I915_WRITE(ch_ctl, |
349 | status | | |
350 | DP_AUX_CH_CTL_DONE | | |
351 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
352 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
353 | if (status & DP_AUX_CH_CTL_DONE) | |
a4fc5ed6 KP |
354 | break; |
355 | } | |
356 | ||
a4fc5ed6 | 357 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 358 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
a5b3da54 | 359 | return -EBUSY; |
a4fc5ed6 KP |
360 | } |
361 | ||
362 | /* Check for timeout or receive error. | |
363 | * Timeouts occur when the sink is not connected | |
364 | */ | |
a5b3da54 | 365 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 366 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
a5b3da54 KP |
367 | return -EIO; |
368 | } | |
1ae8c0a5 KP |
369 | |
370 | /* Timeouts occur when the device isn't connected, so they're | |
371 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 372 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 373 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
a5b3da54 | 374 | return -ETIMEDOUT; |
a4fc5ed6 KP |
375 | } |
376 | ||
377 | /* Unload any bytes sent back from the other side */ | |
378 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
379 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
380 | if (recv_bytes > recv_size) |
381 | recv_bytes = recv_size; | |
382 | ||
4f7f7b7e CW |
383 | for (i = 0; i < recv_bytes; i += 4) |
384 | unpack_aux(I915_READ(ch_data + i), | |
385 | recv + i, recv_bytes - i); | |
a4fc5ed6 KP |
386 | |
387 | return recv_bytes; | |
388 | } | |
389 | ||
390 | /* Write data to the aux channel in native mode */ | |
391 | static int | |
ea5b213a | 392 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
393 | uint16_t address, uint8_t *send, int send_bytes) |
394 | { | |
395 | int ret; | |
396 | uint8_t msg[20]; | |
397 | int msg_bytes; | |
398 | uint8_t ack; | |
399 | ||
400 | if (send_bytes > 16) | |
401 | return -1; | |
402 | msg[0] = AUX_NATIVE_WRITE << 4; | |
403 | msg[1] = address >> 8; | |
eebc863e | 404 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
405 | msg[3] = send_bytes - 1; |
406 | memcpy(&msg[4], send, send_bytes); | |
407 | msg_bytes = send_bytes + 4; | |
408 | for (;;) { | |
ea5b213a | 409 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
410 | if (ret < 0) |
411 | return ret; | |
412 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
413 | break; | |
414 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
415 | udelay(100); | |
416 | else | |
a5b3da54 | 417 | return -EIO; |
a4fc5ed6 KP |
418 | } |
419 | return send_bytes; | |
420 | } | |
421 | ||
422 | /* Write a single byte to the aux channel in native mode */ | |
423 | static int | |
ea5b213a | 424 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
425 | uint16_t address, uint8_t byte) |
426 | { | |
ea5b213a | 427 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
428 | } |
429 | ||
430 | /* read bytes from a native aux channel */ | |
431 | static int | |
ea5b213a | 432 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
433 | uint16_t address, uint8_t *recv, int recv_bytes) |
434 | { | |
435 | uint8_t msg[4]; | |
436 | int msg_bytes; | |
437 | uint8_t reply[20]; | |
438 | int reply_bytes; | |
439 | uint8_t ack; | |
440 | int ret; | |
441 | ||
442 | msg[0] = AUX_NATIVE_READ << 4; | |
443 | msg[1] = address >> 8; | |
444 | msg[2] = address & 0xff; | |
445 | msg[3] = recv_bytes - 1; | |
446 | ||
447 | msg_bytes = 4; | |
448 | reply_bytes = recv_bytes + 1; | |
449 | ||
450 | for (;;) { | |
ea5b213a | 451 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 452 | reply, reply_bytes); |
a5b3da54 KP |
453 | if (ret == 0) |
454 | return -EPROTO; | |
455 | if (ret < 0) | |
a4fc5ed6 KP |
456 | return ret; |
457 | ack = reply[0]; | |
458 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
459 | memcpy(recv, reply + 1, ret - 1); | |
460 | return ret - 1; | |
461 | } | |
462 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
463 | udelay(100); | |
464 | else | |
a5b3da54 | 465 | return -EIO; |
a4fc5ed6 KP |
466 | } |
467 | } | |
468 | ||
469 | static int | |
ab2c0672 DA |
470 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
471 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 472 | { |
ab2c0672 | 473 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
474 | struct intel_dp *intel_dp = container_of(adapter, |
475 | struct intel_dp, | |
476 | adapter); | |
ab2c0672 DA |
477 | uint16_t address = algo_data->address; |
478 | uint8_t msg[5]; | |
479 | uint8_t reply[2]; | |
8316f337 | 480 | unsigned retry; |
ab2c0672 DA |
481 | int msg_bytes; |
482 | int reply_bytes; | |
483 | int ret; | |
484 | ||
485 | /* Set up the command byte */ | |
486 | if (mode & MODE_I2C_READ) | |
487 | msg[0] = AUX_I2C_READ << 4; | |
488 | else | |
489 | msg[0] = AUX_I2C_WRITE << 4; | |
490 | ||
491 | if (!(mode & MODE_I2C_STOP)) | |
492 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 493 | |
ab2c0672 DA |
494 | msg[1] = address >> 8; |
495 | msg[2] = address; | |
496 | ||
497 | switch (mode) { | |
498 | case MODE_I2C_WRITE: | |
499 | msg[3] = 0; | |
500 | msg[4] = write_byte; | |
501 | msg_bytes = 5; | |
502 | reply_bytes = 1; | |
503 | break; | |
504 | case MODE_I2C_READ: | |
505 | msg[3] = 0; | |
506 | msg_bytes = 4; | |
507 | reply_bytes = 2; | |
508 | break; | |
509 | default: | |
510 | msg_bytes = 3; | |
511 | reply_bytes = 1; | |
512 | break; | |
513 | } | |
514 | ||
8316f337 DF |
515 | for (retry = 0; retry < 5; retry++) { |
516 | ret = intel_dp_aux_ch(intel_dp, | |
517 | msg, msg_bytes, | |
518 | reply, reply_bytes); | |
ab2c0672 | 519 | if (ret < 0) { |
3ff99164 | 520 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
521 | return ret; |
522 | } | |
8316f337 DF |
523 | |
524 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { | |
525 | case AUX_NATIVE_REPLY_ACK: | |
526 | /* I2C-over-AUX Reply field is only valid | |
527 | * when paired with AUX ACK. | |
528 | */ | |
529 | break; | |
530 | case AUX_NATIVE_REPLY_NACK: | |
531 | DRM_DEBUG_KMS("aux_ch native nack\n"); | |
532 | return -EREMOTEIO; | |
533 | case AUX_NATIVE_REPLY_DEFER: | |
534 | udelay(100); | |
535 | continue; | |
536 | default: | |
537 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", | |
538 | reply[0]); | |
539 | return -EREMOTEIO; | |
540 | } | |
541 | ||
ab2c0672 DA |
542 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
543 | case AUX_I2C_REPLY_ACK: | |
544 | if (mode == MODE_I2C_READ) { | |
545 | *read_byte = reply[1]; | |
546 | } | |
547 | return reply_bytes - 1; | |
548 | case AUX_I2C_REPLY_NACK: | |
8316f337 | 549 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
ab2c0672 DA |
550 | return -EREMOTEIO; |
551 | case AUX_I2C_REPLY_DEFER: | |
8316f337 | 552 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
ab2c0672 DA |
553 | udelay(100); |
554 | break; | |
555 | default: | |
8316f337 | 556 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
ab2c0672 DA |
557 | return -EREMOTEIO; |
558 | } | |
559 | } | |
8316f337 DF |
560 | |
561 | DRM_ERROR("too many retries, giving up\n"); | |
562 | return -EREMOTEIO; | |
a4fc5ed6 KP |
563 | } |
564 | ||
565 | static int | |
ea5b213a | 566 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 567 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 568 | { |
d54e9d28 | 569 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
570 | intel_dp->algo.running = false; |
571 | intel_dp->algo.address = 0; | |
572 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
573 | ||
574 | memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); | |
575 | intel_dp->adapter.owner = THIS_MODULE; | |
576 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
577 | strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); | |
578 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; | |
579 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
580 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
581 | ||
582 | return i2c_dp_aux_add_bus(&intel_dp->adapter); | |
a4fc5ed6 KP |
583 | } |
584 | ||
585 | static bool | |
586 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
587 | struct drm_display_mode *adjusted_mode) | |
588 | { | |
0d3a1bee ZY |
589 | struct drm_device *dev = encoder->dev; |
590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 591 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4fc5ed6 | 592 | int lane_count, clock; |
ea5b213a CW |
593 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
594 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; | |
a4fc5ed6 KP |
595 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
596 | ||
4d926461 | 597 | if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) { |
1d8e1c75 CW |
598 | intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); |
599 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, | |
600 | mode, adjusted_mode); | |
0d3a1bee ZY |
601 | /* |
602 | * the mode->clock is used to calculate the Data&Link M/N | |
603 | * of the pipe. For the eDP the fixed clock should be used. | |
604 | */ | |
605 | mode->clock = dev_priv->panel_fixed_mode->clock; | |
606 | } | |
607 | ||
a4fc5ed6 KP |
608 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
609 | for (clock = 0; clock <= max_clock; clock++) { | |
fe27d53e | 610 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
a4fc5ed6 | 611 | |
ea5b213a | 612 | if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) |
885a5fb5 | 613 | <= link_avail) { |
ea5b213a CW |
614 | intel_dp->link_bw = bws[clock]; |
615 | intel_dp->lane_count = lane_count; | |
616 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
28c97730 ZY |
617 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
618 | "count %d clock %d\n", | |
ea5b213a | 619 | intel_dp->link_bw, intel_dp->lane_count, |
a4fc5ed6 KP |
620 | adjusted_mode->clock); |
621 | return true; | |
622 | } | |
623 | } | |
624 | } | |
fe27d53e | 625 | |
3cf2efb1 CW |
626 | if (is_edp(intel_dp)) { |
627 | /* okay we failed just pick the highest */ | |
628 | intel_dp->lane_count = max_lane_count; | |
629 | intel_dp->link_bw = bws[max_clock]; | |
630 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
631 | DRM_DEBUG_KMS("Force picking display port link bw %02x lane " | |
632 | "count %d clock %d\n", | |
633 | intel_dp->link_bw, intel_dp->lane_count, | |
634 | adjusted_mode->clock); | |
635 | ||
636 | return true; | |
637 | } | |
638 | ||
a4fc5ed6 KP |
639 | return false; |
640 | } | |
641 | ||
642 | struct intel_dp_m_n { | |
643 | uint32_t tu; | |
644 | uint32_t gmch_m; | |
645 | uint32_t gmch_n; | |
646 | uint32_t link_m; | |
647 | uint32_t link_n; | |
648 | }; | |
649 | ||
650 | static void | |
651 | intel_reduce_ratio(uint32_t *num, uint32_t *den) | |
652 | { | |
653 | while (*num > 0xffffff || *den > 0xffffff) { | |
654 | *num >>= 1; | |
655 | *den >>= 1; | |
656 | } | |
657 | } | |
658 | ||
659 | static void | |
36e83a18 | 660 | intel_dp_compute_m_n(int bpp, |
a4fc5ed6 KP |
661 | int nlanes, |
662 | int pixel_clock, | |
663 | int link_clock, | |
664 | struct intel_dp_m_n *m_n) | |
665 | { | |
666 | m_n->tu = 64; | |
36e83a18 | 667 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
a4fc5ed6 KP |
668 | m_n->gmch_n = link_clock * nlanes; |
669 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
670 | m_n->link_m = pixel_clock; | |
671 | m_n->link_n = link_clock; | |
672 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
673 | } | |
674 | ||
675 | void | |
676 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
677 | struct drm_display_mode *adjusted_mode) | |
678 | { | |
679 | struct drm_device *dev = crtc->dev; | |
680 | struct drm_mode_config *mode_config = &dev->mode_config; | |
55f78c43 | 681 | struct drm_encoder *encoder; |
a4fc5ed6 KP |
682 | struct drm_i915_private *dev_priv = dev->dev_private; |
683 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
36e83a18 | 684 | int lane_count = 4, bpp = 24; |
a4fc5ed6 | 685 | struct intel_dp_m_n m_n; |
9db4a9c7 | 686 | int pipe = intel_crtc->pipe; |
a4fc5ed6 KP |
687 | |
688 | /* | |
21d40d37 | 689 | * Find the lane count in the intel_encoder private |
a4fc5ed6 | 690 | */ |
55f78c43 | 691 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
ea5b213a | 692 | struct intel_dp *intel_dp; |
a4fc5ed6 | 693 | |
d8201ab6 | 694 | if (encoder->crtc != crtc) |
a4fc5ed6 KP |
695 | continue; |
696 | ||
ea5b213a CW |
697 | intel_dp = enc_to_intel_dp(encoder); |
698 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
699 | lane_count = intel_dp->lane_count; | |
51190667 JB |
700 | break; |
701 | } else if (is_edp(intel_dp)) { | |
702 | lane_count = dev_priv->edp.lanes; | |
703 | bpp = dev_priv->edp.bpp; | |
a4fc5ed6 KP |
704 | break; |
705 | } | |
706 | } | |
707 | ||
708 | /* | |
709 | * Compute the GMCH and Link ratios. The '3' here is | |
710 | * the number of bytes_per_pixel post-LUT, which we always | |
711 | * set up for 8-bits of R/G/B, or 3 bytes total. | |
712 | */ | |
36e83a18 | 713 | intel_dp_compute_m_n(bpp, lane_count, |
a4fc5ed6 KP |
714 | mode->clock, adjusted_mode->clock, &m_n); |
715 | ||
c619eed4 | 716 | if (HAS_PCH_SPLIT(dev)) { |
9db4a9c7 JB |
717 | I915_WRITE(TRANSDATA_M1(pipe), |
718 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
719 | m_n.gmch_m); | |
720 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); | |
721 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); | |
722 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); | |
a4fc5ed6 | 723 | } else { |
9db4a9c7 JB |
724 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
725 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
726 | m_n.gmch_m); | |
727 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); | |
728 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); | |
729 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); | |
a4fc5ed6 KP |
730 | } |
731 | } | |
732 | ||
733 | static void | |
734 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
735 | struct drm_display_mode *adjusted_mode) | |
736 | { | |
e3421a18 | 737 | struct drm_device *dev = encoder->dev; |
ea5b213a | 738 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4ef69c7a | 739 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
a4fc5ed6 KP |
740 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
741 | ||
e953fd7b CW |
742 | intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
743 | intel_dp->DP |= intel_dp->color_range; | |
9c9e7927 AJ |
744 | |
745 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
ea5b213a | 746 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
9c9e7927 | 747 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
ea5b213a | 748 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
a4fc5ed6 | 749 | |
cfcb0fc9 | 750 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
ea5b213a | 751 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3421a18 | 752 | else |
ea5b213a | 753 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
a4fc5ed6 | 754 | |
ea5b213a | 755 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 756 | case 1: |
ea5b213a | 757 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
758 | break; |
759 | case 2: | |
ea5b213a | 760 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
761 | break; |
762 | case 4: | |
ea5b213a | 763 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
764 | break; |
765 | } | |
ea5b213a CW |
766 | if (intel_dp->has_audio) |
767 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; | |
a4fc5ed6 | 768 | |
ea5b213a CW |
769 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
770 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
771 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
a2cab1b2 | 772 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
a4fc5ed6 KP |
773 | |
774 | /* | |
9962c925 | 775 | * Check for DPCD version > 1.1 and enhanced framing support |
a4fc5ed6 | 776 | */ |
7183dc29 JB |
777 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
778 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { | |
ea5b213a CW |
779 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
780 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
a4fc5ed6 KP |
781 | } |
782 | ||
e3421a18 ZW |
783 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ |
784 | if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) | |
ea5b213a | 785 | intel_dp->DP |= DP_PIPEB_SELECT; |
32f9d658 | 786 | |
895692be | 787 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
32f9d658 | 788 | /* don't miss out required setting for eDP */ |
ea5b213a | 789 | intel_dp->DP |= DP_PLL_ENABLE; |
32f9d658 | 790 | if (adjusted_mode->clock < 200000) |
ea5b213a | 791 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
32f9d658 | 792 | else |
ea5b213a | 793 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
32f9d658 | 794 | } |
a4fc5ed6 KP |
795 | } |
796 | ||
5d613501 JB |
797 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
798 | { | |
799 | struct drm_device *dev = intel_dp->base.base.dev; | |
800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
801 | u32 pp; | |
802 | ||
803 | /* | |
804 | * If the panel wasn't on, make sure there's not a currently | |
805 | * active PP sequence before enabling AUX VDD. | |
806 | */ | |
807 | if (!(I915_READ(PCH_PP_STATUS) & PP_ON)) | |
808 | msleep(dev_priv->panel_t3); | |
809 | ||
810 | pp = I915_READ(PCH_PP_CONTROL); | |
811 | pp |= EDP_FORCE_VDD; | |
812 | I915_WRITE(PCH_PP_CONTROL, pp); | |
813 | POSTING_READ(PCH_PP_CONTROL); | |
814 | } | |
815 | ||
816 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp) | |
817 | { | |
818 | struct drm_device *dev = intel_dp->base.base.dev; | |
819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820 | u32 pp; | |
821 | ||
822 | pp = I915_READ(PCH_PP_CONTROL); | |
823 | pp &= ~EDP_FORCE_VDD; | |
824 | I915_WRITE(PCH_PP_CONTROL, pp); | |
825 | POSTING_READ(PCH_PP_CONTROL); | |
826 | ||
827 | /* Make sure sequencer is idle before allowing subsequent activity */ | |
828 | msleep(dev_priv->panel_t12); | |
829 | } | |
830 | ||
7eaf5547 | 831 | /* Returns true if the panel was already on when called */ |
01cb9ea6 | 832 | static bool ironlake_edp_panel_on (struct intel_dp *intel_dp) |
9934c132 | 833 | { |
01cb9ea6 | 834 | struct drm_device *dev = intel_dp->base.base.dev; |
9934c132 | 835 | struct drm_i915_private *dev_priv = dev->dev_private; |
01cb9ea6 | 836 | u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE; |
9934c132 | 837 | |
913d8d11 | 838 | if (I915_READ(PCH_PP_STATUS) & PP_ON) |
7eaf5547 | 839 | return true; |
9934c132 JB |
840 | |
841 | pp = I915_READ(PCH_PP_CONTROL); | |
37c6c9b0 JB |
842 | |
843 | /* ILK workaround: disable reset around power sequence */ | |
844 | pp &= ~PANEL_POWER_RESET; | |
845 | I915_WRITE(PCH_PP_CONTROL, pp); | |
846 | POSTING_READ(PCH_PP_CONTROL); | |
847 | ||
01cb9ea6 | 848 | pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; |
9934c132 | 849 | I915_WRITE(PCH_PP_CONTROL, pp); |
01cb9ea6 | 850 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 | 851 | |
01cb9ea6 JB |
852 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, |
853 | 5000)) | |
913d8d11 CW |
854 | DRM_ERROR("panel on wait timed out: 0x%08x\n", |
855 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 856 | |
37c6c9b0 | 857 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 858 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 859 | POSTING_READ(PCH_PP_CONTROL); |
7eaf5547 JB |
860 | |
861 | return false; | |
9934c132 JB |
862 | } |
863 | ||
864 | static void ironlake_edp_panel_off (struct drm_device *dev) | |
865 | { | |
866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
01cb9ea6 JB |
867 | u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | |
868 | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK; | |
9934c132 JB |
869 | |
870 | pp = I915_READ(PCH_PP_CONTROL); | |
37c6c9b0 JB |
871 | |
872 | /* ILK workaround: disable reset around power sequence */ | |
873 | pp &= ~PANEL_POWER_RESET; | |
874 | I915_WRITE(PCH_PP_CONTROL, pp); | |
875 | POSTING_READ(PCH_PP_CONTROL); | |
876 | ||
9934c132 JB |
877 | pp &= ~POWER_TARGET_ON; |
878 | I915_WRITE(PCH_PP_CONTROL, pp); | |
01cb9ea6 | 879 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 | 880 | |
01cb9ea6 | 881 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000)) |
913d8d11 CW |
882 | DRM_ERROR("panel off wait timed out: 0x%08x\n", |
883 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 884 | |
3969c9c9 | 885 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 886 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 887 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 JB |
888 | } |
889 | ||
f2b115e6 | 890 | static void ironlake_edp_backlight_on (struct drm_device *dev) |
32f9d658 ZW |
891 | { |
892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
893 | u32 pp; | |
894 | ||
28c97730 | 895 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
896 | /* |
897 | * If we enable the backlight right away following a panel power | |
898 | * on, we may see slight flicker as the panel syncs with the eDP | |
899 | * link. So delay a bit to make sure the image is solid before | |
900 | * allowing it to appear. | |
901 | */ | |
902 | msleep(300); | |
32f9d658 ZW |
903 | pp = I915_READ(PCH_PP_CONTROL); |
904 | pp |= EDP_BLC_ENABLE; | |
905 | I915_WRITE(PCH_PP_CONTROL, pp); | |
906 | } | |
907 | ||
f2b115e6 | 908 | static void ironlake_edp_backlight_off (struct drm_device *dev) |
32f9d658 ZW |
909 | { |
910 | struct drm_i915_private *dev_priv = dev->dev_private; | |
911 | u32 pp; | |
912 | ||
28c97730 | 913 | DRM_DEBUG_KMS("\n"); |
32f9d658 ZW |
914 | pp = I915_READ(PCH_PP_CONTROL); |
915 | pp &= ~EDP_BLC_ENABLE; | |
916 | I915_WRITE(PCH_PP_CONTROL, pp); | |
917 | } | |
a4fc5ed6 | 918 | |
d240f20f JB |
919 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
920 | { | |
921 | struct drm_device *dev = encoder->dev; | |
922 | struct drm_i915_private *dev_priv = dev->dev_private; | |
923 | u32 dpa_ctl; | |
924 | ||
925 | DRM_DEBUG_KMS("\n"); | |
926 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 927 | dpa_ctl |= DP_PLL_ENABLE; |
d240f20f | 928 | I915_WRITE(DP_A, dpa_ctl); |
298b0b39 JB |
929 | POSTING_READ(DP_A); |
930 | udelay(200); | |
d240f20f JB |
931 | } |
932 | ||
933 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) | |
934 | { | |
935 | struct drm_device *dev = encoder->dev; | |
936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
937 | u32 dpa_ctl; | |
938 | ||
939 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 940 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 941 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 942 | POSTING_READ(DP_A); |
d240f20f JB |
943 | udelay(200); |
944 | } | |
945 | ||
c7ad3810 JB |
946 | /* If the sink supports it, try to set the power state appropriately */ |
947 | static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) | |
948 | { | |
949 | int ret, i; | |
950 | ||
951 | /* Should have a valid DPCD by this point */ | |
952 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
953 | return; | |
954 | ||
955 | if (mode != DRM_MODE_DPMS_ON) { | |
956 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, | |
957 | DP_SET_POWER_D3); | |
958 | if (ret != 1) | |
959 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
960 | } else { | |
961 | /* | |
962 | * When turning on, we need to retry for 1ms to give the sink | |
963 | * time to wake up. | |
964 | */ | |
965 | for (i = 0; i < 3; i++) { | |
966 | ret = intel_dp_aux_native_write_1(intel_dp, | |
967 | DP_SET_POWER, | |
968 | DP_SET_POWER_D0); | |
969 | if (ret == 1) | |
970 | break; | |
971 | msleep(1); | |
972 | } | |
973 | } | |
974 | } | |
975 | ||
d240f20f JB |
976 | static void intel_dp_prepare(struct drm_encoder *encoder) |
977 | { | |
978 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
979 | struct drm_device *dev = encoder->dev; | |
d240f20f | 980 | |
c7ad3810 JB |
981 | /* Wake up the sink first */ |
982 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
983 | ||
4d926461 | 984 | if (is_edp(intel_dp)) { |
d240f20f | 985 | ironlake_edp_backlight_off(dev); |
5d613501 | 986 | ironlake_edp_panel_off(dev); |
01cb9ea6 JB |
987 | if (!is_pch_edp(intel_dp)) |
988 | ironlake_edp_pll_on(encoder); | |
989 | else | |
990 | ironlake_edp_pll_off(encoder); | |
d240f20f | 991 | } |
736085bc | 992 | intel_dp_link_down(intel_dp); |
d240f20f JB |
993 | } |
994 | ||
995 | static void intel_dp_commit(struct drm_encoder *encoder) | |
996 | { | |
997 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
998 | struct drm_device *dev = encoder->dev; | |
d240f20f | 999 | |
5d613501 JB |
1000 | if (is_edp(intel_dp)) |
1001 | ironlake_edp_panel_vdd_on(intel_dp); | |
1002 | ||
33a34e4e JB |
1003 | intel_dp_start_link_train(intel_dp); |
1004 | ||
5d613501 | 1005 | if (is_edp(intel_dp)) { |
01cb9ea6 | 1006 | ironlake_edp_panel_on(intel_dp); |
5d613501 JB |
1007 | ironlake_edp_panel_vdd_off(intel_dp); |
1008 | } | |
33a34e4e JB |
1009 | |
1010 | intel_dp_complete_link_train(intel_dp); | |
1011 | ||
4d926461 | 1012 | if (is_edp(intel_dp)) |
d240f20f JB |
1013 | ironlake_edp_backlight_on(dev); |
1014 | } | |
1015 | ||
a4fc5ed6 KP |
1016 | static void |
1017 | intel_dp_dpms(struct drm_encoder *encoder, int mode) | |
1018 | { | |
ea5b213a | 1019 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
55f78c43 | 1020 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 | 1021 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1022 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
a4fc5ed6 KP |
1023 | |
1024 | if (mode != DRM_MODE_DPMS_ON) { | |
01cb9ea6 | 1025 | if (is_edp(intel_dp)) |
7643a7fa | 1026 | ironlake_edp_backlight_off(dev); |
c7ad3810 | 1027 | intel_dp_sink_dpms(intel_dp, mode); |
736085bc | 1028 | intel_dp_link_down(intel_dp); |
4d926461 | 1029 | if (is_edp(intel_dp)) |
01cb9ea6 JB |
1030 | ironlake_edp_panel_off(dev); |
1031 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) | |
d240f20f | 1032 | ironlake_edp_pll_off(encoder); |
a4fc5ed6 | 1033 | } else { |
736085bc | 1034 | if (is_edp(intel_dp)) |
5d613501 | 1035 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1036 | intel_dp_sink_dpms(intel_dp, mode); |
32f9d658 | 1037 | if (!(dp_reg & DP_PORT_EN)) { |
01cb9ea6 | 1038 | intel_dp_start_link_train(intel_dp); |
5d613501 JB |
1039 | if (is_edp(intel_dp)) { |
1040 | ironlake_edp_panel_on(intel_dp); | |
1041 | ironlake_edp_panel_vdd_off(intel_dp); | |
1042 | } | |
33a34e4e | 1043 | intel_dp_complete_link_train(intel_dp); |
32f9d658 | 1044 | } |
736085bc JB |
1045 | if (is_edp(intel_dp)) |
1046 | ironlake_edp_backlight_on(dev); | |
a4fc5ed6 KP |
1047 | } |
1048 | } | |
1049 | ||
1050 | /* | |
df0c237d JB |
1051 | * Native read with retry for link status and receiver capability reads for |
1052 | * cases where the sink may still be asleep. | |
a4fc5ed6 KP |
1053 | */ |
1054 | static bool | |
df0c237d JB |
1055 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
1056 | uint8_t *recv, int recv_bytes) | |
a4fc5ed6 | 1057 | { |
61da5fab JB |
1058 | int ret, i; |
1059 | ||
df0c237d JB |
1060 | /* |
1061 | * Sinks are *supposed* to come up within 1ms from an off state, | |
1062 | * but we're also supposed to retry 3 times per the spec. | |
1063 | */ | |
61da5fab | 1064 | for (i = 0; i < 3; i++) { |
df0c237d JB |
1065 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
1066 | recv_bytes); | |
1067 | if (ret == recv_bytes) | |
61da5fab JB |
1068 | return true; |
1069 | msleep(1); | |
1070 | } | |
a4fc5ed6 | 1071 | |
61da5fab | 1072 | return false; |
a4fc5ed6 KP |
1073 | } |
1074 | ||
df0c237d JB |
1075 | /* |
1076 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
1077 | * link status information | |
1078 | */ | |
1079 | static bool | |
1080 | intel_dp_get_link_status(struct intel_dp *intel_dp) | |
1081 | { | |
1082 | return intel_dp_aux_native_read_retry(intel_dp, | |
1083 | DP_LANE0_1_STATUS, | |
1084 | intel_dp->link_status, | |
1085 | DP_LINK_STATUS_SIZE); | |
1086 | } | |
1087 | ||
a4fc5ed6 KP |
1088 | static uint8_t |
1089 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1090 | int r) | |
1091 | { | |
1092 | return link_status[r - DP_LANE0_1_STATUS]; | |
1093 | } | |
1094 | ||
a4fc5ed6 KP |
1095 | static uint8_t |
1096 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1097 | int lane) | |
1098 | { | |
1099 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
1100 | int s = ((lane & 1) ? | |
1101 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
1102 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
1103 | uint8_t l = intel_dp_link_status(link_status, i); | |
1104 | ||
1105 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
1106 | } | |
1107 | ||
1108 | static uint8_t | |
1109 | intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1110 | int lane) | |
1111 | { | |
1112 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
1113 | int s = ((lane & 1) ? | |
1114 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
1115 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
1116 | uint8_t l = intel_dp_link_status(link_status, i); | |
1117 | ||
1118 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
1119 | } | |
1120 | ||
1121 | ||
1122 | #if 0 | |
1123 | static char *voltage_names[] = { | |
1124 | "0.4V", "0.6V", "0.8V", "1.2V" | |
1125 | }; | |
1126 | static char *pre_emph_names[] = { | |
1127 | "0dB", "3.5dB", "6dB", "9.5dB" | |
1128 | }; | |
1129 | static char *link_train_names[] = { | |
1130 | "pattern 1", "pattern 2", "idle", "off" | |
1131 | }; | |
1132 | #endif | |
1133 | ||
1134 | /* | |
1135 | * These are source-specific values; current Intel hardware supports | |
1136 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1137 | */ | |
1138 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 | |
1139 | ||
1140 | static uint8_t | |
1141 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) | |
1142 | { | |
1143 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1144 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1145 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1146 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1147 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1148 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1149 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1150 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1151 | default: | |
1152 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1153 | } | |
1154 | } | |
1155 | ||
1156 | static void | |
33a34e4e | 1157 | intel_get_adjust_train(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1158 | { |
1159 | uint8_t v = 0; | |
1160 | uint8_t p = 0; | |
1161 | int lane; | |
1162 | ||
33a34e4e JB |
1163 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1164 | uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane); | |
1165 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1166 | |
1167 | if (this_v > v) | |
1168 | v = this_v; | |
1169 | if (this_p > p) | |
1170 | p = this_p; | |
1171 | } | |
1172 | ||
1173 | if (v >= I830_DP_VOLTAGE_MAX) | |
1174 | v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; | |
1175 | ||
1176 | if (p >= intel_dp_pre_emphasis_max(v)) | |
1177 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
1178 | ||
1179 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 1180 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
1181 | } |
1182 | ||
1183 | static uint32_t | |
3cf2efb1 | 1184 | intel_dp_signal_levels(uint8_t train_set, int lane_count) |
a4fc5ed6 | 1185 | { |
3cf2efb1 | 1186 | uint32_t signal_levels = 0; |
a4fc5ed6 | 1187 | |
3cf2efb1 | 1188 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
1189 | case DP_TRAIN_VOLTAGE_SWING_400: |
1190 | default: | |
1191 | signal_levels |= DP_VOLTAGE_0_4; | |
1192 | break; | |
1193 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1194 | signal_levels |= DP_VOLTAGE_0_6; | |
1195 | break; | |
1196 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1197 | signal_levels |= DP_VOLTAGE_0_8; | |
1198 | break; | |
1199 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1200 | signal_levels |= DP_VOLTAGE_1_2; | |
1201 | break; | |
1202 | } | |
3cf2efb1 | 1203 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
1204 | case DP_TRAIN_PRE_EMPHASIS_0: |
1205 | default: | |
1206 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1207 | break; | |
1208 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1209 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1210 | break; | |
1211 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1212 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1213 | break; | |
1214 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1215 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1216 | break; | |
1217 | } | |
1218 | return signal_levels; | |
1219 | } | |
1220 | ||
e3421a18 ZW |
1221 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1222 | static uint32_t | |
1223 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1224 | { | |
3c5a62b5 YL |
1225 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1226 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1227 | switch (signal_levels) { | |
e3421a18 | 1228 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1229 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
1230 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
1231 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1232 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 1233 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
1234 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
1235 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 1236 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
1237 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
1238 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 1239 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1240 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
1241 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 1242 | default: |
3c5a62b5 YL |
1243 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
1244 | "0x%x\n", signal_levels); | |
1245 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
1246 | } |
1247 | } | |
1248 | ||
a4fc5ed6 KP |
1249 | static uint8_t |
1250 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1251 | int lane) | |
1252 | { | |
1253 | int i = DP_LANE0_1_STATUS + (lane >> 1); | |
1254 | int s = (lane & 1) * 4; | |
1255 | uint8_t l = intel_dp_link_status(link_status, i); | |
1256 | ||
1257 | return (l >> s) & 0xf; | |
1258 | } | |
1259 | ||
1260 | /* Check for clock recovery is done on all channels */ | |
1261 | static bool | |
1262 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1263 | { | |
1264 | int lane; | |
1265 | uint8_t lane_status; | |
1266 | ||
1267 | for (lane = 0; lane < lane_count; lane++) { | |
1268 | lane_status = intel_get_lane_status(link_status, lane); | |
1269 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
1270 | return false; | |
1271 | } | |
1272 | return true; | |
1273 | } | |
1274 | ||
1275 | /* Check to see if channel eq is done on all channels */ | |
1276 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ | |
1277 | DP_LANE_CHANNEL_EQ_DONE|\ | |
1278 | DP_LANE_SYMBOL_LOCKED) | |
1279 | static bool | |
33a34e4e | 1280 | intel_channel_eq_ok(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1281 | { |
1282 | uint8_t lane_align; | |
1283 | uint8_t lane_status; | |
1284 | int lane; | |
1285 | ||
33a34e4e | 1286 | lane_align = intel_dp_link_status(intel_dp->link_status, |
a4fc5ed6 KP |
1287 | DP_LANE_ALIGN_STATUS_UPDATED); |
1288 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
1289 | return false; | |
33a34e4e JB |
1290 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1291 | lane_status = intel_get_lane_status(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1292 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
1293 | return false; | |
1294 | } | |
1295 | return true; | |
1296 | } | |
1297 | ||
1298 | static bool | |
ea5b213a | 1299 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 | 1300 | uint32_t dp_reg_value, |
58e10eb9 | 1301 | uint8_t dp_train_pat) |
a4fc5ed6 | 1302 | { |
4ef69c7a | 1303 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1304 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1305 | int ret; |
1306 | ||
ea5b213a CW |
1307 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1308 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1309 | |
ea5b213a | 1310 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1311 | DP_TRAINING_PATTERN_SET, |
1312 | dp_train_pat); | |
1313 | ||
ea5b213a | 1314 | ret = intel_dp_aux_native_write(intel_dp, |
58e10eb9 CW |
1315 | DP_TRAINING_LANE0_SET, |
1316 | intel_dp->train_set, 4); | |
a4fc5ed6 KP |
1317 | if (ret != 4) |
1318 | return false; | |
1319 | ||
1320 | return true; | |
1321 | } | |
1322 | ||
33a34e4e | 1323 | /* Enable corresponding port and start training pattern 1 */ |
a4fc5ed6 | 1324 | static void |
33a34e4e | 1325 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1326 | { |
4ef69c7a | 1327 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1328 | struct drm_i915_private *dev_priv = dev->dev_private; |
58e10eb9 | 1329 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); |
a4fc5ed6 KP |
1330 | int i; |
1331 | uint8_t voltage; | |
1332 | bool clock_recovery = false; | |
a4fc5ed6 | 1333 | int tries; |
e3421a18 | 1334 | u32 reg; |
ea5b213a | 1335 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1336 | |
e8519464 AJ |
1337 | /* |
1338 | * On CPT we have to enable the port in training pattern 1, which | |
1339 | * will happen below in intel_dp_set_link_train. Otherwise, enable | |
1340 | * the port and wait for it to become active. | |
1341 | */ | |
1342 | if (!HAS_PCH_CPT(dev)) { | |
1343 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
1344 | POSTING_READ(intel_dp->output_reg); | |
1345 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1346 | } | |
a4fc5ed6 | 1347 | |
3cf2efb1 CW |
1348 | /* Write the link configuration data */ |
1349 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, | |
1350 | intel_dp->link_configuration, | |
1351 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
1352 | |
1353 | DP |= DP_PORT_EN; | |
cfcb0fc9 | 1354 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1355 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1356 | else | |
1357 | DP &= ~DP_LINK_TRAIN_MASK; | |
33a34e4e | 1358 | memset(intel_dp->train_set, 0, 4); |
a4fc5ed6 KP |
1359 | voltage = 0xff; |
1360 | tries = 0; | |
1361 | clock_recovery = false; | |
1362 | for (;;) { | |
33a34e4e | 1363 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 | 1364 | uint32_t signal_levels; |
cfcb0fc9 | 1365 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
33a34e4e | 1366 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1367 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1368 | } else { | |
3cf2efb1 | 1369 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1370 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1371 | } | |
a4fc5ed6 | 1372 | |
cfcb0fc9 | 1373 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1374 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
1375 | else | |
1376 | reg = DP | DP_LINK_TRAIN_PAT_1; | |
1377 | ||
ea5b213a | 1378 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1379 | DP_TRAINING_PATTERN_1 | |
1380 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 | 1381 | break; |
a4fc5ed6 KP |
1382 | /* Set training pattern 1 */ |
1383 | ||
3cf2efb1 CW |
1384 | udelay(100); |
1385 | if (!intel_dp_get_link_status(intel_dp)) | |
a4fc5ed6 | 1386 | break; |
a4fc5ed6 | 1387 | |
3cf2efb1 CW |
1388 | if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { |
1389 | clock_recovery = true; | |
1390 | break; | |
1391 | } | |
1392 | ||
1393 | /* Check to see if we've tried the max voltage */ | |
1394 | for (i = 0; i < intel_dp->lane_count; i++) | |
1395 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 1396 | break; |
3cf2efb1 CW |
1397 | if (i == intel_dp->lane_count) |
1398 | break; | |
a4fc5ed6 | 1399 | |
3cf2efb1 CW |
1400 | /* Check to see if we've tried the same voltage 5 times */ |
1401 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { | |
1402 | ++tries; | |
1403 | if (tries == 5) | |
a4fc5ed6 | 1404 | break; |
3cf2efb1 CW |
1405 | } else |
1406 | tries = 0; | |
1407 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 1408 | |
3cf2efb1 CW |
1409 | /* Compute new intel_dp->train_set as requested by target */ |
1410 | intel_get_adjust_train(intel_dp); | |
a4fc5ed6 KP |
1411 | } |
1412 | ||
33a34e4e JB |
1413 | intel_dp->DP = DP; |
1414 | } | |
1415 | ||
1416 | static void | |
1417 | intel_dp_complete_link_train(struct intel_dp *intel_dp) | |
1418 | { | |
4ef69c7a | 1419 | struct drm_device *dev = intel_dp->base.base.dev; |
33a34e4e JB |
1420 | struct drm_i915_private *dev_priv = dev->dev_private; |
1421 | bool channel_eq = false; | |
37f80975 | 1422 | int tries, cr_tries; |
33a34e4e JB |
1423 | u32 reg; |
1424 | uint32_t DP = intel_dp->DP; | |
1425 | ||
a4fc5ed6 KP |
1426 | /* channel equalization */ |
1427 | tries = 0; | |
37f80975 | 1428 | cr_tries = 0; |
a4fc5ed6 KP |
1429 | channel_eq = false; |
1430 | for (;;) { | |
33a34e4e | 1431 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 ZW |
1432 | uint32_t signal_levels; |
1433 | ||
37f80975 JB |
1434 | if (cr_tries > 5) { |
1435 | DRM_ERROR("failed to train DP, aborting\n"); | |
1436 | intel_dp_link_down(intel_dp); | |
1437 | break; | |
1438 | } | |
1439 | ||
cfcb0fc9 | 1440 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
33a34e4e | 1441 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1442 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1443 | } else { | |
3cf2efb1 | 1444 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1445 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1446 | } | |
1447 | ||
cfcb0fc9 | 1448 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1449 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
1450 | else | |
1451 | reg = DP | DP_LINK_TRAIN_PAT_2; | |
a4fc5ed6 KP |
1452 | |
1453 | /* channel eq pattern */ | |
ea5b213a | 1454 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1455 | DP_TRAINING_PATTERN_2 | |
1456 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 KP |
1457 | break; |
1458 | ||
3cf2efb1 CW |
1459 | udelay(400); |
1460 | if (!intel_dp_get_link_status(intel_dp)) | |
a4fc5ed6 | 1461 | break; |
a4fc5ed6 | 1462 | |
37f80975 JB |
1463 | /* Make sure clock is still ok */ |
1464 | if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { | |
1465 | intel_dp_start_link_train(intel_dp); | |
1466 | cr_tries++; | |
1467 | continue; | |
1468 | } | |
1469 | ||
3cf2efb1 CW |
1470 | if (intel_channel_eq_ok(intel_dp)) { |
1471 | channel_eq = true; | |
1472 | break; | |
1473 | } | |
a4fc5ed6 | 1474 | |
37f80975 JB |
1475 | /* Try 5 times, then try clock recovery if that fails */ |
1476 | if (tries > 5) { | |
1477 | intel_dp_link_down(intel_dp); | |
1478 | intel_dp_start_link_train(intel_dp); | |
1479 | tries = 0; | |
1480 | cr_tries++; | |
1481 | continue; | |
1482 | } | |
a4fc5ed6 | 1483 | |
3cf2efb1 CW |
1484 | /* Compute new intel_dp->train_set as requested by target */ |
1485 | intel_get_adjust_train(intel_dp); | |
1486 | ++tries; | |
869184a6 | 1487 | } |
3cf2efb1 | 1488 | |
cfcb0fc9 | 1489 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1490 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
1491 | else | |
1492 | reg = DP | DP_LINK_TRAIN_OFF; | |
1493 | ||
ea5b213a CW |
1494 | I915_WRITE(intel_dp->output_reg, reg); |
1495 | POSTING_READ(intel_dp->output_reg); | |
1496 | intel_dp_aux_native_write_1(intel_dp, | |
a4fc5ed6 KP |
1497 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
1498 | } | |
1499 | ||
1500 | static void | |
ea5b213a | 1501 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 1502 | { |
4ef69c7a | 1503 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1504 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1505 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1506 | |
1b39d6f3 CW |
1507 | if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) |
1508 | return; | |
1509 | ||
28c97730 | 1510 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1511 | |
cfcb0fc9 | 1512 | if (is_edp(intel_dp)) { |
32f9d658 | 1513 | DP &= ~DP_PLL_ENABLE; |
ea5b213a CW |
1514 | I915_WRITE(intel_dp->output_reg, DP); |
1515 | POSTING_READ(intel_dp->output_reg); | |
32f9d658 ZW |
1516 | udelay(100); |
1517 | } | |
1518 | ||
cfcb0fc9 | 1519 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) { |
e3421a18 | 1520 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 1521 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
1522 | } else { |
1523 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 1524 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 1525 | } |
fe255d00 | 1526 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 1527 | |
fe255d00 | 1528 | msleep(17); |
5eb08b69 | 1529 | |
cfcb0fc9 | 1530 | if (is_edp(intel_dp)) |
32f9d658 | 1531 | DP |= DP_LINK_TRAIN_OFF; |
5bddd17f | 1532 | |
1b39d6f3 CW |
1533 | if (!HAS_PCH_CPT(dev) && |
1534 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { | |
31acbcc4 CW |
1535 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
1536 | ||
5bddd17f EA |
1537 | /* Hardware workaround: leaving our transcoder select |
1538 | * set to transcoder B while it's off will prevent the | |
1539 | * corresponding HDMI output on transcoder A. | |
1540 | * | |
1541 | * Combine this with another hardware workaround: | |
1542 | * transcoder select bit can only be cleared while the | |
1543 | * port is enabled. | |
1544 | */ | |
1545 | DP &= ~DP_PIPEB_SELECT; | |
1546 | I915_WRITE(intel_dp->output_reg, DP); | |
1547 | ||
1548 | /* Changes to enable or select take place the vblank | |
1549 | * after being written. | |
1550 | */ | |
31acbcc4 CW |
1551 | if (crtc == NULL) { |
1552 | /* We can arrive here never having been attached | |
1553 | * to a CRTC, for instance, due to inheriting | |
1554 | * random state from the BIOS. | |
1555 | * | |
1556 | * If the pipe is not running, play safe and | |
1557 | * wait for the clocks to stabilise before | |
1558 | * continuing. | |
1559 | */ | |
1560 | POSTING_READ(intel_dp->output_reg); | |
1561 | msleep(50); | |
1562 | } else | |
1563 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
5bddd17f EA |
1564 | } |
1565 | ||
ea5b213a CW |
1566 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
1567 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 KP |
1568 | } |
1569 | ||
26d61aad KP |
1570 | static bool |
1571 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 1572 | { |
92fd8fd1 KP |
1573 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
1574 | sizeof (intel_dp->dpcd)) && | |
1575 | (intel_dp->dpcd[DP_DPCD_REV] != 0)) { | |
26d61aad | 1576 | return true; |
92fd8fd1 KP |
1577 | } |
1578 | ||
26d61aad | 1579 | return false; |
92fd8fd1 KP |
1580 | } |
1581 | ||
a4fc5ed6 KP |
1582 | /* |
1583 | * According to DP spec | |
1584 | * 5.1.2: | |
1585 | * 1. Read DPCD | |
1586 | * 2. Configure link according to Receiver Capabilities | |
1587 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
1588 | * 4. Check link status on receipt of hot-plug interrupt | |
1589 | */ | |
1590 | ||
1591 | static void | |
ea5b213a | 1592 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1593 | { |
4ef69c7a | 1594 | if (!intel_dp->base.base.crtc) |
a4fc5ed6 KP |
1595 | return; |
1596 | ||
92fd8fd1 | 1597 | /* Try to read receiver status if the link appears to be up */ |
33a34e4e | 1598 | if (!intel_dp_get_link_status(intel_dp)) { |
ea5b213a | 1599 | intel_dp_link_down(intel_dp); |
a4fc5ed6 KP |
1600 | return; |
1601 | } | |
1602 | ||
92fd8fd1 | 1603 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 1604 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
1605 | intel_dp_link_down(intel_dp); |
1606 | return; | |
1607 | } | |
1608 | ||
33a34e4e | 1609 | if (!intel_channel_eq_ok(intel_dp)) { |
92fd8fd1 KP |
1610 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
1611 | drm_get_encoder_name(&intel_dp->base.base)); | |
33a34e4e JB |
1612 | intel_dp_start_link_train(intel_dp); |
1613 | intel_dp_complete_link_train(intel_dp); | |
1614 | } | |
a4fc5ed6 | 1615 | } |
a4fc5ed6 | 1616 | |
26d61aad KP |
1617 | static enum drm_connector_status |
1618 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) | |
1619 | { | |
1620 | if (intel_dp_get_dpcd(intel_dp)) | |
1621 | return connector_status_connected; | |
1622 | return connector_status_disconnected; | |
1623 | } | |
1624 | ||
5eb08b69 | 1625 | static enum drm_connector_status |
a9756bb5 | 1626 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 1627 | { |
5eb08b69 ZW |
1628 | enum drm_connector_status status; |
1629 | ||
fe16d949 CW |
1630 | /* Can't disconnect eDP, but you can close the lid... */ |
1631 | if (is_edp(intel_dp)) { | |
1632 | status = intel_panel_detect(intel_dp->base.base.dev); | |
1633 | if (status == connector_status_unknown) | |
1634 | status = connector_status_connected; | |
1635 | return status; | |
1636 | } | |
01cb9ea6 | 1637 | |
26d61aad | 1638 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
1639 | } |
1640 | ||
a4fc5ed6 | 1641 | static enum drm_connector_status |
a9756bb5 | 1642 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 1643 | { |
4ef69c7a | 1644 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1645 | struct drm_i915_private *dev_priv = dev->dev_private; |
a9756bb5 | 1646 | uint32_t temp, bit; |
5eb08b69 | 1647 | |
ea5b213a | 1648 | switch (intel_dp->output_reg) { |
a4fc5ed6 KP |
1649 | case DP_B: |
1650 | bit = DPB_HOTPLUG_INT_STATUS; | |
1651 | break; | |
1652 | case DP_C: | |
1653 | bit = DPC_HOTPLUG_INT_STATUS; | |
1654 | break; | |
1655 | case DP_D: | |
1656 | bit = DPD_HOTPLUG_INT_STATUS; | |
1657 | break; | |
1658 | default: | |
1659 | return connector_status_unknown; | |
1660 | } | |
1661 | ||
1662 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
1663 | ||
1664 | if ((temp & bit) == 0) | |
1665 | return connector_status_disconnected; | |
1666 | ||
26d61aad | 1667 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
1668 | } |
1669 | ||
1670 | /** | |
1671 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. | |
1672 | * | |
1673 | * \return true if DP port is connected. | |
1674 | * \return false if DP port is disconnected. | |
1675 | */ | |
1676 | static enum drm_connector_status | |
1677 | intel_dp_detect(struct drm_connector *connector, bool force) | |
1678 | { | |
1679 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1680 | struct drm_device *dev = intel_dp->base.base.dev; | |
1681 | enum drm_connector_status status; | |
1682 | struct edid *edid = NULL; | |
1683 | ||
1684 | intel_dp->has_audio = false; | |
97cdd710 | 1685 | memset(intel_dp->dpcd, 0, sizeof(intel_dp->dpcd)); |
a9756bb5 ZW |
1686 | |
1687 | if (HAS_PCH_SPLIT(dev)) | |
1688 | status = ironlake_dp_detect(intel_dp); | |
1689 | else | |
1690 | status = g4x_dp_detect(intel_dp); | |
1b9be9d0 | 1691 | |
ac66ae83 AJ |
1692 | DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", |
1693 | intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], | |
1694 | intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], | |
1695 | intel_dp->dpcd[6], intel_dp->dpcd[7]); | |
1b9be9d0 | 1696 | |
a9756bb5 ZW |
1697 | if (status != connector_status_connected) |
1698 | return status; | |
1699 | ||
f684960e CW |
1700 | if (intel_dp->force_audio) { |
1701 | intel_dp->has_audio = intel_dp->force_audio > 0; | |
1702 | } else { | |
1703 | edid = drm_get_edid(connector, &intel_dp->adapter); | |
1704 | if (edid) { | |
1705 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
1706 | connector->display_info.raw_edid = NULL; | |
1707 | kfree(edid); | |
1708 | } | |
a9756bb5 ZW |
1709 | } |
1710 | ||
1711 | return connector_status_connected; | |
a4fc5ed6 KP |
1712 | } |
1713 | ||
1714 | static int intel_dp_get_modes(struct drm_connector *connector) | |
1715 | { | |
df0e9248 | 1716 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4ef69c7a | 1717 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1718 | struct drm_i915_private *dev_priv = dev->dev_private; |
1719 | int ret; | |
a4fc5ed6 KP |
1720 | |
1721 | /* We should parse the EDID data and find out if it has an audio sink | |
1722 | */ | |
1723 | ||
f899fc64 | 1724 | ret = intel_ddc_get_modes(connector, &intel_dp->adapter); |
b9efc480 | 1725 | if (ret) { |
4d926461 | 1726 | if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) { |
b9efc480 ZY |
1727 | struct drm_display_mode *newmode; |
1728 | list_for_each_entry(newmode, &connector->probed_modes, | |
1729 | head) { | |
1730 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
1731 | dev_priv->panel_fixed_mode = | |
1732 | drm_mode_duplicate(dev, newmode); | |
1733 | break; | |
1734 | } | |
1735 | } | |
1736 | } | |
1737 | ||
32f9d658 | 1738 | return ret; |
b9efc480 | 1739 | } |
32f9d658 ZW |
1740 | |
1741 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ | |
4d926461 | 1742 | if (is_edp(intel_dp)) { |
32f9d658 ZW |
1743 | if (dev_priv->panel_fixed_mode != NULL) { |
1744 | struct drm_display_mode *mode; | |
1745 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); | |
1746 | drm_mode_probed_add(connector, mode); | |
1747 | return 1; | |
1748 | } | |
1749 | } | |
1750 | return 0; | |
a4fc5ed6 KP |
1751 | } |
1752 | ||
1aad7ac0 CW |
1753 | static bool |
1754 | intel_dp_detect_audio(struct drm_connector *connector) | |
1755 | { | |
1756 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1757 | struct edid *edid; | |
1758 | bool has_audio = false; | |
1759 | ||
1760 | edid = drm_get_edid(connector, &intel_dp->adapter); | |
1761 | if (edid) { | |
1762 | has_audio = drm_detect_monitor_audio(edid); | |
1763 | ||
1764 | connector->display_info.raw_edid = NULL; | |
1765 | kfree(edid); | |
1766 | } | |
1767 | ||
1768 | return has_audio; | |
1769 | } | |
1770 | ||
f684960e CW |
1771 | static int |
1772 | intel_dp_set_property(struct drm_connector *connector, | |
1773 | struct drm_property *property, | |
1774 | uint64_t val) | |
1775 | { | |
e953fd7b | 1776 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
f684960e CW |
1777 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
1778 | int ret; | |
1779 | ||
1780 | ret = drm_connector_property_set_value(connector, property, val); | |
1781 | if (ret) | |
1782 | return ret; | |
1783 | ||
3f43c48d | 1784 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
1785 | int i = val; |
1786 | bool has_audio; | |
1787 | ||
1788 | if (i == intel_dp->force_audio) | |
f684960e CW |
1789 | return 0; |
1790 | ||
1aad7ac0 | 1791 | intel_dp->force_audio = i; |
f684960e | 1792 | |
1aad7ac0 CW |
1793 | if (i == 0) |
1794 | has_audio = intel_dp_detect_audio(connector); | |
1795 | else | |
1796 | has_audio = i > 0; | |
1797 | ||
1798 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
1799 | return 0; |
1800 | ||
1aad7ac0 | 1801 | intel_dp->has_audio = has_audio; |
f684960e CW |
1802 | goto done; |
1803 | } | |
1804 | ||
e953fd7b CW |
1805 | if (property == dev_priv->broadcast_rgb_property) { |
1806 | if (val == !!intel_dp->color_range) | |
1807 | return 0; | |
1808 | ||
1809 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; | |
1810 | goto done; | |
1811 | } | |
1812 | ||
f684960e CW |
1813 | return -EINVAL; |
1814 | ||
1815 | done: | |
1816 | if (intel_dp->base.base.crtc) { | |
1817 | struct drm_crtc *crtc = intel_dp->base.base.crtc; | |
1818 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
1819 | crtc->x, crtc->y, | |
1820 | crtc->fb); | |
1821 | } | |
1822 | ||
1823 | return 0; | |
1824 | } | |
1825 | ||
a4fc5ed6 KP |
1826 | static void |
1827 | intel_dp_destroy (struct drm_connector *connector) | |
1828 | { | |
a4fc5ed6 KP |
1829 | drm_sysfs_connector_remove(connector); |
1830 | drm_connector_cleanup(connector); | |
55f78c43 | 1831 | kfree(connector); |
a4fc5ed6 KP |
1832 | } |
1833 | ||
24d05927 DV |
1834 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
1835 | { | |
1836 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1837 | ||
1838 | i2c_del_adapter(&intel_dp->adapter); | |
1839 | drm_encoder_cleanup(encoder); | |
1840 | kfree(intel_dp); | |
1841 | } | |
1842 | ||
a4fc5ed6 KP |
1843 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
1844 | .dpms = intel_dp_dpms, | |
1845 | .mode_fixup = intel_dp_mode_fixup, | |
d240f20f | 1846 | .prepare = intel_dp_prepare, |
a4fc5ed6 | 1847 | .mode_set = intel_dp_mode_set, |
d240f20f | 1848 | .commit = intel_dp_commit, |
a4fc5ed6 KP |
1849 | }; |
1850 | ||
1851 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
1852 | .dpms = drm_helper_connector_dpms, | |
a4fc5ed6 KP |
1853 | .detect = intel_dp_detect, |
1854 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 1855 | .set_property = intel_dp_set_property, |
a4fc5ed6 KP |
1856 | .destroy = intel_dp_destroy, |
1857 | }; | |
1858 | ||
1859 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
1860 | .get_modes = intel_dp_get_modes, | |
1861 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 1862 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
1863 | }; |
1864 | ||
a4fc5ed6 | 1865 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 1866 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
1867 | }; |
1868 | ||
995b6762 | 1869 | static void |
21d40d37 | 1870 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 1871 | { |
ea5b213a | 1872 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
c8110e52 | 1873 | |
885a5014 | 1874 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 1875 | } |
6207937d | 1876 | |
e3421a18 ZW |
1877 | /* Return which DP Port should be selected for Transcoder DP control */ |
1878 | int | |
1879 | intel_trans_dp_port_sel (struct drm_crtc *crtc) | |
1880 | { | |
1881 | struct drm_device *dev = crtc->dev; | |
1882 | struct drm_mode_config *mode_config = &dev->mode_config; | |
1883 | struct drm_encoder *encoder; | |
e3421a18 ZW |
1884 | |
1885 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a CW |
1886 | struct intel_dp *intel_dp; |
1887 | ||
d8201ab6 | 1888 | if (encoder->crtc != crtc) |
e3421a18 ZW |
1889 | continue; |
1890 | ||
ea5b213a CW |
1891 | intel_dp = enc_to_intel_dp(encoder); |
1892 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) | |
1893 | return intel_dp->output_reg; | |
e3421a18 | 1894 | } |
ea5b213a | 1895 | |
e3421a18 ZW |
1896 | return -1; |
1897 | } | |
1898 | ||
36e83a18 | 1899 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 1900 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
1901 | { |
1902 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1903 | struct child_device_config *p_child; | |
1904 | int i; | |
1905 | ||
1906 | if (!dev_priv->child_dev_num) | |
1907 | return false; | |
1908 | ||
1909 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
1910 | p_child = dev_priv->child_dev + i; | |
1911 | ||
1912 | if (p_child->dvo_port == PORT_IDPD && | |
1913 | p_child->device_type == DEVICE_TYPE_eDP) | |
1914 | return true; | |
1915 | } | |
1916 | return false; | |
1917 | } | |
1918 | ||
f684960e CW |
1919 | static void |
1920 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
1921 | { | |
3f43c48d | 1922 | intel_attach_force_audio_property(connector); |
e953fd7b | 1923 | intel_attach_broadcast_rgb_property(connector); |
f684960e CW |
1924 | } |
1925 | ||
a4fc5ed6 KP |
1926 | void |
1927 | intel_dp_init(struct drm_device *dev, int output_reg) | |
1928 | { | |
1929 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1930 | struct drm_connector *connector; | |
ea5b213a | 1931 | struct intel_dp *intel_dp; |
21d40d37 | 1932 | struct intel_encoder *intel_encoder; |
55f78c43 | 1933 | struct intel_connector *intel_connector; |
5eb08b69 | 1934 | const char *name = NULL; |
b329530c | 1935 | int type; |
a4fc5ed6 | 1936 | |
ea5b213a CW |
1937 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
1938 | if (!intel_dp) | |
a4fc5ed6 KP |
1939 | return; |
1940 | ||
3d3dc149 | 1941 | intel_dp->output_reg = output_reg; |
3d3dc149 | 1942 | |
55f78c43 ZW |
1943 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
1944 | if (!intel_connector) { | |
ea5b213a | 1945 | kfree(intel_dp); |
55f78c43 ZW |
1946 | return; |
1947 | } | |
ea5b213a | 1948 | intel_encoder = &intel_dp->base; |
55f78c43 | 1949 | |
ea5b213a | 1950 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
b329530c | 1951 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 1952 | intel_dp->is_pch_edp = true; |
b329530c | 1953 | |
cfcb0fc9 | 1954 | if (output_reg == DP_A || is_pch_edp(intel_dp)) { |
b329530c AJ |
1955 | type = DRM_MODE_CONNECTOR_eDP; |
1956 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
1957 | } else { | |
1958 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
1959 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
1960 | } | |
1961 | ||
55f78c43 | 1962 | connector = &intel_connector->base; |
b329530c | 1963 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
1964 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
1965 | ||
eb1f8e4f DA |
1966 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
1967 | ||
652af9d7 | 1968 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
21d40d37 | 1969 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
652af9d7 | 1970 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
21d40d37 | 1971 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
652af9d7 | 1972 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
21d40d37 | 1973 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
f8aed700 | 1974 | |
cfcb0fc9 | 1975 | if (is_edp(intel_dp)) |
21d40d37 | 1976 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
6251ec0a | 1977 | |
21d40d37 | 1978 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
a4fc5ed6 KP |
1979 | connector->interlace_allowed = true; |
1980 | connector->doublescan_allowed = 0; | |
1981 | ||
4ef69c7a | 1982 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
a4fc5ed6 | 1983 | DRM_MODE_ENCODER_TMDS); |
4ef69c7a | 1984 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
a4fc5ed6 | 1985 | |
df0e9248 | 1986 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
1987 | drm_sysfs_connector_add(connector); |
1988 | ||
1989 | /* Set up the DDC bus. */ | |
5eb08b69 | 1990 | switch (output_reg) { |
32f9d658 ZW |
1991 | case DP_A: |
1992 | name = "DPDDC-A"; | |
1993 | break; | |
5eb08b69 ZW |
1994 | case DP_B: |
1995 | case PCH_DP_B: | |
b01f2c3a JB |
1996 | dev_priv->hotplug_supported_mask |= |
1997 | HDMIB_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1998 | name = "DPDDC-B"; |
1999 | break; | |
2000 | case DP_C: | |
2001 | case PCH_DP_C: | |
b01f2c3a JB |
2002 | dev_priv->hotplug_supported_mask |= |
2003 | HDMIC_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2004 | name = "DPDDC-C"; |
2005 | break; | |
2006 | case DP_D: | |
2007 | case PCH_DP_D: | |
b01f2c3a JB |
2008 | dev_priv->hotplug_supported_mask |= |
2009 | HDMID_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2010 | name = "DPDDC-D"; |
2011 | break; | |
2012 | } | |
2013 | ||
ea5b213a | 2014 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
32f9d658 | 2015 | |
89667383 JB |
2016 | /* Cache some DPCD data in the eDP case */ |
2017 | if (is_edp(intel_dp)) { | |
59f3e272 | 2018 | bool ret; |
5d613501 JB |
2019 | u32 pp_on, pp_div; |
2020 | ||
2021 | pp_on = I915_READ(PCH_PP_ON_DELAYS); | |
2022 | pp_div = I915_READ(PCH_PP_DIVISOR); | |
89667383 | 2023 | |
5d613501 JB |
2024 | /* Get T3 & T12 values (note: VESA not bspec terminology) */ |
2025 | dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16; | |
2026 | dev_priv->panel_t3 /= 10; /* t3 in 100us units */ | |
2027 | dev_priv->panel_t12 = pp_div & 0xf; | |
2028 | dev_priv->panel_t12 *= 100; /* t12 in 100ms units */ | |
2029 | ||
2030 | ironlake_edp_panel_vdd_on(intel_dp); | |
59f3e272 | 2031 | ret = intel_dp_get_dpcd(intel_dp); |
3d3dc149 | 2032 | ironlake_edp_panel_vdd_off(intel_dp); |
59f3e272 | 2033 | if (ret) { |
7183dc29 JB |
2034 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
2035 | dev_priv->no_aux_handshake = | |
2036 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
89667383 JB |
2037 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
2038 | } else { | |
3d3dc149 | 2039 | /* if this fails, presume the device is a ghost */ |
48898b03 | 2040 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
3d3dc149 | 2041 | intel_dp_encoder_destroy(&intel_dp->base.base); |
48898b03 | 2042 | intel_dp_destroy(&intel_connector->base); |
3d3dc149 | 2043 | return; |
89667383 | 2044 | } |
89667383 JB |
2045 | } |
2046 | ||
21d40d37 | 2047 | intel_encoder->hot_plug = intel_dp_hot_plug; |
a4fc5ed6 | 2048 | |
4d926461 | 2049 | if (is_edp(intel_dp)) { |
32f9d658 ZW |
2050 | /* initialize panel mode from VBT if available for eDP */ |
2051 | if (dev_priv->lfp_lvds_vbt_mode) { | |
2052 | dev_priv->panel_fixed_mode = | |
2053 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); | |
2054 | if (dev_priv->panel_fixed_mode) { | |
2055 | dev_priv->panel_fixed_mode->type |= | |
2056 | DRM_MODE_TYPE_PREFERRED; | |
2057 | } | |
2058 | } | |
2059 | } | |
2060 | ||
f684960e CW |
2061 | intel_dp_add_properties(intel_dp, connector); |
2062 | ||
a4fc5ed6 KP |
2063 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
2064 | * 0xd. Failure to do so will result in spurious interrupts being | |
2065 | * generated on the port when a cable is not attached. | |
2066 | */ | |
2067 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
2068 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
2069 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2070 | } | |
2071 | } |