]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/intel_dp.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Splitting intel_dp_detect
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf 50struct dp_link_dpll {
840b32b7 51 int clock;
9dd4ffdf
CML		 52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
840b32b7 56 { 162000,
9dd4ffdf 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
840b32b7 58 { 270000,
9dd4ffdf
CML		 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
840b32b7 63 { 162000,
9dd4ffdf 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
840b32b7 65 { 270000,
9dd4ffdf
CML		 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5 69static const struct dp_link_dpll vlv_dpll[] = {
840b32b7 70 { 162000,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
840b32b7 72 { 270000,
65ce4bf5
CML		 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
840b32b7 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
ef9348c8 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
840b32b7 88 { 270000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
840b32b7 90 { 540000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8
CML		 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15
VS		 97 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 99
cfcb0fc9
JB		 100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
da63a9f2
PZ		 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 112}
113
68b4d824 114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 115{
68b4d824
ID		 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 119}
120
df0e9248
CW		 121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
fa90ecef 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 124}
125
ea5b213a 126static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
f21a2198 132static void intel_dp_unset_edid(struct intel_dp *intel_dp);
a4fc5ed6 133
e0fce78f
VS		 134static unsigned int intel_dp_unused_lane_mask(int lane_count)
135{
136 return ~((1 << lane_count) - 1) & 0xf;
137}
138
ed4e9c1d
VS		 139static int
140intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 141{
7183dc29 142 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 143
144 switch (max_link_bw) {
145 case DP_LINK_BW_1_62:
146 case DP_LINK_BW_2_7:
1db10e28 147 case DP_LINK_BW_5_4:
d4eead50 148 break;
a4fc5ed6 149 default:
d4eead50
ID		 150 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
151 max_link_bw);
a4fc5ed6
KP		 152 max_link_bw = DP_LINK_BW_1_62;
153 break;
154 }
155 return max_link_bw;
156}
157
eeb6324d
PZ		 158static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
159{
160 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
eeb6324d
PZ		 161 u8 source_max, sink_max;
162
ccb1a831 163 source_max = intel_dig_port->max_lanes;
eeb6324d
PZ		 164 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
165
166 return min(source_max, sink_max);
167}
168
cd9dde44
AJ		 169/*
170 * The units on the numbers in the next two are... bizarre. Examples will
171 * make it clearer; this one parallels an example in the eDP spec.
172 *
173 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
174 *
175 * 270000 * 1 * 8 / 10 == 216000
176 *
177 * The actual data capacity of that configuration is 2.16Gbit/s, so the
178 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
179 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
180 * 119000. At 18bpp that's 2142000 kilobits per second.
181 *
182 * Thus the strange-looking division by 10 in intel_dp_link_required, to
183 * get the result in decakilobits instead of kilobits.
184 */
185
a4fc5ed6 186static int
c898261c 187intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 188{
cd9dde44 189 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 190}
191
fe27d53e
DA		 192static int
193intel_dp_max_data_rate(int max_link_clock, int max_lanes)
194{
195 return (max_link_clock * max_lanes * 8) / 10;
196}
197
c19de8eb 198static enum drm_mode_status
a4fc5ed6
KP		 199intel_dp_mode_valid(struct drm_connector *connector,
200 struct drm_display_mode *mode)
201{
df0e9248 202 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 203 struct intel_connector *intel_connector = to_intel_connector(connector);
204 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 205 int target_clock = mode->clock;
206 int max_rate, mode_rate, max_lanes, max_link_clock;
799487f5 207 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
a4fc5ed6 208
dd06f90e
JN		 209 if (is_edp(intel_dp) && fixed_mode) {
210 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 211 return MODE_PANEL;
212
dd06f90e 213 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 214 return MODE_PANEL;
03afc4a2
DV		 215
216 target_clock = fixed_mode->clock;
7de56f43
ZY		 217 }
218
50fec21a 219 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 220 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 221
222 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
223 mode_rate = intel_dp_link_required(target_clock, 18);
224
799487f5 225 if (mode_rate > max_rate || target_clock > max_dotclk)
c4867936 226 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 227
228 if (mode->clock < 10000)
229 return MODE_CLOCK_LOW;
230
0af78a2b
DV		 231 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
232 return MODE_H_ILLEGAL;
233
a4fc5ed6
KP		 234 return MODE_OK;
235}
236
a4f1289e 237uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 238{
239 int i;
240 uint32_t v = 0;
241
242 if (src_bytes > 4)
243 src_bytes = 4;
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
246 return v;
247}
248
c2af70e2 249static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 250{
251 int i;
252 if (dst_bytes > 4)
253 dst_bytes = 4;
254 for (i = 0; i < dst_bytes; i++)
255 dst[i] = src >> ((3-i) * 8);
256}
257
bf13e81b
JN		 258static void
259intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 260 struct intel_dp *intel_dp);
bf13e81b
JN		 261static void
262intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 263 struct intel_dp *intel_dp);
bf13e81b 264
773538e8
VS		 265static void pps_lock(struct intel_dp *intel_dp)
266{
267 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
268 struct intel_encoder *encoder = &intel_dig_port->base;
269 struct drm_device *dev = encoder->base.dev;
270 struct drm_i915_private *dev_priv = dev->dev_private;
271 enum intel_display_power_domain power_domain;
272
273 /*
274 * See vlv_power_sequencer_reset() why we need
275 * a power domain reference here.
276 */
25f78f58 277 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 278 intel_display_power_get(dev_priv, power_domain);
279
280 mutex_lock(&dev_priv->pps_mutex);
281}
282
283static void pps_unlock(struct intel_dp *intel_dp)
284{
285 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
286 struct intel_encoder *encoder = &intel_dig_port->base;
287 struct drm_device *dev = encoder->base.dev;
288 struct drm_i915_private *dev_priv = dev->dev_private;
289 enum intel_display_power_domain power_domain;
290
291 mutex_unlock(&dev_priv->pps_mutex);
292
25f78f58 293 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 294 intel_display_power_put(dev_priv, power_domain);
295}
296
961a0db0
VS		 297static void
298vlv_power_sequencer_kick(struct intel_dp *intel_dp)
299{
300 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
301 struct drm_device *dev = intel_dig_port->base.base.dev;
302 struct drm_i915_private *dev_priv = dev->dev_private;
303 enum pipe pipe = intel_dp->pps_pipe;
0047eedc
VS		 304 bool pll_enabled, release_cl_override = false;
305 enum dpio_phy phy = DPIO_PHY(pipe);
306 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
961a0db0
VS		 307 uint32_t DP;
308
309 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
310 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
311 pipe_name(pipe), port_name(intel_dig_port->port)))
312 return;
313
314 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
315 pipe_name(pipe), port_name(intel_dig_port->port));
316
317 /* Preserve the BIOS-computed detected bit. This is
318 * supposed to be read-only.
319 */
320 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
321 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
322 DP |= DP_PORT_WIDTH(1);
323 DP |= DP_LINK_TRAIN_PAT_1;
324
325 if (IS_CHERRYVIEW(dev))
326 DP |= DP_PIPE_SELECT_CHV(pipe);
327 else if (pipe == PIPE_B)
328 DP |= DP_PIPEB_SELECT;
329
d288f65f
VS		 330 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
331
332 /*
333 * The DPLL for the pipe must be enabled for this to work.
334 * So enable temporarily it if it's not already enabled.
335 */
0047eedc
VS		 336 if (!pll_enabled) {
337 release_cl_override = IS_CHERRYVIEW(dev) &&
338 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
339
3f36b937
TU		 340 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
341 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
342 DRM_ERROR("Failed to force on pll for pipe %c!\n",
343 pipe_name(pipe));
344 return;
345 }
0047eedc 346 }
d288f65f 347
961a0db0
VS		 348 /*
349 * Similar magic as in intel_dp_enable_port().
350 * We _must_ do this port enable + disable trick
351 * to make this power seqeuencer lock onto the port.
352 * Otherwise even VDD force bit won't work.
353 */
354 I915_WRITE(intel_dp->output_reg, DP);
355 POSTING_READ(intel_dp->output_reg);
356
357 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
358 POSTING_READ(intel_dp->output_reg);
359
360 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
361 POSTING_READ(intel_dp->output_reg);
d288f65f 362
0047eedc 363 if (!pll_enabled) {
d288f65f 364 vlv_force_pll_off(dev, pipe);
0047eedc
VS		 365
366 if (release_cl_override)
367 chv_phy_powergate_ch(dev_priv, phy, ch, false);
368 }
961a0db0
VS		 369}
370
bf13e81b
JN		 371static enum pipe
372vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
373{
374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 375 struct drm_device *dev = intel_dig_port->base.base.dev;
376 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 377 struct intel_encoder *encoder;
378 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 379 enum pipe pipe;
bf13e81b 380
e39b999a 381 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 382
a8c3344e
VS		 383 /* We should never land here with regular DP ports */
384 WARN_ON(!is_edp(intel_dp));
385
a4a5d2f8
VS		 386 if (intel_dp->pps_pipe != INVALID_PIPE)
387 return intel_dp->pps_pipe;
388
389 /*
390 * We don't have power sequencer currently.
391 * Pick one that's not used by other ports.
392 */
19c8054c 393 for_each_intel_encoder(dev, encoder) {
a4a5d2f8
VS		 394 struct intel_dp *tmp;
395
396 if (encoder->type != INTEL_OUTPUT_EDP)
397 continue;
398
399 tmp = enc_to_intel_dp(&encoder->base);
400
401 if (tmp->pps_pipe != INVALID_PIPE)
402 pipes &= ~(1 << tmp->pps_pipe);
403 }
404
405 /*
406 * Didn't find one. This should not happen since there
407 * are two power sequencers and up to two eDP ports.
408 */
409 if (WARN_ON(pipes == 0))
a8c3344e
VS		 410 pipe = PIPE_A;
411 else
412 pipe = ffs(pipes) - 1;
a4a5d2f8 413
a8c3344e
VS		 414 vlv_steal_power_sequencer(dev, pipe);
415 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 416
417 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
418 pipe_name(intel_dp->pps_pipe),
419 port_name(intel_dig_port->port));
420
421 /* init power sequencer on this pipe and port */
36b5f425
VS		 422 intel_dp_init_panel_power_sequencer(dev, intel_dp);
423 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 424
961a0db0
VS		 425 /*
426 * Even vdd force doesn't work until we've made
427 * the power sequencer lock in on the port.
428 */
429 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 430
431 return intel_dp->pps_pipe;
432}
433
6491ab27
VS		 434typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
435 enum pipe pipe);
436
437static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
438 enum pipe pipe)
439{
440 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
441}
442
443static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
444 enum pipe pipe)
445{
446 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
447}
448
449static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
450 enum pipe pipe)
451{
452 return true;
453}
bf13e81b 454
a4a5d2f8 455static enum pipe
6491ab27
VS		 456vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
457 enum port port,
458 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 459{
460 enum pipe pipe;
bf13e81b 461
bf13e81b
JN		 462 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
463 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
464 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 465
466 if (port_sel != PANEL_PORT_SELECT_VLV(port))
467 continue;
468
6491ab27
VS		 469 if (!pipe_check(dev_priv, pipe))
470 continue;
471
a4a5d2f8 472 return pipe;
bf13e81b
JN		 473 }
474
a4a5d2f8
VS		 475 return INVALID_PIPE;
476}
477
478static void
479vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
480{
481 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
482 struct drm_device *dev = intel_dig_port->base.base.dev;
483 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 484 enum port port = intel_dig_port->port;
485
486 lockdep_assert_held(&dev_priv->pps_mutex);
487
488 /* try to find a pipe with this port selected */
6491ab27
VS		 489 /* first pick one where the panel is on */
490 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
491 vlv_pipe_has_pp_on);
492 /* didn't find one? pick one where vdd is on */
493 if (intel_dp->pps_pipe == INVALID_PIPE)
494 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
495 vlv_pipe_has_vdd_on);
496 /* didn't find one? pick one with just the correct port */
497 if (intel_dp->pps_pipe == INVALID_PIPE)
498 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
499 vlv_pipe_any);
a4a5d2f8
VS		 500
501 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
502 if (intel_dp->pps_pipe == INVALID_PIPE) {
503 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
504 port_name(port));
505 return;
bf13e81b
JN		 506 }
507
a4a5d2f8
VS		 508 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
509 port_name(port), pipe_name(intel_dp->pps_pipe));
510
36b5f425
VS		 511 intel_dp_init_panel_power_sequencer(dev, intel_dp);
512 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 513}
514
773538e8
VS		 515void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
516{
517 struct drm_device *dev = dev_priv->dev;
518 struct intel_encoder *encoder;
519
666a4537 520 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)))
773538e8
VS		 521 return;
522
523 /*
524 * We can't grab pps_mutex here due to deadlock with power_domain
525 * mutex when power_domain functions are called while holding pps_mutex.
526 * That also means that in order to use pps_pipe the code needs to
527 * hold both a power domain reference and pps_mutex, and the power domain
528 * reference get/put must be done while _not_ holding pps_mutex.
529 * pps_{lock,unlock}() do these steps in the correct order, so one
530 * should use them always.
531 */
532
19c8054c 533 for_each_intel_encoder(dev, encoder) {
773538e8
VS		 534 struct intel_dp *intel_dp;
535
536 if (encoder->type != INTEL_OUTPUT_EDP)
537 continue;
538
539 intel_dp = enc_to_intel_dp(&encoder->base);
540 intel_dp->pps_pipe = INVALID_PIPE;
541 }
bf13e81b
JN		 542}
543
f0f59a00
VS		 544static i915_reg_t
545_pp_ctrl_reg(struct intel_dp *intel_dp)
bf13e81b
JN		 546{
547 struct drm_device *dev = intel_dp_to_dev(intel_dp);
548
b0a08bec
VK		 549 if (IS_BROXTON(dev))
550 return BXT_PP_CONTROL(0);
551 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 552 return PCH_PP_CONTROL;
553 else
554 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
555}
556
f0f59a00
VS		 557static i915_reg_t
558_pp_stat_reg(struct intel_dp *intel_dp)
bf13e81b
JN		 559{
560 struct drm_device *dev = intel_dp_to_dev(intel_dp);
561
b0a08bec
VK		 562 if (IS_BROXTON(dev))
563 return BXT_PP_STATUS(0);
564 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 565 return PCH_PP_STATUS;
566 else
567 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
568}
569
01527b31
CT		 570/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
571 This function only applicable when panel PM state is not to be tracked */
572static int edp_notify_handler(struct notifier_block *this, unsigned long code,
573 void *unused)
574{
575 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
576 edp_notifier);
577 struct drm_device *dev = intel_dp_to_dev(intel_dp);
578 struct drm_i915_private *dev_priv = dev->dev_private;
01527b31
CT		 579
580 if (!is_edp(intel_dp) || code != SYS_RESTART)
581 return 0;
582
773538e8 583 pps_lock(intel_dp);
e39b999a 584
666a4537 585 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e39b999a 586 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
f0f59a00 587 i915_reg_t pp_ctrl_reg, pp_div_reg;
649636ef 588 u32 pp_div;
e39b999a 589
01527b31
CT		 590 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
591 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
592 pp_div = I915_READ(pp_div_reg);
593 pp_div &= PP_REFERENCE_DIVIDER_MASK;
594
595 /* 0x1F write to PP_DIV_REG sets max cycle delay */
596 I915_WRITE(pp_div_reg, pp_div | 0x1F);
597 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
598 msleep(intel_dp->panel_power_cycle_delay);
599 }
600
773538e8 601 pps_unlock(intel_dp);
e39b999a 602
01527b31
CT		 603 return 0;
604}
605
4be73780 606static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 607{
30add22d 608 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 609 struct drm_i915_private *dev_priv = dev->dev_private;
610
e39b999a
VS		 611 lockdep_assert_held(&dev_priv->pps_mutex);
612
666a4537 613 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 614 intel_dp->pps_pipe == INVALID_PIPE)
615 return false;
616
bf13e81b 617 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 618}
619
4be73780 620static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 621{
30add22d 622 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 623 struct drm_i915_private *dev_priv = dev->dev_private;
624
e39b999a
VS		 625 lockdep_assert_held(&dev_priv->pps_mutex);
626
666a4537 627 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 628 intel_dp->pps_pipe == INVALID_PIPE)
629 return false;
630
773538e8 631 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 632}
633
9b984dae
KP		 634static void
635intel_dp_check_edp(struct intel_dp *intel_dp)
636{
30add22d 637 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 638 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 639
9b984dae
KP		 640 if (!is_edp(intel_dp))
641 return;
453c5420 642
4be73780 643 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 644 WARN(1, "eDP powered off while attempting aux channel communication.\n");
645 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 646 I915_READ(_pp_stat_reg(intel_dp)),
647 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 648 }
649}
650
9ee32fea
DV		 651static uint32_t
652intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
653{
654 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
655 struct drm_device *dev = intel_dig_port->base.base.dev;
656 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 657 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 658 uint32_t status;
659 bool done;
660
ef04f00d 661#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 662 if (has_aux_irq)
b18ac466 663 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 664 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 665 else
666 done = wait_for_atomic(C, 10) == 0;
667 if (!done)
668 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
669 has_aux_irq);
670#undef C
671
672 return status;
673}
674
6ffb1be7 675static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 676{
174edf1f 677 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
e7dc33f3 678 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
9ee32fea 679
a457f54b
VS		 680 if (index)
681 return 0;
682
ec5b01dd
DL		 683 /*
684 * The clock divider is based off the hrawclk, and would like to run at
a457f54b 685 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
a4fc5ed6 686 */
a457f54b 687 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 688}
689
690static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
691{
692 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 693 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd
DL		 694
695 if (index)
696 return 0;
697
a457f54b
VS		 698 /*
699 * The clock divider is based off the cdclk or PCH rawclk, and would
700 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
701 * divide by 2000 and use that
702 */
e7dc33f3 703 if (intel_dig_port->port == PORT_A)
fce18c4c 704 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
e7dc33f3
VS		 705 else
706 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 707}
708
709static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
710{
711 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 712 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd 713
a457f54b 714 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
2c55c336 715 /* Workaround for non-ULT HSW */
bc86625a
CW		 716 switch (index) {
717 case 0: return 63;
718 case 1: return 72;
719 default: return 0;
720 }
2c55c336 721 }
a457f54b
VS		 722
723 return ilk_get_aux_clock_divider(intel_dp, index);
b84a1cf8
RV		 724}
725
b6b5e383
DL		 726static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
727{
728 /*
729 * SKL doesn't need us to program the AUX clock divider (Hardware will
730 * derive the clock from CDCLK automatically). We still implement the
731 * get_aux_clock_divider vfunc to plug-in into the existing code.
732 */
733 return index ? 0 : 1;
734}
735
6ffb1be7
VS		 736static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
737 bool has_aux_irq,
738 int send_bytes,
739 uint32_t aux_clock_divider)
5ed12a19
DL		 740{
741 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
742 struct drm_device *dev = intel_dig_port->base.base.dev;
743 uint32_t precharge, timeout;
744
745 if (IS_GEN6(dev))
746 precharge = 3;
747 else
748 precharge = 5;
749
f3c6a3a7 750 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
5ed12a19
DL		 751 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
752 else
753 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
754
755 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 756 DP_AUX_CH_CTL_DONE |
5ed12a19 757 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 758 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 759 timeout |
788d4433 760 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 761 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
762 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 763 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 764}
765
b9ca5fad
DL		 766static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
767 bool has_aux_irq,
768 int send_bytes,
769 uint32_t unused)
770{
771 return DP_AUX_CH_CTL_SEND_BUSY |
772 DP_AUX_CH_CTL_DONE |
773 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
774 DP_AUX_CH_CTL_TIME_OUT_ERROR |
775 DP_AUX_CH_CTL_TIME_OUT_1600us |
776 DP_AUX_CH_CTL_RECEIVE_ERROR |
777 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
778 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
779}
780
b84a1cf8
RV		 781static int
782intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 783 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 784 uint8_t *recv, int recv_size)
785{
786 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
787 struct drm_device *dev = intel_dig_port->base.base.dev;
788 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 789 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
bc86625a 790 uint32_t aux_clock_divider;
b84a1cf8
RV		 791 int i, ret, recv_bytes;
792 uint32_t status;
5ed12a19 793 int try, clock = 0;
4e6b788c 794 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 795 bool vdd;
796
773538e8 797 pps_lock(intel_dp);
e39b999a 798
72c3500a
VS		 799 /*
800 * We will be called with VDD already enabled for dpcd/edid/oui reads.
801 * In such cases we want to leave VDD enabled and it's up to upper layers
802 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
803 * ourselves.
804 */
1e0560e0 805 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 806
807 /* dp aux is extremely sensitive to irq latency, hence request the
808 * lowest possible wakeup latency and so prevent the cpu from going into
809 * deep sleep states.
810 */
811 pm_qos_update_request(&dev_priv->pm_qos, 0);
812
813 intel_dp_check_edp(intel_dp);
5eb08b69 814
11bee43e
JB		 815 /* Try to wait for any previous AUX channel activity */
816 for (try = 0; try < 3; try++) {
ef04f00d 817 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 818 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
819 break;
820 msleep(1);
821 }
822
823 if (try == 3) {
02196c77
MK		 824 static u32 last_status = -1;
825 const u32 status = I915_READ(ch_ctl);
826
827 if (status != last_status) {
828 WARN(1, "dp_aux_ch not started status 0x%08x\n",
829 status);
830 last_status = status;
831 }
832
9ee32fea
DV		 833 ret = -EBUSY;
834 goto out;
4f7f7b7e
CW		 835 }
836
46a5ae9f
PZ		 837 /* Only 5 data registers! */
838 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
839 ret = -E2BIG;
840 goto out;
841 }
842
ec5b01dd 843 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 844 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
845 has_aux_irq,
846 send_bytes,
847 aux_clock_divider);
5ed12a19 848
bc86625a
CW		 849 /* Must try at least 3 times according to DP spec */
850 for (try = 0; try < 5; try++) {
851 /* Load the send data into the aux channel data registers */
852 for (i = 0; i < send_bytes; i += 4)
330e20ec 853 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
a4f1289e
RV		 854 intel_dp_pack_aux(send + i,
855 send_bytes - i));
bc86625a
CW		 856
857 /* Send the command and wait for it to complete */
5ed12a19 858 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 859
860 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
861
862 /* Clear done status and any errors */
863 I915_WRITE(ch_ctl,
864 status |
865 DP_AUX_CH_CTL_DONE |
866 DP_AUX_CH_CTL_TIME_OUT_ERROR |
867 DP_AUX_CH_CTL_RECEIVE_ERROR);
868
74ebf294 869 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 870 continue;
74ebf294
TP		 871
872 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
873 * 400us delay required for errors and timeouts
874 * Timeout errors from the HW already meet this
875 * requirement so skip to next iteration
876 */
877 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
878 usleep_range(400, 500);
bc86625a 879 continue;
74ebf294 880 }
bc86625a 881 if (status & DP_AUX_CH_CTL_DONE)
e058c945 882 goto done;
bc86625a 883 }
a4fc5ed6
KP		 884 }
885
a4fc5ed6 886 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 887 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 888 ret = -EBUSY;
889 goto out;
a4fc5ed6
KP		 890 }
891
e058c945 892done:
a4fc5ed6
KP		 893 /* Check for timeout or receive error.
894 * Timeouts occur when the sink is not connected
895 */
a5b3da54 896 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 897 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 898 ret = -EIO;
899 goto out;
a5b3da54 900 }
1ae8c0a5
KP		 901
902 /* Timeouts occur when the device isn't connected, so they're
903 * "normal" -- don't fill the kernel log with these */
a5b3da54 904 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 905 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 906 ret = -ETIMEDOUT;
907 goto out;
a4fc5ed6
KP		 908 }
909
910 /* Unload any bytes sent back from the other side */
911 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
912 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
14e01889
RV		 913
914 /*
915 * By BSpec: "Message sizes of 0 or >20 are not allowed."
916 * We have no idea of what happened so we return -EBUSY so
917 * drm layer takes care for the necessary retries.
918 */
919 if (recv_bytes == 0 || recv_bytes > 20) {
920 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
921 recv_bytes);
922 /*
923 * FIXME: This patch was created on top of a series that
924 * organize the retries at drm level. There EBUSY should
925 * also take care for 1ms wait before retrying.
926 * That aux retries re-org is still needed and after that is
927 * merged we remove this sleep from here.
928 */
929 usleep_range(1000, 1500);
930 ret = -EBUSY;
931 goto out;
932 }
933
a4fc5ed6
KP		 934 if (recv_bytes > recv_size)
935 recv_bytes = recv_size;
0206e353 936
4f7f7b7e 937 for (i = 0; i < recv_bytes; i += 4)
330e20ec 938 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
a4f1289e 939 recv + i, recv_bytes - i);
a4fc5ed6 940
9ee32fea
DV		 941 ret = recv_bytes;
942out:
943 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
944
884f19e9
JN		 945 if (vdd)
946 edp_panel_vdd_off(intel_dp, false);
947
773538e8 948 pps_unlock(intel_dp);
e39b999a 949
9ee32fea 950 return ret;
a4fc5ed6
KP		 951}
952
a6c8aff0
JN		 953#define BARE_ADDRESS_SIZE 3
954#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 955static ssize_t
956intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 957{
9d1a1031
JN		 958 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
959 uint8_t txbuf[20], rxbuf[20];
960 size_t txsize, rxsize;
a4fc5ed6 961 int ret;
a4fc5ed6 962
d2d9cbbd
VS		 963 txbuf[0] = (msg->request << 4) |
964 ((msg->address >> 16) & 0xf);
965 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 966 txbuf[2] = msg->address & 0xff;
967 txbuf[3] = msg->size - 1;
46a5ae9f 968
9d1a1031
JN		 969 switch (msg->request & ~DP_AUX_I2C_MOT) {
970 case DP_AUX_NATIVE_WRITE:
971 case DP_AUX_I2C_WRITE:
c1e74122 972 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
a6c8aff0 973 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 974 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 975
9d1a1031
JN		 976 if (WARN_ON(txsize > 20))
977 return -E2BIG;
a4fc5ed6 978
d81a67cc
ID		 979 if (msg->buffer)
980 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
981 else
982 WARN_ON(msg->size);
a4fc5ed6 983
9d1a1031
JN		 984 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
985 if (ret > 0) {
986 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 987
a1ddefd8
JN		 988 if (ret > 1) {
989 /* Number of bytes written in a short write. */
990 ret = clamp_t(int, rxbuf[1], 0, msg->size);
991 } else {
992 /* Return payload size. */
993 ret = msg->size;
994 }
9d1a1031
JN		 995 }
996 break;
46a5ae9f 997
9d1a1031
JN		 998 case DP_AUX_NATIVE_READ:
999 case DP_AUX_I2C_READ:
a6c8aff0 1000 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 1001 rxsize = msg->size + 1;
a4fc5ed6 1002
9d1a1031
JN		 1003 if (WARN_ON(rxsize > 20))
1004 return -E2BIG;
a4fc5ed6 1005
9d1a1031
JN		 1006 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1007 if (ret > 0) {
1008 msg->reply = rxbuf[0] >> 4;
1009 /*
1010 * Assume happy day, and copy the data. The caller is
1011 * expected to check msg->reply before touching it.
1012 *
1013 * Return payload size.
1014 */
1015 ret--;
1016 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1017 }
9d1a1031
JN		 1018 break;
1019
1020 default:
1021 ret = -EINVAL;
1022 break;
a4fc5ed6 1023 }
f51a44b9 1024
9d1a1031 1025 return ret;
a4fc5ed6
KP		 1026}
1027
f0f59a00
VS		 1028static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1029 enum port port)
da00bdcf
VS		 1030{
1031 switch (port) {
1032 case PORT_B:
1033 case PORT_C:
1034 case PORT_D:
1035 return DP_AUX_CH_CTL(port);
1036 default:
1037 MISSING_CASE(port);
1038 return DP_AUX_CH_CTL(PORT_B);
1039 }
1040}
1041
f0f59a00
VS		 1042static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1043 enum port port, int index)
330e20ec
VS		 1044{
1045 switch (port) {
1046 case PORT_B:
1047 case PORT_C:
1048 case PORT_D:
1049 return DP_AUX_CH_DATA(port, index);
1050 default:
1051 MISSING_CASE(port);
1052 return DP_AUX_CH_DATA(PORT_B, index);
1053 }
1054}
1055
f0f59a00
VS		 1056static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1057 enum port port)
da00bdcf
VS		 1058{
1059 switch (port) {
1060 case PORT_A:
1061 return DP_AUX_CH_CTL(port);
1062 case PORT_B:
1063 case PORT_C:
1064 case PORT_D:
1065 return PCH_DP_AUX_CH_CTL(port);
1066 default:
1067 MISSING_CASE(port);
1068 return DP_AUX_CH_CTL(PORT_A);
1069 }
1070}
1071
f0f59a00
VS		 1072static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1073 enum port port, int index)
330e20ec
VS		 1074{
1075 switch (port) {
1076 case PORT_A:
1077 return DP_AUX_CH_DATA(port, index);
1078 case PORT_B:
1079 case PORT_C:
1080 case PORT_D:
1081 return PCH_DP_AUX_CH_DATA(port, index);
1082 default:
1083 MISSING_CASE(port);
1084 return DP_AUX_CH_DATA(PORT_A, index);
1085 }
1086}
1087
da00bdcf
VS		 1088/*
1089 * On SKL we don't have Aux for port E so we rely
1090 * on VBT to set a proper alternate aux channel.
1091 */
1092static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1093{
1094 const struct ddi_vbt_port_info *info =
1095 &dev_priv->vbt.ddi_port_info[PORT_E];
1096
1097 switch (info->alternate_aux_channel) {
1098 case DP_AUX_A:
1099 return PORT_A;
1100 case DP_AUX_B:
1101 return PORT_B;
1102 case DP_AUX_C:
1103 return PORT_C;
1104 case DP_AUX_D:
1105 return PORT_D;
1106 default:
1107 MISSING_CASE(info->alternate_aux_channel);
1108 return PORT_A;
1109 }
1110}
1111
f0f59a00
VS		 1112static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1113 enum port port)
da00bdcf
VS		 1114{
1115 if (port == PORT_E)
1116 port = skl_porte_aux_port(dev_priv);
1117
1118 switch (port) {
1119 case PORT_A:
1120 case PORT_B:
1121 case PORT_C:
1122 case PORT_D:
1123 return DP_AUX_CH_CTL(port);
1124 default:
1125 MISSING_CASE(port);
1126 return DP_AUX_CH_CTL(PORT_A);
1127 }
1128}
1129
f0f59a00
VS		 1130static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1131 enum port port, int index)
330e20ec
VS		 1132{
1133 if (port == PORT_E)
1134 port = skl_porte_aux_port(dev_priv);
1135
1136 switch (port) {
1137 case PORT_A:
1138 case PORT_B:
1139 case PORT_C:
1140 case PORT_D:
1141 return DP_AUX_CH_DATA(port, index);
1142 default:
1143 MISSING_CASE(port);
1144 return DP_AUX_CH_DATA(PORT_A, index);
1145 }
1146}
1147
f0f59a00
VS		 1148static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1149 enum port port)
330e20ec
VS		 1150{
1151 if (INTEL_INFO(dev_priv)->gen >= 9)
1152 return skl_aux_ctl_reg(dev_priv, port);
1153 else if (HAS_PCH_SPLIT(dev_priv))
1154 return ilk_aux_ctl_reg(dev_priv, port);
1155 else
1156 return g4x_aux_ctl_reg(dev_priv, port);
1157}
1158
f0f59a00
VS		 1159static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1160 enum port port, int index)
330e20ec
VS		 1161{
1162 if (INTEL_INFO(dev_priv)->gen >= 9)
1163 return skl_aux_data_reg(dev_priv, port, index);
1164 else if (HAS_PCH_SPLIT(dev_priv))
1165 return ilk_aux_data_reg(dev_priv, port, index);
1166 else
1167 return g4x_aux_data_reg(dev_priv, port, index);
1168}
1169
1170static void intel_aux_reg_init(struct intel_dp *intel_dp)
1171{
1172 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1173 enum port port = dp_to_dig_port(intel_dp)->port;
1174 int i;
1175
1176 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1177 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1178 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1179}
1180
9d1a1031 1181static void
a121f4e5
VS		 1182intel_dp_aux_fini(struct intel_dp *intel_dp)
1183{
1184 drm_dp_aux_unregister(&intel_dp->aux);
1185 kfree(intel_dp->aux.name);
1186}
1187
1188static int
9d1a1031
JN		 1189intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1190{
33ad6626
JN		 1191 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1192 enum port port = intel_dig_port->port;
ab2c0672
DA		 1193 int ret;
1194
330e20ec 1195 intel_aux_reg_init(intel_dp);
8316f337 1196
a121f4e5
VS		 1197 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1198 if (!intel_dp->aux.name)
1199 return -ENOMEM;
1200
4d32c0d8 1201 intel_dp->aux.dev = connector->base.kdev;
9d1a1031 1202 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1203
a121f4e5
VS		 1204 DRM_DEBUG_KMS("registering %s bus for %s\n",
1205 intel_dp->aux.name,
0b99836f 1206 connector->base.kdev->kobj.name);
8316f337 1207
4f71d0cb 1208 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1209 if (ret < 0) {
4f71d0cb 1210 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
a121f4e5
VS		 1211 intel_dp->aux.name, ret);
1212 kfree(intel_dp->aux.name);
1213 return ret;
ab2c0672 1214 }
8a5e6aeb 1215
a121f4e5 1216 return 0;
a4fc5ed6
KP		 1217}
1218
80f65de3
ID		 1219static void
1220intel_dp_connector_unregister(struct intel_connector *intel_connector)
1221{
1222 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1223
4d32c0d8 1224 intel_dp_aux_fini(intel_dp);
80f65de3
ID		 1225 intel_connector_unregister(intel_connector);
1226}
1227
fc0f8e25 1228static int
12f6a2e2 1229intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1230{
94ca719e
VS		 1231 if (intel_dp->num_sink_rates) {
1232 *sink_rates = intel_dp->sink_rates;
1233 return intel_dp->num_sink_rates;
fc0f8e25 1234 }
12f6a2e2
VS		 1235
1236 *sink_rates = default_rates;
1237
1238 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1239}
1240
e588fa18 1241bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
ed63baaf 1242{
e588fa18
ACO		 1243 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1244 struct drm_device *dev = dig_port->base.base.dev;
1245
ed63baaf 1246 /* WaDisableHBR2:skl */
e87a005d 1247 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
ed63baaf
TS		 1248 return false;
1249
1250 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1251 (INTEL_INFO(dev)->gen >= 9))
1252 return true;
1253 else
1254 return false;
1255}
1256
a8f3ef61 1257static int
e588fa18 1258intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
a8f3ef61 1259{
e588fa18
ACO		 1260 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1261 struct drm_device *dev = dig_port->base.base.dev;
af7080f5
TS		 1262 int size;
1263
64987fc5
SJ		 1264 if (IS_BROXTON(dev)) {
1265 *source_rates = bxt_rates;
af7080f5 1266 size = ARRAY_SIZE(bxt_rates);
ef11bdb3 1267 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
637a9c63 1268 *source_rates = skl_rates;
af7080f5
TS		 1269 size = ARRAY_SIZE(skl_rates);
1270 } else {
1271 *source_rates = default_rates;
1272 size = ARRAY_SIZE(default_rates);
a8f3ef61 1273 }
636280ba 1274
ed63baaf 1275 /* This depends on the fact that 5.4 is last value in the array */
e588fa18 1276 if (!intel_dp_source_supports_hbr2(intel_dp))
af7080f5 1277 size--;
636280ba 1278
af7080f5 1279 return size;
a8f3ef61
SJ		 1280}
1281
c6bb3538
DV		 1282static void
1283intel_dp_set_clock(struct intel_encoder *encoder,
840b32b7 1284 struct intel_crtc_state *pipe_config)
c6bb3538
DV		 1285{
1286 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1287 const struct dp_link_dpll *divisor = NULL;
1288 int i, count = 0;
c6bb3538
DV		 1289
1290 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1291 divisor = gen4_dpll;
1292 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1293 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1294 divisor = pch_dpll;
1295 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1296 } else if (IS_CHERRYVIEW(dev)) {
1297 divisor = chv_dpll;
1298 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1299 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1300 divisor = vlv_dpll;
1301 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1302 }
9dd4ffdf
CML		 1303
1304 if (divisor && count) {
1305 for (i = 0; i < count; i++) {
840b32b7 1306 if (pipe_config->port_clock == divisor[i].clock) {
9dd4ffdf
CML		 1307 pipe_config->dpll = divisor[i].dpll;
1308 pipe_config->clock_set = true;
1309 break;
1310 }
1311 }
c6bb3538
DV		 1312 }
1313}
1314
2ecae76a
VS		 1315static int intersect_rates(const int *source_rates, int source_len,
1316 const int *sink_rates, int sink_len,
94ca719e 1317 int *common_rates)
a8f3ef61
SJ		 1318{
1319 int i = 0, j = 0, k = 0;
1320
a8f3ef61
SJ		 1321 while (i < source_len && j < sink_len) {
1322 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1323 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1324 return k;
94ca719e 1325 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1326 ++k;
1327 ++i;
1328 ++j;
1329 } else if (source_rates[i] < sink_rates[j]) {
1330 ++i;
1331 } else {
1332 ++j;
1333 }
1334 }
1335 return k;
1336}
1337
94ca719e
VS		 1338static int intel_dp_common_rates(struct intel_dp *intel_dp,
1339 int *common_rates)
2ecae76a 1340{
2ecae76a
VS		 1341 const int *source_rates, *sink_rates;
1342 int source_len, sink_len;
1343
1344 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
e588fa18 1345 source_len = intel_dp_source_rates(intel_dp, &source_rates);
2ecae76a
VS		 1346
1347 return intersect_rates(source_rates, source_len,
1348 sink_rates, sink_len,
94ca719e 1349 common_rates);
2ecae76a
VS		 1350}
1351
0336400e
VS		 1352static void snprintf_int_array(char *str, size_t len,
1353 const int *array, int nelem)
1354{
1355 int i;
1356
1357 str[0] = '\0';
1358
1359 for (i = 0; i < nelem; i++) {
b2f505be 1360 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1361 if (r >= len)
1362 return;
1363 str += r;
1364 len -= r;
1365 }
1366}
1367
1368static void intel_dp_print_rates(struct intel_dp *intel_dp)
1369{
0336400e 1370 const int *source_rates, *sink_rates;
94ca719e
VS		 1371 int source_len, sink_len, common_len;
1372 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1373 char str[128]; /* FIXME: too big for stack? */
1374
1375 if ((drm_debug & DRM_UT_KMS) == 0)
1376 return;
1377
e588fa18 1378 source_len = intel_dp_source_rates(intel_dp, &source_rates);
0336400e
VS		 1379 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1380 DRM_DEBUG_KMS("source rates: %s\n", str);
1381
1382 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1383 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1384 DRM_DEBUG_KMS("sink rates: %s\n", str);
1385
94ca719e
VS		 1386 common_len = intel_dp_common_rates(intel_dp, common_rates);
1387 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1388 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1389}
1390
f4896f15 1391static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1392{
1393 int i = 0;
1394
1395 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1396 if (find == rates[i])
1397 break;
1398
1399 return i;
1400}
1401
50fec21a
VS		 1402int
1403intel_dp_max_link_rate(struct intel_dp *intel_dp)
1404{
1405 int rates[DP_MAX_SUPPORTED_RATES] = {};
1406 int len;
1407
94ca719e 1408 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1409 if (WARN_ON(len <= 0))
1410 return 162000;
1411
1412 return rates[rate_to_index(0, rates) - 1];
1413}
1414
ed4e9c1d
VS		 1415int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1416{
94ca719e 1417 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1418}
1419
94223d04
ACO		 1420void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1421 uint8_t *link_bw, uint8_t *rate_select)
04a60f9f
VS		 1422{
1423 if (intel_dp->num_sink_rates) {
1424 *link_bw = 0;
1425 *rate_select =
1426 intel_dp_rate_select(intel_dp, port_clock);
1427 } else {
1428 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1429 *rate_select = 0;
1430 }
1431}
1432
00c09d70 1433bool
5bfe2ac0 1434intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1435 struct intel_crtc_state *pipe_config)
a4fc5ed6 1436{
5bfe2ac0 1437 struct drm_device *dev = encoder->base.dev;
36008365 1438 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1439 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1440 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1441 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1442 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1443 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1444 int lane_count, clock;
56071a20 1445 int min_lane_count = 1;
eeb6324d 1446 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1447 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1448 int min_clock = 0;
a8f3ef61 1449 int max_clock;
083f9560 1450 int bpp, mode_rate;
ff9a6750 1451 int link_avail, link_clock;
94ca719e
VS		 1452 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1453 int common_len;
04a60f9f 1454 uint8_t link_bw, rate_select;
a8f3ef61 1455
94ca719e 1456 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1457
1458 /* No common link rates between source and sink */
94ca719e 1459 WARN_ON(common_len <= 0);
a8f3ef61 1460
94ca719e 1461 max_clock = common_len - 1;
a4fc5ed6 1462
bc7d38a4 1463 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1464 pipe_config->has_pch_encoder = true;
1465
03afc4a2 1466 pipe_config->has_dp_encoder = true;
f769cd24 1467 pipe_config->has_drrs = false;
9fcb1704 1468 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1469
dd06f90e
JN		 1470 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1471 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1472 adjusted_mode);
a1b2278e
CK		 1473
1474 if (INTEL_INFO(dev)->gen >= 9) {
1475 int ret;
e435d6e5 1476 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1477 if (ret)
1478 return ret;
1479 }
1480
b5667627 1481 if (HAS_GMCH_DISPLAY(dev))
2dd24552
JB		 1482 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1483 intel_connector->panel.fitting_mode);
1484 else
b074cec8
JB		 1485 intel_pch_panel_fitting(intel_crtc, pipe_config,
1486 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1487 }
1488
cb1793ce 1489 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1490 return false;
1491
083f9560 1492 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1493 "max bw %d pixel clock %iKHz\n",
94ca719e 1494 max_lane_count, common_rates[max_clock],
241bfc38 1495 adjusted_mode->crtc_clock);
083f9560 1496
36008365
DV		 1497 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1498 * bpc in between. */
3e7ca985 1499 bpp = pipe_config->pipe_bpp;
56071a20 1500 if (is_edp(intel_dp)) {
22ce5628
TS		 1501
1502 /* Get bpp from vbt only for panels that dont have bpp in edid */
1503 if (intel_connector->base.display_info.bpc == 0 &&
6aa23e65 1504 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
56071a20 1505 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
6aa23e65
JN		 1506 dev_priv->vbt.edp.bpp);
1507 bpp = dev_priv->vbt.edp.bpp;
56071a20
JN		 1508 }
1509
344c5bbc
JN		 1510 /*
1511 * Use the maximum clock and number of lanes the eDP panel
1512 * advertizes being capable of. The panels are generally
1513 * designed to support only a single clock and lane
1514 * configuration, and typically these values correspond to the
1515 * native resolution of the panel.
1516 */
1517 min_lane_count = max_lane_count;
1518 min_clock = max_clock;
7984211e 1519 }
657445fe 1520
36008365 1521 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1522 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1523 bpp);
36008365 1524
c6930992 1525 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1526 for (lane_count = min_lane_count;
1527 lane_count <= max_lane_count;
1528 lane_count <<= 1) {
1529
94ca719e 1530 link_clock = common_rates[clock];
36008365
DV		 1531 link_avail = intel_dp_max_data_rate(link_clock,
1532 lane_count);
1533
1534 if (mode_rate <= link_avail) {
1535 goto found;
1536 }
1537 }
1538 }
1539 }
c4867936 1540
36008365 1541 return false;
3685a8f3 1542
36008365 1543found:
55bc60db
VS		 1544 if (intel_dp->color_range_auto) {
1545 /*
1546 * See:
1547 * CEA-861-E - 5.1 Default Encoding Parameters
1548 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1549 */
0f2a2a75
VS		 1550 pipe_config->limited_color_range =
1551 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1552 } else {
1553 pipe_config->limited_color_range =
1554 intel_dp->limited_color_range;
55bc60db
VS		 1555 }
1556
90a6b7b0 1557 pipe_config->lane_count = lane_count;
a8f3ef61 1558
657445fe 1559 pipe_config->pipe_bpp = bpp;
94ca719e 1560 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1561
04a60f9f
VS		 1562 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1563 &link_bw, &rate_select);
1564
1565 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1566 link_bw, rate_select, pipe_config->lane_count,
ff9a6750 1567 pipe_config->port_clock, bpp);
36008365
DV		 1568 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1569 mode_rate, link_avail);
a4fc5ed6 1570
03afc4a2 1571 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1572 adjusted_mode->crtc_clock,
1573 pipe_config->port_clock,
03afc4a2 1574 &pipe_config->dp_m_n);
9d1a455b 1575
439d7ac0 1576 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1577 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1578 pipe_config->has_drrs = true;
439d7ac0
PB		 1579 intel_link_compute_m_n(bpp, lane_count,
1580 intel_connector->panel.downclock_mode->clock,
1581 pipe_config->port_clock,
1582 &pipe_config->dp_m2_n2);
1583 }
1584
a3c988ea 1585 if (!HAS_DDI(dev))
840b32b7 1586 intel_dp_set_clock(encoder, pipe_config);
c6bb3538 1587
03afc4a2 1588 return true;
a4fc5ed6
KP		 1589}
1590
901c2daf
VS		 1591void intel_dp_set_link_params(struct intel_dp *intel_dp,
1592 const struct intel_crtc_state *pipe_config)
1593{
1594 intel_dp->link_rate = pipe_config->port_clock;
1595 intel_dp->lane_count = pipe_config->lane_count;
1596}
1597
8ac33ed3 1598static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1599{
b934223d 1600 struct drm_device *dev = encoder->base.dev;
417e822d 1601 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1602 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1603 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1604 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
7c5f93b0 1605 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1606
901c2daf
VS		 1607 intel_dp_set_link_params(intel_dp, crtc->config);
1608
417e822d 1609 /*
1a2eb460 1610 * There are four kinds of DP registers:
417e822d
KP		 1611 *
1612 * IBX PCH
1a2eb460
KP		 1613 * SNB CPU
1614 * IVB CPU
417e822d
KP		 1615 * CPT PCH
1616 *
1617 * IBX PCH and CPU are the same for almost everything,
1618 * except that the CPU DP PLL is configured in this
1619 * register
1620 *
1621 * CPT PCH is quite different, having many bits moved
1622 * to the TRANS_DP_CTL register instead. That
1623 * configuration happens (oddly) in ironlake_pch_enable
1624 */
9c9e7927 1625
417e822d
KP		 1626 /* Preserve the BIOS-computed detected bit. This is
1627 * supposed to be read-only.
1628 */
1629 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1630
417e822d 1631 /* Handle DP bits in common between all three register formats */
417e822d 1632 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
90a6b7b0 1633 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
a4fc5ed6 1634
417e822d 1635 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1636
39e5fa88 1637 if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1638 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1639 intel_dp->DP |= DP_SYNC_HS_HIGH;
1640 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1641 intel_dp->DP |= DP_SYNC_VS_HIGH;
1642 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1643
6aba5b6c 1644 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1645 intel_dp->DP |= DP_ENHANCED_FRAMING;
1646
7c62a164 1647 intel_dp->DP |= crtc->pipe << 29;
39e5fa88 1648 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
e3ef4479
VS		 1649 u32 trans_dp;
1650
39e5fa88 1651 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1652
1653 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1654 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1655 trans_dp |= TRANS_DP_ENH_FRAMING;
1656 else
1657 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1658 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1659 } else {
0f2a2a75 1660 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 1661 !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
0f2a2a75 1662 intel_dp->DP |= DP_COLOR_RANGE_16_235;
417e822d
KP		 1663
1664 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1665 intel_dp->DP |= DP_SYNC_HS_HIGH;
1666 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1667 intel_dp->DP |= DP_SYNC_VS_HIGH;
1668 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1669
6aba5b6c 1670 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1671 intel_dp->DP |= DP_ENHANCED_FRAMING;
1672
39e5fa88 1673 if (IS_CHERRYVIEW(dev))
44f37d1f 1674 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1675 else if (crtc->pipe == PIPE_B)
1676 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1677 }
a4fc5ed6
KP		 1678}
1679
ffd6749d
PZ		 1680#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1681#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1682
1a5ef5b7
PZ		 1683#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1684#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1685
ffd6749d
PZ		 1686#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1687#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1688
4be73780 1689static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1690 u32 mask,
1691 u32 value)
bd943159 1692{
30add22d 1693 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1694 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 1695 i915_reg_t pp_stat_reg, pp_ctrl_reg;
453c5420 1696
e39b999a
VS		 1697 lockdep_assert_held(&dev_priv->pps_mutex);
1698
bf13e81b
JN		 1699 pp_stat_reg = _pp_stat_reg(intel_dp);
1700 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1701
99ea7127 1702 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1703 mask, value,
1704 I915_READ(pp_stat_reg),
1705 I915_READ(pp_ctrl_reg));
32ce697c 1706
3f177625
TU		 1707 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value,
1708 5 * USEC_PER_SEC, 10 * USEC_PER_MSEC))
99ea7127 1709 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1710 I915_READ(pp_stat_reg),
1711 I915_READ(pp_ctrl_reg));
54c136d4
CW		 1712
1713 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1714}
32ce697c 1715
4be73780 1716static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1717{
1718 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1719 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1720}
1721
4be73780 1722static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1723{
1724 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1725 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1726}
1727
4be73780 1728static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127 1729{
d28d4731
AK		 1730 ktime_t panel_power_on_time;
1731 s64 panel_power_off_duration;
1732
99ea7127 1733 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c 1734
d28d4731
AK		 1735 /* take the difference of currrent time and panel power off time
1736 * and then make panel wait for t11_t12 if needed. */
1737 panel_power_on_time = ktime_get_boottime();
1738 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1739
dce56b3c
PZ		 1740 /* When we disable the VDD override bit last we have to do the manual
1741 * wait. */
d28d4731
AK		 1742 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1743 wait_remaining_ms_from_jiffies(jiffies,
1744 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
dce56b3c 1745
4be73780 1746 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1747}
1748
4be73780 1749static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1750{
1751 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1752 intel_dp->backlight_on_delay);
1753}
1754
4be73780 1755static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1756{
1757 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1758 intel_dp->backlight_off_delay);
1759}
99ea7127 1760
832dd3c1
KP		 1761/* Read the current pp_control value, unlocking the register if it
1762 * is locked
1763 */
1764
453c5420 1765static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1766{
453c5420
JB		 1767 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1768 struct drm_i915_private *dev_priv = dev->dev_private;
1769 u32 control;
832dd3c1 1770
e39b999a
VS		 1771 lockdep_assert_held(&dev_priv->pps_mutex);
1772
bf13e81b 1773 control = I915_READ(_pp_ctrl_reg(intel_dp));
b0a08bec
VK		 1774 if (!IS_BROXTON(dev)) {
1775 control &= ~PANEL_UNLOCK_MASK;
1776 control |= PANEL_UNLOCK_REGS;
1777 }
832dd3c1 1778 return control;
bd943159
KP		 1779}
1780
951468f3
VS		 1781/*
1782 * Must be paired with edp_panel_vdd_off().
1783 * Must hold pps_mutex around the whole on/off sequence.
1784 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1785 */
1e0560e0 1786static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1787{
30add22d 1788 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1789 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1790 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1791 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1792 enum intel_display_power_domain power_domain;
5d613501 1793 u32 pp;
f0f59a00 1794 i915_reg_t pp_stat_reg, pp_ctrl_reg;
adddaaf4 1795 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1796
e39b999a
VS		 1797 lockdep_assert_held(&dev_priv->pps_mutex);
1798
97af61f5 1799 if (!is_edp(intel_dp))
adddaaf4 1800 return false;
bd943159 1801
2c623c11 1802 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1803 intel_dp->want_panel_vdd = true;
99ea7127 1804
4be73780 1805 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1806 return need_to_disable;
b0665d57 1807
25f78f58 1808 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 1809 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1810
3936fcf4
VS		 1811 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1812 port_name(intel_dig_port->port));
bd943159 1813
4be73780
DV		 1814 if (!edp_have_panel_power(intel_dp))
1815 wait_panel_power_cycle(intel_dp);
99ea7127 1816
453c5420 1817 pp = ironlake_get_pp_control(intel_dp);
5d613501 1818 pp |= EDP_FORCE_VDD;
ebf33b18 1819
bf13e81b
JN		 1820 pp_stat_reg = _pp_stat_reg(intel_dp);
1821 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1822
1823 I915_WRITE(pp_ctrl_reg, pp);
1824 POSTING_READ(pp_ctrl_reg);
1825 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1826 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1827 /*
1828 * If the panel wasn't on, delay before accessing aux channel
1829 */
4be73780 1830 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1831 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1832 port_name(intel_dig_port->port));
f01eca2e 1833 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1834 }
adddaaf4
JN		 1835
1836 return need_to_disable;
1837}
1838
951468f3
VS		 1839/*
1840 * Must be paired with intel_edp_panel_vdd_off() or
1841 * intel_edp_panel_off().
1842 * Nested calls to these functions are not allowed since
1843 * we drop the lock. Caller must use some higher level
1844 * locking to prevent nested calls from other threads.
1845 */
b80d6c78 1846void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1847{
c695b6b6 1848 bool vdd;
adddaaf4 1849
c695b6b6
VS		 1850 if (!is_edp(intel_dp))
1851 return;
1852
773538e8 1853 pps_lock(intel_dp);
c695b6b6 1854 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1855 pps_unlock(intel_dp);
c695b6b6 1856
e2c719b7 1857 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1858 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1859}
1860
4be73780 1861static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1862{
30add22d 1863 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1864 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1865 struct intel_digital_port *intel_dig_port =
1866 dp_to_dig_port(intel_dp);
1867 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1868 enum intel_display_power_domain power_domain;
5d613501 1869 u32 pp;
f0f59a00 1870 i915_reg_t pp_stat_reg, pp_ctrl_reg;
5d613501 1871
e39b999a 1872 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1873
15e899a0 1874 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1875
15e899a0 1876 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1877 return;
b0665d57 1878
3936fcf4
VS		 1879 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1880 port_name(intel_dig_port->port));
bd943159 1881
be2c9196
VS		 1882 pp = ironlake_get_pp_control(intel_dp);
1883 pp &= ~EDP_FORCE_VDD;
453c5420 1884
be2c9196
VS		 1885 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1886 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1887
be2c9196
VS		 1888 I915_WRITE(pp_ctrl_reg, pp);
1889 POSTING_READ(pp_ctrl_reg);
90791a5c 1890
be2c9196
VS		 1891 /* Make sure sequencer is idle before allowing subsequent activity */
1892 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1893 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1894
be2c9196 1895 if ((pp & POWER_TARGET_ON) == 0)
d28d4731 1896 intel_dp->panel_power_off_time = ktime_get_boottime();
e9cb81a2 1897
25f78f58 1898 power_domain = intel_display_port_aux_power_domain(intel_encoder);
be2c9196 1899 intel_display_power_put(dev_priv, power_domain);
bd943159 1900}
5d613501 1901
4be73780 1902static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1903{
1904 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1905 struct intel_dp, panel_vdd_work);
bd943159 1906
773538e8 1907 pps_lock(intel_dp);
15e899a0
VS		 1908 if (!intel_dp->want_panel_vdd)
1909 edp_panel_vdd_off_sync(intel_dp);
773538e8 1910 pps_unlock(intel_dp);
bd943159
KP		 1911}
1912
aba86890
ID		 1913static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1914{
1915 unsigned long delay;
1916
1917 /*
1918 * Queue the timer to fire a long time from now (relative to the power
1919 * down delay) to keep the panel power up across a sequence of
1920 * operations.
1921 */
1922 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1923 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1924}
1925
951468f3
VS		 1926/*
1927 * Must be paired with edp_panel_vdd_on().
1928 * Must hold pps_mutex around the whole on/off sequence.
1929 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1930 */
4be73780 1931static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1932{
e39b999a
VS		 1933 struct drm_i915_private *dev_priv =
1934 intel_dp_to_dev(intel_dp)->dev_private;
1935
1936 lockdep_assert_held(&dev_priv->pps_mutex);
1937
97af61f5
KP		 1938 if (!is_edp(intel_dp))
1939 return;
5d613501 1940
e2c719b7 1941 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1942 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1943
bd943159
KP		 1944 intel_dp->want_panel_vdd = false;
1945
aba86890 1946 if (sync)
4be73780 1947 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1948 else
1949 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1950}
1951
9f0fb5be 1952static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1953{
30add22d 1954 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1955 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1956 u32 pp;
f0f59a00 1957 i915_reg_t pp_ctrl_reg;
9934c132 1958
9f0fb5be
VS		 1959 lockdep_assert_held(&dev_priv->pps_mutex);
1960
97af61f5 1961 if (!is_edp(intel_dp))
bd943159 1962 return;
99ea7127 1963
3936fcf4
VS		 1964 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1965 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1966
e7a89ace
VS		 1967 if (WARN(edp_have_panel_power(intel_dp),
1968 "eDP port %c panel power already on\n",
1969 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1970 return;
9934c132 1971
4be73780 1972 wait_panel_power_cycle(intel_dp);
37c6c9b0 1973
bf13e81b 1974 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1975 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1976 if (IS_GEN5(dev)) {
1977 /* ILK workaround: disable reset around power sequence */
1978 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1979 I915_WRITE(pp_ctrl_reg, pp);
1980 POSTING_READ(pp_ctrl_reg);
05ce1a49 1981 }
37c6c9b0 1982
1c0ae80a 1983 pp |= POWER_TARGET_ON;
99ea7127
KP		 1984 if (!IS_GEN5(dev))
1985 pp |= PANEL_POWER_RESET;
1986
453c5420
JB		 1987 I915_WRITE(pp_ctrl_reg, pp);
1988 POSTING_READ(pp_ctrl_reg);
9934c132 1989
4be73780 1990 wait_panel_on(intel_dp);
dce56b3c 1991 intel_dp->last_power_on = jiffies;
9934c132 1992
05ce1a49
KP		 1993 if (IS_GEN5(dev)) {
1994 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1995 I915_WRITE(pp_ctrl_reg, pp);
1996 POSTING_READ(pp_ctrl_reg);
05ce1a49 1997 }
9f0fb5be 1998}
e39b999a 1999
9f0fb5be
VS		 2000void intel_edp_panel_on(struct intel_dp *intel_dp)
2001{
2002 if (!is_edp(intel_dp))
2003 return;
2004
2005 pps_lock(intel_dp);
2006 edp_panel_on(intel_dp);
773538e8 2007 pps_unlock(intel_dp);
9934c132
JB		 2008}
2009
9f0fb5be
VS		 2010
2011static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 2012{
4e6e1a54
ID		 2013 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2014 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 2015 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 2016 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 2017 enum intel_display_power_domain power_domain;
99ea7127 2018 u32 pp;
f0f59a00 2019 i915_reg_t pp_ctrl_reg;
9934c132 2020
9f0fb5be
VS		 2021 lockdep_assert_held(&dev_priv->pps_mutex);
2022
97af61f5
KP		 2023 if (!is_edp(intel_dp))
2024 return;
37c6c9b0 2025
3936fcf4
VS		 2026 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2027 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 2028
3936fcf4
VS		 2029 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2030 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 2031
453c5420 2032 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 2033 /* We need to switch off panel power _and_ force vdd, for otherwise some
2034 * panels get very unhappy and cease to work. */
b3064154
PJ		 2035 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2036 EDP_BLC_ENABLE);
453c5420 2037
bf13e81b 2038 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2039
849e39f5
PZ		 2040 intel_dp->want_panel_vdd = false;
2041
453c5420
JB		 2042 I915_WRITE(pp_ctrl_reg, pp);
2043 POSTING_READ(pp_ctrl_reg);
9934c132 2044
d28d4731 2045 intel_dp->panel_power_off_time = ktime_get_boottime();
4be73780 2046 wait_panel_off(intel_dp);
849e39f5
PZ		 2047
2048 /* We got a reference when we enabled the VDD. */
25f78f58 2049 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 2050 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 2051}
e39b999a 2052
9f0fb5be
VS		 2053void intel_edp_panel_off(struct intel_dp *intel_dp)
2054{
2055 if (!is_edp(intel_dp))
2056 return;
e39b999a 2057
9f0fb5be
VS		 2058 pps_lock(intel_dp);
2059 edp_panel_off(intel_dp);
773538e8 2060 pps_unlock(intel_dp);
9934c132
JB		 2061}
2062
1250d107
JN		 2063/* Enable backlight in the panel power control. */
2064static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2065{
da63a9f2
PZ		 2066 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2067 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 2068 struct drm_i915_private *dev_priv = dev->dev_private;
2069 u32 pp;
f0f59a00 2070 i915_reg_t pp_ctrl_reg;
32f9d658 2071
01cb9ea6
JB		 2072 /*
2073 * If we enable the backlight right away following a panel power
2074 * on, we may see slight flicker as the panel syncs with the eDP
2075 * link. So delay a bit to make sure the image is solid before
2076 * allowing it to appear.
2077 */
4be73780 2078 wait_backlight_on(intel_dp);
e39b999a 2079
773538e8 2080 pps_lock(intel_dp);
e39b999a 2081
453c5420 2082 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2083 pp |= EDP_BLC_ENABLE;
453c5420 2084
bf13e81b 2085 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2086
2087 I915_WRITE(pp_ctrl_reg, pp);
2088 POSTING_READ(pp_ctrl_reg);
e39b999a 2089
773538e8 2090 pps_unlock(intel_dp);
32f9d658
ZW		 2091}
2092
1250d107
JN		 2093/* Enable backlight PWM and backlight PP control. */
2094void intel_edp_backlight_on(struct intel_dp *intel_dp)
2095{
2096 if (!is_edp(intel_dp))
2097 return;
2098
2099 DRM_DEBUG_KMS("\n");
2100
2101 intel_panel_enable_backlight(intel_dp->attached_connector);
2102 _intel_edp_backlight_on(intel_dp);
2103}
2104
2105/* Disable backlight in the panel power control. */
2106static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2107{
30add22d 2108 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 2109 struct drm_i915_private *dev_priv = dev->dev_private;
2110 u32 pp;
f0f59a00 2111 i915_reg_t pp_ctrl_reg;
32f9d658 2112
f01eca2e
KP		 2113 if (!is_edp(intel_dp))
2114 return;
2115
773538e8 2116 pps_lock(intel_dp);
e39b999a 2117
453c5420 2118 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2119 pp &= ~EDP_BLC_ENABLE;
453c5420 2120
bf13e81b 2121 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2122
2123 I915_WRITE(pp_ctrl_reg, pp);
2124 POSTING_READ(pp_ctrl_reg);
f7d2323c 2125
773538e8 2126 pps_unlock(intel_dp);
e39b999a
VS		 2127
2128 intel_dp->last_backlight_off = jiffies;
f7d2323c 2129 edp_wait_backlight_off(intel_dp);
1250d107 2130}
f7d2323c 2131
1250d107
JN		 2132/* Disable backlight PP control and backlight PWM. */
2133void intel_edp_backlight_off(struct intel_dp *intel_dp)
2134{
2135 if (!is_edp(intel_dp))
2136 return;
2137
2138 DRM_DEBUG_KMS("\n");
f7d2323c 2139
1250d107 2140 _intel_edp_backlight_off(intel_dp);
f7d2323c 2141 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2142}
a4fc5ed6 2143
73580fb7
JN		 2144/*
2145 * Hook for controlling the panel power control backlight through the bl_power
2146 * sysfs attribute. Take care to handle multiple calls.
2147 */
2148static void intel_edp_backlight_power(struct intel_connector *connector,
2149 bool enable)
2150{
2151 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2152 bool is_enabled;
2153
773538e8 2154 pps_lock(intel_dp);
e39b999a 2155 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2156 pps_unlock(intel_dp);
73580fb7
JN		 2157
2158 if (is_enabled == enable)
2159 return;
2160
23ba9373
JN		 2161 DRM_DEBUG_KMS("panel power control backlight %s\n",
2162 enable ? "enable" : "disable");
73580fb7
JN		 2163
2164 if (enable)
2165 _intel_edp_backlight_on(intel_dp);
2166 else
2167 _intel_edp_backlight_off(intel_dp);
2168}
2169
64e1077a
VS		 2170static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2171{
2172 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2173 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2174 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2175
2176 I915_STATE_WARN(cur_state != state,
2177 "DP port %c state assertion failure (expected %s, current %s)\n",
2178 port_name(dig_port->port),
87ad3212 2179 onoff(state), onoff(cur_state));
64e1077a
VS		 2180}
2181#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2182
2183static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2184{
2185 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2186
2187 I915_STATE_WARN(cur_state != state,
2188 "eDP PLL state assertion failure (expected %s, current %s)\n",
87ad3212 2189 onoff(state), onoff(cur_state));
64e1077a
VS		 2190}
2191#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2192#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2193
2bd2ad64 2194static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2195{
da63a9f2 2196 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2197 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2198 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2199
64e1077a
VS		 2200 assert_pipe_disabled(dev_priv, crtc->pipe);
2201 assert_dp_port_disabled(intel_dp);
2202 assert_edp_pll_disabled(dev_priv);
2bd2ad64 2203
abfce949
VS		 2204 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2205 crtc->config->port_clock);
2206
2207 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2208
2209 if (crtc->config->port_clock == 162000)
2210 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2211 else
2212 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2213
2214 I915_WRITE(DP_A, intel_dp->DP);
2215 POSTING_READ(DP_A);
2216 udelay(500);
2217
0767935e 2218 intel_dp->DP |= DP_PLL_ENABLE;
6fec7662 2219
0767935e 2220 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2221 POSTING_READ(DP_A);
2222 udelay(200);
d240f20f
JB		 2223}
2224
2bd2ad64 2225static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2226{
da63a9f2 2227 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2228 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2229 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2230
64e1077a
VS		 2231 assert_pipe_disabled(dev_priv, crtc->pipe);
2232 assert_dp_port_disabled(intel_dp);
2233 assert_edp_pll_enabled(dev_priv);
2bd2ad64 2234
abfce949
VS		 2235 DRM_DEBUG_KMS("disabling eDP PLL\n");
2236
6fec7662 2237 intel_dp->DP &= ~DP_PLL_ENABLE;
0767935e 2238
6fec7662 2239 I915_WRITE(DP_A, intel_dp->DP);
1af5fa1b 2240 POSTING_READ(DP_A);
d240f20f
JB		 2241 udelay(200);
2242}
2243
c7ad3810 2244/* If the sink supports it, try to set the power state appropriately */
c19b0669 2245void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2246{
2247 int ret, i;
2248
2249 /* Should have a valid DPCD by this point */
2250 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2251 return;
2252
2253 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2254 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2255 DP_SET_POWER_D3);
c7ad3810
JB		 2256 } else {
2257 /*
2258 * When turning on, we need to retry for 1ms to give the sink
2259 * time to wake up.
2260 */
2261 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2262 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2263 DP_SET_POWER_D0);
c7ad3810
JB		 2264 if (ret == 1)
2265 break;
2266 msleep(1);
2267 }
2268 }
f9cac721
JN		 2269
2270 if (ret != 1)
2271 DRM_DEBUG_KMS("failed to %s sink power state\n",
2272 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2273}
2274
19d8fe15
DV		 2275static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2276 enum pipe *pipe)
d240f20f 2277{
19d8fe15 2278 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2279 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2280 struct drm_device *dev = encoder->base.dev;
2281 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2282 enum intel_display_power_domain power_domain;
2283 u32 tmp;
6fa9a5ec 2284 bool ret;
6d129bea
ID		 2285
2286 power_domain = intel_display_port_power_domain(encoder);
6fa9a5ec 2287 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 2288 return false;
2289
6fa9a5ec
ID		 2290 ret = false;
2291
6d129bea 2292 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2293
2294 if (!(tmp & DP_PORT_EN))
6fa9a5ec 2295 goto out;
19d8fe15 2296
39e5fa88 2297 if (IS_GEN7(dev) && port == PORT_A) {
19d8fe15 2298 *pipe = PORT_TO_PIPE_CPT(tmp);
39e5fa88 2299 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
adc289d7 2300 enum pipe p;
19d8fe15 2301
adc289d7
VS		 2302 for_each_pipe(dev_priv, p) {
2303 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2304 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2305 *pipe = p;
6fa9a5ec
ID		 2306 ret = true;
2307
2308 goto out;
19d8fe15
DV		 2309 }
2310 }
19d8fe15 2311
4a0833ec 2312 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
f0f59a00 2313 i915_mmio_reg_offset(intel_dp->output_reg));
39e5fa88
VS		 2314 } else if (IS_CHERRYVIEW(dev)) {
2315 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2316 } else {
2317 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2318 }
d240f20f 2319
6fa9a5ec
ID		 2320 ret = true;
2321
2322out:
2323 intel_display_power_put(dev_priv, power_domain);
2324
2325 return ret;
19d8fe15 2326}
d240f20f 2327
045ac3b5 2328static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2329 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2330{
2331 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2332 u32 tmp, flags = 0;
63000ef6
XZ		 2333 struct drm_device *dev = encoder->base.dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 enum port port = dp_to_dig_port(intel_dp)->port;
2336 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 2337
9ed109a7 2338 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2339
2340 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2341
39e5fa88 2342 if (HAS_PCH_CPT(dev) && port != PORT_A) {
b81e34c2
VS		 2343 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2344
2345 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2346 flags |= DRM_MODE_FLAG_PHSYNC;
2347 else
2348 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2349
b81e34c2 2350 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2351 flags |= DRM_MODE_FLAG_PVSYNC;
2352 else
2353 flags |= DRM_MODE_FLAG_NVSYNC;
2354 } else {
39e5fa88 2355 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2356 flags |= DRM_MODE_FLAG_PHSYNC;
2357 else
2358 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2359
39e5fa88 2360 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2361 flags |= DRM_MODE_FLAG_PVSYNC;
2362 else
2363 flags |= DRM_MODE_FLAG_NVSYNC;
2364 }
045ac3b5 2365
2d112de7 2366 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2367
8c875fca 2368 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 2369 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
8c875fca
VS		 2370 pipe_config->limited_color_range = true;
2371
eb14cb74
VS		 2372 pipe_config->has_dp_encoder = true;
2373
90a6b7b0
VS		 2374 pipe_config->lane_count =
2375 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2376
eb14cb74
VS		 2377 intel_dp_get_m_n(crtc, pipe_config);
2378
18442d08 2379 if (port == PORT_A) {
b377e0df 2380 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
f1f644dc
JB		 2381 pipe_config->port_clock = 162000;
2382 else
2383 pipe_config->port_clock = 270000;
2384 }
18442d08 2385
e3b247da
VS		 2386 pipe_config->base.adjusted_mode.crtc_clock =
2387 intel_dotclock_calculate(pipe_config->port_clock,
2388 &pipe_config->dp_m_n);
7f16e5c1 2389
6aa23e65
JN		 2390 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2391 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
c6cd2ee2
JN		 2392 /*
2393 * This is a big fat ugly hack.
2394 *
2395 * Some machines in UEFI boot mode provide us a VBT that has 18
2396 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2397 * unknown we fail to light up. Yet the same BIOS boots up with
2398 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2399 * max, not what it tells us to use.
2400 *
2401 * Note: This will still be broken if the eDP panel is not lit
2402 * up by the BIOS, and thus we can't get the mode at module
2403 * load.
2404 */
2405 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2406 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2407 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
c6cd2ee2 2408 }
045ac3b5
JB		 2409}
2410
e8cb4558 2411static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2412{
e8cb4558 2413 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2414 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2415 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2416
6e3c9717 2417 if (crtc->config->has_audio)
495a5bb8 2418 intel_audio_codec_disable(encoder);
6cb49835 2419
b32c6f48
RV		 2420 if (HAS_PSR(dev) && !HAS_DDI(dev))
2421 intel_psr_disable(intel_dp);
2422
6cb49835
DV		 2423 /* Make sure the panel is off before trying to change the mode. But also
2424 * ensure that we have vdd while we switch off the panel. */
24f3e092 2425 intel_edp_panel_vdd_on(intel_dp);
4be73780 2426 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2427 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2428 intel_edp_panel_off(intel_dp);
3739850b 2429
08aff3fe
VS		 2430 /* disable the port before the pipe on g4x */
2431 if (INTEL_INFO(dev)->gen < 5)
3739850b 2432 intel_dp_link_down(intel_dp);
d240f20f
JB		 2433}
2434
08aff3fe 2435static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2436{
2bd2ad64 2437 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2438 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2439
49277c31 2440 intel_dp_link_down(intel_dp);
abfce949
VS		 2441
2442 /* Only ilk+ has port A */
08aff3fe
VS		 2443 if (port == PORT_A)
2444 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2445}
2446
2447static void vlv_post_disable_dp(struct intel_encoder *encoder)
2448{
2449 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2450
2451 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2452}
2453
a8f327fb
VS		 2454static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
2455 bool reset)
580d3811 2456{
a8f327fb
VS		 2457 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2458 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
2459 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2460 enum pipe pipe = crtc->pipe;
2461 uint32_t val;
580d3811 2462
a8f327fb
VS		 2463 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2464 if (reset)
2465 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2466 else
2467 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2468 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
580d3811 2469
a8f327fb
VS		 2470 if (crtc->config->lane_count > 2) {
2471 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2472 if (reset)
2473 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2474 else
2475 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2476 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2477 }
580d3811 2478
97fd4d5c 2479 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2480 val |= CHV_PCS_REQ_SOFTRESET_EN;
a8f327fb
VS		 2481 if (reset)
2482 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2483 else
2484 val |= DPIO_PCS_CLK_SOFT_RESET;
97fd4d5c 2485 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2486
a8f327fb 2487 if (crtc->config->lane_count > 2) {
e0fce78f
VS		 2488 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2489 val |= CHV_PCS_REQ_SOFTRESET_EN;
a8f327fb
VS		 2490 if (reset)
2491 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2492 else
2493 val |= DPIO_PCS_CLK_SOFT_RESET;
e0fce78f
VS		 2494 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2495 }
a8f327fb 2496}
97fd4d5c 2497
a8f327fb
VS		 2498static void chv_post_disable_dp(struct intel_encoder *encoder)
2499{
2500 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2501 struct drm_device *dev = encoder->base.dev;
2502 struct drm_i915_private *dev_priv = dev->dev_private;
97fd4d5c 2503
a8f327fb
VS		 2504 intel_dp_link_down(intel_dp);
2505
2506 mutex_lock(&dev_priv->sb_lock);
2507
2508 /* Assert data lane reset */
2509 chv_data_lane_soft_reset(encoder, true);
580d3811 2510
a580516d 2511 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2512}
2513
7b13b58a
VS		 2514static void
2515_intel_dp_set_link_train(struct intel_dp *intel_dp,
2516 uint32_t *DP,
2517 uint8_t dp_train_pat)
2518{
2519 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2520 struct drm_device *dev = intel_dig_port->base.base.dev;
2521 struct drm_i915_private *dev_priv = dev->dev_private;
2522 enum port port = intel_dig_port->port;
2523
2524 if (HAS_DDI(dev)) {
2525 uint32_t temp = I915_READ(DP_TP_CTL(port));
2526
2527 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2528 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2529 else
2530 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2531
2532 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2533 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2534 case DP_TRAINING_PATTERN_DISABLE:
2535 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2536
2537 break;
2538 case DP_TRAINING_PATTERN_1:
2539 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2540 break;
2541 case DP_TRAINING_PATTERN_2:
2542 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2543 break;
2544 case DP_TRAINING_PATTERN_3:
2545 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2546 break;
2547 }
2548 I915_WRITE(DP_TP_CTL(port), temp);
2549
39e5fa88
VS		 2550 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2551 (HAS_PCH_CPT(dev) && port != PORT_A)) {
7b13b58a
VS		 2552 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2553
2554 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2555 case DP_TRAINING_PATTERN_DISABLE:
2556 *DP |= DP_LINK_TRAIN_OFF_CPT;
2557 break;
2558 case DP_TRAINING_PATTERN_1:
2559 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2560 break;
2561 case DP_TRAINING_PATTERN_2:
2562 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2563 break;
2564 case DP_TRAINING_PATTERN_3:
2565 DRM_ERROR("DP training pattern 3 not supported\n");
2566 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2567 break;
2568 }
2569
2570 } else {
2571 if (IS_CHERRYVIEW(dev))
2572 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2573 else
2574 *DP &= ~DP_LINK_TRAIN_MASK;
2575
2576 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2577 case DP_TRAINING_PATTERN_DISABLE:
2578 *DP |= DP_LINK_TRAIN_OFF;
2579 break;
2580 case DP_TRAINING_PATTERN_1:
2581 *DP |= DP_LINK_TRAIN_PAT_1;
2582 break;
2583 case DP_TRAINING_PATTERN_2:
2584 *DP |= DP_LINK_TRAIN_PAT_2;
2585 break;
2586 case DP_TRAINING_PATTERN_3:
2587 if (IS_CHERRYVIEW(dev)) {
2588 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2589 } else {
2590 DRM_ERROR("DP training pattern 3 not supported\n");
2591 *DP |= DP_LINK_TRAIN_PAT_2;
2592 }
2593 break;
2594 }
2595 }
2596}
2597
2598static void intel_dp_enable_port(struct intel_dp *intel_dp)
2599{
2600 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2601 struct drm_i915_private *dev_priv = dev->dev_private;
6fec7662
VS		 2602 struct intel_crtc *crtc =
2603 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
7b13b58a 2604
7b13b58a
VS		 2605 /* enable with pattern 1 (as per spec) */
2606 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2607 DP_TRAINING_PATTERN_1);
2608
2609 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2610 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2611
2612 /*
2613 * Magic for VLV/CHV. We _must_ first set up the register
2614 * without actually enabling the port, and then do another
2615 * write to enable the port. Otherwise link training will
2616 * fail when the power sequencer is freshly used for this port.
2617 */
2618 intel_dp->DP |= DP_PORT_EN;
6fec7662
VS		 2619 if (crtc->config->has_audio)
2620 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
7b713f50
VS		 2621
2622 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2623 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2624}
2625
e8cb4558 2626static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2627{
e8cb4558
DV		 2628 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2629 struct drm_device *dev = encoder->base.dev;
2630 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2631 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2632 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
d6fbdd15
VS		 2633 enum port port = dp_to_dig_port(intel_dp)->port;
2634 enum pipe pipe = crtc->pipe;
5d613501 2635
0c33d8d7
DV		 2636 if (WARN_ON(dp_reg & DP_PORT_EN))
2637 return;
5d613501 2638
093e3f13
VS		 2639 pps_lock(intel_dp);
2640
666a4537 2641 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
093e3f13
VS		 2642 vlv_init_panel_power_sequencer(intel_dp);
2643
7864578a
VS		 2644 /*
2645 * We get an occasional spurious underrun between the port
2646 * enable and vdd enable, when enabling port A eDP.
2647 *
2648 * FIXME: Not sure if this applies to (PCH) port D eDP as well
2649 */
2650 if (port == PORT_A)
2651 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2652
7b13b58a 2653 intel_dp_enable_port(intel_dp);
093e3f13 2654
d6fbdd15
VS		 2655 if (port == PORT_A && IS_GEN5(dev_priv)) {
2656 /*
2657 * Underrun reporting for the other pipe was disabled in
2658 * g4x_pre_enable_dp(). The eDP PLL and port have now been
2659 * enabled, so it's now safe to re-enable underrun reporting.
2660 */
2661 intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
2662 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
2663 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
2664 }
2665
093e3f13
VS		 2666 edp_panel_vdd_on(intel_dp);
2667 edp_panel_on(intel_dp);
2668 edp_panel_vdd_off(intel_dp, true);
2669
7864578a
VS		 2670 if (port == PORT_A)
2671 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2672
093e3f13
VS		 2673 pps_unlock(intel_dp);
2674
666a4537 2675 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e0fce78f
VS		 2676 unsigned int lane_mask = 0x0;
2677
2678 if (IS_CHERRYVIEW(dev))
2679 lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2680
9b6de0a1
VS		 2681 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2682 lane_mask);
e0fce78f 2683 }
61234fa5 2684
f01eca2e 2685 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2686 intel_dp_start_link_train(intel_dp);
3ab9c637 2687 intel_dp_stop_link_train(intel_dp);
c1dec79a 2688
6e3c9717 2689 if (crtc->config->has_audio) {
c1dec79a 2690 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
d6fbdd15 2691 pipe_name(pipe));
c1dec79a
JN		 2692 intel_audio_codec_enable(encoder);
2693 }
ab1f90f9 2694}
89b667f8 2695
ecff4f3b
JN		 2696static void g4x_enable_dp(struct intel_encoder *encoder)
2697{
828f5c6e
JN		 2698 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2699
ecff4f3b 2700 intel_enable_dp(encoder);
4be73780 2701 intel_edp_backlight_on(intel_dp);
ab1f90f9 2702}
89b667f8 2703
ab1f90f9
JN		 2704static void vlv_enable_dp(struct intel_encoder *encoder)
2705{
828f5c6e
JN		 2706 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2707
4be73780 2708 intel_edp_backlight_on(intel_dp);
b32c6f48 2709 intel_psr_enable(intel_dp);
d240f20f
JB		 2710}
2711
ecff4f3b 2712static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9 2713{
d6fbdd15 2714 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ab1f90f9 2715 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6fbdd15
VS		 2716 enum port port = dp_to_dig_port(intel_dp)->port;
2717 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
ab1f90f9 2718
8ac33ed3
DV		 2719 intel_dp_prepare(encoder);
2720
d6fbdd15
VS		 2721 if (port == PORT_A && IS_GEN5(dev_priv)) {
2722 /*
2723 * We get FIFO underruns on the other pipe when
2724 * enabling the CPU eDP PLL, and when enabling CPU
2725 * eDP port. We could potentially avoid the PLL
2726 * underrun with a vblank wait just prior to enabling
2727 * the PLL, but that doesn't appear to help the port
2728 * enable case. Just sweep it all under the rug.
2729 */
2730 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
2731 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
2732 }
2733
d41f1efb 2734 /* Only ilk+ has port A */
abfce949 2735 if (port == PORT_A)
ab1f90f9
JN		 2736 ironlake_edp_pll_on(intel_dp);
2737}
2738
83b84597
VS		 2739static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2740{
2741 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2742 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2743 enum pipe pipe = intel_dp->pps_pipe;
f0f59a00 2744 i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
83b84597
VS		 2745
2746 edp_panel_vdd_off_sync(intel_dp);
2747
2748 /*
2749 * VLV seems to get confused when multiple power seqeuencers
2750 * have the same port selected (even if only one has power/vdd
2751 * enabled). The failure manifests as vlv_wait_port_ready() failing
2752 * CHV on the other hand doesn't seem to mind having the same port
2753 * selected in multiple power seqeuencers, but let's clear the
2754 * port select always when logically disconnecting a power sequencer
2755 * from a port.
2756 */
2757 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2758 pipe_name(pipe), port_name(intel_dig_port->port));
2759 I915_WRITE(pp_on_reg, 0);
2760 POSTING_READ(pp_on_reg);
2761
2762 intel_dp->pps_pipe = INVALID_PIPE;
2763}
2764
a4a5d2f8
VS		 2765static void vlv_steal_power_sequencer(struct drm_device *dev,
2766 enum pipe pipe)
2767{
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 struct intel_encoder *encoder;
2770
2771 lockdep_assert_held(&dev_priv->pps_mutex);
2772
ac3c12e4
VS		 2773 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2774 return;
2775
19c8054c 2776 for_each_intel_encoder(dev, encoder) {
a4a5d2f8 2777 struct intel_dp *intel_dp;
773538e8 2778 enum port port;
a4a5d2f8
VS		 2779
2780 if (encoder->type != INTEL_OUTPUT_EDP)
2781 continue;
2782
2783 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2784 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2785
2786 if (intel_dp->pps_pipe != pipe)
2787 continue;
2788
2789 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2790 pipe_name(pipe), port_name(port));
a4a5d2f8 2791
e02f9a06 2792 WARN(encoder->base.crtc,
034e43c6
VS		 2793 "stealing pipe %c power sequencer from active eDP port %c\n",
2794 pipe_name(pipe), port_name(port));
a4a5d2f8 2795
a4a5d2f8 2796 /* make sure vdd is off before we steal it */
83b84597 2797 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2798 }
2799}
2800
2801static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2802{
2803 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2804 struct intel_encoder *encoder = &intel_dig_port->base;
2805 struct drm_device *dev = encoder->base.dev;
2806 struct drm_i915_private *dev_priv = dev->dev_private;
2807 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2808
2809 lockdep_assert_held(&dev_priv->pps_mutex);
2810
093e3f13
VS		 2811 if (!is_edp(intel_dp))
2812 return;
2813
a4a5d2f8
VS		 2814 if (intel_dp->pps_pipe == crtc->pipe)
2815 return;
2816
2817 /*
2818 * If another power sequencer was being used on this
2819 * port previously make sure to turn off vdd there while
2820 * we still have control of it.
2821 */
2822 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2823 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2824
2825 /*
2826 * We may be stealing the power
2827 * sequencer from another port.
2828 */
2829 vlv_steal_power_sequencer(dev, crtc->pipe);
2830
2831 /* now it's all ours */
2832 intel_dp->pps_pipe = crtc->pipe;
2833
2834 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2835 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2836
2837 /* init power sequencer on this pipe and port */
36b5f425
VS		 2838 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2839 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2840}
2841
ab1f90f9 2842static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2843{
2bd2ad64 2844 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2845 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2846 struct drm_device *dev = encoder->base.dev;
89b667f8 2847 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2848 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2849 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2850 int pipe = intel_crtc->pipe;
2851 u32 val;
a4fc5ed6 2852
a580516d 2853 mutex_lock(&dev_priv->sb_lock);
89b667f8 2854
ab3c759a 2855 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2856 val = 0;
2857 if (pipe)
2858 val |= (1<<21);
2859 else
2860 val &= ~(1<<21);
2861 val |= 0x001000c4;
ab3c759a
CML		 2862 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2863 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2864 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2865
a580516d 2866 mutex_unlock(&dev_priv->sb_lock);
ab1f90f9
JN		 2867
2868 intel_enable_dp(encoder);
89b667f8
JB		 2869}
2870
ecff4f3b 2871static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2872{
2873 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2874 struct drm_device *dev = encoder->base.dev;
2875 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2876 struct intel_crtc *intel_crtc =
2877 to_intel_crtc(encoder->base.crtc);
e4607fcf 2878 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2879 int pipe = intel_crtc->pipe;
89b667f8 2880
8ac33ed3
DV		 2881 intel_dp_prepare(encoder);
2882
89b667f8 2883 /* Program Tx lane resets to default */
a580516d 2884 mutex_lock(&dev_priv->sb_lock);
ab3c759a 2885 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2886 DPIO_PCS_TX_LANE2_RESET |
2887 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2888 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2889 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2890 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2891 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2892 DPIO_PCS_CLK_SOFT_RESET);
2893
2894 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2895 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2896 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2897 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
a580516d 2898 mutex_unlock(&dev_priv->sb_lock);
a4fc5ed6
KP		 2899}
2900
e4a1d846
CML		 2901static void chv_pre_enable_dp(struct intel_encoder *encoder)
2902{
2903 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2904 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2905 struct drm_device *dev = encoder->base.dev;
2906 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2907 struct intel_crtc *intel_crtc =
2908 to_intel_crtc(encoder->base.crtc);
2909 enum dpio_channel ch = vlv_dport_to_channel(dport);
2910 int pipe = intel_crtc->pipe;
2e523e98 2911 int data, i, stagger;
949c1d43 2912 u32 val;
e4a1d846 2913
a580516d 2914 mutex_lock(&dev_priv->sb_lock);
949c1d43 2915
570e2a74
VS		 2916 /* allow hardware to manage TX FIFO reset source */
2917 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2918 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2919 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2920
e0fce78f
VS		 2921 if (intel_crtc->config->lane_count > 2) {
2922 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2923 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2924 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2925 }
570e2a74 2926
949c1d43 2927 /* Program Tx lane latency optimal setting*/
e0fce78f 2928 for (i = 0; i < intel_crtc->config->lane_count; i++) {
e4a1d846 2929 /* Set the upar bit */
e0fce78f
VS		 2930 if (intel_crtc->config->lane_count == 1)
2931 data = 0x0;
2932 else
2933 data = (i == 1) ? 0x0 : 0x1;
e4a1d846
CML		 2934 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2935 data << DPIO_UPAR_SHIFT);
2936 }
2937
2938 /* Data lane stagger programming */
2e523e98
VS		 2939 if (intel_crtc->config->port_clock > 270000)
2940 stagger = 0x18;
2941 else if (intel_crtc->config->port_clock > 135000)
2942 stagger = 0xd;
2943 else if (intel_crtc->config->port_clock > 67500)
2944 stagger = 0x7;
2945 else if (intel_crtc->config->port_clock > 33750)
2946 stagger = 0x4;
2947 else
2948 stagger = 0x2;
2949
2950 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2951 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2952 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2953
e0fce78f
VS		 2954 if (intel_crtc->config->lane_count > 2) {
2955 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2956 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2957 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2958 }
2e523e98
VS		 2959
2960 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
2961 DPIO_LANESTAGGER_STRAP(stagger) |
2962 DPIO_LANESTAGGER_STRAP_OVRD |
2963 DPIO_TX1_STAGGER_MASK(0x1f) |
2964 DPIO_TX1_STAGGER_MULT(6) |
2965 DPIO_TX2_STAGGER_MULT(0));
2966
e0fce78f
VS		 2967 if (intel_crtc->config->lane_count > 2) {
2968 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
2969 DPIO_LANESTAGGER_STRAP(stagger) |
2970 DPIO_LANESTAGGER_STRAP_OVRD |
2971 DPIO_TX1_STAGGER_MASK(0x1f) |
2972 DPIO_TX1_STAGGER_MULT(7) |
2973 DPIO_TX2_STAGGER_MULT(5));
2974 }
e4a1d846 2975
a8f327fb
VS		 2976 /* Deassert data lane reset */
2977 chv_data_lane_soft_reset(encoder, false);
2978
a580516d 2979 mutex_unlock(&dev_priv->sb_lock);
e4a1d846 2980
e4a1d846 2981 intel_enable_dp(encoder);
b0b33846
VS		 2982
2983 /* Second common lane will stay alive on its own now */
2984 if (dport->release_cl2_override) {
2985 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
2986 dport->release_cl2_override = false;
2987 }
e4a1d846
CML		 2988}
2989
9197c88b
VS		 2990static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2991{
2992 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2993 struct drm_device *dev = encoder->base.dev;
2994 struct drm_i915_private *dev_priv = dev->dev_private;
2995 struct intel_crtc *intel_crtc =
2996 to_intel_crtc(encoder->base.crtc);
2997 enum dpio_channel ch = vlv_dport_to_channel(dport);
2998 enum pipe pipe = intel_crtc->pipe;
e0fce78f
VS		 2999 unsigned int lane_mask =
3000 intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
9197c88b
VS		 3001 u32 val;
3002
625695f8
VS		 3003 intel_dp_prepare(encoder);
3004
b0b33846
VS		 3005 /*
3006 * Must trick the second common lane into life.
3007 * Otherwise we can't even access the PLL.
3008 */
3009 if (ch == DPIO_CH0 && pipe == PIPE_B)
3010 dport->release_cl2_override =
3011 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
3012
e0fce78f
VS		 3013 chv_phy_powergate_lanes(encoder, true, lane_mask);
3014
a580516d 3015 mutex_lock(&dev_priv->sb_lock);
9197c88b 3016
a8f327fb
VS		 3017 /* Assert data lane reset */
3018 chv_data_lane_soft_reset(encoder, true);
3019
b9e5ac3c
VS		 3020 /* program left/right clock distribution */
3021 if (pipe != PIPE_B) {
3022 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3023 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3024 if (ch == DPIO_CH0)
3025 val |= CHV_BUFLEFTENA1_FORCE;
3026 if (ch == DPIO_CH1)
3027 val |= CHV_BUFRIGHTENA1_FORCE;
3028 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3029 } else {
3030 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3031 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3032 if (ch == DPIO_CH0)
3033 val |= CHV_BUFLEFTENA2_FORCE;
3034 if (ch == DPIO_CH1)
3035 val |= CHV_BUFRIGHTENA2_FORCE;
3036 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3037 }
3038
9197c88b
VS		 3039 /* program clock channel usage */
3040 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
3041 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3042 if (pipe != PIPE_B)
3043 val &= ~CHV_PCS_USEDCLKCHANNEL;
3044 else
3045 val |= CHV_PCS_USEDCLKCHANNEL;
3046 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
3047
e0fce78f
VS		 3048 if (intel_crtc->config->lane_count > 2) {
3049 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
3050 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3051 if (pipe != PIPE_B)
3052 val &= ~CHV_PCS_USEDCLKCHANNEL;
3053 else
3054 val |= CHV_PCS_USEDCLKCHANNEL;
3055 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
3056 }
9197c88b
VS		 3057
3058 /*
3059 * This a a bit weird since generally CL
3060 * matches the pipe, but here we need to
3061 * pick the CL based on the port.
3062 */
3063 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
3064 if (pipe != PIPE_B)
3065 val &= ~CHV_CMN_USEDCLKCHANNEL;
3066 else
3067 val |= CHV_CMN_USEDCLKCHANNEL;
3068 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
3069
a580516d 3070 mutex_unlock(&dev_priv->sb_lock);
9197c88b
VS		 3071}
3072
d6db995f
VS		 3073static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
3074{
3075 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3076 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
3077 u32 val;
3078
3079 mutex_lock(&dev_priv->sb_lock);
3080
3081 /* disable left/right clock distribution */
3082 if (pipe != PIPE_B) {
3083 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3084 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3085 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3086 } else {
3087 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3088 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3089 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3090 }
3091
3092 mutex_unlock(&dev_priv->sb_lock);
e0fce78f 3093
b0b33846
VS		 3094 /*
3095 * Leave the power down bit cleared for at least one
3096 * lane so that chv_powergate_phy_ch() will power
3097 * on something when the channel is otherwise unused.
3098 * When the port is off and the override is removed
3099 * the lanes power down anyway, so otherwise it doesn't
3100 * really matter what the state of power down bits is
3101 * after this.
3102 */
e0fce78f 3103 chv_phy_powergate_lanes(encoder, false, 0x0);
d6db995f
VS		 3104}
3105
a4fc5ed6 3106/*
df0c237d
JB		 3107 * Native read with retry for link status and receiver capability reads for
3108 * cases where the sink may still be asleep.
9d1a1031
JN		 3109 *
3110 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
3111 * supposed to retry 3 times per the spec.
a4fc5ed6 3112 */
9d1a1031
JN		 3113static ssize_t
3114intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
3115 void *buffer, size_t size)
a4fc5ed6 3116{
9d1a1031
JN		 3117 ssize_t ret;
3118 int i;
61da5fab 3119
f6a19066
VS		 3120 /*
3121 * Sometime we just get the same incorrect byte repeated
3122 * over the entire buffer. Doing just one throw away read
3123 * initially seems to "solve" it.
3124 */
3125 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
3126
61da5fab 3127 for (i = 0; i < 3; i++) {
9d1a1031
JN		 3128 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
3129 if (ret == size)
3130 return ret;
61da5fab
JB		 3131 msleep(1);
3132 }
a4fc5ed6 3133
9d1a1031 3134 return ret;
a4fc5ed6
KP		 3135}
3136
3137/*
3138 * Fetch AUX CH registers 0x202 - 0x207 which contain
3139 * link status information
3140 */
94223d04 3141bool
93f62dad 3142intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 3143{
9d1a1031
JN		 3144 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3145 DP_LANE0_1_STATUS,
3146 link_status,
3147 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 3148}
3149
1100244e 3150/* These are source-specific values. */
94223d04 3151uint8_t
1a2eb460 3152intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 3153{
30add22d 3154 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 3155 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 3156 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3157
9314726b
VK		 3158 if (IS_BROXTON(dev))
3159 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3160 else if (INTEL_INFO(dev)->gen >= 9) {
06411f08 3161 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
7ad14a29 3162 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 3163 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
666a4537 3164 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
bd60018a 3165 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 3166 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 3167 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 3168 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 3169 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 3170 else
bd60018a 3171 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 3172}
3173
94223d04 3174uint8_t
1a2eb460
KP		 3175intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3176{
30add22d 3177 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 3178 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3179
5a9d1f1a
DL		 3180 if (INTEL_INFO(dev)->gen >= 9) {
3181 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3182 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3183 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3184 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3185 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3187 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 3188 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3189 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 3190 default:
3191 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3192 }
3193 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 3194 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3196 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3198 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3200 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 3202 default:
bd60018a 3203 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 3204 }
666a4537 3205 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e2fa6fba 3206 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3208 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3209 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3210 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3211 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3212 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 3214 default:
bd60018a 3215 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3216 }
bc7d38a4 3217 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 3218 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3220 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3221 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3223 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3224 default:
bd60018a 3225 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3226 }
3227 } else {
3228 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3230 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3231 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3232 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3233 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3234 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3236 default:
bd60018a 3237 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3238 }
a4fc5ed6
KP		 3239 }
3240}
3241
5829975c 3242static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba
P		 3243{
3244 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3245 struct drm_i915_private *dev_priv = dev->dev_private;
3246 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 3247 struct intel_crtc *intel_crtc =
3248 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 3249 unsigned long demph_reg_value, preemph_reg_value,
3250 uniqtranscale_reg_value;
3251 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 3252 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 3253 int pipe = intel_crtc->pipe;
e2fa6fba
P		 3254
3255 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3256 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3257 preemph_reg_value = 0x0004000;
3258 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3259 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3260 demph_reg_value = 0x2B405555;
3261 uniqtranscale_reg_value = 0x552AB83A;
3262 break;
bd60018a 3263 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3264 demph_reg_value = 0x2B404040;
3265 uniqtranscale_reg_value = 0x5548B83A;
3266 break;
bd60018a 3267 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3268 demph_reg_value = 0x2B245555;
3269 uniqtranscale_reg_value = 0x5560B83A;
3270 break;
bd60018a 3271 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3272 demph_reg_value = 0x2B405555;
3273 uniqtranscale_reg_value = 0x5598DA3A;
3274 break;
3275 default:
3276 return 0;
3277 }
3278 break;
bd60018a 3279 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3280 preemph_reg_value = 0x0002000;
3281 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3282 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3283 demph_reg_value = 0x2B404040;
3284 uniqtranscale_reg_value = 0x5552B83A;
3285 break;
bd60018a 3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3287 demph_reg_value = 0x2B404848;
3288 uniqtranscale_reg_value = 0x5580B83A;
3289 break;
bd60018a 3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3291 demph_reg_value = 0x2B404040;
3292 uniqtranscale_reg_value = 0x55ADDA3A;
3293 break;
3294 default:
3295 return 0;
3296 }
3297 break;
bd60018a 3298 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3299 preemph_reg_value = 0x0000000;
3300 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3301 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3302 demph_reg_value = 0x2B305555;
3303 uniqtranscale_reg_value = 0x5570B83A;
3304 break;
bd60018a 3305 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3306 demph_reg_value = 0x2B2B4040;
3307 uniqtranscale_reg_value = 0x55ADDA3A;
3308 break;
3309 default:
3310 return 0;
3311 }
3312 break;
bd60018a 3313 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3314 preemph_reg_value = 0x0006000;
3315 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3316 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3317 demph_reg_value = 0x1B405555;
3318 uniqtranscale_reg_value = 0x55ADDA3A;
3319 break;
3320 default:
3321 return 0;
3322 }
3323 break;
3324 default:
3325 return 0;
3326 }
3327
a580516d 3328 mutex_lock(&dev_priv->sb_lock);
ab3c759a
CML		 3329 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3330 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3331 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3332 uniqtranscale_reg_value);
ab3c759a
CML		 3333 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3334 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3335 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3336 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
a580516d 3337 mutex_unlock(&dev_priv->sb_lock);
e2fa6fba
P		 3338
3339 return 0;
3340}
3341
67fa24b4
VS		 3342static bool chv_need_uniq_trans_scale(uint8_t train_set)
3343{
3344 return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
3345 (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3346}
3347
5829975c 3348static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846
CML		 3349{
3350 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3351 struct drm_i915_private *dev_priv = dev->dev_private;
3352 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3353 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3354 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3355 uint8_t train_set = intel_dp->train_set[0];
3356 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3357 enum pipe pipe = intel_crtc->pipe;
3358 int i;
e4a1d846
CML		 3359
3360 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3361 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3362 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3363 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3364 deemph_reg_value = 128;
3365 margin_reg_value = 52;
3366 break;
bd60018a 3367 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3368 deemph_reg_value = 128;
3369 margin_reg_value = 77;
3370 break;
bd60018a 3371 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3372 deemph_reg_value = 128;
3373 margin_reg_value = 102;
3374 break;
bd60018a 3375 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3376 deemph_reg_value = 128;
3377 margin_reg_value = 154;
3378 /* FIXME extra to set for 1200 */
3379 break;
3380 default:
3381 return 0;
3382 }
3383 break;
bd60018a 3384 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3385 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3386 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3387 deemph_reg_value = 85;
3388 margin_reg_value = 78;
3389 break;
bd60018a 3390 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3391 deemph_reg_value = 85;
3392 margin_reg_value = 116;
3393 break;
bd60018a 3394 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3395 deemph_reg_value = 85;
3396 margin_reg_value = 154;
3397 break;
3398 default:
3399 return 0;
3400 }
3401 break;
bd60018a 3402 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3403 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3404 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3405 deemph_reg_value = 64;
3406 margin_reg_value = 104;
3407 break;
bd60018a 3408 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3409 deemph_reg_value = 64;
3410 margin_reg_value = 154;
3411 break;
3412 default:
3413 return 0;
3414 }
3415 break;
bd60018a 3416 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3417 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3418 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3419 deemph_reg_value = 43;
3420 margin_reg_value = 154;
3421 break;
3422 default:
3423 return 0;
3424 }
3425 break;
3426 default:
3427 return 0;
3428 }
3429
a580516d 3430 mutex_lock(&dev_priv->sb_lock);
e4a1d846
CML		 3431
3432 /* Clear calc init */
1966e59e
VS		 3433 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3434 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3435 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3436 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3437 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3438
e0fce78f
VS		 3439 if (intel_crtc->config->lane_count > 2) {
3440 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3441 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3442 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3443 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3444 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3445 }
e4a1d846 3446
a02ef3c7
VS		 3447 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3448 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3449 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3450 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3451
e0fce78f
VS		 3452 if (intel_crtc->config->lane_count > 2) {
3453 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3454 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3455 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3456 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3457 }
a02ef3c7 3458
e4a1d846 3459 /* Program swing deemph */
e0fce78f 3460 for (i = 0; i < intel_crtc->config->lane_count; i++) {
f72df8db
VS		 3461 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3462 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3463 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3464 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3465 }
e4a1d846
CML		 3466
3467 /* Program swing margin */
e0fce78f 3468 for (i = 0; i < intel_crtc->config->lane_count; i++) {
f72df8db 3469 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
67fa24b4 3470
1fb44505
VS		 3471 val &= ~DPIO_SWING_MARGIN000_MASK;
3472 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
67fa24b4
VS		 3473
3474 /*
3475 * Supposedly this value shouldn't matter when unique transition
3476 * scale is disabled, but in fact it does matter. Let's just
3477 * always program the same value and hope it's OK.
3478 */
3479 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3480 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
3481
f72df8db
VS		 3482 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3483 }
e4a1d846 3484
67fa24b4
VS		 3485 /*
3486 * The document said it needs to set bit 27 for ch0 and bit 26
3487 * for ch1. Might be a typo in the doc.
3488 * For now, for this unique transition scale selection, set bit
3489 * 27 for ch0 and ch1.
3490 */
e0fce78f 3491 for (i = 0; i < intel_crtc->config->lane_count; i++) {
f72df8db 3492 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
67fa24b4 3493 if (chv_need_uniq_trans_scale(train_set))
f72df8db 3494 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
67fa24b4
VS		 3495 else
3496 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3497 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
e4a1d846
CML		 3498 }
3499
3500 /* Start swing calculation */
1966e59e
VS		 3501 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3502 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3503 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3504
e0fce78f
VS		 3505 if (intel_crtc->config->lane_count > 2) {
3506 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3507 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3508 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3509 }
e4a1d846 3510
a580516d 3511 mutex_unlock(&dev_priv->sb_lock);
e4a1d846
CML		 3512
3513 return 0;
3514}
3515
a4fc5ed6 3516static uint32_t
5829975c 3517gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3518{
3cf2efb1 3519 uint32_t signal_levels = 0;
a4fc5ed6 3520
3cf2efb1 3521 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3522 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3523 default:
3524 signal_levels |= DP_VOLTAGE_0_4;
3525 break;
bd60018a 3526 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3527 signal_levels |= DP_VOLTAGE_0_6;
3528 break;
bd60018a 3529 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3530 signal_levels |= DP_VOLTAGE_0_8;
3531 break;
bd60018a 3532 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3533 signal_levels |= DP_VOLTAGE_1_2;
3534 break;
3535 }
3cf2efb1 3536 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3537 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3538 default:
3539 signal_levels |= DP_PRE_EMPHASIS_0;
3540 break;
bd60018a 3541 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3542 signal_levels |= DP_PRE_EMPHASIS_3_5;
3543 break;
bd60018a 3544 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3545 signal_levels |= DP_PRE_EMPHASIS_6;
3546 break;
bd60018a 3547 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3548 signal_levels |= DP_PRE_EMPHASIS_9_5;
3549 break;
3550 }
3551 return signal_levels;
3552}
3553
e3421a18
ZW		 3554/* Gen6's DP voltage swing and pre-emphasis control */
3555static uint32_t
5829975c 3556gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3557{
3c5a62b5
YL		 3558 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3559 DP_TRAIN_PRE_EMPHASIS_MASK);
3560 switch (signal_levels) {
bd60018a
SJ		 3561 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3562 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3563 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3564 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3565 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3566 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3567 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3568 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3569 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3570 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3571 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3572 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3573 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3574 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3575 default:
3c5a62b5
YL		 3576 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3577 "0x%x\n", signal_levels);
3578 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3579 }
3580}
3581
1a2eb460
KP		 3582/* Gen7's DP voltage swing and pre-emphasis control */
3583static uint32_t
5829975c 3584gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3585{
3586 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3587 DP_TRAIN_PRE_EMPHASIS_MASK);
3588 switch (signal_levels) {
bd60018a 3589 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3590 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3591 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3592 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3593 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3594 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3595
bd60018a 3596 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3597 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3598 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3599 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3600
bd60018a 3601 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3602 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3603 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3604 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3605
3606 default:
3607 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3608 "0x%x\n", signal_levels);
3609 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3610 }
3611}
3612
94223d04 3613void
f4eb692e 3614intel_dp_set_signal_levels(struct intel_dp *intel_dp)
f0a3424e
PZ		 3615{
3616 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3617 enum port port = intel_dig_port->port;
f0a3424e 3618 struct drm_device *dev = intel_dig_port->base.base.dev;
b905a915 3619 struct drm_i915_private *dev_priv = to_i915(dev);
f8896f5d 3620 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3621 uint8_t train_set = intel_dp->train_set[0];
3622
f8896f5d
DW		 3623 if (HAS_DDI(dev)) {
3624 signal_levels = ddi_signal_levels(intel_dp);
3625
3626 if (IS_BROXTON(dev))
3627 signal_levels = 0;
3628 else
3629 mask = DDI_BUF_EMP_MASK;
e4a1d846 3630 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3631 signal_levels = chv_signal_levels(intel_dp);
e2fa6fba 3632 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3633 signal_levels = vlv_signal_levels(intel_dp);
bc7d38a4 3634 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3635 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3636 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3637 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3638 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3639 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3640 } else {
5829975c 3641 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3642 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3643 }
3644
96fb9f9b
VK		 3645 if (mask)
3646 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3647
3648 DRM_DEBUG_KMS("Using vswing level %d\n",
3649 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3650 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3651 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3652 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e 3653
f4eb692e 3654 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
b905a915
ACO		 3655
3656 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3657 POSTING_READ(intel_dp->output_reg);
f0a3424e
PZ		 3658}
3659
94223d04 3660void
e9c176d5
ACO		 3661intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3662 uint8_t dp_train_pat)
a4fc5ed6 3663{
174edf1f 3664 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3665 struct drm_i915_private *dev_priv =
3666 to_i915(intel_dig_port->base.base.dev);
a4fc5ed6 3667
f4eb692e 3668 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
47ea7542 3669
f4eb692e 3670 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
ea5b213a 3671 POSTING_READ(intel_dp->output_reg);
e9c176d5
ACO		 3672}
3673
94223d04 3674void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3ab9c637
ID		 3675{
3676 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3677 struct drm_device *dev = intel_dig_port->base.base.dev;
3678 struct drm_i915_private *dev_priv = dev->dev_private;
3679 enum port port = intel_dig_port->port;
3680 uint32_t val;
3681
3682 if (!HAS_DDI(dev))
3683 return;
3684
3685 val = I915_READ(DP_TP_CTL(port));
3686 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3687 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3688 I915_WRITE(DP_TP_CTL(port), val);
3689
3690 /*
3691 * On PORT_A we can have only eDP in SST mode. There the only reason
3692 * we need to set idle transmission mode is to work around a HW issue
3693 * where we enable the pipe while not in idle link-training mode.
3694 * In this case there is requirement to wait for a minimum number of
3695 * idle patterns to be sent.
3696 */
3697 if (port == PORT_A)
3698 return;
3699
3700 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3701 1))
3702 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3703}
3704
a4fc5ed6 3705static void
ea5b213a 3706intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3707{
da63a9f2 3708 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3709 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3710 enum port port = intel_dig_port->port;
da63a9f2 3711 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3712 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3713 uint32_t DP = intel_dp->DP;
a4fc5ed6 3714
bc76e320 3715 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3716 return;
3717
0c33d8d7 3718 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3719 return;
3720
28c97730 3721 DRM_DEBUG_KMS("\n");
32f9d658 3722
39e5fa88
VS		 3723 if ((IS_GEN7(dev) && port == PORT_A) ||
3724 (HAS_PCH_CPT(dev) && port != PORT_A)) {
e3421a18 3725 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3726 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3727 } else {
aad3d14d
VS		 3728 if (IS_CHERRYVIEW(dev))
3729 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3730 else
3731 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3732 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3733 }
1612c8bd 3734 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3735 POSTING_READ(intel_dp->output_reg);
5eb08b69 3736
1612c8bd
VS		 3737 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3738 I915_WRITE(intel_dp->output_reg, DP);
3739 POSTING_READ(intel_dp->output_reg);
3740
3741 /*
3742 * HW workaround for IBX, we need to move the port
3743 * to transcoder A after disabling it to allow the
3744 * matching HDMI port to be enabled on transcoder A.
3745 */
3746 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
0c241d5b
VS		 3747 /*
3748 * We get CPU/PCH FIFO underruns on the other pipe when
3749 * doing the workaround. Sweep them under the rug.
3750 */
3751 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3752 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3753
1612c8bd
VS		 3754 /* always enable with pattern 1 (as per spec) */
3755 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3756 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3757 I915_WRITE(intel_dp->output_reg, DP);
3758 POSTING_READ(intel_dp->output_reg);
3759
3760 DP &= ~DP_PORT_EN;
5bddd17f 3761 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3762 POSTING_READ(intel_dp->output_reg);
0c241d5b
VS		 3763
3764 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3765 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3766 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5bddd17f
EA		 3767 }
3768
f01eca2e 3769 msleep(intel_dp->panel_power_down_delay);
6fec7662
VS		 3770
3771 intel_dp->DP = DP;
a4fc5ed6
KP		 3772}
3773
26d61aad
KP		 3774static bool
3775intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3776{
a031d709
RV		 3777 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3778 struct drm_device *dev = dig_port->base.base.dev;
3779 struct drm_i915_private *dev_priv = dev->dev_private;
fc0f8e25 3780 uint8_t rev;
a031d709 3781
9d1a1031
JN		 3782 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3783 sizeof(intel_dp->dpcd)) < 0)
edb39244 3784 return false; /* aux transfer failed */
92fd8fd1 3785
a8e98153 3786 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3787
edb39244
AJ		 3788 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3789 return false; /* DPCD not present */
3790
2293bb5c
SK		 3791 /* Check if the panel supports PSR */
3792 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3793 if (is_edp(intel_dp)) {
9d1a1031
JN		 3794 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3795 intel_dp->psr_dpcd,
3796 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3797 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3798 dev_priv->psr.sink_support = true;
50003939 3799 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3800 }
474d1ec4
SJ		 3801
3802 if (INTEL_INFO(dev)->gen >= 9 &&
3803 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3804 uint8_t frame_sync_cap;
3805
3806 dev_priv->psr.sink_support = true;
3807 intel_dp_dpcd_read_wake(&intel_dp->aux,
3808 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3809 &frame_sync_cap, 1);
3810 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3811 /* PSR2 needs frame sync as well */
3812 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3813 DRM_DEBUG_KMS("PSR2 %s on sink",
3814 dev_priv->psr.psr2_support ? "supported" : "not supported");
3815 }
50003939
JN		 3816 }
3817
bc5133d5 3818 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
e588fa18 3819 yesno(intel_dp_source_supports_hbr2(intel_dp)),
742f491d 3820 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
06ea66b6 3821
fc0f8e25
SJ		 3822 /* Intermediate frequency support */
3823 if (is_edp(intel_dp) &&
3824 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3825 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3826 (rev >= 0x03)) { /* eDp v1.4 or higher */
94ca719e 3827 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3828 int i;
3829
fc0f8e25
SJ		 3830 intel_dp_dpcd_read_wake(&intel_dp->aux,
3831 DP_SUPPORTED_LINK_RATES,
94ca719e
VS		 3832 sink_rates,
3833 sizeof(sink_rates));
ea2d8a42 3834
94ca719e
VS		 3835 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3836 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3837
3838 if (val == 0)
3839 break;
3840
af77b974
SJ		 3841 /* Value read is in kHz while drm clock is saved in deca-kHz */
3842 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3843 }
94ca719e 3844 intel_dp->num_sink_rates = i;
fc0f8e25 3845 }
0336400e
VS		 3846
3847 intel_dp_print_rates(intel_dp);
3848
edb39244
AJ		 3849 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3850 DP_DWN_STRM_PORT_PRESENT))
3851 return true; /* native DP sink */
3852
3853 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3854 return true; /* no per-port downstream info */
3855
9d1a1031
JN		 3856 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3857 intel_dp->downstream_ports,
3858 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3859 return false; /* downstream port status fetch failed */
3860
3861 return true;
92fd8fd1
KP		 3862}
3863
0d198328
AJ		 3864static void
3865intel_dp_probe_oui(struct intel_dp *intel_dp)
3866{
3867 u8 buf[3];
3868
3869 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3870 return;
3871
9d1a1031 3872 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3873 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3874 buf[0], buf[1], buf[2]);
3875
9d1a1031 3876 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3877 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3878 buf[0], buf[1], buf[2]);
3879}
3880
0e32b39c
DA		 3881static bool
3882intel_dp_probe_mst(struct intel_dp *intel_dp)
3883{
3884 u8 buf[1];
3885
7cc96139
NS		 3886 if (!i915.enable_dp_mst)
3887 return false;
3888
0e32b39c
DA		 3889 if (!intel_dp->can_mst)
3890 return false;
3891
3892 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3893 return false;
3894
0e32b39c
DA		 3895 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3896 if (buf[0] & DP_MST_CAP) {
3897 DRM_DEBUG_KMS("Sink is MST capable\n");
3898 intel_dp->is_mst = true;
3899 } else {
3900 DRM_DEBUG_KMS("Sink is not MST capable\n");
3901 intel_dp->is_mst = false;
3902 }
3903 }
0e32b39c
DA		 3904
3905 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3906 return intel_dp->is_mst;
3907}
3908
e5a1cab5 3909static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
d2e216d0 3910{
082dcc7c 3911 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3912 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c 3913 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
ad9dc91b 3914 u8 buf;
e5a1cab5 3915 int ret = 0;
c6297843
RV		 3916 int count = 0;
3917 int attempts = 10;
d2e216d0 3918
082dcc7c
RV		 3919 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3920 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3921 ret = -EIO;
3922 goto out;
4373f0f2
PZ		 3923 }
3924
082dcc7c 3925 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
e5a1cab5 3926 buf & ~DP_TEST_SINK_START) < 0) {
082dcc7c 3927 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3928 ret = -EIO;
3929 goto out;
3930 }
d2e216d0 3931
c6297843
RV		 3932 do {
3933 intel_wait_for_vblank(dev, intel_crtc->pipe);
3934
3935 if (drm_dp_dpcd_readb(&intel_dp->aux,
3936 DP_TEST_SINK_MISC, &buf) < 0) {
3937 ret = -EIO;
3938 goto out;
3939 }
3940 count = buf & DP_TEST_COUNT_MASK;
3941 } while (--attempts && count);
3942
3943 if (attempts == 0) {
dc5a9037 3944 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
c6297843
RV		 3945 ret = -ETIMEDOUT;
3946 }
3947
e5a1cab5 3948 out:
082dcc7c 3949 hsw_enable_ips(intel_crtc);
e5a1cab5 3950 return ret;
082dcc7c
RV		 3951}
3952
3953static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3954{
3955 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3956 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c
RV		 3957 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3958 u8 buf;
e5a1cab5
RV		 3959 int ret;
3960
082dcc7c
RV		 3961 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3962 return -EIO;
3963
3964 if (!(buf & DP_TEST_CRC_SUPPORTED))
3965 return -ENOTTY;
3966
3967 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3968 return -EIO;
3969
6d8175da
RV		 3970 if (buf & DP_TEST_SINK_START) {
3971 ret = intel_dp_sink_crc_stop(intel_dp);
3972 if (ret)
3973 return ret;
3974 }
3975
082dcc7c 3976 hsw_disable_ips(intel_crtc);
1dda5f93 3977
9d1a1031 3978 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
082dcc7c
RV		 3979 buf | DP_TEST_SINK_START) < 0) {
3980 hsw_enable_ips(intel_crtc);
3981 return -EIO;
4373f0f2
PZ		 3982 }
3983
d72f9d91 3984 intel_wait_for_vblank(dev, intel_crtc->pipe);
082dcc7c
RV		 3985 return 0;
3986}
3987
3988int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3989{
3990 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3991 struct drm_device *dev = dig_port->base.base.dev;
3992 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3993 u8 buf;
621d4c76 3994 int count, ret;
082dcc7c 3995 int attempts = 6;
082dcc7c
RV		 3996
3997 ret = intel_dp_sink_crc_start(intel_dp);
3998 if (ret)
3999 return ret;
4000
ad9dc91b 4001 do {
621d4c76
RV		 4002 intel_wait_for_vblank(dev, intel_crtc->pipe);
4003
1dda5f93 4004 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 4005 DP_TEST_SINK_MISC, &buf) < 0) {
4006 ret = -EIO;
afe0d67e 4007 goto stop;
4373f0f2 4008 }
621d4c76 4009 count = buf & DP_TEST_COUNT_MASK;
aabc95dc 4010
7e38eeff 4011 } while (--attempts && count == 0);
ad9dc91b
RV		 4012
4013 if (attempts == 0) {
7e38eeff
RV		 4014 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4015 ret = -ETIMEDOUT;
4016 goto stop;
4017 }
4018
4019 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4020 ret = -EIO;
4021 goto stop;
ad9dc91b 4022 }
d2e216d0 4023
afe0d67e 4024stop:
082dcc7c 4025 intel_dp_sink_crc_stop(intel_dp);
4373f0f2 4026 return ret;
d2e216d0
RV		 4027}
4028
a60f0e38
JB		 4029static bool
4030intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4031{
9d1a1031
JN		 4032 return intel_dp_dpcd_read_wake(&intel_dp->aux,
4033 DP_DEVICE_SERVICE_IRQ_VECTOR,
4034 sink_irq_vector, 1) == 1;
a60f0e38
JB		 4035}
4036
0e32b39c
DA		 4037static bool
4038intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4039{
4040 int ret;
4041
4042 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4043 DP_SINK_COUNT_ESI,
4044 sink_irq_vector, 14);
4045 if (ret != 14)
4046 return false;
4047
4048 return true;
4049}
4050
c5d5ab7a
TP		 4051static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4052{
4053 uint8_t test_result = DP_TEST_ACK;
4054 return test_result;
4055}
4056
4057static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4058{
4059 uint8_t test_result = DP_TEST_NAK;
4060 return test_result;
4061}
4062
4063static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 4064{
c5d5ab7a 4065 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 4066 struct intel_connector *intel_connector = intel_dp->attached_connector;
4067 struct drm_connector *connector = &intel_connector->base;
4068
4069 if (intel_connector->detect_edid == NULL ||
ac6f2e29 4070 connector->edid_corrupt ||
559be30c
TP		 4071 intel_dp->aux.i2c_defer_count > 6) {
4072 /* Check EDID read for NACKs, DEFERs and corruption
4073 * (DP CTS 1.2 Core r1.1)
4074 * 4.2.2.4 : Failed EDID read, I2C_NAK
4075 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4076 * 4.2.2.6 : EDID corruption detected
4077 * Use failsafe mode for all cases
4078 */
4079 if (intel_dp->aux.i2c_nack_count > 0 ||
4080 intel_dp->aux.i2c_defer_count > 0)
4081 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4082 intel_dp->aux.i2c_nack_count,
4083 intel_dp->aux.i2c_defer_count);
4084 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4085 } else {
f79b468e
TS		 4086 struct edid *block = intel_connector->detect_edid;
4087
4088 /* We have to write the checksum
4089 * of the last block read
4090 */
4091 block += intel_connector->detect_edid->extensions;
4092
559be30c
TP		 4093 if (!drm_dp_dpcd_write(&intel_dp->aux,
4094 DP_TEST_EDID_CHECKSUM,
f79b468e 4095 &block->checksum,
5a1cc655 4096 1))
559be30c
TP		 4097 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4098
4099 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4100 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4101 }
4102
4103 /* Set test active flag here so userspace doesn't interrupt things */
4104 intel_dp->compliance_test_active = 1;
4105
c5d5ab7a
TP		 4106 return test_result;
4107}
4108
4109static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 4110{
c5d5ab7a
TP		 4111 uint8_t test_result = DP_TEST_NAK;
4112 return test_result;
4113}
4114
4115static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4116{
4117 uint8_t response = DP_TEST_NAK;
4118 uint8_t rxdata = 0;
4119 int status = 0;
4120
c5d5ab7a
TP		 4121 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4122 if (status <= 0) {
4123 DRM_DEBUG_KMS("Could not read test request from sink\n");
4124 goto update_status;
4125 }
4126
4127 switch (rxdata) {
4128 case DP_TEST_LINK_TRAINING:
4129 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4130 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4131 response = intel_dp_autotest_link_training(intel_dp);
4132 break;
4133 case DP_TEST_LINK_VIDEO_PATTERN:
4134 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4135 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4136 response = intel_dp_autotest_video_pattern(intel_dp);
4137 break;
4138 case DP_TEST_LINK_EDID_READ:
4139 DRM_DEBUG_KMS("EDID test requested\n");
4140 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4141 response = intel_dp_autotest_edid(intel_dp);
4142 break;
4143 case DP_TEST_LINK_PHY_TEST_PATTERN:
4144 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4145 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4146 response = intel_dp_autotest_phy_pattern(intel_dp);
4147 break;
4148 default:
4149 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4150 break;
4151 }
4152
4153update_status:
4154 status = drm_dp_dpcd_write(&intel_dp->aux,
4155 DP_TEST_RESPONSE,
4156 &response, 1);
4157 if (status <= 0)
4158 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 4159}
4160
0e32b39c
DA		 4161static int
4162intel_dp_check_mst_status(struct intel_dp *intel_dp)
4163{
4164 bool bret;
4165
4166 if (intel_dp->is_mst) {
4167 u8 esi[16] = { 0 };
4168 int ret = 0;
4169 int retry;
4170 bool handled;
4171 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4172go_again:
4173 if (bret == true) {
4174
4175 /* check link status - esi[10] = 0x200c */
90a6b7b0 4176 if (intel_dp->active_mst_links &&
901c2daf 4177 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
0e32b39c
DA		 4178 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4179 intel_dp_start_link_train(intel_dp);
0e32b39c
DA		 4180 intel_dp_stop_link_train(intel_dp);
4181 }
4182
6f34cc39 4183 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 4184 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4185
4186 if (handled) {
4187 for (retry = 0; retry < 3; retry++) {
4188 int wret;
4189 wret = drm_dp_dpcd_write(&intel_dp->aux,
4190 DP_SINK_COUNT_ESI+1,
4191 &esi[1], 3);
4192 if (wret == 3) {
4193 break;
4194 }
4195 }
4196
4197 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4198 if (bret == true) {
6f34cc39 4199 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 4200 goto go_again;
4201 }
4202 } else
4203 ret = 0;
4204
4205 return ret;
4206 } else {
4207 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4208 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4209 intel_dp->is_mst = false;
4210 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4211 /* send a hotplug event */
4212 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4213 }
4214 }
4215 return -EINVAL;
4216}
4217
a4fc5ed6
KP		 4218/*
4219 * According to DP spec
4220 * 5.1.2:
4221 * 1. Read DPCD
4222 * 2. Configure link according to Receiver Capabilities
4223 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4224 * 4. Check link status on receipt of hot-plug interrupt
4225 */
a5146200 4226static void
ea5b213a 4227intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4228{
5b215bcf 4229 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4230 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4231 u8 sink_irq_vector;
93f62dad 4232 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4233
5b215bcf
DA		 4234 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4235
4df6960e
SS		 4236 /*
4237 * Clearing compliance test variables to allow capturing
4238 * of values for next automated test request.
4239 */
4240 intel_dp->compliance_test_active = 0;
4241 intel_dp->compliance_test_type = 0;
4242 intel_dp->compliance_test_data = 0;
4243
e02f9a06 4244 if (!intel_encoder->base.crtc)
a4fc5ed6
KP		 4245 return;
4246
1a125d8a
ID		 4247 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4248 return;
4249
92fd8fd1 4250 /* Try to read receiver status if the link appears to be up */
93f62dad 4251 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4252 return;
4253 }
4254
92fd8fd1 4255 /* Now read the DPCD to see if it's actually running */
26d61aad 4256 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4257 return;
4258 }
4259
a60f0e38
JB		 4260 /* Try to read the source of the interrupt */
4261 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4262 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4263 /* Clear interrupt source */
9d1a1031
JN		 4264 drm_dp_dpcd_writeb(&intel_dp->aux,
4265 DP_DEVICE_SERVICE_IRQ_VECTOR,
4266 sink_irq_vector);
a60f0e38
JB		 4267
4268 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 4269 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 4270 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4271 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4272 }
4273
14631e9d
SS		 4274 /* if link training is requested we should perform it always */
4275 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4276 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
92fd8fd1 4277 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4278 intel_encoder->base.name);
33a34e4e 4279 intel_dp_start_link_train(intel_dp);
3ab9c637 4280 intel_dp_stop_link_train(intel_dp);
33a34e4e 4281 }
a4fc5ed6 4282}
a4fc5ed6 4283
caf9ab24 4284/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4285static enum drm_connector_status
26d61aad 4286intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4287{
caf9ab24 4288 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4289 uint8_t type;
4290
4291 if (!intel_dp_get_dpcd(intel_dp))
4292 return connector_status_disconnected;
4293
4294 /* if there's no downstream port, we're done */
4295 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4296 return connector_status_connected;
caf9ab24
AJ		 4297
4298 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4299 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4300 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4301 uint8_t reg;
9d1a1031
JN		 4302
4303 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4304 &reg, 1) < 0)
caf9ab24 4305 return connector_status_unknown;
9d1a1031 4306
23235177
AJ		 4307 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4308 : connector_status_disconnected;
caf9ab24
AJ		 4309 }
4310
4311 /* If no HPD, poke DDC gently */
0b99836f 4312 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4313 return connector_status_connected;
caf9ab24
AJ		 4314
4315 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4316 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4317 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4318 if (type == DP_DS_PORT_TYPE_VGA ||
4319 type == DP_DS_PORT_TYPE_NON_EDID)
4320 return connector_status_unknown;
4321 } else {
4322 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4323 DP_DWN_STRM_PORT_TYPE_MASK;
4324 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4325 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4326 return connector_status_unknown;
4327 }
caf9ab24
AJ		 4328
4329 /* Anything else is out of spec, warn and ignore */
4330 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4331 return connector_status_disconnected;
71ba9000
AJ		 4332}
4333
d410b56d
CW		 4334static enum drm_connector_status
4335edp_detect(struct intel_dp *intel_dp)
4336{
4337 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4338 enum drm_connector_status status;
4339
4340 status = intel_panel_detect(dev);
4341 if (status == connector_status_unknown)
4342 status = connector_status_connected;
4343
4344 return status;
4345}
4346
b93433cc
JN		 4347static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4348 struct intel_digital_port *port)
5eb08b69 4349{
b93433cc 4350 u32 bit;
01cb9ea6 4351
0df53b77
JN		 4352 switch (port->port) {
4353 case PORT_A:
4354 return true;
4355 case PORT_B:
4356 bit = SDE_PORTB_HOTPLUG;
4357 break;
4358 case PORT_C:
4359 bit = SDE_PORTC_HOTPLUG;
4360 break;
4361 case PORT_D:
4362 bit = SDE_PORTD_HOTPLUG;
4363 break;
4364 default:
4365 MISSING_CASE(port->port);
4366 return false;
4367 }
4368
4369 return I915_READ(SDEISR) & bit;
4370}
4371
4372static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4373 struct intel_digital_port *port)
4374{
4375 u32 bit;
4376
4377 switch (port->port) {
4378 case PORT_A:
4379 return true;
4380 case PORT_B:
4381 bit = SDE_PORTB_HOTPLUG_CPT;
4382 break;
4383 case PORT_C:
4384 bit = SDE_PORTC_HOTPLUG_CPT;
4385 break;
4386 case PORT_D:
4387 bit = SDE_PORTD_HOTPLUG_CPT;
4388 break;
a78695d3
JN		 4389 case PORT_E:
4390 bit = SDE_PORTE_HOTPLUG_SPT;
4391 break;
0df53b77
JN		 4392 default:
4393 MISSING_CASE(port->port);
4394 return false;
b93433cc 4395 }
1b469639 4396
b93433cc 4397 return I915_READ(SDEISR) & bit;
5eb08b69
ZW		 4398}
4399
7e66bcf2 4400static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
1d245987 4401 struct intel_digital_port *port)
a4fc5ed6 4402{
9642c81c 4403 u32 bit;
5eb08b69 4404
9642c81c
JN		 4405 switch (port->port) {
4406 case PORT_B:
4407 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4408 break;
4409 case PORT_C:
4410 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4411 break;
4412 case PORT_D:
4413 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4414 break;
4415 default:
4416 MISSING_CASE(port->port);
4417 return false;
4418 }
4419
4420 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4421}
4422
0780cd36
VS		 4423static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4424 struct intel_digital_port *port)
9642c81c
JN		 4425{
4426 u32 bit;
4427
4428 switch (port->port) {
4429 case PORT_B:
0780cd36 4430 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4431 break;
4432 case PORT_C:
0780cd36 4433 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4434 break;
4435 case PORT_D:
0780cd36 4436 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4437 break;
4438 default:
4439 MISSING_CASE(port->port);
4440 return false;
a4fc5ed6
KP		 4441 }
4442
1d245987 4443 return I915_READ(PORT_HOTPLUG_STAT) & bit;
2a592bec
DA		 4444}
4445
e464bfde 4446static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
e2ec35a5 4447 struct intel_digital_port *intel_dig_port)
e464bfde 4448{
e2ec35a5
SJ		 4449 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4450 enum port port;
e464bfde
JN		 4451 u32 bit;
4452
e2ec35a5
SJ		 4453 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4454 switch (port) {
e464bfde
JN		 4455 case PORT_A:
4456 bit = BXT_DE_PORT_HP_DDIA;
4457 break;
4458 case PORT_B:
4459 bit = BXT_DE_PORT_HP_DDIB;
4460 break;
4461 case PORT_C:
4462 bit = BXT_DE_PORT_HP_DDIC;
4463 break;
4464 default:
e2ec35a5 4465 MISSING_CASE(port);
e464bfde
JN		 4466 return false;
4467 }
4468
4469 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4470}
4471
7e66bcf2
JN		 4472/*
4473 * intel_digital_port_connected - is the specified port connected?
4474 * @dev_priv: i915 private structure
4475 * @port: the port to test
4476 *
4477 * Return %true if @port is connected, %false otherwise.
4478 */
237ed86c 4479bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
7e66bcf2
JN		 4480 struct intel_digital_port *port)
4481{
0df53b77 4482 if (HAS_PCH_IBX(dev_priv))
7e66bcf2 4483 return ibx_digital_port_connected(dev_priv, port);
22824fac 4484 else if (HAS_PCH_SPLIT(dev_priv))
0df53b77 4485 return cpt_digital_port_connected(dev_priv, port);
e464bfde
JN		 4486 else if (IS_BROXTON(dev_priv))
4487 return bxt_digital_port_connected(dev_priv, port);
0780cd36
VS		 4488 else if (IS_GM45(dev_priv))
4489 return gm45_digital_port_connected(dev_priv, port);
7e66bcf2
JN		 4490 else
4491 return g4x_digital_port_connected(dev_priv, port);
4492}
4493
8c241fef 4494static struct edid *
beb60608 4495intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4496{
beb60608 4497 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4498
9cd300e0
JN		 4499 /* use cached edid if we have one */
4500 if (intel_connector->edid) {
9cd300e0
JN		 4501 /* invalid edid */
4502 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4503 return NULL;
4504
55e9edeb 4505 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4506 } else
4507 return drm_get_edid(&intel_connector->base,
4508 &intel_dp->aux.ddc);
4509}
8c241fef 4510
beb60608
CW		 4511static void
4512intel_dp_set_edid(struct intel_dp *intel_dp)
4513{
4514 struct intel_connector *intel_connector = intel_dp->attached_connector;
4515 struct edid *edid;
8c241fef 4516
f21a2198 4517 intel_dp_unset_edid(intel_dp);
beb60608
CW		 4518 edid = intel_dp_get_edid(intel_dp);
4519 intel_connector->detect_edid = edid;
4520
4521 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4522 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4523 else
4524 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4525}
4526
beb60608
CW		 4527static void
4528intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4529{
beb60608 4530 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4531
beb60608
CW		 4532 kfree(intel_connector->detect_edid);
4533 intel_connector->detect_edid = NULL;
9cd300e0 4534
beb60608
CW		 4535 intel_dp->has_audio = false;
4536}
d6f24d0f 4537
f21a2198
SS		 4538static void
4539intel_dp_long_pulse(struct intel_connector *intel_connector)
a9756bb5 4540{
f21a2198 4541 struct drm_connector *connector = &intel_connector->base;
a9756bb5 4542 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4543 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4544 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4545 struct drm_device *dev = connector->dev;
a9756bb5 4546 enum drm_connector_status status;
671dedd2 4547 enum intel_display_power_domain power_domain;
0e32b39c 4548 bool ret;
09b1eb13 4549 u8 sink_irq_vector;
a9756bb5 4550
25f78f58
VS		 4551 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4552 intel_display_power_get(to_i915(dev), power_domain);
a9756bb5 4553
d410b56d
CW		 4554 /* Can't disconnect eDP, but you can close the lid... */
4555 if (is_edp(intel_dp))
4556 status = edp_detect(intel_dp);
c555a81d
ACO		 4557 else if (intel_digital_port_connected(to_i915(dev),
4558 dp_to_dig_port(intel_dp)))
4559 status = intel_dp_detect_dpcd(intel_dp);
a9756bb5 4560 else
c555a81d
ACO		 4561 status = connector_status_disconnected;
4562
4df6960e
SS		 4563 if (status != connector_status_connected) {
4564 intel_dp->compliance_test_active = 0;
4565 intel_dp->compliance_test_type = 0;
4566 intel_dp->compliance_test_data = 0;
4567
c8c8fb33 4568 goto out;
4df6960e 4569 }
a9756bb5 4570
f21a2198
SS		 4571 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4572 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4573
0d198328
AJ		 4574 intel_dp_probe_oui(intel_dp);
4575
0e32b39c
DA		 4576 ret = intel_dp_probe_mst(intel_dp);
4577 if (ret) {
f21a2198
SS		 4578 /*
4579 * If we are in MST mode then this connector
4580 * won't appear connected or have anything
4581 * with EDID on it
4582 */
0e32b39c
DA		 4583 status = connector_status_disconnected;
4584 goto out;
4585 }
4586
4df6960e
SS		 4587 /*
4588 * Clearing NACK and defer counts to get their exact values
4589 * while reading EDID which are required by Compliance tests
4590 * 4.2.2.4 and 4.2.2.5
4591 */
4592 intel_dp->aux.i2c_nack_count = 0;
4593 intel_dp->aux.i2c_defer_count = 0;
4594
beb60608 4595 intel_dp_set_edid(intel_dp);
a9756bb5 4596
c8c8fb33
PZ		 4597 status = connector_status_connected;
4598
09b1eb13
TP		 4599 /* Try to read the source of the interrupt */
4600 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4601 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4602 /* Clear interrupt source */
4603 drm_dp_dpcd_writeb(&intel_dp->aux,
4604 DP_DEVICE_SERVICE_IRQ_VECTOR,
4605 sink_irq_vector);
4606
4607 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4608 intel_dp_handle_test_request(intel_dp);
4609 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4610 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4611 }
4612
c8c8fb33 4613out:
f21a2198
SS		 4614 if (status != connector_status_connected)
4615 intel_dp_unset_edid(intel_dp);
25f78f58 4616 intel_display_power_put(to_i915(dev), power_domain);
f21a2198
SS		 4617 return;
4618}
4619
4620static enum drm_connector_status
4621intel_dp_detect(struct drm_connector *connector, bool force)
4622{
4623 struct intel_dp *intel_dp = intel_attached_dp(connector);
4624 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4625 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4626 struct intel_connector *intel_connector = to_intel_connector(connector);
4627
4628 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4629 connector->base.id, connector->name);
4630
4631 if (intel_dp->is_mst) {
4632 /* MST devices are disconnected from a monitor POV */
4633 intel_dp_unset_edid(intel_dp);
4634 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4635 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4636 return connector_status_disconnected;
4637 }
4638
4639 intel_dp_long_pulse(intel_dp->attached_connector);
4640
4641 if (intel_connector->detect_edid)
4642 return connector_status_connected;
4643 else
4644 return connector_status_disconnected;
a4fc5ed6
KP		 4645}
4646
beb60608
CW		 4647static void
4648intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4649{
df0e9248 4650 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4651 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
25f78f58 4652 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
671dedd2 4653 enum intel_display_power_domain power_domain;
a4fc5ed6 4654
beb60608
CW		 4655 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4656 connector->base.id, connector->name);
4657 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4658
beb60608
CW		 4659 if (connector->status != connector_status_connected)
4660 return;
671dedd2 4661
25f78f58
VS		 4662 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4663 intel_display_power_get(dev_priv, power_domain);
beb60608
CW		 4664
4665 intel_dp_set_edid(intel_dp);
4666
25f78f58 4667 intel_display_power_put(dev_priv, power_domain);
beb60608
CW		 4668
4669 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4670 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4671}
4672
4673static int intel_dp_get_modes(struct drm_connector *connector)
4674{
4675 struct intel_connector *intel_connector = to_intel_connector(connector);
4676 struct edid *edid;
4677
4678 edid = intel_connector->detect_edid;
4679 if (edid) {
4680 int ret = intel_connector_update_modes(connector, edid);
4681 if (ret)
4682 return ret;
4683 }
32f9d658 4684
f8779fda 4685 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4686 if (is_edp(intel_attached_dp(connector)) &&
4687 intel_connector->panel.fixed_mode) {
f8779fda 4688 struct drm_display_mode *mode;
beb60608
CW		 4689
4690 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4691 intel_connector->panel.fixed_mode);
f8779fda 4692 if (mode) {
32f9d658
ZW		 4693 drm_mode_probed_add(connector, mode);
4694 return 1;
4695 }
4696 }
beb60608 4697
32f9d658 4698 return 0;
a4fc5ed6
KP		 4699}
4700
1aad7ac0
CW		 4701static bool
4702intel_dp_detect_audio(struct drm_connector *connector)
4703{
1aad7ac0 4704 bool has_audio = false;
beb60608 4705 struct edid *edid;
1aad7ac0 4706
beb60608
CW		 4707 edid = to_intel_connector(connector)->detect_edid;
4708 if (edid)
1aad7ac0 4709 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4710
1aad7ac0
CW		 4711 return has_audio;
4712}
4713
f684960e
CW		 4714static int
4715intel_dp_set_property(struct drm_connector *connector,
4716 struct drm_property *property,
4717 uint64_t val)
4718{
e953fd7b 4719 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4720 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4721 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4722 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4723 int ret;
4724
662595df 4725 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4726 if (ret)
4727 return ret;
4728
3f43c48d 4729 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4730 int i = val;
4731 bool has_audio;
4732
4733 if (i == intel_dp->force_audio)
f684960e
CW		 4734 return 0;
4735
1aad7ac0 4736 intel_dp->force_audio = i;
f684960e 4737
c3e5f67b 4738 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4739 has_audio = intel_dp_detect_audio(connector);
4740 else
c3e5f67b 4741 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4742
4743 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4744 return 0;
4745
1aad7ac0 4746 intel_dp->has_audio = has_audio;
f684960e
CW		 4747 goto done;
4748 }
4749
e953fd7b 4750 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 4751 bool old_auto = intel_dp->color_range_auto;
0f2a2a75 4752 bool old_range = intel_dp->limited_color_range;
ae4edb80 4753
55bc60db
VS		 4754 switch (val) {
4755 case INTEL_BROADCAST_RGB_AUTO:
4756 intel_dp->color_range_auto = true;
4757 break;
4758 case INTEL_BROADCAST_RGB_FULL:
4759 intel_dp->color_range_auto = false;
0f2a2a75 4760 intel_dp->limited_color_range = false;
55bc60db
VS		 4761 break;
4762 case INTEL_BROADCAST_RGB_LIMITED:
4763 intel_dp->color_range_auto = false;
0f2a2a75 4764 intel_dp->limited_color_range = true;
55bc60db
VS		 4765 break;
4766 default:
4767 return -EINVAL;
4768 }
ae4edb80
DV		 4769
4770 if (old_auto == intel_dp->color_range_auto &&
0f2a2a75 4771 old_range == intel_dp->limited_color_range)
ae4edb80
DV		 4772 return 0;
4773
e953fd7b
CW		 4774 goto done;
4775 }
4776
53b41837
YN		 4777 if (is_edp(intel_dp) &&
4778 property == connector->dev->mode_config.scaling_mode_property) {
4779 if (val == DRM_MODE_SCALE_NONE) {
4780 DRM_DEBUG_KMS("no scaling not supported\n");
4781 return -EINVAL;
4782 }
4783
4784 if (intel_connector->panel.fitting_mode == val) {
4785 /* the eDP scaling property is not changed */
4786 return 0;
4787 }
4788 intel_connector->panel.fitting_mode = val;
4789
4790 goto done;
4791 }
4792
f684960e
CW		 4793 return -EINVAL;
4794
4795done:
c0c36b94
CW		 4796 if (intel_encoder->base.crtc)
4797 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4798
4799 return 0;
4800}
4801
a4fc5ed6 4802static void
73845adf 4803intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4804{
1d508706 4805 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4806
10e972d3 4807 kfree(intel_connector->detect_edid);
beb60608 4808
9cd300e0
JN		 4809 if (!IS_ERR_OR_NULL(intel_connector->edid))
4810 kfree(intel_connector->edid);
4811
acd8db10
PZ		 4812 /* Can't call is_edp() since the encoder may have been destroyed
4813 * already. */
4814 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4815 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4816
a4fc5ed6 4817 drm_connector_cleanup(connector);
55f78c43 4818 kfree(connector);
a4fc5ed6
KP		 4819}
4820
00c09d70 4821void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4822{
da63a9f2
PZ		 4823 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4824 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4825
0e32b39c 4826 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4827 if (is_edp(intel_dp)) {
4828 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4829 /*
4830 * vdd might still be enabled do to the delayed vdd off.
4831 * Make sure vdd is actually turned off here.
4832 */
773538e8 4833 pps_lock(intel_dp);
4be73780 4834 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4835 pps_unlock(intel_dp);
4836
01527b31
CT		 4837 if (intel_dp->edp_notifier.notifier_call) {
4838 unregister_reboot_notifier(&intel_dp->edp_notifier);
4839 intel_dp->edp_notifier.notifier_call = NULL;
4840 }
bd943159 4841 }
c8bd0e49 4842 drm_encoder_cleanup(encoder);
da63a9f2 4843 kfree(intel_dig_port);
24d05927
DV		 4844}
4845
07f9cd0b
ID		 4846static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4847{
4848 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4849
4850 if (!is_edp(intel_dp))
4851 return;
4852
951468f3
VS		 4853 /*
4854 * vdd might still be enabled do to the delayed vdd off.
4855 * Make sure vdd is actually turned off here.
4856 */
afa4e53a 4857 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4858 pps_lock(intel_dp);
07f9cd0b 4859 edp_panel_vdd_off_sync(intel_dp);
773538e8 4860 pps_unlock(intel_dp);
07f9cd0b
ID		 4861}
4862
49e6bc51
VS		 4863static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4864{
4865 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4866 struct drm_device *dev = intel_dig_port->base.base.dev;
4867 struct drm_i915_private *dev_priv = dev->dev_private;
4868 enum intel_display_power_domain power_domain;
4869
4870 lockdep_assert_held(&dev_priv->pps_mutex);
4871
4872 if (!edp_have_panel_vdd(intel_dp))
4873 return;
4874
4875 /*
4876 * The VDD bit needs a power domain reference, so if the bit is
4877 * already enabled when we boot or resume, grab this reference and
4878 * schedule a vdd off, so we don't hold on to the reference
4879 * indefinitely.
4880 */
4881 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
25f78f58 4882 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
49e6bc51
VS		 4883 intel_display_power_get(dev_priv, power_domain);
4884
4885 edp_panel_vdd_schedule_off(intel_dp);
4886}
4887
6d93c0c4
ID		 4888static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4889{
49e6bc51
VS		 4890 struct intel_dp *intel_dp;
4891
4892 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4893 return;
4894
4895 intel_dp = enc_to_intel_dp(encoder);
4896
4897 pps_lock(intel_dp);
4898
4899 /*
4900 * Read out the current power sequencer assignment,
4901 * in case the BIOS did something with it.
4902 */
666a4537 4903 if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
49e6bc51
VS		 4904 vlv_initial_power_sequencer_setup(intel_dp);
4905
4906 intel_edp_panel_vdd_sanitize(intel_dp);
4907
4908 pps_unlock(intel_dp);
6d93c0c4
ID		 4909}
4910
a4fc5ed6 4911static const struct drm_connector_funcs intel_dp_connector_funcs = {
4d688a2a 4912 .dpms = drm_atomic_helper_connector_dpms,
a4fc5ed6 4913 .detect = intel_dp_detect,
beb60608 4914 .force = intel_dp_force,
a4fc5ed6 4915 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4916 .set_property = intel_dp_set_property,
2545e4a6 4917 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4918 .destroy = intel_dp_connector_destroy,
c6f95f27 4919 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4920 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4921};
4922
4923static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4924 .get_modes = intel_dp_get_modes,
4925 .mode_valid = intel_dp_mode_valid,
df0e9248 4926 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4927};
4928
a4fc5ed6 4929static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4930 .reset = intel_dp_encoder_reset,
24d05927 4931 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4932};
4933
b2c5c181 4934enum irqreturn
13cf5504
DA		 4935intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4936{
4937 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4938 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4939 struct drm_device *dev = intel_dig_port->base.base.dev;
4940 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4941 enum intel_display_power_domain power_domain;
b2c5c181 4942 enum irqreturn ret = IRQ_NONE;
1c767b33 4943
2540058f
TI		 4944 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4945 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
0e32b39c 4946 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4947
7a7f84cc
VS		 4948 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4949 /*
4950 * vdd off can generate a long pulse on eDP which
4951 * would require vdd on to handle it, and thus we
4952 * would end up in an endless cycle of
4953 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4954 */
4955 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4956 port_name(intel_dig_port->port));
a8b3d52f 4957 return IRQ_HANDLED;
7a7f84cc
VS		 4958 }
4959
26fbb774
VS		 4960 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4961 port_name(intel_dig_port->port),
0e32b39c 4962 long_hpd ? "long" : "short");
13cf5504 4963
25f78f58 4964 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1c767b33
ID		 4965 intel_display_power_get(dev_priv, power_domain);
4966
0e32b39c 4967 if (long_hpd) {
5fa836a9
MK		 4968 /* indicate that we need to restart link training */
4969 intel_dp->train_set_valid = false;
2a592bec 4970
7e66bcf2
JN		 4971 if (!intel_digital_port_connected(dev_priv, intel_dig_port))
4972 goto mst_fail;
0e32b39c
DA		 4973
4974 if (!intel_dp_get_dpcd(intel_dp)) {
4975 goto mst_fail;
4976 }
4977
4978 intel_dp_probe_oui(intel_dp);
4979
d14e7b6d
VS		 4980 if (!intel_dp_probe_mst(intel_dp)) {
4981 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4982 intel_dp_check_link_status(intel_dp);
4983 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c 4984 goto mst_fail;
d14e7b6d 4985 }
0e32b39c
DA		 4986 } else {
4987 if (intel_dp->is_mst) {
1c767b33 4988 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4989 goto mst_fail;
4990 }
4991
4992 if (!intel_dp->is_mst) {
5b215bcf 4993 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4994 intel_dp_check_link_status(intel_dp);
5b215bcf 4995 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4996 }
4997 }
b2c5c181
DV		 4998
4999 ret = IRQ_HANDLED;
5000
1c767b33 5001 goto put_power;
0e32b39c
DA		 5002mst_fail:
5003 /* if we were in MST mode, and device is not there get out of MST mode */
5004 if (intel_dp->is_mst) {
5005 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5006 intel_dp->is_mst = false;
5007 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
5008 }
1c767b33
ID		 5009put_power:
5010 intel_display_power_put(dev_priv, power_domain);
5011
5012 return ret;
13cf5504
DA		 5013}
5014
477ec328 5015/* check the VBT to see whether the eDP is on another port */
5d8a7752 5016bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 5017{
5018 struct drm_i915_private *dev_priv = dev->dev_private;
36e83a18 5019
53ce81a7
VS		 5020 /*
5021 * eDP not supported on g4x. so bail out early just
5022 * for a bit extra safety in case the VBT is bonkers.
5023 */
5024 if (INTEL_INFO(dev)->gen < 5)
5025 return false;
5026
3b32a35b
VS		 5027 if (port == PORT_A)
5028 return true;
5029
951d9efe 5030 return intel_bios_is_port_edp(dev_priv, port);
36e83a18
ZY		 5031}
5032
0e32b39c 5033void
f684960e
CW		 5034intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5035{
53b41837
YN		 5036 struct intel_connector *intel_connector = to_intel_connector(connector);
5037
3f43c48d 5038 intel_attach_force_audio_property(connector);
e953fd7b 5039 intel_attach_broadcast_rgb_property(connector);
55bc60db 5040 intel_dp->color_range_auto = true;
53b41837
YN		 5041
5042 if (is_edp(intel_dp)) {
5043 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 5044 drm_object_attach_property(
5045 &connector->base,
53b41837 5046 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 5047 DRM_MODE_SCALE_ASPECT);
5048 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 5049 }
f684960e
CW		 5050}
5051
dada1a9f
ID		 5052static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5053{
d28d4731 5054 intel_dp->panel_power_off_time = ktime_get_boottime();
dada1a9f
ID		 5055 intel_dp->last_power_on = jiffies;
5056 intel_dp->last_backlight_off = jiffies;
5057}
5058
67a54566
DV		 5059static void
5060intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 5061 struct intel_dp *intel_dp)
67a54566
DV		 5062{
5063 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 5064 struct edp_power_seq cur, vbt, spec,
5065 *final = &intel_dp->pps_delays;
b0a08bec 5066 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
f0f59a00 5067 i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 5068
e39b999a
VS		 5069 lockdep_assert_held(&dev_priv->pps_mutex);
5070
81ddbc69
VS		 5071 /* already initialized? */
5072 if (final->t11_t12 != 0)
5073 return;
5074
b0a08bec
VK		 5075 if (IS_BROXTON(dev)) {
5076 /*
5077 * TODO: BXT has 2 sets of PPS registers.
5078 * Correct Register for Broxton need to be identified
5079 * using VBT. hardcoding for now
5080 */
5081 pp_ctrl_reg = BXT_PP_CONTROL(0);
5082 pp_on_reg = BXT_PP_ON_DELAYS(0);
5083 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5084 } else if (HAS_PCH_SPLIT(dev)) {
bf13e81b 5085 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 5086 pp_on_reg = PCH_PP_ON_DELAYS;
5087 pp_off_reg = PCH_PP_OFF_DELAYS;
5088 pp_div_reg = PCH_PP_DIVISOR;
5089 } else {
bf13e81b
JN		 5090 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5091
5092 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5093 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5094 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5095 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 5096 }
67a54566
DV		 5097
5098 /* Workaround: Need to write PP_CONTROL with the unlock key as
5099 * the very first thing. */
b0a08bec 5100 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 5101
453c5420
JB		 5102 pp_on = I915_READ(pp_on_reg);
5103 pp_off = I915_READ(pp_off_reg);
b0a08bec
VK		 5104 if (!IS_BROXTON(dev)) {
5105 I915_WRITE(pp_ctrl_reg, pp_ctl);
5106 pp_div = I915_READ(pp_div_reg);
5107 }
67a54566
DV		 5108
5109 /* Pull timing values out of registers */
5110 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5111 PANEL_POWER_UP_DELAY_SHIFT;
5112
5113 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5114 PANEL_LIGHT_ON_DELAY_SHIFT;
5115
5116 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5117 PANEL_LIGHT_OFF_DELAY_SHIFT;
5118
5119 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5120 PANEL_POWER_DOWN_DELAY_SHIFT;
5121
b0a08bec
VK		 5122 if (IS_BROXTON(dev)) {
5123 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5124 BXT_POWER_CYCLE_DELAY_SHIFT;
5125 if (tmp > 0)
5126 cur.t11_t12 = (tmp - 1) * 1000;
5127 else
5128 cur.t11_t12 = 0;
5129 } else {
5130 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 5131 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 5132 }
67a54566
DV		 5133
5134 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5135 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5136
6aa23e65 5137 vbt = dev_priv->vbt.edp.pps;
67a54566
DV		 5138
5139 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5140 * our hw here, which are all in 100usec. */
5141 spec.t1_t3 = 210 * 10;
5142 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5143 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5144 spec.t10 = 500 * 10;
5145 /* This one is special and actually in units of 100ms, but zero
5146 * based in the hw (so we need to add 100 ms). But the sw vbt
5147 * table multiplies it with 1000 to make it in units of 100usec,
5148 * too. */
5149 spec.t11_t12 = (510 + 100) * 10;
5150
5151 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5152 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5153
5154 /* Use the max of the register settings and vbt. If both are
5155 * unset, fall back to the spec limits. */
36b5f425 5156#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 5157 spec.field : \
5158 max(cur.field, vbt.field))
5159 assign_final(t1_t3);
5160 assign_final(t8);
5161 assign_final(t9);
5162 assign_final(t10);
5163 assign_final(t11_t12);
5164#undef assign_final
5165
36b5f425 5166#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 5167 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5168 intel_dp->backlight_on_delay = get_delay(t8);
5169 intel_dp->backlight_off_delay = get_delay(t9);
5170 intel_dp->panel_power_down_delay = get_delay(t10);
5171 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5172#undef get_delay
5173
f30d26e4
JN		 5174 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5175 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5176 intel_dp->panel_power_cycle_delay);
5177
5178 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5179 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 5180}
5181
5182static void
5183intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 5184 struct intel_dp *intel_dp)
f30d26e4
JN		 5185{
5186 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 5187 u32 pp_on, pp_off, pp_div, port_sel = 0;
e7dc33f3 5188 int div = dev_priv->rawclk_freq / 1000;
f0f59a00 5189 i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg;
ad933b56 5190 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 5191 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 5192
e39b999a 5193 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 5194
b0a08bec
VK		 5195 if (IS_BROXTON(dev)) {
5196 /*
5197 * TODO: BXT has 2 sets of PPS registers.
5198 * Correct Register for Broxton need to be identified
5199 * using VBT. hardcoding for now
5200 */
5201 pp_ctrl_reg = BXT_PP_CONTROL(0);
5202 pp_on_reg = BXT_PP_ON_DELAYS(0);
5203 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5204
5205 } else if (HAS_PCH_SPLIT(dev)) {
453c5420
JB		 5206 pp_on_reg = PCH_PP_ON_DELAYS;
5207 pp_off_reg = PCH_PP_OFF_DELAYS;
5208 pp_div_reg = PCH_PP_DIVISOR;
5209 } else {
bf13e81b
JN		 5210 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5211
5212 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5213 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5214 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 5215 }
5216
b2f19d1a
PZ		 5217 /*
5218 * And finally store the new values in the power sequencer. The
5219 * backlight delays are set to 1 because we do manual waits on them. For
5220 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5221 * we'll end up waiting for the backlight off delay twice: once when we
5222 * do the manual sleep, and once when we disable the panel and wait for
5223 * the PP_STATUS bit to become zero.
5224 */
f30d26e4 5225 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 5226 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5227 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5228 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5229 /* Compute the divisor for the pp clock, simply match the Bspec
5230 * formula. */
b0a08bec
VK		 5231 if (IS_BROXTON(dev)) {
5232 pp_div = I915_READ(pp_ctrl_reg);
5233 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5234 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5235 << BXT_POWER_CYCLE_DELAY_SHIFT);
5236 } else {
5237 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5238 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5239 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5240 }
67a54566
DV		 5241
5242 /* Haswell doesn't have any port selection bits for the panel
5243 * power sequencer any more. */
666a4537 5244 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
ad933b56 5245 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 5246 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 5247 if (port == PORT_A)
a24c144c 5248 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5249 else
a24c144c 5250 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5251 }
5252
453c5420
JB		 5253 pp_on |= port_sel;
5254
5255 I915_WRITE(pp_on_reg, pp_on);
5256 I915_WRITE(pp_off_reg, pp_off);
b0a08bec
VK		 5257 if (IS_BROXTON(dev))
5258 I915_WRITE(pp_ctrl_reg, pp_div);
5259 else
5260 I915_WRITE(pp_div_reg, pp_div);
67a54566 5261
67a54566 5262 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 5263 I915_READ(pp_on_reg),
5264 I915_READ(pp_off_reg),
b0a08bec
VK		 5265 IS_BROXTON(dev) ?
5266 (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
453c5420 5267 I915_READ(pp_div_reg));
f684960e
CW		 5268}
5269
b33a2815
VK		 5270/**
5271 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5272 * @dev: DRM device
5273 * @refresh_rate: RR to be programmed
5274 *
5275 * This function gets called when refresh rate (RR) has to be changed from
5276 * one frequency to another. Switches can be between high and low RR
5277 * supported by the panel or to any other RR based on media playback (in
5278 * this case, RR value needs to be passed from user space).
5279 *
5280 * The caller of this function needs to take a lock on dev_priv->drrs.
5281 */
96178eeb 5282static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 5283{
5284 struct drm_i915_private *dev_priv = dev->dev_private;
5285 struct intel_encoder *encoder;
96178eeb
VK		 5286 struct intel_digital_port *dig_port = NULL;
5287 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 5288 struct intel_crtc_state *config = NULL;
439d7ac0 5289 struct intel_crtc *intel_crtc = NULL;
96178eeb 5290 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5291
5292 if (refresh_rate <= 0) {
5293 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5294 return;
5295 }
5296
96178eeb
VK		 5297 if (intel_dp == NULL) {
5298 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5299 return;
5300 }
5301
1fcc9d1c 5302 /*
e4d59f6b
RV		 5303 * FIXME: This needs proper synchronization with psr state for some
5304 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5305 */
439d7ac0 5306
96178eeb
VK		 5307 dig_port = dp_to_dig_port(intel_dp);
5308 encoder = &dig_port->base;
723f9aab 5309 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5310
5311 if (!intel_crtc) {
5312 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5313 return;
5314 }
5315
6e3c9717 5316 config = intel_crtc->config;
439d7ac0 5317
96178eeb 5318 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5319 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5320 return;
5321 }
5322
96178eeb
VK		 5323 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5324 refresh_rate)
439d7ac0
PB		 5325 index = DRRS_LOW_RR;
5326
96178eeb 5327 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5328 DRM_DEBUG_KMS(
5329 "DRRS requested for previously set RR...ignoring\n");
5330 return;
5331 }
5332
5333 if (!intel_crtc->active) {
5334 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5335 return;
5336 }
5337
44395bfe 5338 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5339 switch (index) {
5340 case DRRS_HIGH_RR:
5341 intel_dp_set_m_n(intel_crtc, M1_N1);
5342 break;
5343 case DRRS_LOW_RR:
5344 intel_dp_set_m_n(intel_crtc, M2_N2);
5345 break;
5346 case DRRS_MAX_RR:
5347 default:
5348 DRM_ERROR("Unsupported refreshrate type\n");
5349 }
5350 } else if (INTEL_INFO(dev)->gen > 6) {
f0f59a00 5351 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
649636ef 5352 u32 val;
a4c30b1d 5353
649636ef 5354 val = I915_READ(reg);
439d7ac0 5355 if (index > DRRS_HIGH_RR) {
666a4537 5356 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6fa7aec1
VK		 5357 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5358 else
5359 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5360 } else {
666a4537 5361 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6fa7aec1
VK		 5362 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5363 else
5364 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5365 }
5366 I915_WRITE(reg, val);
5367 }
5368
4e9ac947
VK		 5369 dev_priv->drrs.refresh_rate_type = index;
5370
5371 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5372}
5373
b33a2815
VK		 5374/**
5375 * intel_edp_drrs_enable - init drrs struct if supported
5376 * @intel_dp: DP struct
5377 *
5378 * Initializes frontbuffer_bits and drrs.dp
5379 */
c395578e
VK		 5380void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5381{
5382 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5383 struct drm_i915_private *dev_priv = dev->dev_private;
5384 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5385 struct drm_crtc *crtc = dig_port->base.base.crtc;
5386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5387
5388 if (!intel_crtc->config->has_drrs) {
5389 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5390 return;
5391 }
5392
5393 mutex_lock(&dev_priv->drrs.mutex);
5394 if (WARN_ON(dev_priv->drrs.dp)) {
5395 DRM_ERROR("DRRS already enabled\n");
5396 goto unlock;
5397 }
5398
5399 dev_priv->drrs.busy_frontbuffer_bits = 0;
5400
5401 dev_priv->drrs.dp = intel_dp;
5402
5403unlock:
5404 mutex_unlock(&dev_priv->drrs.mutex);
5405}
5406
b33a2815
VK		 5407/**
5408 * intel_edp_drrs_disable - Disable DRRS
5409 * @intel_dp: DP struct
5410 *
5411 */
c395578e
VK		 5412void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5413{
5414 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5415 struct drm_i915_private *dev_priv = dev->dev_private;
5416 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5417 struct drm_crtc *crtc = dig_port->base.base.crtc;
5418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5419
5420 if (!intel_crtc->config->has_drrs)
5421 return;
5422
5423 mutex_lock(&dev_priv->drrs.mutex);
5424 if (!dev_priv->drrs.dp) {
5425 mutex_unlock(&dev_priv->drrs.mutex);
5426 return;
5427 }
5428
5429 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5430 intel_dp_set_drrs_state(dev_priv->dev,
5431 intel_dp->attached_connector->panel.
5432 fixed_mode->vrefresh);
5433
5434 dev_priv->drrs.dp = NULL;
5435 mutex_unlock(&dev_priv->drrs.mutex);
5436
5437 cancel_delayed_work_sync(&dev_priv->drrs.work);
5438}
5439
4e9ac947
VK		 5440static void intel_edp_drrs_downclock_work(struct work_struct *work)
5441{
5442 struct drm_i915_private *dev_priv =
5443 container_of(work, typeof(*dev_priv), drrs.work.work);
5444 struct intel_dp *intel_dp;
5445
5446 mutex_lock(&dev_priv->drrs.mutex);
5447
5448 intel_dp = dev_priv->drrs.dp;
5449
5450 if (!intel_dp)
5451 goto unlock;
5452
439d7ac0 5453 /*
4e9ac947
VK		 5454 * The delayed work can race with an invalidate hence we need to
5455 * recheck.
439d7ac0
PB		 5456 */
5457
4e9ac947
VK		 5458 if (dev_priv->drrs.busy_frontbuffer_bits)
5459 goto unlock;
439d7ac0 5460
4e9ac947
VK		 5461 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5462 intel_dp_set_drrs_state(dev_priv->dev,
5463 intel_dp->attached_connector->panel.
5464 downclock_mode->vrefresh);
439d7ac0 5465
4e9ac947 5466unlock:
4e9ac947 5467 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5468}
5469
b33a2815 5470/**
0ddfd203 5471 * intel_edp_drrs_invalidate - Disable Idleness DRRS
b33a2815
VK		 5472 * @dev: DRM device
5473 * @frontbuffer_bits: frontbuffer plane tracking bits
5474 *
0ddfd203
R		 5475 * This function gets called everytime rendering on the given planes start.
5476 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5477 *
5478 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5479 */
a93fad0f
VK		 5480void intel_edp_drrs_invalidate(struct drm_device *dev,
5481 unsigned frontbuffer_bits)
5482{
5483 struct drm_i915_private *dev_priv = dev->dev_private;
5484 struct drm_crtc *crtc;
5485 enum pipe pipe;
5486
9da7d693 5487 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5488 return;
5489
88f933a8 5490 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5491
a93fad0f 5492 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5493 if (!dev_priv->drrs.dp) {
5494 mutex_unlock(&dev_priv->drrs.mutex);
5495 return;
5496 }
5497
a93fad0f
VK		 5498 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5499 pipe = to_intel_crtc(crtc)->pipe;
5500
c1d038c6
DV		 5501 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5502 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5503
0ddfd203 5504 /* invalidate means busy screen hence upclock */
c1d038c6 5505 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
a93fad0f
VK		 5506 intel_dp_set_drrs_state(dev_priv->dev,
5507 dev_priv->drrs.dp->attached_connector->panel.
5508 fixed_mode->vrefresh);
a93fad0f 5509
a93fad0f
VK		 5510 mutex_unlock(&dev_priv->drrs.mutex);
5511}
5512
b33a2815 5513/**
0ddfd203 5514 * intel_edp_drrs_flush - Restart Idleness DRRS
b33a2815
VK		 5515 * @dev: DRM device
5516 * @frontbuffer_bits: frontbuffer plane tracking bits
5517 *
0ddfd203
R		 5518 * This function gets called every time rendering on the given planes has
5519 * completed or flip on a crtc is completed. So DRRS should be upclocked
5520 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5521 * if no other planes are dirty.
b33a2815
VK		 5522 *
5523 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5524 */
a93fad0f
VK		 5525void intel_edp_drrs_flush(struct drm_device *dev,
5526 unsigned frontbuffer_bits)
5527{
5528 struct drm_i915_private *dev_priv = dev->dev_private;
5529 struct drm_crtc *crtc;
5530 enum pipe pipe;
5531
9da7d693 5532 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5533 return;
5534
88f933a8 5535 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5536
a93fad0f 5537 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5538 if (!dev_priv->drrs.dp) {
5539 mutex_unlock(&dev_priv->drrs.mutex);
5540 return;
5541 }
5542
a93fad0f
VK		 5543 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5544 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5545
5546 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5547 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5548
0ddfd203 5549 /* flush means busy screen hence upclock */
c1d038c6 5550 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
0ddfd203
R		 5551 intel_dp_set_drrs_state(dev_priv->dev,
5552 dev_priv->drrs.dp->attached_connector->panel.
5553 fixed_mode->vrefresh);
5554
5555 /*
5556 * flush also means no more activity hence schedule downclock, if all
5557 * other fbs are quiescent too
5558 */
5559 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5560 schedule_delayed_work(&dev_priv->drrs.work,
5561 msecs_to_jiffies(1000));
5562 mutex_unlock(&dev_priv->drrs.mutex);
5563}
5564
b33a2815
VK		 5565/**
5566 * DOC: Display Refresh Rate Switching (DRRS)
5567 *
5568 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5569 * which enables swtching between low and high refresh rates,
5570 * dynamically, based on the usage scenario. This feature is applicable
5571 * for internal panels.
5572 *
5573 * Indication that the panel supports DRRS is given by the panel EDID, which
5574 * would list multiple refresh rates for one resolution.
5575 *
5576 * DRRS is of 2 types - static and seamless.
5577 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5578 * (may appear as a blink on screen) and is used in dock-undock scenario.
5579 * Seamless DRRS involves changing RR without any visual effect to the user
5580 * and can be used during normal system usage. This is done by programming
5581 * certain registers.
5582 *
5583 * Support for static/seamless DRRS may be indicated in the VBT based on
5584 * inputs from the panel spec.
5585 *
5586 * DRRS saves power by switching to low RR based on usage scenarios.
5587 *
5588 * eDP DRRS:-
5589 * The implementation is based on frontbuffer tracking implementation.
5590 * When there is a disturbance on the screen triggered by user activity or a
5591 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5592 * When there is no movement on screen, after a timeout of 1 second, a switch
5593 * to low RR is made.
5594 * For integration with frontbuffer tracking code,
5595 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5596 *
5597 * DRRS can be further extended to support other internal panels and also
5598 * the scenario of video playback wherein RR is set based on the rate
5599 * requested by userspace.
5600 */
5601
5602/**
5603 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5604 * @intel_connector: eDP connector
5605 * @fixed_mode: preferred mode of panel
5606 *
5607 * This function is called only once at driver load to initialize basic
5608 * DRRS stuff.
5609 *
5610 * Returns:
5611 * Downclock mode if panel supports it, else return NULL.
5612 * DRRS support is determined by the presence of downclock mode (apart
5613 * from VBT setting).
5614 */
4f9db5b5 5615static struct drm_display_mode *
96178eeb
VK		 5616intel_dp_drrs_init(struct intel_connector *intel_connector,
5617 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5618{
5619 struct drm_connector *connector = &intel_connector->base;
96178eeb 5620 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5621 struct drm_i915_private *dev_priv = dev->dev_private;
5622 struct drm_display_mode *downclock_mode = NULL;
5623
9da7d693
DV		 5624 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5625 mutex_init(&dev_priv->drrs.mutex);
5626
4f9db5b5
PB		 5627 if (INTEL_INFO(dev)->gen <= 6) {
5628 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5629 return NULL;
5630 }
5631
5632 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5633 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5634 return NULL;
5635 }
5636
5637 downclock_mode = intel_find_panel_downclock
5638 (dev, fixed_mode, connector);
5639
5640 if (!downclock_mode) {
a1d26342 5641 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5642 return NULL;
5643 }
5644
96178eeb 5645 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5646
96178eeb 5647 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5648 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5649 return downclock_mode;
5650}
5651
ed92f0b2 5652static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5653 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5654{
5655 struct drm_connector *connector = &intel_connector->base;
5656 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5657 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5658 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5659 struct drm_i915_private *dev_priv = dev->dev_private;
5660 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5661 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5662 bool has_dpcd;
5663 struct drm_display_mode *scan;
5664 struct edid *edid;
6517d273 5665 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5666
5667 if (!is_edp(intel_dp))
5668 return true;
5669
49e6bc51
VS		 5670 pps_lock(intel_dp);
5671 intel_edp_panel_vdd_sanitize(intel_dp);
5672 pps_unlock(intel_dp);
63635217 5673
ed92f0b2 5674 /* Cache DPCD and EDID for edp. */
ed92f0b2 5675 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5676
5677 if (has_dpcd) {
5678 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5679 dev_priv->no_aux_handshake =
5680 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5681 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5682 } else {
5683 /* if this fails, presume the device is a ghost */
5684 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5685 return false;
5686 }
5687
5688 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5689 pps_lock(intel_dp);
36b5f425 5690 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5691 pps_unlock(intel_dp);
ed92f0b2 5692
060c8778 5693 mutex_lock(&dev->mode_config.mutex);
0b99836f 5694 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5695 if (edid) {
5696 if (drm_add_edid_modes(connector, edid)) {
5697 drm_mode_connector_update_edid_property(connector,
5698 edid);
5699 drm_edid_to_eld(connector, edid);
5700 } else {
5701 kfree(edid);
5702 edid = ERR_PTR(-EINVAL);
5703 }
5704 } else {
5705 edid = ERR_PTR(-ENOENT);
5706 }
5707 intel_connector->edid = edid;
5708
5709 /* prefer fixed mode from EDID if available */
5710 list_for_each_entry(scan, &connector->probed_modes, head) {
5711 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5712 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5713 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5714 intel_connector, fixed_mode);
ed92f0b2
PZ		 5715 break;
5716 }
5717 }
5718
5719 /* fallback to VBT if available for eDP */
5720 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5721 fixed_mode = drm_mode_duplicate(dev,
5722 dev_priv->vbt.lfp_lvds_vbt_mode);
5723 if (fixed_mode)
5724 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5725 }
060c8778 5726 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5727
666a4537 5728 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
01527b31
CT		 5729 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5730 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5731
5732 /*
5733 * Figure out the current pipe for the initial backlight setup.
5734 * If the current pipe isn't valid, try the PPS pipe, and if that
5735 * fails just assume pipe A.
5736 */
5737 if (IS_CHERRYVIEW(dev))
5738 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5739 else
5740 pipe = PORT_TO_PIPE(intel_dp->DP);
5741
5742 if (pipe != PIPE_A && pipe != PIPE_B)
5743 pipe = intel_dp->pps_pipe;
5744
5745 if (pipe != PIPE_A && pipe != PIPE_B)
5746 pipe = PIPE_A;
5747
5748 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5749 pipe_name(pipe));
01527b31
CT		 5750 }
5751
4f9db5b5 5752 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5507faeb 5753 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6517d273 5754 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5755
5756 return true;
5757}
5758
16c25533 5759bool
f0fec3f2
PZ		 5760intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5761 struct intel_connector *intel_connector)
a4fc5ed6 5762{
f0fec3f2
PZ		 5763 struct drm_connector *connector = &intel_connector->base;
5764 struct intel_dp *intel_dp = &intel_dig_port->dp;
5765 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5766 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5767 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5768 enum port port = intel_dig_port->port;
a121f4e5 5769 int type, ret;
a4fc5ed6 5770
ccb1a831
VS		 5771 if (WARN(intel_dig_port->max_lanes < 1,
5772 "Not enough lanes (%d) for DP on port %c\n",
5773 intel_dig_port->max_lanes, port_name(port)))
5774 return false;
5775
a4a5d2f8
VS		 5776 intel_dp->pps_pipe = INVALID_PIPE;
5777
ec5b01dd 5778 /* intel_dp vfuncs */
b6b5e383
DL		 5779 if (INTEL_INFO(dev)->gen >= 9)
5780 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
ec5b01dd
DL		 5781 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5782 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5783 else if (HAS_PCH_SPLIT(dev))
5784 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5785 else
6ffb1be7 5786 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
ec5b01dd 5787
b9ca5fad
DL		 5788 if (INTEL_INFO(dev)->gen >= 9)
5789 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5790 else
6ffb1be7 5791 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
153b1100 5792
ad64217b
ACO		 5793 if (HAS_DDI(dev))
5794 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5795
0767935e
DV		 5796 /* Preserve the current hw state. */
5797 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5798 intel_dp->attached_connector = intel_connector;
3d3dc149 5799
3b32a35b 5800 if (intel_dp_is_edp(dev, port))
b329530c 5801 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5802 else
5803 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5804
f7d24902
ID		 5805 /*
5806 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5807 * for DP the encoder type can be set by the caller to
5808 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5809 */
5810 if (type == DRM_MODE_CONNECTOR_eDP)
5811 intel_encoder->type = INTEL_OUTPUT_EDP;
5812
c17ed5b5 5813 /* eDP only on port B and/or C on vlv/chv */
666a4537
WB		 5814 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5815 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
c17ed5b5
VS		 5816 return false;
5817
e7281eab
ID		 5818 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5819 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5820 port_name(port));
5821
b329530c 5822 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5823 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5824
a4fc5ed6
KP		 5825 connector->interlace_allowed = true;
5826 connector->doublescan_allowed = 0;
5827
f0fec3f2 5828 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5829 edp_panel_vdd_work);
a4fc5ed6 5830
df0e9248 5831 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5832 drm_connector_register(connector);
a4fc5ed6 5833
affa9354 5834 if (HAS_DDI(dev))
bcbc889b
PZ		 5835 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5836 else
5837 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5838 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5839
0b99836f 5840 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5841 switch (port) {
5842 case PORT_A:
1d843f9d 5843 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5844 break;
5845 case PORT_B:
1d843f9d 5846 intel_encoder->hpd_pin = HPD_PORT_B;
e87a005d 5847 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
cf1d5883 5848 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5849 break;
5850 case PORT_C:
1d843f9d 5851 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5852 break;
5853 case PORT_D:
1d843f9d 5854 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30 5855 break;
26951caf
XZ		 5856 case PORT_E:
5857 intel_encoder->hpd_pin = HPD_PORT_E;
5858 break;
ab9d7c30 5859 default:
ad1c0b19 5860 BUG();
5eb08b69
ZW		 5861 }
5862
dada1a9f 5863 if (is_edp(intel_dp)) {
773538e8 5864 pps_lock(intel_dp);
1e74a324 5865 intel_dp_init_panel_power_timestamps(intel_dp);
666a4537 5866 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
a4a5d2f8 5867 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5868 else
36b5f425 5869 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5870 pps_unlock(intel_dp);
dada1a9f 5871 }
0095e6dc 5872
a121f4e5
VS		 5873 ret = intel_dp_aux_init(intel_dp, intel_connector);
5874 if (ret)
5875 goto fail;
c1f05264 5876
0e32b39c 5877 /* init MST on ports that can support it */
0c9b3715
JN		 5878 if (HAS_DP_MST(dev) &&
5879 (port == PORT_B || port == PORT_C || port == PORT_D))
5880 intel_dp_mst_encoder_init(intel_dig_port,
5881 intel_connector->base.base.id);
0e32b39c 5882
36b5f425 5883 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
a121f4e5
VS		 5884 intel_dp_aux_fini(intel_dp);
5885 intel_dp_mst_encoder_cleanup(intel_dig_port);
5886 goto fail;
b2f246a8 5887 }
32f9d658 5888
f684960e
CW		 5889 intel_dp_add_properties(intel_dp, connector);
5890
a4fc5ed6
KP		 5891 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5892 * 0xd. Failure to do so will result in spurious interrupts being
5893 * generated on the port when a cable is not attached.
5894 */
5895 if (IS_G4X(dev) && !IS_GM45(dev)) {
5896 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5897 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5898 }
16c25533 5899
aa7471d2
JN		 5900 i915_debugfs_connector_add(connector);
5901
16c25533 5902 return true;
a121f4e5
VS		 5903
5904fail:
5905 if (is_edp(intel_dp)) {
5906 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5907 /*
5908 * vdd might still be enabled do to the delayed vdd off.
5909 * Make sure vdd is actually turned off here.
5910 */
5911 pps_lock(intel_dp);
5912 edp_panel_vdd_off_sync(intel_dp);
5913 pps_unlock(intel_dp);
5914 }
5915 drm_connector_unregister(connector);
5916 drm_connector_cleanup(connector);
5917
5918 return false;
a4fc5ed6 5919}
f0fec3f2
PZ		 5920
5921void
f0f59a00
VS		 5922intel_dp_init(struct drm_device *dev,
5923 i915_reg_t output_reg, enum port port)
f0fec3f2 5924{
13cf5504 5925 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5926 struct intel_digital_port *intel_dig_port;
5927 struct intel_encoder *intel_encoder;
5928 struct drm_encoder *encoder;
5929 struct intel_connector *intel_connector;
5930
b14c5679 5931 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5932 if (!intel_dig_port)
5933 return;
5934
08d9bc92 5935 intel_connector = intel_connector_alloc();
11aee0f6
SM		 5936 if (!intel_connector)
5937 goto err_connector_alloc;
f0fec3f2
PZ		 5938
5939 intel_encoder = &intel_dig_port->base;
5940 encoder = &intel_encoder->base;
5941
893da0c9 5942 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
ade1ba73 5943 DRM_MODE_ENCODER_TMDS, NULL))
893da0c9 5944 goto err_encoder_init;
f0fec3f2 5945
5bfe2ac0 5946 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5947 intel_encoder->disable = intel_disable_dp;
00c09d70 5948 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5949 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5950 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5951 if (IS_CHERRYVIEW(dev)) {
9197c88b 5952 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5953 intel_encoder->pre_enable = chv_pre_enable_dp;
5954 intel_encoder->enable = vlv_enable_dp;
580d3811 5955 intel_encoder->post_disable = chv_post_disable_dp;
d6db995f 5956 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
e4a1d846 5957 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5958 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5959 intel_encoder->pre_enable = vlv_pre_enable_dp;
5960 intel_encoder->enable = vlv_enable_dp;
49277c31 5961 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5962 } else {
ecff4f3b
JN		 5963 intel_encoder->pre_enable = g4x_pre_enable_dp;
5964 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5965 if (INTEL_INFO(dev)->gen >= 5)
5966 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5967 }
f0fec3f2 5968
174edf1f 5969 intel_dig_port->port = port;
f0fec3f2 5970 intel_dig_port->dp.output_reg = output_reg;
ccb1a831 5971 intel_dig_port->max_lanes = 4;
f0fec3f2 5972
00c09d70 5973 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5974 if (IS_CHERRYVIEW(dev)) {
5975 if (port == PORT_D)
5976 intel_encoder->crtc_mask = 1 << 2;
5977 else
5978 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5979 } else {
5980 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5981 }
bc079e8b 5982 intel_encoder->cloneable = 0;
f0fec3f2 5983
13cf5504 5984 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 5985 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 5986
11aee0f6
SM		 5987 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5988 goto err_init_connector;
5989
5990 return;
5991
5992err_init_connector:
5993 drm_encoder_cleanup(encoder);
893da0c9 5994err_encoder_init:
11aee0f6
SM		 5995 kfree(intel_connector);
5996err_connector_alloc:
5997 kfree(intel_dig_port);
5998
5999 return;
f0fec3f2 6000}
0e32b39c
DA		 6001
6002void intel_dp_mst_suspend(struct drm_device *dev)
6003{
6004 struct drm_i915_private *dev_priv = dev->dev_private;
6005 int i;
6006
6007 /* disable MST */
6008 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 6009 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 6010 if (!intel_dig_port)
6011 continue;
6012
6013 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6014 if (!intel_dig_port->dp.can_mst)
6015 continue;
6016 if (intel_dig_port->dp.is_mst)
6017 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6018 }
6019 }
6020}
6021
6022void intel_dp_mst_resume(struct drm_device *dev)
6023{
6024 struct drm_i915_private *dev_priv = dev->dev_private;
6025 int i;
6026
6027 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 6028 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 6029 if (!intel_dig_port)
6030 continue;
6031 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6032 int ret;
6033
6034 if (!intel_dig_port->dp.can_mst)
6035 continue;
6036
6037 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6038 if (ret != 0) {
6039 intel_dp_check_mst_status(&intel_dig_port->dp);
6040 }
6041 }
6042 }
6043}
ubuntu-bionic-kernel mirror