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drm/i915: correct BLC vs PWM enable/disable ordering
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
ef9348c8
CML		 67/*
68 * CHV supports eDP 1.4 that have more link rates.
69 * Below only provides the fixed rate but exclude variable rate.
70 */
71static const struct dp_link_dpll chv_dpll[] = {
72 /*
73 * CHV requires to program fractional division for m2.
74 * m2 is stored in fixed point format using formula below
75 * (m2_int << 22) | m2_fraction
76 */
77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
83};
84
cfcb0fc9
JB		 85/**
86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
87 * @intel_dp: DP struct
88 *
89 * If a CPU or PCH DP output is attached to an eDP panel, this function
90 * will return true, and false otherwise.
91 */
92static bool is_edp(struct intel_dp *intel_dp)
93{
da63a9f2
PZ		 94 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
95
96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 97}
98
68b4d824 99static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 100{
68b4d824
ID		 101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
102
103 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 104}
105
df0e9248
CW		 106static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
107{
fa90ecef 108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 109}
110
ea5b213a 111static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 112static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 113static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 114
a4fc5ed6 115static int
ea5b213a 116intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 117{
7183dc29 118 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 119 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 120
121 switch (max_link_bw) {
122 case DP_LINK_BW_1_62:
123 case DP_LINK_BW_2_7:
124 break;
d4eead50 125 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 126 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
127 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 128 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
129 max_link_bw = DP_LINK_BW_5_4;
130 else
131 max_link_bw = DP_LINK_BW_2_7;
d4eead50 132 break;
a4fc5ed6 133 default:
d4eead50
ID		 134 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
135 max_link_bw);
a4fc5ed6
KP		 136 max_link_bw = DP_LINK_BW_1_62;
137 break;
138 }
139 return max_link_bw;
140}
141
eeb6324d
PZ		 142static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
143{
144 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
145 struct drm_device *dev = intel_dig_port->base.base.dev;
146 u8 source_max, sink_max;
147
148 source_max = 4;
149 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
150 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
151 source_max = 2;
152
153 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
154
155 return min(source_max, sink_max);
156}
157
cd9dde44
AJ		 158/*
159 * The units on the numbers in the next two are... bizarre. Examples will
160 * make it clearer; this one parallels an example in the eDP spec.
161 *
162 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
163 *
164 * 270000 * 1 * 8 / 10 == 216000
165 *
166 * The actual data capacity of that configuration is 2.16Gbit/s, so the
167 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
168 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
169 * 119000. At 18bpp that's 2142000 kilobits per second.
170 *
171 * Thus the strange-looking division by 10 in intel_dp_link_required, to
172 * get the result in decakilobits instead of kilobits.
173 */
174
a4fc5ed6 175static int
c898261c 176intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 177{
cd9dde44 178 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 179}
180
fe27d53e
DA		 181static int
182intel_dp_max_data_rate(int max_link_clock, int max_lanes)
183{
184 return (max_link_clock * max_lanes * 8) / 10;
185}
186
c19de8eb 187static enum drm_mode_status
a4fc5ed6
KP		 188intel_dp_mode_valid(struct drm_connector *connector,
189 struct drm_display_mode *mode)
190{
df0e9248 191 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 192 struct intel_connector *intel_connector = to_intel_connector(connector);
193 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 194 int target_clock = mode->clock;
195 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 196
dd06f90e
JN		 197 if (is_edp(intel_dp) && fixed_mode) {
198 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 199 return MODE_PANEL;
200
dd06f90e 201 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 202 return MODE_PANEL;
03afc4a2
DV		 203
204 target_clock = fixed_mode->clock;
7de56f43
ZY		 205 }
206
36008365 207 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 208 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 209
210 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
211 mode_rate = intel_dp_link_required(target_clock, 18);
212
213 if (mode_rate > max_rate)
c4867936 214 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 215
216 if (mode->clock < 10000)
217 return MODE_CLOCK_LOW;
218
0af78a2b
DV		 219 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
220 return MODE_H_ILLEGAL;
221
a4fc5ed6
KP		 222 return MODE_OK;
223}
224
225static uint32_t
226pack_aux(uint8_t *src, int src_bytes)
227{
228 int i;
229 uint32_t v = 0;
230
231 if (src_bytes > 4)
232 src_bytes = 4;
233 for (i = 0; i < src_bytes; i++)
234 v |= ((uint32_t) src[i]) << ((3-i) * 8);
235 return v;
236}
237
238static void
239unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
240{
241 int i;
242 if (dst_bytes > 4)
243 dst_bytes = 4;
244 for (i = 0; i < dst_bytes; i++)
245 dst[i] = src >> ((3-i) * 8);
246}
247
fb0f8fbf
KP		 248/* hrawclock is 1/4 the FSB frequency */
249static int
250intel_hrawclk(struct drm_device *dev)
251{
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 uint32_t clkcfg;
254
9473c8f4
VP		 255 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
256 if (IS_VALLEYVIEW(dev))
257 return 200;
258
fb0f8fbf
KP		 259 clkcfg = I915_READ(CLKCFG);
260 switch (clkcfg & CLKCFG_FSB_MASK) {
261 case CLKCFG_FSB_400:
262 return 100;
263 case CLKCFG_FSB_533:
264 return 133;
265 case CLKCFG_FSB_667:
266 return 166;
267 case CLKCFG_FSB_800:
268 return 200;
269 case CLKCFG_FSB_1067:
270 return 266;
271 case CLKCFG_FSB_1333:
272 return 333;
273 /* these two are just a guess; one of them might be right */
274 case CLKCFG_FSB_1600:
275 case CLKCFG_FSB_1600_ALT:
276 return 400;
277 default:
278 return 133;
279 }
280}
281
bf13e81b
JN		 282static void
283intel_dp_init_panel_power_sequencer(struct drm_device *dev,
284 struct intel_dp *intel_dp,
285 struct edp_power_seq *out);
286static void
287intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
288 struct intel_dp *intel_dp,
289 struct edp_power_seq *out);
290
291static enum pipe
292vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
296 struct drm_device *dev = intel_dig_port->base.base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum port port = intel_dig_port->port;
299 enum pipe pipe;
300
301 /* modeset should have pipe */
302 if (crtc)
303 return to_intel_crtc(crtc)->pipe;
304
305 /* init time, try to find a pipe with this port selected */
306 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
307 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
308 PANEL_PORT_SELECT_MASK;
309 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
310 return pipe;
311 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
312 return pipe;
313 }
314
315 /* shrug */
316 return PIPE_A;
317}
318
319static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
322
323 if (HAS_PCH_SPLIT(dev))
324 return PCH_PP_CONTROL;
325 else
326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
327}
328
329static u32 _pp_stat_reg(struct intel_dp *intel_dp)
330{
331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
332
333 if (HAS_PCH_SPLIT(dev))
334 return PCH_PP_STATUS;
335 else
336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
337}
338
4be73780 339static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 340{
30add22d 341 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 342 struct drm_i915_private *dev_priv = dev->dev_private;
343
bf13e81b 344 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 345}
346
4be73780 347static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 348{
30add22d 349 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 350 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 351 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
352 struct intel_encoder *intel_encoder = &intel_dig_port->base;
353 enum intel_display_power_domain power_domain;
ebf33b18 354
bb4932c4
ID		 355 power_domain = intel_display_port_power_domain(intel_encoder);
356 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 357 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 358}
359
9b984dae
KP		 360static void
361intel_dp_check_edp(struct intel_dp *intel_dp)
362{
30add22d 363 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 364 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 365
9b984dae
KP		 366 if (!is_edp(intel_dp))
367 return;
453c5420 368
4be73780 369 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 370 WARN(1, "eDP powered off while attempting aux channel communication.\n");
371 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 372 I915_READ(_pp_stat_reg(intel_dp)),
373 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 374 }
375}
376
9ee32fea
DV		 377static uint32_t
378intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
379{
380 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
381 struct drm_device *dev = intel_dig_port->base.base.dev;
382 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 383 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 384 uint32_t status;
385 bool done;
386
ef04f00d 387#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 388 if (has_aux_irq)
b18ac466 389 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 390 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 391 else
392 done = wait_for_atomic(C, 10) == 0;
393 if (!done)
394 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
395 has_aux_irq);
396#undef C
397
398 return status;
399}
400
ec5b01dd 401static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 402{
174edf1f
PZ		 403 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
404 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 405
ec5b01dd
DL		 406 /*
407 * The clock divider is based off the hrawclk, and would like to run at
408 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 409 */
ec5b01dd
DL		 410 return index ? 0 : intel_hrawclk(dev) / 2;
411}
412
413static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
414{
415 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
416 struct drm_device *dev = intel_dig_port->base.base.dev;
417
418 if (index)
419 return 0;
420
421 if (intel_dig_port->port == PORT_A) {
422 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 423 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 424 else
b84a1cf8 425 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 426 } else {
427 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
428 }
429}
430
431static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
432{
433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
434 struct drm_device *dev = intel_dig_port->base.base.dev;
435 struct drm_i915_private *dev_priv = dev->dev_private;
436
437 if (intel_dig_port->port == PORT_A) {
438 if (index)
439 return 0;
440 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 441 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
442 /* Workaround for non-ULT HSW */
bc86625a
CW		 443 switch (index) {
444 case 0: return 63;
445 case 1: return 72;
446 default: return 0;
447 }
ec5b01dd 448 } else {
bc86625a 449 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 450 }
b84a1cf8
RV		 451}
452
ec5b01dd
DL		 453static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
454{
455 return index ? 0 : 100;
456}
457
5ed12a19
DL		 458static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
459 bool has_aux_irq,
460 int send_bytes,
461 uint32_t aux_clock_divider)
462{
463 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
464 struct drm_device *dev = intel_dig_port->base.base.dev;
465 uint32_t precharge, timeout;
466
467 if (IS_GEN6(dev))
468 precharge = 3;
469 else
470 precharge = 5;
471
472 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
473 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
474 else
475 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
476
477 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 478 DP_AUX_CH_CTL_DONE |
5ed12a19 479 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 480 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 481 timeout |
788d4433 482 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 483 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
484 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 485 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 486}
487
b84a1cf8
RV		 488static int
489intel_dp_aux_ch(struct intel_dp *intel_dp,
490 uint8_t *send, int send_bytes,
491 uint8_t *recv, int recv_size)
492{
493 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
494 struct drm_device *dev = intel_dig_port->base.base.dev;
495 struct drm_i915_private *dev_priv = dev->dev_private;
496 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
497 uint32_t ch_data = ch_ctl + 4;
bc86625a 498 uint32_t aux_clock_divider;
b84a1cf8
RV		 499 int i, ret, recv_bytes;
500 uint32_t status;
5ed12a19 501 int try, clock = 0;
4e6b788c 502 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 503 bool vdd;
504
505 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 506
507 /* dp aux is extremely sensitive to irq latency, hence request the
508 * lowest possible wakeup latency and so prevent the cpu from going into
509 * deep sleep states.
510 */
511 pm_qos_update_request(&dev_priv->pm_qos, 0);
512
513 intel_dp_check_edp(intel_dp);
5eb08b69 514
c67a470b
PZ		 515 intel_aux_display_runtime_get(dev_priv);
516
11bee43e
JB		 517 /* Try to wait for any previous AUX channel activity */
518 for (try = 0; try < 3; try++) {
ef04f00d 519 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 520 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
521 break;
522 msleep(1);
523 }
524
525 if (try == 3) {
526 WARN(1, "dp_aux_ch not started status 0x%08x\n",
527 I915_READ(ch_ctl));
9ee32fea
DV		 528 ret = -EBUSY;
529 goto out;
4f7f7b7e
CW		 530 }
531
46a5ae9f
PZ		 532 /* Only 5 data registers! */
533 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
534 ret = -E2BIG;
535 goto out;
536 }
537
ec5b01dd 538 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 539 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
540 has_aux_irq,
541 send_bytes,
542 aux_clock_divider);
5ed12a19 543
bc86625a
CW		 544 /* Must try at least 3 times according to DP spec */
545 for (try = 0; try < 5; try++) {
546 /* Load the send data into the aux channel data registers */
547 for (i = 0; i < send_bytes; i += 4)
548 I915_WRITE(ch_data + i,
549 pack_aux(send + i, send_bytes - i));
550
551 /* Send the command and wait for it to complete */
5ed12a19 552 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 553
554 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
555
556 /* Clear done status and any errors */
557 I915_WRITE(ch_ctl,
558 status |
559 DP_AUX_CH_CTL_DONE |
560 DP_AUX_CH_CTL_TIME_OUT_ERROR |
561 DP_AUX_CH_CTL_RECEIVE_ERROR);
562
563 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
564 DP_AUX_CH_CTL_RECEIVE_ERROR))
565 continue;
566 if (status & DP_AUX_CH_CTL_DONE)
567 break;
568 }
4f7f7b7e 569 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 570 break;
571 }
572
a4fc5ed6 573 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 574 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 575 ret = -EBUSY;
576 goto out;
a4fc5ed6
KP		 577 }
578
579 /* Check for timeout or receive error.
580 * Timeouts occur when the sink is not connected
581 */
a5b3da54 582 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 583 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 584 ret = -EIO;
585 goto out;
a5b3da54 586 }
1ae8c0a5
KP		 587
588 /* Timeouts occur when the device isn't connected, so they're
589 * "normal" -- don't fill the kernel log with these */
a5b3da54 590 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 591 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 592 ret = -ETIMEDOUT;
593 goto out;
a4fc5ed6
KP		 594 }
595
596 /* Unload any bytes sent back from the other side */
597 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
598 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 599 if (recv_bytes > recv_size)
600 recv_bytes = recv_size;
0206e353 601
4f7f7b7e
CW		 602 for (i = 0; i < recv_bytes; i += 4)
603 unpack_aux(I915_READ(ch_data + i),
604 recv + i, recv_bytes - i);
a4fc5ed6 605
9ee32fea
DV		 606 ret = recv_bytes;
607out:
608 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 609 intel_aux_display_runtime_put(dev_priv);
9ee32fea 610
884f19e9
JN		 611 if (vdd)
612 edp_panel_vdd_off(intel_dp, false);
613
9ee32fea 614 return ret;
a4fc5ed6
KP		 615}
616
a6c8aff0
JN		 617#define BARE_ADDRESS_SIZE 3
618#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 619static ssize_t
620intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 621{
9d1a1031
JN		 622 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
623 uint8_t txbuf[20], rxbuf[20];
624 size_t txsize, rxsize;
a4fc5ed6 625 int ret;
a4fc5ed6 626
9d1a1031
JN		 627 txbuf[0] = msg->request << 4;
628 txbuf[1] = msg->address >> 8;
629 txbuf[2] = msg->address & 0xff;
630 txbuf[3] = msg->size - 1;
46a5ae9f 631
9d1a1031
JN		 632 switch (msg->request & ~DP_AUX_I2C_MOT) {
633 case DP_AUX_NATIVE_WRITE:
634 case DP_AUX_I2C_WRITE:
a6c8aff0 635 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 636 rxsize = 1;
f51a44b9 637
9d1a1031
JN		 638 if (WARN_ON(txsize > 20))
639 return -E2BIG;
a4fc5ed6 640
9d1a1031 641 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 642
9d1a1031
JN		 643 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
644 if (ret > 0) {
645 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 646
9d1a1031
JN		 647 /* Return payload size. */
648 ret = msg->size;
649 }
650 break;
46a5ae9f 651
9d1a1031
JN		 652 case DP_AUX_NATIVE_READ:
653 case DP_AUX_I2C_READ:
a6c8aff0 654 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 655 rxsize = msg->size + 1;
a4fc5ed6 656
9d1a1031
JN		 657 if (WARN_ON(rxsize > 20))
658 return -E2BIG;
a4fc5ed6 659
9d1a1031
JN		 660 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
661 if (ret > 0) {
662 msg->reply = rxbuf[0] >> 4;
663 /*
664 * Assume happy day, and copy the data. The caller is
665 * expected to check msg->reply before touching it.
666 *
667 * Return payload size.
668 */
669 ret--;
670 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 671 }
9d1a1031
JN		 672 break;
673
674 default:
675 ret = -EINVAL;
676 break;
a4fc5ed6 677 }
f51a44b9 678
9d1a1031 679 return ret;
a4fc5ed6
KP		 680}
681
9d1a1031
JN		 682static void
683intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
684{
685 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 686 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
687 enum port port = intel_dig_port->port;
0b99836f 688 const char *name = NULL;
ab2c0672
DA		 689 int ret;
690
33ad6626
JN		 691 switch (port) {
692 case PORT_A:
693 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 694 name = "DPDDC-A";
ab2c0672 695 break;
33ad6626
JN		 696 case PORT_B:
697 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 698 name = "DPDDC-B";
ab2c0672 699 break;
33ad6626
JN		 700 case PORT_C:
701 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 702 name = "DPDDC-C";
ab2c0672 703 break;
33ad6626
JN		 704 case PORT_D:
705 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 706 name = "DPDDC-D";
33ad6626
JN		 707 break;
708 default:
709 BUG();
ab2c0672
DA		 710 }
711
33ad6626
JN		 712 if (!HAS_DDI(dev))
713 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 714
0b99836f 715 intel_dp->aux.name = name;
9d1a1031
JN		 716 intel_dp->aux.dev = dev->dev;
717 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 718
0b99836f
JN		 719 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
720 connector->base.kdev->kobj.name);
8316f337 721
4f71d0cb 722 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 723 if (ret < 0) {
4f71d0cb 724 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 725 name, ret);
726 return;
ab2c0672 727 }
8a5e6aeb 728
0b99836f
JN		 729 ret = sysfs_create_link(&connector->base.kdev->kobj,
730 &intel_dp->aux.ddc.dev.kobj,
731 intel_dp->aux.ddc.dev.kobj.name);
732 if (ret < 0) {
733 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 734 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 735 }
a4fc5ed6
KP		 736}
737
80f65de3
ID		 738static void
739intel_dp_connector_unregister(struct intel_connector *intel_connector)
740{
741 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
742
743 sysfs_remove_link(&intel_connector->base.kdev->kobj,
0b99836f 744 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 745 intel_connector_unregister(intel_connector);
746}
747
c6bb3538
DV		 748static void
749intel_dp_set_clock(struct intel_encoder *encoder,
750 struct intel_crtc_config *pipe_config, int link_bw)
751{
752 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 753 const struct dp_link_dpll *divisor = NULL;
754 int i, count = 0;
c6bb3538
DV		 755
756 if (IS_G4X(dev)) {
9dd4ffdf
CML		 757 divisor = gen4_dpll;
758 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 759 } else if (IS_HASWELL(dev)) {
760 /* Haswell has special-purpose DP DDI clocks. */
761 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 762 divisor = pch_dpll;
763 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 764 } else if (IS_CHERRYVIEW(dev)) {
765 divisor = chv_dpll;
766 count = ARRAY_SIZE(chv_dpll);
c6bb3538 767 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 768 divisor = vlv_dpll;
769 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 770 }
9dd4ffdf
CML		 771
772 if (divisor && count) {
773 for (i = 0; i < count; i++) {
774 if (link_bw == divisor[i].link_bw) {
775 pipe_config->dpll = divisor[i].dpll;
776 pipe_config->clock_set = true;
777 break;
778 }
779 }
c6bb3538
DV		 780 }
781}
782
439d7ac0
PB		 783static void
784intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
785{
786 struct drm_device *dev = crtc->base.dev;
787 struct drm_i915_private *dev_priv = dev->dev_private;
788 enum transcoder transcoder = crtc->config.cpu_transcoder;
789
790 I915_WRITE(PIPE_DATA_M2(transcoder),
791 TU_SIZE(m_n->tu) | m_n->gmch_m);
792 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
793 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
794 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
795}
796
00c09d70 797bool
5bfe2ac0
DV		 798intel_dp_compute_config(struct intel_encoder *encoder,
799 struct intel_crtc_config *pipe_config)
a4fc5ed6 800{
5bfe2ac0 801 struct drm_device *dev = encoder->base.dev;
36008365 802 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 803 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 804 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 805 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 806 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 807 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 808 int lane_count, clock;
56071a20 809 int min_lane_count = 1;
eeb6324d 810 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 811 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 812 int min_clock = 0;
06ea66b6 813 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 814 int bpp, mode_rate;
06ea66b6 815 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 816 int link_avail, link_clock;
a4fc5ed6 817
bc7d38a4 818 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 819 pipe_config->has_pch_encoder = true;
820
03afc4a2 821 pipe_config->has_dp_encoder = true;
9ed109a7 822 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 823
dd06f90e
JN		 824 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
825 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
826 adjusted_mode);
2dd24552
JB		 827 if (!HAS_PCH_SPLIT(dev))
828 intel_gmch_panel_fitting(intel_crtc, pipe_config,
829 intel_connector->panel.fitting_mode);
830 else
b074cec8
JB		 831 intel_pch_panel_fitting(intel_crtc, pipe_config,
832 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 833 }
834
cb1793ce 835 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 836 return false;
837
083f9560
DV		 838 DRM_DEBUG_KMS("DP link computation with max lane count %i "
839 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 840 max_lane_count, bws[max_clock],
841 adjusted_mode->crtc_clock);
083f9560 842
36008365
DV		 843 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
844 * bpc in between. */
3e7ca985 845 bpp = pipe_config->pipe_bpp;
56071a20
JN		 846 if (is_edp(intel_dp)) {
847 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
848 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
849 dev_priv->vbt.edp_bpp);
850 bpp = dev_priv->vbt.edp_bpp;
851 }
852
f4cdbc21
JN		 853 if (IS_BROADWELL(dev)) {
854 /* Yes, it's an ugly hack. */
855 min_lane_count = max_lane_count;
856 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
857 min_lane_count);
858 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 859 min_lane_count = min(dev_priv->vbt.edp_lanes,
860 max_lane_count);
861 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
862 min_lane_count);
863 }
864
865 if (dev_priv->vbt.edp_rate) {
866 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
867 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
868 bws[min_clock]);
869 }
7984211e 870 }
657445fe 871
36008365 872 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 873 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
874 bpp);
36008365 875
56071a20
JN		 876 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
877 for (clock = min_clock; clock <= max_clock; clock++) {
36008365
DV		 878 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
879 link_avail = intel_dp_max_data_rate(link_clock,
880 lane_count);
881
882 if (mode_rate <= link_avail) {
883 goto found;
884 }
885 }
886 }
887 }
c4867936 888
36008365 889 return false;
3685a8f3 890
36008365 891found:
55bc60db
VS		 892 if (intel_dp->color_range_auto) {
893 /*
894 * See:
895 * CEA-861-E - 5.1 Default Encoding Parameters
896 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
897 */
18316c8c 898 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 899 intel_dp->color_range = DP_COLOR_RANGE_16_235;
900 else
901 intel_dp->color_range = 0;
902 }
903
3685a8f3 904 if (intel_dp->color_range)
50f3b016 905 pipe_config->limited_color_range = true;
a4fc5ed6 906
36008365
DV		 907 intel_dp->link_bw = bws[clock];
908 intel_dp->lane_count = lane_count;
657445fe 909 pipe_config->pipe_bpp = bpp;
ff9a6750 910 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 911
36008365
DV		 912 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
913 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 914 pipe_config->port_clock, bpp);
36008365
DV		 915 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
916 mode_rate, link_avail);
a4fc5ed6 917
03afc4a2 918 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 919 adjusted_mode->crtc_clock,
920 pipe_config->port_clock,
03afc4a2 921 &pipe_config->dp_m_n);
9d1a455b 922
439d7ac0
PB		 923 if (intel_connector->panel.downclock_mode != NULL &&
924 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
925 intel_link_compute_m_n(bpp, lane_count,
926 intel_connector->panel.downclock_mode->clock,
927 pipe_config->port_clock,
928 &pipe_config->dp_m2_n2);
929 }
930
c6bb3538
DV		 931 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
932
03afc4a2 933 return true;
a4fc5ed6
KP		 934}
935
7c62a164 936static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 937{
7c62a164
DV		 938 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
939 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
940 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 941 struct drm_i915_private *dev_priv = dev->dev_private;
942 u32 dpa_ctl;
943
ff9a6750 944 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 945 dpa_ctl = I915_READ(DP_A);
946 dpa_ctl &= ~DP_PLL_FREQ_MASK;
947
ff9a6750 948 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 949 /* For a long time we've carried around a ILK-DevA w/a for the
950 * 160MHz clock. If we're really unlucky, it's still required.
951 */
952 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 953 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 954 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 955 } else {
956 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 957 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 958 }
1ce17038 959
ea9b6006
DV		 960 I915_WRITE(DP_A, dpa_ctl);
961
962 POSTING_READ(DP_A);
963 udelay(500);
964}
965
8ac33ed3 966static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 967{
b934223d 968 struct drm_device *dev = encoder->base.dev;
417e822d 969 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 970 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 971 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 972 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
973 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 974
417e822d 975 /*
1a2eb460 976 * There are four kinds of DP registers:
417e822d
KP		 977 *
978 * IBX PCH
1a2eb460
KP		 979 * SNB CPU
980 * IVB CPU
417e822d
KP		 981 * CPT PCH
982 *
983 * IBX PCH and CPU are the same for almost everything,
984 * except that the CPU DP PLL is configured in this
985 * register
986 *
987 * CPT PCH is quite different, having many bits moved
988 * to the TRANS_DP_CTL register instead. That
989 * configuration happens (oddly) in ironlake_pch_enable
990 */
9c9e7927 991
417e822d
KP		 992 /* Preserve the BIOS-computed detected bit. This is
993 * supposed to be read-only.
994 */
995 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 996
417e822d 997 /* Handle DP bits in common between all three register formats */
417e822d 998 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 999 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1000
9ed109a7 1001 if (crtc->config.has_audio) {
e0dac65e 1002 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1003 pipe_name(crtc->pipe));
ea5b213a 1004 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1005 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1006 }
247d89f6 1007
417e822d 1008 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1009
bc7d38a4 1010 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1011 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1012 intel_dp->DP |= DP_SYNC_HS_HIGH;
1013 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1014 intel_dp->DP |= DP_SYNC_VS_HIGH;
1015 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1016
6aba5b6c 1017 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1018 intel_dp->DP |= DP_ENHANCED_FRAMING;
1019
7c62a164 1020 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1021 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1022 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1023 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1024
1025 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1026 intel_dp->DP |= DP_SYNC_HS_HIGH;
1027 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1028 intel_dp->DP |= DP_SYNC_VS_HIGH;
1029 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1030
6aba5b6c 1031 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1032 intel_dp->DP |= DP_ENHANCED_FRAMING;
1033
44f37d1f
CML		 1034 if (!IS_CHERRYVIEW(dev)) {
1035 if (crtc->pipe == 1)
1036 intel_dp->DP |= DP_PIPEB_SELECT;
1037 } else {
1038 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1039 }
417e822d
KP		 1040 } else {
1041 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1042 }
a4fc5ed6
KP		 1043}
1044
ffd6749d
PZ		 1045#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1046#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1047
1a5ef5b7
PZ		 1048#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1049#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1050
ffd6749d
PZ		 1051#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1052#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1053
4be73780 1054static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1055 u32 mask,
1056 u32 value)
bd943159 1057{
30add22d 1058 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1059 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1060 u32 pp_stat_reg, pp_ctrl_reg;
1061
bf13e81b
JN		 1062 pp_stat_reg = _pp_stat_reg(intel_dp);
1063 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1064
99ea7127 1065 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1066 mask, value,
1067 I915_READ(pp_stat_reg),
1068 I915_READ(pp_ctrl_reg));
32ce697c 1069
453c5420 1070 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1071 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1072 I915_READ(pp_stat_reg),
1073 I915_READ(pp_ctrl_reg));
32ce697c 1074 }
54c136d4
CW		 1075
1076 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1077}
32ce697c 1078
4be73780 1079static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1080{
1081 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1082 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1083}
1084
4be73780 1085static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1086{
1087 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1088 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1089}
1090
4be73780 1091static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1092{
1093 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1094
1095 /* When we disable the VDD override bit last we have to do the manual
1096 * wait. */
1097 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1098 intel_dp->panel_power_cycle_delay);
1099
4be73780 1100 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1101}
1102
4be73780 1103static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1104{
1105 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1106 intel_dp->backlight_on_delay);
1107}
1108
4be73780 1109static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1110{
1111 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1112 intel_dp->backlight_off_delay);
1113}
99ea7127 1114
832dd3c1
KP		 1115/* Read the current pp_control value, unlocking the register if it
1116 * is locked
1117 */
1118
453c5420 1119static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1120{
453c5420
JB		 1121 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1122 struct drm_i915_private *dev_priv = dev->dev_private;
1123 u32 control;
832dd3c1 1124
bf13e81b 1125 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1126 control &= ~PANEL_UNLOCK_MASK;
1127 control |= PANEL_UNLOCK_REGS;
1128 return control;
bd943159
KP		 1129}
1130
adddaaf4 1131static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1132{
30add22d 1133 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1134 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1135 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1136 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1137 enum intel_display_power_domain power_domain;
5d613501 1138 u32 pp;
453c5420 1139 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1140 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1141
97af61f5 1142 if (!is_edp(intel_dp))
adddaaf4 1143 return false;
bd943159
KP		 1144
1145 intel_dp->want_panel_vdd = true;
99ea7127 1146
4be73780 1147 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1148 return need_to_disable;
b0665d57 1149
4e6e1a54
ID		 1150 power_domain = intel_display_port_power_domain(intel_encoder);
1151 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1152
b0665d57 1153 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1154
4be73780
DV		 1155 if (!edp_have_panel_power(intel_dp))
1156 wait_panel_power_cycle(intel_dp);
99ea7127 1157
453c5420 1158 pp = ironlake_get_pp_control(intel_dp);
5d613501 1159 pp |= EDP_FORCE_VDD;
ebf33b18 1160
bf13e81b
JN		 1161 pp_stat_reg = _pp_stat_reg(intel_dp);
1162 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1163
1164 I915_WRITE(pp_ctrl_reg, pp);
1165 POSTING_READ(pp_ctrl_reg);
1166 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1167 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1168 /*
1169 * If the panel wasn't on, delay before accessing aux channel
1170 */
4be73780 1171 if (!edp_have_panel_power(intel_dp)) {
bd943159 1172 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1173 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1174 }
adddaaf4
JN		 1175
1176 return need_to_disable;
1177}
1178
b80d6c78 1179void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1180{
1181 if (is_edp(intel_dp)) {
1182 bool vdd = _edp_panel_vdd_on(intel_dp);
1183
1184 WARN(!vdd, "eDP VDD already requested on\n");
1185 }
5d613501
JB		 1186}
1187
4be73780 1188static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1189{
30add22d 1190 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1191 struct drm_i915_private *dev_priv = dev->dev_private;
1192 u32 pp;
453c5420 1193 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1194
51fd371b 1195 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
a0e99e68 1196
4be73780 1197 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1198 struct intel_digital_port *intel_dig_port =
1199 dp_to_dig_port(intel_dp);
1200 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1201 enum intel_display_power_domain power_domain;
1202
b0665d57
PZ		 1203 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1204
453c5420 1205 pp = ironlake_get_pp_control(intel_dp);
bd943159 1206 pp &= ~EDP_FORCE_VDD;
bd943159 1207
9f08ef59
PZ		 1208 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1209 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1210
1211 I915_WRITE(pp_ctrl_reg, pp);
1212 POSTING_READ(pp_ctrl_reg);
99ea7127 1213
453c5420
JB		 1214 /* Make sure sequencer is idle before allowing subsequent activity */
1215 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1216 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1217
1218 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1219 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1220
4e6e1a54
ID		 1221 power_domain = intel_display_port_power_domain(intel_encoder);
1222 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1223 }
1224}
5d613501 1225
4be73780 1226static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1227{
1228 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1229 struct intel_dp, panel_vdd_work);
30add22d 1230 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1231
51fd371b 1232 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 1233 edp_panel_vdd_off_sync(intel_dp);
51fd371b 1234 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159
KP		 1235}
1236
4be73780 1237static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1238{
97af61f5
KP		 1239 if (!is_edp(intel_dp))
1240 return;
5d613501 1241
bd943159 1242 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1243
bd943159
KP		 1244 intel_dp->want_panel_vdd = false;
1245
1246 if (sync) {
4be73780 1247 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1248 } else {
1249 /*
1250 * Queue the timer to fire a long
1251 * time from now (relative to the power down delay)
1252 * to keep the panel power up across a sequence of operations
1253 */
1254 schedule_delayed_work(&intel_dp->panel_vdd_work,
1255 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1256 }
5d613501
JB		 1257}
1258
4be73780 1259void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1260{
30add22d 1261 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1262 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1263 u32 pp;
453c5420 1264 u32 pp_ctrl_reg;
9934c132 1265
97af61f5 1266 if (!is_edp(intel_dp))
bd943159 1267 return;
99ea7127
KP		 1268
1269 DRM_DEBUG_KMS("Turn eDP power on\n");
1270
4be73780 1271 if (edp_have_panel_power(intel_dp)) {
99ea7127 1272 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1273 return;
99ea7127 1274 }
9934c132 1275
4be73780 1276 wait_panel_power_cycle(intel_dp);
37c6c9b0 1277
bf13e81b 1278 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1279 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1280 if (IS_GEN5(dev)) {
1281 /* ILK workaround: disable reset around power sequence */
1282 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1283 I915_WRITE(pp_ctrl_reg, pp);
1284 POSTING_READ(pp_ctrl_reg);
05ce1a49 1285 }
37c6c9b0 1286
1c0ae80a 1287 pp |= POWER_TARGET_ON;
99ea7127
KP		 1288 if (!IS_GEN5(dev))
1289 pp |= PANEL_POWER_RESET;
1290
453c5420
JB		 1291 I915_WRITE(pp_ctrl_reg, pp);
1292 POSTING_READ(pp_ctrl_reg);
9934c132 1293
4be73780 1294 wait_panel_on(intel_dp);
dce56b3c 1295 intel_dp->last_power_on = jiffies;
9934c132 1296
05ce1a49
KP		 1297 if (IS_GEN5(dev)) {
1298 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1299 I915_WRITE(pp_ctrl_reg, pp);
1300 POSTING_READ(pp_ctrl_reg);
05ce1a49 1301 }
9934c132
JB		 1302}
1303
4be73780 1304void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1305{
4e6e1a54
ID		 1306 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1307 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1308 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1309 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1310 enum intel_display_power_domain power_domain;
99ea7127 1311 u32 pp;
453c5420 1312 u32 pp_ctrl_reg;
9934c132 1313
97af61f5
KP		 1314 if (!is_edp(intel_dp))
1315 return;
37c6c9b0 1316
99ea7127 1317 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1318
24f3e092
JN		 1319 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1320
453c5420 1321 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1322 /* We need to switch off panel power _and_ force vdd, for otherwise some
1323 * panels get very unhappy and cease to work. */
b3064154
PJ		 1324 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1325 EDP_BLC_ENABLE);
453c5420 1326
bf13e81b 1327 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1328
849e39f5
PZ		 1329 intel_dp->want_panel_vdd = false;
1330
453c5420
JB		 1331 I915_WRITE(pp_ctrl_reg, pp);
1332 POSTING_READ(pp_ctrl_reg);
9934c132 1333
dce56b3c 1334 intel_dp->last_power_cycle = jiffies;
4be73780 1335 wait_panel_off(intel_dp);
849e39f5
PZ		 1336
1337 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1338 power_domain = intel_display_port_power_domain(intel_encoder);
1339 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1340}
1341
4be73780 1342void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1343{
da63a9f2
PZ		 1344 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1345 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1346 struct drm_i915_private *dev_priv = dev->dev_private;
1347 u32 pp;
453c5420 1348 u32 pp_ctrl_reg;
32f9d658 1349
f01eca2e
KP		 1350 if (!is_edp(intel_dp))
1351 return;
1352
28c97730 1353 DRM_DEBUG_KMS("\n");
f7d2323c
JB		 1354
1355 intel_panel_enable_backlight(intel_dp->attached_connector);
1356
01cb9ea6
JB		 1357 /*
1358 * If we enable the backlight right away following a panel power
1359 * on, we may see slight flicker as the panel syncs with the eDP
1360 * link. So delay a bit to make sure the image is solid before
1361 * allowing it to appear.
1362 */
4be73780 1363 wait_backlight_on(intel_dp);
453c5420 1364 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1365 pp |= EDP_BLC_ENABLE;
453c5420 1366
bf13e81b 1367 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1368
1369 I915_WRITE(pp_ctrl_reg, pp);
1370 POSTING_READ(pp_ctrl_reg);
32f9d658
ZW		 1371}
1372
4be73780 1373void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1374{
30add22d 1375 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1376 struct drm_i915_private *dev_priv = dev->dev_private;
1377 u32 pp;
453c5420 1378 u32 pp_ctrl_reg;
32f9d658 1379
f01eca2e
KP		 1380 if (!is_edp(intel_dp))
1381 return;
1382
28c97730 1383 DRM_DEBUG_KMS("\n");
453c5420 1384 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1385 pp &= ~EDP_BLC_ENABLE;
453c5420 1386
bf13e81b 1387 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1388
1389 I915_WRITE(pp_ctrl_reg, pp);
1390 POSTING_READ(pp_ctrl_reg);
dce56b3c 1391 intel_dp->last_backlight_off = jiffies;
f7d2323c
JB		 1392
1393 edp_wait_backlight_off(intel_dp);
1394
1395 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1396}
a4fc5ed6 1397
2bd2ad64 1398static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1399{
da63a9f2
PZ		 1400 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1401 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1402 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1403 struct drm_i915_private *dev_priv = dev->dev_private;
1404 u32 dpa_ctl;
1405
2bd2ad64
DV		 1406 assert_pipe_disabled(dev_priv,
1407 to_intel_crtc(crtc)->pipe);
1408
d240f20f
JB		 1409 DRM_DEBUG_KMS("\n");
1410 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1411 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1412 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1413
1414 /* We don't adjust intel_dp->DP while tearing down the link, to
1415 * facilitate link retraining (e.g. after hotplug). Hence clear all
1416 * enable bits here to ensure that we don't enable too much. */
1417 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1418 intel_dp->DP |= DP_PLL_ENABLE;
1419 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1420 POSTING_READ(DP_A);
1421 udelay(200);
d240f20f
JB		 1422}
1423
2bd2ad64 1424static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1425{
da63a9f2
PZ		 1426 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1427 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1428 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1429 struct drm_i915_private *dev_priv = dev->dev_private;
1430 u32 dpa_ctl;
1431
2bd2ad64
DV		 1432 assert_pipe_disabled(dev_priv,
1433 to_intel_crtc(crtc)->pipe);
1434
d240f20f 1435 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1436 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1437 "dp pll off, should be on\n");
1438 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1439
1440 /* We can't rely on the value tracked for the DP register in
1441 * intel_dp->DP because link_down must not change that (otherwise link
1442 * re-training will fail. */
298b0b39 1443 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1444 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1445 POSTING_READ(DP_A);
d240f20f
JB		 1446 udelay(200);
1447}
1448
c7ad3810 1449/* If the sink supports it, try to set the power state appropriately */
c19b0669 1450void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1451{
1452 int ret, i;
1453
1454 /* Should have a valid DPCD by this point */
1455 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1456 return;
1457
1458 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1459 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1460 DP_SET_POWER_D3);
c7ad3810
JB		 1461 if (ret != 1)
1462 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1463 } else {
1464 /*
1465 * When turning on, we need to retry for 1ms to give the sink
1466 * time to wake up.
1467 */
1468 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1469 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1470 DP_SET_POWER_D0);
c7ad3810
JB		 1471 if (ret == 1)
1472 break;
1473 msleep(1);
1474 }
1475 }
1476}
1477
19d8fe15
DV		 1478static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1479 enum pipe *pipe)
d240f20f 1480{
19d8fe15 1481 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1482 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1483 struct drm_device *dev = encoder->base.dev;
1484 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1485 enum intel_display_power_domain power_domain;
1486 u32 tmp;
1487
1488 power_domain = intel_display_port_power_domain(encoder);
1489 if (!intel_display_power_enabled(dev_priv, power_domain))
1490 return false;
1491
1492 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1493
1494 if (!(tmp & DP_PORT_EN))
1495 return false;
1496
bc7d38a4 1497 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1498 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1499 } else if (IS_CHERRYVIEW(dev)) {
1500 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1501 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1502 *pipe = PORT_TO_PIPE(tmp);
1503 } else {
1504 u32 trans_sel;
1505 u32 trans_dp;
1506 int i;
1507
1508 switch (intel_dp->output_reg) {
1509 case PCH_DP_B:
1510 trans_sel = TRANS_DP_PORT_SEL_B;
1511 break;
1512 case PCH_DP_C:
1513 trans_sel = TRANS_DP_PORT_SEL_C;
1514 break;
1515 case PCH_DP_D:
1516 trans_sel = TRANS_DP_PORT_SEL_D;
1517 break;
1518 default:
1519 return true;
1520 }
1521
1522 for_each_pipe(i) {
1523 trans_dp = I915_READ(TRANS_DP_CTL(i));
1524 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1525 *pipe = i;
1526 return true;
1527 }
1528 }
19d8fe15 1529
4a0833ec
DV		 1530 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1531 intel_dp->output_reg);
1532 }
d240f20f 1533
19d8fe15
DV		 1534 return true;
1535}
d240f20f 1536
045ac3b5
JB		 1537static void intel_dp_get_config(struct intel_encoder *encoder,
1538 struct intel_crtc_config *pipe_config)
1539{
1540 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1541 u32 tmp, flags = 0;
63000ef6
XZ		 1542 struct drm_device *dev = encoder->base.dev;
1543 struct drm_i915_private *dev_priv = dev->dev_private;
1544 enum port port = dp_to_dig_port(intel_dp)->port;
1545 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1546 int dotclock;
045ac3b5 1547
9ed109a7
DV		 1548 tmp = I915_READ(intel_dp->output_reg);
1549 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1550 pipe_config->has_audio = true;
1551
63000ef6 1552 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1553 if (tmp & DP_SYNC_HS_HIGH)
1554 flags |= DRM_MODE_FLAG_PHSYNC;
1555 else
1556 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1557
63000ef6
XZ		 1558 if (tmp & DP_SYNC_VS_HIGH)
1559 flags |= DRM_MODE_FLAG_PVSYNC;
1560 else
1561 flags |= DRM_MODE_FLAG_NVSYNC;
1562 } else {
1563 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1564 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1565 flags |= DRM_MODE_FLAG_PHSYNC;
1566 else
1567 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1568
63000ef6
XZ		 1569 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1570 flags |= DRM_MODE_FLAG_PVSYNC;
1571 else
1572 flags |= DRM_MODE_FLAG_NVSYNC;
1573 }
045ac3b5
JB		 1574
1575 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1576
eb14cb74
VS		 1577 pipe_config->has_dp_encoder = true;
1578
1579 intel_dp_get_m_n(crtc, pipe_config);
1580
18442d08 1581 if (port == PORT_A) {
f1f644dc
JB		 1582 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1583 pipe_config->port_clock = 162000;
1584 else
1585 pipe_config->port_clock = 270000;
1586 }
18442d08
VS		 1587
1588 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1589 &pipe_config->dp_m_n);
1590
1591 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1592 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1593
241bfc38 1594 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1595
c6cd2ee2
JN		 1596 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1597 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1598 /*
1599 * This is a big fat ugly hack.
1600 *
1601 * Some machines in UEFI boot mode provide us a VBT that has 18
1602 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1603 * unknown we fail to light up. Yet the same BIOS boots up with
1604 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1605 * max, not what it tells us to use.
1606 *
1607 * Note: This will still be broken if the eDP panel is not lit
1608 * up by the BIOS, and thus we can't get the mode at module
1609 * load.
1610 */
1611 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1612 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1613 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1614 }
045ac3b5
JB		 1615}
1616
34eb7579 1617static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1618{
34eb7579 1619 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1620}
1621
2b28bb1b
RV		 1622static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1623{
1624 struct drm_i915_private *dev_priv = dev->dev_private;
1625
18b5992c 1626 if (!HAS_PSR(dev))
2b28bb1b
RV		 1627 return false;
1628
18b5992c 1629 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1630}
1631
1632static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1633 struct edp_vsc_psr *vsc_psr)
1634{
1635 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1636 struct drm_device *dev = dig_port->base.base.dev;
1637 struct drm_i915_private *dev_priv = dev->dev_private;
1638 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1639 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1640 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1641 uint32_t *data = (uint32_t *) vsc_psr;
1642 unsigned int i;
1643
1644 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1645 the video DIP being updated before program video DIP data buffer
1646 registers for DIP being updated. */
1647 I915_WRITE(ctl_reg, 0);
1648 POSTING_READ(ctl_reg);
1649
1650 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1651 if (i < sizeof(struct edp_vsc_psr))
1652 I915_WRITE(data_reg + i, *data++);
1653 else
1654 I915_WRITE(data_reg + i, 0);
1655 }
1656
1657 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1658 POSTING_READ(ctl_reg);
1659}
1660
1661static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1662{
1663 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1664 struct drm_i915_private *dev_priv = dev->dev_private;
1665 struct edp_vsc_psr psr_vsc;
1666
6118efe5 1667 if (dev_priv->psr.setup_done)
2b28bb1b
RV		 1668 return;
1669
1670 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1671 memset(&psr_vsc, 0, sizeof(psr_vsc));
1672 psr_vsc.sdp_header.HB0 = 0;
1673 psr_vsc.sdp_header.HB1 = 0x7;
1674 psr_vsc.sdp_header.HB2 = 0x2;
1675 psr_vsc.sdp_header.HB3 = 0x8;
1676 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1677
1678 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1679 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1680 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b 1681
6118efe5 1682 dev_priv->psr.setup_done = true;
2b28bb1b
RV		 1683}
1684
1685static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1686{
0e0ae652
RV		 1687 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1688 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 1689 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1690 uint32_t aux_clock_divider;
2b28bb1b
RV		 1691 int precharge = 0x3;
1692 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 1693 bool only_standby = false;
2b28bb1b 1694
ec5b01dd
DL		 1695 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1696
0e0ae652
RV		 1697 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1698 only_standby = true;
1699
2b28bb1b 1700 /* Enable PSR in sink */
0e0ae652 1701 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 1702 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1703 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1704 else
9d1a1031
JN		 1705 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1706 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1707
1708 /* Setup AUX registers */
18b5992c
BW		 1709 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1710 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1711 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1712 DP_AUX_CH_CTL_TIME_OUT_400us |
1713 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1714 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1715 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1716}
1717
1718static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1719{
0e0ae652
RV		 1720 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1721 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 1722 struct drm_i915_private *dev_priv = dev->dev_private;
1723 uint32_t max_sleep_time = 0x1f;
1724 uint32_t idle_frames = 1;
1725 uint32_t val = 0x0;
ed8546ac 1726 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 1727 bool only_standby = false;
1728
1729 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1730 only_standby = true;
2b28bb1b 1731
0e0ae652 1732 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 1733 val |= EDP_PSR_LINK_STANDBY;
1734 val |= EDP_PSR_TP2_TP3_TIME_0us;
1735 val |= EDP_PSR_TP1_TIME_0us;
1736 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 1737 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 1738 } else
1739 val |= EDP_PSR_LINK_DISABLE;
1740
18b5992c 1741 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1742 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1743 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1744 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1745 EDP_PSR_ENABLE);
1746}
1747
3f51e471
RV		 1748static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1749{
1750 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1751 struct drm_device *dev = dig_port->base.base.dev;
1752 struct drm_i915_private *dev_priv = dev->dev_private;
1753 struct drm_crtc *crtc = dig_port->base.base.crtc;
1754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f4510a27 1755 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1756 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1757
a031d709
RV		 1758 dev_priv->psr.source_ok = false;
1759
0e0ae652
RV		 1760 if (!HAS_PSR(dev)) {
1761 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1762 return false;
1763 }
1764
1765 if (IS_HASWELL(dev) && (intel_encoder->type != INTEL_OUTPUT_EDP ||
1766 dig_port->port != PORT_A)) {
3f51e471 1767 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1768 return false;
1769 }
1770
d330a953 1771 if (!i915.enable_psr) {
105b7c11 1772 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1773 return false;
1774 }
1775
cd234b0b
CW		 1776 crtc = dig_port->base.base.crtc;
1777 if (crtc == NULL) {
1778 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1779 return false;
1780 }
1781
1782 intel_crtc = to_intel_crtc(crtc);
20ddf665 1783 if (!intel_crtc_active(crtc)) {
3f51e471 1784 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1785 return false;
1786 }
1787
f4510a27 1788 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1789 if (obj->tiling_mode != I915_TILING_X ||
1790 obj->fence_reg == I915_FENCE_REG_NONE) {
1791 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1792 return false;
1793 }
1794
4c8c7000
RV		 1795 /* Below limitations aren't valid for Broadwell */
1796 if (IS_BROADWELL(dev))
1797 goto out;
1798
3f51e471
RV		 1799 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1800 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1801 return false;
1802 }
1803
1804 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1805 S3D_ENABLE) {
1806 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1807 return false;
1808 }
1809
ca73b4f0 1810 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1811 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1812 return false;
1813 }
1814
4c8c7000 1815 out:
a031d709 1816 dev_priv->psr.source_ok = true;
3f51e471
RV		 1817 return true;
1818}
1819
3d739d92 1820static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 1821{
7c8f8a70
RV		 1822 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1823 struct drm_device *dev = intel_dig_port->base.base.dev;
1824 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 1825
7c8f8a70 1826 if (intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1827 return;
1828
2b28bb1b
RV		 1829 /* Enable PSR on the panel */
1830 intel_edp_psr_enable_sink(intel_dp);
1831
1832 /* Enable PSR on the host */
1833 intel_edp_psr_enable_source(intel_dp);
7c8f8a70
RV		 1834
1835 dev_priv->psr.enabled = true;
1836 dev_priv->psr.active = true;
2b28bb1b
RV		 1837}
1838
3d739d92
RV		 1839void intel_edp_psr_enable(struct intel_dp *intel_dp)
1840{
1841 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1842
4704c573
RV		 1843 if (!HAS_PSR(dev)) {
1844 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1845 return;
1846 }
1847
34eb7579
RV		 1848 if (!is_edp_psr(intel_dp)) {
1849 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1850 return;
1851 }
1852
16487254
RV		 1853 /* Setup PSR once */
1854 intel_edp_psr_setup(intel_dp);
1855
7c8f8a70 1856 if (intel_edp_psr_match_conditions(intel_dp))
3d739d92
RV		 1857 intel_edp_psr_do_enable(intel_dp);
1858}
1859
2b28bb1b
RV		 1860void intel_edp_psr_disable(struct intel_dp *intel_dp)
1861{
1862 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1863 struct drm_i915_private *dev_priv = dev->dev_private;
1864
7c8f8a70 1865 if (!dev_priv->psr.enabled)
2b28bb1b
RV		 1866 return;
1867
18b5992c
BW		 1868 I915_WRITE(EDP_PSR_CTL(dev),
1869 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1870
1871 /* Wait till PSR is idle */
18b5992c 1872 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1873 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1874 DRM_ERROR("Timed out waiting for PSR Idle State\n");
7c8f8a70
RV		 1875
1876 dev_priv->psr.enabled = false;
2b28bb1b
RV		 1877}
1878
f02a326e 1879static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 1880{
1881 struct drm_i915_private *dev_priv =
1882 container_of(work, typeof(*dev_priv), psr.work.work);
1883 struct drm_device *dev = dev_priv->dev;
1884 struct intel_encoder *encoder;
1885 struct intel_dp *intel_dp = NULL;
1886
3d739d92
RV		 1887 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1888 if (encoder->type == INTEL_OUTPUT_EDP) {
1889 intel_dp = enc_to_intel_dp(&encoder->base);
1890
3d739d92
RV		 1891 if (!intel_edp_psr_match_conditions(intel_dp))
1892 intel_edp_psr_disable(intel_dp);
1893 else
7c8f8a70 1894 intel_edp_psr_do_enable(intel_dp);
3d739d92
RV		 1895 }
1896}
1897
f02a326e 1898static void intel_edp_psr_inactivate(struct drm_device *dev)
7c8f8a70
RV		 1899{
1900 struct drm_i915_private *dev_priv = dev->dev_private;
7c8f8a70 1901
77c70c56 1902 dev_priv->psr.active = false;
7c8f8a70 1903
77c70c56
DV		 1904 I915_WRITE(EDP_PSR_CTL(dev), I915_READ(EDP_PSR_CTL(dev))
1905 & ~EDP_PSR_ENABLE);
7c8f8a70
RV		 1906}
1907
3108e99e 1908void intel_edp_psr_exit(struct drm_device *dev)
7c8f8a70
RV		 1909{
1910 struct drm_i915_private *dev_priv = dev->dev_private;
1911
1912 if (!HAS_PSR(dev))
1913 return;
1914
1915 if (!dev_priv->psr.setup_done)
1916 return;
1917
1918 cancel_delayed_work_sync(&dev_priv->psr.work);
1919
1920 if (dev_priv->psr.active)
1921 intel_edp_psr_inactivate(dev);
1922
3108e99e
DV		 1923 schedule_delayed_work(&dev_priv->psr.work,
1924 msecs_to_jiffies(100));
7c8f8a70
RV		 1925}
1926
1927void intel_edp_psr_init(struct drm_device *dev)
1928{
1929 struct drm_i915_private *dev_priv = dev->dev_private;
1930
1931 if (!HAS_PSR(dev))
1932 return;
1933
1934 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
1935}
1936
e8cb4558 1937static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1938{
e8cb4558 1939 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1940 enum port port = dp_to_dig_port(intel_dp)->port;
1941 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1942
1943 /* Make sure the panel is off before trying to change the mode. But also
1944 * ensure that we have vdd while we switch off the panel. */
24f3e092 1945 intel_edp_panel_vdd_on(intel_dp);
4be73780 1946 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1947 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1948 intel_edp_panel_off(intel_dp);
3739850b
DV		 1949
1950 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1951 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1952 intel_dp_link_down(intel_dp);
d240f20f
JB		 1953}
1954
49277c31 1955static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1956{
2bd2ad64 1957 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1958 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 1959
49277c31
VS		 1960 if (port != PORT_A)
1961 return;
1962
1963 intel_dp_link_down(intel_dp);
1964 ironlake_edp_pll_off(intel_dp);
1965}
1966
1967static void vlv_post_disable_dp(struct intel_encoder *encoder)
1968{
1969 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1970
1971 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 1972}
1973
580d3811
VS		 1974static void chv_post_disable_dp(struct intel_encoder *encoder)
1975{
1976 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1977 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1978 struct drm_device *dev = encoder->base.dev;
1979 struct drm_i915_private *dev_priv = dev->dev_private;
1980 struct intel_crtc *intel_crtc =
1981 to_intel_crtc(encoder->base.crtc);
1982 enum dpio_channel ch = vlv_dport_to_channel(dport);
1983 enum pipe pipe = intel_crtc->pipe;
1984 u32 val;
1985
1986 intel_dp_link_down(intel_dp);
1987
1988 mutex_lock(&dev_priv->dpio_lock);
1989
1990 /* Propagate soft reset to data lane reset */
97fd4d5c 1991 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 1992 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 1993 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 1994
97fd4d5c
VS		 1995 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1996 val |= CHV_PCS_REQ_SOFTRESET_EN;
1997 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1998
1999 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2000 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2001 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2002
2003 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2004 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2005 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2006
2007 mutex_unlock(&dev_priv->dpio_lock);
2008}
2009
e8cb4558 2010static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2011{
e8cb4558
DV		 2012 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2013 struct drm_device *dev = encoder->base.dev;
2014 struct drm_i915_private *dev_priv = dev->dev_private;
2015 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2016
0c33d8d7
DV		 2017 if (WARN_ON(dp_reg & DP_PORT_EN))
2018 return;
5d613501 2019
24f3e092 2020 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 2021 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2022 intel_dp_start_link_train(intel_dp);
4be73780
DV		 2023 intel_edp_panel_on(intel_dp);
2024 edp_panel_vdd_off(intel_dp, true);
33a34e4e 2025 intel_dp_complete_link_train(intel_dp);
3ab9c637 2026 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2027}
89b667f8 2028
ecff4f3b
JN		 2029static void g4x_enable_dp(struct intel_encoder *encoder)
2030{
828f5c6e
JN		 2031 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2032
ecff4f3b 2033 intel_enable_dp(encoder);
4be73780 2034 intel_edp_backlight_on(intel_dp);
ab1f90f9 2035}
89b667f8 2036
ab1f90f9
JN		 2037static void vlv_enable_dp(struct intel_encoder *encoder)
2038{
828f5c6e
JN		 2039 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2040
4be73780 2041 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2042}
2043
ecff4f3b 2044static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2045{
2046 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2047 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2048
8ac33ed3
DV		 2049 intel_dp_prepare(encoder);
2050
d41f1efb
DV		 2051 /* Only ilk+ has port A */
2052 if (dport->port == PORT_A) {
2053 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2054 ironlake_edp_pll_on(intel_dp);
d41f1efb 2055 }
ab1f90f9
JN		 2056}
2057
2058static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2059{
2bd2ad64 2060 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2061 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2062 struct drm_device *dev = encoder->base.dev;
89b667f8 2063 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2064 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2065 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 2066 int pipe = intel_crtc->pipe;
bf13e81b 2067 struct edp_power_seq power_seq;
ab1f90f9 2068 u32 val;
a4fc5ed6 2069
ab1f90f9 2070 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2071
ab3c759a 2072 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2073 val = 0;
2074 if (pipe)
2075 val |= (1<<21);
2076 else
2077 val &= ~(1<<21);
2078 val |= 0x001000c4;
ab3c759a
CML		 2079 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2080 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2081 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2082
ab1f90f9
JN		 2083 mutex_unlock(&dev_priv->dpio_lock);
2084
2cac613b
ID		 2085 if (is_edp(intel_dp)) {
2086 /* init power sequencer on this pipe and port */
2087 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2088 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2089 &power_seq);
2090 }
bf13e81b 2091
ab1f90f9
JN		 2092 intel_enable_dp(encoder);
2093
e4607fcf 2094 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2095}
2096
ecff4f3b 2097static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2098{
2099 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2100 struct drm_device *dev = encoder->base.dev;
2101 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2102 struct intel_crtc *intel_crtc =
2103 to_intel_crtc(encoder->base.crtc);
e4607fcf 2104 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2105 int pipe = intel_crtc->pipe;
89b667f8 2106
8ac33ed3
DV		 2107 intel_dp_prepare(encoder);
2108
89b667f8 2109 /* Program Tx lane resets to default */
0980a60f 2110 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2111 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2112 DPIO_PCS_TX_LANE2_RESET |
2113 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2114 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2115 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2116 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2117 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2118 DPIO_PCS_CLK_SOFT_RESET);
2119
2120 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2121 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2122 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2123 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2124 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2125}
2126
e4a1d846
CML		 2127static void chv_pre_enable_dp(struct intel_encoder *encoder)
2128{
2129 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2130 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2131 struct drm_device *dev = encoder->base.dev;
2132 struct drm_i915_private *dev_priv = dev->dev_private;
2133 struct edp_power_seq power_seq;
2134 struct intel_crtc *intel_crtc =
2135 to_intel_crtc(encoder->base.crtc);
2136 enum dpio_channel ch = vlv_dport_to_channel(dport);
2137 int pipe = intel_crtc->pipe;
2138 int data, i;
949c1d43 2139 u32 val;
e4a1d846 2140
e4a1d846 2141 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2142
2143 /* Deassert soft data lane reset*/
97fd4d5c 2144 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2145 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2146 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2147
2148 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2149 val |= CHV_PCS_REQ_SOFTRESET_EN;
2150 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2151
2152 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2153 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2154 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2155
97fd4d5c 2156 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2157 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2158 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2159
2160 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2161 for (i = 0; i < 4; i++) {
2162 /* Set the latency optimal bit */
2163 data = (i == 1) ? 0x0 : 0x6;
2164 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2165 data << DPIO_FRC_LATENCY_SHFIT);
2166
2167 /* Set the upar bit */
2168 data = (i == 1) ? 0x0 : 0x1;
2169 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2170 data << DPIO_UPAR_SHIFT);
2171 }
2172
2173 /* Data lane stagger programming */
2174 /* FIXME: Fix up value only after power analysis */
2175
2176 mutex_unlock(&dev_priv->dpio_lock);
2177
2178 if (is_edp(intel_dp)) {
2179 /* init power sequencer on this pipe and port */
2180 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2181 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2182 &power_seq);
2183 }
2184
2185 intel_enable_dp(encoder);
2186
2187 vlv_wait_port_ready(dev_priv, dport);
2188}
2189
9197c88b
VS		 2190static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2191{
2192 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2193 struct drm_device *dev = encoder->base.dev;
2194 struct drm_i915_private *dev_priv = dev->dev_private;
2195 struct intel_crtc *intel_crtc =
2196 to_intel_crtc(encoder->base.crtc);
2197 enum dpio_channel ch = vlv_dport_to_channel(dport);
2198 enum pipe pipe = intel_crtc->pipe;
2199 u32 val;
2200
2201 mutex_lock(&dev_priv->dpio_lock);
2202
b9e5ac3c
VS		 2203 /* program left/right clock distribution */
2204 if (pipe != PIPE_B) {
2205 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2206 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2207 if (ch == DPIO_CH0)
2208 val |= CHV_BUFLEFTENA1_FORCE;
2209 if (ch == DPIO_CH1)
2210 val |= CHV_BUFRIGHTENA1_FORCE;
2211 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2212 } else {
2213 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2214 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2215 if (ch == DPIO_CH0)
2216 val |= CHV_BUFLEFTENA2_FORCE;
2217 if (ch == DPIO_CH1)
2218 val |= CHV_BUFRIGHTENA2_FORCE;
2219 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2220 }
2221
9197c88b
VS		 2222 /* program clock channel usage */
2223 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2224 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2225 if (pipe != PIPE_B)
2226 val &= ~CHV_PCS_USEDCLKCHANNEL;
2227 else
2228 val |= CHV_PCS_USEDCLKCHANNEL;
2229 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2230
2231 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2232 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2233 if (pipe != PIPE_B)
2234 val &= ~CHV_PCS_USEDCLKCHANNEL;
2235 else
2236 val |= CHV_PCS_USEDCLKCHANNEL;
2237 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2238
2239 /*
2240 * This a a bit weird since generally CL
2241 * matches the pipe, but here we need to
2242 * pick the CL based on the port.
2243 */
2244 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2245 if (pipe != PIPE_B)
2246 val &= ~CHV_CMN_USEDCLKCHANNEL;
2247 else
2248 val |= CHV_CMN_USEDCLKCHANNEL;
2249 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2250
2251 mutex_unlock(&dev_priv->dpio_lock);
2252}
2253
a4fc5ed6 2254/*
df0c237d
JB		 2255 * Native read with retry for link status and receiver capability reads for
2256 * cases where the sink may still be asleep.
9d1a1031
JN		 2257 *
2258 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2259 * supposed to retry 3 times per the spec.
a4fc5ed6 2260 */
9d1a1031
JN		 2261static ssize_t
2262intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2263 void *buffer, size_t size)
a4fc5ed6 2264{
9d1a1031
JN		 2265 ssize_t ret;
2266 int i;
61da5fab 2267
61da5fab 2268 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2269 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2270 if (ret == size)
2271 return ret;
61da5fab
JB		 2272 msleep(1);
2273 }
a4fc5ed6 2274
9d1a1031 2275 return ret;
a4fc5ed6
KP		 2276}
2277
2278/*
2279 * Fetch AUX CH registers 0x202 - 0x207 which contain
2280 * link status information
2281 */
2282static bool
93f62dad 2283intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2284{
9d1a1031
JN		 2285 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2286 DP_LANE0_1_STATUS,
2287 link_status,
2288 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2289}
2290
1100244e 2291/* These are source-specific values. */
a4fc5ed6 2292static uint8_t
1a2eb460 2293intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2294{
30add22d 2295 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2296 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2297
9576c27f 2298 if (IS_VALLEYVIEW(dev))
e2fa6fba 2299 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2300 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2301 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2302 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2303 return DP_TRAIN_VOLTAGE_SWING_1200;
2304 else
2305 return DP_TRAIN_VOLTAGE_SWING_800;
2306}
2307
2308static uint8_t
2309intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2310{
30add22d 2311 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2312 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2313
9576c27f 2314 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722
PZ		 2315 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2316 case DP_TRAIN_VOLTAGE_SWING_400:
2317 return DP_TRAIN_PRE_EMPHASIS_9_5;
2318 case DP_TRAIN_VOLTAGE_SWING_600:
2319 return DP_TRAIN_PRE_EMPHASIS_6;
2320 case DP_TRAIN_VOLTAGE_SWING_800:
2321 return DP_TRAIN_PRE_EMPHASIS_3_5;
2322 case DP_TRAIN_VOLTAGE_SWING_1200:
2323 default:
2324 return DP_TRAIN_PRE_EMPHASIS_0;
2325 }
e2fa6fba
P		 2326 } else if (IS_VALLEYVIEW(dev)) {
2327 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2328 case DP_TRAIN_VOLTAGE_SWING_400:
2329 return DP_TRAIN_PRE_EMPHASIS_9_5;
2330 case DP_TRAIN_VOLTAGE_SWING_600:
2331 return DP_TRAIN_PRE_EMPHASIS_6;
2332 case DP_TRAIN_VOLTAGE_SWING_800:
2333 return DP_TRAIN_PRE_EMPHASIS_3_5;
2334 case DP_TRAIN_VOLTAGE_SWING_1200:
2335 default:
2336 return DP_TRAIN_PRE_EMPHASIS_0;
2337 }
bc7d38a4 2338 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2339 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2340 case DP_TRAIN_VOLTAGE_SWING_400:
2341 return DP_TRAIN_PRE_EMPHASIS_6;
2342 case DP_TRAIN_VOLTAGE_SWING_600:
2343 case DP_TRAIN_VOLTAGE_SWING_800:
2344 return DP_TRAIN_PRE_EMPHASIS_3_5;
2345 default:
2346 return DP_TRAIN_PRE_EMPHASIS_0;
2347 }
2348 } else {
2349 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2350 case DP_TRAIN_VOLTAGE_SWING_400:
2351 return DP_TRAIN_PRE_EMPHASIS_6;
2352 case DP_TRAIN_VOLTAGE_SWING_600:
2353 return DP_TRAIN_PRE_EMPHASIS_6;
2354 case DP_TRAIN_VOLTAGE_SWING_800:
2355 return DP_TRAIN_PRE_EMPHASIS_3_5;
2356 case DP_TRAIN_VOLTAGE_SWING_1200:
2357 default:
2358 return DP_TRAIN_PRE_EMPHASIS_0;
2359 }
a4fc5ed6
KP		 2360 }
2361}
2362
e2fa6fba
P		 2363static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2364{
2365 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2368 struct intel_crtc *intel_crtc =
2369 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2370 unsigned long demph_reg_value, preemph_reg_value,
2371 uniqtranscale_reg_value;
2372 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2373 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2374 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2375
2376 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2377 case DP_TRAIN_PRE_EMPHASIS_0:
2378 preemph_reg_value = 0x0004000;
2379 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2380 case DP_TRAIN_VOLTAGE_SWING_400:
2381 demph_reg_value = 0x2B405555;
2382 uniqtranscale_reg_value = 0x552AB83A;
2383 break;
2384 case DP_TRAIN_VOLTAGE_SWING_600:
2385 demph_reg_value = 0x2B404040;
2386 uniqtranscale_reg_value = 0x5548B83A;
2387 break;
2388 case DP_TRAIN_VOLTAGE_SWING_800:
2389 demph_reg_value = 0x2B245555;
2390 uniqtranscale_reg_value = 0x5560B83A;
2391 break;
2392 case DP_TRAIN_VOLTAGE_SWING_1200:
2393 demph_reg_value = 0x2B405555;
2394 uniqtranscale_reg_value = 0x5598DA3A;
2395 break;
2396 default:
2397 return 0;
2398 }
2399 break;
2400 case DP_TRAIN_PRE_EMPHASIS_3_5:
2401 preemph_reg_value = 0x0002000;
2402 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2403 case DP_TRAIN_VOLTAGE_SWING_400:
2404 demph_reg_value = 0x2B404040;
2405 uniqtranscale_reg_value = 0x5552B83A;
2406 break;
2407 case DP_TRAIN_VOLTAGE_SWING_600:
2408 demph_reg_value = 0x2B404848;
2409 uniqtranscale_reg_value = 0x5580B83A;
2410 break;
2411 case DP_TRAIN_VOLTAGE_SWING_800:
2412 demph_reg_value = 0x2B404040;
2413 uniqtranscale_reg_value = 0x55ADDA3A;
2414 break;
2415 default:
2416 return 0;
2417 }
2418 break;
2419 case DP_TRAIN_PRE_EMPHASIS_6:
2420 preemph_reg_value = 0x0000000;
2421 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2422 case DP_TRAIN_VOLTAGE_SWING_400:
2423 demph_reg_value = 0x2B305555;
2424 uniqtranscale_reg_value = 0x5570B83A;
2425 break;
2426 case DP_TRAIN_VOLTAGE_SWING_600:
2427 demph_reg_value = 0x2B2B4040;
2428 uniqtranscale_reg_value = 0x55ADDA3A;
2429 break;
2430 default:
2431 return 0;
2432 }
2433 break;
2434 case DP_TRAIN_PRE_EMPHASIS_9_5:
2435 preemph_reg_value = 0x0006000;
2436 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2437 case DP_TRAIN_VOLTAGE_SWING_400:
2438 demph_reg_value = 0x1B405555;
2439 uniqtranscale_reg_value = 0x55ADDA3A;
2440 break;
2441 default:
2442 return 0;
2443 }
2444 break;
2445 default:
2446 return 0;
2447 }
2448
0980a60f 2449 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2450 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2451 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2452 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2453 uniqtranscale_reg_value);
ab3c759a
CML		 2454 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2455 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2456 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2457 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2458 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2459
2460 return 0;
2461}
2462
e4a1d846
CML		 2463static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2464{
2465 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2466 struct drm_i915_private *dev_priv = dev->dev_private;
2467 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2468 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2469 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2470 uint8_t train_set = intel_dp->train_set[0];
2471 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2472 enum pipe pipe = intel_crtc->pipe;
2473 int i;
e4a1d846
CML		 2474
2475 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2476 case DP_TRAIN_PRE_EMPHASIS_0:
2477 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2478 case DP_TRAIN_VOLTAGE_SWING_400:
2479 deemph_reg_value = 128;
2480 margin_reg_value = 52;
2481 break;
2482 case DP_TRAIN_VOLTAGE_SWING_600:
2483 deemph_reg_value = 128;
2484 margin_reg_value = 77;
2485 break;
2486 case DP_TRAIN_VOLTAGE_SWING_800:
2487 deemph_reg_value = 128;
2488 margin_reg_value = 102;
2489 break;
2490 case DP_TRAIN_VOLTAGE_SWING_1200:
2491 deemph_reg_value = 128;
2492 margin_reg_value = 154;
2493 /* FIXME extra to set for 1200 */
2494 break;
2495 default:
2496 return 0;
2497 }
2498 break;
2499 case DP_TRAIN_PRE_EMPHASIS_3_5:
2500 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2501 case DP_TRAIN_VOLTAGE_SWING_400:
2502 deemph_reg_value = 85;
2503 margin_reg_value = 78;
2504 break;
2505 case DP_TRAIN_VOLTAGE_SWING_600:
2506 deemph_reg_value = 85;
2507 margin_reg_value = 116;
2508 break;
2509 case DP_TRAIN_VOLTAGE_SWING_800:
2510 deemph_reg_value = 85;
2511 margin_reg_value = 154;
2512 break;
2513 default:
2514 return 0;
2515 }
2516 break;
2517 case DP_TRAIN_PRE_EMPHASIS_6:
2518 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2519 case DP_TRAIN_VOLTAGE_SWING_400:
2520 deemph_reg_value = 64;
2521 margin_reg_value = 104;
2522 break;
2523 case DP_TRAIN_VOLTAGE_SWING_600:
2524 deemph_reg_value = 64;
2525 margin_reg_value = 154;
2526 break;
2527 default:
2528 return 0;
2529 }
2530 break;
2531 case DP_TRAIN_PRE_EMPHASIS_9_5:
2532 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2533 case DP_TRAIN_VOLTAGE_SWING_400:
2534 deemph_reg_value = 43;
2535 margin_reg_value = 154;
2536 break;
2537 default:
2538 return 0;
2539 }
2540 break;
2541 default:
2542 return 0;
2543 }
2544
2545 mutex_lock(&dev_priv->dpio_lock);
2546
2547 /* Clear calc init */
1966e59e
VS		 2548 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2549 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2550 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2551
2552 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2553 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2554 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2555
2556 /* Program swing deemph */
f72df8db
VS		 2557 for (i = 0; i < 4; i++) {
2558 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2559 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2560 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2561 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2562 }
e4a1d846
CML		 2563
2564 /* Program swing margin */
f72df8db
VS		 2565 for (i = 0; i < 4; i++) {
2566 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2567 val &= ~DPIO_SWING_MARGIN_MASK;
2568 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2569 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2570 }
e4a1d846
CML		 2571
2572 /* Disable unique transition scale */
f72df8db
VS		 2573 for (i = 0; i < 4; i++) {
2574 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2575 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2576 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2577 }
e4a1d846
CML		 2578
2579 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2580 == DP_TRAIN_PRE_EMPHASIS_0) &&
2581 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2582 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2583
2584 /*
2585 * The document said it needs to set bit 27 for ch0 and bit 26
2586 * for ch1. Might be a typo in the doc.
2587 * For now, for this unique transition scale selection, set bit
2588 * 27 for ch0 and ch1.
2589 */
f72df8db
VS		 2590 for (i = 0; i < 4; i++) {
2591 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2592 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2593 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2594 }
e4a1d846 2595
f72df8db
VS		 2596 for (i = 0; i < 4; i++) {
2597 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2598 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2599 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2600 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2601 }
e4a1d846
CML		 2602 }
2603
2604 /* Start swing calculation */
1966e59e
VS		 2605 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2606 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2607 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2608
2609 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2610 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2611 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2612
2613 /* LRC Bypass */
2614 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2615 val |= DPIO_LRC_BYPASS;
2616 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2617
2618 mutex_unlock(&dev_priv->dpio_lock);
2619
2620 return 0;
2621}
2622
a4fc5ed6 2623static void
0301b3ac
JN		 2624intel_get_adjust_train(struct intel_dp *intel_dp,
2625 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2626{
2627 uint8_t v = 0;
2628 uint8_t p = 0;
2629 int lane;
1a2eb460
KP		 2630 uint8_t voltage_max;
2631 uint8_t preemph_max;
a4fc5ed6 2632
33a34e4e 2633 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2634 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2635 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2636
2637 if (this_v > v)
2638 v = this_v;
2639 if (this_p > p)
2640 p = this_p;
2641 }
2642
1a2eb460 2643 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2644 if (v >= voltage_max)
2645 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2646
1a2eb460
KP		 2647 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2648 if (p >= preemph_max)
2649 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2650
2651 for (lane = 0; lane < 4; lane++)
33a34e4e 2652 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2653}
2654
2655static uint32_t
f0a3424e 2656intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2657{
3cf2efb1 2658 uint32_t signal_levels = 0;
a4fc5ed6 2659
3cf2efb1 2660 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2661 case DP_TRAIN_VOLTAGE_SWING_400:
2662 default:
2663 signal_levels |= DP_VOLTAGE_0_4;
2664 break;
2665 case DP_TRAIN_VOLTAGE_SWING_600:
2666 signal_levels |= DP_VOLTAGE_0_6;
2667 break;
2668 case DP_TRAIN_VOLTAGE_SWING_800:
2669 signal_levels |= DP_VOLTAGE_0_8;
2670 break;
2671 case DP_TRAIN_VOLTAGE_SWING_1200:
2672 signal_levels |= DP_VOLTAGE_1_2;
2673 break;
2674 }
3cf2efb1 2675 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2676 case DP_TRAIN_PRE_EMPHASIS_0:
2677 default:
2678 signal_levels |= DP_PRE_EMPHASIS_0;
2679 break;
2680 case DP_TRAIN_PRE_EMPHASIS_3_5:
2681 signal_levels |= DP_PRE_EMPHASIS_3_5;
2682 break;
2683 case DP_TRAIN_PRE_EMPHASIS_6:
2684 signal_levels |= DP_PRE_EMPHASIS_6;
2685 break;
2686 case DP_TRAIN_PRE_EMPHASIS_9_5:
2687 signal_levels |= DP_PRE_EMPHASIS_9_5;
2688 break;
2689 }
2690 return signal_levels;
2691}
2692
e3421a18
ZW		 2693/* Gen6's DP voltage swing and pre-emphasis control */
2694static uint32_t
2695intel_gen6_edp_signal_levels(uint8_t train_set)
2696{
3c5a62b5
YL		 2697 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2698 DP_TRAIN_PRE_EMPHASIS_MASK);
2699 switch (signal_levels) {
e3421a18 2700 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2701 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2702 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2703 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2704 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2705 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2706 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2707 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2708 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2709 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2710 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2711 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2712 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2713 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2714 default:
3c5a62b5
YL		 2715 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2716 "0x%x\n", signal_levels);
2717 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2718 }
2719}
2720
1a2eb460
KP		 2721/* Gen7's DP voltage swing and pre-emphasis control */
2722static uint32_t
2723intel_gen7_edp_signal_levels(uint8_t train_set)
2724{
2725 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2726 DP_TRAIN_PRE_EMPHASIS_MASK);
2727 switch (signal_levels) {
2728 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2729 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2730 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2731 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2732 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2733 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2734
2735 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2736 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2737 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2738 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2739
2740 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2741 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2742 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2743 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2744
2745 default:
2746 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2747 "0x%x\n", signal_levels);
2748 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2749 }
2750}
2751
d6c0d722
PZ		 2752/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2753static uint32_t
f0a3424e 2754intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2755{
d6c0d722
PZ		 2756 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2757 DP_TRAIN_PRE_EMPHASIS_MASK);
2758 switch (signal_levels) {
2759 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2760 return DDI_BUF_EMP_400MV_0DB_HSW;
2761 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2762 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2763 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2764 return DDI_BUF_EMP_400MV_6DB_HSW;
2765 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2766 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2767
d6c0d722
PZ		 2768 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2769 return DDI_BUF_EMP_600MV_0DB_HSW;
2770 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2771 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2772 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2773 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2774
d6c0d722
PZ		 2775 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2776 return DDI_BUF_EMP_800MV_0DB_HSW;
2777 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2778 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2779 default:
2780 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2781 "0x%x\n", signal_levels);
2782 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2783 }
a4fc5ed6
KP		 2784}
2785
f0a3424e
PZ		 2786/* Properly updates "DP" with the correct signal levels. */
2787static void
2788intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2789{
2790 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2791 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2792 struct drm_device *dev = intel_dig_port->base.base.dev;
2793 uint32_t signal_levels, mask;
2794 uint8_t train_set = intel_dp->train_set[0];
2795
9576c27f 2796 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 2797 signal_levels = intel_hsw_signal_levels(train_set);
2798 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2799 } else if (IS_CHERRYVIEW(dev)) {
2800 signal_levels = intel_chv_signal_levels(intel_dp);
2801 mask = 0;
e2fa6fba
P		 2802 } else if (IS_VALLEYVIEW(dev)) {
2803 signal_levels = intel_vlv_signal_levels(intel_dp);
2804 mask = 0;
bc7d38a4 2805 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2806 signal_levels = intel_gen7_edp_signal_levels(train_set);
2807 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2808 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2809 signal_levels = intel_gen6_edp_signal_levels(train_set);
2810 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2811 } else {
2812 signal_levels = intel_gen4_signal_levels(train_set);
2813 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2814 }
2815
2816 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2817
2818 *DP = (*DP & ~mask) | signal_levels;
2819}
2820
a4fc5ed6 2821static bool
ea5b213a 2822intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2823 uint32_t *DP,
58e10eb9 2824 uint8_t dp_train_pat)
a4fc5ed6 2825{
174edf1f
PZ		 2826 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2827 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2828 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2829 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2830 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2831 int ret, len;
a4fc5ed6 2832
22b8bf17 2833 if (HAS_DDI(dev)) {
3ab9c637 2834 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2835
2836 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2837 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2838 else
2839 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2840
2841 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2842 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2843 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2844 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2845
2846 break;
2847 case DP_TRAINING_PATTERN_1:
2848 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2849 break;
2850 case DP_TRAINING_PATTERN_2:
2851 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2852 break;
2853 case DP_TRAINING_PATTERN_3:
2854 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2855 break;
2856 }
174edf1f 2857 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2858
bc7d38a4 2859 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2860 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2861
2862 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2863 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2864 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2865 break;
2866 case DP_TRAINING_PATTERN_1:
70aff66c 2867 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2868 break;
2869 case DP_TRAINING_PATTERN_2:
70aff66c 2870 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2871 break;
2872 case DP_TRAINING_PATTERN_3:
2873 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2874 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2875 break;
2876 }
2877
2878 } else {
70aff66c 2879 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2880
2881 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2882 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2883 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2884 break;
2885 case DP_TRAINING_PATTERN_1:
70aff66c 2886 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2887 break;
2888 case DP_TRAINING_PATTERN_2:
70aff66c 2889 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2890 break;
2891 case DP_TRAINING_PATTERN_3:
2892 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2893 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2894 break;
2895 }
2896 }
2897
70aff66c 2898 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2899 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2900
2cdfe6c8
JN		 2901 buf[0] = dp_train_pat;
2902 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2903 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2904 /* don't write DP_TRAINING_LANEx_SET on disable */
2905 len = 1;
2906 } else {
2907 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2908 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2909 len = intel_dp->lane_count + 1;
47ea7542 2910 }
a4fc5ed6 2911
9d1a1031
JN		 2912 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2913 buf, len);
2cdfe6c8
JN		 2914
2915 return ret == len;
a4fc5ed6
KP		 2916}
2917
70aff66c
JN		 2918static bool
2919intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2920 uint8_t dp_train_pat)
2921{
953d22e8 2922 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2923 intel_dp_set_signal_levels(intel_dp, DP);
2924 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2925}
2926
2927static bool
2928intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2929 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2930{
2931 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2932 struct drm_device *dev = intel_dig_port->base.base.dev;
2933 struct drm_i915_private *dev_priv = dev->dev_private;
2934 int ret;
2935
2936 intel_get_adjust_train(intel_dp, link_status);
2937 intel_dp_set_signal_levels(intel_dp, DP);
2938
2939 I915_WRITE(intel_dp->output_reg, *DP);
2940 POSTING_READ(intel_dp->output_reg);
2941
9d1a1031
JN		 2942 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2943 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2944
2945 return ret == intel_dp->lane_count;
2946}
2947
3ab9c637
ID		 2948static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2949{
2950 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2951 struct drm_device *dev = intel_dig_port->base.base.dev;
2952 struct drm_i915_private *dev_priv = dev->dev_private;
2953 enum port port = intel_dig_port->port;
2954 uint32_t val;
2955
2956 if (!HAS_DDI(dev))
2957 return;
2958
2959 val = I915_READ(DP_TP_CTL(port));
2960 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2961 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2962 I915_WRITE(DP_TP_CTL(port), val);
2963
2964 /*
2965 * On PORT_A we can have only eDP in SST mode. There the only reason
2966 * we need to set idle transmission mode is to work around a HW issue
2967 * where we enable the pipe while not in idle link-training mode.
2968 * In this case there is requirement to wait for a minimum number of
2969 * idle patterns to be sent.
2970 */
2971 if (port == PORT_A)
2972 return;
2973
2974 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2975 1))
2976 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2977}
2978
33a34e4e 2979/* Enable corresponding port and start training pattern 1 */
c19b0669 2980void
33a34e4e 2981intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2982{
da63a9f2 2983 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2984 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2985 int i;
2986 uint8_t voltage;
cdb0e95b 2987 int voltage_tries, loop_tries;
ea5b213a 2988 uint32_t DP = intel_dp->DP;
6aba5b6c 2989 uint8_t link_config[2];
a4fc5ed6 2990
affa9354 2991 if (HAS_DDI(dev))
c19b0669
PZ		 2992 intel_ddi_prepare_link_retrain(encoder);
2993
3cf2efb1 2994 /* Write the link configuration data */
6aba5b6c
JN		 2995 link_config[0] = intel_dp->link_bw;
2996 link_config[1] = intel_dp->lane_count;
2997 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2998 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 2999 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3000
3001 link_config[0] = 0;
3002 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3003 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3004
3005 DP |= DP_PORT_EN;
1a2eb460 3006
70aff66c
JN		 3007 /* clock recovery */
3008 if (!intel_dp_reset_link_train(intel_dp, &DP,
3009 DP_TRAINING_PATTERN_1 |
3010 DP_LINK_SCRAMBLING_DISABLE)) {
3011 DRM_ERROR("failed to enable link training\n");
3012 return;
3013 }
3014
a4fc5ed6 3015 voltage = 0xff;
cdb0e95b
KP		 3016 voltage_tries = 0;
3017 loop_tries = 0;
a4fc5ed6 3018 for (;;) {
70aff66c 3019 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3020
a7c9655f 3021 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3022 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3023 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3024 break;
93f62dad 3025 }
a4fc5ed6 3026
01916270 3027 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3028 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3029 break;
3030 }
3031
3032 /* Check to see if we've tried the max voltage */
3033 for (i = 0; i < intel_dp->lane_count; i++)
3034 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3035 break;
3b4f819d 3036 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3037 ++loop_tries;
3038 if (loop_tries == 5) {
3def84b3 3039 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3040 break;
3041 }
70aff66c
JN		 3042 intel_dp_reset_link_train(intel_dp, &DP,
3043 DP_TRAINING_PATTERN_1 |
3044 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3045 voltage_tries = 0;
3046 continue;
3047 }
a4fc5ed6 3048
3cf2efb1 3049 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3050 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3051 ++voltage_tries;
b06fbda3 3052 if (voltage_tries == 5) {
3def84b3 3053 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3054 break;
3055 }
3056 } else
3057 voltage_tries = 0;
3058 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3059
70aff66c
JN		 3060 /* Update training set as requested by target */
3061 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3062 DRM_ERROR("failed to update link training\n");
3063 break;
3064 }
a4fc5ed6
KP		 3065 }
3066
33a34e4e
JB		 3067 intel_dp->DP = DP;
3068}
3069
c19b0669 3070void
33a34e4e
JB		 3071intel_dp_complete_link_train(struct intel_dp *intel_dp)
3072{
33a34e4e 3073 bool channel_eq = false;
37f80975 3074 int tries, cr_tries;
33a34e4e 3075 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3076 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3077
3078 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3079 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3080 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3081
a4fc5ed6 3082 /* channel equalization */
70aff66c 3083 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3084 training_pattern |
70aff66c
JN		 3085 DP_LINK_SCRAMBLING_DISABLE)) {
3086 DRM_ERROR("failed to start channel equalization\n");
3087 return;
3088 }
3089
a4fc5ed6 3090 tries = 0;
37f80975 3091 cr_tries = 0;
a4fc5ed6
KP		 3092 channel_eq = false;
3093 for (;;) {
70aff66c 3094 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3095
37f80975
JB		 3096 if (cr_tries > 5) {
3097 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3098 break;
3099 }
3100
a7c9655f 3101 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3102 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3103 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3104 break;
70aff66c 3105 }
a4fc5ed6 3106
37f80975 3107 /* Make sure clock is still ok */
01916270 3108 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3109 intel_dp_start_link_train(intel_dp);
70aff66c 3110 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3111 training_pattern |
70aff66c 3112 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3113 cr_tries++;
3114 continue;
3115 }
3116
1ffdff13 3117 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3118 channel_eq = true;
3119 break;
3120 }
a4fc5ed6 3121
37f80975
JB		 3122 /* Try 5 times, then try clock recovery if that fails */
3123 if (tries > 5) {
3124 intel_dp_link_down(intel_dp);
3125 intel_dp_start_link_train(intel_dp);
70aff66c 3126 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3127 training_pattern |
70aff66c 3128 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3129 tries = 0;
3130 cr_tries++;
3131 continue;
3132 }
a4fc5ed6 3133
70aff66c
JN		 3134 /* Update training set as requested by target */
3135 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3136 DRM_ERROR("failed to update link training\n");
3137 break;
3138 }
3cf2efb1 3139 ++tries;
869184a6 3140 }
3cf2efb1 3141
3ab9c637
ID		 3142 intel_dp_set_idle_link_train(intel_dp);
3143
3144 intel_dp->DP = DP;
3145
d6c0d722 3146 if (channel_eq)
07f42258 3147 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3148
3ab9c637
ID		 3149}
3150
3151void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3152{
70aff66c 3153 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3154 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3155}
3156
3157static void
ea5b213a 3158intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3159{
da63a9f2 3160 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3161 enum port port = intel_dig_port->port;
da63a9f2 3162 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3163 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3164 struct intel_crtc *intel_crtc =
3165 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3166 uint32_t DP = intel_dp->DP;
a4fc5ed6 3167
bc76e320 3168 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3169 return;
3170
0c33d8d7 3171 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3172 return;
3173
28c97730 3174 DRM_DEBUG_KMS("\n");
32f9d658 3175
bc7d38a4 3176 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3177 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3178 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 3179 } else {
3180 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3181 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3182 }
fe255d00 3183 POSTING_READ(intel_dp->output_reg);
5eb08b69 3184
493a7081 3185 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3186 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3187 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3188
5bddd17f
EA		 3189 /* Hardware workaround: leaving our transcoder select
3190 * set to transcoder B while it's off will prevent the
3191 * corresponding HDMI output on transcoder A.
3192 *
3193 * Combine this with another hardware workaround:
3194 * transcoder select bit can only be cleared while the
3195 * port is enabled.
3196 */
3197 DP &= ~DP_PIPEB_SELECT;
3198 I915_WRITE(intel_dp->output_reg, DP);
3199
3200 /* Changes to enable or select take place the vblank
3201 * after being written.
3202 */
ff50afe9
DV		 3203 if (WARN_ON(crtc == NULL)) {
3204 /* We should never try to disable a port without a crtc
3205 * attached. For paranoia keep the code around for a
3206 * bit. */
31acbcc4
CW		 3207 POSTING_READ(intel_dp->output_reg);
3208 msleep(50);
3209 } else
ab527efc 3210 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3211 }
3212
832afda6 3213 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3214 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3215 POSTING_READ(intel_dp->output_reg);
f01eca2e 3216 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3217}
3218
26d61aad
KP		 3219static bool
3220intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3221{
a031d709
RV		 3222 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3223 struct drm_device *dev = dig_port->base.base.dev;
3224 struct drm_i915_private *dev_priv = dev->dev_private;
3225
577c7a50
DL		 3226 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3227
9d1a1031
JN		 3228 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3229 sizeof(intel_dp->dpcd)) < 0)
edb39244 3230 return false; /* aux transfer failed */
92fd8fd1 3231
577c7a50
DL		 3232 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3233 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3234 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3235
edb39244
AJ		 3236 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3237 return false; /* DPCD not present */
3238
2293bb5c
SK		 3239 /* Check if the panel supports PSR */
3240 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3241 if (is_edp(intel_dp)) {
9d1a1031
JN		 3242 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3243 intel_dp->psr_dpcd,
3244 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3245 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3246 dev_priv->psr.sink_support = true;
50003939 3247 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3248 }
50003939
JN		 3249 }
3250
06ea66b6
TP		 3251 /* Training Pattern 3 support */
3252 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3253 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3254 intel_dp->use_tps3 = true;
3255 DRM_DEBUG_KMS("Displayport TPS3 supported");
3256 } else
3257 intel_dp->use_tps3 = false;
3258
edb39244
AJ		 3259 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3260 DP_DWN_STRM_PORT_PRESENT))
3261 return true; /* native DP sink */
3262
3263 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3264 return true; /* no per-port downstream info */
3265
9d1a1031
JN		 3266 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3267 intel_dp->downstream_ports,
3268 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3269 return false; /* downstream port status fetch failed */
3270
3271 return true;
92fd8fd1
KP		 3272}
3273
0d198328
AJ		 3274static void
3275intel_dp_probe_oui(struct intel_dp *intel_dp)
3276{
3277 u8 buf[3];
3278
3279 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3280 return;
3281
24f3e092 3282 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3283
9d1a1031 3284 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3285 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3286 buf[0], buf[1], buf[2]);
3287
9d1a1031 3288 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3289 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3290 buf[0], buf[1], buf[2]);
351cfc34 3291
4be73780 3292 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3293}
3294
d2e216d0
RV		 3295int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3296{
3297 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3298 struct drm_device *dev = intel_dig_port->base.base.dev;
3299 struct intel_crtc *intel_crtc =
3300 to_intel_crtc(intel_dig_port->base.base.crtc);
3301 u8 buf[1];
3302
9d1a1031 3303 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3304 return -EAGAIN;
3305
3306 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3307 return -ENOTTY;
3308
9d1a1031
JN		 3309 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3310 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3311 return -EAGAIN;
3312
3313 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3314 intel_wait_for_vblank(dev, intel_crtc->pipe);
3315 intel_wait_for_vblank(dev, intel_crtc->pipe);
3316
9d1a1031 3317 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3318 return -EAGAIN;
3319
9d1a1031 3320 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3321 return 0;
3322}
3323
a60f0e38
JB		 3324static bool
3325intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3326{
9d1a1031
JN		 3327 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3328 DP_DEVICE_SERVICE_IRQ_VECTOR,
3329 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3330}
3331
3332static void
3333intel_dp_handle_test_request(struct intel_dp *intel_dp)
3334{
3335 /* NAK by default */
9d1a1031 3336 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3337}
3338
a4fc5ed6
KP		 3339/*
3340 * According to DP spec
3341 * 5.1.2:
3342 * 1. Read DPCD
3343 * 2. Configure link according to Receiver Capabilities
3344 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3345 * 4. Check link status on receipt of hot-plug interrupt
3346 */
3347
00c09d70 3348void
ea5b213a 3349intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3350{
da63a9f2 3351 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3352 u8 sink_irq_vector;
93f62dad 3353 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3354
6e9f798d 3355 /* FIXME: This access isn't protected by any locks. */
da63a9f2 3356 if (!intel_encoder->connectors_active)
d2b996ac 3357 return;
59cd09e1 3358
da63a9f2 3359 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3360 return;
3361
92fd8fd1 3362 /* Try to read receiver status if the link appears to be up */
93f62dad 3363 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3364 return;
3365 }
3366
92fd8fd1 3367 /* Now read the DPCD to see if it's actually running */
26d61aad 3368 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3369 return;
3370 }
3371
a60f0e38
JB		 3372 /* Try to read the source of the interrupt */
3373 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3374 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3375 /* Clear interrupt source */
9d1a1031
JN		 3376 drm_dp_dpcd_writeb(&intel_dp->aux,
3377 DP_DEVICE_SERVICE_IRQ_VECTOR,
3378 sink_irq_vector);
a60f0e38
JB		 3379
3380 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3381 intel_dp_handle_test_request(intel_dp);
3382 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3383 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3384 }
3385
1ffdff13 3386 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3387 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3388 intel_encoder->base.name);
33a34e4e
JB		 3389 intel_dp_start_link_train(intel_dp);
3390 intel_dp_complete_link_train(intel_dp);
3ab9c637 3391 intel_dp_stop_link_train(intel_dp);
33a34e4e 3392 }
a4fc5ed6 3393}
a4fc5ed6 3394
caf9ab24 3395/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3396static enum drm_connector_status
26d61aad 3397intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3398{
caf9ab24 3399 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3400 uint8_t type;
3401
3402 if (!intel_dp_get_dpcd(intel_dp))
3403 return connector_status_disconnected;
3404
3405 /* if there's no downstream port, we're done */
3406 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3407 return connector_status_connected;
caf9ab24
AJ		 3408
3409 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3410 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3411 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3412 uint8_t reg;
9d1a1031
JN		 3413
3414 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3415 &reg, 1) < 0)
caf9ab24 3416 return connector_status_unknown;
9d1a1031 3417
23235177
AJ		 3418 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3419 : connector_status_disconnected;
caf9ab24
AJ		 3420 }
3421
3422 /* If no HPD, poke DDC gently */
0b99836f 3423 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3424 return connector_status_connected;
caf9ab24
AJ		 3425
3426 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3427 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3428 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3429 if (type == DP_DS_PORT_TYPE_VGA ||
3430 type == DP_DS_PORT_TYPE_NON_EDID)
3431 return connector_status_unknown;
3432 } else {
3433 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3434 DP_DWN_STRM_PORT_TYPE_MASK;
3435 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3436 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3437 return connector_status_unknown;
3438 }
caf9ab24
AJ		 3439
3440 /* Anything else is out of spec, warn and ignore */
3441 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3442 return connector_status_disconnected;
71ba9000
AJ		 3443}
3444
5eb08b69 3445static enum drm_connector_status
a9756bb5 3446ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3447{
30add22d 3448 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3449 struct drm_i915_private *dev_priv = dev->dev_private;
3450 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3451 enum drm_connector_status status;
3452
fe16d949
CW		 3453 /* Can't disconnect eDP, but you can close the lid... */
3454 if (is_edp(intel_dp)) {
30add22d 3455 status = intel_panel_detect(dev);
fe16d949
CW		 3456 if (status == connector_status_unknown)
3457 status = connector_status_connected;
3458 return status;
3459 }
01cb9ea6 3460
1b469639
DL		 3461 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3462 return connector_status_disconnected;
3463
26d61aad 3464 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3465}
3466
a4fc5ed6 3467static enum drm_connector_status
a9756bb5 3468g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3469{
30add22d 3470 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3471 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3472 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3473 uint32_t bit;
5eb08b69 3474
35aad75f
JB		 3475 /* Can't disconnect eDP, but you can close the lid... */
3476 if (is_edp(intel_dp)) {
3477 enum drm_connector_status status;
3478
3479 status = intel_panel_detect(dev);
3480 if (status == connector_status_unknown)
3481 status = connector_status_connected;
3482 return status;
3483 }
3484
232a6ee9
TP		 3485 if (IS_VALLEYVIEW(dev)) {
3486 switch (intel_dig_port->port) {
3487 case PORT_B:
3488 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3489 break;
3490 case PORT_C:
3491 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3492 break;
3493 case PORT_D:
3494 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3495 break;
3496 default:
3497 return connector_status_unknown;
3498 }
3499 } else {
3500 switch (intel_dig_port->port) {
3501 case PORT_B:
3502 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3503 break;
3504 case PORT_C:
3505 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3506 break;
3507 case PORT_D:
3508 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3509 break;
3510 default:
3511 return connector_status_unknown;
3512 }
a4fc5ed6
KP		 3513 }
3514
10f76a38 3515 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3516 return connector_status_disconnected;
3517
26d61aad 3518 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3519}
3520
8c241fef
KP		 3521static struct edid *
3522intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3523{
9cd300e0 3524 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3525
9cd300e0
JN		 3526 /* use cached edid if we have one */
3527 if (intel_connector->edid) {
9cd300e0
JN		 3528 /* invalid edid */
3529 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3530 return NULL;
3531
55e9edeb 3532 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3533 }
8c241fef 3534
9cd300e0 3535 return drm_get_edid(connector, adapter);
8c241fef
KP		 3536}
3537
3538static int
3539intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3540{
9cd300e0 3541 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3542
9cd300e0
JN		 3543 /* use cached edid if we have one */
3544 if (intel_connector->edid) {
3545 /* invalid edid */
3546 if (IS_ERR(intel_connector->edid))
3547 return 0;
3548
3549 return intel_connector_update_modes(connector,
3550 intel_connector->edid);
d6f24d0f
JB		 3551 }
3552
9cd300e0 3553 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3554}
3555
a9756bb5
ZW		 3556static enum drm_connector_status
3557intel_dp_detect(struct drm_connector *connector, bool force)
3558{
3559 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3560 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3561 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3562 struct drm_device *dev = connector->dev;
c8c8fb33 3563 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3564 enum drm_connector_status status;
671dedd2 3565 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3566 struct edid *edid = NULL;
3567
c8c8fb33
PZ		 3568 intel_runtime_pm_get(dev_priv);
3569
671dedd2
ID		 3570 power_domain = intel_display_port_power_domain(intel_encoder);
3571 intel_display_power_get(dev_priv, power_domain);
3572
164c8598 3573 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 3574 connector->base.id, connector->name);
164c8598 3575
a9756bb5
ZW		 3576 intel_dp->has_audio = false;
3577
3578 if (HAS_PCH_SPLIT(dev))
3579 status = ironlake_dp_detect(intel_dp);
3580 else
3581 status = g4x_dp_detect(intel_dp);
1b9be9d0 3582
a9756bb5 3583 if (status != connector_status_connected)
c8c8fb33 3584 goto out;
a9756bb5 3585
0d198328
AJ		 3586 intel_dp_probe_oui(intel_dp);
3587
c3e5f67b
DV		 3588 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3589 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3590 } else {
0b99836f 3591 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3592 if (edid) {
3593 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3594 kfree(edid);
3595 }
a9756bb5
ZW		 3596 }
3597
d63885da
PZ		 3598 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3599 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3600 status = connector_status_connected;
3601
3602out:
671dedd2
ID		 3603 intel_display_power_put(dev_priv, power_domain);
3604
c8c8fb33 3605 intel_runtime_pm_put(dev_priv);
671dedd2 3606
c8c8fb33 3607 return status;
a4fc5ed6
KP		 3608}
3609
3610static int intel_dp_get_modes(struct drm_connector *connector)
3611{
df0e9248 3612 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3613 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3614 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3615 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3616 struct drm_device *dev = connector->dev;
671dedd2
ID		 3617 struct drm_i915_private *dev_priv = dev->dev_private;
3618 enum intel_display_power_domain power_domain;
32f9d658 3619 int ret;
a4fc5ed6
KP		 3620
3621 /* We should parse the EDID data and find out if it has an audio sink
3622 */
3623
671dedd2
ID		 3624 power_domain = intel_display_port_power_domain(intel_encoder);
3625 intel_display_power_get(dev_priv, power_domain);
3626
0b99836f 3627 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3628 intel_display_power_put(dev_priv, power_domain);
f8779fda 3629 if (ret)
32f9d658
ZW		 3630 return ret;
3631
f8779fda 3632 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3633 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3634 struct drm_display_mode *mode;
dd06f90e
JN		 3635 mode = drm_mode_duplicate(dev,
3636 intel_connector->panel.fixed_mode);
f8779fda 3637 if (mode) {
32f9d658
ZW		 3638 drm_mode_probed_add(connector, mode);
3639 return 1;
3640 }
3641 }
3642 return 0;
a4fc5ed6
KP		 3643}
3644
1aad7ac0
CW		 3645static bool
3646intel_dp_detect_audio(struct drm_connector *connector)
3647{
3648 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3649 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3650 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3651 struct drm_device *dev = connector->dev;
3652 struct drm_i915_private *dev_priv = dev->dev_private;
3653 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3654 struct edid *edid;
3655 bool has_audio = false;
3656
671dedd2
ID		 3657 power_domain = intel_display_port_power_domain(intel_encoder);
3658 intel_display_power_get(dev_priv, power_domain);
3659
0b99836f 3660 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3661 if (edid) {
3662 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3663 kfree(edid);
3664 }
3665
671dedd2
ID		 3666 intel_display_power_put(dev_priv, power_domain);
3667
1aad7ac0
CW		 3668 return has_audio;
3669}
3670
f684960e
CW		 3671static int
3672intel_dp_set_property(struct drm_connector *connector,
3673 struct drm_property *property,
3674 uint64_t val)
3675{
e953fd7b 3676 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3677 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3678 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3679 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3680 int ret;
3681
662595df 3682 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3683 if (ret)
3684 return ret;
3685
3f43c48d 3686 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3687 int i = val;
3688 bool has_audio;
3689
3690 if (i == intel_dp->force_audio)
f684960e
CW		 3691 return 0;
3692
1aad7ac0 3693 intel_dp->force_audio = i;
f684960e 3694
c3e5f67b 3695 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3696 has_audio = intel_dp_detect_audio(connector);
3697 else
c3e5f67b 3698 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3699
3700 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3701 return 0;
3702
1aad7ac0 3703 intel_dp->has_audio = has_audio;
f684960e
CW		 3704 goto done;
3705 }
3706
e953fd7b 3707 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3708 bool old_auto = intel_dp->color_range_auto;
3709 uint32_t old_range = intel_dp->color_range;
3710
55bc60db
VS		 3711 switch (val) {
3712 case INTEL_BROADCAST_RGB_AUTO:
3713 intel_dp->color_range_auto = true;
3714 break;
3715 case INTEL_BROADCAST_RGB_FULL:
3716 intel_dp->color_range_auto = false;
3717 intel_dp->color_range = 0;
3718 break;
3719 case INTEL_BROADCAST_RGB_LIMITED:
3720 intel_dp->color_range_auto = false;
3721 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3722 break;
3723 default:
3724 return -EINVAL;
3725 }
ae4edb80
DV		 3726
3727 if (old_auto == intel_dp->color_range_auto &&
3728 old_range == intel_dp->color_range)
3729 return 0;
3730
e953fd7b
CW		 3731 goto done;
3732 }
3733
53b41837
YN		 3734 if (is_edp(intel_dp) &&
3735 property == connector->dev->mode_config.scaling_mode_property) {
3736 if (val == DRM_MODE_SCALE_NONE) {
3737 DRM_DEBUG_KMS("no scaling not supported\n");
3738 return -EINVAL;
3739 }
3740
3741 if (intel_connector->panel.fitting_mode == val) {
3742 /* the eDP scaling property is not changed */
3743 return 0;
3744 }
3745 intel_connector->panel.fitting_mode = val;
3746
3747 goto done;
3748 }
3749
f684960e
CW		 3750 return -EINVAL;
3751
3752done:
c0c36b94
CW		 3753 if (intel_encoder->base.crtc)
3754 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3755
3756 return 0;
3757}
3758
a4fc5ed6 3759static void
73845adf 3760intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3761{
1d508706 3762 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3763
9cd300e0
JN		 3764 if (!IS_ERR_OR_NULL(intel_connector->edid))
3765 kfree(intel_connector->edid);
3766
acd8db10
PZ		 3767 /* Can't call is_edp() since the encoder may have been destroyed
3768 * already. */
3769 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3770 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3771
a4fc5ed6 3772 drm_connector_cleanup(connector);
55f78c43 3773 kfree(connector);
a4fc5ed6
KP		 3774}
3775
00c09d70 3776void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3777{
da63a9f2
PZ		 3778 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3779 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3780 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3781
4f71d0cb 3782 drm_dp_aux_unregister(&intel_dp->aux);
24d05927 3783 drm_encoder_cleanup(encoder);
bd943159
KP		 3784 if (is_edp(intel_dp)) {
3785 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 3786 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 3787 edp_panel_vdd_off_sync(intel_dp);
51fd371b 3788 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159 3789 }
da63a9f2 3790 kfree(intel_dig_port);
24d05927
DV		 3791}
3792
a4fc5ed6 3793static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3794 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3795 .detect = intel_dp_detect,
3796 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3797 .set_property = intel_dp_set_property,
73845adf 3798 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3799};
3800
3801static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3802 .get_modes = intel_dp_get_modes,
3803 .mode_valid = intel_dp_mode_valid,
df0e9248 3804 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3805};
3806
a4fc5ed6 3807static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3808 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3809};
3810
995b6762 3811static void
21d40d37 3812intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3813{
fa90ecef 3814 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3815
885a5014 3816 intel_dp_check_link_status(intel_dp);
c8110e52 3817}
6207937d 3818
13cf5504
DA		 3819bool
3820intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
3821{
3822 struct intel_dp *intel_dp = &intel_dig_port->dp;
3823
3824 if (long_hpd)
3825 return true;
3826
3827 /*
3828 * we'll check the link status via the normal hot plug path later -
3829 * but for short hpds we should check it now
3830 */
3831 intel_dp_check_link_status(intel_dp);
3832 return false;
3833}
3834
e3421a18
ZW		 3835/* Return which DP Port should be selected for Transcoder DP control */
3836int
0206e353 3837intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3838{
3839 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3840 struct intel_encoder *intel_encoder;
3841 struct intel_dp *intel_dp;
e3421a18 3842
fa90ecef
PZ		 3843 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3844 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3845
fa90ecef
PZ		 3846 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3847 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3848 return intel_dp->output_reg;
e3421a18 3849 }
ea5b213a 3850
e3421a18
ZW		 3851 return -1;
3852}
3853
36e83a18 3854/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3855bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3856{
3857 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3858 union child_device_config *p_child;
36e83a18 3859 int i;
5d8a7752
VS		 3860 static const short port_mapping[] = {
3861 [PORT_B] = PORT_IDPB,
3862 [PORT_C] = PORT_IDPC,
3863 [PORT_D] = PORT_IDPD,
3864 };
36e83a18 3865
3b32a35b
VS		 3866 if (port == PORT_A)
3867 return true;
3868
41aa3448 3869 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3870 return false;
3871
41aa3448
RV		 3872 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3873 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3874
5d8a7752 3875 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3876 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3877 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3878 return true;
3879 }
3880 return false;
3881}
3882
f684960e
CW		 3883static void
3884intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3885{
53b41837
YN		 3886 struct intel_connector *intel_connector = to_intel_connector(connector);
3887
3f43c48d 3888 intel_attach_force_audio_property(connector);
e953fd7b 3889 intel_attach_broadcast_rgb_property(connector);
55bc60db 3890 intel_dp->color_range_auto = true;
53b41837
YN		 3891
3892 if (is_edp(intel_dp)) {
3893 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3894 drm_object_attach_property(
3895 &connector->base,
53b41837 3896 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3897 DRM_MODE_SCALE_ASPECT);
3898 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3899 }
f684960e
CW		 3900}
3901
dada1a9f
ID		 3902static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3903{
3904 intel_dp->last_power_cycle = jiffies;
3905 intel_dp->last_power_on = jiffies;
3906 intel_dp->last_backlight_off = jiffies;
3907}
3908
67a54566
DV		 3909static void
3910intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3911 struct intel_dp *intel_dp,
3912 struct edp_power_seq *out)
67a54566
DV		 3913{
3914 struct drm_i915_private *dev_priv = dev->dev_private;
3915 struct edp_power_seq cur, vbt, spec, final;
3916 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3917 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3918
3919 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3920 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3921 pp_on_reg = PCH_PP_ON_DELAYS;
3922 pp_off_reg = PCH_PP_OFF_DELAYS;
3923 pp_div_reg = PCH_PP_DIVISOR;
3924 } else {
bf13e81b
JN		 3925 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3926
3927 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3928 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3929 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3930 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3931 }
67a54566
DV		 3932
3933 /* Workaround: Need to write PP_CONTROL with the unlock key as
3934 * the very first thing. */
453c5420 3935 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3936 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3937
453c5420
JB		 3938 pp_on = I915_READ(pp_on_reg);
3939 pp_off = I915_READ(pp_off_reg);
3940 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3941
3942 /* Pull timing values out of registers */
3943 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3944 PANEL_POWER_UP_DELAY_SHIFT;
3945
3946 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3947 PANEL_LIGHT_ON_DELAY_SHIFT;
3948
3949 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3950 PANEL_LIGHT_OFF_DELAY_SHIFT;
3951
3952 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3953 PANEL_POWER_DOWN_DELAY_SHIFT;
3954
3955 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3956 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3957
3958 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3959 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3960
41aa3448 3961 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3962
3963 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3964 * our hw here, which are all in 100usec. */
3965 spec.t1_t3 = 210 * 10;
3966 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3967 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3968 spec.t10 = 500 * 10;
3969 /* This one is special and actually in units of 100ms, but zero
3970 * based in the hw (so we need to add 100 ms). But the sw vbt
3971 * table multiplies it with 1000 to make it in units of 100usec,
3972 * too. */
3973 spec.t11_t12 = (510 + 100) * 10;
3974
3975 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3976 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3977
3978 /* Use the max of the register settings and vbt. If both are
3979 * unset, fall back to the spec limits. */
3980#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3981 spec.field : \
3982 max(cur.field, vbt.field))
3983 assign_final(t1_t3);
3984 assign_final(t8);
3985 assign_final(t9);
3986 assign_final(t10);
3987 assign_final(t11_t12);
3988#undef assign_final
3989
3990#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3991 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3992 intel_dp->backlight_on_delay = get_delay(t8);
3993 intel_dp->backlight_off_delay = get_delay(t9);
3994 intel_dp->panel_power_down_delay = get_delay(t10);
3995 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3996#undef get_delay
3997
f30d26e4
JN		 3998 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3999 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4000 intel_dp->panel_power_cycle_delay);
4001
4002 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4003 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4004
4005 if (out)
4006 *out = final;
4007}
4008
4009static void
4010intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4011 struct intel_dp *intel_dp,
4012 struct edp_power_seq *seq)
4013{
4014 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4015 u32 pp_on, pp_off, pp_div, port_sel = 0;
4016 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4017 int pp_on_reg, pp_off_reg, pp_div_reg;
4018
4019 if (HAS_PCH_SPLIT(dev)) {
4020 pp_on_reg = PCH_PP_ON_DELAYS;
4021 pp_off_reg = PCH_PP_OFF_DELAYS;
4022 pp_div_reg = PCH_PP_DIVISOR;
4023 } else {
bf13e81b
JN		 4024 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4025
4026 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4027 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4028 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4029 }
4030
b2f19d1a
PZ		 4031 /*
4032 * And finally store the new values in the power sequencer. The
4033 * backlight delays are set to 1 because we do manual waits on them. For
4034 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4035 * we'll end up waiting for the backlight off delay twice: once when we
4036 * do the manual sleep, and once when we disable the panel and wait for
4037 * the PP_STATUS bit to become zero.
4038 */
f30d26e4 4039 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4040 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4041 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4042 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4043 /* Compute the divisor for the pp clock, simply match the Bspec
4044 * formula. */
453c5420 4045 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4046 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4047 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4048
4049 /* Haswell doesn't have any port selection bits for the panel
4050 * power sequencer any more. */
bc7d38a4 4051 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 4052 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4053 port_sel = PANEL_PORT_SELECT_DPB_VLV;
4054 else
4055 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 4056 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4057 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 4058 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4059 else
a24c144c 4060 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4061 }
4062
453c5420
JB		 4063 pp_on |= port_sel;
4064
4065 I915_WRITE(pp_on_reg, pp_on);
4066 I915_WRITE(pp_off_reg, pp_off);
4067 I915_WRITE(pp_div_reg, pp_div);
67a54566 4068
67a54566 4069 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4070 I915_READ(pp_on_reg),
4071 I915_READ(pp_off_reg),
4072 I915_READ(pp_div_reg));
f684960e
CW		 4073}
4074
439d7ac0
PB		 4075void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4076{
4077 struct drm_i915_private *dev_priv = dev->dev_private;
4078 struct intel_encoder *encoder;
4079 struct intel_dp *intel_dp = NULL;
4080 struct intel_crtc_config *config = NULL;
4081 struct intel_crtc *intel_crtc = NULL;
4082 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4083 u32 reg, val;
4084 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4085
4086 if (refresh_rate <= 0) {
4087 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4088 return;
4089 }
4090
4091 if (intel_connector == NULL) {
4092 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4093 return;
4094 }
4095
4096 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4097 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4098 return;
4099 }
4100
4101 encoder = intel_attached_encoder(&intel_connector->base);
4102 intel_dp = enc_to_intel_dp(&encoder->base);
4103 intel_crtc = encoder->new_crtc;
4104
4105 if (!intel_crtc) {
4106 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4107 return;
4108 }
4109
4110 config = &intel_crtc->config;
4111
4112 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4113 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4114 return;
4115 }
4116
4117 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4118 index = DRRS_LOW_RR;
4119
4120 if (index == intel_dp->drrs_state.refresh_rate_type) {
4121 DRM_DEBUG_KMS(
4122 "DRRS requested for previously set RR...ignoring\n");
4123 return;
4124 }
4125
4126 if (!intel_crtc->active) {
4127 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4128 return;
4129 }
4130
4131 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4132 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4133 val = I915_READ(reg);
4134 if (index > DRRS_HIGH_RR) {
4135 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4136 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
4137 } else {
4138 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4139 }
4140 I915_WRITE(reg, val);
4141 }
4142
4143 /*
4144 * mutex taken to ensure that there is no race between differnt
4145 * drrs calls trying to update refresh rate. This scenario may occur
4146 * in future when idleness detection based DRRS in kernel and
4147 * possible calls from user space to set differnt RR are made.
4148 */
4149
4150 mutex_lock(&intel_dp->drrs_state.mutex);
4151
4152 intel_dp->drrs_state.refresh_rate_type = index;
4153
4154 mutex_unlock(&intel_dp->drrs_state.mutex);
4155
4156 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4157}
4158
4f9db5b5
PB		 4159static struct drm_display_mode *
4160intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4161 struct intel_connector *intel_connector,
4162 struct drm_display_mode *fixed_mode)
4163{
4164 struct drm_connector *connector = &intel_connector->base;
4165 struct intel_dp *intel_dp = &intel_dig_port->dp;
4166 struct drm_device *dev = intel_dig_port->base.base.dev;
4167 struct drm_i915_private *dev_priv = dev->dev_private;
4168 struct drm_display_mode *downclock_mode = NULL;
4169
4170 if (INTEL_INFO(dev)->gen <= 6) {
4171 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4172 return NULL;
4173 }
4174
4175 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4176 DRM_INFO("VBT doesn't support DRRS\n");
4177 return NULL;
4178 }
4179
4180 downclock_mode = intel_find_panel_downclock
4181 (dev, fixed_mode, connector);
4182
4183 if (!downclock_mode) {
4184 DRM_INFO("DRRS not supported\n");
4185 return NULL;
4186 }
4187
439d7ac0
PB		 4188 dev_priv->drrs.connector = intel_connector;
4189
4190 mutex_init(&intel_dp->drrs_state.mutex);
4191
4f9db5b5
PB		 4192 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4193
4194 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4195 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4196 return downclock_mode;
4197}
4198
ed92f0b2 4199static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4200 struct intel_connector *intel_connector,
4201 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4202{
4203 struct drm_connector *connector = &intel_connector->base;
4204 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4205 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4206 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4207 struct drm_i915_private *dev_priv = dev->dev_private;
4208 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4209 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4210 bool has_dpcd;
4211 struct drm_display_mode *scan;
4212 struct edid *edid;
4213
4f9db5b5
PB		 4214 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4215
ed92f0b2
PZ		 4216 if (!is_edp(intel_dp))
4217 return true;
4218
63635217
PZ		 4219 /* The VDD bit needs a power domain reference, so if the bit is already
4220 * enabled when we boot, grab this reference. */
4221 if (edp_have_panel_vdd(intel_dp)) {
4222 enum intel_display_power_domain power_domain;
4223 power_domain = intel_display_port_power_domain(intel_encoder);
4224 intel_display_power_get(dev_priv, power_domain);
4225 }
4226
ed92f0b2 4227 /* Cache DPCD and EDID for edp. */
24f3e092 4228 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4229 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 4230 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4231
4232 if (has_dpcd) {
4233 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4234 dev_priv->no_aux_handshake =
4235 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4236 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4237 } else {
4238 /* if this fails, presume the device is a ghost */
4239 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4240 return false;
4241 }
4242
4243 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4244 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4245
060c8778 4246 mutex_lock(&dev->mode_config.mutex);
0b99836f 4247 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4248 if (edid) {
4249 if (drm_add_edid_modes(connector, edid)) {
4250 drm_mode_connector_update_edid_property(connector,
4251 edid);
4252 drm_edid_to_eld(connector, edid);
4253 } else {
4254 kfree(edid);
4255 edid = ERR_PTR(-EINVAL);
4256 }
4257 } else {
4258 edid = ERR_PTR(-ENOENT);
4259 }
4260 intel_connector->edid = edid;
4261
4262 /* prefer fixed mode from EDID if available */
4263 list_for_each_entry(scan, &connector->probed_modes, head) {
4264 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4265 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4266 downclock_mode = intel_dp_drrs_init(
4267 intel_dig_port,
4268 intel_connector, fixed_mode);
ed92f0b2
PZ		 4269 break;
4270 }
4271 }
4272
4273 /* fallback to VBT if available for eDP */
4274 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4275 fixed_mode = drm_mode_duplicate(dev,
4276 dev_priv->vbt.lfp_lvds_vbt_mode);
4277 if (fixed_mode)
4278 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4279 }
060c8778 4280 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4281
4f9db5b5 4282 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
ed92f0b2
PZ		 4283 intel_panel_setup_backlight(connector);
4284
4285 return true;
4286}
4287
16c25533 4288bool
f0fec3f2
PZ		 4289intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4290 struct intel_connector *intel_connector)
a4fc5ed6 4291{
f0fec3f2
PZ		 4292 struct drm_connector *connector = &intel_connector->base;
4293 struct intel_dp *intel_dp = &intel_dig_port->dp;
4294 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4295 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4296 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4297 enum port port = intel_dig_port->port;
0095e6dc 4298 struct edp_power_seq power_seq = { 0 };
0b99836f 4299 int type;
a4fc5ed6 4300
ec5b01dd
DL		 4301 /* intel_dp vfuncs */
4302 if (IS_VALLEYVIEW(dev))
4303 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4304 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4305 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4306 else if (HAS_PCH_SPLIT(dev))
4307 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4308 else
4309 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4310
153b1100
DL		 4311 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4312
0767935e
DV		 4313 /* Preserve the current hw state. */
4314 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4315 intel_dp->attached_connector = intel_connector;
3d3dc149 4316
3b32a35b 4317 if (intel_dp_is_edp(dev, port))
b329530c 4318 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4319 else
4320 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4321
f7d24902
ID		 4322 /*
4323 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4324 * for DP the encoder type can be set by the caller to
4325 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4326 */
4327 if (type == DRM_MODE_CONNECTOR_eDP)
4328 intel_encoder->type = INTEL_OUTPUT_EDP;
4329
e7281eab
ID		 4330 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4331 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4332 port_name(port));
4333
b329530c 4334 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4335 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4336
a4fc5ed6
KP		 4337 connector->interlace_allowed = true;
4338 connector->doublescan_allowed = 0;
4339
f0fec3f2 4340 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4341 edp_panel_vdd_work);
a4fc5ed6 4342
df0e9248 4343 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 4344 drm_sysfs_connector_add(connector);
4345
affa9354 4346 if (HAS_DDI(dev))
bcbc889b
PZ		 4347 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4348 else
4349 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4350 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4351
0b99836f 4352 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4353 switch (port) {
4354 case PORT_A:
1d843f9d 4355 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4356 break;
4357 case PORT_B:
1d843f9d 4358 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4359 break;
4360 case PORT_C:
1d843f9d 4361 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4362 break;
4363 case PORT_D:
1d843f9d 4364 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4365 break;
4366 default:
ad1c0b19 4367 BUG();
5eb08b69
ZW		 4368 }
4369
dada1a9f
ID		 4370 if (is_edp(intel_dp)) {
4371 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4372 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4373 }
0095e6dc 4374
9d1a1031 4375 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4376
0095e6dc 4377 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4378 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4379 if (is_edp(intel_dp)) {
4380 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4381 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4382 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4383 drm_modeset_unlock(&dev->mode_config.connection_mutex);
15b1d171 4384 }
b2f246a8
PZ		 4385 drm_sysfs_connector_remove(connector);
4386 drm_connector_cleanup(connector);
16c25533 4387 return false;
b2f246a8 4388 }
32f9d658 4389
f684960e
CW		 4390 intel_dp_add_properties(intel_dp, connector);
4391
a4fc5ed6
KP		 4392 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4393 * 0xd. Failure to do so will result in spurious interrupts being
4394 * generated on the port when a cable is not attached.
4395 */
4396 if (IS_G4X(dev) && !IS_GM45(dev)) {
4397 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4398 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4399 }
16c25533
PZ		 4400
4401 return true;
a4fc5ed6 4402}
f0fec3f2
PZ		 4403
4404void
4405intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4406{
13cf5504 4407 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 4408 struct intel_digital_port *intel_dig_port;
4409 struct intel_encoder *intel_encoder;
4410 struct drm_encoder *encoder;
4411 struct intel_connector *intel_connector;
4412
b14c5679 4413 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4414 if (!intel_dig_port)
4415 return;
4416
b14c5679 4417 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4418 if (!intel_connector) {
4419 kfree(intel_dig_port);
4420 return;
4421 }
4422
4423 intel_encoder = &intel_dig_port->base;
4424 encoder = &intel_encoder->base;
4425
4426 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4427 DRM_MODE_ENCODER_TMDS);
4428
5bfe2ac0 4429 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4430 intel_encoder->disable = intel_disable_dp;
00c09d70 4431 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4432 intel_encoder->get_config = intel_dp_get_config;
e4a1d846 4433 if (IS_CHERRYVIEW(dev)) {
9197c88b 4434 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 4435 intel_encoder->pre_enable = chv_pre_enable_dp;
4436 intel_encoder->enable = vlv_enable_dp;
580d3811 4437 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4438 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4439 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4440 intel_encoder->pre_enable = vlv_pre_enable_dp;
4441 intel_encoder->enable = vlv_enable_dp;
49277c31 4442 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4443 } else {
ecff4f3b
JN		 4444 intel_encoder->pre_enable = g4x_pre_enable_dp;
4445 intel_encoder->enable = g4x_enable_dp;
49277c31 4446 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4447 }
f0fec3f2 4448
174edf1f 4449 intel_dig_port->port = port;
f0fec3f2
PZ		 4450 intel_dig_port->dp.output_reg = output_reg;
4451
00c09d70 4452 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4453 if (IS_CHERRYVIEW(dev)) {
4454 if (port == PORT_D)
4455 intel_encoder->crtc_mask = 1 << 2;
4456 else
4457 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4458 } else {
4459 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4460 }
bc079e8b 4461 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4462 intel_encoder->hot_plug = intel_dp_hot_plug;
4463
13cf5504
DA		 4464 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4465 dev_priv->hpd_irq_port[port] = intel_dig_port;
4466
15b1d171
PZ		 4467 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4468 drm_encoder_cleanup(encoder);
4469 kfree(intel_dig_port);
b2f246a8 4470 kfree(intel_connector);
15b1d171 4471 }
f0fec3f2 4472}
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