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Revert "drm/i915: fix infinite loop at gen6_update_ring_freq"
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 94static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 95static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 96
a4fc5ed6 97static int
ea5b213a 98intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 99{
7183dc29 100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 101 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 102
103 switch (max_link_bw) {
104 case DP_LINK_BW_1_62:
105 case DP_LINK_BW_2_7:
106 break;
d4eead50 107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
110 max_link_bw = DP_LINK_BW_5_4;
111 else
112 max_link_bw = DP_LINK_BW_2_7;
d4eead50 113 break;
a4fc5ed6 114 default:
d4eead50
ID		 115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
116 max_link_bw);
a4fc5ed6
KP		 117 max_link_bw = DP_LINK_BW_1_62;
118 break;
119 }
120 return max_link_bw;
121}
122
cd9dde44
AJ		 123/*
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
126 *
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
128 *
129 * 270000 * 1 * 8 / 10 == 216000
130 *
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
135 *
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
138 */
139
a4fc5ed6 140static int
c898261c 141intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 142{
cd9dde44 143 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 144}
145
fe27d53e
DA		 146static int
147intel_dp_max_data_rate(int max_link_clock, int max_lanes)
148{
149 return (max_link_clock * max_lanes * 8) / 10;
150}
151
c19de8eb 152static enum drm_mode_status
a4fc5ed6
KP		 153intel_dp_mode_valid(struct drm_connector *connector,
154 struct drm_display_mode *mode)
155{
df0e9248 156 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 157 struct intel_connector *intel_connector = to_intel_connector(connector);
158 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 159 int target_clock = mode->clock;
160 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 161
dd06f90e
JN		 162 if (is_edp(intel_dp) && fixed_mode) {
163 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 164 return MODE_PANEL;
165
dd06f90e 166 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 167 return MODE_PANEL;
03afc4a2
DV		 168
169 target_clock = fixed_mode->clock;
7de56f43
ZY		 170 }
171
36008365
DV		 172 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
173 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
174
175 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
176 mode_rate = intel_dp_link_required(target_clock, 18);
177
178 if (mode_rate > max_rate)
c4867936 179 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 180
181 if (mode->clock < 10000)
182 return MODE_CLOCK_LOW;
183
0af78a2b
DV		 184 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
185 return MODE_H_ILLEGAL;
186
a4fc5ed6
KP		 187 return MODE_OK;
188}
189
190static uint32_t
191pack_aux(uint8_t *src, int src_bytes)
192{
193 int i;
194 uint32_t v = 0;
195
196 if (src_bytes > 4)
197 src_bytes = 4;
198 for (i = 0; i < src_bytes; i++)
199 v |= ((uint32_t) src[i]) << ((3-i) * 8);
200 return v;
201}
202
203static void
204unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
205{
206 int i;
207 if (dst_bytes > 4)
208 dst_bytes = 4;
209 for (i = 0; i < dst_bytes; i++)
210 dst[i] = src >> ((3-i) * 8);
211}
212
fb0f8fbf
KP		 213/* hrawclock is 1/4 the FSB frequency */
214static int
215intel_hrawclk(struct drm_device *dev)
216{
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 uint32_t clkcfg;
219
9473c8f4
VP		 220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev))
222 return 200;
223
fb0f8fbf
KP		 224 clkcfg = I915_READ(CLKCFG);
225 switch (clkcfg & CLKCFG_FSB_MASK) {
226 case CLKCFG_FSB_400:
227 return 100;
228 case CLKCFG_FSB_533:
229 return 133;
230 case CLKCFG_FSB_667:
231 return 166;
232 case CLKCFG_FSB_800:
233 return 200;
234 case CLKCFG_FSB_1067:
235 return 266;
236 case CLKCFG_FSB_1333:
237 return 333;
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600:
240 case CLKCFG_FSB_1600_ALT:
241 return 400;
242 default:
243 return 133;
244 }
245}
246
bf13e81b
JN		 247static void
248intel_dp_init_panel_power_sequencer(struct drm_device *dev,
249 struct intel_dp *intel_dp,
250 struct edp_power_seq *out);
251static void
252intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
253 struct intel_dp *intel_dp,
254 struct edp_power_seq *out);
255
256static enum pipe
257vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
258{
259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
261 struct drm_device *dev = intel_dig_port->base.base.dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 enum port port = intel_dig_port->port;
264 enum pipe pipe;
265
266 /* modeset should have pipe */
267 if (crtc)
268 return to_intel_crtc(crtc)->pipe;
269
270 /* init time, try to find a pipe with this port selected */
271 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
272 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
273 PANEL_PORT_SELECT_MASK;
274 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
275 return pipe;
276 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
277 return pipe;
278 }
279
280 /* shrug */
281 return PIPE_A;
282}
283
284static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
285{
286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
287
288 if (HAS_PCH_SPLIT(dev))
289 return PCH_PP_CONTROL;
290 else
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
292}
293
294static u32 _pp_stat_reg(struct intel_dp *intel_dp)
295{
296 struct drm_device *dev = intel_dp_to_dev(intel_dp);
297
298 if (HAS_PCH_SPLIT(dev))
299 return PCH_PP_STATUS;
300 else
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
302}
303
4be73780 304static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 305{
30add22d 306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 307 struct drm_i915_private *dev_priv = dev->dev_private;
308
bf13e81b 309 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 310}
311
4be73780 312static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 313{
30add22d 314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 315 struct drm_i915_private *dev_priv = dev->dev_private;
316
efbc20ab
PZ		 317 return !dev_priv->pm.suspended &&
318 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 319}
320
9b984dae
KP		 321static void
322intel_dp_check_edp(struct intel_dp *intel_dp)
323{
30add22d 324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 325 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 326
9b984dae
KP		 327 if (!is_edp(intel_dp))
328 return;
453c5420 329
4be73780 330 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 331 WARN(1, "eDP powered off while attempting aux channel communication.\n");
332 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 333 I915_READ(_pp_stat_reg(intel_dp)),
334 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 335 }
336}
337
9ee32fea
DV		 338static uint32_t
339intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
340{
341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
342 struct drm_device *dev = intel_dig_port->base.base.dev;
343 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 344 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 345 uint32_t status;
346 bool done;
347
ef04f00d 348#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 349 if (has_aux_irq)
b18ac466 350 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 351 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 352 else
353 done = wait_for_atomic(C, 10) == 0;
354 if (!done)
355 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
356 has_aux_irq);
357#undef C
358
359 return status;
360}
361
ec5b01dd 362static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 363{
174edf1f
PZ		 364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
365 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 366
ec5b01dd
DL		 367 /*
368 * The clock divider is based off the hrawclk, and would like to run at
369 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 370 */
ec5b01dd
DL		 371 return index ? 0 : intel_hrawclk(dev) / 2;
372}
373
374static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
375{
376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
377 struct drm_device *dev = intel_dig_port->base.base.dev;
378
379 if (index)
380 return 0;
381
382 if (intel_dig_port->port == PORT_A) {
383 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 384 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 385 else
b84a1cf8 386 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 387 } else {
388 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
389 }
390}
391
392static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
393{
394 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
395 struct drm_device *dev = intel_dig_port->base.base.dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397
398 if (intel_dig_port->port == PORT_A) {
399 if (index)
400 return 0;
401 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 402 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
403 /* Workaround for non-ULT HSW */
bc86625a
CW		 404 switch (index) {
405 case 0: return 63;
406 case 1: return 72;
407 default: return 0;
408 }
ec5b01dd 409 } else {
bc86625a 410 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 411 }
b84a1cf8
RV		 412}
413
ec5b01dd
DL		 414static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
415{
416 return index ? 0 : 100;
417}
418
5ed12a19
DL		 419static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
420 bool has_aux_irq,
421 int send_bytes,
422 uint32_t aux_clock_divider)
423{
424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
425 struct drm_device *dev = intel_dig_port->base.base.dev;
426 uint32_t precharge, timeout;
427
428 if (IS_GEN6(dev))
429 precharge = 3;
430 else
431 precharge = 5;
432
433 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
434 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
435 else
436 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
437
438 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 439 DP_AUX_CH_CTL_DONE |
5ed12a19 440 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 441 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 442 timeout |
788d4433 443 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 444 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
445 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 446 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 447}
448
b84a1cf8
RV		 449static int
450intel_dp_aux_ch(struct intel_dp *intel_dp,
451 uint8_t *send, int send_bytes,
452 uint8_t *recv, int recv_size)
453{
454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
455 struct drm_device *dev = intel_dig_port->base.base.dev;
456 struct drm_i915_private *dev_priv = dev->dev_private;
457 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
458 uint32_t ch_data = ch_ctl + 4;
bc86625a 459 uint32_t aux_clock_divider;
b84a1cf8
RV		 460 int i, ret, recv_bytes;
461 uint32_t status;
5ed12a19 462 int try, clock = 0;
4e6b788c 463 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 464 bool vdd;
465
466 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 467
468 /* dp aux is extremely sensitive to irq latency, hence request the
469 * lowest possible wakeup latency and so prevent the cpu from going into
470 * deep sleep states.
471 */
472 pm_qos_update_request(&dev_priv->pm_qos, 0);
473
474 intel_dp_check_edp(intel_dp);
5eb08b69 475
c67a470b
PZ		 476 intel_aux_display_runtime_get(dev_priv);
477
11bee43e
JB		 478 /* Try to wait for any previous AUX channel activity */
479 for (try = 0; try < 3; try++) {
ef04f00d 480 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 481 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
482 break;
483 msleep(1);
484 }
485
486 if (try == 3) {
487 WARN(1, "dp_aux_ch not started status 0x%08x\n",
488 I915_READ(ch_ctl));
9ee32fea
DV		 489 ret = -EBUSY;
490 goto out;
4f7f7b7e
CW		 491 }
492
46a5ae9f
PZ		 493 /* Only 5 data registers! */
494 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
495 ret = -E2BIG;
496 goto out;
497 }
498
ec5b01dd 499 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 500 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
501 has_aux_irq,
502 send_bytes,
503 aux_clock_divider);
5ed12a19 504
bc86625a
CW		 505 /* Must try at least 3 times according to DP spec */
506 for (try = 0; try < 5; try++) {
507 /* Load the send data into the aux channel data registers */
508 for (i = 0; i < send_bytes; i += 4)
509 I915_WRITE(ch_data + i,
510 pack_aux(send + i, send_bytes - i));
511
512 /* Send the command and wait for it to complete */
5ed12a19 513 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 514
515 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
516
517 /* Clear done status and any errors */
518 I915_WRITE(ch_ctl,
519 status |
520 DP_AUX_CH_CTL_DONE |
521 DP_AUX_CH_CTL_TIME_OUT_ERROR |
522 DP_AUX_CH_CTL_RECEIVE_ERROR);
523
524 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
525 DP_AUX_CH_CTL_RECEIVE_ERROR))
526 continue;
527 if (status & DP_AUX_CH_CTL_DONE)
528 break;
529 }
4f7f7b7e 530 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 531 break;
532 }
533
a4fc5ed6 534 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 535 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 536 ret = -EBUSY;
537 goto out;
a4fc5ed6
KP		 538 }
539
540 /* Check for timeout or receive error.
541 * Timeouts occur when the sink is not connected
542 */
a5b3da54 543 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 544 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 545 ret = -EIO;
546 goto out;
a5b3da54 547 }
1ae8c0a5
KP		 548
549 /* Timeouts occur when the device isn't connected, so they're
550 * "normal" -- don't fill the kernel log with these */
a5b3da54 551 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 552 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 553 ret = -ETIMEDOUT;
554 goto out;
a4fc5ed6
KP		 555 }
556
557 /* Unload any bytes sent back from the other side */
558 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
559 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 560 if (recv_bytes > recv_size)
561 recv_bytes = recv_size;
0206e353 562
4f7f7b7e
CW		 563 for (i = 0; i < recv_bytes; i += 4)
564 unpack_aux(I915_READ(ch_data + i),
565 recv + i, recv_bytes - i);
a4fc5ed6 566
9ee32fea
DV		 567 ret = recv_bytes;
568out:
569 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 570 intel_aux_display_runtime_put(dev_priv);
9ee32fea 571
884f19e9
JN		 572 if (vdd)
573 edp_panel_vdd_off(intel_dp, false);
574
9ee32fea 575 return ret;
a4fc5ed6
KP		 576}
577
9d1a1031
JN		 578#define HEADER_SIZE 4
579static ssize_t
580intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 581{
9d1a1031
JN		 582 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
583 uint8_t txbuf[20], rxbuf[20];
584 size_t txsize, rxsize;
a4fc5ed6 585 int ret;
a4fc5ed6 586
9d1a1031
JN		 587 txbuf[0] = msg->request << 4;
588 txbuf[1] = msg->address >> 8;
589 txbuf[2] = msg->address & 0xff;
590 txbuf[3] = msg->size - 1;
46a5ae9f 591
9d1a1031
JN		 592 switch (msg->request & ~DP_AUX_I2C_MOT) {
593 case DP_AUX_NATIVE_WRITE:
594 case DP_AUX_I2C_WRITE:
595 txsize = HEADER_SIZE + msg->size;
596 rxsize = 1;
f51a44b9 597
9d1a1031
JN		 598 if (WARN_ON(txsize > 20))
599 return -E2BIG;
a4fc5ed6 600
9d1a1031 601 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 602
9d1a1031
JN		 603 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
604 if (ret > 0) {
605 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 606
9d1a1031
JN		 607 /* Return payload size. */
608 ret = msg->size;
609 }
610 break;
46a5ae9f 611
9d1a1031
JN		 612 case DP_AUX_NATIVE_READ:
613 case DP_AUX_I2C_READ:
614 txsize = HEADER_SIZE;
615 rxsize = msg->size + 1;
a4fc5ed6 616
9d1a1031
JN		 617 if (WARN_ON(rxsize > 20))
618 return -E2BIG;
a4fc5ed6 619
9d1a1031
JN		 620 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
621 if (ret > 0) {
622 msg->reply = rxbuf[0] >> 4;
623 /*
624 * Assume happy day, and copy the data. The caller is
625 * expected to check msg->reply before touching it.
626 *
627 * Return payload size.
628 */
629 ret--;
630 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 631 }
9d1a1031
JN		 632 break;
633
634 default:
635 ret = -EINVAL;
636 break;
a4fc5ed6 637 }
f51a44b9 638
9d1a1031 639 return ret;
a4fc5ed6
KP		 640}
641
9d1a1031
JN		 642static void
643intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
644{
645 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 646 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
647 enum port port = intel_dig_port->port;
0b99836f 648 const char *name = NULL;
ab2c0672
DA		 649 int ret;
650
33ad6626
JN		 651 switch (port) {
652 case PORT_A:
653 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 654 name = "DPDDC-A";
ab2c0672 655 break;
33ad6626
JN		 656 case PORT_B:
657 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 658 name = "DPDDC-B";
ab2c0672 659 break;
33ad6626
JN		 660 case PORT_C:
661 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 662 name = "DPDDC-C";
ab2c0672 663 break;
33ad6626
JN		 664 case PORT_D:
665 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 666 name = "DPDDC-D";
33ad6626
JN		 667 break;
668 default:
669 BUG();
ab2c0672
DA		 670 }
671
33ad6626
JN		 672 if (!HAS_DDI(dev))
673 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 674
0b99836f 675 intel_dp->aux.name = name;
9d1a1031
JN		 676 intel_dp->aux.dev = dev->dev;
677 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 678
0b99836f
JN		 679 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
680 connector->base.kdev->kobj.name);
8316f337 681
0b99836f
JN		 682 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
683 if (ret < 0) {
684 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
685 name, ret);
686 return;
ab2c0672 687 }
8a5e6aeb 688
0b99836f
JN		 689 ret = sysfs_create_link(&connector->base.kdev->kobj,
690 &intel_dp->aux.ddc.dev.kobj,
691 intel_dp->aux.ddc.dev.kobj.name);
692 if (ret < 0) {
693 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
694 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
ab2c0672 695 }
a4fc5ed6
KP		 696}
697
80f65de3
ID		 698static void
699intel_dp_connector_unregister(struct intel_connector *intel_connector)
700{
701 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
702
703 sysfs_remove_link(&intel_connector->base.kdev->kobj,
0b99836f 704 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 705 intel_connector_unregister(intel_connector);
706}
707
c6bb3538
DV		 708static void
709intel_dp_set_clock(struct intel_encoder *encoder,
710 struct intel_crtc_config *pipe_config, int link_bw)
711{
712 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 713 const struct dp_link_dpll *divisor = NULL;
714 int i, count = 0;
c6bb3538
DV		 715
716 if (IS_G4X(dev)) {
9dd4ffdf
CML		 717 divisor = gen4_dpll;
718 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 719 } else if (IS_HASWELL(dev)) {
720 /* Haswell has special-purpose DP DDI clocks. */
721 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 722 divisor = pch_dpll;
723 count = ARRAY_SIZE(pch_dpll);
c6bb3538 724 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 725 divisor = vlv_dpll;
726 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 727 }
9dd4ffdf
CML		 728
729 if (divisor && count) {
730 for (i = 0; i < count; i++) {
731 if (link_bw == divisor[i].link_bw) {
732 pipe_config->dpll = divisor[i].dpll;
733 pipe_config->clock_set = true;
734 break;
735 }
736 }
c6bb3538
DV		 737 }
738}
739
00c09d70 740bool
5bfe2ac0
DV		 741intel_dp_compute_config(struct intel_encoder *encoder,
742 struct intel_crtc_config *pipe_config)
a4fc5ed6 743{
5bfe2ac0 744 struct drm_device *dev = encoder->base.dev;
36008365 745 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 746 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 747 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 748 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 749 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 750 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 751 int lane_count, clock;
397fe157 752 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 753 /* Conveniently, the link BW constants become indices with a shift...*/
754 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 755 int bpp, mode_rate;
06ea66b6 756 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 757 int link_avail, link_clock;
a4fc5ed6 758
bc7d38a4 759 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 760 pipe_config->has_pch_encoder = true;
761
03afc4a2 762 pipe_config->has_dp_encoder = true;
a4fc5ed6 763
dd06f90e
JN		 764 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
765 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
766 adjusted_mode);
2dd24552
JB		 767 if (!HAS_PCH_SPLIT(dev))
768 intel_gmch_panel_fitting(intel_crtc, pipe_config,
769 intel_connector->panel.fitting_mode);
770 else
b074cec8
JB		 771 intel_pch_panel_fitting(intel_crtc, pipe_config,
772 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 773 }
774
cb1793ce 775 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 776 return false;
777
083f9560
DV		 778 DRM_DEBUG_KMS("DP link computation with max lane count %i "
779 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 780 max_lane_count, bws[max_clock],
781 adjusted_mode->crtc_clock);
083f9560 782
36008365
DV		 783 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
784 * bpc in between. */
3e7ca985 785 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 786 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
787 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 788 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
789 dev_priv->vbt.edp_bpp);
6da7f10d 790 bpp = dev_priv->vbt.edp_bpp;
7984211e 791 }
657445fe 792
36008365 793 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 794 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
795 bpp);
36008365 796
38aecea0
DV		 797 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
798 for (clock = 0; clock <= max_clock; clock++) {
36008365
DV		 799 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
800 link_avail = intel_dp_max_data_rate(link_clock,
801 lane_count);
802
803 if (mode_rate <= link_avail) {
804 goto found;
805 }
806 }
807 }
808 }
c4867936 809
36008365 810 return false;
3685a8f3 811
36008365 812found:
55bc60db
VS		 813 if (intel_dp->color_range_auto) {
814 /*
815 * See:
816 * CEA-861-E - 5.1 Default Encoding Parameters
817 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
818 */
18316c8c 819 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 820 intel_dp->color_range = DP_COLOR_RANGE_16_235;
821 else
822 intel_dp->color_range = 0;
823 }
824
3685a8f3 825 if (intel_dp->color_range)
50f3b016 826 pipe_config->limited_color_range = true;
a4fc5ed6 827
36008365
DV		 828 intel_dp->link_bw = bws[clock];
829 intel_dp->lane_count = lane_count;
657445fe 830 pipe_config->pipe_bpp = bpp;
ff9a6750 831 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 832
36008365
DV		 833 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
834 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 835 pipe_config->port_clock, bpp);
36008365
DV		 836 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
837 mode_rate, link_avail);
a4fc5ed6 838
03afc4a2 839 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 840 adjusted_mode->crtc_clock,
841 pipe_config->port_clock,
03afc4a2 842 &pipe_config->dp_m_n);
9d1a455b 843
c6bb3538
DV		 844 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
845
03afc4a2 846 return true;
a4fc5ed6
KP		 847}
848
7c62a164 849static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 850{
7c62a164
DV		 851 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
852 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
853 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 854 struct drm_i915_private *dev_priv = dev->dev_private;
855 u32 dpa_ctl;
856
ff9a6750 857 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 858 dpa_ctl = I915_READ(DP_A);
859 dpa_ctl &= ~DP_PLL_FREQ_MASK;
860
ff9a6750 861 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 862 /* For a long time we've carried around a ILK-DevA w/a for the
863 * 160MHz clock. If we're really unlucky, it's still required.
864 */
865 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 866 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 867 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 868 } else {
869 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 870 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 871 }
1ce17038 872
ea9b6006
DV		 873 I915_WRITE(DP_A, dpa_ctl);
874
875 POSTING_READ(DP_A);
876 udelay(500);
877}
878
b934223d 879static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 880{
b934223d 881 struct drm_device *dev = encoder->base.dev;
417e822d 882 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 883 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 884 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 885 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
886 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 887
417e822d 888 /*
1a2eb460 889 * There are four kinds of DP registers:
417e822d
KP		 890 *
891 * IBX PCH
1a2eb460
KP		 892 * SNB CPU
893 * IVB CPU
417e822d
KP		 894 * CPT PCH
895 *
896 * IBX PCH and CPU are the same for almost everything,
897 * except that the CPU DP PLL is configured in this
898 * register
899 *
900 * CPT PCH is quite different, having many bits moved
901 * to the TRANS_DP_CTL register instead. That
902 * configuration happens (oddly) in ironlake_pch_enable
903 */
9c9e7927 904
417e822d
KP		 905 /* Preserve the BIOS-computed detected bit. This is
906 * supposed to be read-only.
907 */
908 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 909
417e822d 910 /* Handle DP bits in common between all three register formats */
417e822d 911 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 912 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 913
e0dac65e
WF		 914 if (intel_dp->has_audio) {
915 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 916 pipe_name(crtc->pipe));
ea5b213a 917 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 918 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 919 }
247d89f6 920
417e822d 921 /* Split out the IBX/CPU vs CPT settings */
32f9d658 922
bc7d38a4 923 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 924 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
925 intel_dp->DP |= DP_SYNC_HS_HIGH;
926 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
927 intel_dp->DP |= DP_SYNC_VS_HIGH;
928 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
929
6aba5b6c 930 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 931 intel_dp->DP |= DP_ENHANCED_FRAMING;
932
7c62a164 933 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 934 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 935 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 936 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 937
938 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
939 intel_dp->DP |= DP_SYNC_HS_HIGH;
940 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
941 intel_dp->DP |= DP_SYNC_VS_HIGH;
942 intel_dp->DP |= DP_LINK_TRAIN_OFF;
943
6aba5b6c 944 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 945 intel_dp->DP |= DP_ENHANCED_FRAMING;
946
7c62a164 947 if (crtc->pipe == 1)
417e822d 948 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 949 } else {
950 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 951 }
ea9b6006 952
bc7d38a4 953 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 954 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 955}
956
ffd6749d
PZ		 957#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
958#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 959
1a5ef5b7
PZ		 960#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
961#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 962
ffd6749d
PZ		 963#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
964#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 965
4be73780 966static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 967 u32 mask,
968 u32 value)
bd943159 969{
30add22d 970 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 971 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 972 u32 pp_stat_reg, pp_ctrl_reg;
973
bf13e81b
JN		 974 pp_stat_reg = _pp_stat_reg(intel_dp);
975 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 976
99ea7127 977 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 978 mask, value,
979 I915_READ(pp_stat_reg),
980 I915_READ(pp_ctrl_reg));
32ce697c 981
453c5420 982 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 983 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 984 I915_READ(pp_stat_reg),
985 I915_READ(pp_ctrl_reg));
32ce697c 986 }
54c136d4
CW		 987
988 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 989}
32ce697c 990
4be73780 991static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 992{
993 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 994 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 995}
996
4be73780 997static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 998{
999 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1000 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1001}
1002
4be73780 1003static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1004{
1005 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1006
1007 /* When we disable the VDD override bit last we have to do the manual
1008 * wait. */
1009 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1010 intel_dp->panel_power_cycle_delay);
1011
4be73780 1012 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1013}
1014
4be73780 1015static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1016{
1017 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1018 intel_dp->backlight_on_delay);
1019}
1020
4be73780 1021static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1022{
1023 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1024 intel_dp->backlight_off_delay);
1025}
99ea7127 1026
832dd3c1
KP		 1027/* Read the current pp_control value, unlocking the register if it
1028 * is locked
1029 */
1030
453c5420 1031static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1032{
453c5420
JB		 1033 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1034 struct drm_i915_private *dev_priv = dev->dev_private;
1035 u32 control;
832dd3c1 1036
bf13e81b 1037 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1038 control &= ~PANEL_UNLOCK_MASK;
1039 control |= PANEL_UNLOCK_REGS;
1040 return control;
bd943159
KP		 1041}
1042
adddaaf4 1043static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1044{
30add22d 1045 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1046 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1047 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1048 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1049 enum intel_display_power_domain power_domain;
5d613501 1050 u32 pp;
453c5420 1051 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1052 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1053
97af61f5 1054 if (!is_edp(intel_dp))
adddaaf4 1055 return false;
bd943159
KP		 1056
1057 intel_dp->want_panel_vdd = true;
99ea7127 1058
4be73780 1059 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1060 return need_to_disable;
b0665d57 1061
4e6e1a54
ID		 1062 power_domain = intel_display_port_power_domain(intel_encoder);
1063 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1064
b0665d57 1065 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1066
4be73780
DV		 1067 if (!edp_have_panel_power(intel_dp))
1068 wait_panel_power_cycle(intel_dp);
99ea7127 1069
453c5420 1070 pp = ironlake_get_pp_control(intel_dp);
5d613501 1071 pp |= EDP_FORCE_VDD;
ebf33b18 1072
bf13e81b
JN		 1073 pp_stat_reg = _pp_stat_reg(intel_dp);
1074 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1075
1076 I915_WRITE(pp_ctrl_reg, pp);
1077 POSTING_READ(pp_ctrl_reg);
1078 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1079 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1080 /*
1081 * If the panel wasn't on, delay before accessing aux channel
1082 */
4be73780 1083 if (!edp_have_panel_power(intel_dp)) {
bd943159 1084 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1085 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1086 }
adddaaf4
JN		 1087
1088 return need_to_disable;
1089}
1090
b80d6c78 1091void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1092{
1093 if (is_edp(intel_dp)) {
1094 bool vdd = _edp_panel_vdd_on(intel_dp);
1095
1096 WARN(!vdd, "eDP VDD already requested on\n");
1097 }
5d613501
JB		 1098}
1099
4be73780 1100static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1101{
30add22d 1102 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1103 struct drm_i915_private *dev_priv = dev->dev_private;
1104 u32 pp;
453c5420 1105 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1106
a0e99e68
DV		 1107 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1108
4be73780 1109 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1110 struct intel_digital_port *intel_dig_port =
1111 dp_to_dig_port(intel_dp);
1112 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1113 enum intel_display_power_domain power_domain;
1114
b0665d57
PZ		 1115 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1116
453c5420 1117 pp = ironlake_get_pp_control(intel_dp);
bd943159 1118 pp &= ~EDP_FORCE_VDD;
bd943159 1119
9f08ef59
PZ		 1120 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1121 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1122
1123 I915_WRITE(pp_ctrl_reg, pp);
1124 POSTING_READ(pp_ctrl_reg);
99ea7127 1125
453c5420
JB		 1126 /* Make sure sequencer is idle before allowing subsequent activity */
1127 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1128 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1129
1130 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1131 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1132
4e6e1a54
ID		 1133 power_domain = intel_display_port_power_domain(intel_encoder);
1134 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1135 }
1136}
5d613501 1137
4be73780 1138static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1139{
1140 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1141 struct intel_dp, panel_vdd_work);
30add22d 1142 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1143
627f7675 1144 mutex_lock(&dev->mode_config.mutex);
4be73780 1145 edp_panel_vdd_off_sync(intel_dp);
627f7675 1146 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1147}
1148
4be73780 1149static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1150{
97af61f5
KP		 1151 if (!is_edp(intel_dp))
1152 return;
5d613501 1153
bd943159 1154 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1155
bd943159
KP		 1156 intel_dp->want_panel_vdd = false;
1157
1158 if (sync) {
4be73780 1159 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1160 } else {
1161 /*
1162 * Queue the timer to fire a long
1163 * time from now (relative to the power down delay)
1164 * to keep the panel power up across a sequence of operations
1165 */
1166 schedule_delayed_work(&intel_dp->panel_vdd_work,
1167 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1168 }
5d613501
JB		 1169}
1170
4be73780 1171void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1172{
30add22d 1173 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1174 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1175 u32 pp;
453c5420 1176 u32 pp_ctrl_reg;
9934c132 1177
97af61f5 1178 if (!is_edp(intel_dp))
bd943159 1179 return;
99ea7127
KP		 1180
1181 DRM_DEBUG_KMS("Turn eDP power on\n");
1182
4be73780 1183 if (edp_have_panel_power(intel_dp)) {
99ea7127 1184 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1185 return;
99ea7127 1186 }
9934c132 1187
4be73780 1188 wait_panel_power_cycle(intel_dp);
37c6c9b0 1189
bf13e81b 1190 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1191 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1192 if (IS_GEN5(dev)) {
1193 /* ILK workaround: disable reset around power sequence */
1194 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1195 I915_WRITE(pp_ctrl_reg, pp);
1196 POSTING_READ(pp_ctrl_reg);
05ce1a49 1197 }
37c6c9b0 1198
1c0ae80a 1199 pp |= POWER_TARGET_ON;
99ea7127
KP		 1200 if (!IS_GEN5(dev))
1201 pp |= PANEL_POWER_RESET;
1202
453c5420
JB		 1203 I915_WRITE(pp_ctrl_reg, pp);
1204 POSTING_READ(pp_ctrl_reg);
9934c132 1205
4be73780 1206 wait_panel_on(intel_dp);
dce56b3c 1207 intel_dp->last_power_on = jiffies;
9934c132 1208
05ce1a49
KP		 1209 if (IS_GEN5(dev)) {
1210 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1211 I915_WRITE(pp_ctrl_reg, pp);
1212 POSTING_READ(pp_ctrl_reg);
05ce1a49 1213 }
9934c132
JB		 1214}
1215
4be73780 1216void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1217{
4e6e1a54
ID		 1218 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1219 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1220 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1221 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1222 enum intel_display_power_domain power_domain;
99ea7127 1223 u32 pp;
453c5420 1224 u32 pp_ctrl_reg;
9934c132 1225
97af61f5
KP		 1226 if (!is_edp(intel_dp))
1227 return;
37c6c9b0 1228
99ea7127 1229 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1230
4be73780 1231 edp_wait_backlight_off(intel_dp);
dce56b3c 1232
24f3e092
JN		 1233 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1234
453c5420 1235 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1236 /* We need to switch off panel power _and_ force vdd, for otherwise some
1237 * panels get very unhappy and cease to work. */
b3064154
PJ		 1238 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1239 EDP_BLC_ENABLE);
453c5420 1240
bf13e81b 1241 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1242
849e39f5
PZ		 1243 intel_dp->want_panel_vdd = false;
1244
453c5420
JB		 1245 I915_WRITE(pp_ctrl_reg, pp);
1246 POSTING_READ(pp_ctrl_reg);
9934c132 1247
dce56b3c 1248 intel_dp->last_power_cycle = jiffies;
4be73780 1249 wait_panel_off(intel_dp);
849e39f5
PZ		 1250
1251 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1252 power_domain = intel_display_port_power_domain(intel_encoder);
1253 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1254}
1255
4be73780 1256void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1257{
da63a9f2
PZ		 1258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1259 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1260 struct drm_i915_private *dev_priv = dev->dev_private;
1261 u32 pp;
453c5420 1262 u32 pp_ctrl_reg;
32f9d658 1263
f01eca2e
KP		 1264 if (!is_edp(intel_dp))
1265 return;
1266
28c97730 1267 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1268 /*
1269 * If we enable the backlight right away following a panel power
1270 * on, we may see slight flicker as the panel syncs with the eDP
1271 * link. So delay a bit to make sure the image is solid before
1272 * allowing it to appear.
1273 */
4be73780 1274 wait_backlight_on(intel_dp);
453c5420 1275 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1276 pp |= EDP_BLC_ENABLE;
453c5420 1277
bf13e81b 1278 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1279
1280 I915_WRITE(pp_ctrl_reg, pp);
1281 POSTING_READ(pp_ctrl_reg);
035aa3de 1282
752aa88a 1283 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1284}
1285
4be73780 1286void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1287{
30add22d 1288 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1289 struct drm_i915_private *dev_priv = dev->dev_private;
1290 u32 pp;
453c5420 1291 u32 pp_ctrl_reg;
32f9d658 1292
f01eca2e
KP		 1293 if (!is_edp(intel_dp))
1294 return;
1295
752aa88a 1296 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1297
28c97730 1298 DRM_DEBUG_KMS("\n");
453c5420 1299 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1300 pp &= ~EDP_BLC_ENABLE;
453c5420 1301
bf13e81b 1302 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1303
1304 I915_WRITE(pp_ctrl_reg, pp);
1305 POSTING_READ(pp_ctrl_reg);
dce56b3c 1306 intel_dp->last_backlight_off = jiffies;
32f9d658 1307}
a4fc5ed6 1308
2bd2ad64 1309static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1310{
da63a9f2
PZ		 1311 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1312 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1313 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1314 struct drm_i915_private *dev_priv = dev->dev_private;
1315 u32 dpa_ctl;
1316
2bd2ad64
DV		 1317 assert_pipe_disabled(dev_priv,
1318 to_intel_crtc(crtc)->pipe);
1319
d240f20f
JB		 1320 DRM_DEBUG_KMS("\n");
1321 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1322 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1323 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1324
1325 /* We don't adjust intel_dp->DP while tearing down the link, to
1326 * facilitate link retraining (e.g. after hotplug). Hence clear all
1327 * enable bits here to ensure that we don't enable too much. */
1328 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1329 intel_dp->DP |= DP_PLL_ENABLE;
1330 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1331 POSTING_READ(DP_A);
1332 udelay(200);
d240f20f
JB		 1333}
1334
2bd2ad64 1335static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1336{
da63a9f2
PZ		 1337 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1338 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1339 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1340 struct drm_i915_private *dev_priv = dev->dev_private;
1341 u32 dpa_ctl;
1342
2bd2ad64
DV		 1343 assert_pipe_disabled(dev_priv,
1344 to_intel_crtc(crtc)->pipe);
1345
d240f20f 1346 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1347 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1348 "dp pll off, should be on\n");
1349 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1350
1351 /* We can't rely on the value tracked for the DP register in
1352 * intel_dp->DP because link_down must not change that (otherwise link
1353 * re-training will fail. */
298b0b39 1354 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1355 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1356 POSTING_READ(DP_A);
d240f20f
JB		 1357 udelay(200);
1358}
1359
c7ad3810 1360/* If the sink supports it, try to set the power state appropriately */
c19b0669 1361void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1362{
1363 int ret, i;
1364
1365 /* Should have a valid DPCD by this point */
1366 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1367 return;
1368
1369 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1370 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1371 DP_SET_POWER_D3);
c7ad3810
JB		 1372 if (ret != 1)
1373 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1374 } else {
1375 /*
1376 * When turning on, we need to retry for 1ms to give the sink
1377 * time to wake up.
1378 */
1379 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1380 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1381 DP_SET_POWER_D0);
c7ad3810
JB		 1382 if (ret == 1)
1383 break;
1384 msleep(1);
1385 }
1386 }
1387}
1388
19d8fe15
DV		 1389static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1390 enum pipe *pipe)
d240f20f 1391{
19d8fe15 1392 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1393 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1394 struct drm_device *dev = encoder->base.dev;
1395 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1396 enum intel_display_power_domain power_domain;
1397 u32 tmp;
1398
1399 power_domain = intel_display_port_power_domain(encoder);
1400 if (!intel_display_power_enabled(dev_priv, power_domain))
1401 return false;
1402
1403 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1404
1405 if (!(tmp & DP_PORT_EN))
1406 return false;
1407
bc7d38a4 1408 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1409 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1410 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1411 *pipe = PORT_TO_PIPE(tmp);
1412 } else {
1413 u32 trans_sel;
1414 u32 trans_dp;
1415 int i;
1416
1417 switch (intel_dp->output_reg) {
1418 case PCH_DP_B:
1419 trans_sel = TRANS_DP_PORT_SEL_B;
1420 break;
1421 case PCH_DP_C:
1422 trans_sel = TRANS_DP_PORT_SEL_C;
1423 break;
1424 case PCH_DP_D:
1425 trans_sel = TRANS_DP_PORT_SEL_D;
1426 break;
1427 default:
1428 return true;
1429 }
1430
1431 for_each_pipe(i) {
1432 trans_dp = I915_READ(TRANS_DP_CTL(i));
1433 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1434 *pipe = i;
1435 return true;
1436 }
1437 }
19d8fe15 1438
4a0833ec
DV		 1439 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1440 intel_dp->output_reg);
1441 }
d240f20f 1442
19d8fe15
DV		 1443 return true;
1444}
d240f20f 1445
045ac3b5
JB		 1446static void intel_dp_get_config(struct intel_encoder *encoder,
1447 struct intel_crtc_config *pipe_config)
1448{
1449 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1450 u32 tmp, flags = 0;
63000ef6
XZ		 1451 struct drm_device *dev = encoder->base.dev;
1452 struct drm_i915_private *dev_priv = dev->dev_private;
1453 enum port port = dp_to_dig_port(intel_dp)->port;
1454 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1455 int dotclock;
045ac3b5 1456
63000ef6
XZ		 1457 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1458 tmp = I915_READ(intel_dp->output_reg);
1459 if (tmp & DP_SYNC_HS_HIGH)
1460 flags |= DRM_MODE_FLAG_PHSYNC;
1461 else
1462 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1463
63000ef6
XZ		 1464 if (tmp & DP_SYNC_VS_HIGH)
1465 flags |= DRM_MODE_FLAG_PVSYNC;
1466 else
1467 flags |= DRM_MODE_FLAG_NVSYNC;
1468 } else {
1469 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1470 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1471 flags |= DRM_MODE_FLAG_PHSYNC;
1472 else
1473 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1474
63000ef6
XZ		 1475 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1476 flags |= DRM_MODE_FLAG_PVSYNC;
1477 else
1478 flags |= DRM_MODE_FLAG_NVSYNC;
1479 }
045ac3b5
JB		 1480
1481 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1482
eb14cb74
VS		 1483 pipe_config->has_dp_encoder = true;
1484
1485 intel_dp_get_m_n(crtc, pipe_config);
1486
18442d08 1487 if (port == PORT_A) {
f1f644dc
JB		 1488 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1489 pipe_config->port_clock = 162000;
1490 else
1491 pipe_config->port_clock = 270000;
1492 }
18442d08
VS		 1493
1494 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1495 &pipe_config->dp_m_n);
1496
1497 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1498 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1499
241bfc38 1500 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1501
c6cd2ee2
JN		 1502 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1503 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1504 /*
1505 * This is a big fat ugly hack.
1506 *
1507 * Some machines in UEFI boot mode provide us a VBT that has 18
1508 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1509 * unknown we fail to light up. Yet the same BIOS boots up with
1510 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1511 * max, not what it tells us to use.
1512 *
1513 * Note: This will still be broken if the eDP panel is not lit
1514 * up by the BIOS, and thus we can't get the mode at module
1515 * load.
1516 */
1517 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1518 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1519 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1520 }
045ac3b5
JB		 1521}
1522
a031d709 1523static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1524{
a031d709
RV		 1525 struct drm_i915_private *dev_priv = dev->dev_private;
1526
1527 return dev_priv->psr.sink_support;
2293bb5c
SK		 1528}
1529
2b28bb1b
RV		 1530static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1531{
1532 struct drm_i915_private *dev_priv = dev->dev_private;
1533
18b5992c 1534 if (!HAS_PSR(dev))
2b28bb1b
RV		 1535 return false;
1536
18b5992c 1537 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1538}
1539
1540static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1541 struct edp_vsc_psr *vsc_psr)
1542{
1543 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1544 struct drm_device *dev = dig_port->base.base.dev;
1545 struct drm_i915_private *dev_priv = dev->dev_private;
1546 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1547 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1548 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1549 uint32_t *data = (uint32_t *) vsc_psr;
1550 unsigned int i;
1551
1552 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1553 the video DIP being updated before program video DIP data buffer
1554 registers for DIP being updated. */
1555 I915_WRITE(ctl_reg, 0);
1556 POSTING_READ(ctl_reg);
1557
1558 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1559 if (i < sizeof(struct edp_vsc_psr))
1560 I915_WRITE(data_reg + i, *data++);
1561 else
1562 I915_WRITE(data_reg + i, 0);
1563 }
1564
1565 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1566 POSTING_READ(ctl_reg);
1567}
1568
1569static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1570{
1571 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1572 struct drm_i915_private *dev_priv = dev->dev_private;
1573 struct edp_vsc_psr psr_vsc;
1574
1575 if (intel_dp->psr_setup_done)
1576 return;
1577
1578 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1579 memset(&psr_vsc, 0, sizeof(psr_vsc));
1580 psr_vsc.sdp_header.HB0 = 0;
1581 psr_vsc.sdp_header.HB1 = 0x7;
1582 psr_vsc.sdp_header.HB2 = 0x2;
1583 psr_vsc.sdp_header.HB3 = 0x8;
1584 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1585
1586 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1587 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1588 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1589
1590 intel_dp->psr_setup_done = true;
1591}
1592
1593static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1594{
1595 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1596 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1597 uint32_t aux_clock_divider;
2b28bb1b
RV		 1598 int precharge = 0x3;
1599 int msg_size = 5; /* Header(4) + Message(1) */
1600
ec5b01dd
DL		 1601 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1602
2b28bb1b
RV		 1603 /* Enable PSR in sink */
1604 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
9d1a1031
JN		 1605 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1606 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1607 else
9d1a1031
JN		 1608 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1609 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1610
1611 /* Setup AUX registers */
18b5992c
BW		 1612 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1613 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1614 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1615 DP_AUX_CH_CTL_TIME_OUT_400us |
1616 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1617 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1618 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1619}
1620
1621static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1622{
1623 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1624 struct drm_i915_private *dev_priv = dev->dev_private;
1625 uint32_t max_sleep_time = 0x1f;
1626 uint32_t idle_frames = 1;
1627 uint32_t val = 0x0;
ed8546ac 1628 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1629
1630 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1631 val |= EDP_PSR_LINK_STANDBY;
1632 val |= EDP_PSR_TP2_TP3_TIME_0us;
1633 val |= EDP_PSR_TP1_TIME_0us;
1634 val |= EDP_PSR_SKIP_AUX_EXIT;
1635 } else
1636 val |= EDP_PSR_LINK_DISABLE;
1637
18b5992c 1638 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1639 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1640 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1641 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1642 EDP_PSR_ENABLE);
1643}
1644
3f51e471
RV		 1645static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1646{
1647 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1648 struct drm_device *dev = dig_port->base.base.dev;
1649 struct drm_i915_private *dev_priv = dev->dev_private;
1650 struct drm_crtc *crtc = dig_port->base.base.crtc;
1651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f4510a27 1652 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1653 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1654
a031d709
RV		 1655 dev_priv->psr.source_ok = false;
1656
18b5992c 1657 if (!HAS_PSR(dev)) {
3f51e471 1658 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1659 return false;
1660 }
1661
1662 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1663 (dig_port->port != PORT_A)) {
1664 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1665 return false;
1666 }
1667
d330a953 1668 if (!i915.enable_psr) {
105b7c11 1669 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1670 return false;
1671 }
1672
cd234b0b
CW		 1673 crtc = dig_port->base.base.crtc;
1674 if (crtc == NULL) {
1675 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1676 return false;
1677 }
1678
1679 intel_crtc = to_intel_crtc(crtc);
20ddf665 1680 if (!intel_crtc_active(crtc)) {
3f51e471 1681 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1682 return false;
1683 }
1684
f4510a27 1685 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1686 if (obj->tiling_mode != I915_TILING_X ||
1687 obj->fence_reg == I915_FENCE_REG_NONE) {
1688 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1689 return false;
1690 }
1691
1692 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1693 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1694 return false;
1695 }
1696
1697 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1698 S3D_ENABLE) {
1699 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1700 return false;
1701 }
1702
ca73b4f0 1703 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1704 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1705 return false;
1706 }
1707
a031d709 1708 dev_priv->psr.source_ok = true;
3f51e471
RV		 1709 return true;
1710}
1711
3d739d92 1712static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1713{
1714 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1715
3f51e471
RV		 1716 if (!intel_edp_psr_match_conditions(intel_dp) ||
1717 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1718 return;
1719
1720 /* Setup PSR once */
1721 intel_edp_psr_setup(intel_dp);
1722
1723 /* Enable PSR on the panel */
1724 intel_edp_psr_enable_sink(intel_dp);
1725
1726 /* Enable PSR on the host */
1727 intel_edp_psr_enable_source(intel_dp);
1728}
1729
3d739d92
RV		 1730void intel_edp_psr_enable(struct intel_dp *intel_dp)
1731{
1732 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1733
1734 if (intel_edp_psr_match_conditions(intel_dp) &&
1735 !intel_edp_is_psr_enabled(dev))
1736 intel_edp_psr_do_enable(intel_dp);
1737}
1738
2b28bb1b
RV		 1739void intel_edp_psr_disable(struct intel_dp *intel_dp)
1740{
1741 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743
1744 if (!intel_edp_is_psr_enabled(dev))
1745 return;
1746
18b5992c
BW		 1747 I915_WRITE(EDP_PSR_CTL(dev),
1748 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1749
1750 /* Wait till PSR is idle */
18b5992c 1751 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1752 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1753 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1754}
1755
3d739d92
RV		 1756void intel_edp_psr_update(struct drm_device *dev)
1757{
1758 struct intel_encoder *encoder;
1759 struct intel_dp *intel_dp = NULL;
1760
1761 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1762 if (encoder->type == INTEL_OUTPUT_EDP) {
1763 intel_dp = enc_to_intel_dp(&encoder->base);
1764
a031d709 1765 if (!is_edp_psr(dev))
3d739d92
RV		 1766 return;
1767
1768 if (!intel_edp_psr_match_conditions(intel_dp))
1769 intel_edp_psr_disable(intel_dp);
1770 else
1771 if (!intel_edp_is_psr_enabled(dev))
1772 intel_edp_psr_do_enable(intel_dp);
1773 }
1774}
1775
e8cb4558 1776static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1777{
e8cb4558 1778 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1779 enum port port = dp_to_dig_port(intel_dp)->port;
1780 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1781
1782 /* Make sure the panel is off before trying to change the mode. But also
1783 * ensure that we have vdd while we switch off the panel. */
24f3e092 1784 intel_edp_panel_vdd_on(intel_dp);
4be73780 1785 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1786 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1787 intel_edp_panel_off(intel_dp);
3739850b
DV		 1788
1789 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1790 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1791 intel_dp_link_down(intel_dp);
d240f20f
JB		 1792}
1793
49277c31 1794static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1795{
2bd2ad64 1796 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1797 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 1798
49277c31
VS		 1799 if (port != PORT_A)
1800 return;
1801
1802 intel_dp_link_down(intel_dp);
1803 ironlake_edp_pll_off(intel_dp);
1804}
1805
1806static void vlv_post_disable_dp(struct intel_encoder *encoder)
1807{
1808 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1809
1810 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 1811}
1812
e8cb4558 1813static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1814{
e8cb4558
DV		 1815 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1816 struct drm_device *dev = encoder->base.dev;
1817 struct drm_i915_private *dev_priv = dev->dev_private;
1818 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1819
0c33d8d7
DV		 1820 if (WARN_ON(dp_reg & DP_PORT_EN))
1821 return;
5d613501 1822
24f3e092 1823 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 1824 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1825 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1826 intel_edp_panel_on(intel_dp);
1827 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1828 intel_dp_complete_link_train(intel_dp);
3ab9c637 1829 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1830}
89b667f8 1831
ecff4f3b
JN		 1832static void g4x_enable_dp(struct intel_encoder *encoder)
1833{
828f5c6e
JN		 1834 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1835
ecff4f3b 1836 intel_enable_dp(encoder);
4be73780 1837 intel_edp_backlight_on(intel_dp);
ab1f90f9 1838}
89b667f8 1839
ab1f90f9
JN		 1840static void vlv_enable_dp(struct intel_encoder *encoder)
1841{
828f5c6e
JN		 1842 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1843
4be73780 1844 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1845}
1846
ecff4f3b 1847static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1848{
1849 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1850 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1851
1852 if (dport->port == PORT_A)
1853 ironlake_edp_pll_on(intel_dp);
1854}
1855
1856static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1857{
2bd2ad64 1858 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1859 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1860 struct drm_device *dev = encoder->base.dev;
89b667f8 1861 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1862 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1863 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1864 int pipe = intel_crtc->pipe;
bf13e81b 1865 struct edp_power_seq power_seq;
ab1f90f9 1866 u32 val;
a4fc5ed6 1867
ab1f90f9 1868 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1869
ab3c759a 1870 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1871 val = 0;
1872 if (pipe)
1873 val |= (1<<21);
1874 else
1875 val &= ~(1<<21);
1876 val |= 0x001000c4;
ab3c759a
CML		 1877 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1878 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1879 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1880
ab1f90f9
JN		 1881 mutex_unlock(&dev_priv->dpio_lock);
1882
2cac613b
ID		 1883 if (is_edp(intel_dp)) {
1884 /* init power sequencer on this pipe and port */
1885 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1886 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1887 &power_seq);
1888 }
bf13e81b 1889
ab1f90f9
JN		 1890 intel_enable_dp(encoder);
1891
e4607fcf 1892 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1893}
1894
ecff4f3b 1895static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1896{
1897 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1898 struct drm_device *dev = encoder->base.dev;
1899 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1900 struct intel_crtc *intel_crtc =
1901 to_intel_crtc(encoder->base.crtc);
e4607fcf 1902 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1903 int pipe = intel_crtc->pipe;
89b667f8 1904
89b667f8 1905 /* Program Tx lane resets to default */
0980a60f 1906 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 1907 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1908 DPIO_PCS_TX_LANE2_RESET |
1909 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1910 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1911 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1912 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1913 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1914 DPIO_PCS_CLK_SOFT_RESET);
1915
1916 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1917 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1918 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1919 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 1920 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1921}
1922
1923/*
df0c237d
JB		 1924 * Native read with retry for link status and receiver capability reads for
1925 * cases where the sink may still be asleep.
9d1a1031
JN		 1926 *
1927 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1928 * supposed to retry 3 times per the spec.
a4fc5ed6 1929 */
9d1a1031
JN		 1930static ssize_t
1931intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
1932 void *buffer, size_t size)
a4fc5ed6 1933{
9d1a1031
JN		 1934 ssize_t ret;
1935 int i;
61da5fab 1936
61da5fab 1937 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1938 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
1939 if (ret == size)
1940 return ret;
61da5fab
JB		 1941 msleep(1);
1942 }
a4fc5ed6 1943
9d1a1031 1944 return ret;
a4fc5ed6
KP		 1945}
1946
1947/*
1948 * Fetch AUX CH registers 0x202 - 0x207 which contain
1949 * link status information
1950 */
1951static bool
93f62dad 1952intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1953{
9d1a1031
JN		 1954 return intel_dp_dpcd_read_wake(&intel_dp->aux,
1955 DP_LANE0_1_STATUS,
1956 link_status,
1957 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 1958}
1959
a4fc5ed6
KP		 1960/*
1961 * These are source-specific values; current Intel hardware supports
1962 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1963 */
a4fc5ed6
KP		 1964
1965static uint8_t
1a2eb460 1966intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1967{
30add22d 1968 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1969 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1970
8f93f4f1 1971 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 1972 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1973 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1974 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1975 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1976 return DP_TRAIN_VOLTAGE_SWING_1200;
1977 else
1978 return DP_TRAIN_VOLTAGE_SWING_800;
1979}
1980
1981static uint8_t
1982intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1983{
30add22d 1984 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1985 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1986
8f93f4f1
PZ		 1987 if (IS_BROADWELL(dev)) {
1988 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1989 case DP_TRAIN_VOLTAGE_SWING_400:
1990 case DP_TRAIN_VOLTAGE_SWING_600:
1991 return DP_TRAIN_PRE_EMPHASIS_6;
1992 case DP_TRAIN_VOLTAGE_SWING_800:
1993 return DP_TRAIN_PRE_EMPHASIS_3_5;
1994 case DP_TRAIN_VOLTAGE_SWING_1200:
1995 default:
1996 return DP_TRAIN_PRE_EMPHASIS_0;
1997 }
1998 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 1999 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2000 case DP_TRAIN_VOLTAGE_SWING_400:
2001 return DP_TRAIN_PRE_EMPHASIS_9_5;
2002 case DP_TRAIN_VOLTAGE_SWING_600:
2003 return DP_TRAIN_PRE_EMPHASIS_6;
2004 case DP_TRAIN_VOLTAGE_SWING_800:
2005 return DP_TRAIN_PRE_EMPHASIS_3_5;
2006 case DP_TRAIN_VOLTAGE_SWING_1200:
2007 default:
2008 return DP_TRAIN_PRE_EMPHASIS_0;
2009 }
e2fa6fba
P		 2010 } else if (IS_VALLEYVIEW(dev)) {
2011 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2012 case DP_TRAIN_VOLTAGE_SWING_400:
2013 return DP_TRAIN_PRE_EMPHASIS_9_5;
2014 case DP_TRAIN_VOLTAGE_SWING_600:
2015 return DP_TRAIN_PRE_EMPHASIS_6;
2016 case DP_TRAIN_VOLTAGE_SWING_800:
2017 return DP_TRAIN_PRE_EMPHASIS_3_5;
2018 case DP_TRAIN_VOLTAGE_SWING_1200:
2019 default:
2020 return DP_TRAIN_PRE_EMPHASIS_0;
2021 }
bc7d38a4 2022 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2023 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2024 case DP_TRAIN_VOLTAGE_SWING_400:
2025 return DP_TRAIN_PRE_EMPHASIS_6;
2026 case DP_TRAIN_VOLTAGE_SWING_600:
2027 case DP_TRAIN_VOLTAGE_SWING_800:
2028 return DP_TRAIN_PRE_EMPHASIS_3_5;
2029 default:
2030 return DP_TRAIN_PRE_EMPHASIS_0;
2031 }
2032 } else {
2033 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2034 case DP_TRAIN_VOLTAGE_SWING_400:
2035 return DP_TRAIN_PRE_EMPHASIS_6;
2036 case DP_TRAIN_VOLTAGE_SWING_600:
2037 return DP_TRAIN_PRE_EMPHASIS_6;
2038 case DP_TRAIN_VOLTAGE_SWING_800:
2039 return DP_TRAIN_PRE_EMPHASIS_3_5;
2040 case DP_TRAIN_VOLTAGE_SWING_1200:
2041 default:
2042 return DP_TRAIN_PRE_EMPHASIS_0;
2043 }
a4fc5ed6
KP		 2044 }
2045}
2046
e2fa6fba
P		 2047static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2048{
2049 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2050 struct drm_i915_private *dev_priv = dev->dev_private;
2051 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2052 struct intel_crtc *intel_crtc =
2053 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2054 unsigned long demph_reg_value, preemph_reg_value,
2055 uniqtranscale_reg_value;
2056 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2057 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2058 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2059
2060 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2061 case DP_TRAIN_PRE_EMPHASIS_0:
2062 preemph_reg_value = 0x0004000;
2063 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2064 case DP_TRAIN_VOLTAGE_SWING_400:
2065 demph_reg_value = 0x2B405555;
2066 uniqtranscale_reg_value = 0x552AB83A;
2067 break;
2068 case DP_TRAIN_VOLTAGE_SWING_600:
2069 demph_reg_value = 0x2B404040;
2070 uniqtranscale_reg_value = 0x5548B83A;
2071 break;
2072 case DP_TRAIN_VOLTAGE_SWING_800:
2073 demph_reg_value = 0x2B245555;
2074 uniqtranscale_reg_value = 0x5560B83A;
2075 break;
2076 case DP_TRAIN_VOLTAGE_SWING_1200:
2077 demph_reg_value = 0x2B405555;
2078 uniqtranscale_reg_value = 0x5598DA3A;
2079 break;
2080 default:
2081 return 0;
2082 }
2083 break;
2084 case DP_TRAIN_PRE_EMPHASIS_3_5:
2085 preemph_reg_value = 0x0002000;
2086 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2087 case DP_TRAIN_VOLTAGE_SWING_400:
2088 demph_reg_value = 0x2B404040;
2089 uniqtranscale_reg_value = 0x5552B83A;
2090 break;
2091 case DP_TRAIN_VOLTAGE_SWING_600:
2092 demph_reg_value = 0x2B404848;
2093 uniqtranscale_reg_value = 0x5580B83A;
2094 break;
2095 case DP_TRAIN_VOLTAGE_SWING_800:
2096 demph_reg_value = 0x2B404040;
2097 uniqtranscale_reg_value = 0x55ADDA3A;
2098 break;
2099 default:
2100 return 0;
2101 }
2102 break;
2103 case DP_TRAIN_PRE_EMPHASIS_6:
2104 preemph_reg_value = 0x0000000;
2105 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2106 case DP_TRAIN_VOLTAGE_SWING_400:
2107 demph_reg_value = 0x2B305555;
2108 uniqtranscale_reg_value = 0x5570B83A;
2109 break;
2110 case DP_TRAIN_VOLTAGE_SWING_600:
2111 demph_reg_value = 0x2B2B4040;
2112 uniqtranscale_reg_value = 0x55ADDA3A;
2113 break;
2114 default:
2115 return 0;
2116 }
2117 break;
2118 case DP_TRAIN_PRE_EMPHASIS_9_5:
2119 preemph_reg_value = 0x0006000;
2120 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2121 case DP_TRAIN_VOLTAGE_SWING_400:
2122 demph_reg_value = 0x1B405555;
2123 uniqtranscale_reg_value = 0x55ADDA3A;
2124 break;
2125 default:
2126 return 0;
2127 }
2128 break;
2129 default:
2130 return 0;
2131 }
2132
0980a60f 2133 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2134 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2135 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2136 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2137 uniqtranscale_reg_value);
ab3c759a
CML		 2138 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2139 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2140 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2141 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2142 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2143
2144 return 0;
2145}
2146
a4fc5ed6 2147static void
0301b3ac
JN		 2148intel_get_adjust_train(struct intel_dp *intel_dp,
2149 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2150{
2151 uint8_t v = 0;
2152 uint8_t p = 0;
2153 int lane;
1a2eb460
KP		 2154 uint8_t voltage_max;
2155 uint8_t preemph_max;
a4fc5ed6 2156
33a34e4e 2157 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2158 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2159 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2160
2161 if (this_v > v)
2162 v = this_v;
2163 if (this_p > p)
2164 p = this_p;
2165 }
2166
1a2eb460 2167 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2168 if (v >= voltage_max)
2169 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2170
1a2eb460
KP		 2171 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2172 if (p >= preemph_max)
2173 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2174
2175 for (lane = 0; lane < 4; lane++)
33a34e4e 2176 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2177}
2178
2179static uint32_t
f0a3424e 2180intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2181{
3cf2efb1 2182 uint32_t signal_levels = 0;
a4fc5ed6 2183
3cf2efb1 2184 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2185 case DP_TRAIN_VOLTAGE_SWING_400:
2186 default:
2187 signal_levels |= DP_VOLTAGE_0_4;
2188 break;
2189 case DP_TRAIN_VOLTAGE_SWING_600:
2190 signal_levels |= DP_VOLTAGE_0_6;
2191 break;
2192 case DP_TRAIN_VOLTAGE_SWING_800:
2193 signal_levels |= DP_VOLTAGE_0_8;
2194 break;
2195 case DP_TRAIN_VOLTAGE_SWING_1200:
2196 signal_levels |= DP_VOLTAGE_1_2;
2197 break;
2198 }
3cf2efb1 2199 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2200 case DP_TRAIN_PRE_EMPHASIS_0:
2201 default:
2202 signal_levels |= DP_PRE_EMPHASIS_0;
2203 break;
2204 case DP_TRAIN_PRE_EMPHASIS_3_5:
2205 signal_levels |= DP_PRE_EMPHASIS_3_5;
2206 break;
2207 case DP_TRAIN_PRE_EMPHASIS_6:
2208 signal_levels |= DP_PRE_EMPHASIS_6;
2209 break;
2210 case DP_TRAIN_PRE_EMPHASIS_9_5:
2211 signal_levels |= DP_PRE_EMPHASIS_9_5;
2212 break;
2213 }
2214 return signal_levels;
2215}
2216
e3421a18
ZW		 2217/* Gen6's DP voltage swing and pre-emphasis control */
2218static uint32_t
2219intel_gen6_edp_signal_levels(uint8_t train_set)
2220{
3c5a62b5
YL		 2221 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2222 DP_TRAIN_PRE_EMPHASIS_MASK);
2223 switch (signal_levels) {
e3421a18 2224 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2225 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2226 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2227 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2228 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2229 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2230 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2231 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2232 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2233 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2234 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2235 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2236 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2237 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2238 default:
3c5a62b5
YL		 2239 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2240 "0x%x\n", signal_levels);
2241 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2242 }
2243}
2244
1a2eb460
KP		 2245/* Gen7's DP voltage swing and pre-emphasis control */
2246static uint32_t
2247intel_gen7_edp_signal_levels(uint8_t train_set)
2248{
2249 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2250 DP_TRAIN_PRE_EMPHASIS_MASK);
2251 switch (signal_levels) {
2252 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2253 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2254 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2255 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2256 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2257 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2258
2259 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2260 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2261 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2262 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2263
2264 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2265 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2266 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2267 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2268
2269 default:
2270 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2271 "0x%x\n", signal_levels);
2272 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2273 }
2274}
2275
d6c0d722
PZ		 2276/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2277static uint32_t
f0a3424e 2278intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2279{
d6c0d722
PZ		 2280 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2281 DP_TRAIN_PRE_EMPHASIS_MASK);
2282 switch (signal_levels) {
2283 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2284 return DDI_BUF_EMP_400MV_0DB_HSW;
2285 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2286 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2287 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2288 return DDI_BUF_EMP_400MV_6DB_HSW;
2289 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2290 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2291
d6c0d722
PZ		 2292 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2293 return DDI_BUF_EMP_600MV_0DB_HSW;
2294 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2295 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2296 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2297 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2298
d6c0d722
PZ		 2299 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2300 return DDI_BUF_EMP_800MV_0DB_HSW;
2301 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2302 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2303 default:
2304 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2305 "0x%x\n", signal_levels);
2306 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2307 }
a4fc5ed6
KP		 2308}
2309
8f93f4f1
PZ		 2310static uint32_t
2311intel_bdw_signal_levels(uint8_t train_set)
2312{
2313 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2314 DP_TRAIN_PRE_EMPHASIS_MASK);
2315 switch (signal_levels) {
2316 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2317 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2318 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2319 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2320 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2321 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2322
2323 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2324 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2325 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2326 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2327 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2328 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2329
2330 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2331 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2332 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2333 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2334
2335 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2336 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2337
2338 default:
2339 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2340 "0x%x\n", signal_levels);
2341 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2342 }
2343}
2344
f0a3424e
PZ		 2345/* Properly updates "DP" with the correct signal levels. */
2346static void
2347intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2348{
2349 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2350 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2351 struct drm_device *dev = intel_dig_port->base.base.dev;
2352 uint32_t signal_levels, mask;
2353 uint8_t train_set = intel_dp->train_set[0];
2354
8f93f4f1
PZ		 2355 if (IS_BROADWELL(dev)) {
2356 signal_levels = intel_bdw_signal_levels(train_set);
2357 mask = DDI_BUF_EMP_MASK;
2358 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2359 signal_levels = intel_hsw_signal_levels(train_set);
2360 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2361 } else if (IS_VALLEYVIEW(dev)) {
2362 signal_levels = intel_vlv_signal_levels(intel_dp);
2363 mask = 0;
bc7d38a4 2364 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2365 signal_levels = intel_gen7_edp_signal_levels(train_set);
2366 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2367 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2368 signal_levels = intel_gen6_edp_signal_levels(train_set);
2369 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2370 } else {
2371 signal_levels = intel_gen4_signal_levels(train_set);
2372 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2373 }
2374
2375 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2376
2377 *DP = (*DP & ~mask) | signal_levels;
2378}
2379
a4fc5ed6 2380static bool
ea5b213a 2381intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2382 uint32_t *DP,
58e10eb9 2383 uint8_t dp_train_pat)
a4fc5ed6 2384{
174edf1f
PZ		 2385 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2386 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2387 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2388 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2389 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2390 int ret, len;
a4fc5ed6 2391
22b8bf17 2392 if (HAS_DDI(dev)) {
3ab9c637 2393 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2394
2395 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2396 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2397 else
2398 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2399
2400 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2401 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2402 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2403 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2404
2405 break;
2406 case DP_TRAINING_PATTERN_1:
2407 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2408 break;
2409 case DP_TRAINING_PATTERN_2:
2410 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2411 break;
2412 case DP_TRAINING_PATTERN_3:
2413 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2414 break;
2415 }
174edf1f 2416 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2417
bc7d38a4 2418 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2419 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2420
2421 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2422 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2423 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2424 break;
2425 case DP_TRAINING_PATTERN_1:
70aff66c 2426 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2427 break;
2428 case DP_TRAINING_PATTERN_2:
70aff66c 2429 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2430 break;
2431 case DP_TRAINING_PATTERN_3:
2432 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2433 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2434 break;
2435 }
2436
2437 } else {
70aff66c 2438 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2439
2440 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2441 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2442 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2443 break;
2444 case DP_TRAINING_PATTERN_1:
70aff66c 2445 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2446 break;
2447 case DP_TRAINING_PATTERN_2:
70aff66c 2448 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2449 break;
2450 case DP_TRAINING_PATTERN_3:
2451 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2452 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2453 break;
2454 }
2455 }
2456
70aff66c 2457 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2458 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2459
2cdfe6c8
JN		 2460 buf[0] = dp_train_pat;
2461 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2462 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2463 /* don't write DP_TRAINING_LANEx_SET on disable */
2464 len = 1;
2465 } else {
2466 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2467 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2468 len = intel_dp->lane_count + 1;
47ea7542 2469 }
a4fc5ed6 2470
9d1a1031
JN		 2471 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2472 buf, len);
2cdfe6c8
JN		 2473
2474 return ret == len;
a4fc5ed6
KP		 2475}
2476
70aff66c
JN		 2477static bool
2478intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2479 uint8_t dp_train_pat)
2480{
953d22e8 2481 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2482 intel_dp_set_signal_levels(intel_dp, DP);
2483 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2484}
2485
2486static bool
2487intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2488 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2489{
2490 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2491 struct drm_device *dev = intel_dig_port->base.base.dev;
2492 struct drm_i915_private *dev_priv = dev->dev_private;
2493 int ret;
2494
2495 intel_get_adjust_train(intel_dp, link_status);
2496 intel_dp_set_signal_levels(intel_dp, DP);
2497
2498 I915_WRITE(intel_dp->output_reg, *DP);
2499 POSTING_READ(intel_dp->output_reg);
2500
9d1a1031
JN		 2501 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2502 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2503
2504 return ret == intel_dp->lane_count;
2505}
2506
3ab9c637
ID		 2507static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2508{
2509 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2510 struct drm_device *dev = intel_dig_port->base.base.dev;
2511 struct drm_i915_private *dev_priv = dev->dev_private;
2512 enum port port = intel_dig_port->port;
2513 uint32_t val;
2514
2515 if (!HAS_DDI(dev))
2516 return;
2517
2518 val = I915_READ(DP_TP_CTL(port));
2519 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2520 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2521 I915_WRITE(DP_TP_CTL(port), val);
2522
2523 /*
2524 * On PORT_A we can have only eDP in SST mode. There the only reason
2525 * we need to set idle transmission mode is to work around a HW issue
2526 * where we enable the pipe while not in idle link-training mode.
2527 * In this case there is requirement to wait for a minimum number of
2528 * idle patterns to be sent.
2529 */
2530 if (port == PORT_A)
2531 return;
2532
2533 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2534 1))
2535 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2536}
2537
33a34e4e 2538/* Enable corresponding port and start training pattern 1 */
c19b0669 2539void
33a34e4e 2540intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2541{
da63a9f2 2542 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2543 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2544 int i;
2545 uint8_t voltage;
cdb0e95b 2546 int voltage_tries, loop_tries;
ea5b213a 2547 uint32_t DP = intel_dp->DP;
6aba5b6c 2548 uint8_t link_config[2];
a4fc5ed6 2549
affa9354 2550 if (HAS_DDI(dev))
c19b0669
PZ		 2551 intel_ddi_prepare_link_retrain(encoder);
2552
3cf2efb1 2553 /* Write the link configuration data */
6aba5b6c
JN		 2554 link_config[0] = intel_dp->link_bw;
2555 link_config[1] = intel_dp->lane_count;
2556 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2557 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 2558 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 2559
2560 link_config[0] = 0;
2561 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 2562 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2563
2564 DP |= DP_PORT_EN;
1a2eb460 2565
70aff66c
JN		 2566 /* clock recovery */
2567 if (!intel_dp_reset_link_train(intel_dp, &DP,
2568 DP_TRAINING_PATTERN_1 |
2569 DP_LINK_SCRAMBLING_DISABLE)) {
2570 DRM_ERROR("failed to enable link training\n");
2571 return;
2572 }
2573
a4fc5ed6 2574 voltage = 0xff;
cdb0e95b
KP		 2575 voltage_tries = 0;
2576 loop_tries = 0;
a4fc5ed6 2577 for (;;) {
70aff66c 2578 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2579
a7c9655f 2580 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2581 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2582 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2583 break;
93f62dad 2584 }
a4fc5ed6 2585
01916270 2586 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2587 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2588 break;
2589 }
2590
2591 /* Check to see if we've tried the max voltage */
2592 for (i = 0; i < intel_dp->lane_count; i++)
2593 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2594 break;
3b4f819d 2595 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2596 ++loop_tries;
2597 if (loop_tries == 5) {
3def84b3 2598 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2599 break;
2600 }
70aff66c
JN		 2601 intel_dp_reset_link_train(intel_dp, &DP,
2602 DP_TRAINING_PATTERN_1 |
2603 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2604 voltage_tries = 0;
2605 continue;
2606 }
a4fc5ed6 2607
3cf2efb1 2608 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2609 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2610 ++voltage_tries;
b06fbda3 2611 if (voltage_tries == 5) {
3def84b3 2612 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2613 break;
2614 }
2615 } else
2616 voltage_tries = 0;
2617 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2618
70aff66c
JN		 2619 /* Update training set as requested by target */
2620 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2621 DRM_ERROR("failed to update link training\n");
2622 break;
2623 }
a4fc5ed6
KP		 2624 }
2625
33a34e4e
JB		 2626 intel_dp->DP = DP;
2627}
2628
c19b0669 2629void
33a34e4e
JB		 2630intel_dp_complete_link_train(struct intel_dp *intel_dp)
2631{
33a34e4e 2632 bool channel_eq = false;
37f80975 2633 int tries, cr_tries;
33a34e4e 2634 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2635 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2636
2637 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2638 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2639 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2640
a4fc5ed6 2641 /* channel equalization */
70aff66c 2642 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2643 training_pattern |
70aff66c
JN		 2644 DP_LINK_SCRAMBLING_DISABLE)) {
2645 DRM_ERROR("failed to start channel equalization\n");
2646 return;
2647 }
2648
a4fc5ed6 2649 tries = 0;
37f80975 2650 cr_tries = 0;
a4fc5ed6
KP		 2651 channel_eq = false;
2652 for (;;) {
70aff66c 2653 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2654
37f80975
JB		 2655 if (cr_tries > 5) {
2656 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2657 break;
2658 }
2659
a7c9655f 2660 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2661 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2662 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2663 break;
70aff66c 2664 }
a4fc5ed6 2665
37f80975 2666 /* Make sure clock is still ok */
01916270 2667 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2668 intel_dp_start_link_train(intel_dp);
70aff66c 2669 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2670 training_pattern |
70aff66c 2671 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2672 cr_tries++;
2673 continue;
2674 }
2675
1ffdff13 2676 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2677 channel_eq = true;
2678 break;
2679 }
a4fc5ed6 2680
37f80975
JB		 2681 /* Try 5 times, then try clock recovery if that fails */
2682 if (tries > 5) {
2683 intel_dp_link_down(intel_dp);
2684 intel_dp_start_link_train(intel_dp);
70aff66c 2685 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2686 training_pattern |
70aff66c 2687 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2688 tries = 0;
2689 cr_tries++;
2690 continue;
2691 }
a4fc5ed6 2692
70aff66c
JN		 2693 /* Update training set as requested by target */
2694 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2695 DRM_ERROR("failed to update link training\n");
2696 break;
2697 }
3cf2efb1 2698 ++tries;
869184a6 2699 }
3cf2efb1 2700
3ab9c637
ID		 2701 intel_dp_set_idle_link_train(intel_dp);
2702
2703 intel_dp->DP = DP;
2704
d6c0d722 2705 if (channel_eq)
07f42258 2706 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2707
3ab9c637
ID		 2708}
2709
2710void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2711{
70aff66c 2712 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2713 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2714}
2715
2716static void
ea5b213a 2717intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2718{
da63a9f2 2719 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2720 enum port port = intel_dig_port->port;
da63a9f2 2721 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2722 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2723 struct intel_crtc *intel_crtc =
2724 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2725 uint32_t DP = intel_dp->DP;
a4fc5ed6 2726
c19b0669
PZ		 2727 /*
2728 * DDI code has a strict mode set sequence and we should try to respect
2729 * it, otherwise we might hang the machine in many different ways. So we
2730 * really should be disabling the port only on a complete crtc_disable
2731 * sequence. This function is just called under two conditions on DDI
2732 * code:
2733 * - Link train failed while doing crtc_enable, and on this case we
2734 * really should respect the mode set sequence and wait for a
2735 * crtc_disable.
2736 * - Someone turned the monitor off and intel_dp_check_link_status
2737 * called us. We don't need to disable the whole port on this case, so
2738 * when someone turns the monitor on again,
2739 * intel_ddi_prepare_link_retrain will take care of redoing the link
2740 * train.
2741 */
affa9354 2742 if (HAS_DDI(dev))
c19b0669
PZ		 2743 return;
2744
0c33d8d7 2745 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2746 return;
2747
28c97730 2748 DRM_DEBUG_KMS("\n");
32f9d658 2749
bc7d38a4 2750 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2751 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2752 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2753 } else {
2754 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2755 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2756 }
fe255d00 2757 POSTING_READ(intel_dp->output_reg);
5eb08b69 2758
ab527efc
DV		 2759 /* We don't really know why we're doing this */
2760 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2761
493a7081 2762 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2763 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2764 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2765
5bddd17f
EA		 2766 /* Hardware workaround: leaving our transcoder select
2767 * set to transcoder B while it's off will prevent the
2768 * corresponding HDMI output on transcoder A.
2769 *
2770 * Combine this with another hardware workaround:
2771 * transcoder select bit can only be cleared while the
2772 * port is enabled.
2773 */
2774 DP &= ~DP_PIPEB_SELECT;
2775 I915_WRITE(intel_dp->output_reg, DP);
2776
2777 /* Changes to enable or select take place the vblank
2778 * after being written.
2779 */
ff50afe9
DV		 2780 if (WARN_ON(crtc == NULL)) {
2781 /* We should never try to disable a port without a crtc
2782 * attached. For paranoia keep the code around for a
2783 * bit. */
31acbcc4
CW		 2784 POSTING_READ(intel_dp->output_reg);
2785 msleep(50);
2786 } else
ab527efc 2787 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2788 }
2789
832afda6 2790 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2791 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2792 POSTING_READ(intel_dp->output_reg);
f01eca2e 2793 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2794}
2795
26d61aad
KP		 2796static bool
2797intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2798{
a031d709
RV		 2799 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2800 struct drm_device *dev = dig_port->base.base.dev;
2801 struct drm_i915_private *dev_priv = dev->dev_private;
2802
577c7a50
DL		 2803 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2804
9d1a1031
JN		 2805 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2806 sizeof(intel_dp->dpcd)) < 0)
edb39244 2807 return false; /* aux transfer failed */
92fd8fd1 2808
577c7a50
DL		 2809 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2810 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2811 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2812
edb39244
AJ		 2813 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2814 return false; /* DPCD not present */
2815
2293bb5c
SK		 2816 /* Check if the panel supports PSR */
2817 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 2818 if (is_edp(intel_dp)) {
9d1a1031
JN		 2819 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2820 intel_dp->psr_dpcd,
2821 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2822 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2823 dev_priv->psr.sink_support = true;
50003939 2824 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2825 }
50003939
JN		 2826 }
2827
06ea66b6
TP		 2828 /* Training Pattern 3 support */
2829 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2830 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2831 intel_dp->use_tps3 = true;
2832 DRM_DEBUG_KMS("Displayport TPS3 supported");
2833 } else
2834 intel_dp->use_tps3 = false;
2835
edb39244
AJ		 2836 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2837 DP_DWN_STRM_PORT_PRESENT))
2838 return true; /* native DP sink */
2839
2840 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2841 return true; /* no per-port downstream info */
2842
9d1a1031
JN		 2843 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2844 intel_dp->downstream_ports,
2845 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 2846 return false; /* downstream port status fetch failed */
2847
2848 return true;
92fd8fd1
KP		 2849}
2850
0d198328
AJ		 2851static void
2852intel_dp_probe_oui(struct intel_dp *intel_dp)
2853{
2854 u8 buf[3];
2855
2856 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2857 return;
2858
24f3e092 2859 intel_edp_panel_vdd_on(intel_dp);
351cfc34 2860
9d1a1031 2861 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 2862 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2863 buf[0], buf[1], buf[2]);
2864
9d1a1031 2865 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 2866 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2867 buf[0], buf[1], buf[2]);
351cfc34 2868
4be73780 2869 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2870}
2871
d2e216d0
RV		 2872int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2873{
2874 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2875 struct drm_device *dev = intel_dig_port->base.base.dev;
2876 struct intel_crtc *intel_crtc =
2877 to_intel_crtc(intel_dig_port->base.base.crtc);
2878 u8 buf[1];
2879
9d1a1031 2880 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 2881 return -EAGAIN;
2882
2883 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2884 return -ENOTTY;
2885
9d1a1031
JN		 2886 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2887 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 2888 return -EAGAIN;
2889
2890 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2891 intel_wait_for_vblank(dev, intel_crtc->pipe);
2892 intel_wait_for_vblank(dev, intel_crtc->pipe);
2893
9d1a1031 2894 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 2895 return -EAGAIN;
2896
9d1a1031 2897 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 2898 return 0;
2899}
2900
a60f0e38
JB		 2901static bool
2902intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2903{
9d1a1031
JN		 2904 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2905 DP_DEVICE_SERVICE_IRQ_VECTOR,
2906 sink_irq_vector, 1) == 1;
a60f0e38
JB		 2907}
2908
2909static void
2910intel_dp_handle_test_request(struct intel_dp *intel_dp)
2911{
2912 /* NAK by default */
9d1a1031 2913 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2914}
2915
a4fc5ed6
KP		 2916/*
2917 * According to DP spec
2918 * 5.1.2:
2919 * 1. Read DPCD
2920 * 2. Configure link according to Receiver Capabilities
2921 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2922 * 4. Check link status on receipt of hot-plug interrupt
2923 */
2924
00c09d70 2925void
ea5b213a 2926intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2927{
da63a9f2 2928 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2929 u8 sink_irq_vector;
93f62dad 2930 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2931
da63a9f2 2932 if (!intel_encoder->connectors_active)
d2b996ac 2933 return;
59cd09e1 2934
da63a9f2 2935 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2936 return;
2937
92fd8fd1 2938 /* Try to read receiver status if the link appears to be up */
93f62dad 2939 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 2940 return;
2941 }
2942
92fd8fd1 2943 /* Now read the DPCD to see if it's actually running */
26d61aad 2944 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2945 return;
2946 }
2947
a60f0e38
JB		 2948 /* Try to read the source of the interrupt */
2949 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2950 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2951 /* Clear interrupt source */
9d1a1031
JN		 2952 drm_dp_dpcd_writeb(&intel_dp->aux,
2953 DP_DEVICE_SERVICE_IRQ_VECTOR,
2954 sink_irq_vector);
a60f0e38
JB		 2955
2956 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2957 intel_dp_handle_test_request(intel_dp);
2958 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2959 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2960 }
2961
1ffdff13 2962 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2963 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2964 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2965 intel_dp_start_link_train(intel_dp);
2966 intel_dp_complete_link_train(intel_dp);
3ab9c637 2967 intel_dp_stop_link_train(intel_dp);
33a34e4e 2968 }
a4fc5ed6 2969}
a4fc5ed6 2970
caf9ab24 2971/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2972static enum drm_connector_status
26d61aad 2973intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2974{
caf9ab24 2975 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 2976 uint8_t type;
2977
2978 if (!intel_dp_get_dpcd(intel_dp))
2979 return connector_status_disconnected;
2980
2981 /* if there's no downstream port, we're done */
2982 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2983 return connector_status_connected;
caf9ab24
AJ		 2984
2985 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 2986 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2987 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 2988 uint8_t reg;
9d1a1031
JN		 2989
2990 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
2991 &reg, 1) < 0)
caf9ab24 2992 return connector_status_unknown;
9d1a1031 2993
23235177
AJ		 2994 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2995 : connector_status_disconnected;
caf9ab24
AJ		 2996 }
2997
2998 /* If no HPD, poke DDC gently */
0b99836f 2999 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3000 return connector_status_connected;
caf9ab24
AJ		 3001
3002 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3003 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3004 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3005 if (type == DP_DS_PORT_TYPE_VGA ||
3006 type == DP_DS_PORT_TYPE_NON_EDID)
3007 return connector_status_unknown;
3008 } else {
3009 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3010 DP_DWN_STRM_PORT_TYPE_MASK;
3011 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3012 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3013 return connector_status_unknown;
3014 }
caf9ab24
AJ		 3015
3016 /* Anything else is out of spec, warn and ignore */
3017 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3018 return connector_status_disconnected;
71ba9000
AJ		 3019}
3020
5eb08b69 3021static enum drm_connector_status
a9756bb5 3022ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3023{
30add22d 3024 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3025 struct drm_i915_private *dev_priv = dev->dev_private;
3026 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3027 enum drm_connector_status status;
3028
fe16d949
CW		 3029 /* Can't disconnect eDP, but you can close the lid... */
3030 if (is_edp(intel_dp)) {
30add22d 3031 status = intel_panel_detect(dev);
fe16d949
CW		 3032 if (status == connector_status_unknown)
3033 status = connector_status_connected;
3034 return status;
3035 }
01cb9ea6 3036
1b469639
DL		 3037 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3038 return connector_status_disconnected;
3039
26d61aad 3040 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3041}
3042
a4fc5ed6 3043static enum drm_connector_status
a9756bb5 3044g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3045{
30add22d 3046 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3047 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3048 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3049 uint32_t bit;
5eb08b69 3050
35aad75f
JB		 3051 /* Can't disconnect eDP, but you can close the lid... */
3052 if (is_edp(intel_dp)) {
3053 enum drm_connector_status status;
3054
3055 status = intel_panel_detect(dev);
3056 if (status == connector_status_unknown)
3057 status = connector_status_connected;
3058 return status;
3059 }
3060
232a6ee9
TP		 3061 if (IS_VALLEYVIEW(dev)) {
3062 switch (intel_dig_port->port) {
3063 case PORT_B:
3064 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3065 break;
3066 case PORT_C:
3067 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3068 break;
3069 case PORT_D:
3070 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3071 break;
3072 default:
3073 return connector_status_unknown;
3074 }
3075 } else {
3076 switch (intel_dig_port->port) {
3077 case PORT_B:
3078 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3079 break;
3080 case PORT_C:
3081 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3082 break;
3083 case PORT_D:
3084 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3085 break;
3086 default:
3087 return connector_status_unknown;
3088 }
a4fc5ed6
KP		 3089 }
3090
10f76a38 3091 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3092 return connector_status_disconnected;
3093
26d61aad 3094 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3095}
3096
8c241fef
KP		 3097static struct edid *
3098intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3099{
9cd300e0 3100 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3101
9cd300e0
JN		 3102 /* use cached edid if we have one */
3103 if (intel_connector->edid) {
9cd300e0
JN		 3104 /* invalid edid */
3105 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3106 return NULL;
3107
55e9edeb 3108 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3109 }
8c241fef 3110
9cd300e0 3111 return drm_get_edid(connector, adapter);
8c241fef
KP		 3112}
3113
3114static int
3115intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3116{
9cd300e0 3117 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3118
9cd300e0
JN		 3119 /* use cached edid if we have one */
3120 if (intel_connector->edid) {
3121 /* invalid edid */
3122 if (IS_ERR(intel_connector->edid))
3123 return 0;
3124
3125 return intel_connector_update_modes(connector,
3126 intel_connector->edid);
d6f24d0f
JB		 3127 }
3128
9cd300e0 3129 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3130}
3131
a9756bb5
ZW		 3132static enum drm_connector_status
3133intel_dp_detect(struct drm_connector *connector, bool force)
3134{
3135 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3136 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3137 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3138 struct drm_device *dev = connector->dev;
c8c8fb33 3139 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3140 enum drm_connector_status status;
671dedd2 3141 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3142 struct edid *edid = NULL;
3143
c8c8fb33
PZ		 3144 intel_runtime_pm_get(dev_priv);
3145
671dedd2
ID		 3146 power_domain = intel_display_port_power_domain(intel_encoder);
3147 intel_display_power_get(dev_priv, power_domain);
3148
164c8598
CW		 3149 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3150 connector->base.id, drm_get_connector_name(connector));
3151
a9756bb5
ZW		 3152 intel_dp->has_audio = false;
3153
3154 if (HAS_PCH_SPLIT(dev))
3155 status = ironlake_dp_detect(intel_dp);
3156 else
3157 status = g4x_dp_detect(intel_dp);
1b9be9d0 3158
a9756bb5 3159 if (status != connector_status_connected)
c8c8fb33 3160 goto out;
a9756bb5 3161
0d198328
AJ		 3162 intel_dp_probe_oui(intel_dp);
3163
c3e5f67b
DV		 3164 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3165 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3166 } else {
0b99836f 3167 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3168 if (edid) {
3169 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3170 kfree(edid);
3171 }
a9756bb5
ZW		 3172 }
3173
d63885da
PZ		 3174 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3175 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3176 status = connector_status_connected;
3177
3178out:
671dedd2
ID		 3179 intel_display_power_put(dev_priv, power_domain);
3180
c8c8fb33 3181 intel_runtime_pm_put(dev_priv);
671dedd2 3182
c8c8fb33 3183 return status;
a4fc5ed6
KP		 3184}
3185
3186static int intel_dp_get_modes(struct drm_connector *connector)
3187{
df0e9248 3188 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3189 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3190 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3191 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3192 struct drm_device *dev = connector->dev;
671dedd2
ID		 3193 struct drm_i915_private *dev_priv = dev->dev_private;
3194 enum intel_display_power_domain power_domain;
32f9d658 3195 int ret;
a4fc5ed6
KP		 3196
3197 /* We should parse the EDID data and find out if it has an audio sink
3198 */
3199
671dedd2
ID		 3200 power_domain = intel_display_port_power_domain(intel_encoder);
3201 intel_display_power_get(dev_priv, power_domain);
3202
0b99836f 3203 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3204 intel_display_power_put(dev_priv, power_domain);
f8779fda 3205 if (ret)
32f9d658
ZW		 3206 return ret;
3207
f8779fda 3208 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3209 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3210 struct drm_display_mode *mode;
dd06f90e
JN		 3211 mode = drm_mode_duplicate(dev,
3212 intel_connector->panel.fixed_mode);
f8779fda 3213 if (mode) {
32f9d658
ZW		 3214 drm_mode_probed_add(connector, mode);
3215 return 1;
3216 }
3217 }
3218 return 0;
a4fc5ed6
KP		 3219}
3220
1aad7ac0
CW		 3221static bool
3222intel_dp_detect_audio(struct drm_connector *connector)
3223{
3224 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3225 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3226 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3227 struct drm_device *dev = connector->dev;
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3230 struct edid *edid;
3231 bool has_audio = false;
3232
671dedd2
ID		 3233 power_domain = intel_display_port_power_domain(intel_encoder);
3234 intel_display_power_get(dev_priv, power_domain);
3235
0b99836f 3236 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3237 if (edid) {
3238 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3239 kfree(edid);
3240 }
3241
671dedd2
ID		 3242 intel_display_power_put(dev_priv, power_domain);
3243
1aad7ac0
CW		 3244 return has_audio;
3245}
3246
f684960e
CW		 3247static int
3248intel_dp_set_property(struct drm_connector *connector,
3249 struct drm_property *property,
3250 uint64_t val)
3251{
e953fd7b 3252 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3253 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3254 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3255 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3256 int ret;
3257
662595df 3258 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3259 if (ret)
3260 return ret;
3261
3f43c48d 3262 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3263 int i = val;
3264 bool has_audio;
3265
3266 if (i == intel_dp->force_audio)
f684960e
CW		 3267 return 0;
3268
1aad7ac0 3269 intel_dp->force_audio = i;
f684960e 3270
c3e5f67b 3271 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3272 has_audio = intel_dp_detect_audio(connector);
3273 else
c3e5f67b 3274 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3275
3276 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3277 return 0;
3278
1aad7ac0 3279 intel_dp->has_audio = has_audio;
f684960e
CW		 3280 goto done;
3281 }
3282
e953fd7b 3283 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3284 bool old_auto = intel_dp->color_range_auto;
3285 uint32_t old_range = intel_dp->color_range;
3286
55bc60db
VS		 3287 switch (val) {
3288 case INTEL_BROADCAST_RGB_AUTO:
3289 intel_dp->color_range_auto = true;
3290 break;
3291 case INTEL_BROADCAST_RGB_FULL:
3292 intel_dp->color_range_auto = false;
3293 intel_dp->color_range = 0;
3294 break;
3295 case INTEL_BROADCAST_RGB_LIMITED:
3296 intel_dp->color_range_auto = false;
3297 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3298 break;
3299 default:
3300 return -EINVAL;
3301 }
ae4edb80
DV		 3302
3303 if (old_auto == intel_dp->color_range_auto &&
3304 old_range == intel_dp->color_range)
3305 return 0;
3306
e953fd7b
CW		 3307 goto done;
3308 }
3309
53b41837
YN		 3310 if (is_edp(intel_dp) &&
3311 property == connector->dev->mode_config.scaling_mode_property) {
3312 if (val == DRM_MODE_SCALE_NONE) {
3313 DRM_DEBUG_KMS("no scaling not supported\n");
3314 return -EINVAL;
3315 }
3316
3317 if (intel_connector->panel.fitting_mode == val) {
3318 /* the eDP scaling property is not changed */
3319 return 0;
3320 }
3321 intel_connector->panel.fitting_mode = val;
3322
3323 goto done;
3324 }
3325
f684960e
CW		 3326 return -EINVAL;
3327
3328done:
c0c36b94
CW		 3329 if (intel_encoder->base.crtc)
3330 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3331
3332 return 0;
3333}
3334
a4fc5ed6 3335static void
73845adf 3336intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3337{
1d508706 3338 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3339
9cd300e0
JN		 3340 if (!IS_ERR_OR_NULL(intel_connector->edid))
3341 kfree(intel_connector->edid);
3342
acd8db10
PZ		 3343 /* Can't call is_edp() since the encoder may have been destroyed
3344 * already. */
3345 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3346 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3347
a4fc5ed6 3348 drm_connector_cleanup(connector);
55f78c43 3349 kfree(connector);
a4fc5ed6
KP		 3350}
3351
00c09d70 3352void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3353{
da63a9f2
PZ		 3354 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3355 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3356 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3357
0b99836f 3358 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
24d05927 3359 drm_encoder_cleanup(encoder);
bd943159
KP		 3360 if (is_edp(intel_dp)) {
3361 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3362 mutex_lock(&dev->mode_config.mutex);
4be73780 3363 edp_panel_vdd_off_sync(intel_dp);
bd173813 3364 mutex_unlock(&dev->mode_config.mutex);
bd943159 3365 }
da63a9f2 3366 kfree(intel_dig_port);
24d05927
DV		 3367}
3368
a4fc5ed6 3369static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3370 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3371 .detect = intel_dp_detect,
3372 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3373 .set_property = intel_dp_set_property,
73845adf 3374 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3375};
3376
3377static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3378 .get_modes = intel_dp_get_modes,
3379 .mode_valid = intel_dp_mode_valid,
df0e9248 3380 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3381};
3382
a4fc5ed6 3383static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3384 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3385};
3386
995b6762 3387static void
21d40d37 3388intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3389{
fa90ecef 3390 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3391
885a5014 3392 intel_dp_check_link_status(intel_dp);
c8110e52 3393}
6207937d 3394
e3421a18
ZW		 3395/* Return which DP Port should be selected for Transcoder DP control */
3396int
0206e353 3397intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3398{
3399 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3400 struct intel_encoder *intel_encoder;
3401 struct intel_dp *intel_dp;
e3421a18 3402
fa90ecef
PZ		 3403 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3404 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3405
fa90ecef
PZ		 3406 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3407 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3408 return intel_dp->output_reg;
e3421a18 3409 }
ea5b213a 3410
e3421a18
ZW		 3411 return -1;
3412}
3413
36e83a18 3414/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3415bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3416{
3417 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3418 union child_device_config *p_child;
36e83a18 3419 int i;
5d8a7752
VS		 3420 static const short port_mapping[] = {
3421 [PORT_B] = PORT_IDPB,
3422 [PORT_C] = PORT_IDPC,
3423 [PORT_D] = PORT_IDPD,
3424 };
36e83a18 3425
3b32a35b
VS		 3426 if (port == PORT_A)
3427 return true;
3428
41aa3448 3429 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3430 return false;
3431
41aa3448
RV		 3432 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3433 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3434
5d8a7752 3435 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3436 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3437 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3438 return true;
3439 }
3440 return false;
3441}
3442
f684960e
CW		 3443static void
3444intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3445{
53b41837
YN		 3446 struct intel_connector *intel_connector = to_intel_connector(connector);
3447
3f43c48d 3448 intel_attach_force_audio_property(connector);
e953fd7b 3449 intel_attach_broadcast_rgb_property(connector);
55bc60db 3450 intel_dp->color_range_auto = true;
53b41837
YN		 3451
3452 if (is_edp(intel_dp)) {
3453 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3454 drm_object_attach_property(
3455 &connector->base,
53b41837 3456 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3457 DRM_MODE_SCALE_ASPECT);
3458 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3459 }
f684960e
CW		 3460}
3461
dada1a9f
ID		 3462static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3463{
3464 intel_dp->last_power_cycle = jiffies;
3465 intel_dp->last_power_on = jiffies;
3466 intel_dp->last_backlight_off = jiffies;
3467}
3468
67a54566
DV		 3469static void
3470intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3471 struct intel_dp *intel_dp,
3472 struct edp_power_seq *out)
67a54566
DV		 3473{
3474 struct drm_i915_private *dev_priv = dev->dev_private;
3475 struct edp_power_seq cur, vbt, spec, final;
3476 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3477 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3478
3479 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3480 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3481 pp_on_reg = PCH_PP_ON_DELAYS;
3482 pp_off_reg = PCH_PP_OFF_DELAYS;
3483 pp_div_reg = PCH_PP_DIVISOR;
3484 } else {
bf13e81b
JN		 3485 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3486
3487 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3488 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3489 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3490 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3491 }
67a54566
DV		 3492
3493 /* Workaround: Need to write PP_CONTROL with the unlock key as
3494 * the very first thing. */
453c5420 3495 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3496 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3497
453c5420
JB		 3498 pp_on = I915_READ(pp_on_reg);
3499 pp_off = I915_READ(pp_off_reg);
3500 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3501
3502 /* Pull timing values out of registers */
3503 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3504 PANEL_POWER_UP_DELAY_SHIFT;
3505
3506 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3507 PANEL_LIGHT_ON_DELAY_SHIFT;
3508
3509 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3510 PANEL_LIGHT_OFF_DELAY_SHIFT;
3511
3512 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3513 PANEL_POWER_DOWN_DELAY_SHIFT;
3514
3515 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3516 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3517
3518 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3519 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3520
41aa3448 3521 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3522
3523 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3524 * our hw here, which are all in 100usec. */
3525 spec.t1_t3 = 210 * 10;
3526 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3527 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3528 spec.t10 = 500 * 10;
3529 /* This one is special and actually in units of 100ms, but zero
3530 * based in the hw (so we need to add 100 ms). But the sw vbt
3531 * table multiplies it with 1000 to make it in units of 100usec,
3532 * too. */
3533 spec.t11_t12 = (510 + 100) * 10;
3534
3535 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3536 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3537
3538 /* Use the max of the register settings and vbt. If both are
3539 * unset, fall back to the spec limits. */
3540#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3541 spec.field : \
3542 max(cur.field, vbt.field))
3543 assign_final(t1_t3);
3544 assign_final(t8);
3545 assign_final(t9);
3546 assign_final(t10);
3547 assign_final(t11_t12);
3548#undef assign_final
3549
3550#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3551 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3552 intel_dp->backlight_on_delay = get_delay(t8);
3553 intel_dp->backlight_off_delay = get_delay(t9);
3554 intel_dp->panel_power_down_delay = get_delay(t10);
3555 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3556#undef get_delay
3557
f30d26e4
JN		 3558 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3559 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3560 intel_dp->panel_power_cycle_delay);
3561
3562 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3563 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3564
3565 if (out)
3566 *out = final;
3567}
3568
3569static void
3570intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3571 struct intel_dp *intel_dp,
3572 struct edp_power_seq *seq)
3573{
3574 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3575 u32 pp_on, pp_off, pp_div, port_sel = 0;
3576 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3577 int pp_on_reg, pp_off_reg, pp_div_reg;
3578
3579 if (HAS_PCH_SPLIT(dev)) {
3580 pp_on_reg = PCH_PP_ON_DELAYS;
3581 pp_off_reg = PCH_PP_OFF_DELAYS;
3582 pp_div_reg = PCH_PP_DIVISOR;
3583 } else {
bf13e81b
JN		 3584 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3585
3586 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3587 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3588 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3589 }
3590
b2f19d1a
PZ		 3591 /*
3592 * And finally store the new values in the power sequencer. The
3593 * backlight delays are set to 1 because we do manual waits on them. For
3594 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3595 * we'll end up waiting for the backlight off delay twice: once when we
3596 * do the manual sleep, and once when we disable the panel and wait for
3597 * the PP_STATUS bit to become zero.
3598 */
f30d26e4 3599 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3600 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3601 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3602 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3603 /* Compute the divisor for the pp clock, simply match the Bspec
3604 * formula. */
453c5420 3605 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3606 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3607 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3608
3609 /* Haswell doesn't have any port selection bits for the panel
3610 * power sequencer any more. */
bc7d38a4 3611 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3612 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3613 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3614 else
3615 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3616 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3617 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3618 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3619 else
a24c144c 3620 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3621 }
3622
453c5420
JB		 3623 pp_on |= port_sel;
3624
3625 I915_WRITE(pp_on_reg, pp_on);
3626 I915_WRITE(pp_off_reg, pp_off);
3627 I915_WRITE(pp_div_reg, pp_div);
67a54566 3628
67a54566 3629 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3630 I915_READ(pp_on_reg),
3631 I915_READ(pp_off_reg),
3632 I915_READ(pp_div_reg));
f684960e
CW		 3633}
3634
ed92f0b2 3635static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3636 struct intel_connector *intel_connector,
3637 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3638{
3639 struct drm_connector *connector = &intel_connector->base;
3640 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3641 struct drm_device *dev = intel_dig_port->base.base.dev;
3642 struct drm_i915_private *dev_priv = dev->dev_private;
3643 struct drm_display_mode *fixed_mode = NULL;
ed92f0b2
PZ		 3644 bool has_dpcd;
3645 struct drm_display_mode *scan;
3646 struct edid *edid;
3647
3648 if (!is_edp(intel_dp))
3649 return true;
3650
ed92f0b2 3651 /* Cache DPCD and EDID for edp. */
24f3e092 3652 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 3653 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 3654 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 3655
3656 if (has_dpcd) {
3657 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3658 dev_priv->no_aux_handshake =
3659 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3660 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3661 } else {
3662 /* if this fails, presume the device is a ghost */
3663 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3664 return false;
3665 }
3666
3667 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3668 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3669
4da98541 3670 mutex_lock(&dev->mode_config.mutex);
0b99836f 3671 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 3672 if (edid) {
3673 if (drm_add_edid_modes(connector, edid)) {
3674 drm_mode_connector_update_edid_property(connector,
3675 edid);
3676 drm_edid_to_eld(connector, edid);
3677 } else {
3678 kfree(edid);
3679 edid = ERR_PTR(-EINVAL);
3680 }
3681 } else {
3682 edid = ERR_PTR(-ENOENT);
3683 }
3684 intel_connector->edid = edid;
3685
3686 /* prefer fixed mode from EDID if available */
3687 list_for_each_entry(scan, &connector->probed_modes, head) {
3688 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3689 fixed_mode = drm_mode_duplicate(dev, scan);
3690 break;
3691 }
3692 }
3693
3694 /* fallback to VBT if available for eDP */
3695 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3696 fixed_mode = drm_mode_duplicate(dev,
3697 dev_priv->vbt.lfp_lvds_vbt_mode);
3698 if (fixed_mode)
3699 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3700 }
4da98541 3701 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 3702
4b6ed685 3703 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
ed92f0b2
PZ		 3704 intel_panel_setup_backlight(connector);
3705
3706 return true;
3707}
3708
16c25533 3709bool
f0fec3f2
PZ		 3710intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3711 struct intel_connector *intel_connector)
a4fc5ed6 3712{
f0fec3f2
PZ		 3713 struct drm_connector *connector = &intel_connector->base;
3714 struct intel_dp *intel_dp = &intel_dig_port->dp;
3715 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3716 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3717 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3718 enum port port = intel_dig_port->port;
0095e6dc 3719 struct edp_power_seq power_seq = { 0 };
0b99836f 3720 int type;
a4fc5ed6 3721
ec5b01dd
DL		 3722 /* intel_dp vfuncs */
3723 if (IS_VALLEYVIEW(dev))
3724 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3725 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3726 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3727 else if (HAS_PCH_SPLIT(dev))
3728 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3729 else
3730 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3731
153b1100
DL		 3732 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3733
0767935e
DV		 3734 /* Preserve the current hw state. */
3735 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3736 intel_dp->attached_connector = intel_connector;
3d3dc149 3737
3b32a35b 3738 if (intel_dp_is_edp(dev, port))
b329530c 3739 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3740 else
3741 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3742
f7d24902
ID		 3743 /*
3744 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3745 * for DP the encoder type can be set by the caller to
3746 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3747 */
3748 if (type == DRM_MODE_CONNECTOR_eDP)
3749 intel_encoder->type = INTEL_OUTPUT_EDP;
3750
e7281eab
ID		 3751 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3752 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3753 port_name(port));
3754
b329530c 3755 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3756 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3757
a4fc5ed6
KP		 3758 connector->interlace_allowed = true;
3759 connector->doublescan_allowed = 0;
3760
f0fec3f2 3761 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 3762 edp_panel_vdd_work);
a4fc5ed6 3763
df0e9248 3764 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3765 drm_sysfs_connector_add(connector);
3766
affa9354 3767 if (HAS_DDI(dev))
bcbc889b
PZ		 3768 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3769 else
3770 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 3771 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 3772
0b99836f 3773 /* Set up the hotplug pin. */
ab9d7c30
PZ		 3774 switch (port) {
3775 case PORT_A:
1d843f9d 3776 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3777 break;
3778 case PORT_B:
1d843f9d 3779 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3780 break;
3781 case PORT_C:
1d843f9d 3782 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3783 break;
3784 case PORT_D:
1d843f9d 3785 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3786 break;
3787 default:
ad1c0b19 3788 BUG();
5eb08b69
ZW		 3789 }
3790
dada1a9f
ID		 3791 if (is_edp(intel_dp)) {
3792 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 3793 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 3794 }
0095e6dc 3795
9d1a1031 3796 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 3797
2b28bb1b
RV		 3798 intel_dp->psr_setup_done = false;
3799
0095e6dc 3800 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
0b99836f 3801 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
15b1d171
PZ		 3802 if (is_edp(intel_dp)) {
3803 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3804 mutex_lock(&dev->mode_config.mutex);
4be73780 3805 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 3806 mutex_unlock(&dev->mode_config.mutex);
3807 }
b2f246a8
PZ		 3808 drm_sysfs_connector_remove(connector);
3809 drm_connector_cleanup(connector);
16c25533 3810 return false;
b2f246a8 3811 }
32f9d658 3812
f684960e
CW		 3813 intel_dp_add_properties(intel_dp, connector);
3814
a4fc5ed6
KP		 3815 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3816 * 0xd. Failure to do so will result in spurious interrupts being
3817 * generated on the port when a cable is not attached.
3818 */
3819 if (IS_G4X(dev) && !IS_GM45(dev)) {
3820 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3821 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3822 }
16c25533
PZ		 3823
3824 return true;
a4fc5ed6 3825}
f0fec3f2
PZ		 3826
3827void
3828intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3829{
3830 struct intel_digital_port *intel_dig_port;
3831 struct intel_encoder *intel_encoder;
3832 struct drm_encoder *encoder;
3833 struct intel_connector *intel_connector;
3834
b14c5679 3835 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3836 if (!intel_dig_port)
3837 return;
3838
b14c5679 3839 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3840 if (!intel_connector) {
3841 kfree(intel_dig_port);
3842 return;
3843 }
3844
3845 intel_encoder = &intel_dig_port->base;
3846 encoder = &intel_encoder->base;
3847
3848 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3849 DRM_MODE_ENCODER_TMDS);
3850
5bfe2ac0 3851 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3852 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70 3853 intel_encoder->disable = intel_disable_dp;
00c09d70 3854 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3855 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3856 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3857 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3858 intel_encoder->pre_enable = vlv_pre_enable_dp;
3859 intel_encoder->enable = vlv_enable_dp;
49277c31 3860 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 3861 } else {
ecff4f3b
JN		 3862 intel_encoder->pre_enable = g4x_pre_enable_dp;
3863 intel_encoder->enable = g4x_enable_dp;
49277c31 3864 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 3865 }
f0fec3f2 3866
174edf1f 3867 intel_dig_port->port = port;
f0fec3f2
PZ		 3868 intel_dig_port->dp.output_reg = output_reg;
3869
00c09d70 3870 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2 3871 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3872 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 3873 intel_encoder->hot_plug = intel_dp_hot_plug;
3874
15b1d171
PZ		 3875 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3876 drm_encoder_cleanup(encoder);
3877 kfree(intel_dig_port);
b2f246a8 3878 kfree(intel_connector);
15b1d171 3879 }
f0fec3f2 3880}
ubuntu-zesty-kernel mirror