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drm/i915: Move panel's backlight setup next to panel init
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf 50struct dp_link_dpll {
840b32b7 51 int clock;
9dd4ffdf
CML		 52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
840b32b7 56 { 162000,
9dd4ffdf 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
840b32b7 58 { 270000,
9dd4ffdf
CML		 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
840b32b7 63 { 162000,
9dd4ffdf 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
840b32b7 65 { 270000,
9dd4ffdf
CML		 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5 69static const struct dp_link_dpll vlv_dpll[] = {
840b32b7 70 { 162000,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
840b32b7 72 { 270000,
65ce4bf5
CML		 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
840b32b7 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
ef9348c8 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
840b32b7 88 { 270000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
840b32b7 90 { 540000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8
CML		 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15
VS		 97 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 99
cfcb0fc9
JB		 100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
da63a9f2
PZ		 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 112}
113
68b4d824 114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 115{
68b4d824
ID		 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 119}
120
df0e9248
CW		 121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
fa90ecef 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 124}
125
ea5b213a 126static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
f21a2198 132static void intel_dp_unset_edid(struct intel_dp *intel_dp);
a4fc5ed6 133
ed4e9c1d
VS		 134static int
135intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 136{
7183dc29 137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 138
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
141 case DP_LINK_BW_2_7:
1db10e28 142 case DP_LINK_BW_5_4:
d4eead50 143 break;
a4fc5ed6 144 default:
d4eead50
ID		 145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
146 max_link_bw);
a4fc5ed6
KP		 147 max_link_bw = DP_LINK_BW_1_62;
148 break;
149 }
150 return max_link_bw;
151}
152
eeb6324d
PZ		 153static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
154{
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
eeb6324d
PZ		 156 u8 source_max, sink_max;
157
ccb1a831 158 source_max = intel_dig_port->max_lanes;
eeb6324d
PZ		 159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
160
161 return min(source_max, sink_max);
162}
163
cd9dde44
AJ		 164/*
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
167 *
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
169 *
170 * 270000 * 1 * 8 / 10 == 216000
171 *
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
176 *
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
179 */
180
a4fc5ed6 181static int
c898261c 182intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 183{
cd9dde44 184 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 185}
186
fe27d53e
DA		 187static int
188intel_dp_max_data_rate(int max_link_clock, int max_lanes)
189{
190 return (max_link_clock * max_lanes * 8) / 10;
191}
192
c19de8eb 193static enum drm_mode_status
a4fc5ed6
KP		 194intel_dp_mode_valid(struct drm_connector *connector,
195 struct drm_display_mode *mode)
196{
df0e9248 197 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 198 struct intel_connector *intel_connector = to_intel_connector(connector);
199 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 200 int target_clock = mode->clock;
201 int max_rate, mode_rate, max_lanes, max_link_clock;
799487f5 202 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
a4fc5ed6 203
dd06f90e
JN		 204 if (is_edp(intel_dp) && fixed_mode) {
205 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 206 return MODE_PANEL;
207
dd06f90e 208 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 209 return MODE_PANEL;
03afc4a2
DV		 210
211 target_clock = fixed_mode->clock;
7de56f43
ZY		 212 }
213
50fec21a 214 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 215 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 216
217 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
218 mode_rate = intel_dp_link_required(target_clock, 18);
219
799487f5 220 if (mode_rate > max_rate || target_clock > max_dotclk)
c4867936 221 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 222
223 if (mode->clock < 10000)
224 return MODE_CLOCK_LOW;
225
0af78a2b
DV		 226 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
227 return MODE_H_ILLEGAL;
228
a4fc5ed6
KP		 229 return MODE_OK;
230}
231
a4f1289e 232uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 233{
234 int i;
235 uint32_t v = 0;
236
237 if (src_bytes > 4)
238 src_bytes = 4;
239 for (i = 0; i < src_bytes; i++)
240 v |= ((uint32_t) src[i]) << ((3-i) * 8);
241 return v;
242}
243
c2af70e2 244static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 245{
246 int i;
247 if (dst_bytes > 4)
248 dst_bytes = 4;
249 for (i = 0; i < dst_bytes; i++)
250 dst[i] = src >> ((3-i) * 8);
251}
252
bf13e81b
JN		 253static void
254intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 255 struct intel_dp *intel_dp);
bf13e81b
JN		 256static void
257intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 258 struct intel_dp *intel_dp);
bf13e81b 259
773538e8
VS		 260static void pps_lock(struct intel_dp *intel_dp)
261{
262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
263 struct intel_encoder *encoder = &intel_dig_port->base;
264 struct drm_device *dev = encoder->base.dev;
265 struct drm_i915_private *dev_priv = dev->dev_private;
266 enum intel_display_power_domain power_domain;
267
268 /*
269 * See vlv_power_sequencer_reset() why we need
270 * a power domain reference here.
271 */
25f78f58 272 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 273 intel_display_power_get(dev_priv, power_domain);
274
275 mutex_lock(&dev_priv->pps_mutex);
276}
277
278static void pps_unlock(struct intel_dp *intel_dp)
279{
280 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
281 struct intel_encoder *encoder = &intel_dig_port->base;
282 struct drm_device *dev = encoder->base.dev;
283 struct drm_i915_private *dev_priv = dev->dev_private;
284 enum intel_display_power_domain power_domain;
285
286 mutex_unlock(&dev_priv->pps_mutex);
287
25f78f58 288 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 289 intel_display_power_put(dev_priv, power_domain);
290}
291
961a0db0
VS		 292static void
293vlv_power_sequencer_kick(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct drm_device *dev = intel_dig_port->base.base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum pipe pipe = intel_dp->pps_pipe;
0047eedc
VS		 299 bool pll_enabled, release_cl_override = false;
300 enum dpio_phy phy = DPIO_PHY(pipe);
301 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
961a0db0
VS		 302 uint32_t DP;
303
304 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
305 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
306 pipe_name(pipe), port_name(intel_dig_port->port)))
307 return;
308
309 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
310 pipe_name(pipe), port_name(intel_dig_port->port));
311
312 /* Preserve the BIOS-computed detected bit. This is
313 * supposed to be read-only.
314 */
315 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
316 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
317 DP |= DP_PORT_WIDTH(1);
318 DP |= DP_LINK_TRAIN_PAT_1;
319
320 if (IS_CHERRYVIEW(dev))
321 DP |= DP_PIPE_SELECT_CHV(pipe);
322 else if (pipe == PIPE_B)
323 DP |= DP_PIPEB_SELECT;
324
d288f65f
VS		 325 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
326
327 /*
328 * The DPLL for the pipe must be enabled for this to work.
329 * So enable temporarily it if it's not already enabled.
330 */
0047eedc
VS		 331 if (!pll_enabled) {
332 release_cl_override = IS_CHERRYVIEW(dev) &&
333 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
334
3f36b937
TU		 335 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
336 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
337 DRM_ERROR("Failed to force on pll for pipe %c!\n",
338 pipe_name(pipe));
339 return;
340 }
0047eedc 341 }
d288f65f 342
961a0db0
VS		 343 /*
344 * Similar magic as in intel_dp_enable_port().
345 * We _must_ do this port enable + disable trick
346 * to make this power seqeuencer lock onto the port.
347 * Otherwise even VDD force bit won't work.
348 */
349 I915_WRITE(intel_dp->output_reg, DP);
350 POSTING_READ(intel_dp->output_reg);
351
352 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
353 POSTING_READ(intel_dp->output_reg);
354
355 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
356 POSTING_READ(intel_dp->output_reg);
d288f65f 357
0047eedc 358 if (!pll_enabled) {
d288f65f 359 vlv_force_pll_off(dev, pipe);
0047eedc
VS		 360
361 if (release_cl_override)
362 chv_phy_powergate_ch(dev_priv, phy, ch, false);
363 }
961a0db0
VS		 364}
365
bf13e81b
JN		 366static enum pipe
367vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
368{
369 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 370 struct drm_device *dev = intel_dig_port->base.base.dev;
371 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 372 struct intel_encoder *encoder;
373 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 374 enum pipe pipe;
bf13e81b 375
e39b999a 376 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 377
a8c3344e
VS		 378 /* We should never land here with regular DP ports */
379 WARN_ON(!is_edp(intel_dp));
380
a4a5d2f8
VS		 381 if (intel_dp->pps_pipe != INVALID_PIPE)
382 return intel_dp->pps_pipe;
383
384 /*
385 * We don't have power sequencer currently.
386 * Pick one that's not used by other ports.
387 */
19c8054c 388 for_each_intel_encoder(dev, encoder) {
a4a5d2f8
VS		 389 struct intel_dp *tmp;
390
391 if (encoder->type != INTEL_OUTPUT_EDP)
392 continue;
393
394 tmp = enc_to_intel_dp(&encoder->base);
395
396 if (tmp->pps_pipe != INVALID_PIPE)
397 pipes &= ~(1 << tmp->pps_pipe);
398 }
399
400 /*
401 * Didn't find one. This should not happen since there
402 * are two power sequencers and up to two eDP ports.
403 */
404 if (WARN_ON(pipes == 0))
a8c3344e
VS		 405 pipe = PIPE_A;
406 else
407 pipe = ffs(pipes) - 1;
a4a5d2f8 408
a8c3344e
VS		 409 vlv_steal_power_sequencer(dev, pipe);
410 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 411
412 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
413 pipe_name(intel_dp->pps_pipe),
414 port_name(intel_dig_port->port));
415
416 /* init power sequencer on this pipe and port */
36b5f425
VS		 417 intel_dp_init_panel_power_sequencer(dev, intel_dp);
418 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 419
961a0db0
VS		 420 /*
421 * Even vdd force doesn't work until we've made
422 * the power sequencer lock in on the port.
423 */
424 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 425
426 return intel_dp->pps_pipe;
427}
428
78597996
ID		 429static int
430bxt_power_sequencer_idx(struct intel_dp *intel_dp)
431{
432 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
433 struct drm_device *dev = intel_dig_port->base.base.dev;
434 struct drm_i915_private *dev_priv = dev->dev_private;
435
436 lockdep_assert_held(&dev_priv->pps_mutex);
437
438 /* We should never land here with regular DP ports */
439 WARN_ON(!is_edp(intel_dp));
440
441 /*
442 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
443 * mapping needs to be retrieved from VBT, for now just hard-code to
444 * use instance #0 always.
445 */
446 if (!intel_dp->pps_reset)
447 return 0;
448
449 intel_dp->pps_reset = false;
450
451 /*
452 * Only the HW needs to be reprogrammed, the SW state is fixed and
453 * has been setup during connector init.
454 */
455 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
456
457 return 0;
458}
459
6491ab27
VS		 460typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
461 enum pipe pipe);
462
463static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
464 enum pipe pipe)
465{
466 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
467}
468
469static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
470 enum pipe pipe)
471{
472 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
473}
474
475static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
476 enum pipe pipe)
477{
478 return true;
479}
bf13e81b 480
a4a5d2f8 481static enum pipe
6491ab27
VS		 482vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
483 enum port port,
484 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 485{
486 enum pipe pipe;
bf13e81b 487
bf13e81b
JN		 488 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
489 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
490 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 491
492 if (port_sel != PANEL_PORT_SELECT_VLV(port))
493 continue;
494
6491ab27
VS		 495 if (!pipe_check(dev_priv, pipe))
496 continue;
497
a4a5d2f8 498 return pipe;
bf13e81b
JN		 499 }
500
a4a5d2f8
VS		 501 return INVALID_PIPE;
502}
503
504static void
505vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
506{
507 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
508 struct drm_device *dev = intel_dig_port->base.base.dev;
509 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 510 enum port port = intel_dig_port->port;
511
512 lockdep_assert_held(&dev_priv->pps_mutex);
513
514 /* try to find a pipe with this port selected */
6491ab27
VS		 515 /* first pick one where the panel is on */
516 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
517 vlv_pipe_has_pp_on);
518 /* didn't find one? pick one where vdd is on */
519 if (intel_dp->pps_pipe == INVALID_PIPE)
520 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
521 vlv_pipe_has_vdd_on);
522 /* didn't find one? pick one with just the correct port */
523 if (intel_dp->pps_pipe == INVALID_PIPE)
524 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
525 vlv_pipe_any);
a4a5d2f8
VS		 526
527 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
528 if (intel_dp->pps_pipe == INVALID_PIPE) {
529 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
530 port_name(port));
531 return;
bf13e81b
JN		 532 }
533
a4a5d2f8
VS		 534 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
535 port_name(port), pipe_name(intel_dp->pps_pipe));
536
36b5f425
VS		 537 intel_dp_init_panel_power_sequencer(dev, intel_dp);
538 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 539}
540
78597996 541void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
773538e8
VS		 542{
543 struct drm_device *dev = dev_priv->dev;
544 struct intel_encoder *encoder;
545
78597996
ID		 546 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
547 !IS_BROXTON(dev)))
773538e8
VS		 548 return;
549
550 /*
551 * We can't grab pps_mutex here due to deadlock with power_domain
552 * mutex when power_domain functions are called while holding pps_mutex.
553 * That also means that in order to use pps_pipe the code needs to
554 * hold both a power domain reference and pps_mutex, and the power domain
555 * reference get/put must be done while _not_ holding pps_mutex.
556 * pps_{lock,unlock}() do these steps in the correct order, so one
557 * should use them always.
558 */
559
19c8054c 560 for_each_intel_encoder(dev, encoder) {
773538e8
VS		 561 struct intel_dp *intel_dp;
562
563 if (encoder->type != INTEL_OUTPUT_EDP)
564 continue;
565
566 intel_dp = enc_to_intel_dp(&encoder->base);
78597996
ID		 567 if (IS_BROXTON(dev))
568 intel_dp->pps_reset = true;
569 else
570 intel_dp->pps_pipe = INVALID_PIPE;
773538e8 571 }
bf13e81b
JN		 572}
573
8e8232d5
ID		 574struct pps_registers {
575 i915_reg_t pp_ctrl;
576 i915_reg_t pp_stat;
577 i915_reg_t pp_on;
578 i915_reg_t pp_off;
579 i915_reg_t pp_div;
580};
581
582static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
583 struct intel_dp *intel_dp,
584 struct pps_registers *regs)
585{
586 memset(regs, 0, sizeof(*regs));
587
588 if (IS_BROXTON(dev_priv)) {
589 int idx = bxt_power_sequencer_idx(intel_dp);
590
591 regs->pp_ctrl = BXT_PP_CONTROL(idx);
592 regs->pp_stat = BXT_PP_STATUS(idx);
593 regs->pp_on = BXT_PP_ON_DELAYS(idx);
594 regs->pp_off = BXT_PP_OFF_DELAYS(idx);
595 } else if (HAS_PCH_SPLIT(dev_priv)) {
596 regs->pp_ctrl = PCH_PP_CONTROL;
597 regs->pp_stat = PCH_PP_STATUS;
598 regs->pp_on = PCH_PP_ON_DELAYS;
599 regs->pp_off = PCH_PP_OFF_DELAYS;
600 regs->pp_div = PCH_PP_DIVISOR;
601 } else {
602 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
603
604 regs->pp_ctrl = VLV_PIPE_PP_CONTROL(pipe);
605 regs->pp_stat = VLV_PIPE_PP_STATUS(pipe);
606 regs->pp_on = VLV_PIPE_PP_ON_DELAYS(pipe);
607 regs->pp_off = VLV_PIPE_PP_OFF_DELAYS(pipe);
608 regs->pp_div = VLV_PIPE_PP_DIVISOR(pipe);
609 }
610}
611
f0f59a00
VS		 612static i915_reg_t
613_pp_ctrl_reg(struct intel_dp *intel_dp)
bf13e81b 614{
8e8232d5 615 struct pps_registers regs;
bf13e81b 616
8e8232d5
ID		 617 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
618 &regs);
619
620 return regs.pp_ctrl;
bf13e81b
JN		 621}
622
f0f59a00
VS		 623static i915_reg_t
624_pp_stat_reg(struct intel_dp *intel_dp)
bf13e81b 625{
8e8232d5 626 struct pps_registers regs;
bf13e81b 627
8e8232d5
ID		 628 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
629 &regs);
630
631 return regs.pp_stat;
bf13e81b
JN		 632}
633
01527b31
CT		 634/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
635 This function only applicable when panel PM state is not to be tracked */
636static int edp_notify_handler(struct notifier_block *this, unsigned long code,
637 void *unused)
638{
639 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
640 edp_notifier);
641 struct drm_device *dev = intel_dp_to_dev(intel_dp);
642 struct drm_i915_private *dev_priv = dev->dev_private;
01527b31
CT		 643
644 if (!is_edp(intel_dp) || code != SYS_RESTART)
645 return 0;
646
773538e8 647 pps_lock(intel_dp);
e39b999a 648
666a4537 649 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e39b999a 650 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
f0f59a00 651 i915_reg_t pp_ctrl_reg, pp_div_reg;
649636ef 652 u32 pp_div;
e39b999a 653
01527b31
CT		 654 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
655 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
656 pp_div = I915_READ(pp_div_reg);
657 pp_div &= PP_REFERENCE_DIVIDER_MASK;
658
659 /* 0x1F write to PP_DIV_REG sets max cycle delay */
660 I915_WRITE(pp_div_reg, pp_div | 0x1F);
661 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
662 msleep(intel_dp->panel_power_cycle_delay);
663 }
664
773538e8 665 pps_unlock(intel_dp);
e39b999a 666
01527b31
CT		 667 return 0;
668}
669
4be73780 670static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 671{
30add22d 672 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 673 struct drm_i915_private *dev_priv = dev->dev_private;
674
e39b999a
VS		 675 lockdep_assert_held(&dev_priv->pps_mutex);
676
666a4537 677 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 678 intel_dp->pps_pipe == INVALID_PIPE)
679 return false;
680
bf13e81b 681 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 682}
683
4be73780 684static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 685{
30add22d 686 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 687 struct drm_i915_private *dev_priv = dev->dev_private;
688
e39b999a
VS		 689 lockdep_assert_held(&dev_priv->pps_mutex);
690
666a4537 691 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 692 intel_dp->pps_pipe == INVALID_PIPE)
693 return false;
694
773538e8 695 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 696}
697
9b984dae
KP		 698static void
699intel_dp_check_edp(struct intel_dp *intel_dp)
700{
30add22d 701 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 702 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 703
9b984dae
KP		 704 if (!is_edp(intel_dp))
705 return;
453c5420 706
4be73780 707 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 708 WARN(1, "eDP powered off while attempting aux channel communication.\n");
709 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 710 I915_READ(_pp_stat_reg(intel_dp)),
711 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 712 }
713}
714
9ee32fea
DV		 715static uint32_t
716intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
717{
718 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
719 struct drm_device *dev = intel_dig_port->base.base.dev;
720 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 721 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 722 uint32_t status;
723 bool done;
724
ef04f00d 725#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 726 if (has_aux_irq)
b18ac466 727 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 728 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 729 else
730 done = wait_for_atomic(C, 10) == 0;
731 if (!done)
732 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
733 has_aux_irq);
734#undef C
735
736 return status;
737}
738
6ffb1be7 739static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 740{
174edf1f 741 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
e7dc33f3 742 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
9ee32fea 743
a457f54b
VS		 744 if (index)
745 return 0;
746
ec5b01dd
DL		 747 /*
748 * The clock divider is based off the hrawclk, and would like to run at
a457f54b 749 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
a4fc5ed6 750 */
a457f54b 751 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 752}
753
754static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
755{
756 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 757 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd
DL		 758
759 if (index)
760 return 0;
761
a457f54b
VS		 762 /*
763 * The clock divider is based off the cdclk or PCH rawclk, and would
764 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
765 * divide by 2000 and use that
766 */
e7dc33f3 767 if (intel_dig_port->port == PORT_A)
fce18c4c 768 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
e7dc33f3
VS		 769 else
770 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 771}
772
773static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
774{
775 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 776 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd 777
a457f54b 778 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
2c55c336 779 /* Workaround for non-ULT HSW */
bc86625a
CW		 780 switch (index) {
781 case 0: return 63;
782 case 1: return 72;
783 default: return 0;
784 }
2c55c336 785 }
a457f54b
VS		 786
787 return ilk_get_aux_clock_divider(intel_dp, index);
b84a1cf8
RV		 788}
789
b6b5e383
DL		 790static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
791{
792 /*
793 * SKL doesn't need us to program the AUX clock divider (Hardware will
794 * derive the clock from CDCLK automatically). We still implement the
795 * get_aux_clock_divider vfunc to plug-in into the existing code.
796 */
797 return index ? 0 : 1;
798}
799
6ffb1be7
VS		 800static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
801 bool has_aux_irq,
802 int send_bytes,
803 uint32_t aux_clock_divider)
5ed12a19
DL		 804{
805 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
806 struct drm_device *dev = intel_dig_port->base.base.dev;
807 uint32_t precharge, timeout;
808
809 if (IS_GEN6(dev))
810 precharge = 3;
811 else
812 precharge = 5;
813
f3c6a3a7 814 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
5ed12a19
DL		 815 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
816 else
817 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
818
819 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 820 DP_AUX_CH_CTL_DONE |
5ed12a19 821 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 822 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 823 timeout |
788d4433 824 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 825 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
826 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 827 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 828}
829
b9ca5fad
DL		 830static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
831 bool has_aux_irq,
832 int send_bytes,
833 uint32_t unused)
834{
835 return DP_AUX_CH_CTL_SEND_BUSY |
836 DP_AUX_CH_CTL_DONE |
837 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
838 DP_AUX_CH_CTL_TIME_OUT_ERROR |
839 DP_AUX_CH_CTL_TIME_OUT_1600us |
840 DP_AUX_CH_CTL_RECEIVE_ERROR |
841 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
d4dcbdce 842 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
b9ca5fad
DL		 843 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
844}
845
b84a1cf8
RV		 846static int
847intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 848 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 849 uint8_t *recv, int recv_size)
850{
851 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
852 struct drm_device *dev = intel_dig_port->base.base.dev;
853 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 854 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
bc86625a 855 uint32_t aux_clock_divider;
b84a1cf8
RV		 856 int i, ret, recv_bytes;
857 uint32_t status;
5ed12a19 858 int try, clock = 0;
4e6b788c 859 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 860 bool vdd;
861
773538e8 862 pps_lock(intel_dp);
e39b999a 863
72c3500a
VS		 864 /*
865 * We will be called with VDD already enabled for dpcd/edid/oui reads.
866 * In such cases we want to leave VDD enabled and it's up to upper layers
867 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
868 * ourselves.
869 */
1e0560e0 870 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 871
872 /* dp aux is extremely sensitive to irq latency, hence request the
873 * lowest possible wakeup latency and so prevent the cpu from going into
874 * deep sleep states.
875 */
876 pm_qos_update_request(&dev_priv->pm_qos, 0);
877
878 intel_dp_check_edp(intel_dp);
5eb08b69 879
11bee43e
JB		 880 /* Try to wait for any previous AUX channel activity */
881 for (try = 0; try < 3; try++) {
ef04f00d 882 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 883 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
884 break;
885 msleep(1);
886 }
887
888 if (try == 3) {
02196c77
MK		 889 static u32 last_status = -1;
890 const u32 status = I915_READ(ch_ctl);
891
892 if (status != last_status) {
893 WARN(1, "dp_aux_ch not started status 0x%08x\n",
894 status);
895 last_status = status;
896 }
897
9ee32fea
DV		 898 ret = -EBUSY;
899 goto out;
4f7f7b7e
CW		 900 }
901
46a5ae9f
PZ		 902 /* Only 5 data registers! */
903 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
904 ret = -E2BIG;
905 goto out;
906 }
907
ec5b01dd 908 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 909 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
910 has_aux_irq,
911 send_bytes,
912 aux_clock_divider);
5ed12a19 913
bc86625a
CW		 914 /* Must try at least 3 times according to DP spec */
915 for (try = 0; try < 5; try++) {
916 /* Load the send data into the aux channel data registers */
917 for (i = 0; i < send_bytes; i += 4)
330e20ec 918 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
a4f1289e
RV		 919 intel_dp_pack_aux(send + i,
920 send_bytes - i));
bc86625a
CW		 921
922 /* Send the command and wait for it to complete */
5ed12a19 923 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 924
925 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
926
927 /* Clear done status and any errors */
928 I915_WRITE(ch_ctl,
929 status |
930 DP_AUX_CH_CTL_DONE |
931 DP_AUX_CH_CTL_TIME_OUT_ERROR |
932 DP_AUX_CH_CTL_RECEIVE_ERROR);
933
74ebf294 934 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 935 continue;
74ebf294
TP		 936
937 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
938 * 400us delay required for errors and timeouts
939 * Timeout errors from the HW already meet this
940 * requirement so skip to next iteration
941 */
942 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
943 usleep_range(400, 500);
bc86625a 944 continue;
74ebf294 945 }
bc86625a 946 if (status & DP_AUX_CH_CTL_DONE)
e058c945 947 goto done;
bc86625a 948 }
a4fc5ed6
KP		 949 }
950
a4fc5ed6 951 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 952 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 953 ret = -EBUSY;
954 goto out;
a4fc5ed6
KP		 955 }
956
e058c945 957done:
a4fc5ed6
KP		 958 /* Check for timeout or receive error.
959 * Timeouts occur when the sink is not connected
960 */
a5b3da54 961 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 962 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 963 ret = -EIO;
964 goto out;
a5b3da54 965 }
1ae8c0a5
KP		 966
967 /* Timeouts occur when the device isn't connected, so they're
968 * "normal" -- don't fill the kernel log with these */
a5b3da54 969 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 970 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 971 ret = -ETIMEDOUT;
972 goto out;
a4fc5ed6
KP		 973 }
974
975 /* Unload any bytes sent back from the other side */
976 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
977 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
14e01889
RV		 978
979 /*
980 * By BSpec: "Message sizes of 0 or >20 are not allowed."
981 * We have no idea of what happened so we return -EBUSY so
982 * drm layer takes care for the necessary retries.
983 */
984 if (recv_bytes == 0 || recv_bytes > 20) {
985 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
986 recv_bytes);
987 /*
988 * FIXME: This patch was created on top of a series that
989 * organize the retries at drm level. There EBUSY should
990 * also take care for 1ms wait before retrying.
991 * That aux retries re-org is still needed and after that is
992 * merged we remove this sleep from here.
993 */
994 usleep_range(1000, 1500);
995 ret = -EBUSY;
996 goto out;
997 }
998
a4fc5ed6
KP		 999 if (recv_bytes > recv_size)
1000 recv_bytes = recv_size;
0206e353 1001
4f7f7b7e 1002 for (i = 0; i < recv_bytes; i += 4)
330e20ec 1003 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
a4f1289e 1004 recv + i, recv_bytes - i);
a4fc5ed6 1005
9ee32fea
DV		 1006 ret = recv_bytes;
1007out:
1008 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1009
884f19e9
JN		 1010 if (vdd)
1011 edp_panel_vdd_off(intel_dp, false);
1012
773538e8 1013 pps_unlock(intel_dp);
e39b999a 1014
9ee32fea 1015 return ret;
a4fc5ed6
KP		 1016}
1017
a6c8aff0
JN		 1018#define BARE_ADDRESS_SIZE 3
1019#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 1020static ssize_t
1021intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 1022{
9d1a1031
JN		 1023 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1024 uint8_t txbuf[20], rxbuf[20];
1025 size_t txsize, rxsize;
a4fc5ed6 1026 int ret;
a4fc5ed6 1027
d2d9cbbd
VS		 1028 txbuf[0] = (msg->request << 4) |
1029 ((msg->address >> 16) & 0xf);
1030 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 1031 txbuf[2] = msg->address & 0xff;
1032 txbuf[3] = msg->size - 1;
46a5ae9f 1033
9d1a1031
JN		 1034 switch (msg->request & ~DP_AUX_I2C_MOT) {
1035 case DP_AUX_NATIVE_WRITE:
1036 case DP_AUX_I2C_WRITE:
c1e74122 1037 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
a6c8aff0 1038 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 1039 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 1040
9d1a1031
JN		 1041 if (WARN_ON(txsize > 20))
1042 return -E2BIG;
a4fc5ed6 1043
d81a67cc
ID		 1044 if (msg->buffer)
1045 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1046 else
1047 WARN_ON(msg->size);
a4fc5ed6 1048
9d1a1031
JN		 1049 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1050 if (ret > 0) {
1051 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 1052
a1ddefd8
JN		 1053 if (ret > 1) {
1054 /* Number of bytes written in a short write. */
1055 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1056 } else {
1057 /* Return payload size. */
1058 ret = msg->size;
1059 }
9d1a1031
JN		 1060 }
1061 break;
46a5ae9f 1062
9d1a1031
JN		 1063 case DP_AUX_NATIVE_READ:
1064 case DP_AUX_I2C_READ:
a6c8aff0 1065 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 1066 rxsize = msg->size + 1;
a4fc5ed6 1067
9d1a1031
JN		 1068 if (WARN_ON(rxsize > 20))
1069 return -E2BIG;
a4fc5ed6 1070
9d1a1031
JN		 1071 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1072 if (ret > 0) {
1073 msg->reply = rxbuf[0] >> 4;
1074 /*
1075 * Assume happy day, and copy the data. The caller is
1076 * expected to check msg->reply before touching it.
1077 *
1078 * Return payload size.
1079 */
1080 ret--;
1081 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1082 }
9d1a1031
JN		 1083 break;
1084
1085 default:
1086 ret = -EINVAL;
1087 break;
a4fc5ed6 1088 }
f51a44b9 1089
9d1a1031 1090 return ret;
a4fc5ed6
KP		 1091}
1092
f0f59a00
VS		 1093static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1094 enum port port)
da00bdcf
VS		 1095{
1096 switch (port) {
1097 case PORT_B:
1098 case PORT_C:
1099 case PORT_D:
1100 return DP_AUX_CH_CTL(port);
1101 default:
1102 MISSING_CASE(port);
1103 return DP_AUX_CH_CTL(PORT_B);
1104 }
1105}
1106
f0f59a00
VS		 1107static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1108 enum port port, int index)
330e20ec
VS		 1109{
1110 switch (port) {
1111 case PORT_B:
1112 case PORT_C:
1113 case PORT_D:
1114 return DP_AUX_CH_DATA(port, index);
1115 default:
1116 MISSING_CASE(port);
1117 return DP_AUX_CH_DATA(PORT_B, index);
1118 }
1119}
1120
f0f59a00
VS		 1121static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1122 enum port port)
da00bdcf
VS		 1123{
1124 switch (port) {
1125 case PORT_A:
1126 return DP_AUX_CH_CTL(port);
1127 case PORT_B:
1128 case PORT_C:
1129 case PORT_D:
1130 return PCH_DP_AUX_CH_CTL(port);
1131 default:
1132 MISSING_CASE(port);
1133 return DP_AUX_CH_CTL(PORT_A);
1134 }
1135}
1136
f0f59a00
VS		 1137static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1138 enum port port, int index)
330e20ec
VS		 1139{
1140 switch (port) {
1141 case PORT_A:
1142 return DP_AUX_CH_DATA(port, index);
1143 case PORT_B:
1144 case PORT_C:
1145 case PORT_D:
1146 return PCH_DP_AUX_CH_DATA(port, index);
1147 default:
1148 MISSING_CASE(port);
1149 return DP_AUX_CH_DATA(PORT_A, index);
1150 }
1151}
1152
da00bdcf
VS		 1153/*
1154 * On SKL we don't have Aux for port E so we rely
1155 * on VBT to set a proper alternate aux channel.
1156 */
1157static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1158{
1159 const struct ddi_vbt_port_info *info =
1160 &dev_priv->vbt.ddi_port_info[PORT_E];
1161
1162 switch (info->alternate_aux_channel) {
1163 case DP_AUX_A:
1164 return PORT_A;
1165 case DP_AUX_B:
1166 return PORT_B;
1167 case DP_AUX_C:
1168 return PORT_C;
1169 case DP_AUX_D:
1170 return PORT_D;
1171 default:
1172 MISSING_CASE(info->alternate_aux_channel);
1173 return PORT_A;
1174 }
1175}
1176
f0f59a00
VS		 1177static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1178 enum port port)
da00bdcf
VS		 1179{
1180 if (port == PORT_E)
1181 port = skl_porte_aux_port(dev_priv);
1182
1183 switch (port) {
1184 case PORT_A:
1185 case PORT_B:
1186 case PORT_C:
1187 case PORT_D:
1188 return DP_AUX_CH_CTL(port);
1189 default:
1190 MISSING_CASE(port);
1191 return DP_AUX_CH_CTL(PORT_A);
1192 }
1193}
1194
f0f59a00
VS		 1195static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1196 enum port port, int index)
330e20ec
VS		 1197{
1198 if (port == PORT_E)
1199 port = skl_porte_aux_port(dev_priv);
1200
1201 switch (port) {
1202 case PORT_A:
1203 case PORT_B:
1204 case PORT_C:
1205 case PORT_D:
1206 return DP_AUX_CH_DATA(port, index);
1207 default:
1208 MISSING_CASE(port);
1209 return DP_AUX_CH_DATA(PORT_A, index);
1210 }
1211}
1212
f0f59a00
VS		 1213static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1214 enum port port)
330e20ec
VS		 1215{
1216 if (INTEL_INFO(dev_priv)->gen >= 9)
1217 return skl_aux_ctl_reg(dev_priv, port);
1218 else if (HAS_PCH_SPLIT(dev_priv))
1219 return ilk_aux_ctl_reg(dev_priv, port);
1220 else
1221 return g4x_aux_ctl_reg(dev_priv, port);
1222}
1223
f0f59a00
VS		 1224static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1225 enum port port, int index)
330e20ec
VS		 1226{
1227 if (INTEL_INFO(dev_priv)->gen >= 9)
1228 return skl_aux_data_reg(dev_priv, port, index);
1229 else if (HAS_PCH_SPLIT(dev_priv))
1230 return ilk_aux_data_reg(dev_priv, port, index);
1231 else
1232 return g4x_aux_data_reg(dev_priv, port, index);
1233}
1234
1235static void intel_aux_reg_init(struct intel_dp *intel_dp)
1236{
1237 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1238 enum port port = dp_to_dig_port(intel_dp)->port;
1239 int i;
1240
1241 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1242 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1243 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1244}
1245
9d1a1031 1246static void
a121f4e5
VS		 1247intel_dp_aux_fini(struct intel_dp *intel_dp)
1248{
a121f4e5
VS		 1249 kfree(intel_dp->aux.name);
1250}
1251
1252static int
9d1a1031
JN		 1253intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1254{
33ad6626
JN		 1255 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1256 enum port port = intel_dig_port->port;
ab2c0672
DA		 1257 int ret;
1258
330e20ec 1259 intel_aux_reg_init(intel_dp);
8316f337 1260
a121f4e5
VS		 1261 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1262 if (!intel_dp->aux.name)
1263 return -ENOMEM;
1264
4d32c0d8 1265 intel_dp->aux.dev = connector->base.kdev;
9d1a1031 1266 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1267
a121f4e5
VS		 1268 DRM_DEBUG_KMS("registering %s bus for %s\n",
1269 intel_dp->aux.name,
0b99836f 1270 connector->base.kdev->kobj.name);
8316f337 1271
4f71d0cb 1272 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1273 if (ret < 0) {
4f71d0cb 1274 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
a121f4e5
VS		 1275 intel_dp->aux.name, ret);
1276 kfree(intel_dp->aux.name);
1277 return ret;
ab2c0672 1278 }
8a5e6aeb 1279
a121f4e5 1280 return 0;
a4fc5ed6
KP		 1281}
1282
fc0f8e25 1283static int
12f6a2e2 1284intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1285{
94ca719e
VS		 1286 if (intel_dp->num_sink_rates) {
1287 *sink_rates = intel_dp->sink_rates;
1288 return intel_dp->num_sink_rates;
fc0f8e25 1289 }
12f6a2e2
VS		 1290
1291 *sink_rates = default_rates;
1292
1293 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1294}
1295
e588fa18 1296bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
ed63baaf 1297{
e588fa18
ACO		 1298 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1299 struct drm_device *dev = dig_port->base.base.dev;
1300
ed63baaf 1301 /* WaDisableHBR2:skl */
e87a005d 1302 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
ed63baaf
TS		 1303 return false;
1304
1305 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1306 (INTEL_INFO(dev)->gen >= 9))
1307 return true;
1308 else
1309 return false;
1310}
1311
a8f3ef61 1312static int
e588fa18 1313intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
a8f3ef61 1314{
e588fa18
ACO		 1315 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1316 struct drm_device *dev = dig_port->base.base.dev;
af7080f5
TS		 1317 int size;
1318
64987fc5
SJ		 1319 if (IS_BROXTON(dev)) {
1320 *source_rates = bxt_rates;
af7080f5 1321 size = ARRAY_SIZE(bxt_rates);
ef11bdb3 1322 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
637a9c63 1323 *source_rates = skl_rates;
af7080f5
TS		 1324 size = ARRAY_SIZE(skl_rates);
1325 } else {
1326 *source_rates = default_rates;
1327 size = ARRAY_SIZE(default_rates);
a8f3ef61 1328 }
636280ba 1329
ed63baaf 1330 /* This depends on the fact that 5.4 is last value in the array */
e588fa18 1331 if (!intel_dp_source_supports_hbr2(intel_dp))
af7080f5 1332 size--;
636280ba 1333
af7080f5 1334 return size;
a8f3ef61
SJ		 1335}
1336
c6bb3538
DV		 1337static void
1338intel_dp_set_clock(struct intel_encoder *encoder,
840b32b7 1339 struct intel_crtc_state *pipe_config)
c6bb3538
DV		 1340{
1341 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1342 const struct dp_link_dpll *divisor = NULL;
1343 int i, count = 0;
c6bb3538
DV		 1344
1345 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1346 divisor = gen4_dpll;
1347 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1348 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1349 divisor = pch_dpll;
1350 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1351 } else if (IS_CHERRYVIEW(dev)) {
1352 divisor = chv_dpll;
1353 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1354 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1355 divisor = vlv_dpll;
1356 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1357 }
9dd4ffdf
CML		 1358
1359 if (divisor && count) {
1360 for (i = 0; i < count; i++) {
840b32b7 1361 if (pipe_config->port_clock == divisor[i].clock) {
9dd4ffdf
CML		 1362 pipe_config->dpll = divisor[i].dpll;
1363 pipe_config->clock_set = true;
1364 break;
1365 }
1366 }
c6bb3538
DV		 1367 }
1368}
1369
2ecae76a
VS		 1370static int intersect_rates(const int *source_rates, int source_len,
1371 const int *sink_rates, int sink_len,
94ca719e 1372 int *common_rates)
a8f3ef61
SJ		 1373{
1374 int i = 0, j = 0, k = 0;
1375
a8f3ef61
SJ		 1376 while (i < source_len && j < sink_len) {
1377 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1378 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1379 return k;
94ca719e 1380 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1381 ++k;
1382 ++i;
1383 ++j;
1384 } else if (source_rates[i] < sink_rates[j]) {
1385 ++i;
1386 } else {
1387 ++j;
1388 }
1389 }
1390 return k;
1391}
1392
94ca719e
VS		 1393static int intel_dp_common_rates(struct intel_dp *intel_dp,
1394 int *common_rates)
2ecae76a 1395{
2ecae76a
VS		 1396 const int *source_rates, *sink_rates;
1397 int source_len, sink_len;
1398
1399 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
e588fa18 1400 source_len = intel_dp_source_rates(intel_dp, &source_rates);
2ecae76a
VS		 1401
1402 return intersect_rates(source_rates, source_len,
1403 sink_rates, sink_len,
94ca719e 1404 common_rates);
2ecae76a
VS		 1405}
1406
0336400e
VS		 1407static void snprintf_int_array(char *str, size_t len,
1408 const int *array, int nelem)
1409{
1410 int i;
1411
1412 str[0] = '\0';
1413
1414 for (i = 0; i < nelem; i++) {
b2f505be 1415 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1416 if (r >= len)
1417 return;
1418 str += r;
1419 len -= r;
1420 }
1421}
1422
1423static void intel_dp_print_rates(struct intel_dp *intel_dp)
1424{
0336400e 1425 const int *source_rates, *sink_rates;
94ca719e
VS		 1426 int source_len, sink_len, common_len;
1427 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1428 char str[128]; /* FIXME: too big for stack? */
1429
1430 if ((drm_debug & DRM_UT_KMS) == 0)
1431 return;
1432
e588fa18 1433 source_len = intel_dp_source_rates(intel_dp, &source_rates);
0336400e
VS		 1434 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1435 DRM_DEBUG_KMS("source rates: %s\n", str);
1436
1437 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1438 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1439 DRM_DEBUG_KMS("sink rates: %s\n", str);
1440
94ca719e
VS		 1441 common_len = intel_dp_common_rates(intel_dp, common_rates);
1442 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1443 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1444}
1445
f4896f15 1446static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1447{
1448 int i = 0;
1449
1450 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1451 if (find == rates[i])
1452 break;
1453
1454 return i;
1455}
1456
50fec21a
VS		 1457int
1458intel_dp_max_link_rate(struct intel_dp *intel_dp)
1459{
1460 int rates[DP_MAX_SUPPORTED_RATES] = {};
1461 int len;
1462
94ca719e 1463 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1464 if (WARN_ON(len <= 0))
1465 return 162000;
1466
1467 return rates[rate_to_index(0, rates) - 1];
1468}
1469
ed4e9c1d
VS		 1470int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1471{
94ca719e 1472 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1473}
1474
94223d04
ACO		 1475void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1476 uint8_t *link_bw, uint8_t *rate_select)
04a60f9f
VS		 1477{
1478 if (intel_dp->num_sink_rates) {
1479 *link_bw = 0;
1480 *rate_select =
1481 intel_dp_rate_select(intel_dp, port_clock);
1482 } else {
1483 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1484 *rate_select = 0;
1485 }
1486}
1487
00c09d70 1488bool
5bfe2ac0 1489intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1490 struct intel_crtc_state *pipe_config)
a4fc5ed6 1491{
5bfe2ac0 1492 struct drm_device *dev = encoder->base.dev;
36008365 1493 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1494 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1495 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1496 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1497 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1498 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1499 int lane_count, clock;
56071a20 1500 int min_lane_count = 1;
eeb6324d 1501 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1502 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1503 int min_clock = 0;
a8f3ef61 1504 int max_clock;
083f9560 1505 int bpp, mode_rate;
ff9a6750 1506 int link_avail, link_clock;
94ca719e
VS		 1507 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1508 int common_len;
04a60f9f 1509 uint8_t link_bw, rate_select;
a8f3ef61 1510
94ca719e 1511 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1512
1513 /* No common link rates between source and sink */
94ca719e 1514 WARN_ON(common_len <= 0);
a8f3ef61 1515
94ca719e 1516 max_clock = common_len - 1;
a4fc5ed6 1517
bc7d38a4 1518 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1519 pipe_config->has_pch_encoder = true;
1520
03afc4a2 1521 pipe_config->has_dp_encoder = true;
f769cd24 1522 pipe_config->has_drrs = false;
9fcb1704 1523 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1524
dd06f90e
JN		 1525 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1526 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1527 adjusted_mode);
a1b2278e
CK		 1528
1529 if (INTEL_INFO(dev)->gen >= 9) {
1530 int ret;
e435d6e5 1531 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1532 if (ret)
1533 return ret;
1534 }
1535
b5667627 1536 if (HAS_GMCH_DISPLAY(dev))
2dd24552
JB		 1537 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1538 intel_connector->panel.fitting_mode);
1539 else
b074cec8
JB		 1540 intel_pch_panel_fitting(intel_crtc, pipe_config,
1541 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1542 }
1543
cb1793ce 1544 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1545 return false;
1546
083f9560 1547 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1548 "max bw %d pixel clock %iKHz\n",
94ca719e 1549 max_lane_count, common_rates[max_clock],
241bfc38 1550 adjusted_mode->crtc_clock);
083f9560 1551
36008365
DV		 1552 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1553 * bpc in between. */
3e7ca985 1554 bpp = pipe_config->pipe_bpp;
56071a20 1555 if (is_edp(intel_dp)) {
22ce5628
TS		 1556
1557 /* Get bpp from vbt only for panels that dont have bpp in edid */
1558 if (intel_connector->base.display_info.bpc == 0 &&
6aa23e65 1559 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
56071a20 1560 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
6aa23e65
JN		 1561 dev_priv->vbt.edp.bpp);
1562 bpp = dev_priv->vbt.edp.bpp;
56071a20
JN		 1563 }
1564
344c5bbc
JN		 1565 /*
1566 * Use the maximum clock and number of lanes the eDP panel
1567 * advertizes being capable of. The panels are generally
1568 * designed to support only a single clock and lane
1569 * configuration, and typically these values correspond to the
1570 * native resolution of the panel.
1571 */
1572 min_lane_count = max_lane_count;
1573 min_clock = max_clock;
7984211e 1574 }
657445fe 1575
36008365 1576 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1577 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1578 bpp);
36008365 1579
c6930992 1580 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1581 for (lane_count = min_lane_count;
1582 lane_count <= max_lane_count;
1583 lane_count <<= 1) {
1584
94ca719e 1585 link_clock = common_rates[clock];
36008365
DV		 1586 link_avail = intel_dp_max_data_rate(link_clock,
1587 lane_count);
1588
1589 if (mode_rate <= link_avail) {
1590 goto found;
1591 }
1592 }
1593 }
1594 }
c4867936 1595
36008365 1596 return false;
3685a8f3 1597
36008365 1598found:
55bc60db
VS		 1599 if (intel_dp->color_range_auto) {
1600 /*
1601 * See:
1602 * CEA-861-E - 5.1 Default Encoding Parameters
1603 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1604 */
0f2a2a75
VS		 1605 pipe_config->limited_color_range =
1606 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1607 } else {
1608 pipe_config->limited_color_range =
1609 intel_dp->limited_color_range;
55bc60db
VS		 1610 }
1611
90a6b7b0 1612 pipe_config->lane_count = lane_count;
a8f3ef61 1613
657445fe 1614 pipe_config->pipe_bpp = bpp;
94ca719e 1615 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1616
04a60f9f
VS		 1617 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1618 &link_bw, &rate_select);
1619
1620 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1621 link_bw, rate_select, pipe_config->lane_count,
ff9a6750 1622 pipe_config->port_clock, bpp);
36008365
DV		 1623 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1624 mode_rate, link_avail);
a4fc5ed6 1625
03afc4a2 1626 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1627 adjusted_mode->crtc_clock,
1628 pipe_config->port_clock,
03afc4a2 1629 &pipe_config->dp_m_n);
9d1a455b 1630
439d7ac0 1631 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1632 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1633 pipe_config->has_drrs = true;
439d7ac0
PB		 1634 intel_link_compute_m_n(bpp, lane_count,
1635 intel_connector->panel.downclock_mode->clock,
1636 pipe_config->port_clock,
1637 &pipe_config->dp_m2_n2);
1638 }
1639
14d41b3b
VS		 1640 /*
1641 * DPLL0 VCO may need to be adjusted to get the correct
1642 * clock for eDP. This will affect cdclk as well.
1643 */
1644 if (is_edp(intel_dp) &&
1645 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1646 int vco;
1647
1648 switch (pipe_config->port_clock / 2) {
1649 case 108000:
1650 case 216000:
63911d72 1651 vco = 8640000;
14d41b3b
VS		 1652 break;
1653 default:
63911d72 1654 vco = 8100000;
14d41b3b
VS		 1655 break;
1656 }
1657
1658 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1659 }
1660
a3c988ea 1661 if (!HAS_DDI(dev))
840b32b7 1662 intel_dp_set_clock(encoder, pipe_config);
c6bb3538 1663
03afc4a2 1664 return true;
a4fc5ed6
KP		 1665}
1666
901c2daf
VS		 1667void intel_dp_set_link_params(struct intel_dp *intel_dp,
1668 const struct intel_crtc_state *pipe_config)
1669{
1670 intel_dp->link_rate = pipe_config->port_clock;
1671 intel_dp->lane_count = pipe_config->lane_count;
1672}
1673
8ac33ed3 1674static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1675{
b934223d 1676 struct drm_device *dev = encoder->base.dev;
417e822d 1677 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1678 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1679 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1680 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
7c5f93b0 1681 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1682
901c2daf
VS		 1683 intel_dp_set_link_params(intel_dp, crtc->config);
1684
417e822d 1685 /*
1a2eb460 1686 * There are four kinds of DP registers:
417e822d
KP		 1687 *
1688 * IBX PCH
1a2eb460
KP		 1689 * SNB CPU
1690 * IVB CPU
417e822d
KP		 1691 * CPT PCH
1692 *
1693 * IBX PCH and CPU are the same for almost everything,
1694 * except that the CPU DP PLL is configured in this
1695 * register
1696 *
1697 * CPT PCH is quite different, having many bits moved
1698 * to the TRANS_DP_CTL register instead. That
1699 * configuration happens (oddly) in ironlake_pch_enable
1700 */
9c9e7927 1701
417e822d
KP		 1702 /* Preserve the BIOS-computed detected bit. This is
1703 * supposed to be read-only.
1704 */
1705 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1706
417e822d 1707 /* Handle DP bits in common between all three register formats */
417e822d 1708 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
90a6b7b0 1709 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
a4fc5ed6 1710
417e822d 1711 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1712
39e5fa88 1713 if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1714 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1715 intel_dp->DP |= DP_SYNC_HS_HIGH;
1716 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1717 intel_dp->DP |= DP_SYNC_VS_HIGH;
1718 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1719
6aba5b6c 1720 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1721 intel_dp->DP |= DP_ENHANCED_FRAMING;
1722
7c62a164 1723 intel_dp->DP |= crtc->pipe << 29;
39e5fa88 1724 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
e3ef4479
VS		 1725 u32 trans_dp;
1726
39e5fa88 1727 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1728
1729 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1730 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1731 trans_dp |= TRANS_DP_ENH_FRAMING;
1732 else
1733 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1734 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1735 } else {
0f2a2a75 1736 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 1737 !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
0f2a2a75 1738 intel_dp->DP |= DP_COLOR_RANGE_16_235;
417e822d
KP		 1739
1740 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1741 intel_dp->DP |= DP_SYNC_HS_HIGH;
1742 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1743 intel_dp->DP |= DP_SYNC_VS_HIGH;
1744 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1745
6aba5b6c 1746 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1747 intel_dp->DP |= DP_ENHANCED_FRAMING;
1748
39e5fa88 1749 if (IS_CHERRYVIEW(dev))
44f37d1f 1750 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1751 else if (crtc->pipe == PIPE_B)
1752 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1753 }
a4fc5ed6
KP		 1754}
1755
ffd6749d
PZ		 1756#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1757#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1758
1a5ef5b7
PZ		 1759#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1760#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1761
ffd6749d
PZ		 1762#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1763#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1764
de9c1b6b
ID		 1765static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1766 struct intel_dp *intel_dp);
1767
4be73780 1768static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1769 u32 mask,
1770 u32 value)
bd943159 1771{
30add22d 1772 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1773 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 1774 i915_reg_t pp_stat_reg, pp_ctrl_reg;
453c5420 1775
e39b999a
VS		 1776 lockdep_assert_held(&dev_priv->pps_mutex);
1777
de9c1b6b
ID		 1778 intel_pps_verify_state(dev_priv, intel_dp);
1779
bf13e81b
JN		 1780 pp_stat_reg = _pp_stat_reg(intel_dp);
1781 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1782
99ea7127 1783 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1784 mask, value,
1785 I915_READ(pp_stat_reg),
1786 I915_READ(pp_ctrl_reg));
32ce697c 1787
3f177625
TU		 1788 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value,
1789 5 * USEC_PER_SEC, 10 * USEC_PER_MSEC))
99ea7127 1790 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1791 I915_READ(pp_stat_reg),
1792 I915_READ(pp_ctrl_reg));
54c136d4
CW		 1793
1794 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1795}
32ce697c 1796
4be73780 1797static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1798{
1799 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1800 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1801}
1802
4be73780 1803static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1804{
1805 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1806 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1807}
1808
4be73780 1809static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127 1810{
d28d4731
AK		 1811 ktime_t panel_power_on_time;
1812 s64 panel_power_off_duration;
1813
99ea7127 1814 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c 1815
d28d4731
AK		 1816 /* take the difference of currrent time and panel power off time
1817 * and then make panel wait for t11_t12 if needed. */
1818 panel_power_on_time = ktime_get_boottime();
1819 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1820
dce56b3c
PZ		 1821 /* When we disable the VDD override bit last we have to do the manual
1822 * wait. */
d28d4731
AK		 1823 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1824 wait_remaining_ms_from_jiffies(jiffies,
1825 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
dce56b3c 1826
4be73780 1827 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1828}
1829
4be73780 1830static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1831{
1832 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1833 intel_dp->backlight_on_delay);
1834}
1835
4be73780 1836static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1837{
1838 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1839 intel_dp->backlight_off_delay);
1840}
99ea7127 1841
832dd3c1
KP		 1842/* Read the current pp_control value, unlocking the register if it
1843 * is locked
1844 */
1845
453c5420 1846static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1847{
453c5420
JB		 1848 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1849 struct drm_i915_private *dev_priv = dev->dev_private;
1850 u32 control;
832dd3c1 1851
e39b999a
VS		 1852 lockdep_assert_held(&dev_priv->pps_mutex);
1853
bf13e81b 1854 control = I915_READ(_pp_ctrl_reg(intel_dp));
b0a08bec
VK		 1855 if (!IS_BROXTON(dev)) {
1856 control &= ~PANEL_UNLOCK_MASK;
1857 control |= PANEL_UNLOCK_REGS;
1858 }
832dd3c1 1859 return control;
bd943159
KP		 1860}
1861
951468f3
VS		 1862/*
1863 * Must be paired with edp_panel_vdd_off().
1864 * Must hold pps_mutex around the whole on/off sequence.
1865 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1866 */
1e0560e0 1867static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1868{
30add22d 1869 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1870 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1871 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1872 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1873 enum intel_display_power_domain power_domain;
5d613501 1874 u32 pp;
f0f59a00 1875 i915_reg_t pp_stat_reg, pp_ctrl_reg;
adddaaf4 1876 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1877
e39b999a
VS		 1878 lockdep_assert_held(&dev_priv->pps_mutex);
1879
97af61f5 1880 if (!is_edp(intel_dp))
adddaaf4 1881 return false;
bd943159 1882
2c623c11 1883 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1884 intel_dp->want_panel_vdd = true;
99ea7127 1885
4be73780 1886 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1887 return need_to_disable;
b0665d57 1888
25f78f58 1889 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 1890 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1891
3936fcf4
VS		 1892 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1893 port_name(intel_dig_port->port));
bd943159 1894
4be73780
DV		 1895 if (!edp_have_panel_power(intel_dp))
1896 wait_panel_power_cycle(intel_dp);
99ea7127 1897
453c5420 1898 pp = ironlake_get_pp_control(intel_dp);
5d613501 1899 pp |= EDP_FORCE_VDD;
ebf33b18 1900
bf13e81b
JN		 1901 pp_stat_reg = _pp_stat_reg(intel_dp);
1902 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1903
1904 I915_WRITE(pp_ctrl_reg, pp);
1905 POSTING_READ(pp_ctrl_reg);
1906 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1907 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1908 /*
1909 * If the panel wasn't on, delay before accessing aux channel
1910 */
4be73780 1911 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1912 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1913 port_name(intel_dig_port->port));
f01eca2e 1914 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1915 }
adddaaf4
JN		 1916
1917 return need_to_disable;
1918}
1919
951468f3
VS		 1920/*
1921 * Must be paired with intel_edp_panel_vdd_off() or
1922 * intel_edp_panel_off().
1923 * Nested calls to these functions are not allowed since
1924 * we drop the lock. Caller must use some higher level
1925 * locking to prevent nested calls from other threads.
1926 */
b80d6c78 1927void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1928{
c695b6b6 1929 bool vdd;
adddaaf4 1930
c695b6b6
VS		 1931 if (!is_edp(intel_dp))
1932 return;
1933
773538e8 1934 pps_lock(intel_dp);
c695b6b6 1935 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1936 pps_unlock(intel_dp);
c695b6b6 1937
e2c719b7 1938 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1939 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1940}
1941
4be73780 1942static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1943{
30add22d 1944 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1945 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1946 struct intel_digital_port *intel_dig_port =
1947 dp_to_dig_port(intel_dp);
1948 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1949 enum intel_display_power_domain power_domain;
5d613501 1950 u32 pp;
f0f59a00 1951 i915_reg_t pp_stat_reg, pp_ctrl_reg;
5d613501 1952
e39b999a 1953 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1954
15e899a0 1955 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1956
15e899a0 1957 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1958 return;
b0665d57 1959
3936fcf4
VS		 1960 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1961 port_name(intel_dig_port->port));
bd943159 1962
be2c9196
VS		 1963 pp = ironlake_get_pp_control(intel_dp);
1964 pp &= ~EDP_FORCE_VDD;
453c5420 1965
be2c9196
VS		 1966 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1967 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1968
be2c9196
VS		 1969 I915_WRITE(pp_ctrl_reg, pp);
1970 POSTING_READ(pp_ctrl_reg);
90791a5c 1971
be2c9196
VS		 1972 /* Make sure sequencer is idle before allowing subsequent activity */
1973 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1974 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1975
be2c9196 1976 if ((pp & POWER_TARGET_ON) == 0)
d28d4731 1977 intel_dp->panel_power_off_time = ktime_get_boottime();
e9cb81a2 1978
25f78f58 1979 power_domain = intel_display_port_aux_power_domain(intel_encoder);
be2c9196 1980 intel_display_power_put(dev_priv, power_domain);
bd943159 1981}
5d613501 1982
4be73780 1983static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1984{
1985 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1986 struct intel_dp, panel_vdd_work);
bd943159 1987
773538e8 1988 pps_lock(intel_dp);
15e899a0
VS		 1989 if (!intel_dp->want_panel_vdd)
1990 edp_panel_vdd_off_sync(intel_dp);
773538e8 1991 pps_unlock(intel_dp);
bd943159
KP		 1992}
1993
aba86890
ID		 1994static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1995{
1996 unsigned long delay;
1997
1998 /*
1999 * Queue the timer to fire a long time from now (relative to the power
2000 * down delay) to keep the panel power up across a sequence of
2001 * operations.
2002 */
2003 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2004 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2005}
2006
951468f3
VS		 2007/*
2008 * Must be paired with edp_panel_vdd_on().
2009 * Must hold pps_mutex around the whole on/off sequence.
2010 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2011 */
4be73780 2012static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 2013{
e39b999a
VS		 2014 struct drm_i915_private *dev_priv =
2015 intel_dp_to_dev(intel_dp)->dev_private;
2016
2017 lockdep_assert_held(&dev_priv->pps_mutex);
2018
97af61f5
KP		 2019 if (!is_edp(intel_dp))
2020 return;
5d613501 2021
e2c719b7 2022 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 2023 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 2024
bd943159
KP		 2025 intel_dp->want_panel_vdd = false;
2026
aba86890 2027 if (sync)
4be73780 2028 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 2029 else
2030 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 2031}
2032
9f0fb5be 2033static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 2034{
30add22d 2035 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 2036 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 2037 u32 pp;
f0f59a00 2038 i915_reg_t pp_ctrl_reg;
9934c132 2039
9f0fb5be
VS		 2040 lockdep_assert_held(&dev_priv->pps_mutex);
2041
97af61f5 2042 if (!is_edp(intel_dp))
bd943159 2043 return;
99ea7127 2044
3936fcf4
VS		 2045 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2046 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 2047
e7a89ace
VS		 2048 if (WARN(edp_have_panel_power(intel_dp),
2049 "eDP port %c panel power already on\n",
2050 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 2051 return;
9934c132 2052
4be73780 2053 wait_panel_power_cycle(intel_dp);
37c6c9b0 2054
bf13e81b 2055 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2056 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 2057 if (IS_GEN5(dev)) {
2058 /* ILK workaround: disable reset around power sequence */
2059 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 2060 I915_WRITE(pp_ctrl_reg, pp);
2061 POSTING_READ(pp_ctrl_reg);
05ce1a49 2062 }
37c6c9b0 2063
1c0ae80a 2064 pp |= POWER_TARGET_ON;
99ea7127
KP		 2065 if (!IS_GEN5(dev))
2066 pp |= PANEL_POWER_RESET;
2067
453c5420
JB		 2068 I915_WRITE(pp_ctrl_reg, pp);
2069 POSTING_READ(pp_ctrl_reg);
9934c132 2070
4be73780 2071 wait_panel_on(intel_dp);
dce56b3c 2072 intel_dp->last_power_on = jiffies;
9934c132 2073
05ce1a49
KP		 2074 if (IS_GEN5(dev)) {
2075 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 2076 I915_WRITE(pp_ctrl_reg, pp);
2077 POSTING_READ(pp_ctrl_reg);
05ce1a49 2078 }
9f0fb5be 2079}
e39b999a 2080
9f0fb5be
VS		 2081void intel_edp_panel_on(struct intel_dp *intel_dp)
2082{
2083 if (!is_edp(intel_dp))
2084 return;
2085
2086 pps_lock(intel_dp);
2087 edp_panel_on(intel_dp);
773538e8 2088 pps_unlock(intel_dp);
9934c132
JB		 2089}
2090
9f0fb5be
VS		 2091
2092static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 2093{
4e6e1a54
ID		 2094 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2095 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 2096 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 2097 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 2098 enum intel_display_power_domain power_domain;
99ea7127 2099 u32 pp;
f0f59a00 2100 i915_reg_t pp_ctrl_reg;
9934c132 2101
9f0fb5be
VS		 2102 lockdep_assert_held(&dev_priv->pps_mutex);
2103
97af61f5
KP		 2104 if (!is_edp(intel_dp))
2105 return;
37c6c9b0 2106
3936fcf4
VS		 2107 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2108 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 2109
3936fcf4
VS		 2110 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2111 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 2112
453c5420 2113 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 2114 /* We need to switch off panel power _and_ force vdd, for otherwise some
2115 * panels get very unhappy and cease to work. */
b3064154
PJ		 2116 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2117 EDP_BLC_ENABLE);
453c5420 2118
bf13e81b 2119 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2120
849e39f5
PZ		 2121 intel_dp->want_panel_vdd = false;
2122
453c5420
JB		 2123 I915_WRITE(pp_ctrl_reg, pp);
2124 POSTING_READ(pp_ctrl_reg);
9934c132 2125
d28d4731 2126 intel_dp->panel_power_off_time = ktime_get_boottime();
4be73780 2127 wait_panel_off(intel_dp);
849e39f5
PZ		 2128
2129 /* We got a reference when we enabled the VDD. */
25f78f58 2130 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 2131 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 2132}
e39b999a 2133
9f0fb5be
VS		 2134void intel_edp_panel_off(struct intel_dp *intel_dp)
2135{
2136 if (!is_edp(intel_dp))
2137 return;
e39b999a 2138
9f0fb5be
VS		 2139 pps_lock(intel_dp);
2140 edp_panel_off(intel_dp);
773538e8 2141 pps_unlock(intel_dp);
9934c132
JB		 2142}
2143
1250d107
JN		 2144/* Enable backlight in the panel power control. */
2145static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2146{
da63a9f2
PZ		 2147 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2148 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 2149 struct drm_i915_private *dev_priv = dev->dev_private;
2150 u32 pp;
f0f59a00 2151 i915_reg_t pp_ctrl_reg;
32f9d658 2152
01cb9ea6
JB		 2153 /*
2154 * If we enable the backlight right away following a panel power
2155 * on, we may see slight flicker as the panel syncs with the eDP
2156 * link. So delay a bit to make sure the image is solid before
2157 * allowing it to appear.
2158 */
4be73780 2159 wait_backlight_on(intel_dp);
e39b999a 2160
773538e8 2161 pps_lock(intel_dp);
e39b999a 2162
453c5420 2163 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2164 pp |= EDP_BLC_ENABLE;
453c5420 2165
bf13e81b 2166 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2167
2168 I915_WRITE(pp_ctrl_reg, pp);
2169 POSTING_READ(pp_ctrl_reg);
e39b999a 2170
773538e8 2171 pps_unlock(intel_dp);
32f9d658
ZW		 2172}
2173
1250d107
JN		 2174/* Enable backlight PWM and backlight PP control. */
2175void intel_edp_backlight_on(struct intel_dp *intel_dp)
2176{
2177 if (!is_edp(intel_dp))
2178 return;
2179
2180 DRM_DEBUG_KMS("\n");
2181
2182 intel_panel_enable_backlight(intel_dp->attached_connector);
2183 _intel_edp_backlight_on(intel_dp);
2184}
2185
2186/* Disable backlight in the panel power control. */
2187static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2188{
30add22d 2189 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 2190 struct drm_i915_private *dev_priv = dev->dev_private;
2191 u32 pp;
f0f59a00 2192 i915_reg_t pp_ctrl_reg;
32f9d658 2193
f01eca2e
KP		 2194 if (!is_edp(intel_dp))
2195 return;
2196
773538e8 2197 pps_lock(intel_dp);
e39b999a 2198
453c5420 2199 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2200 pp &= ~EDP_BLC_ENABLE;
453c5420 2201
bf13e81b 2202 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2203
2204 I915_WRITE(pp_ctrl_reg, pp);
2205 POSTING_READ(pp_ctrl_reg);
f7d2323c 2206
773538e8 2207 pps_unlock(intel_dp);
e39b999a
VS		 2208
2209 intel_dp->last_backlight_off = jiffies;
f7d2323c 2210 edp_wait_backlight_off(intel_dp);
1250d107 2211}
f7d2323c 2212
1250d107
JN		 2213/* Disable backlight PP control and backlight PWM. */
2214void intel_edp_backlight_off(struct intel_dp *intel_dp)
2215{
2216 if (!is_edp(intel_dp))
2217 return;
2218
2219 DRM_DEBUG_KMS("\n");
f7d2323c 2220
1250d107 2221 _intel_edp_backlight_off(intel_dp);
f7d2323c 2222 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2223}
a4fc5ed6 2224
73580fb7
JN		 2225/*
2226 * Hook for controlling the panel power control backlight through the bl_power
2227 * sysfs attribute. Take care to handle multiple calls.
2228 */
2229static void intel_edp_backlight_power(struct intel_connector *connector,
2230 bool enable)
2231{
2232 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2233 bool is_enabled;
2234
773538e8 2235 pps_lock(intel_dp);
e39b999a 2236 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2237 pps_unlock(intel_dp);
73580fb7
JN		 2238
2239 if (is_enabled == enable)
2240 return;
2241
23ba9373
JN		 2242 DRM_DEBUG_KMS("panel power control backlight %s\n",
2243 enable ? "enable" : "disable");
73580fb7
JN		 2244
2245 if (enable)
2246 _intel_edp_backlight_on(intel_dp);
2247 else
2248 _intel_edp_backlight_off(intel_dp);
2249}
2250
64e1077a
VS		 2251static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2252{
2253 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2254 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2255 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2256
2257 I915_STATE_WARN(cur_state != state,
2258 "DP port %c state assertion failure (expected %s, current %s)\n",
2259 port_name(dig_port->port),
87ad3212 2260 onoff(state), onoff(cur_state));
64e1077a
VS		 2261}
2262#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2263
2264static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2265{
2266 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2267
2268 I915_STATE_WARN(cur_state != state,
2269 "eDP PLL state assertion failure (expected %s, current %s)\n",
87ad3212 2270 onoff(state), onoff(cur_state));
64e1077a
VS		 2271}
2272#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2273#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2274
2bd2ad64 2275static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2276{
da63a9f2 2277 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2278 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2279 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2280
64e1077a
VS		 2281 assert_pipe_disabled(dev_priv, crtc->pipe);
2282 assert_dp_port_disabled(intel_dp);
2283 assert_edp_pll_disabled(dev_priv);
2bd2ad64 2284
abfce949
VS		 2285 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2286 crtc->config->port_clock);
2287
2288 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2289
2290 if (crtc->config->port_clock == 162000)
2291 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2292 else
2293 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2294
2295 I915_WRITE(DP_A, intel_dp->DP);
2296 POSTING_READ(DP_A);
2297 udelay(500);
2298
6b23f3e8
VS		 2299 /*
2300 * [DevILK] Work around required when enabling DP PLL
2301 * while a pipe is enabled going to FDI:
2302 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2303 * 2. Program DP PLL enable
2304 */
2305 if (IS_GEN5(dev_priv))
2306 intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe);
2307
0767935e 2308 intel_dp->DP |= DP_PLL_ENABLE;
6fec7662 2309
0767935e 2310 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2311 POSTING_READ(DP_A);
2312 udelay(200);
d240f20f
JB		 2313}
2314
2bd2ad64 2315static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2316{
da63a9f2 2317 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2318 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2319 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2320
64e1077a
VS		 2321 assert_pipe_disabled(dev_priv, crtc->pipe);
2322 assert_dp_port_disabled(intel_dp);
2323 assert_edp_pll_enabled(dev_priv);
2bd2ad64 2324
abfce949
VS		 2325 DRM_DEBUG_KMS("disabling eDP PLL\n");
2326
6fec7662 2327 intel_dp->DP &= ~DP_PLL_ENABLE;
0767935e 2328
6fec7662 2329 I915_WRITE(DP_A, intel_dp->DP);
1af5fa1b 2330 POSTING_READ(DP_A);
d240f20f
JB		 2331 udelay(200);
2332}
2333
c7ad3810 2334/* If the sink supports it, try to set the power state appropriately */
c19b0669 2335void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2336{
2337 int ret, i;
2338
2339 /* Should have a valid DPCD by this point */
2340 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2341 return;
2342
2343 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2344 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2345 DP_SET_POWER_D3);
c7ad3810
JB		 2346 } else {
2347 /*
2348 * When turning on, we need to retry for 1ms to give the sink
2349 * time to wake up.
2350 */
2351 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2352 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2353 DP_SET_POWER_D0);
c7ad3810
JB		 2354 if (ret == 1)
2355 break;
2356 msleep(1);
2357 }
2358 }
f9cac721
JN		 2359
2360 if (ret != 1)
2361 DRM_DEBUG_KMS("failed to %s sink power state\n",
2362 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2363}
2364
19d8fe15
DV		 2365static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2366 enum pipe *pipe)
d240f20f 2367{
19d8fe15 2368 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2369 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2370 struct drm_device *dev = encoder->base.dev;
2371 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2372 enum intel_display_power_domain power_domain;
2373 u32 tmp;
6fa9a5ec 2374 bool ret;
6d129bea
ID		 2375
2376 power_domain = intel_display_port_power_domain(encoder);
6fa9a5ec 2377 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 2378 return false;
2379
6fa9a5ec
ID		 2380 ret = false;
2381
6d129bea 2382 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2383
2384 if (!(tmp & DP_PORT_EN))
6fa9a5ec 2385 goto out;
19d8fe15 2386
39e5fa88 2387 if (IS_GEN7(dev) && port == PORT_A) {
19d8fe15 2388 *pipe = PORT_TO_PIPE_CPT(tmp);
39e5fa88 2389 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
adc289d7 2390 enum pipe p;
19d8fe15 2391
adc289d7
VS		 2392 for_each_pipe(dev_priv, p) {
2393 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2394 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2395 *pipe = p;
6fa9a5ec
ID		 2396 ret = true;
2397
2398 goto out;
19d8fe15
DV		 2399 }
2400 }
19d8fe15 2401
4a0833ec 2402 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
f0f59a00 2403 i915_mmio_reg_offset(intel_dp->output_reg));
39e5fa88
VS		 2404 } else if (IS_CHERRYVIEW(dev)) {
2405 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2406 } else {
2407 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2408 }
d240f20f 2409
6fa9a5ec
ID		 2410 ret = true;
2411
2412out:
2413 intel_display_power_put(dev_priv, power_domain);
2414
2415 return ret;
19d8fe15 2416}
d240f20f 2417
045ac3b5 2418static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2419 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2420{
2421 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2422 u32 tmp, flags = 0;
63000ef6
XZ		 2423 struct drm_device *dev = encoder->base.dev;
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2425 enum port port = dp_to_dig_port(intel_dp)->port;
2426 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 2427
9ed109a7 2428 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2429
2430 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2431
39e5fa88 2432 if (HAS_PCH_CPT(dev) && port != PORT_A) {
b81e34c2
VS		 2433 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2434
2435 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2436 flags |= DRM_MODE_FLAG_PHSYNC;
2437 else
2438 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2439
b81e34c2 2440 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2441 flags |= DRM_MODE_FLAG_PVSYNC;
2442 else
2443 flags |= DRM_MODE_FLAG_NVSYNC;
2444 } else {
39e5fa88 2445 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2446 flags |= DRM_MODE_FLAG_PHSYNC;
2447 else
2448 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2449
39e5fa88 2450 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2451 flags |= DRM_MODE_FLAG_PVSYNC;
2452 else
2453 flags |= DRM_MODE_FLAG_NVSYNC;
2454 }
045ac3b5 2455
2d112de7 2456 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2457
8c875fca 2458 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 2459 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
8c875fca
VS		 2460 pipe_config->limited_color_range = true;
2461
eb14cb74
VS		 2462 pipe_config->has_dp_encoder = true;
2463
90a6b7b0
VS		 2464 pipe_config->lane_count =
2465 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2466
eb14cb74
VS		 2467 intel_dp_get_m_n(crtc, pipe_config);
2468
18442d08 2469 if (port == PORT_A) {
b377e0df 2470 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
f1f644dc
JB		 2471 pipe_config->port_clock = 162000;
2472 else
2473 pipe_config->port_clock = 270000;
2474 }
18442d08 2475
e3b247da
VS		 2476 pipe_config->base.adjusted_mode.crtc_clock =
2477 intel_dotclock_calculate(pipe_config->port_clock,
2478 &pipe_config->dp_m_n);
7f16e5c1 2479
6aa23e65
JN		 2480 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2481 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
c6cd2ee2
JN		 2482 /*
2483 * This is a big fat ugly hack.
2484 *
2485 * Some machines in UEFI boot mode provide us a VBT that has 18
2486 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2487 * unknown we fail to light up. Yet the same BIOS boots up with
2488 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2489 * max, not what it tells us to use.
2490 *
2491 * Note: This will still be broken if the eDP panel is not lit
2492 * up by the BIOS, and thus we can't get the mode at module
2493 * load.
2494 */
2495 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2496 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2497 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
c6cd2ee2 2498 }
045ac3b5
JB		 2499}
2500
e8cb4558 2501static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2502{
e8cb4558 2503 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2504 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2505 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2506
6e3c9717 2507 if (crtc->config->has_audio)
495a5bb8 2508 intel_audio_codec_disable(encoder);
6cb49835 2509
b32c6f48
RV		 2510 if (HAS_PSR(dev) && !HAS_DDI(dev))
2511 intel_psr_disable(intel_dp);
2512
6cb49835
DV		 2513 /* Make sure the panel is off before trying to change the mode. But also
2514 * ensure that we have vdd while we switch off the panel. */
24f3e092 2515 intel_edp_panel_vdd_on(intel_dp);
4be73780 2516 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2517 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2518 intel_edp_panel_off(intel_dp);
3739850b 2519
08aff3fe
VS		 2520 /* disable the port before the pipe on g4x */
2521 if (INTEL_INFO(dev)->gen < 5)
3739850b 2522 intel_dp_link_down(intel_dp);
d240f20f
JB		 2523}
2524
08aff3fe 2525static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2526{
2bd2ad64 2527 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2528 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2529
49277c31 2530 intel_dp_link_down(intel_dp);
abfce949
VS		 2531
2532 /* Only ilk+ has port A */
08aff3fe
VS		 2533 if (port == PORT_A)
2534 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2535}
2536
2537static void vlv_post_disable_dp(struct intel_encoder *encoder)
2538{
2539 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2540
2541 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2542}
2543
a8f327fb
VS		 2544static void chv_post_disable_dp(struct intel_encoder *encoder)
2545{
2546 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2547 struct drm_device *dev = encoder->base.dev;
2548 struct drm_i915_private *dev_priv = dev->dev_private;
97fd4d5c 2549
a8f327fb
VS		 2550 intel_dp_link_down(intel_dp);
2551
2552 mutex_lock(&dev_priv->sb_lock);
2553
2554 /* Assert data lane reset */
2555 chv_data_lane_soft_reset(encoder, true);
580d3811 2556
a580516d 2557 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2558}
2559
7b13b58a
VS		 2560static void
2561_intel_dp_set_link_train(struct intel_dp *intel_dp,
2562 uint32_t *DP,
2563 uint8_t dp_train_pat)
2564{
2565 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2566 struct drm_device *dev = intel_dig_port->base.base.dev;
2567 struct drm_i915_private *dev_priv = dev->dev_private;
2568 enum port port = intel_dig_port->port;
2569
2570 if (HAS_DDI(dev)) {
2571 uint32_t temp = I915_READ(DP_TP_CTL(port));
2572
2573 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2574 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2575 else
2576 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2577
2578 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2579 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2580 case DP_TRAINING_PATTERN_DISABLE:
2581 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2582
2583 break;
2584 case DP_TRAINING_PATTERN_1:
2585 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2586 break;
2587 case DP_TRAINING_PATTERN_2:
2588 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2589 break;
2590 case DP_TRAINING_PATTERN_3:
2591 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2592 break;
2593 }
2594 I915_WRITE(DP_TP_CTL(port), temp);
2595
39e5fa88
VS		 2596 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2597 (HAS_PCH_CPT(dev) && port != PORT_A)) {
7b13b58a
VS		 2598 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2599
2600 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2601 case DP_TRAINING_PATTERN_DISABLE:
2602 *DP |= DP_LINK_TRAIN_OFF_CPT;
2603 break;
2604 case DP_TRAINING_PATTERN_1:
2605 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2606 break;
2607 case DP_TRAINING_PATTERN_2:
2608 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2609 break;
2610 case DP_TRAINING_PATTERN_3:
2611 DRM_ERROR("DP training pattern 3 not supported\n");
2612 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2613 break;
2614 }
2615
2616 } else {
2617 if (IS_CHERRYVIEW(dev))
2618 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2619 else
2620 *DP &= ~DP_LINK_TRAIN_MASK;
2621
2622 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2623 case DP_TRAINING_PATTERN_DISABLE:
2624 *DP |= DP_LINK_TRAIN_OFF;
2625 break;
2626 case DP_TRAINING_PATTERN_1:
2627 *DP |= DP_LINK_TRAIN_PAT_1;
2628 break;
2629 case DP_TRAINING_PATTERN_2:
2630 *DP |= DP_LINK_TRAIN_PAT_2;
2631 break;
2632 case DP_TRAINING_PATTERN_3:
2633 if (IS_CHERRYVIEW(dev)) {
2634 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2635 } else {
2636 DRM_ERROR("DP training pattern 3 not supported\n");
2637 *DP |= DP_LINK_TRAIN_PAT_2;
2638 }
2639 break;
2640 }
2641 }
2642}
2643
2644static void intel_dp_enable_port(struct intel_dp *intel_dp)
2645{
2646 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2647 struct drm_i915_private *dev_priv = dev->dev_private;
6fec7662
VS		 2648 struct intel_crtc *crtc =
2649 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
7b13b58a 2650
7b13b58a
VS		 2651 /* enable with pattern 1 (as per spec) */
2652 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2653 DP_TRAINING_PATTERN_1);
2654
2655 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2656 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2657
2658 /*
2659 * Magic for VLV/CHV. We _must_ first set up the register
2660 * without actually enabling the port, and then do another
2661 * write to enable the port. Otherwise link training will
2662 * fail when the power sequencer is freshly used for this port.
2663 */
2664 intel_dp->DP |= DP_PORT_EN;
6fec7662
VS		 2665 if (crtc->config->has_audio)
2666 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
7b713f50
VS		 2667
2668 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2669 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2670}
2671
e8cb4558 2672static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2673{
e8cb4558
DV		 2674 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2675 struct drm_device *dev = encoder->base.dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2677 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2678 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
d6fbdd15 2679 enum pipe pipe = crtc->pipe;
5d613501 2680
0c33d8d7
DV		 2681 if (WARN_ON(dp_reg & DP_PORT_EN))
2682 return;
5d613501 2683
093e3f13
VS		 2684 pps_lock(intel_dp);
2685
666a4537 2686 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
093e3f13
VS		 2687 vlv_init_panel_power_sequencer(intel_dp);
2688
7b13b58a 2689 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2690
2691 edp_panel_vdd_on(intel_dp);
2692 edp_panel_on(intel_dp);
2693 edp_panel_vdd_off(intel_dp, true);
2694
2695 pps_unlock(intel_dp);
2696
666a4537 2697 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e0fce78f
VS		 2698 unsigned int lane_mask = 0x0;
2699
2700 if (IS_CHERRYVIEW(dev))
2701 lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2702
9b6de0a1
VS		 2703 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2704 lane_mask);
e0fce78f 2705 }
61234fa5 2706
f01eca2e 2707 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2708 intel_dp_start_link_train(intel_dp);
3ab9c637 2709 intel_dp_stop_link_train(intel_dp);
c1dec79a 2710
6e3c9717 2711 if (crtc->config->has_audio) {
c1dec79a 2712 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
d6fbdd15 2713 pipe_name(pipe));
c1dec79a
JN		 2714 intel_audio_codec_enable(encoder);
2715 }
ab1f90f9 2716}
89b667f8 2717
ecff4f3b
JN		 2718static void g4x_enable_dp(struct intel_encoder *encoder)
2719{
828f5c6e
JN		 2720 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2721
ecff4f3b 2722 intel_enable_dp(encoder);
4be73780 2723 intel_edp_backlight_on(intel_dp);
ab1f90f9 2724}
89b667f8 2725
ab1f90f9
JN		 2726static void vlv_enable_dp(struct intel_encoder *encoder)
2727{
828f5c6e
JN		 2728 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2729
4be73780 2730 intel_edp_backlight_on(intel_dp);
b32c6f48 2731 intel_psr_enable(intel_dp);
d240f20f
JB		 2732}
2733
ecff4f3b 2734static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2735{
2736 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6fbdd15 2737 enum port port = dp_to_dig_port(intel_dp)->port;
ab1f90f9 2738
8ac33ed3
DV		 2739 intel_dp_prepare(encoder);
2740
d41f1efb 2741 /* Only ilk+ has port A */
abfce949 2742 if (port == PORT_A)
ab1f90f9
JN		 2743 ironlake_edp_pll_on(intel_dp);
2744}
2745
83b84597
VS		 2746static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2747{
2748 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2749 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2750 enum pipe pipe = intel_dp->pps_pipe;
f0f59a00 2751 i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
83b84597
VS		 2752
2753 edp_panel_vdd_off_sync(intel_dp);
2754
2755 /*
2756 * VLV seems to get confused when multiple power seqeuencers
2757 * have the same port selected (even if only one has power/vdd
2758 * enabled). The failure manifests as vlv_wait_port_ready() failing
2759 * CHV on the other hand doesn't seem to mind having the same port
2760 * selected in multiple power seqeuencers, but let's clear the
2761 * port select always when logically disconnecting a power sequencer
2762 * from a port.
2763 */
2764 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2765 pipe_name(pipe), port_name(intel_dig_port->port));
2766 I915_WRITE(pp_on_reg, 0);
2767 POSTING_READ(pp_on_reg);
2768
2769 intel_dp->pps_pipe = INVALID_PIPE;
2770}
2771
a4a5d2f8
VS		 2772static void vlv_steal_power_sequencer(struct drm_device *dev,
2773 enum pipe pipe)
2774{
2775 struct drm_i915_private *dev_priv = dev->dev_private;
2776 struct intel_encoder *encoder;
2777
2778 lockdep_assert_held(&dev_priv->pps_mutex);
2779
ac3c12e4
VS		 2780 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2781 return;
2782
19c8054c 2783 for_each_intel_encoder(dev, encoder) {
a4a5d2f8 2784 struct intel_dp *intel_dp;
773538e8 2785 enum port port;
a4a5d2f8
VS		 2786
2787 if (encoder->type != INTEL_OUTPUT_EDP)
2788 continue;
2789
2790 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2791 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2792
2793 if (intel_dp->pps_pipe != pipe)
2794 continue;
2795
2796 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2797 pipe_name(pipe), port_name(port));
a4a5d2f8 2798
e02f9a06 2799 WARN(encoder->base.crtc,
034e43c6
VS		 2800 "stealing pipe %c power sequencer from active eDP port %c\n",
2801 pipe_name(pipe), port_name(port));
a4a5d2f8 2802
a4a5d2f8 2803 /* make sure vdd is off before we steal it */
83b84597 2804 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2805 }
2806}
2807
2808static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2809{
2810 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2811 struct intel_encoder *encoder = &intel_dig_port->base;
2812 struct drm_device *dev = encoder->base.dev;
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2815
2816 lockdep_assert_held(&dev_priv->pps_mutex);
2817
093e3f13
VS		 2818 if (!is_edp(intel_dp))
2819 return;
2820
a4a5d2f8
VS		 2821 if (intel_dp->pps_pipe == crtc->pipe)
2822 return;
2823
2824 /*
2825 * If another power sequencer was being used on this
2826 * port previously make sure to turn off vdd there while
2827 * we still have control of it.
2828 */
2829 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2830 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2831
2832 /*
2833 * We may be stealing the power
2834 * sequencer from another port.
2835 */
2836 vlv_steal_power_sequencer(dev, crtc->pipe);
2837
2838 /* now it's all ours */
2839 intel_dp->pps_pipe = crtc->pipe;
2840
2841 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2842 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2843
2844 /* init power sequencer on this pipe and port */
36b5f425
VS		 2845 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2846 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2847}
2848
ab1f90f9 2849static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2850{
5f68c275 2851 vlv_phy_pre_encoder_enable(encoder);
ab1f90f9
JN		 2852
2853 intel_enable_dp(encoder);
89b667f8
JB		 2854}
2855
ecff4f3b 2856static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8 2857{
8ac33ed3
DV		 2858 intel_dp_prepare(encoder);
2859
6da2e616 2860 vlv_phy_pre_pll_enable(encoder);
a4fc5ed6
KP		 2861}
2862
e4a1d846
CML		 2863static void chv_pre_enable_dp(struct intel_encoder *encoder)
2864{
e7d2a717 2865 chv_phy_pre_encoder_enable(encoder);
e4a1d846 2866
e4a1d846 2867 intel_enable_dp(encoder);
b0b33846
VS		 2868
2869 /* Second common lane will stay alive on its own now */
e7d2a717 2870 chv_phy_release_cl2_override(encoder);
e4a1d846
CML		 2871}
2872
9197c88b
VS		 2873static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2874{
625695f8
VS		 2875 intel_dp_prepare(encoder);
2876
419b1b7a 2877 chv_phy_pre_pll_enable(encoder);
9197c88b
VS		 2878}
2879
d6db995f
VS		 2880static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
2881{
204970b5 2882 chv_phy_post_pll_disable(encoder);
d6db995f
VS		 2883}
2884
a4fc5ed6
KP		 2885/*
2886 * Fetch AUX CH registers 0x202 - 0x207 which contain
2887 * link status information
2888 */
94223d04 2889bool
93f62dad 2890intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2891{
9f085ebb
L		 2892 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2893 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2894}
2895
1100244e 2896/* These are source-specific values. */
94223d04 2897uint8_t
1a2eb460 2898intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2899{
30add22d 2900 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 2901 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 2902 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2903
9314726b
VK		 2904 if (IS_BROXTON(dev))
2905 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2906 else if (INTEL_INFO(dev)->gen >= 9) {
06411f08 2907 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
7ad14a29 2908 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2909 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
666a4537 2910 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
bd60018a 2911 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2912 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2913 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2914 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2915 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2916 else
bd60018a 2917 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2918}
2919
94223d04 2920uint8_t
1a2eb460
KP		 2921intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2922{
30add22d 2923 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2924 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2925
5a9d1f1a
DL		 2926 if (INTEL_INFO(dev)->gen >= 9) {
2927 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2928 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2929 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2930 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2931 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2932 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2933 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 2934 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2935 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 2936 default:
2937 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2938 }
2939 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2940 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2941 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2942 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2943 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2944 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2945 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2946 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2947 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2948 default:
bd60018a 2949 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2950 }
666a4537 2951 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e2fa6fba 2952 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2953 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2954 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2955 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2956 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2957 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2958 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2960 default:
bd60018a 2961 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2962 }
bc7d38a4 2963 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2964 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2965 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2966 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2968 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2969 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2970 default:
bd60018a 2971 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2972 }
2973 } else {
2974 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2975 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2976 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2977 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2978 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2979 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2980 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2981 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2982 default:
bd60018a 2983 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2984 }
a4fc5ed6
KP		 2985 }
2986}
2987
5829975c 2988static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba 2989{
53d98725 2990 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
e2fa6fba
P		 2991 unsigned long demph_reg_value, preemph_reg_value,
2992 uniqtranscale_reg_value;
2993 uint8_t train_set = intel_dp->train_set[0];
e2fa6fba
P		 2994
2995 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2996 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2997 preemph_reg_value = 0x0004000;
2998 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2999 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3000 demph_reg_value = 0x2B405555;
3001 uniqtranscale_reg_value = 0x552AB83A;
3002 break;
bd60018a 3003 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3004 demph_reg_value = 0x2B404040;
3005 uniqtranscale_reg_value = 0x5548B83A;
3006 break;
bd60018a 3007 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3008 demph_reg_value = 0x2B245555;
3009 uniqtranscale_reg_value = 0x5560B83A;
3010 break;
bd60018a 3011 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3012 demph_reg_value = 0x2B405555;
3013 uniqtranscale_reg_value = 0x5598DA3A;
3014 break;
3015 default:
3016 return 0;
3017 }
3018 break;
bd60018a 3019 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3020 preemph_reg_value = 0x0002000;
3021 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3023 demph_reg_value = 0x2B404040;
3024 uniqtranscale_reg_value = 0x5552B83A;
3025 break;
bd60018a 3026 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3027 demph_reg_value = 0x2B404848;
3028 uniqtranscale_reg_value = 0x5580B83A;
3029 break;
bd60018a 3030 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3031 demph_reg_value = 0x2B404040;
3032 uniqtranscale_reg_value = 0x55ADDA3A;
3033 break;
3034 default:
3035 return 0;
3036 }
3037 break;
bd60018a 3038 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3039 preemph_reg_value = 0x0000000;
3040 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3041 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3042 demph_reg_value = 0x2B305555;
3043 uniqtranscale_reg_value = 0x5570B83A;
3044 break;
bd60018a 3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3046 demph_reg_value = 0x2B2B4040;
3047 uniqtranscale_reg_value = 0x55ADDA3A;
3048 break;
3049 default:
3050 return 0;
3051 }
3052 break;
bd60018a 3053 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3054 preemph_reg_value = 0x0006000;
3055 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3056 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3057 demph_reg_value = 0x1B405555;
3058 uniqtranscale_reg_value = 0x55ADDA3A;
3059 break;
3060 default:
3061 return 0;
3062 }
3063 break;
3064 default:
3065 return 0;
3066 }
3067
53d98725
ACO		 3068 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3069 uniqtranscale_reg_value, 0);
e2fa6fba
P		 3070
3071 return 0;
3072}
3073
5829975c 3074static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846 3075{
b7fa22d8
ACO		 3076 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3077 u32 deemph_reg_value, margin_reg_value;
3078 bool uniq_trans_scale = false;
e4a1d846 3079 uint8_t train_set = intel_dp->train_set[0];
e4a1d846
CML		 3080
3081 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3082 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3083 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3084 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3085 deemph_reg_value = 128;
3086 margin_reg_value = 52;
3087 break;
bd60018a 3088 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3089 deemph_reg_value = 128;
3090 margin_reg_value = 77;
3091 break;
bd60018a 3092 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3093 deemph_reg_value = 128;
3094 margin_reg_value = 102;
3095 break;
bd60018a 3096 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3097 deemph_reg_value = 128;
3098 margin_reg_value = 154;
b7fa22d8 3099 uniq_trans_scale = true;
e4a1d846
CML		 3100 break;
3101 default:
3102 return 0;
3103 }
3104 break;
bd60018a 3105 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3106 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3107 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3108 deemph_reg_value = 85;
3109 margin_reg_value = 78;
3110 break;
bd60018a 3111 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3112 deemph_reg_value = 85;
3113 margin_reg_value = 116;
3114 break;
bd60018a 3115 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3116 deemph_reg_value = 85;
3117 margin_reg_value = 154;
3118 break;
3119 default:
3120 return 0;
3121 }
3122 break;
bd60018a 3123 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3124 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3126 deemph_reg_value = 64;
3127 margin_reg_value = 104;
3128 break;
bd60018a 3129 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3130 deemph_reg_value = 64;
3131 margin_reg_value = 154;
3132 break;
3133 default:
3134 return 0;
3135 }
3136 break;
bd60018a 3137 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3138 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3139 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3140 deemph_reg_value = 43;
3141 margin_reg_value = 154;
3142 break;
3143 default:
3144 return 0;
3145 }
3146 break;
3147 default:
3148 return 0;
3149 }
3150
b7fa22d8
ACO		 3151 chv_set_phy_signal_level(encoder, deemph_reg_value,
3152 margin_reg_value, uniq_trans_scale);
e4a1d846
CML		 3153
3154 return 0;
3155}
3156
a4fc5ed6 3157static uint32_t
5829975c 3158gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3159{
3cf2efb1 3160 uint32_t signal_levels = 0;
a4fc5ed6 3161
3cf2efb1 3162 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3163 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3164 default:
3165 signal_levels |= DP_VOLTAGE_0_4;
3166 break;
bd60018a 3167 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3168 signal_levels |= DP_VOLTAGE_0_6;
3169 break;
bd60018a 3170 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3171 signal_levels |= DP_VOLTAGE_0_8;
3172 break;
bd60018a 3173 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3174 signal_levels |= DP_VOLTAGE_1_2;
3175 break;
3176 }
3cf2efb1 3177 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3178 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3179 default:
3180 signal_levels |= DP_PRE_EMPHASIS_0;
3181 break;
bd60018a 3182 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3183 signal_levels |= DP_PRE_EMPHASIS_3_5;
3184 break;
bd60018a 3185 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3186 signal_levels |= DP_PRE_EMPHASIS_6;
3187 break;
bd60018a 3188 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3189 signal_levels |= DP_PRE_EMPHASIS_9_5;
3190 break;
3191 }
3192 return signal_levels;
3193}
3194
e3421a18
ZW		 3195/* Gen6's DP voltage swing and pre-emphasis control */
3196static uint32_t
5829975c 3197gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3198{
3c5a62b5
YL		 3199 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3200 DP_TRAIN_PRE_EMPHASIS_MASK);
3201 switch (signal_levels) {
bd60018a
SJ		 3202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3204 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3206 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3209 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3211 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3212 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3214 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3215 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3216 default:
3c5a62b5
YL		 3217 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3218 "0x%x\n", signal_levels);
3219 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3220 }
3221}
3222
1a2eb460
KP		 3223/* Gen7's DP voltage swing and pre-emphasis control */
3224static uint32_t
5829975c 3225gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3226{
3227 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3228 DP_TRAIN_PRE_EMPHASIS_MASK);
3229 switch (signal_levels) {
bd60018a 3230 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3231 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3232 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3233 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3234 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3235 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3236
bd60018a 3237 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3238 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3239 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3240 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3241
bd60018a 3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3243 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3244 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3245 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3246
3247 default:
3248 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3249 "0x%x\n", signal_levels);
3250 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3251 }
3252}
3253
94223d04 3254void
f4eb692e 3255intel_dp_set_signal_levels(struct intel_dp *intel_dp)
f0a3424e
PZ		 3256{
3257 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3258 enum port port = intel_dig_port->port;
f0a3424e 3259 struct drm_device *dev = intel_dig_port->base.base.dev;
b905a915 3260 struct drm_i915_private *dev_priv = to_i915(dev);
f8896f5d 3261 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3262 uint8_t train_set = intel_dp->train_set[0];
3263
f8896f5d
DW		 3264 if (HAS_DDI(dev)) {
3265 signal_levels = ddi_signal_levels(intel_dp);
3266
3267 if (IS_BROXTON(dev))
3268 signal_levels = 0;
3269 else
3270 mask = DDI_BUF_EMP_MASK;
e4a1d846 3271 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3272 signal_levels = chv_signal_levels(intel_dp);
e2fa6fba 3273 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3274 signal_levels = vlv_signal_levels(intel_dp);
bc7d38a4 3275 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3276 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3277 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3278 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3279 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3280 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3281 } else {
5829975c 3282 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3283 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3284 }
3285
96fb9f9b
VK		 3286 if (mask)
3287 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3288
3289 DRM_DEBUG_KMS("Using vswing level %d\n",
3290 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3291 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3292 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3293 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e 3294
f4eb692e 3295 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
b905a915
ACO		 3296
3297 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3298 POSTING_READ(intel_dp->output_reg);
f0a3424e
PZ		 3299}
3300
94223d04 3301void
e9c176d5
ACO		 3302intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3303 uint8_t dp_train_pat)
a4fc5ed6 3304{
174edf1f 3305 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3306 struct drm_i915_private *dev_priv =
3307 to_i915(intel_dig_port->base.base.dev);
a4fc5ed6 3308
f4eb692e 3309 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
47ea7542 3310
f4eb692e 3311 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
ea5b213a 3312 POSTING_READ(intel_dp->output_reg);
e9c176d5
ACO		 3313}
3314
94223d04 3315void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3ab9c637
ID		 3316{
3317 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3318 struct drm_device *dev = intel_dig_port->base.base.dev;
3319 struct drm_i915_private *dev_priv = dev->dev_private;
3320 enum port port = intel_dig_port->port;
3321 uint32_t val;
3322
3323 if (!HAS_DDI(dev))
3324 return;
3325
3326 val = I915_READ(DP_TP_CTL(port));
3327 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3328 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3329 I915_WRITE(DP_TP_CTL(port), val);
3330
3331 /*
3332 * On PORT_A we can have only eDP in SST mode. There the only reason
3333 * we need to set idle transmission mode is to work around a HW issue
3334 * where we enable the pipe while not in idle link-training mode.
3335 * In this case there is requirement to wait for a minimum number of
3336 * idle patterns to be sent.
3337 */
3338 if (port == PORT_A)
3339 return;
3340
3341 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3342 1))
3343 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3344}
3345
a4fc5ed6 3346static void
ea5b213a 3347intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3348{
da63a9f2 3349 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3350 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3351 enum port port = intel_dig_port->port;
da63a9f2 3352 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3353 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3354 uint32_t DP = intel_dp->DP;
a4fc5ed6 3355
bc76e320 3356 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3357 return;
3358
0c33d8d7 3359 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3360 return;
3361
28c97730 3362 DRM_DEBUG_KMS("\n");
32f9d658 3363
39e5fa88
VS		 3364 if ((IS_GEN7(dev) && port == PORT_A) ||
3365 (HAS_PCH_CPT(dev) && port != PORT_A)) {
e3421a18 3366 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3367 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3368 } else {
aad3d14d
VS		 3369 if (IS_CHERRYVIEW(dev))
3370 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3371 else
3372 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3373 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3374 }
1612c8bd 3375 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3376 POSTING_READ(intel_dp->output_reg);
5eb08b69 3377
1612c8bd
VS		 3378 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3379 I915_WRITE(intel_dp->output_reg, DP);
3380 POSTING_READ(intel_dp->output_reg);
3381
3382 /*
3383 * HW workaround for IBX, we need to move the port
3384 * to transcoder A after disabling it to allow the
3385 * matching HDMI port to be enabled on transcoder A.
3386 */
3387 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
0c241d5b
VS		 3388 /*
3389 * We get CPU/PCH FIFO underruns on the other pipe when
3390 * doing the workaround. Sweep them under the rug.
3391 */
3392 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3393 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3394
1612c8bd
VS		 3395 /* always enable with pattern 1 (as per spec) */
3396 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3397 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3398 I915_WRITE(intel_dp->output_reg, DP);
3399 POSTING_READ(intel_dp->output_reg);
3400
3401 DP &= ~DP_PORT_EN;
5bddd17f 3402 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3403 POSTING_READ(intel_dp->output_reg);
0c241d5b
VS		 3404
3405 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3406 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3407 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5bddd17f
EA		 3408 }
3409
f01eca2e 3410 msleep(intel_dp->panel_power_down_delay);
6fec7662
VS		 3411
3412 intel_dp->DP = DP;
a4fc5ed6
KP		 3413}
3414
26d61aad
KP		 3415static bool
3416intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3417{
a031d709
RV		 3418 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3419 struct drm_device *dev = dig_port->base.base.dev;
3420 struct drm_i915_private *dev_priv = dev->dev_private;
3421
9f085ebb
L		 3422 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3423 sizeof(intel_dp->dpcd)) < 0)
edb39244 3424 return false; /* aux transfer failed */
92fd8fd1 3425
a8e98153 3426 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3427
edb39244
AJ		 3428 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3429 return false; /* DPCD not present */
3430
9f085ebb
L		 3431 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3432 &intel_dp->sink_count, 1) < 0)
30d9aa42
SS		 3433 return false;
3434
3435 /*
3436 * Sink count can change between short pulse hpd hence
3437 * a member variable in intel_dp will track any changes
3438 * between short pulse interrupts.
3439 */
3440 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3441
3442 /*
3443 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3444 * a dongle is present but no display. Unless we require to know
3445 * if a dongle is present or not, we don't need to update
3446 * downstream port information. So, an early return here saves
3447 * time from performing other operations which are not required.
3448 */
1034ce70 3449 if (!is_edp(intel_dp) && !intel_dp->sink_count)
30d9aa42
SS		 3450 return false;
3451
2293bb5c
SK		 3452 /* Check if the panel supports PSR */
3453 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3454 if (is_edp(intel_dp)) {
9f085ebb
L		 3455 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3456 intel_dp->psr_dpcd,
3457 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3458 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3459 dev_priv->psr.sink_support = true;
50003939 3460 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3461 }
474d1ec4
SJ		 3462
3463 if (INTEL_INFO(dev)->gen >= 9 &&
3464 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3465 uint8_t frame_sync_cap;
3466
3467 dev_priv->psr.sink_support = true;
9f085ebb
L		 3468 drm_dp_dpcd_read(&intel_dp->aux,
3469 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3470 &frame_sync_cap, 1);
474d1ec4
SJ		 3471 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3472 /* PSR2 needs frame sync as well */
3473 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3474 DRM_DEBUG_KMS("PSR2 %s on sink",
3475 dev_priv->psr.psr2_support ? "supported" : "not supported");
3476 }
86ee27b5
YA		 3477
3478 /* Read the eDP Display control capabilities registers */
3479 memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd));
3480 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
9a652cc0 3481 (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
86ee27b5
YA		 3482 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3483 sizeof(intel_dp->edp_dpcd)))
3484 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3485 intel_dp->edp_dpcd);
50003939
JN		 3486 }
3487
bc5133d5 3488 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
e588fa18 3489 yesno(intel_dp_source_supports_hbr2(intel_dp)),
742f491d 3490 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
06ea66b6 3491
fc0f8e25 3492 /* Intermediate frequency support */
86ee27b5 3493 if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */
94ca719e 3494 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3495 int i;
3496
9f085ebb
L		 3497 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3498 sink_rates, sizeof(sink_rates));
ea2d8a42 3499
94ca719e
VS		 3500 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3501 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3502
3503 if (val == 0)
3504 break;
3505
af77b974
SJ		 3506 /* Value read is in kHz while drm clock is saved in deca-kHz */
3507 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3508 }
94ca719e 3509 intel_dp->num_sink_rates = i;
fc0f8e25 3510 }
0336400e
VS		 3511
3512 intel_dp_print_rates(intel_dp);
3513
edb39244
AJ		 3514 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3515 DP_DWN_STRM_PORT_PRESENT))
3516 return true; /* native DP sink */
3517
3518 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3519 return true; /* no per-port downstream info */
3520
9f085ebb
L		 3521 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3522 intel_dp->downstream_ports,
3523 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3524 return false; /* downstream port status fetch failed */
3525
3526 return true;
92fd8fd1
KP		 3527}
3528
0d198328
AJ		 3529static void
3530intel_dp_probe_oui(struct intel_dp *intel_dp)
3531{
3532 u8 buf[3];
3533
3534 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3535 return;
3536
9f085ebb 3537 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3538 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3539 buf[0], buf[1], buf[2]);
3540
9f085ebb 3541 if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3542 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3543 buf[0], buf[1], buf[2]);
3544}
3545
0e32b39c
DA		 3546static bool
3547intel_dp_probe_mst(struct intel_dp *intel_dp)
3548{
3549 u8 buf[1];
3550
7cc96139
NS		 3551 if (!i915.enable_dp_mst)
3552 return false;
3553
0e32b39c
DA		 3554 if (!intel_dp->can_mst)
3555 return false;
3556
3557 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3558 return false;
3559
9f085ebb 3560 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
0e32b39c
DA		 3561 if (buf[0] & DP_MST_CAP) {
3562 DRM_DEBUG_KMS("Sink is MST capable\n");
3563 intel_dp->is_mst = true;
3564 } else {
3565 DRM_DEBUG_KMS("Sink is not MST capable\n");
3566 intel_dp->is_mst = false;
3567 }
3568 }
0e32b39c
DA		 3569
3570 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3571 return intel_dp->is_mst;
3572}
3573
e5a1cab5 3574static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
d2e216d0 3575{
082dcc7c 3576 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3577 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c 3578 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
ad9dc91b 3579 u8 buf;
e5a1cab5 3580 int ret = 0;
c6297843
RV		 3581 int count = 0;
3582 int attempts = 10;
d2e216d0 3583
082dcc7c
RV		 3584 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3585 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3586 ret = -EIO;
3587 goto out;
4373f0f2
PZ		 3588 }
3589
082dcc7c 3590 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
e5a1cab5 3591 buf & ~DP_TEST_SINK_START) < 0) {
082dcc7c 3592 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3593 ret = -EIO;
3594 goto out;
3595 }
d2e216d0 3596
c6297843
RV		 3597 do {
3598 intel_wait_for_vblank(dev, intel_crtc->pipe);
3599
3600 if (drm_dp_dpcd_readb(&intel_dp->aux,
3601 DP_TEST_SINK_MISC, &buf) < 0) {
3602 ret = -EIO;
3603 goto out;
3604 }
3605 count = buf & DP_TEST_COUNT_MASK;
3606 } while (--attempts && count);
3607
3608 if (attempts == 0) {
dc5a9037 3609 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
c6297843
RV		 3610 ret = -ETIMEDOUT;
3611 }
3612
e5a1cab5 3613 out:
082dcc7c 3614 hsw_enable_ips(intel_crtc);
e5a1cab5 3615 return ret;
082dcc7c
RV		 3616}
3617
3618static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3619{
3620 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3621 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c
RV		 3622 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3623 u8 buf;
e5a1cab5
RV		 3624 int ret;
3625
082dcc7c
RV		 3626 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3627 return -EIO;
3628
3629 if (!(buf & DP_TEST_CRC_SUPPORTED))
3630 return -ENOTTY;
3631
3632 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3633 return -EIO;
3634
6d8175da
RV		 3635 if (buf & DP_TEST_SINK_START) {
3636 ret = intel_dp_sink_crc_stop(intel_dp);
3637 if (ret)
3638 return ret;
3639 }
3640
082dcc7c 3641 hsw_disable_ips(intel_crtc);
1dda5f93 3642
9d1a1031 3643 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
082dcc7c
RV		 3644 buf | DP_TEST_SINK_START) < 0) {
3645 hsw_enable_ips(intel_crtc);
3646 return -EIO;
4373f0f2
PZ		 3647 }
3648
d72f9d91 3649 intel_wait_for_vblank(dev, intel_crtc->pipe);
082dcc7c
RV		 3650 return 0;
3651}
3652
3653int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3654{
3655 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3656 struct drm_device *dev = dig_port->base.base.dev;
3657 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3658 u8 buf;
621d4c76 3659 int count, ret;
082dcc7c 3660 int attempts = 6;
082dcc7c
RV		 3661
3662 ret = intel_dp_sink_crc_start(intel_dp);
3663 if (ret)
3664 return ret;
3665
ad9dc91b 3666 do {
621d4c76
RV		 3667 intel_wait_for_vblank(dev, intel_crtc->pipe);
3668
1dda5f93 3669 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 3670 DP_TEST_SINK_MISC, &buf) < 0) {
3671 ret = -EIO;
afe0d67e 3672 goto stop;
4373f0f2 3673 }
621d4c76 3674 count = buf & DP_TEST_COUNT_MASK;
aabc95dc 3675
7e38eeff 3676 } while (--attempts && count == 0);
ad9dc91b
RV		 3677
3678 if (attempts == 0) {
7e38eeff
RV		 3679 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3680 ret = -ETIMEDOUT;
3681 goto stop;
3682 }
3683
3684 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3685 ret = -EIO;
3686 goto stop;
ad9dc91b 3687 }
d2e216d0 3688
afe0d67e 3689stop:
082dcc7c 3690 intel_dp_sink_crc_stop(intel_dp);
4373f0f2 3691 return ret;
d2e216d0
RV		 3692}
3693
a60f0e38
JB		 3694static bool
3695intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3696{
9f085ebb 3697 return drm_dp_dpcd_read(&intel_dp->aux,
9d1a1031
JN		 3698 DP_DEVICE_SERVICE_IRQ_VECTOR,
3699 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3700}
3701
0e32b39c
DA		 3702static bool
3703intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3704{
3705 int ret;
3706
9f085ebb 3707 ret = drm_dp_dpcd_read(&intel_dp->aux,
0e32b39c
DA		 3708 DP_SINK_COUNT_ESI,
3709 sink_irq_vector, 14);
3710 if (ret != 14)
3711 return false;
3712
3713 return true;
3714}
3715
c5d5ab7a
TP		 3716static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3717{
3718 uint8_t test_result = DP_TEST_ACK;
3719 return test_result;
3720}
3721
3722static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3723{
3724 uint8_t test_result = DP_TEST_NAK;
3725 return test_result;
3726}
3727
3728static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 3729{
c5d5ab7a 3730 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 3731 struct intel_connector *intel_connector = intel_dp->attached_connector;
3732 struct drm_connector *connector = &intel_connector->base;
3733
3734 if (intel_connector->detect_edid == NULL ||
ac6f2e29 3735 connector->edid_corrupt ||
559be30c
TP		 3736 intel_dp->aux.i2c_defer_count > 6) {
3737 /* Check EDID read for NACKs, DEFERs and corruption
3738 * (DP CTS 1.2 Core r1.1)
3739 * 4.2.2.4 : Failed EDID read, I2C_NAK
3740 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3741 * 4.2.2.6 : EDID corruption detected
3742 * Use failsafe mode for all cases
3743 */
3744 if (intel_dp->aux.i2c_nack_count > 0 ||
3745 intel_dp->aux.i2c_defer_count > 0)
3746 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3747 intel_dp->aux.i2c_nack_count,
3748 intel_dp->aux.i2c_defer_count);
3749 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3750 } else {
f79b468e
TS		 3751 struct edid *block = intel_connector->detect_edid;
3752
3753 /* We have to write the checksum
3754 * of the last block read
3755 */
3756 block += intel_connector->detect_edid->extensions;
3757
559be30c
TP		 3758 if (!drm_dp_dpcd_write(&intel_dp->aux,
3759 DP_TEST_EDID_CHECKSUM,
f79b468e 3760 &block->checksum,
5a1cc655 3761 1))
559be30c
TP		 3762 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3763
3764 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3765 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3766 }
3767
3768 /* Set test active flag here so userspace doesn't interrupt things */
3769 intel_dp->compliance_test_active = 1;
3770
c5d5ab7a
TP		 3771 return test_result;
3772}
3773
3774static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 3775{
c5d5ab7a
TP		 3776 uint8_t test_result = DP_TEST_NAK;
3777 return test_result;
3778}
3779
3780static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3781{
3782 uint8_t response = DP_TEST_NAK;
3783 uint8_t rxdata = 0;
3784 int status = 0;
3785
c5d5ab7a
TP		 3786 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3787 if (status <= 0) {
3788 DRM_DEBUG_KMS("Could not read test request from sink\n");
3789 goto update_status;
3790 }
3791
3792 switch (rxdata) {
3793 case DP_TEST_LINK_TRAINING:
3794 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3795 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3796 response = intel_dp_autotest_link_training(intel_dp);
3797 break;
3798 case DP_TEST_LINK_VIDEO_PATTERN:
3799 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3800 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3801 response = intel_dp_autotest_video_pattern(intel_dp);
3802 break;
3803 case DP_TEST_LINK_EDID_READ:
3804 DRM_DEBUG_KMS("EDID test requested\n");
3805 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3806 response = intel_dp_autotest_edid(intel_dp);
3807 break;
3808 case DP_TEST_LINK_PHY_TEST_PATTERN:
3809 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3810 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3811 response = intel_dp_autotest_phy_pattern(intel_dp);
3812 break;
3813 default:
3814 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3815 break;
3816 }
3817
3818update_status:
3819 status = drm_dp_dpcd_write(&intel_dp->aux,
3820 DP_TEST_RESPONSE,
3821 &response, 1);
3822 if (status <= 0)
3823 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 3824}
3825
0e32b39c
DA		 3826static int
3827intel_dp_check_mst_status(struct intel_dp *intel_dp)
3828{
3829 bool bret;
3830
3831 if (intel_dp->is_mst) {
3832 u8 esi[16] = { 0 };
3833 int ret = 0;
3834 int retry;
3835 bool handled;
3836 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3837go_again:
3838 if (bret == true) {
3839
3840 /* check link status - esi[10] = 0x200c */
90a6b7b0 3841 if (intel_dp->active_mst_links &&
901c2daf 3842 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
0e32b39c
DA		 3843 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3844 intel_dp_start_link_train(intel_dp);
0e32b39c
DA		 3845 intel_dp_stop_link_train(intel_dp);
3846 }
3847
6f34cc39 3848 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 3849 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3850
3851 if (handled) {
3852 for (retry = 0; retry < 3; retry++) {
3853 int wret;
3854 wret = drm_dp_dpcd_write(&intel_dp->aux,
3855 DP_SINK_COUNT_ESI+1,
3856 &esi[1], 3);
3857 if (wret == 3) {
3858 break;
3859 }
3860 }
3861
3862 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3863 if (bret == true) {
6f34cc39 3864 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 3865 goto go_again;
3866 }
3867 } else
3868 ret = 0;
3869
3870 return ret;
3871 } else {
3872 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3873 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3874 intel_dp->is_mst = false;
3875 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3876 /* send a hotplug event */
3877 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3878 }
3879 }
3880 return -EINVAL;
3881}
3882
5c9114d0
SS		 3883static void
3884intel_dp_check_link_status(struct intel_dp *intel_dp)
3885{
3886 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3887 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3888 u8 link_status[DP_LINK_STATUS_SIZE];
3889
3890 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3891
3892 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3893 DRM_ERROR("Failed to get link status\n");
3894 return;
3895 }
3896
3897 if (!intel_encoder->base.crtc)
3898 return;
3899
3900 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3901 return;
3902
3903 /* if link training is requested we should perform it always */
3904 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
3905 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
3906 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3907 intel_encoder->base.name);
3908 intel_dp_start_link_train(intel_dp);
3909 intel_dp_stop_link_train(intel_dp);
3910 }
3911}
3912
a4fc5ed6
KP		 3913/*
3914 * According to DP spec
3915 * 5.1.2:
3916 * 1. Read DPCD
3917 * 2. Configure link according to Receiver Capabilities
3918 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3919 * 4. Check link status on receipt of hot-plug interrupt
39ff747b
SS		 3920 *
3921 * intel_dp_short_pulse - handles short pulse interrupts
3922 * when full detection is not required.
3923 * Returns %true if short pulse is handled and full detection
3924 * is NOT required and %false otherwise.
a4fc5ed6 3925 */
39ff747b 3926static bool
5c9114d0 3927intel_dp_short_pulse(struct intel_dp *intel_dp)
a4fc5ed6 3928{
5b215bcf 3929 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a60f0e38 3930 u8 sink_irq_vector;
39ff747b
SS		 3931 u8 old_sink_count = intel_dp->sink_count;
3932 bool ret;
5b215bcf 3933
4df6960e
SS		 3934 /*
3935 * Clearing compliance test variables to allow capturing
3936 * of values for next automated test request.
3937 */
3938 intel_dp->compliance_test_active = 0;
3939 intel_dp->compliance_test_type = 0;
3940 intel_dp->compliance_test_data = 0;
3941
39ff747b
SS		 3942 /*
3943 * Now read the DPCD to see if it's actually running
3944 * If the current value of sink count doesn't match with
3945 * the value that was stored earlier or dpcd read failed
3946 * we need to do full detection
3947 */
3948 ret = intel_dp_get_dpcd(intel_dp);
3949
3950 if ((old_sink_count != intel_dp->sink_count) || !ret) {
3951 /* No need to proceed if we are going to do full detect */
3952 return false;
59cd09e1
JB		 3953 }
3954
a60f0e38
JB		 3955 /* Try to read the source of the interrupt */
3956 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3957 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3958 /* Clear interrupt source */
9d1a1031
JN		 3959 drm_dp_dpcd_writeb(&intel_dp->aux,
3960 DP_DEVICE_SERVICE_IRQ_VECTOR,
3961 sink_irq_vector);
a60f0e38
JB		 3962
3963 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 3964 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 3965 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3966 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3967 }
3968
5c9114d0
SS		 3969 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3970 intel_dp_check_link_status(intel_dp);
3971 drm_modeset_unlock(&dev->mode_config.connection_mutex);
39ff747b
SS		 3972
3973 return true;
a4fc5ed6 3974}
a4fc5ed6 3975
caf9ab24 3976/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3977static enum drm_connector_status
26d61aad 3978intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3979{
caf9ab24 3980 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3981 uint8_t type;
3982
3983 if (!intel_dp_get_dpcd(intel_dp))
3984 return connector_status_disconnected;
3985
1034ce70
SS		 3986 if (is_edp(intel_dp))
3987 return connector_status_connected;
3988
caf9ab24
AJ		 3989 /* if there's no downstream port, we're done */
3990 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3991 return connector_status_connected;
caf9ab24
AJ		 3992
3993 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3994 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3995 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
9d1a1031 3996
30d9aa42
SS		 3997 return intel_dp->sink_count ?
3998 connector_status_connected : connector_status_disconnected;
caf9ab24
AJ		 3999 }
4000
4001 /* If no HPD, poke DDC gently */
0b99836f 4002 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4003 return connector_status_connected;
caf9ab24
AJ		 4004
4005 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4006 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4007 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4008 if (type == DP_DS_PORT_TYPE_VGA ||
4009 type == DP_DS_PORT_TYPE_NON_EDID)
4010 return connector_status_unknown;
4011 } else {
4012 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4013 DP_DWN_STRM_PORT_TYPE_MASK;
4014 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4015 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4016 return connector_status_unknown;
4017 }
caf9ab24
AJ		 4018
4019 /* Anything else is out of spec, warn and ignore */
4020 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4021 return connector_status_disconnected;
71ba9000
AJ		 4022}
4023
d410b56d
CW		 4024static enum drm_connector_status
4025edp_detect(struct intel_dp *intel_dp)
4026{
4027 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4028 enum drm_connector_status status;
4029
4030 status = intel_panel_detect(dev);
4031 if (status == connector_status_unknown)
4032 status = connector_status_connected;
4033
4034 return status;
4035}
4036
b93433cc
JN		 4037static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4038 struct intel_digital_port *port)
5eb08b69 4039{
b93433cc 4040 u32 bit;
01cb9ea6 4041
0df53b77
JN		 4042 switch (port->port) {
4043 case PORT_A:
4044 return true;
4045 case PORT_B:
4046 bit = SDE_PORTB_HOTPLUG;
4047 break;
4048 case PORT_C:
4049 bit = SDE_PORTC_HOTPLUG;
4050 break;
4051 case PORT_D:
4052 bit = SDE_PORTD_HOTPLUG;
4053 break;
4054 default:
4055 MISSING_CASE(port->port);
4056 return false;
4057 }
4058
4059 return I915_READ(SDEISR) & bit;
4060}
4061
4062static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4063 struct intel_digital_port *port)
4064{
4065 u32 bit;
4066
4067 switch (port->port) {
4068 case PORT_A:
4069 return true;
4070 case PORT_B:
4071 bit = SDE_PORTB_HOTPLUG_CPT;
4072 break;
4073 case PORT_C:
4074 bit = SDE_PORTC_HOTPLUG_CPT;
4075 break;
4076 case PORT_D:
4077 bit = SDE_PORTD_HOTPLUG_CPT;
4078 break;
a78695d3
JN		 4079 case PORT_E:
4080 bit = SDE_PORTE_HOTPLUG_SPT;
4081 break;
0df53b77
JN		 4082 default:
4083 MISSING_CASE(port->port);
4084 return false;
b93433cc 4085 }
1b469639 4086
b93433cc 4087 return I915_READ(SDEISR) & bit;
5eb08b69
ZW		 4088}
4089
7e66bcf2 4090static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
1d245987 4091 struct intel_digital_port *port)
a4fc5ed6 4092{
9642c81c 4093 u32 bit;
5eb08b69 4094
9642c81c
JN		 4095 switch (port->port) {
4096 case PORT_B:
4097 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4098 break;
4099 case PORT_C:
4100 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4101 break;
4102 case PORT_D:
4103 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4104 break;
4105 default:
4106 MISSING_CASE(port->port);
4107 return false;
4108 }
4109
4110 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4111}
4112
0780cd36
VS		 4113static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4114 struct intel_digital_port *port)
9642c81c
JN		 4115{
4116 u32 bit;
4117
4118 switch (port->port) {
4119 case PORT_B:
0780cd36 4120 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4121 break;
4122 case PORT_C:
0780cd36 4123 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4124 break;
4125 case PORT_D:
0780cd36 4126 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4127 break;
4128 default:
4129 MISSING_CASE(port->port);
4130 return false;
a4fc5ed6
KP		 4131 }
4132
1d245987 4133 return I915_READ(PORT_HOTPLUG_STAT) & bit;
2a592bec
DA		 4134}
4135
e464bfde 4136static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
e2ec35a5 4137 struct intel_digital_port *intel_dig_port)
e464bfde 4138{
e2ec35a5
SJ		 4139 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4140 enum port port;
e464bfde
JN		 4141 u32 bit;
4142
e2ec35a5
SJ		 4143 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4144 switch (port) {
e464bfde
JN		 4145 case PORT_A:
4146 bit = BXT_DE_PORT_HP_DDIA;
4147 break;
4148 case PORT_B:
4149 bit = BXT_DE_PORT_HP_DDIB;
4150 break;
4151 case PORT_C:
4152 bit = BXT_DE_PORT_HP_DDIC;
4153 break;
4154 default:
e2ec35a5 4155 MISSING_CASE(port);
e464bfde
JN		 4156 return false;
4157 }
4158
4159 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4160}
4161
7e66bcf2
JN		 4162/*
4163 * intel_digital_port_connected - is the specified port connected?
4164 * @dev_priv: i915 private structure
4165 * @port: the port to test
4166 *
4167 * Return %true if @port is connected, %false otherwise.
4168 */
237ed86c 4169bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
7e66bcf2
JN		 4170 struct intel_digital_port *port)
4171{
0df53b77 4172 if (HAS_PCH_IBX(dev_priv))
7e66bcf2 4173 return ibx_digital_port_connected(dev_priv, port);
22824fac 4174 else if (HAS_PCH_SPLIT(dev_priv))
0df53b77 4175 return cpt_digital_port_connected(dev_priv, port);
e464bfde
JN		 4176 else if (IS_BROXTON(dev_priv))
4177 return bxt_digital_port_connected(dev_priv, port);
0780cd36
VS		 4178 else if (IS_GM45(dev_priv))
4179 return gm45_digital_port_connected(dev_priv, port);
7e66bcf2
JN		 4180 else
4181 return g4x_digital_port_connected(dev_priv, port);
4182}
4183
8c241fef 4184static struct edid *
beb60608 4185intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4186{
beb60608 4187 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4188
9cd300e0
JN		 4189 /* use cached edid if we have one */
4190 if (intel_connector->edid) {
9cd300e0
JN		 4191 /* invalid edid */
4192 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4193 return NULL;
4194
55e9edeb 4195 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4196 } else
4197 return drm_get_edid(&intel_connector->base,
4198 &intel_dp->aux.ddc);
4199}
8c241fef 4200
beb60608
CW		 4201static void
4202intel_dp_set_edid(struct intel_dp *intel_dp)
4203{
4204 struct intel_connector *intel_connector = intel_dp->attached_connector;
4205 struct edid *edid;
8c241fef 4206
f21a2198 4207 intel_dp_unset_edid(intel_dp);
beb60608
CW		 4208 edid = intel_dp_get_edid(intel_dp);
4209 intel_connector->detect_edid = edid;
4210
4211 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4212 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4213 else
4214 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4215}
4216
beb60608
CW		 4217static void
4218intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4219{
beb60608 4220 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4221
beb60608
CW		 4222 kfree(intel_connector->detect_edid);
4223 intel_connector->detect_edid = NULL;
9cd300e0 4224
beb60608
CW		 4225 intel_dp->has_audio = false;
4226}
d6f24d0f 4227
f21a2198
SS		 4228static void
4229intel_dp_long_pulse(struct intel_connector *intel_connector)
a9756bb5 4230{
f21a2198 4231 struct drm_connector *connector = &intel_connector->base;
a9756bb5 4232 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4233 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4234 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4235 struct drm_device *dev = connector->dev;
a9756bb5 4236 enum drm_connector_status status;
671dedd2 4237 enum intel_display_power_domain power_domain;
0e32b39c 4238 bool ret;
09b1eb13 4239 u8 sink_irq_vector;
a9756bb5 4240
25f78f58
VS		 4241 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4242 intel_display_power_get(to_i915(dev), power_domain);
a9756bb5 4243
d410b56d
CW		 4244 /* Can't disconnect eDP, but you can close the lid... */
4245 if (is_edp(intel_dp))
4246 status = edp_detect(intel_dp);
c555a81d
ACO		 4247 else if (intel_digital_port_connected(to_i915(dev),
4248 dp_to_dig_port(intel_dp)))
4249 status = intel_dp_detect_dpcd(intel_dp);
a9756bb5 4250 else
c555a81d
ACO		 4251 status = connector_status_disconnected;
4252
4df6960e
SS		 4253 if (status != connector_status_connected) {
4254 intel_dp->compliance_test_active = 0;
4255 intel_dp->compliance_test_type = 0;
4256 intel_dp->compliance_test_data = 0;
4257
0e505a08 4258 if (intel_dp->is_mst) {
4259 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4260 intel_dp->is_mst,
4261 intel_dp->mst_mgr.mst_state);
4262 intel_dp->is_mst = false;
4263 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4264 intel_dp->is_mst);
4265 }
4266
c8c8fb33 4267 goto out;
4df6960e 4268 }
a9756bb5 4269
f21a2198
SS		 4270 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4271 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4272
0d198328
AJ		 4273 intel_dp_probe_oui(intel_dp);
4274
0e32b39c
DA		 4275 ret = intel_dp_probe_mst(intel_dp);
4276 if (ret) {
f21a2198
SS		 4277 /*
4278 * If we are in MST mode then this connector
4279 * won't appear connected or have anything
4280 * with EDID on it
4281 */
0e32b39c
DA		 4282 status = connector_status_disconnected;
4283 goto out;
7d23e3c3
SS		 4284 } else if (connector->status == connector_status_connected) {
4285 /*
4286 * If display was connected already and is still connected
4287 * check links status, there has been known issues of
4288 * link loss triggerring long pulse!!!!
4289 */
4290 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4291 intel_dp_check_link_status(intel_dp);
4292 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4293 goto out;
0e32b39c
DA		 4294 }
4295
4df6960e
SS		 4296 /*
4297 * Clearing NACK and defer counts to get their exact values
4298 * while reading EDID which are required by Compliance tests
4299 * 4.2.2.4 and 4.2.2.5
4300 */
4301 intel_dp->aux.i2c_nack_count = 0;
4302 intel_dp->aux.i2c_defer_count = 0;
4303
beb60608 4304 intel_dp_set_edid(intel_dp);
a9756bb5 4305
c8c8fb33 4306 status = connector_status_connected;
7d23e3c3 4307 intel_dp->detect_done = true;
c8c8fb33 4308
09b1eb13
TP		 4309 /* Try to read the source of the interrupt */
4310 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4311 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4312 /* Clear interrupt source */
4313 drm_dp_dpcd_writeb(&intel_dp->aux,
4314 DP_DEVICE_SERVICE_IRQ_VECTOR,
4315 sink_irq_vector);
4316
4317 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4318 intel_dp_handle_test_request(intel_dp);
4319 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4320 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4321 }
4322
c8c8fb33 4323out:
0e505a08 4324 if ((status != connector_status_connected) &&
4325 (intel_dp->is_mst == false))
f21a2198 4326 intel_dp_unset_edid(intel_dp);
7d23e3c3 4327
25f78f58 4328 intel_display_power_put(to_i915(dev), power_domain);
f21a2198
SS		 4329 return;
4330}
4331
4332static enum drm_connector_status
4333intel_dp_detect(struct drm_connector *connector, bool force)
4334{
4335 struct intel_dp *intel_dp = intel_attached_dp(connector);
4336 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4337 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4338 struct intel_connector *intel_connector = to_intel_connector(connector);
4339
4340 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4341 connector->base.id, connector->name);
4342
4343 if (intel_dp->is_mst) {
4344 /* MST devices are disconnected from a monitor POV */
4345 intel_dp_unset_edid(intel_dp);
4346 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4347 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4348 return connector_status_disconnected;
4349 }
4350
7d23e3c3
SS		 4351 /* If full detect is not performed yet, do a full detect */
4352 if (!intel_dp->detect_done)
4353 intel_dp_long_pulse(intel_dp->attached_connector);
4354
4355 intel_dp->detect_done = false;
f21a2198
SS		 4356
4357 if (intel_connector->detect_edid)
4358 return connector_status_connected;
4359 else
4360 return connector_status_disconnected;
a4fc5ed6
KP		 4361}
4362
beb60608
CW		 4363static void
4364intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4365{
df0e9248 4366 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4367 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
25f78f58 4368 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
671dedd2 4369 enum intel_display_power_domain power_domain;
a4fc5ed6 4370
beb60608
CW		 4371 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4372 connector->base.id, connector->name);
4373 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4374
beb60608
CW		 4375 if (connector->status != connector_status_connected)
4376 return;
671dedd2 4377
25f78f58
VS		 4378 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4379 intel_display_power_get(dev_priv, power_domain);
beb60608
CW		 4380
4381 intel_dp_set_edid(intel_dp);
4382
25f78f58 4383 intel_display_power_put(dev_priv, power_domain);
beb60608
CW		 4384
4385 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4386 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4387}
4388
4389static int intel_dp_get_modes(struct drm_connector *connector)
4390{
4391 struct intel_connector *intel_connector = to_intel_connector(connector);
4392 struct edid *edid;
4393
4394 edid = intel_connector->detect_edid;
4395 if (edid) {
4396 int ret = intel_connector_update_modes(connector, edid);
4397 if (ret)
4398 return ret;
4399 }
32f9d658 4400
f8779fda 4401 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4402 if (is_edp(intel_attached_dp(connector)) &&
4403 intel_connector->panel.fixed_mode) {
f8779fda 4404 struct drm_display_mode *mode;
beb60608
CW		 4405
4406 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4407 intel_connector->panel.fixed_mode);
f8779fda 4408 if (mode) {
32f9d658
ZW		 4409 drm_mode_probed_add(connector, mode);
4410 return 1;
4411 }
4412 }
beb60608 4413
32f9d658 4414 return 0;
a4fc5ed6
KP		 4415}
4416
1aad7ac0
CW		 4417static bool
4418intel_dp_detect_audio(struct drm_connector *connector)
4419{
1aad7ac0 4420 bool has_audio = false;
beb60608 4421 struct edid *edid;
1aad7ac0 4422
beb60608
CW		 4423 edid = to_intel_connector(connector)->detect_edid;
4424 if (edid)
1aad7ac0 4425 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4426
1aad7ac0
CW		 4427 return has_audio;
4428}
4429
f684960e
CW		 4430static int
4431intel_dp_set_property(struct drm_connector *connector,
4432 struct drm_property *property,
4433 uint64_t val)
4434{
e953fd7b 4435 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4436 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4437 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4438 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4439 int ret;
4440
662595df 4441 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4442 if (ret)
4443 return ret;
4444
3f43c48d 4445 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4446 int i = val;
4447 bool has_audio;
4448
4449 if (i == intel_dp->force_audio)
f684960e
CW		 4450 return 0;
4451
1aad7ac0 4452 intel_dp->force_audio = i;
f684960e 4453
c3e5f67b 4454 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4455 has_audio = intel_dp_detect_audio(connector);
4456 else
c3e5f67b 4457 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4458
4459 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4460 return 0;
4461
1aad7ac0 4462 intel_dp->has_audio = has_audio;
f684960e
CW		 4463 goto done;
4464 }
4465
e953fd7b 4466 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 4467 bool old_auto = intel_dp->color_range_auto;
0f2a2a75 4468 bool old_range = intel_dp->limited_color_range;
ae4edb80 4469
55bc60db
VS		 4470 switch (val) {
4471 case INTEL_BROADCAST_RGB_AUTO:
4472 intel_dp->color_range_auto = true;
4473 break;
4474 case INTEL_BROADCAST_RGB_FULL:
4475 intel_dp->color_range_auto = false;
0f2a2a75 4476 intel_dp->limited_color_range = false;
55bc60db
VS		 4477 break;
4478 case INTEL_BROADCAST_RGB_LIMITED:
4479 intel_dp->color_range_auto = false;
0f2a2a75 4480 intel_dp->limited_color_range = true;
55bc60db
VS		 4481 break;
4482 default:
4483 return -EINVAL;
4484 }
ae4edb80
DV		 4485
4486 if (old_auto == intel_dp->color_range_auto &&
0f2a2a75 4487 old_range == intel_dp->limited_color_range)
ae4edb80
DV		 4488 return 0;
4489
e953fd7b
CW		 4490 goto done;
4491 }
4492
53b41837
YN		 4493 if (is_edp(intel_dp) &&
4494 property == connector->dev->mode_config.scaling_mode_property) {
4495 if (val == DRM_MODE_SCALE_NONE) {
4496 DRM_DEBUG_KMS("no scaling not supported\n");
4497 return -EINVAL;
4498 }
234126c6
VS		 4499 if (HAS_GMCH_DISPLAY(dev_priv) &&
4500 val == DRM_MODE_SCALE_CENTER) {
4501 DRM_DEBUG_KMS("centering not supported\n");
4502 return -EINVAL;
4503 }
53b41837
YN		 4504
4505 if (intel_connector->panel.fitting_mode == val) {
4506 /* the eDP scaling property is not changed */
4507 return 0;
4508 }
4509 intel_connector->panel.fitting_mode = val;
4510
4511 goto done;
4512 }
4513
f684960e
CW		 4514 return -EINVAL;
4515
4516done:
c0c36b94
CW		 4517 if (intel_encoder->base.crtc)
4518 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4519
4520 return 0;
4521}
4522
c191eca1
CW		 4523static void
4524intel_dp_connector_unregister(struct drm_connector *connector)
4525{
4526 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4527 intel_connector_unregister(connector);
4528}
4529
a4fc5ed6 4530static void
73845adf 4531intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4532{
1d508706 4533 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4534
10e972d3 4535 kfree(intel_connector->detect_edid);
beb60608 4536
9cd300e0
JN		 4537 if (!IS_ERR_OR_NULL(intel_connector->edid))
4538 kfree(intel_connector->edid);
4539
acd8db10
PZ		 4540 /* Can't call is_edp() since the encoder may have been destroyed
4541 * already. */
4542 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4543 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4544
a4fc5ed6 4545 drm_connector_cleanup(connector);
55f78c43 4546 kfree(connector);
a4fc5ed6
KP		 4547}
4548
00c09d70 4549void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4550{
da63a9f2
PZ		 4551 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4552 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4553
0e32b39c 4554 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4555 if (is_edp(intel_dp)) {
4556 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4557 /*
4558 * vdd might still be enabled do to the delayed vdd off.
4559 * Make sure vdd is actually turned off here.
4560 */
773538e8 4561 pps_lock(intel_dp);
4be73780 4562 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4563 pps_unlock(intel_dp);
4564
01527b31
CT		 4565 if (intel_dp->edp_notifier.notifier_call) {
4566 unregister_reboot_notifier(&intel_dp->edp_notifier);
4567 intel_dp->edp_notifier.notifier_call = NULL;
4568 }
bd943159 4569 }
99681886
CW		 4570
4571 intel_dp_aux_fini(intel_dp);
4572
c8bd0e49 4573 drm_encoder_cleanup(encoder);
da63a9f2 4574 kfree(intel_dig_port);
24d05927
DV		 4575}
4576
bf93ba67 4577void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
07f9cd0b
ID		 4578{
4579 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4580
4581 if (!is_edp(intel_dp))
4582 return;
4583
951468f3
VS		 4584 /*
4585 * vdd might still be enabled do to the delayed vdd off.
4586 * Make sure vdd is actually turned off here.
4587 */
afa4e53a 4588 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4589 pps_lock(intel_dp);
07f9cd0b 4590 edp_panel_vdd_off_sync(intel_dp);
773538e8 4591 pps_unlock(intel_dp);
07f9cd0b
ID		 4592}
4593
49e6bc51
VS		 4594static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4595{
4596 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4597 struct drm_device *dev = intel_dig_port->base.base.dev;
4598 struct drm_i915_private *dev_priv = dev->dev_private;
4599 enum intel_display_power_domain power_domain;
4600
4601 lockdep_assert_held(&dev_priv->pps_mutex);
4602
4603 if (!edp_have_panel_vdd(intel_dp))
4604 return;
4605
4606 /*
4607 * The VDD bit needs a power domain reference, so if the bit is
4608 * already enabled when we boot or resume, grab this reference and
4609 * schedule a vdd off, so we don't hold on to the reference
4610 * indefinitely.
4611 */
4612 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
25f78f58 4613 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
49e6bc51
VS		 4614 intel_display_power_get(dev_priv, power_domain);
4615
4616 edp_panel_vdd_schedule_off(intel_dp);
4617}
4618
bf93ba67 4619void intel_dp_encoder_reset(struct drm_encoder *encoder)
6d93c0c4 4620{
64989ca4
VS		 4621 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4622 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4623
4624 if (!HAS_DDI(dev_priv))
4625 intel_dp->DP = I915_READ(intel_dp->output_reg);
49e6bc51
VS		 4626
4627 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4628 return;
4629
49e6bc51
VS		 4630 pps_lock(intel_dp);
4631
4632 /*
4633 * Read out the current power sequencer assignment,
4634 * in case the BIOS did something with it.
4635 */
666a4537 4636 if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
49e6bc51
VS		 4637 vlv_initial_power_sequencer_setup(intel_dp);
4638
4639 intel_edp_panel_vdd_sanitize(intel_dp);
4640
4641 pps_unlock(intel_dp);
6d93c0c4
ID		 4642}
4643
a4fc5ed6 4644static const struct drm_connector_funcs intel_dp_connector_funcs = {
4d688a2a 4645 .dpms = drm_atomic_helper_connector_dpms,
a4fc5ed6 4646 .detect = intel_dp_detect,
beb60608 4647 .force = intel_dp_force,
a4fc5ed6 4648 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4649 .set_property = intel_dp_set_property,
2545e4a6 4650 .atomic_get_property = intel_connector_atomic_get_property,
c191eca1 4651 .early_unregister = intel_dp_connector_unregister,
73845adf 4652 .destroy = intel_dp_connector_destroy,
c6f95f27 4653 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4654 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4655};
4656
4657static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4658 .get_modes = intel_dp_get_modes,
4659 .mode_valid = intel_dp_mode_valid,
a4fc5ed6
KP		 4660};
4661
a4fc5ed6 4662static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4663 .reset = intel_dp_encoder_reset,
24d05927 4664 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4665};
4666
b2c5c181 4667enum irqreturn
13cf5504
DA		 4668intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4669{
4670 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4671 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4672 struct drm_device *dev = intel_dig_port->base.base.dev;
4673 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4674 enum intel_display_power_domain power_domain;
b2c5c181 4675 enum irqreturn ret = IRQ_NONE;
1c767b33 4676
2540058f
TI		 4677 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4678 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
0e32b39c 4679 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4680
7a7f84cc
VS		 4681 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4682 /*
4683 * vdd off can generate a long pulse on eDP which
4684 * would require vdd on to handle it, and thus we
4685 * would end up in an endless cycle of
4686 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4687 */
4688 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4689 port_name(intel_dig_port->port));
a8b3d52f 4690 return IRQ_HANDLED;
7a7f84cc
VS		 4691 }
4692
26fbb774
VS		 4693 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4694 port_name(intel_dig_port->port),
0e32b39c 4695 long_hpd ? "long" : "short");
13cf5504 4696
25f78f58 4697 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1c767b33
ID		 4698 intel_display_power_get(dev_priv, power_domain);
4699
0e32b39c 4700 if (long_hpd) {
7d23e3c3
SS		 4701 intel_dp_long_pulse(intel_dp->attached_connector);
4702 if (intel_dp->is_mst)
4703 ret = IRQ_HANDLED;
4704 goto put_power;
0e32b39c 4705
0e32b39c
DA		 4706 } else {
4707 if (intel_dp->is_mst) {
7d23e3c3
SS		 4708 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4709 /*
4710 * If we were in MST mode, and device is not
4711 * there, get out of MST mode
4712 */
4713 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4714 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4715 intel_dp->is_mst = false;
4716 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4717 intel_dp->is_mst);
4718 goto put_power;
4719 }
0e32b39c
DA		 4720 }
4721
39ff747b
SS		 4722 if (!intel_dp->is_mst) {
4723 if (!intel_dp_short_pulse(intel_dp)) {
4724 intel_dp_long_pulse(intel_dp->attached_connector);
4725 goto put_power;
4726 }
4727 }
0e32b39c 4728 }
b2c5c181
DV		 4729
4730 ret = IRQ_HANDLED;
4731
1c767b33
ID		 4732put_power:
4733 intel_display_power_put(dev_priv, power_domain);
4734
4735 return ret;
13cf5504
DA		 4736}
4737
477ec328 4738/* check the VBT to see whether the eDP is on another port */
5d8a7752 4739bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4740{
4741 struct drm_i915_private *dev_priv = dev->dev_private;
36e83a18 4742
53ce81a7
VS		 4743 /*
4744 * eDP not supported on g4x. so bail out early just
4745 * for a bit extra safety in case the VBT is bonkers.
4746 */
4747 if (INTEL_INFO(dev)->gen < 5)
4748 return false;
4749
3b32a35b
VS		 4750 if (port == PORT_A)
4751 return true;
4752
951d9efe 4753 return intel_bios_is_port_edp(dev_priv, port);
36e83a18
ZY		 4754}
4755
0e32b39c 4756void
f684960e
CW		 4757intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4758{
53b41837
YN		 4759 struct intel_connector *intel_connector = to_intel_connector(connector);
4760
3f43c48d 4761 intel_attach_force_audio_property(connector);
e953fd7b 4762 intel_attach_broadcast_rgb_property(connector);
55bc60db 4763 intel_dp->color_range_auto = true;
53b41837
YN		 4764
4765 if (is_edp(intel_dp)) {
4766 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4767 drm_object_attach_property(
4768 &connector->base,
53b41837 4769 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4770 DRM_MODE_SCALE_ASPECT);
4771 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4772 }
f684960e
CW		 4773}
4774
dada1a9f
ID		 4775static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4776{
d28d4731 4777 intel_dp->panel_power_off_time = ktime_get_boottime();
dada1a9f
ID		 4778 intel_dp->last_power_on = jiffies;
4779 intel_dp->last_backlight_off = jiffies;
4780}
4781
67a54566 4782static void
54648618
ID		 4783intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
4784 struct intel_dp *intel_dp, struct edp_power_seq *seq)
67a54566 4785{
b0a08bec 4786 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
8e8232d5 4787 struct pps_registers regs;
453c5420 4788
8e8232d5 4789 intel_pps_get_registers(dev_priv, intel_dp, &regs);
67a54566
DV		 4790
4791 /* Workaround: Need to write PP_CONTROL with the unlock key as
4792 * the very first thing. */
b0a08bec 4793 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 4794
8e8232d5
ID		 4795 pp_on = I915_READ(regs.pp_on);
4796 pp_off = I915_READ(regs.pp_off);
54648618 4797 if (!IS_BROXTON(dev_priv)) {
8e8232d5
ID		 4798 I915_WRITE(regs.pp_ctrl, pp_ctl);
4799 pp_div = I915_READ(regs.pp_div);
b0a08bec 4800 }
67a54566
DV		 4801
4802 /* Pull timing values out of registers */
54648618
ID		 4803 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4804 PANEL_POWER_UP_DELAY_SHIFT;
67a54566 4805
54648618
ID		 4806 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4807 PANEL_LIGHT_ON_DELAY_SHIFT;
67a54566 4808
54648618
ID		 4809 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4810 PANEL_LIGHT_OFF_DELAY_SHIFT;
67a54566 4811
54648618
ID		 4812 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4813 PANEL_POWER_DOWN_DELAY_SHIFT;
67a54566 4814
54648618 4815 if (IS_BROXTON(dev_priv)) {
b0a08bec
VK		 4816 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4817 BXT_POWER_CYCLE_DELAY_SHIFT;
4818 if (tmp > 0)
54648618 4819 seq->t11_t12 = (tmp - 1) * 1000;
b0a08bec 4820 else
54648618 4821 seq->t11_t12 = 0;
b0a08bec 4822 } else {
54648618 4823 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 4824 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 4825 }
54648618
ID		 4826}
4827
de9c1b6b
ID		 4828static void
4829intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
4830{
4831 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4832 state_name,
4833 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
4834}
4835
4836static void
4837intel_pps_verify_state(struct drm_i915_private *dev_priv,
4838 struct intel_dp *intel_dp)
4839{
4840 struct edp_power_seq hw;
4841 struct edp_power_seq *sw = &intel_dp->pps_delays;
4842
4843 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
4844
4845 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
4846 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
4847 DRM_ERROR("PPS state mismatch\n");
4848 intel_pps_dump_state("sw", sw);
4849 intel_pps_dump_state("hw", &hw);
4850 }
4851}
4852
54648618
ID		 4853static void
4854intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4855 struct intel_dp *intel_dp)
4856{
4857 struct drm_i915_private *dev_priv = dev->dev_private;
4858 struct edp_power_seq cur, vbt, spec,
4859 *final = &intel_dp->pps_delays;
4860
4861 lockdep_assert_held(&dev_priv->pps_mutex);
4862
4863 /* already initialized? */
4864 if (final->t11_t12 != 0)
4865 return;
4866
4867 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
67a54566 4868
de9c1b6b 4869 intel_pps_dump_state("cur", &cur);
67a54566 4870
6aa23e65 4871 vbt = dev_priv->vbt.edp.pps;
67a54566
DV		 4872
4873 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4874 * our hw here, which are all in 100usec. */
4875 spec.t1_t3 = 210 * 10;
4876 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4877 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4878 spec.t10 = 500 * 10;
4879 /* This one is special and actually in units of 100ms, but zero
4880 * based in the hw (so we need to add 100 ms). But the sw vbt
4881 * table multiplies it with 1000 to make it in units of 100usec,
4882 * too. */
4883 spec.t11_t12 = (510 + 100) * 10;
4884
de9c1b6b 4885 intel_pps_dump_state("vbt", &vbt);
67a54566
DV		 4886
4887 /* Use the max of the register settings and vbt. If both are
4888 * unset, fall back to the spec limits. */
36b5f425 4889#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4890 spec.field : \
4891 max(cur.field, vbt.field))
4892 assign_final(t1_t3);
4893 assign_final(t8);
4894 assign_final(t9);
4895 assign_final(t10);
4896 assign_final(t11_t12);
4897#undef assign_final
4898
36b5f425 4899#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4900 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4901 intel_dp->backlight_on_delay = get_delay(t8);
4902 intel_dp->backlight_off_delay = get_delay(t9);
4903 intel_dp->panel_power_down_delay = get_delay(t10);
4904 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4905#undef get_delay
4906
f30d26e4
JN		 4907 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4908 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4909 intel_dp->panel_power_cycle_delay);
4910
4911 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4912 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
de9c1b6b
ID		 4913
4914 /*
4915 * We override the HW backlight delays to 1 because we do manual waits
4916 * on them. For T8, even BSpec recommends doing it. For T9, if we
4917 * don't do this, we'll end up waiting for the backlight off delay
4918 * twice: once when we do the manual sleep, and once when we disable
4919 * the panel and wait for the PP_STATUS bit to become zero.
4920 */
4921 final->t8 = 1;
4922 final->t9 = 1;
f30d26e4
JN		 4923}
4924
4925static void
4926intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4927 struct intel_dp *intel_dp)
f30d26e4
JN		 4928{
4929 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 4930 u32 pp_on, pp_off, pp_div, port_sel = 0;
e7dc33f3 4931 int div = dev_priv->rawclk_freq / 1000;
8e8232d5 4932 struct pps_registers regs;
ad933b56 4933 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4934 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4935
e39b999a 4936 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 4937
8e8232d5 4938 intel_pps_get_registers(dev_priv, intel_dp, &regs);
453c5420 4939
f30d26e4 4940 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
de9c1b6b
ID		 4941 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
4942 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4943 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4944 /* Compute the divisor for the pp clock, simply match the Bspec
4945 * formula. */
b0a08bec 4946 if (IS_BROXTON(dev)) {
8e8232d5 4947 pp_div = I915_READ(regs.pp_ctrl);
b0a08bec
VK		 4948 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
4949 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
4950 << BXT_POWER_CYCLE_DELAY_SHIFT);
4951 } else {
4952 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4953 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4954 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4955 }
67a54566
DV		 4956
4957 /* Haswell doesn't have any port selection bits for the panel
4958 * power sequencer any more. */
666a4537 4959 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
ad933b56 4960 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4961 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4962 if (port == PORT_A)
a24c144c 4963 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4964 else
a24c144c 4965 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4966 }
4967
453c5420
JB		 4968 pp_on |= port_sel;
4969
8e8232d5
ID		 4970 I915_WRITE(regs.pp_on, pp_on);
4971 I915_WRITE(regs.pp_off, pp_off);
b0a08bec 4972 if (IS_BROXTON(dev))
8e8232d5 4973 I915_WRITE(regs.pp_ctrl, pp_div);
b0a08bec 4974 else
8e8232d5 4975 I915_WRITE(regs.pp_div, pp_div);
67a54566 4976
67a54566 4977 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
8e8232d5
ID		 4978 I915_READ(regs.pp_on),
4979 I915_READ(regs.pp_off),
b0a08bec 4980 IS_BROXTON(dev) ?
8e8232d5
ID		 4981 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
4982 I915_READ(regs.pp_div));
f684960e
CW		 4983}
4984
b33a2815
VK		 4985/**
4986 * intel_dp_set_drrs_state - program registers for RR switch to take effect
4987 * @dev: DRM device
4988 * @refresh_rate: RR to be programmed
4989 *
4990 * This function gets called when refresh rate (RR) has to be changed from
4991 * one frequency to another. Switches can be between high and low RR
4992 * supported by the panel or to any other RR based on media playback (in
4993 * this case, RR value needs to be passed from user space).
4994 *
4995 * The caller of this function needs to take a lock on dev_priv->drrs.
4996 */
96178eeb 4997static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 4998{
4999 struct drm_i915_private *dev_priv = dev->dev_private;
5000 struct intel_encoder *encoder;
96178eeb
VK		 5001 struct intel_digital_port *dig_port = NULL;
5002 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 5003 struct intel_crtc_state *config = NULL;
439d7ac0 5004 struct intel_crtc *intel_crtc = NULL;
96178eeb 5005 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5006
5007 if (refresh_rate <= 0) {
5008 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5009 return;
5010 }
5011
96178eeb
VK		 5012 if (intel_dp == NULL) {
5013 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5014 return;
5015 }
5016
1fcc9d1c 5017 /*
e4d59f6b
RV		 5018 * FIXME: This needs proper synchronization with psr state for some
5019 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5020 */
439d7ac0 5021
96178eeb
VK		 5022 dig_port = dp_to_dig_port(intel_dp);
5023 encoder = &dig_port->base;
723f9aab 5024 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5025
5026 if (!intel_crtc) {
5027 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5028 return;
5029 }
5030
6e3c9717 5031 config = intel_crtc->config;
439d7ac0 5032
96178eeb 5033 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5034 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5035 return;
5036 }
5037
96178eeb
VK		 5038 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5039 refresh_rate)
439d7ac0
PB		 5040 index = DRRS_LOW_RR;
5041
96178eeb 5042 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5043 DRM_DEBUG_KMS(
5044 "DRRS requested for previously set RR...ignoring\n");
5045 return;
5046 }
5047
5048 if (!intel_crtc->active) {
5049 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5050 return;
5051 }
5052
44395bfe 5053 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5054 switch (index) {
5055 case DRRS_HIGH_RR:
5056 intel_dp_set_m_n(intel_crtc, M1_N1);
5057 break;
5058 case DRRS_LOW_RR:
5059 intel_dp_set_m_n(intel_crtc, M2_N2);
5060 break;
5061 case DRRS_MAX_RR:
5062 default:
5063 DRM_ERROR("Unsupported refreshrate type\n");
5064 }
5065 } else if (INTEL_INFO(dev)->gen > 6) {
f0f59a00 5066 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
649636ef 5067 u32 val;
a4c30b1d 5068
649636ef 5069 val = I915_READ(reg);
439d7ac0 5070 if (index > DRRS_HIGH_RR) {
666a4537 5071 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6fa7aec1
VK		 5072 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5073 else
5074 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5075 } else {
666a4537 5076 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6fa7aec1
VK		 5077 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5078 else
5079 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5080 }
5081 I915_WRITE(reg, val);
5082 }
5083
4e9ac947
VK		 5084 dev_priv->drrs.refresh_rate_type = index;
5085
5086 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5087}
5088
b33a2815
VK		 5089/**
5090 * intel_edp_drrs_enable - init drrs struct if supported
5091 * @intel_dp: DP struct
5092 *
5093 * Initializes frontbuffer_bits and drrs.dp
5094 */
c395578e
VK		 5095void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5096{
5097 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5098 struct drm_i915_private *dev_priv = dev->dev_private;
5099 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5100 struct drm_crtc *crtc = dig_port->base.base.crtc;
5101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5102
5103 if (!intel_crtc->config->has_drrs) {
5104 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5105 return;
5106 }
5107
5108 mutex_lock(&dev_priv->drrs.mutex);
5109 if (WARN_ON(dev_priv->drrs.dp)) {
5110 DRM_ERROR("DRRS already enabled\n");
5111 goto unlock;
5112 }
5113
5114 dev_priv->drrs.busy_frontbuffer_bits = 0;
5115
5116 dev_priv->drrs.dp = intel_dp;
5117
5118unlock:
5119 mutex_unlock(&dev_priv->drrs.mutex);
5120}
5121
b33a2815
VK		 5122/**
5123 * intel_edp_drrs_disable - Disable DRRS
5124 * @intel_dp: DP struct
5125 *
5126 */
c395578e
VK		 5127void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5128{
5129 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5130 struct drm_i915_private *dev_priv = dev->dev_private;
5131 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5132 struct drm_crtc *crtc = dig_port->base.base.crtc;
5133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5134
5135 if (!intel_crtc->config->has_drrs)
5136 return;
5137
5138 mutex_lock(&dev_priv->drrs.mutex);
5139 if (!dev_priv->drrs.dp) {
5140 mutex_unlock(&dev_priv->drrs.mutex);
5141 return;
5142 }
5143
5144 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5145 intel_dp_set_drrs_state(dev_priv->dev,
5146 intel_dp->attached_connector->panel.
5147 fixed_mode->vrefresh);
5148
5149 dev_priv->drrs.dp = NULL;
5150 mutex_unlock(&dev_priv->drrs.mutex);
5151
5152 cancel_delayed_work_sync(&dev_priv->drrs.work);
5153}
5154
4e9ac947
VK		 5155static void intel_edp_drrs_downclock_work(struct work_struct *work)
5156{
5157 struct drm_i915_private *dev_priv =
5158 container_of(work, typeof(*dev_priv), drrs.work.work);
5159 struct intel_dp *intel_dp;
5160
5161 mutex_lock(&dev_priv->drrs.mutex);
5162
5163 intel_dp = dev_priv->drrs.dp;
5164
5165 if (!intel_dp)
5166 goto unlock;
5167
439d7ac0 5168 /*
4e9ac947
VK		 5169 * The delayed work can race with an invalidate hence we need to
5170 * recheck.
439d7ac0
PB		 5171 */
5172
4e9ac947
VK		 5173 if (dev_priv->drrs.busy_frontbuffer_bits)
5174 goto unlock;
439d7ac0 5175
4e9ac947
VK		 5176 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5177 intel_dp_set_drrs_state(dev_priv->dev,
5178 intel_dp->attached_connector->panel.
5179 downclock_mode->vrefresh);
439d7ac0 5180
4e9ac947 5181unlock:
4e9ac947 5182 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5183}
5184
b33a2815 5185/**
0ddfd203 5186 * intel_edp_drrs_invalidate - Disable Idleness DRRS
b33a2815
VK		 5187 * @dev: DRM device
5188 * @frontbuffer_bits: frontbuffer plane tracking bits
5189 *
0ddfd203
R		 5190 * This function gets called everytime rendering on the given planes start.
5191 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5192 *
5193 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5194 */
a93fad0f
VK		 5195void intel_edp_drrs_invalidate(struct drm_device *dev,
5196 unsigned frontbuffer_bits)
5197{
5198 struct drm_i915_private *dev_priv = dev->dev_private;
5199 struct drm_crtc *crtc;
5200 enum pipe pipe;
5201
9da7d693 5202 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5203 return;
5204
88f933a8 5205 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5206
a93fad0f 5207 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5208 if (!dev_priv->drrs.dp) {
5209 mutex_unlock(&dev_priv->drrs.mutex);
5210 return;
5211 }
5212
a93fad0f
VK		 5213 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5214 pipe = to_intel_crtc(crtc)->pipe;
5215
c1d038c6
DV		 5216 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5217 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5218
0ddfd203 5219 /* invalidate means busy screen hence upclock */
c1d038c6 5220 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
a93fad0f
VK		 5221 intel_dp_set_drrs_state(dev_priv->dev,
5222 dev_priv->drrs.dp->attached_connector->panel.
5223 fixed_mode->vrefresh);
a93fad0f 5224
a93fad0f
VK		 5225 mutex_unlock(&dev_priv->drrs.mutex);
5226}
5227
b33a2815 5228/**
0ddfd203 5229 * intel_edp_drrs_flush - Restart Idleness DRRS
b33a2815
VK		 5230 * @dev: DRM device
5231 * @frontbuffer_bits: frontbuffer plane tracking bits
5232 *
0ddfd203
R		 5233 * This function gets called every time rendering on the given planes has
5234 * completed or flip on a crtc is completed. So DRRS should be upclocked
5235 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5236 * if no other planes are dirty.
b33a2815
VK		 5237 *
5238 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5239 */
a93fad0f
VK		 5240void intel_edp_drrs_flush(struct drm_device *dev,
5241 unsigned frontbuffer_bits)
5242{
5243 struct drm_i915_private *dev_priv = dev->dev_private;
5244 struct drm_crtc *crtc;
5245 enum pipe pipe;
5246
9da7d693 5247 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5248 return;
5249
88f933a8 5250 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5251
a93fad0f 5252 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5253 if (!dev_priv->drrs.dp) {
5254 mutex_unlock(&dev_priv->drrs.mutex);
5255 return;
5256 }
5257
a93fad0f
VK		 5258 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5259 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5260
5261 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5262 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5263
0ddfd203 5264 /* flush means busy screen hence upclock */
c1d038c6 5265 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
0ddfd203
R		 5266 intel_dp_set_drrs_state(dev_priv->dev,
5267 dev_priv->drrs.dp->attached_connector->panel.
5268 fixed_mode->vrefresh);
5269
5270 /*
5271 * flush also means no more activity hence schedule downclock, if all
5272 * other fbs are quiescent too
5273 */
5274 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5275 schedule_delayed_work(&dev_priv->drrs.work,
5276 msecs_to_jiffies(1000));
5277 mutex_unlock(&dev_priv->drrs.mutex);
5278}
5279
b33a2815
VK		 5280/**
5281 * DOC: Display Refresh Rate Switching (DRRS)
5282 *
5283 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5284 * which enables swtching between low and high refresh rates,
5285 * dynamically, based on the usage scenario. This feature is applicable
5286 * for internal panels.
5287 *
5288 * Indication that the panel supports DRRS is given by the panel EDID, which
5289 * would list multiple refresh rates for one resolution.
5290 *
5291 * DRRS is of 2 types - static and seamless.
5292 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5293 * (may appear as a blink on screen) and is used in dock-undock scenario.
5294 * Seamless DRRS involves changing RR without any visual effect to the user
5295 * and can be used during normal system usage. This is done by programming
5296 * certain registers.
5297 *
5298 * Support for static/seamless DRRS may be indicated in the VBT based on
5299 * inputs from the panel spec.
5300 *
5301 * DRRS saves power by switching to low RR based on usage scenarios.
5302 *
2e7a5701
DV		 5303 * The implementation is based on frontbuffer tracking implementation. When
5304 * there is a disturbance on the screen triggered by user activity or a periodic
5305 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5306 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5307 * made.
5308 *
5309 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5310 * and intel_edp_drrs_flush() are called.
b33a2815
VK		 5311 *
5312 * DRRS can be further extended to support other internal panels and also
5313 * the scenario of video playback wherein RR is set based on the rate
5314 * requested by userspace.
5315 */
5316
5317/**
5318 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5319 * @intel_connector: eDP connector
5320 * @fixed_mode: preferred mode of panel
5321 *
5322 * This function is called only once at driver load to initialize basic
5323 * DRRS stuff.
5324 *
5325 * Returns:
5326 * Downclock mode if panel supports it, else return NULL.
5327 * DRRS support is determined by the presence of downclock mode (apart
5328 * from VBT setting).
5329 */
4f9db5b5 5330static struct drm_display_mode *
96178eeb
VK		 5331intel_dp_drrs_init(struct intel_connector *intel_connector,
5332 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5333{
5334 struct drm_connector *connector = &intel_connector->base;
96178eeb 5335 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5336 struct drm_i915_private *dev_priv = dev->dev_private;
5337 struct drm_display_mode *downclock_mode = NULL;
5338
9da7d693
DV		 5339 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5340 mutex_init(&dev_priv->drrs.mutex);
5341
4f9db5b5
PB		 5342 if (INTEL_INFO(dev)->gen <= 6) {
5343 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5344 return NULL;
5345 }
5346
5347 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5348 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5349 return NULL;
5350 }
5351
5352 downclock_mode = intel_find_panel_downclock
5353 (dev, fixed_mode, connector);
5354
5355 if (!downclock_mode) {
a1d26342 5356 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5357 return NULL;
5358 }
5359
96178eeb 5360 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5361
96178eeb 5362 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5363 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5364 return downclock_mode;
5365}
5366
ed92f0b2 5367static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5368 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5369{
5370 struct drm_connector *connector = &intel_connector->base;
5371 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5372 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5373 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5374 struct drm_i915_private *dev_priv = dev->dev_private;
5375 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5376 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5377 bool has_dpcd;
5378 struct drm_display_mode *scan;
5379 struct edid *edid;
6517d273 5380 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5381
5382 if (!is_edp(intel_dp))
5383 return true;
5384
97a824e1
ID		 5385 /*
5386 * On IBX/CPT we may get here with LVDS already registered. Since the
5387 * driver uses the only internal power sequencer available for both
5388 * eDP and LVDS bail out early in this case to prevent interfering
5389 * with an already powered-on LVDS power sequencer.
5390 */
5391 if (intel_get_lvds_encoder(dev)) {
5392 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5393 DRM_INFO("LVDS was detected, not registering eDP\n");
5394
5395 return false;
5396 }
5397
49e6bc51 5398 pps_lock(intel_dp);
b4d06ede
ID		 5399
5400 intel_dp_init_panel_power_timestamps(intel_dp);
5401
5402 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5403 vlv_initial_power_sequencer_setup(intel_dp);
5404 } else {
5405 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5406 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5407 }
5408
49e6bc51 5409 intel_edp_panel_vdd_sanitize(intel_dp);
b4d06ede 5410
49e6bc51 5411 pps_unlock(intel_dp);
63635217 5412
ed92f0b2 5413 /* Cache DPCD and EDID for edp. */
ed92f0b2 5414 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5415
5416 if (has_dpcd) {
5417 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5418 dev_priv->no_aux_handshake =
5419 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5420 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5421 } else {
5422 /* if this fails, presume the device is a ghost */
5423 DRM_INFO("failed to retrieve link info, disabling eDP\n");
b4d06ede 5424 goto out_vdd_off;
ed92f0b2
PZ		 5425 }
5426
060c8778 5427 mutex_lock(&dev->mode_config.mutex);
0b99836f 5428 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5429 if (edid) {
5430 if (drm_add_edid_modes(connector, edid)) {
5431 drm_mode_connector_update_edid_property(connector,
5432 edid);
5433 drm_edid_to_eld(connector, edid);
5434 } else {
5435 kfree(edid);
5436 edid = ERR_PTR(-EINVAL);
5437 }
5438 } else {
5439 edid = ERR_PTR(-ENOENT);
5440 }
5441 intel_connector->edid = edid;
5442
5443 /* prefer fixed mode from EDID if available */
5444 list_for_each_entry(scan, &connector->probed_modes, head) {
5445 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5446 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5447 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5448 intel_connector, fixed_mode);
ed92f0b2
PZ		 5449 break;
5450 }
5451 }
5452
5453 /* fallback to VBT if available for eDP */
5454 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5455 fixed_mode = drm_mode_duplicate(dev,
5456 dev_priv->vbt.lfp_lvds_vbt_mode);
df457245 5457 if (fixed_mode) {
ed92f0b2 5458 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
df457245
VS		 5459 connector->display_info.width_mm = fixed_mode->width_mm;
5460 connector->display_info.height_mm = fixed_mode->height_mm;
5461 }
ed92f0b2 5462 }
060c8778 5463 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5464
666a4537 5465 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
01527b31
CT		 5466 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5467 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5468
5469 /*
5470 * Figure out the current pipe for the initial backlight setup.
5471 * If the current pipe isn't valid, try the PPS pipe, and if that
5472 * fails just assume pipe A.
5473 */
5474 if (IS_CHERRYVIEW(dev))
5475 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5476 else
5477 pipe = PORT_TO_PIPE(intel_dp->DP);
5478
5479 if (pipe != PIPE_A && pipe != PIPE_B)
5480 pipe = intel_dp->pps_pipe;
5481
5482 if (pipe != PIPE_A && pipe != PIPE_B)
5483 pipe = PIPE_A;
5484
5485 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5486 pipe_name(pipe));
01527b31
CT		 5487 }
5488
4f9db5b5 5489 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5507faeb 5490 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6517d273 5491 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5492
5493 return true;
b4d06ede
ID		 5494
5495out_vdd_off:
5496 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5497 /*
5498 * vdd might still be enabled do to the delayed vdd off.
5499 * Make sure vdd is actually turned off here.
5500 */
5501 pps_lock(intel_dp);
5502 edp_panel_vdd_off_sync(intel_dp);
5503 pps_unlock(intel_dp);
5504
5505 return false;
ed92f0b2
PZ		 5506}
5507
16c25533 5508bool
f0fec3f2
PZ		 5509intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5510 struct intel_connector *intel_connector)
a4fc5ed6 5511{
f0fec3f2
PZ		 5512 struct drm_connector *connector = &intel_connector->base;
5513 struct intel_dp *intel_dp = &intel_dig_port->dp;
5514 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5515 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5516 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5517 enum port port = intel_dig_port->port;
a121f4e5 5518 int type, ret;
a4fc5ed6 5519
ccb1a831
VS		 5520 if (WARN(intel_dig_port->max_lanes < 1,
5521 "Not enough lanes (%d) for DP on port %c\n",
5522 intel_dig_port->max_lanes, port_name(port)))
5523 return false;
5524
a4a5d2f8
VS		 5525 intel_dp->pps_pipe = INVALID_PIPE;
5526
ec5b01dd 5527 /* intel_dp vfuncs */
b6b5e383
DL		 5528 if (INTEL_INFO(dev)->gen >= 9)
5529 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
ec5b01dd
DL		 5530 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5531 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5532 else if (HAS_PCH_SPLIT(dev))
5533 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5534 else
6ffb1be7 5535 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
ec5b01dd 5536
b9ca5fad
DL		 5537 if (INTEL_INFO(dev)->gen >= 9)
5538 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5539 else
6ffb1be7 5540 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
153b1100 5541
ad64217b
ACO		 5542 if (HAS_DDI(dev))
5543 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5544
0767935e
DV		 5545 /* Preserve the current hw state. */
5546 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5547 intel_dp->attached_connector = intel_connector;
3d3dc149 5548
3b32a35b 5549 if (intel_dp_is_edp(dev, port))
b329530c 5550 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5551 else
5552 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5553
f7d24902
ID		 5554 /*
5555 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5556 * for DP the encoder type can be set by the caller to
5557 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5558 */
5559 if (type == DRM_MODE_CONNECTOR_eDP)
5560 intel_encoder->type = INTEL_OUTPUT_EDP;
5561
c17ed5b5 5562 /* eDP only on port B and/or C on vlv/chv */
666a4537
WB		 5563 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5564 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
c17ed5b5
VS		 5565 return false;
5566
e7281eab
ID		 5567 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5568 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5569 port_name(port));
5570
b329530c 5571 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5572 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5573
a4fc5ed6
KP		 5574 connector->interlace_allowed = true;
5575 connector->doublescan_allowed = 0;
5576
f0fec3f2 5577 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5578 edp_panel_vdd_work);
a4fc5ed6 5579
df0e9248 5580 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5581 drm_connector_register(connector);
a4fc5ed6 5582
affa9354 5583 if (HAS_DDI(dev))
bcbc889b
PZ		 5584 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5585 else
5586 intel_connector->get_hw_state = intel_connector_get_hw_state;
5587
0b99836f 5588 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5589 switch (port) {
5590 case PORT_A:
1d843f9d 5591 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5592 break;
5593 case PORT_B:
1d843f9d 5594 intel_encoder->hpd_pin = HPD_PORT_B;
e87a005d 5595 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
cf1d5883 5596 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5597 break;
5598 case PORT_C:
1d843f9d 5599 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5600 break;
5601 case PORT_D:
1d843f9d 5602 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30 5603 break;
26951caf
XZ		 5604 case PORT_E:
5605 intel_encoder->hpd_pin = HPD_PORT_E;
5606 break;
ab9d7c30 5607 default:
ad1c0b19 5608 BUG();
5eb08b69
ZW		 5609 }
5610
a121f4e5
VS		 5611 ret = intel_dp_aux_init(intel_dp, intel_connector);
5612 if (ret)
5613 goto fail;
c1f05264 5614
0e32b39c 5615 /* init MST on ports that can support it */
0c9b3715
JN		 5616 if (HAS_DP_MST(dev) &&
5617 (port == PORT_B || port == PORT_C || port == PORT_D))
5618 intel_dp_mst_encoder_init(intel_dig_port,
5619 intel_connector->base.base.id);
0e32b39c 5620
36b5f425 5621 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
a121f4e5
VS		 5622 intel_dp_aux_fini(intel_dp);
5623 intel_dp_mst_encoder_cleanup(intel_dig_port);
5624 goto fail;
b2f246a8 5625 }
32f9d658 5626
f684960e
CW		 5627 intel_dp_add_properties(intel_dp, connector);
5628
a4fc5ed6
KP		 5629 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5630 * 0xd. Failure to do so will result in spurious interrupts being
5631 * generated on the port when a cable is not attached.
5632 */
5633 if (IS_G4X(dev) && !IS_GM45(dev)) {
5634 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5635 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5636 }
16c25533 5637
aa7471d2
JN		 5638 i915_debugfs_connector_add(connector);
5639
16c25533 5640 return true;
a121f4e5
VS		 5641
5642fail:
a121f4e5
VS		 5643 drm_connector_unregister(connector);
5644 drm_connector_cleanup(connector);
5645
5646 return false;
a4fc5ed6 5647}
f0fec3f2 5648
457c52d8
CW		 5649bool intel_dp_init(struct drm_device *dev,
5650 i915_reg_t output_reg,
5651 enum port port)
f0fec3f2 5652{
13cf5504 5653 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5654 struct intel_digital_port *intel_dig_port;
5655 struct intel_encoder *intel_encoder;
5656 struct drm_encoder *encoder;
5657 struct intel_connector *intel_connector;
5658
b14c5679 5659 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2 5660 if (!intel_dig_port)
457c52d8 5661 return false;
f0fec3f2 5662
08d9bc92 5663 intel_connector = intel_connector_alloc();
11aee0f6
SM		 5664 if (!intel_connector)
5665 goto err_connector_alloc;
f0fec3f2
PZ		 5666
5667 intel_encoder = &intel_dig_port->base;
5668 encoder = &intel_encoder->base;
5669
893da0c9 5670 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
580d8ed5 5671 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
893da0c9 5672 goto err_encoder_init;
f0fec3f2 5673
5bfe2ac0 5674 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5675 intel_encoder->disable = intel_disable_dp;
00c09d70 5676 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5677 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5678 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5679 if (IS_CHERRYVIEW(dev)) {
9197c88b 5680 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5681 intel_encoder->pre_enable = chv_pre_enable_dp;
5682 intel_encoder->enable = vlv_enable_dp;
580d3811 5683 intel_encoder->post_disable = chv_post_disable_dp;
d6db995f 5684 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
e4a1d846 5685 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5686 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5687 intel_encoder->pre_enable = vlv_pre_enable_dp;
5688 intel_encoder->enable = vlv_enable_dp;
49277c31 5689 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5690 } else {
ecff4f3b
JN		 5691 intel_encoder->pre_enable = g4x_pre_enable_dp;
5692 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5693 if (INTEL_INFO(dev)->gen >= 5)
5694 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5695 }
f0fec3f2 5696
174edf1f 5697 intel_dig_port->port = port;
f0fec3f2 5698 intel_dig_port->dp.output_reg = output_reg;
ccb1a831 5699 intel_dig_port->max_lanes = 4;
f0fec3f2 5700
00c09d70 5701 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5702 if (IS_CHERRYVIEW(dev)) {
5703 if (port == PORT_D)
5704 intel_encoder->crtc_mask = 1 << 2;
5705 else
5706 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5707 } else {
5708 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5709 }
bc079e8b 5710 intel_encoder->cloneable = 0;
f0fec3f2 5711
13cf5504 5712 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 5713 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 5714
11aee0f6
SM		 5715 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5716 goto err_init_connector;
5717
457c52d8 5718 return true;
11aee0f6
SM		 5719
5720err_init_connector:
5721 drm_encoder_cleanup(encoder);
893da0c9 5722err_encoder_init:
11aee0f6
SM		 5723 kfree(intel_connector);
5724err_connector_alloc:
5725 kfree(intel_dig_port);
457c52d8 5726 return false;
f0fec3f2 5727}
0e32b39c
DA		 5728
5729void intel_dp_mst_suspend(struct drm_device *dev)
5730{
5731 struct drm_i915_private *dev_priv = dev->dev_private;
5732 int i;
5733
5734 /* disable MST */
5735 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5736 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 5737 if (!intel_dig_port)
5738 continue;
5739
5740 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5741 if (!intel_dig_port->dp.can_mst)
5742 continue;
5743 if (intel_dig_port->dp.is_mst)
5744 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5745 }
5746 }
5747}
5748
5749void intel_dp_mst_resume(struct drm_device *dev)
5750{
5751 struct drm_i915_private *dev_priv = dev->dev_private;
5752 int i;
5753
5754 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5755 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 5756 if (!intel_dig_port)
5757 continue;
5758 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5759 int ret;
5760
5761 if (!intel_dig_port->dp.can_mst)
5762 continue;
5763
5764 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5765 if (ret != 0) {
5766 intel_dp_check_mst_status(&intel_dig_port->dp);
5767 }
5768 }
5769 }
5770}
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