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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
01527b31 CT |
31 | #include <linux/notifier.h> |
32 | #include <linux/reboot.h> | |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_crtc_helper.h> | |
37 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 38 | #include "intel_drv.h" |
760285e7 | 39 | #include <drm/i915_drm.h> |
a4fc5ed6 | 40 | #include "i915_drv.h" |
a4fc5ed6 | 41 | |
a4fc5ed6 KP |
42 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
43 | ||
559be30c TP |
44 | /* Compliance test status bits */ |
45 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 | |
46 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
47 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
48 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
49 | ||
9dd4ffdf | 50 | struct dp_link_dpll { |
840b32b7 | 51 | int clock; |
9dd4ffdf CML |
52 | struct dpll dpll; |
53 | }; | |
54 | ||
55 | static const struct dp_link_dpll gen4_dpll[] = { | |
840b32b7 | 56 | { 162000, |
9dd4ffdf | 57 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
840b32b7 | 58 | { 270000, |
9dd4ffdf CML |
59 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
60 | }; | |
61 | ||
62 | static const struct dp_link_dpll pch_dpll[] = { | |
840b32b7 | 63 | { 162000, |
9dd4ffdf | 64 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
840b32b7 | 65 | { 270000, |
9dd4ffdf CML |
66 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
67 | }; | |
68 | ||
65ce4bf5 | 69 | static const struct dp_link_dpll vlv_dpll[] = { |
840b32b7 | 70 | { 162000, |
58f6e632 | 71 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
840b32b7 | 72 | { 270000, |
65ce4bf5 CML |
73 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
74 | }; | |
75 | ||
ef9348c8 CML |
76 | /* |
77 | * CHV supports eDP 1.4 that have more link rates. | |
78 | * Below only provides the fixed rate but exclude variable rate. | |
79 | */ | |
80 | static const struct dp_link_dpll chv_dpll[] = { | |
81 | /* | |
82 | * CHV requires to program fractional division for m2. | |
83 | * m2 is stored in fixed point format using formula below | |
84 | * (m2_int << 22) | m2_fraction | |
85 | */ | |
840b32b7 | 86 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
ef9348c8 | 87 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
840b32b7 | 88 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 | 89 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
840b32b7 | 90 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 CML |
91 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
92 | }; | |
637a9c63 | 93 | |
64987fc5 SJ |
94 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
95 | 324000, 432000, 540000 }; | |
637a9c63 | 96 | static const int skl_rates[] = { 162000, 216000, 270000, |
f4896f15 VS |
97 | 324000, 432000, 540000 }; |
98 | static const int default_rates[] = { 162000, 270000, 540000 }; | |
ef9348c8 | 99 | |
cfcb0fc9 JB |
100 | /** |
101 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
102 | * @intel_dp: DP struct | |
103 | * | |
104 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
105 | * will return true, and false otherwise. | |
106 | */ | |
107 | static bool is_edp(struct intel_dp *intel_dp) | |
108 | { | |
da63a9f2 PZ |
109 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
110 | ||
111 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
112 | } |
113 | ||
68b4d824 | 114 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 115 | { |
68b4d824 ID |
116 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
117 | ||
118 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
119 | } |
120 | ||
df0e9248 CW |
121 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
122 | { | |
fa90ecef | 123 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
124 | } |
125 | ||
ea5b213a | 126 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
1e0560e0 | 127 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 128 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
093e3f13 | 129 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
a8c3344e VS |
130 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
131 | enum pipe pipe); | |
f21a2198 | 132 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
a4fc5ed6 | 133 | |
ed4e9c1d VS |
134 | static int |
135 | intel_dp_max_link_bw(struct intel_dp *intel_dp) | |
a4fc5ed6 | 136 | { |
7183dc29 | 137 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
138 | |
139 | switch (max_link_bw) { | |
140 | case DP_LINK_BW_1_62: | |
141 | case DP_LINK_BW_2_7: | |
1db10e28 | 142 | case DP_LINK_BW_5_4: |
d4eead50 | 143 | break; |
a4fc5ed6 | 144 | default: |
d4eead50 ID |
145 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
146 | max_link_bw); | |
a4fc5ed6 KP |
147 | max_link_bw = DP_LINK_BW_1_62; |
148 | break; | |
149 | } | |
150 | return max_link_bw; | |
151 | } | |
152 | ||
eeb6324d PZ |
153 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
154 | { | |
155 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
eeb6324d PZ |
156 | u8 source_max, sink_max; |
157 | ||
ccb1a831 | 158 | source_max = intel_dig_port->max_lanes; |
f482984a | 159 | sink_max = intel_dp->max_sink_lane_count; |
eeb6324d PZ |
160 | |
161 | return min(source_max, sink_max); | |
162 | } | |
163 | ||
22a2c8e0 | 164 | int |
c898261c | 165 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 166 | { |
fd81c44e DP |
167 | /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ |
168 | return DIV_ROUND_UP(pixel_clock * bpp, 8); | |
a4fc5ed6 KP |
169 | } |
170 | ||
22a2c8e0 | 171 | int |
fe27d53e DA |
172 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
173 | { | |
fd81c44e DP |
174 | /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the |
175 | * link rate that is generally expressed in Gbps. Since, 8 bits of data | |
176 | * is transmitted every LS_Clk per lane, there is no need to account for | |
177 | * the channel encoding that is done in the PHY layer here. | |
178 | */ | |
179 | ||
180 | return max_link_clock * max_lanes; | |
fe27d53e DA |
181 | } |
182 | ||
70ec0645 MK |
183 | static int |
184 | intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) | |
185 | { | |
186 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
187 | struct intel_encoder *encoder = &intel_dig_port->base; | |
188 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
189 | int max_dotclk = dev_priv->max_dotclk_freq; | |
190 | int ds_max_dotclk; | |
191 | ||
192 | int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
193 | ||
194 | if (type != DP_DS_PORT_TYPE_VGA) | |
195 | return max_dotclk; | |
196 | ||
197 | ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, | |
198 | intel_dp->downstream_ports); | |
199 | ||
200 | if (ds_max_dotclk != 0) | |
201 | max_dotclk = min(max_dotclk, ds_max_dotclk); | |
202 | ||
203 | return max_dotclk; | |
204 | } | |
205 | ||
40dba341 NM |
206 | static int |
207 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) | |
208 | { | |
209 | if (intel_dp->num_sink_rates) { | |
210 | *sink_rates = intel_dp->sink_rates; | |
211 | return intel_dp->num_sink_rates; | |
212 | } | |
213 | ||
214 | *sink_rates = default_rates; | |
215 | ||
f482984a | 216 | return (intel_dp->max_sink_link_bw >> 3) + 1; |
40dba341 NM |
217 | } |
218 | ||
219 | static int | |
220 | intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) | |
221 | { | |
222 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
223 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
224 | int size; | |
225 | ||
cc3f90f0 | 226 | if (IS_GEN9_LP(dev_priv)) { |
40dba341 NM |
227 | *source_rates = bxt_rates; |
228 | size = ARRAY_SIZE(bxt_rates); | |
229 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { | |
230 | *source_rates = skl_rates; | |
231 | size = ARRAY_SIZE(skl_rates); | |
232 | } else { | |
233 | *source_rates = default_rates; | |
234 | size = ARRAY_SIZE(default_rates); | |
235 | } | |
236 | ||
237 | /* This depends on the fact that 5.4 is last value in the array */ | |
238 | if (!intel_dp_source_supports_hbr2(intel_dp)) | |
239 | size--; | |
240 | ||
241 | return size; | |
242 | } | |
243 | ||
244 | static int intersect_rates(const int *source_rates, int source_len, | |
245 | const int *sink_rates, int sink_len, | |
246 | int *common_rates) | |
247 | { | |
248 | int i = 0, j = 0, k = 0; | |
249 | ||
250 | while (i < source_len && j < sink_len) { | |
251 | if (source_rates[i] == sink_rates[j]) { | |
252 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) | |
253 | return k; | |
254 | common_rates[k] = source_rates[i]; | |
255 | ++k; | |
256 | ++i; | |
257 | ++j; | |
258 | } else if (source_rates[i] < sink_rates[j]) { | |
259 | ++i; | |
260 | } else { | |
261 | ++j; | |
262 | } | |
263 | } | |
264 | return k; | |
265 | } | |
266 | ||
267 | static int intel_dp_common_rates(struct intel_dp *intel_dp, | |
268 | int *common_rates) | |
269 | { | |
270 | const int *source_rates, *sink_rates; | |
271 | int source_len, sink_len; | |
272 | ||
273 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); | |
274 | source_len = intel_dp_source_rates(intel_dp, &source_rates); | |
275 | ||
276 | return intersect_rates(source_rates, source_len, | |
277 | sink_rates, sink_len, | |
278 | common_rates); | |
279 | } | |
280 | ||
fdb14d33 MN |
281 | static int intel_dp_link_rate_index(struct intel_dp *intel_dp, |
282 | int *common_rates, int link_rate) | |
283 | { | |
284 | int common_len; | |
285 | int index; | |
286 | ||
287 | common_len = intel_dp_common_rates(intel_dp, common_rates); | |
288 | for (index = 0; index < common_len; index++) { | |
289 | if (link_rate == common_rates[common_len - index - 1]) | |
290 | return common_len - index - 1; | |
291 | } | |
292 | ||
293 | return -1; | |
294 | } | |
295 | ||
296 | int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, | |
297 | int link_rate, uint8_t lane_count) | |
298 | { | |
299 | int common_rates[DP_MAX_SUPPORTED_RATES]; | |
300 | int link_rate_index; | |
301 | ||
302 | link_rate_index = intel_dp_link_rate_index(intel_dp, | |
303 | common_rates, | |
304 | link_rate); | |
305 | if (link_rate_index > 0) { | |
306 | intel_dp->max_sink_link_bw = drm_dp_link_rate_to_bw_code(common_rates[link_rate_index - 1]); | |
307 | intel_dp->max_sink_lane_count = lane_count; | |
308 | } else if (lane_count > 1) { | |
309 | intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp); | |
310 | intel_dp->max_sink_lane_count = lane_count >> 1; | |
311 | } else { | |
312 | DRM_ERROR("Link Training Unsuccessful\n"); | |
313 | return -1; | |
314 | } | |
315 | ||
316 | return 0; | |
317 | } | |
318 | ||
c19de8eb | 319 | static enum drm_mode_status |
a4fc5ed6 KP |
320 | intel_dp_mode_valid(struct drm_connector *connector, |
321 | struct drm_display_mode *mode) | |
322 | { | |
df0e9248 | 323 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
324 | struct intel_connector *intel_connector = to_intel_connector(connector); |
325 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
326 | int target_clock = mode->clock; |
327 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
70ec0645 MK |
328 | int max_dotclk; |
329 | ||
330 | max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); | |
a4fc5ed6 | 331 | |
dd06f90e JN |
332 | if (is_edp(intel_dp) && fixed_mode) { |
333 | if (mode->hdisplay > fixed_mode->hdisplay) | |
7de56f43 ZY |
334 | return MODE_PANEL; |
335 | ||
dd06f90e | 336 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 337 | return MODE_PANEL; |
03afc4a2 DV |
338 | |
339 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
340 | } |
341 | ||
50fec21a | 342 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
eeb6324d | 343 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 DV |
344 | |
345 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
346 | mode_rate = intel_dp_link_required(target_clock, 18); | |
347 | ||
799487f5 | 348 | if (mode_rate > max_rate || target_clock > max_dotclk) |
c4867936 | 349 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
350 | |
351 | if (mode->clock < 10000) | |
352 | return MODE_CLOCK_LOW; | |
353 | ||
0af78a2b DV |
354 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
355 | return MODE_H_ILLEGAL; | |
356 | ||
a4fc5ed6 KP |
357 | return MODE_OK; |
358 | } | |
359 | ||
a4f1289e | 360 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
a4fc5ed6 KP |
361 | { |
362 | int i; | |
363 | uint32_t v = 0; | |
364 | ||
365 | if (src_bytes > 4) | |
366 | src_bytes = 4; | |
367 | for (i = 0; i < src_bytes; i++) | |
368 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
369 | return v; | |
370 | } | |
371 | ||
c2af70e2 | 372 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
a4fc5ed6 KP |
373 | { |
374 | int i; | |
375 | if (dst_bytes > 4) | |
376 | dst_bytes = 4; | |
377 | for (i = 0; i < dst_bytes; i++) | |
378 | dst[i] = src >> ((3-i) * 8); | |
379 | } | |
380 | ||
bf13e81b JN |
381 | static void |
382 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
36b5f425 | 383 | struct intel_dp *intel_dp); |
bf13e81b JN |
384 | static void |
385 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
36b5f425 | 386 | struct intel_dp *intel_dp); |
335f752b ID |
387 | static void |
388 | intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp); | |
bf13e81b | 389 | |
773538e8 VS |
390 | static void pps_lock(struct intel_dp *intel_dp) |
391 | { | |
392 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
393 | struct intel_encoder *encoder = &intel_dig_port->base; | |
394 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 395 | struct drm_i915_private *dev_priv = to_i915(dev); |
773538e8 VS |
396 | enum intel_display_power_domain power_domain; |
397 | ||
398 | /* | |
399 | * See vlv_power_sequencer_reset() why we need | |
400 | * a power domain reference here. | |
401 | */ | |
25f78f58 | 402 | power_domain = intel_display_port_aux_power_domain(encoder); |
773538e8 VS |
403 | intel_display_power_get(dev_priv, power_domain); |
404 | ||
405 | mutex_lock(&dev_priv->pps_mutex); | |
406 | } | |
407 | ||
408 | static void pps_unlock(struct intel_dp *intel_dp) | |
409 | { | |
410 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
411 | struct intel_encoder *encoder = &intel_dig_port->base; | |
412 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 413 | struct drm_i915_private *dev_priv = to_i915(dev); |
773538e8 VS |
414 | enum intel_display_power_domain power_domain; |
415 | ||
416 | mutex_unlock(&dev_priv->pps_mutex); | |
417 | ||
25f78f58 | 418 | power_domain = intel_display_port_aux_power_domain(encoder); |
773538e8 VS |
419 | intel_display_power_put(dev_priv, power_domain); |
420 | } | |
421 | ||
961a0db0 VS |
422 | static void |
423 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) | |
424 | { | |
425 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
30ad9814 | 426 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
961a0db0 | 427 | enum pipe pipe = intel_dp->pps_pipe; |
0047eedc VS |
428 | bool pll_enabled, release_cl_override = false; |
429 | enum dpio_phy phy = DPIO_PHY(pipe); | |
430 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); | |
961a0db0 VS |
431 | uint32_t DP; |
432 | ||
433 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, | |
434 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", | |
435 | pipe_name(pipe), port_name(intel_dig_port->port))) | |
436 | return; | |
437 | ||
438 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", | |
439 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
440 | ||
441 | /* Preserve the BIOS-computed detected bit. This is | |
442 | * supposed to be read-only. | |
443 | */ | |
444 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
445 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
446 | DP |= DP_PORT_WIDTH(1); | |
447 | DP |= DP_LINK_TRAIN_PAT_1; | |
448 | ||
920a14b2 | 449 | if (IS_CHERRYVIEW(dev_priv)) |
961a0db0 VS |
450 | DP |= DP_PIPE_SELECT_CHV(pipe); |
451 | else if (pipe == PIPE_B) | |
452 | DP |= DP_PIPEB_SELECT; | |
453 | ||
d288f65f VS |
454 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
455 | ||
456 | /* | |
457 | * The DPLL for the pipe must be enabled for this to work. | |
458 | * So enable temporarily it if it's not already enabled. | |
459 | */ | |
0047eedc | 460 | if (!pll_enabled) { |
920a14b2 | 461 | release_cl_override = IS_CHERRYVIEW(dev_priv) && |
0047eedc VS |
462 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
463 | ||
30ad9814 | 464 | if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ? |
3f36b937 TU |
465 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
466 | DRM_ERROR("Failed to force on pll for pipe %c!\n", | |
467 | pipe_name(pipe)); | |
468 | return; | |
469 | } | |
0047eedc | 470 | } |
d288f65f | 471 | |
961a0db0 VS |
472 | /* |
473 | * Similar magic as in intel_dp_enable_port(). | |
474 | * We _must_ do this port enable + disable trick | |
475 | * to make this power seqeuencer lock onto the port. | |
476 | * Otherwise even VDD force bit won't work. | |
477 | */ | |
478 | I915_WRITE(intel_dp->output_reg, DP); | |
479 | POSTING_READ(intel_dp->output_reg); | |
480 | ||
481 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); | |
482 | POSTING_READ(intel_dp->output_reg); | |
483 | ||
484 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); | |
485 | POSTING_READ(intel_dp->output_reg); | |
d288f65f | 486 | |
0047eedc | 487 | if (!pll_enabled) { |
30ad9814 | 488 | vlv_force_pll_off(dev_priv, pipe); |
0047eedc VS |
489 | |
490 | if (release_cl_override) | |
491 | chv_phy_powergate_ch(dev_priv, phy, ch, false); | |
492 | } | |
961a0db0 VS |
493 | } |
494 | ||
bf13e81b JN |
495 | static enum pipe |
496 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
497 | { | |
498 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bf13e81b | 499 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 500 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
501 | struct intel_encoder *encoder; |
502 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); | |
a8c3344e | 503 | enum pipe pipe; |
bf13e81b | 504 | |
e39b999a | 505 | lockdep_assert_held(&dev_priv->pps_mutex); |
bf13e81b | 506 | |
a8c3344e VS |
507 | /* We should never land here with regular DP ports */ |
508 | WARN_ON(!is_edp(intel_dp)); | |
509 | ||
a4a5d2f8 VS |
510 | if (intel_dp->pps_pipe != INVALID_PIPE) |
511 | return intel_dp->pps_pipe; | |
512 | ||
513 | /* | |
514 | * We don't have power sequencer currently. | |
515 | * Pick one that's not used by other ports. | |
516 | */ | |
19c8054c | 517 | for_each_intel_encoder(dev, encoder) { |
a4a5d2f8 VS |
518 | struct intel_dp *tmp; |
519 | ||
520 | if (encoder->type != INTEL_OUTPUT_EDP) | |
521 | continue; | |
522 | ||
523 | tmp = enc_to_intel_dp(&encoder->base); | |
524 | ||
525 | if (tmp->pps_pipe != INVALID_PIPE) | |
526 | pipes &= ~(1 << tmp->pps_pipe); | |
527 | } | |
528 | ||
529 | /* | |
530 | * Didn't find one. This should not happen since there | |
531 | * are two power sequencers and up to two eDP ports. | |
532 | */ | |
533 | if (WARN_ON(pipes == 0)) | |
a8c3344e VS |
534 | pipe = PIPE_A; |
535 | else | |
536 | pipe = ffs(pipes) - 1; | |
a4a5d2f8 | 537 | |
a8c3344e VS |
538 | vlv_steal_power_sequencer(dev, pipe); |
539 | intel_dp->pps_pipe = pipe; | |
a4a5d2f8 VS |
540 | |
541 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", | |
542 | pipe_name(intel_dp->pps_pipe), | |
543 | port_name(intel_dig_port->port)); | |
544 | ||
545 | /* init power sequencer on this pipe and port */ | |
36b5f425 VS |
546 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
547 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
a4a5d2f8 | 548 | |
961a0db0 VS |
549 | /* |
550 | * Even vdd force doesn't work until we've made | |
551 | * the power sequencer lock in on the port. | |
552 | */ | |
553 | vlv_power_sequencer_kick(intel_dp); | |
a4a5d2f8 VS |
554 | |
555 | return intel_dp->pps_pipe; | |
556 | } | |
557 | ||
78597996 ID |
558 | static int |
559 | bxt_power_sequencer_idx(struct intel_dp *intel_dp) | |
560 | { | |
561 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
562 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 563 | struct drm_i915_private *dev_priv = to_i915(dev); |
78597996 ID |
564 | |
565 | lockdep_assert_held(&dev_priv->pps_mutex); | |
566 | ||
567 | /* We should never land here with regular DP ports */ | |
568 | WARN_ON(!is_edp(intel_dp)); | |
569 | ||
570 | /* | |
571 | * TODO: BXT has 2 PPS instances. The correct port->PPS instance | |
572 | * mapping needs to be retrieved from VBT, for now just hard-code to | |
573 | * use instance #0 always. | |
574 | */ | |
575 | if (!intel_dp->pps_reset) | |
576 | return 0; | |
577 | ||
578 | intel_dp->pps_reset = false; | |
579 | ||
580 | /* | |
581 | * Only the HW needs to be reprogrammed, the SW state is fixed and | |
582 | * has been setup during connector init. | |
583 | */ | |
584 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
6491ab27 VS |
589 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
590 | enum pipe pipe); | |
591 | ||
592 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, | |
593 | enum pipe pipe) | |
594 | { | |
44cb734c | 595 | return I915_READ(PP_STATUS(pipe)) & PP_ON; |
6491ab27 VS |
596 | } |
597 | ||
598 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, | |
599 | enum pipe pipe) | |
600 | { | |
44cb734c | 601 | return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
6491ab27 VS |
602 | } |
603 | ||
604 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, | |
605 | enum pipe pipe) | |
606 | { | |
607 | return true; | |
608 | } | |
bf13e81b | 609 | |
a4a5d2f8 | 610 | static enum pipe |
6491ab27 VS |
611 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
612 | enum port port, | |
613 | vlv_pipe_check pipe_check) | |
a4a5d2f8 VS |
614 | { |
615 | enum pipe pipe; | |
bf13e81b | 616 | |
bf13e81b | 617 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
44cb734c | 618 | u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & |
bf13e81b | 619 | PANEL_PORT_SELECT_MASK; |
a4a5d2f8 VS |
620 | |
621 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) | |
622 | continue; | |
623 | ||
6491ab27 VS |
624 | if (!pipe_check(dev_priv, pipe)) |
625 | continue; | |
626 | ||
a4a5d2f8 | 627 | return pipe; |
bf13e81b JN |
628 | } |
629 | ||
a4a5d2f8 VS |
630 | return INVALID_PIPE; |
631 | } | |
632 | ||
633 | static void | |
634 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) | |
635 | { | |
636 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
637 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 638 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
639 | enum port port = intel_dig_port->port; |
640 | ||
641 | lockdep_assert_held(&dev_priv->pps_mutex); | |
642 | ||
643 | /* try to find a pipe with this port selected */ | |
6491ab27 VS |
644 | /* first pick one where the panel is on */ |
645 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
646 | vlv_pipe_has_pp_on); | |
647 | /* didn't find one? pick one where vdd is on */ | |
648 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
649 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
650 | vlv_pipe_has_vdd_on); | |
651 | /* didn't find one? pick one with just the correct port */ | |
652 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
653 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
654 | vlv_pipe_any); | |
a4a5d2f8 VS |
655 | |
656 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ | |
657 | if (intel_dp->pps_pipe == INVALID_PIPE) { | |
658 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", | |
659 | port_name(port)); | |
660 | return; | |
bf13e81b JN |
661 | } |
662 | ||
a4a5d2f8 VS |
663 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
664 | port_name(port), pipe_name(intel_dp->pps_pipe)); | |
665 | ||
36b5f425 VS |
666 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
667 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
bf13e81b JN |
668 | } |
669 | ||
78597996 | 670 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) |
773538e8 | 671 | { |
91c8a326 | 672 | struct drm_device *dev = &dev_priv->drm; |
773538e8 VS |
673 | struct intel_encoder *encoder; |
674 | ||
920a14b2 | 675 | if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 676 | !IS_GEN9_LP(dev_priv))) |
773538e8 VS |
677 | return; |
678 | ||
679 | /* | |
680 | * We can't grab pps_mutex here due to deadlock with power_domain | |
681 | * mutex when power_domain functions are called while holding pps_mutex. | |
682 | * That also means that in order to use pps_pipe the code needs to | |
683 | * hold both a power domain reference and pps_mutex, and the power domain | |
684 | * reference get/put must be done while _not_ holding pps_mutex. | |
685 | * pps_{lock,unlock}() do these steps in the correct order, so one | |
686 | * should use them always. | |
687 | */ | |
688 | ||
19c8054c | 689 | for_each_intel_encoder(dev, encoder) { |
773538e8 VS |
690 | struct intel_dp *intel_dp; |
691 | ||
692 | if (encoder->type != INTEL_OUTPUT_EDP) | |
693 | continue; | |
694 | ||
695 | intel_dp = enc_to_intel_dp(&encoder->base); | |
cc3f90f0 | 696 | if (IS_GEN9_LP(dev_priv)) |
78597996 ID |
697 | intel_dp->pps_reset = true; |
698 | else | |
699 | intel_dp->pps_pipe = INVALID_PIPE; | |
773538e8 | 700 | } |
bf13e81b JN |
701 | } |
702 | ||
8e8232d5 ID |
703 | struct pps_registers { |
704 | i915_reg_t pp_ctrl; | |
705 | i915_reg_t pp_stat; | |
706 | i915_reg_t pp_on; | |
707 | i915_reg_t pp_off; | |
708 | i915_reg_t pp_div; | |
709 | }; | |
710 | ||
711 | static void intel_pps_get_registers(struct drm_i915_private *dev_priv, | |
712 | struct intel_dp *intel_dp, | |
713 | struct pps_registers *regs) | |
714 | { | |
44cb734c ID |
715 | int pps_idx = 0; |
716 | ||
8e8232d5 ID |
717 | memset(regs, 0, sizeof(*regs)); |
718 | ||
cc3f90f0 | 719 | if (IS_GEN9_LP(dev_priv)) |
44cb734c ID |
720 | pps_idx = bxt_power_sequencer_idx(intel_dp); |
721 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
722 | pps_idx = vlv_power_sequencer_pipe(intel_dp); | |
8e8232d5 | 723 | |
44cb734c ID |
724 | regs->pp_ctrl = PP_CONTROL(pps_idx); |
725 | regs->pp_stat = PP_STATUS(pps_idx); | |
726 | regs->pp_on = PP_ON_DELAYS(pps_idx); | |
727 | regs->pp_off = PP_OFF_DELAYS(pps_idx); | |
cc3f90f0 | 728 | if (!IS_GEN9_LP(dev_priv)) |
44cb734c | 729 | regs->pp_div = PP_DIVISOR(pps_idx); |
8e8232d5 ID |
730 | } |
731 | ||
f0f59a00 VS |
732 | static i915_reg_t |
733 | _pp_ctrl_reg(struct intel_dp *intel_dp) | |
bf13e81b | 734 | { |
8e8232d5 | 735 | struct pps_registers regs; |
bf13e81b | 736 | |
8e8232d5 ID |
737 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
738 | ®s); | |
739 | ||
740 | return regs.pp_ctrl; | |
bf13e81b JN |
741 | } |
742 | ||
f0f59a00 VS |
743 | static i915_reg_t |
744 | _pp_stat_reg(struct intel_dp *intel_dp) | |
bf13e81b | 745 | { |
8e8232d5 | 746 | struct pps_registers regs; |
bf13e81b | 747 | |
8e8232d5 ID |
748 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
749 | ®s); | |
750 | ||
751 | return regs.pp_stat; | |
bf13e81b JN |
752 | } |
753 | ||
01527b31 CT |
754 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
755 | This function only applicable when panel PM state is not to be tracked */ | |
756 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, | |
757 | void *unused) | |
758 | { | |
759 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), | |
760 | edp_notifier); | |
761 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 762 | struct drm_i915_private *dev_priv = to_i915(dev); |
01527b31 CT |
763 | |
764 | if (!is_edp(intel_dp) || code != SYS_RESTART) | |
765 | return 0; | |
766 | ||
773538e8 | 767 | pps_lock(intel_dp); |
e39b999a | 768 | |
920a14b2 | 769 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e39b999a | 770 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
f0f59a00 | 771 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
649636ef | 772 | u32 pp_div; |
e39b999a | 773 | |
44cb734c ID |
774 | pp_ctrl_reg = PP_CONTROL(pipe); |
775 | pp_div_reg = PP_DIVISOR(pipe); | |
01527b31 CT |
776 | pp_div = I915_READ(pp_div_reg); |
777 | pp_div &= PP_REFERENCE_DIVIDER_MASK; | |
778 | ||
779 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ | |
780 | I915_WRITE(pp_div_reg, pp_div | 0x1F); | |
781 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); | |
782 | msleep(intel_dp->panel_power_cycle_delay); | |
783 | } | |
784 | ||
773538e8 | 785 | pps_unlock(intel_dp); |
e39b999a | 786 | |
01527b31 CT |
787 | return 0; |
788 | } | |
789 | ||
4be73780 | 790 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 791 | { |
30add22d | 792 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 793 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 794 | |
e39b999a VS |
795 | lockdep_assert_held(&dev_priv->pps_mutex); |
796 | ||
920a14b2 | 797 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
798 | intel_dp->pps_pipe == INVALID_PIPE) |
799 | return false; | |
800 | ||
bf13e81b | 801 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
802 | } |
803 | ||
4be73780 | 804 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 805 | { |
30add22d | 806 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 807 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 808 | |
e39b999a VS |
809 | lockdep_assert_held(&dev_priv->pps_mutex); |
810 | ||
920a14b2 | 811 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
812 | intel_dp->pps_pipe == INVALID_PIPE) |
813 | return false; | |
814 | ||
773538e8 | 815 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
ebf33b18 KP |
816 | } |
817 | ||
9b984dae KP |
818 | static void |
819 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
820 | { | |
30add22d | 821 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 822 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 823 | |
9b984dae KP |
824 | if (!is_edp(intel_dp)) |
825 | return; | |
453c5420 | 826 | |
4be73780 | 827 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
828 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
829 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
830 | I915_READ(_pp_stat_reg(intel_dp)), |
831 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
832 | } |
833 | } | |
834 | ||
9ee32fea DV |
835 | static uint32_t |
836 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
837 | { | |
838 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
839 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 840 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 841 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
842 | uint32_t status; |
843 | bool done; | |
844 | ||
ef04f00d | 845 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 846 | if (has_aux_irq) |
b18ac466 | 847 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 848 | msecs_to_jiffies_timeout(10)); |
9ee32fea | 849 | else |
713a6b66 | 850 | done = wait_for(C, 10) == 0; |
9ee32fea DV |
851 | if (!done) |
852 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
853 | has_aux_irq); | |
854 | #undef C | |
855 | ||
856 | return status; | |
857 | } | |
858 | ||
6ffb1be7 | 859 | static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 860 | { |
174edf1f | 861 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
e7dc33f3 | 862 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
9ee32fea | 863 | |
a457f54b VS |
864 | if (index) |
865 | return 0; | |
866 | ||
ec5b01dd DL |
867 | /* |
868 | * The clock divider is based off the hrawclk, and would like to run at | |
a457f54b | 869 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
a4fc5ed6 | 870 | */ |
a457f54b | 871 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
ec5b01dd DL |
872 | } |
873 | ||
874 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
875 | { | |
876 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 877 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd DL |
878 | |
879 | if (index) | |
880 | return 0; | |
881 | ||
a457f54b VS |
882 | /* |
883 | * The clock divider is based off the cdclk or PCH rawclk, and would | |
884 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and | |
885 | * divide by 2000 and use that | |
886 | */ | |
e7dc33f3 | 887 | if (intel_dig_port->port == PORT_A) |
fce18c4c | 888 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
e7dc33f3 VS |
889 | else |
890 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); | |
ec5b01dd DL |
891 | } |
892 | ||
893 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
894 | { | |
895 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 896 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd | 897 | |
a457f54b | 898 | if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { |
2c55c336 | 899 | /* Workaround for non-ULT HSW */ |
bc86625a CW |
900 | switch (index) { |
901 | case 0: return 63; | |
902 | case 1: return 72; | |
903 | default: return 0; | |
904 | } | |
2c55c336 | 905 | } |
a457f54b VS |
906 | |
907 | return ilk_get_aux_clock_divider(intel_dp, index); | |
b84a1cf8 RV |
908 | } |
909 | ||
b6b5e383 DL |
910 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
911 | { | |
912 | /* | |
913 | * SKL doesn't need us to program the AUX clock divider (Hardware will | |
914 | * derive the clock from CDCLK automatically). We still implement the | |
915 | * get_aux_clock_divider vfunc to plug-in into the existing code. | |
916 | */ | |
917 | return index ? 0 : 1; | |
918 | } | |
919 | ||
6ffb1be7 VS |
920 | static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
921 | bool has_aux_irq, | |
922 | int send_bytes, | |
923 | uint32_t aux_clock_divider) | |
5ed12a19 DL |
924 | { |
925 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
8652744b TU |
926 | struct drm_i915_private *dev_priv = |
927 | to_i915(intel_dig_port->base.base.dev); | |
5ed12a19 DL |
928 | uint32_t precharge, timeout; |
929 | ||
8652744b | 930 | if (IS_GEN6(dev_priv)) |
5ed12a19 DL |
931 | precharge = 3; |
932 | else | |
933 | precharge = 5; | |
934 | ||
8652744b | 935 | if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A) |
5ed12a19 DL |
936 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
937 | else | |
938 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
939 | ||
940 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 941 | DP_AUX_CH_CTL_DONE | |
5ed12a19 | 942 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
788d4433 | 943 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 944 | timeout | |
788d4433 | 945 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
946 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
947 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 948 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
949 | } |
950 | ||
b9ca5fad DL |
951 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
952 | bool has_aux_irq, | |
953 | int send_bytes, | |
954 | uint32_t unused) | |
955 | { | |
956 | return DP_AUX_CH_CTL_SEND_BUSY | | |
957 | DP_AUX_CH_CTL_DONE | | |
958 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | | |
959 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
960 | DP_AUX_CH_CTL_TIME_OUT_1600us | | |
961 | DP_AUX_CH_CTL_RECEIVE_ERROR | | |
962 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
d4dcbdce | 963 | DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | |
b9ca5fad DL |
964 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
965 | } | |
966 | ||
b84a1cf8 RV |
967 | static int |
968 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
bd9f74a5 | 969 | const uint8_t *send, int send_bytes, |
b84a1cf8 RV |
970 | uint8_t *recv, int recv_size) |
971 | { | |
972 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
0031fb96 TU |
973 | struct drm_i915_private *dev_priv = |
974 | to_i915(intel_dig_port->base.base.dev); | |
f0f59a00 | 975 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
bc86625a | 976 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
977 | int i, ret, recv_bytes; |
978 | uint32_t status; | |
5ed12a19 | 979 | int try, clock = 0; |
0031fb96 | 980 | bool has_aux_irq = HAS_AUX_IRQ(dev_priv); |
884f19e9 JN |
981 | bool vdd; |
982 | ||
773538e8 | 983 | pps_lock(intel_dp); |
e39b999a | 984 | |
72c3500a VS |
985 | /* |
986 | * We will be called with VDD already enabled for dpcd/edid/oui reads. | |
987 | * In such cases we want to leave VDD enabled and it's up to upper layers | |
988 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off | |
989 | * ourselves. | |
990 | */ | |
1e0560e0 | 991 | vdd = edp_panel_vdd_on(intel_dp); |
b84a1cf8 RV |
992 | |
993 | /* dp aux is extremely sensitive to irq latency, hence request the | |
994 | * lowest possible wakeup latency and so prevent the cpu from going into | |
995 | * deep sleep states. | |
996 | */ | |
997 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
998 | ||
999 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 1000 | |
11bee43e JB |
1001 | /* Try to wait for any previous AUX channel activity */ |
1002 | for (try = 0; try < 3; try++) { | |
ef04f00d | 1003 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
1004 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
1005 | break; | |
1006 | msleep(1); | |
1007 | } | |
1008 | ||
1009 | if (try == 3) { | |
02196c77 MK |
1010 | static u32 last_status = -1; |
1011 | const u32 status = I915_READ(ch_ctl); | |
1012 | ||
1013 | if (status != last_status) { | |
1014 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
1015 | status); | |
1016 | last_status = status; | |
1017 | } | |
1018 | ||
9ee32fea DV |
1019 | ret = -EBUSY; |
1020 | goto out; | |
4f7f7b7e CW |
1021 | } |
1022 | ||
46a5ae9f PZ |
1023 | /* Only 5 data registers! */ |
1024 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
1025 | ret = -E2BIG; | |
1026 | goto out; | |
1027 | } | |
1028 | ||
ec5b01dd | 1029 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
153b1100 DL |
1030 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
1031 | has_aux_irq, | |
1032 | send_bytes, | |
1033 | aux_clock_divider); | |
5ed12a19 | 1034 | |
bc86625a CW |
1035 | /* Must try at least 3 times according to DP spec */ |
1036 | for (try = 0; try < 5; try++) { | |
1037 | /* Load the send data into the aux channel data registers */ | |
1038 | for (i = 0; i < send_bytes; i += 4) | |
330e20ec | 1039 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
a4f1289e RV |
1040 | intel_dp_pack_aux(send + i, |
1041 | send_bytes - i)); | |
bc86625a CW |
1042 | |
1043 | /* Send the command and wait for it to complete */ | |
5ed12a19 | 1044 | I915_WRITE(ch_ctl, send_ctl); |
bc86625a CW |
1045 | |
1046 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
1047 | ||
1048 | /* Clear done status and any errors */ | |
1049 | I915_WRITE(ch_ctl, | |
1050 | status | | |
1051 | DP_AUX_CH_CTL_DONE | | |
1052 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
1053 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
1054 | ||
74ebf294 | 1055 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
bc86625a | 1056 | continue; |
74ebf294 TP |
1057 | |
1058 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 | |
1059 | * 400us delay required for errors and timeouts | |
1060 | * Timeout errors from the HW already meet this | |
1061 | * requirement so skip to next iteration | |
1062 | */ | |
1063 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { | |
1064 | usleep_range(400, 500); | |
bc86625a | 1065 | continue; |
74ebf294 | 1066 | } |
bc86625a | 1067 | if (status & DP_AUX_CH_CTL_DONE) |
e058c945 | 1068 | goto done; |
bc86625a | 1069 | } |
a4fc5ed6 KP |
1070 | } |
1071 | ||
a4fc5ed6 | 1072 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 1073 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
1074 | ret = -EBUSY; |
1075 | goto out; | |
a4fc5ed6 KP |
1076 | } |
1077 | ||
e058c945 | 1078 | done: |
a4fc5ed6 KP |
1079 | /* Check for timeout or receive error. |
1080 | * Timeouts occur when the sink is not connected | |
1081 | */ | |
a5b3da54 | 1082 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 1083 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
1084 | ret = -EIO; |
1085 | goto out; | |
a5b3da54 | 1086 | } |
1ae8c0a5 KP |
1087 | |
1088 | /* Timeouts occur when the device isn't connected, so they're | |
1089 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 1090 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 1091 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
1092 | ret = -ETIMEDOUT; |
1093 | goto out; | |
a4fc5ed6 KP |
1094 | } |
1095 | ||
1096 | /* Unload any bytes sent back from the other side */ | |
1097 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
1098 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
14e01889 RV |
1099 | |
1100 | /* | |
1101 | * By BSpec: "Message sizes of 0 or >20 are not allowed." | |
1102 | * We have no idea of what happened so we return -EBUSY so | |
1103 | * drm layer takes care for the necessary retries. | |
1104 | */ | |
1105 | if (recv_bytes == 0 || recv_bytes > 20) { | |
1106 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", | |
1107 | recv_bytes); | |
1108 | /* | |
1109 | * FIXME: This patch was created on top of a series that | |
1110 | * organize the retries at drm level. There EBUSY should | |
1111 | * also take care for 1ms wait before retrying. | |
1112 | * That aux retries re-org is still needed and after that is | |
1113 | * merged we remove this sleep from here. | |
1114 | */ | |
1115 | usleep_range(1000, 1500); | |
1116 | ret = -EBUSY; | |
1117 | goto out; | |
1118 | } | |
1119 | ||
a4fc5ed6 KP |
1120 | if (recv_bytes > recv_size) |
1121 | recv_bytes = recv_size; | |
0206e353 | 1122 | |
4f7f7b7e | 1123 | for (i = 0; i < recv_bytes; i += 4) |
330e20ec | 1124 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
a4f1289e | 1125 | recv + i, recv_bytes - i); |
a4fc5ed6 | 1126 | |
9ee32fea DV |
1127 | ret = recv_bytes; |
1128 | out: | |
1129 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
1130 | ||
884f19e9 JN |
1131 | if (vdd) |
1132 | edp_panel_vdd_off(intel_dp, false); | |
1133 | ||
773538e8 | 1134 | pps_unlock(intel_dp); |
e39b999a | 1135 | |
9ee32fea | 1136 | return ret; |
a4fc5ed6 KP |
1137 | } |
1138 | ||
a6c8aff0 JN |
1139 | #define BARE_ADDRESS_SIZE 3 |
1140 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
9d1a1031 JN |
1141 | static ssize_t |
1142 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 1143 | { |
9d1a1031 JN |
1144 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
1145 | uint8_t txbuf[20], rxbuf[20]; | |
1146 | size_t txsize, rxsize; | |
a4fc5ed6 | 1147 | int ret; |
a4fc5ed6 | 1148 | |
d2d9cbbd VS |
1149 | txbuf[0] = (msg->request << 4) | |
1150 | ((msg->address >> 16) & 0xf); | |
1151 | txbuf[1] = (msg->address >> 8) & 0xff; | |
9d1a1031 JN |
1152 | txbuf[2] = msg->address & 0xff; |
1153 | txbuf[3] = msg->size - 1; | |
46a5ae9f | 1154 | |
9d1a1031 JN |
1155 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
1156 | case DP_AUX_NATIVE_WRITE: | |
1157 | case DP_AUX_I2C_WRITE: | |
c1e74122 | 1158 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
a6c8aff0 | 1159 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
a1ddefd8 | 1160 | rxsize = 2; /* 0 or 1 data bytes */ |
f51a44b9 | 1161 | |
9d1a1031 JN |
1162 | if (WARN_ON(txsize > 20)) |
1163 | return -E2BIG; | |
a4fc5ed6 | 1164 | |
dd788090 VS |
1165 | WARN_ON(!msg->buffer != !msg->size); |
1166 | ||
d81a67cc ID |
1167 | if (msg->buffer) |
1168 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); | |
a4fc5ed6 | 1169 | |
9d1a1031 JN |
1170 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1171 | if (ret > 0) { | |
1172 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 1173 | |
a1ddefd8 JN |
1174 | if (ret > 1) { |
1175 | /* Number of bytes written in a short write. */ | |
1176 | ret = clamp_t(int, rxbuf[1], 0, msg->size); | |
1177 | } else { | |
1178 | /* Return payload size. */ | |
1179 | ret = msg->size; | |
1180 | } | |
9d1a1031 JN |
1181 | } |
1182 | break; | |
46a5ae9f | 1183 | |
9d1a1031 JN |
1184 | case DP_AUX_NATIVE_READ: |
1185 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 1186 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 1187 | rxsize = msg->size + 1; |
a4fc5ed6 | 1188 | |
9d1a1031 JN |
1189 | if (WARN_ON(rxsize > 20)) |
1190 | return -E2BIG; | |
a4fc5ed6 | 1191 | |
9d1a1031 JN |
1192 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1193 | if (ret > 0) { | |
1194 | msg->reply = rxbuf[0] >> 4; | |
1195 | /* | |
1196 | * Assume happy day, and copy the data. The caller is | |
1197 | * expected to check msg->reply before touching it. | |
1198 | * | |
1199 | * Return payload size. | |
1200 | */ | |
1201 | ret--; | |
1202 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 1203 | } |
9d1a1031 JN |
1204 | break; |
1205 | ||
1206 | default: | |
1207 | ret = -EINVAL; | |
1208 | break; | |
a4fc5ed6 | 1209 | } |
f51a44b9 | 1210 | |
9d1a1031 | 1211 | return ret; |
a4fc5ed6 KP |
1212 | } |
1213 | ||
8f7ce038 VS |
1214 | static enum port intel_aux_port(struct drm_i915_private *dev_priv, |
1215 | enum port port) | |
1216 | { | |
1217 | const struct ddi_vbt_port_info *info = | |
1218 | &dev_priv->vbt.ddi_port_info[port]; | |
1219 | enum port aux_port; | |
1220 | ||
1221 | if (!info->alternate_aux_channel) { | |
1222 | DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n", | |
1223 | port_name(port), port_name(port)); | |
1224 | return port; | |
1225 | } | |
1226 | ||
1227 | switch (info->alternate_aux_channel) { | |
1228 | case DP_AUX_A: | |
1229 | aux_port = PORT_A; | |
1230 | break; | |
1231 | case DP_AUX_B: | |
1232 | aux_port = PORT_B; | |
1233 | break; | |
1234 | case DP_AUX_C: | |
1235 | aux_port = PORT_C; | |
1236 | break; | |
1237 | case DP_AUX_D: | |
1238 | aux_port = PORT_D; | |
1239 | break; | |
1240 | default: | |
1241 | MISSING_CASE(info->alternate_aux_channel); | |
1242 | aux_port = PORT_A; | |
1243 | break; | |
1244 | } | |
1245 | ||
1246 | DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n", | |
1247 | port_name(aux_port), port_name(port)); | |
1248 | ||
1249 | return aux_port; | |
1250 | } | |
1251 | ||
f0f59a00 | 1252 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1253 | enum port port) |
da00bdcf VS |
1254 | { |
1255 | switch (port) { | |
1256 | case PORT_B: | |
1257 | case PORT_C: | |
1258 | case PORT_D: | |
1259 | return DP_AUX_CH_CTL(port); | |
1260 | default: | |
1261 | MISSING_CASE(port); | |
1262 | return DP_AUX_CH_CTL(PORT_B); | |
1263 | } | |
1264 | } | |
1265 | ||
f0f59a00 | 1266 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1267 | enum port port, int index) |
330e20ec VS |
1268 | { |
1269 | switch (port) { | |
1270 | case PORT_B: | |
1271 | case PORT_C: | |
1272 | case PORT_D: | |
1273 | return DP_AUX_CH_DATA(port, index); | |
1274 | default: | |
1275 | MISSING_CASE(port); | |
1276 | return DP_AUX_CH_DATA(PORT_B, index); | |
1277 | } | |
1278 | } | |
1279 | ||
f0f59a00 | 1280 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1281 | enum port port) |
da00bdcf VS |
1282 | { |
1283 | switch (port) { | |
1284 | case PORT_A: | |
1285 | return DP_AUX_CH_CTL(port); | |
1286 | case PORT_B: | |
1287 | case PORT_C: | |
1288 | case PORT_D: | |
1289 | return PCH_DP_AUX_CH_CTL(port); | |
1290 | default: | |
1291 | MISSING_CASE(port); | |
1292 | return DP_AUX_CH_CTL(PORT_A); | |
1293 | } | |
1294 | } | |
1295 | ||
f0f59a00 | 1296 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1297 | enum port port, int index) |
330e20ec VS |
1298 | { |
1299 | switch (port) { | |
1300 | case PORT_A: | |
1301 | return DP_AUX_CH_DATA(port, index); | |
1302 | case PORT_B: | |
1303 | case PORT_C: | |
1304 | case PORT_D: | |
1305 | return PCH_DP_AUX_CH_DATA(port, index); | |
1306 | default: | |
1307 | MISSING_CASE(port); | |
1308 | return DP_AUX_CH_DATA(PORT_A, index); | |
1309 | } | |
1310 | } | |
1311 | ||
f0f59a00 | 1312 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1313 | enum port port) |
da00bdcf | 1314 | { |
da00bdcf VS |
1315 | switch (port) { |
1316 | case PORT_A: | |
1317 | case PORT_B: | |
1318 | case PORT_C: | |
1319 | case PORT_D: | |
1320 | return DP_AUX_CH_CTL(port); | |
1321 | default: | |
1322 | MISSING_CASE(port); | |
1323 | return DP_AUX_CH_CTL(PORT_A); | |
1324 | } | |
1325 | } | |
1326 | ||
f0f59a00 | 1327 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1328 | enum port port, int index) |
330e20ec | 1329 | { |
330e20ec VS |
1330 | switch (port) { |
1331 | case PORT_A: | |
1332 | case PORT_B: | |
1333 | case PORT_C: | |
1334 | case PORT_D: | |
1335 | return DP_AUX_CH_DATA(port, index); | |
1336 | default: | |
1337 | MISSING_CASE(port); | |
1338 | return DP_AUX_CH_DATA(PORT_A, index); | |
1339 | } | |
1340 | } | |
1341 | ||
f0f59a00 | 1342 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1343 | enum port port) |
330e20ec VS |
1344 | { |
1345 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1346 | return skl_aux_ctl_reg(dev_priv, port); | |
1347 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1348 | return ilk_aux_ctl_reg(dev_priv, port); | |
1349 | else | |
1350 | return g4x_aux_ctl_reg(dev_priv, port); | |
1351 | } | |
1352 | ||
f0f59a00 | 1353 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1354 | enum port port, int index) |
330e20ec VS |
1355 | { |
1356 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1357 | return skl_aux_data_reg(dev_priv, port, index); | |
1358 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1359 | return ilk_aux_data_reg(dev_priv, port, index); | |
1360 | else | |
1361 | return g4x_aux_data_reg(dev_priv, port, index); | |
1362 | } | |
1363 | ||
1364 | static void intel_aux_reg_init(struct intel_dp *intel_dp) | |
1365 | { | |
1366 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); | |
8f7ce038 VS |
1367 | enum port port = intel_aux_port(dev_priv, |
1368 | dp_to_dig_port(intel_dp)->port); | |
330e20ec VS |
1369 | int i; |
1370 | ||
1371 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); | |
1372 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) | |
1373 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); | |
1374 | } | |
1375 | ||
9d1a1031 | 1376 | static void |
a121f4e5 VS |
1377 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
1378 | { | |
a121f4e5 VS |
1379 | kfree(intel_dp->aux.name); |
1380 | } | |
1381 | ||
7a418e34 | 1382 | static void |
b6339585 | 1383 | intel_dp_aux_init(struct intel_dp *intel_dp) |
9d1a1031 | 1384 | { |
33ad6626 JN |
1385 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1386 | enum port port = intel_dig_port->port; | |
ab2c0672 | 1387 | |
330e20ec | 1388 | intel_aux_reg_init(intel_dp); |
7a418e34 | 1389 | drm_dp_aux_init(&intel_dp->aux); |
8316f337 | 1390 | |
7a418e34 | 1391 | /* Failure to allocate our preferred name is not critical */ |
a121f4e5 | 1392 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
9d1a1031 | 1393 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
a4fc5ed6 KP |
1394 | } |
1395 | ||
e588fa18 | 1396 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
ed63baaf | 1397 | { |
e588fa18 | 1398 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
577c5430 | 1399 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
e588fa18 | 1400 | |
577c5430 NM |
1401 | if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || |
1402 | IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9)) | |
ed63baaf TS |
1403 | return true; |
1404 | else | |
1405 | return false; | |
1406 | } | |
1407 | ||
c6bb3538 DV |
1408 | static void |
1409 | intel_dp_set_clock(struct intel_encoder *encoder, | |
840b32b7 | 1410 | struct intel_crtc_state *pipe_config) |
c6bb3538 DV |
1411 | { |
1412 | struct drm_device *dev = encoder->base.dev; | |
6e266956 | 1413 | struct drm_i915_private *dev_priv = to_i915(dev); |
9dd4ffdf CML |
1414 | const struct dp_link_dpll *divisor = NULL; |
1415 | int i, count = 0; | |
c6bb3538 | 1416 | |
9beb5fea | 1417 | if (IS_G4X(dev_priv)) { |
9dd4ffdf CML |
1418 | divisor = gen4_dpll; |
1419 | count = ARRAY_SIZE(gen4_dpll); | |
6e266956 | 1420 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
9dd4ffdf CML |
1421 | divisor = pch_dpll; |
1422 | count = ARRAY_SIZE(pch_dpll); | |
920a14b2 | 1423 | } else if (IS_CHERRYVIEW(dev_priv)) { |
ef9348c8 CML |
1424 | divisor = chv_dpll; |
1425 | count = ARRAY_SIZE(chv_dpll); | |
11a914c2 | 1426 | } else if (IS_VALLEYVIEW(dev_priv)) { |
65ce4bf5 CML |
1427 | divisor = vlv_dpll; |
1428 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 1429 | } |
9dd4ffdf CML |
1430 | |
1431 | if (divisor && count) { | |
1432 | for (i = 0; i < count; i++) { | |
840b32b7 | 1433 | if (pipe_config->port_clock == divisor[i].clock) { |
9dd4ffdf CML |
1434 | pipe_config->dpll = divisor[i].dpll; |
1435 | pipe_config->clock_set = true; | |
1436 | break; | |
1437 | } | |
1438 | } | |
c6bb3538 DV |
1439 | } |
1440 | } | |
1441 | ||
0336400e VS |
1442 | static void snprintf_int_array(char *str, size_t len, |
1443 | const int *array, int nelem) | |
1444 | { | |
1445 | int i; | |
1446 | ||
1447 | str[0] = '\0'; | |
1448 | ||
1449 | for (i = 0; i < nelem; i++) { | |
b2f505be | 1450 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
0336400e VS |
1451 | if (r >= len) |
1452 | return; | |
1453 | str += r; | |
1454 | len -= r; | |
1455 | } | |
1456 | } | |
1457 | ||
1458 | static void intel_dp_print_rates(struct intel_dp *intel_dp) | |
1459 | { | |
0336400e | 1460 | const int *source_rates, *sink_rates; |
94ca719e VS |
1461 | int source_len, sink_len, common_len; |
1462 | int common_rates[DP_MAX_SUPPORTED_RATES]; | |
0336400e VS |
1463 | char str[128]; /* FIXME: too big for stack? */ |
1464 | ||
1465 | if ((drm_debug & DRM_UT_KMS) == 0) | |
1466 | return; | |
1467 | ||
e588fa18 | 1468 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
0336400e VS |
1469 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
1470 | DRM_DEBUG_KMS("source rates: %s\n", str); | |
1471 | ||
1472 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); | |
1473 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); | |
1474 | DRM_DEBUG_KMS("sink rates: %s\n", str); | |
1475 | ||
94ca719e VS |
1476 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1477 | snprintf_int_array(str, sizeof(str), common_rates, common_len); | |
1478 | DRM_DEBUG_KMS("common rates: %s\n", str); | |
0336400e VS |
1479 | } |
1480 | ||
489375c8 | 1481 | bool |
7b3fc170 | 1482 | __intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc) |
0e390a33 | 1483 | { |
7b3fc170 ID |
1484 | u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI : |
1485 | DP_SINK_OUI; | |
0e390a33 | 1486 | |
7b3fc170 ID |
1487 | return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) == |
1488 | sizeof(*desc); | |
0e390a33 MK |
1489 | } |
1490 | ||
12a47a42 | 1491 | bool intel_dp_read_desc(struct intel_dp *intel_dp) |
1a2724fa | 1492 | { |
7b3fc170 ID |
1493 | struct intel_dp_desc *desc = &intel_dp->desc; |
1494 | bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & | |
1495 | DP_OUI_SUPPORT; | |
1496 | int dev_id_len; | |
1a2724fa | 1497 | |
7b3fc170 ID |
1498 | if (!__intel_dp_read_desc(intel_dp, desc)) |
1499 | return false; | |
1a2724fa | 1500 | |
7b3fc170 ID |
1501 | dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id)); |
1502 | DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n", | |
1503 | drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink", | |
1504 | (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)", | |
1505 | dev_id_len, desc->device_id, | |
1506 | desc->hw_rev >> 4, desc->hw_rev & 0xf, | |
1507 | desc->sw_major_rev, desc->sw_minor_rev); | |
1a2724fa | 1508 | |
7b3fc170 | 1509 | return true; |
1a2724fa MK |
1510 | } |
1511 | ||
f4896f15 | 1512 | static int rate_to_index(int find, const int *rates) |
a8f3ef61 SJ |
1513 | { |
1514 | int i = 0; | |
1515 | ||
1516 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) | |
1517 | if (find == rates[i]) | |
1518 | break; | |
1519 | ||
1520 | return i; | |
1521 | } | |
1522 | ||
50fec21a VS |
1523 | int |
1524 | intel_dp_max_link_rate(struct intel_dp *intel_dp) | |
1525 | { | |
1526 | int rates[DP_MAX_SUPPORTED_RATES] = {}; | |
1527 | int len; | |
1528 | ||
94ca719e | 1529 | len = intel_dp_common_rates(intel_dp, rates); |
50fec21a VS |
1530 | if (WARN_ON(len <= 0)) |
1531 | return 162000; | |
1532 | ||
1354f734 | 1533 | return rates[len - 1]; |
50fec21a VS |
1534 | } |
1535 | ||
ed4e9c1d VS |
1536 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1537 | { | |
94ca719e | 1538 | return rate_to_index(rate, intel_dp->sink_rates); |
ed4e9c1d VS |
1539 | } |
1540 | ||
94223d04 ACO |
1541 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1542 | uint8_t *link_bw, uint8_t *rate_select) | |
04a60f9f VS |
1543 | { |
1544 | if (intel_dp->num_sink_rates) { | |
1545 | *link_bw = 0; | |
1546 | *rate_select = | |
1547 | intel_dp_rate_select(intel_dp, port_clock); | |
1548 | } else { | |
1549 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); | |
1550 | *rate_select = 0; | |
1551 | } | |
1552 | } | |
1553 | ||
f580bea9 JN |
1554 | static int intel_dp_compute_bpp(struct intel_dp *intel_dp, |
1555 | struct intel_crtc_state *pipe_config) | |
f9bb705e MK |
1556 | { |
1557 | int bpp, bpc; | |
1558 | ||
1559 | bpp = pipe_config->pipe_bpp; | |
1560 | bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports); | |
1561 | ||
1562 | if (bpc > 0) | |
1563 | bpp = min(bpp, 3*bpc); | |
1564 | ||
1565 | return bpp; | |
1566 | } | |
1567 | ||
00c09d70 | 1568 | bool |
5bfe2ac0 | 1569 | intel_dp_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
1570 | struct intel_crtc_state *pipe_config, |
1571 | struct drm_connector_state *conn_state) | |
a4fc5ed6 | 1572 | { |
dd11bc10 | 1573 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2d112de7 | 1574 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
5bfe2ac0 | 1575 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1576 | enum port port = dp_to_dig_port(intel_dp)->port; |
84556d58 | 1577 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
dd06f90e | 1578 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
a4fc5ed6 | 1579 | int lane_count, clock; |
56071a20 | 1580 | int min_lane_count = 1; |
eeb6324d | 1581 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
06ea66b6 | 1582 | /* Conveniently, the link BW constants become indices with a shift...*/ |
56071a20 | 1583 | int min_clock = 0; |
a8f3ef61 | 1584 | int max_clock; |
083f9560 | 1585 | int bpp, mode_rate; |
ff9a6750 | 1586 | int link_avail, link_clock; |
94ca719e VS |
1587 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
1588 | int common_len; | |
04a60f9f | 1589 | uint8_t link_bw, rate_select; |
a8f3ef61 | 1590 | |
94ca719e | 1591 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
a8f3ef61 SJ |
1592 | |
1593 | /* No common link rates between source and sink */ | |
94ca719e | 1594 | WARN_ON(common_len <= 0); |
a8f3ef61 | 1595 | |
94ca719e | 1596 | max_clock = common_len - 1; |
a4fc5ed6 | 1597 | |
4f8036a2 | 1598 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) |
5bfe2ac0 DV |
1599 | pipe_config->has_pch_encoder = true; |
1600 | ||
f769cd24 | 1601 | pipe_config->has_drrs = false; |
9fcb1704 | 1602 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
a4fc5ed6 | 1603 | |
dd06f90e JN |
1604 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
1605 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
1606 | adjusted_mode); | |
a1b2278e | 1607 | |
dd11bc10 | 1608 | if (INTEL_GEN(dev_priv) >= 9) { |
a1b2278e | 1609 | int ret; |
e435d6e5 | 1610 | ret = skl_update_scaler_crtc(pipe_config); |
a1b2278e CK |
1611 | if (ret) |
1612 | return ret; | |
1613 | } | |
1614 | ||
49cff963 | 1615 | if (HAS_GMCH_DISPLAY(dev_priv)) |
2dd24552 JB |
1616 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
1617 | intel_connector->panel.fitting_mode); | |
1618 | else | |
b074cec8 JB |
1619 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
1620 | intel_connector->panel.fitting_mode); | |
0d3a1bee ZY |
1621 | } |
1622 | ||
cb1793ce | 1623 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
1624 | return false; |
1625 | ||
083f9560 | 1626 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
a8f3ef61 | 1627 | "max bw %d pixel clock %iKHz\n", |
94ca719e | 1628 | max_lane_count, common_rates[max_clock], |
241bfc38 | 1629 | adjusted_mode->crtc_clock); |
083f9560 | 1630 | |
36008365 DV |
1631 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1632 | * bpc in between. */ | |
f9bb705e | 1633 | bpp = intel_dp_compute_bpp(intel_dp, pipe_config); |
56071a20 | 1634 | if (is_edp(intel_dp)) { |
22ce5628 TS |
1635 | |
1636 | /* Get bpp from vbt only for panels that dont have bpp in edid */ | |
1637 | if (intel_connector->base.display_info.bpc == 0 && | |
6aa23e65 | 1638 | (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { |
56071a20 | 1639 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
6aa23e65 JN |
1640 | dev_priv->vbt.edp.bpp); |
1641 | bpp = dev_priv->vbt.edp.bpp; | |
56071a20 JN |
1642 | } |
1643 | ||
344c5bbc JN |
1644 | /* |
1645 | * Use the maximum clock and number of lanes the eDP panel | |
1646 | * advertizes being capable of. The panels are generally | |
1647 | * designed to support only a single clock and lane | |
1648 | * configuration, and typically these values correspond to the | |
1649 | * native resolution of the panel. | |
1650 | */ | |
1651 | min_lane_count = max_lane_count; | |
1652 | min_clock = max_clock; | |
7984211e | 1653 | } |
657445fe | 1654 | |
36008365 | 1655 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
1656 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1657 | bpp); | |
36008365 | 1658 | |
c6930992 | 1659 | for (clock = min_clock; clock <= max_clock; clock++) { |
a8f3ef61 SJ |
1660 | for (lane_count = min_lane_count; |
1661 | lane_count <= max_lane_count; | |
1662 | lane_count <<= 1) { | |
1663 | ||
94ca719e | 1664 | link_clock = common_rates[clock]; |
36008365 DV |
1665 | link_avail = intel_dp_max_data_rate(link_clock, |
1666 | lane_count); | |
1667 | ||
1668 | if (mode_rate <= link_avail) { | |
1669 | goto found; | |
1670 | } | |
1671 | } | |
1672 | } | |
1673 | } | |
c4867936 | 1674 | |
36008365 | 1675 | return false; |
3685a8f3 | 1676 | |
36008365 | 1677 | found: |
55bc60db VS |
1678 | if (intel_dp->color_range_auto) { |
1679 | /* | |
1680 | * See: | |
1681 | * CEA-861-E - 5.1 Default Encoding Parameters | |
1682 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
1683 | */ | |
0f2a2a75 VS |
1684 | pipe_config->limited_color_range = |
1685 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; | |
1686 | } else { | |
1687 | pipe_config->limited_color_range = | |
1688 | intel_dp->limited_color_range; | |
55bc60db VS |
1689 | } |
1690 | ||
90a6b7b0 | 1691 | pipe_config->lane_count = lane_count; |
a8f3ef61 | 1692 | |
657445fe | 1693 | pipe_config->pipe_bpp = bpp; |
94ca719e | 1694 | pipe_config->port_clock = common_rates[clock]; |
a4fc5ed6 | 1695 | |
04a60f9f VS |
1696 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
1697 | &link_bw, &rate_select); | |
1698 | ||
1699 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", | |
1700 | link_bw, rate_select, pipe_config->lane_count, | |
ff9a6750 | 1701 | pipe_config->port_clock, bpp); |
36008365 DV |
1702 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1703 | mode_rate, link_avail); | |
a4fc5ed6 | 1704 | |
03afc4a2 | 1705 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
1706 | adjusted_mode->crtc_clock, |
1707 | pipe_config->port_clock, | |
03afc4a2 | 1708 | &pipe_config->dp_m_n); |
9d1a455b | 1709 | |
439d7ac0 | 1710 | if (intel_connector->panel.downclock_mode != NULL && |
96178eeb | 1711 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
f769cd24 | 1712 | pipe_config->has_drrs = true; |
439d7ac0 PB |
1713 | intel_link_compute_m_n(bpp, lane_count, |
1714 | intel_connector->panel.downclock_mode->clock, | |
1715 | pipe_config->port_clock, | |
1716 | &pipe_config->dp_m2_n2); | |
1717 | } | |
1718 | ||
14d41b3b VS |
1719 | /* |
1720 | * DPLL0 VCO may need to be adjusted to get the correct | |
1721 | * clock for eDP. This will affect cdclk as well. | |
1722 | */ | |
1723 | if (is_edp(intel_dp) && | |
1724 | (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) { | |
1725 | int vco; | |
1726 | ||
1727 | switch (pipe_config->port_clock / 2) { | |
1728 | case 108000: | |
1729 | case 216000: | |
63911d72 | 1730 | vco = 8640000; |
14d41b3b VS |
1731 | break; |
1732 | default: | |
63911d72 | 1733 | vco = 8100000; |
14d41b3b VS |
1734 | break; |
1735 | } | |
1736 | ||
1737 | to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco; | |
1738 | } | |
1739 | ||
4f8036a2 | 1740 | if (!HAS_DDI(dev_priv)) |
840b32b7 | 1741 | intel_dp_set_clock(encoder, pipe_config); |
c6bb3538 | 1742 | |
03afc4a2 | 1743 | return true; |
a4fc5ed6 KP |
1744 | } |
1745 | ||
901c2daf | 1746 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
dfa10480 ACO |
1747 | int link_rate, uint8_t lane_count, |
1748 | bool link_mst) | |
901c2daf | 1749 | { |
dfa10480 ACO |
1750 | intel_dp->link_rate = link_rate; |
1751 | intel_dp->lane_count = lane_count; | |
1752 | intel_dp->link_mst = link_mst; | |
901c2daf VS |
1753 | } |
1754 | ||
85cb48a1 ML |
1755 | static void intel_dp_prepare(struct intel_encoder *encoder, |
1756 | struct intel_crtc_state *pipe_config) | |
a4fc5ed6 | 1757 | { |
b934223d | 1758 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1759 | struct drm_i915_private *dev_priv = to_i915(dev); |
b934223d | 1760 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1761 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d | 1762 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
85cb48a1 | 1763 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
a4fc5ed6 | 1764 | |
dfa10480 ACO |
1765 | intel_dp_set_link_params(intel_dp, pipe_config->port_clock, |
1766 | pipe_config->lane_count, | |
1767 | intel_crtc_has_type(pipe_config, | |
1768 | INTEL_OUTPUT_DP_MST)); | |
901c2daf | 1769 | |
417e822d | 1770 | /* |
1a2eb460 | 1771 | * There are four kinds of DP registers: |
417e822d KP |
1772 | * |
1773 | * IBX PCH | |
1a2eb460 KP |
1774 | * SNB CPU |
1775 | * IVB CPU | |
417e822d KP |
1776 | * CPT PCH |
1777 | * | |
1778 | * IBX PCH and CPU are the same for almost everything, | |
1779 | * except that the CPU DP PLL is configured in this | |
1780 | * register | |
1781 | * | |
1782 | * CPT PCH is quite different, having many bits moved | |
1783 | * to the TRANS_DP_CTL register instead. That | |
1784 | * configuration happens (oddly) in ironlake_pch_enable | |
1785 | */ | |
9c9e7927 | 1786 | |
417e822d KP |
1787 | /* Preserve the BIOS-computed detected bit. This is |
1788 | * supposed to be read-only. | |
1789 | */ | |
1790 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 1791 | |
417e822d | 1792 | /* Handle DP bits in common between all three register formats */ |
417e822d | 1793 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
85cb48a1 | 1794 | intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); |
a4fc5ed6 | 1795 | |
417e822d | 1796 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 1797 | |
5db94019 | 1798 | if (IS_GEN7(dev_priv) && port == PORT_A) { |
1a2eb460 KP |
1799 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1800 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1801 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1802 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1803 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
1804 | ||
6aba5b6c | 1805 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
1806 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1807 | ||
7c62a164 | 1808 | intel_dp->DP |= crtc->pipe << 29; |
6e266956 | 1809 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
e3ef4479 VS |
1810 | u32 trans_dp; |
1811 | ||
39e5fa88 | 1812 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3ef4479 VS |
1813 | |
1814 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
1815 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
1816 | trans_dp |= TRANS_DP_ENH_FRAMING; | |
1817 | else | |
1818 | trans_dp &= ~TRANS_DP_ENH_FRAMING; | |
1819 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); | |
39e5fa88 | 1820 | } else { |
c99f53f7 | 1821 | if (IS_G4X(dev_priv) && pipe_config->limited_color_range) |
0f2a2a75 | 1822 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
417e822d KP |
1823 | |
1824 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
1825 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1826 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1827 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1828 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
1829 | ||
6aba5b6c | 1830 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
1831 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1832 | ||
920a14b2 | 1833 | if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 1834 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
39e5fa88 VS |
1835 | else if (crtc->pipe == PIPE_B) |
1836 | intel_dp->DP |= DP_PIPEB_SELECT; | |
32f9d658 | 1837 | } |
a4fc5ed6 KP |
1838 | } |
1839 | ||
ffd6749d PZ |
1840 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1841 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 1842 | |
1a5ef5b7 PZ |
1843 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1844 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 1845 | |
ffd6749d PZ |
1846 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1847 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 1848 | |
de9c1b6b ID |
1849 | static void intel_pps_verify_state(struct drm_i915_private *dev_priv, |
1850 | struct intel_dp *intel_dp); | |
1851 | ||
4be73780 | 1852 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
1853 | u32 mask, |
1854 | u32 value) | |
bd943159 | 1855 | { |
30add22d | 1856 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 1857 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1858 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
453c5420 | 1859 | |
e39b999a VS |
1860 | lockdep_assert_held(&dev_priv->pps_mutex); |
1861 | ||
de9c1b6b ID |
1862 | intel_pps_verify_state(dev_priv, intel_dp); |
1863 | ||
bf13e81b JN |
1864 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1865 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 1866 | |
99ea7127 | 1867 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
1868 | mask, value, |
1869 | I915_READ(pp_stat_reg), | |
1870 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1871 | |
9036ff06 CW |
1872 | if (intel_wait_for_register(dev_priv, |
1873 | pp_stat_reg, mask, value, | |
1874 | 5000)) | |
99ea7127 | 1875 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
1876 | I915_READ(pp_stat_reg), |
1877 | I915_READ(pp_ctrl_reg)); | |
54c136d4 CW |
1878 | |
1879 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 1880 | } |
32ce697c | 1881 | |
4be73780 | 1882 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
1883 | { |
1884 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 1885 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
1886 | } |
1887 | ||
4be73780 | 1888 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
1889 | { |
1890 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 1891 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
1892 | } |
1893 | ||
4be73780 | 1894 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 | 1895 | { |
d28d4731 AK |
1896 | ktime_t panel_power_on_time; |
1897 | s64 panel_power_off_duration; | |
1898 | ||
99ea7127 | 1899 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
dce56b3c | 1900 | |
d28d4731 AK |
1901 | /* take the difference of currrent time and panel power off time |
1902 | * and then make panel wait for t11_t12 if needed. */ | |
1903 | panel_power_on_time = ktime_get_boottime(); | |
1904 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); | |
1905 | ||
dce56b3c PZ |
1906 | /* When we disable the VDD override bit last we have to do the manual |
1907 | * wait. */ | |
d28d4731 AK |
1908 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
1909 | wait_remaining_ms_from_jiffies(jiffies, | |
1910 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); | |
dce56b3c | 1911 | |
4be73780 | 1912 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
1913 | } |
1914 | ||
4be73780 | 1915 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
1916 | { |
1917 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
1918 | intel_dp->backlight_on_delay); | |
1919 | } | |
1920 | ||
4be73780 | 1921 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
1922 | { |
1923 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
1924 | intel_dp->backlight_off_delay); | |
1925 | } | |
99ea7127 | 1926 | |
832dd3c1 KP |
1927 | /* Read the current pp_control value, unlocking the register if it |
1928 | * is locked | |
1929 | */ | |
1930 | ||
453c5420 | 1931 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 1932 | { |
453c5420 | 1933 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 1934 | struct drm_i915_private *dev_priv = to_i915(dev); |
453c5420 | 1935 | u32 control; |
832dd3c1 | 1936 | |
e39b999a VS |
1937 | lockdep_assert_held(&dev_priv->pps_mutex); |
1938 | ||
bf13e81b | 1939 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
8090ba8c ID |
1940 | if (WARN_ON(!HAS_DDI(dev_priv) && |
1941 | (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { | |
b0a08bec VK |
1942 | control &= ~PANEL_UNLOCK_MASK; |
1943 | control |= PANEL_UNLOCK_REGS; | |
1944 | } | |
832dd3c1 | 1945 | return control; |
bd943159 KP |
1946 | } |
1947 | ||
951468f3 VS |
1948 | /* |
1949 | * Must be paired with edp_panel_vdd_off(). | |
1950 | * Must hold pps_mutex around the whole on/off sequence. | |
1951 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
1952 | */ | |
1e0560e0 | 1953 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 1954 | { |
30add22d | 1955 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4e6e1a54 ID |
1956 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1957 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fac5e23e | 1958 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e6e1a54 | 1959 | enum intel_display_power_domain power_domain; |
5d613501 | 1960 | u32 pp; |
f0f59a00 | 1961 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 1962 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 1963 | |
e39b999a VS |
1964 | lockdep_assert_held(&dev_priv->pps_mutex); |
1965 | ||
97af61f5 | 1966 | if (!is_edp(intel_dp)) |
adddaaf4 | 1967 | return false; |
bd943159 | 1968 | |
2c623c11 | 1969 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
bd943159 | 1970 | intel_dp->want_panel_vdd = true; |
99ea7127 | 1971 | |
4be73780 | 1972 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 1973 | return need_to_disable; |
b0665d57 | 1974 | |
25f78f58 | 1975 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4e6e1a54 | 1976 | intel_display_power_get(dev_priv, power_domain); |
e9cb81a2 | 1977 | |
3936fcf4 VS |
1978 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
1979 | port_name(intel_dig_port->port)); | |
bd943159 | 1980 | |
4be73780 DV |
1981 | if (!edp_have_panel_power(intel_dp)) |
1982 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 1983 | |
453c5420 | 1984 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 1985 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 1986 | |
bf13e81b JN |
1987 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1988 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
1989 | |
1990 | I915_WRITE(pp_ctrl_reg, pp); | |
1991 | POSTING_READ(pp_ctrl_reg); | |
1992 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1993 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
1994 | /* |
1995 | * If the panel wasn't on, delay before accessing aux channel | |
1996 | */ | |
4be73780 | 1997 | if (!edp_have_panel_power(intel_dp)) { |
3936fcf4 VS |
1998 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
1999 | port_name(intel_dig_port->port)); | |
f01eca2e | 2000 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 2001 | } |
adddaaf4 JN |
2002 | |
2003 | return need_to_disable; | |
2004 | } | |
2005 | ||
951468f3 VS |
2006 | /* |
2007 | * Must be paired with intel_edp_panel_vdd_off() or | |
2008 | * intel_edp_panel_off(). | |
2009 | * Nested calls to these functions are not allowed since | |
2010 | * we drop the lock. Caller must use some higher level | |
2011 | * locking to prevent nested calls from other threads. | |
2012 | */ | |
b80d6c78 | 2013 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 | 2014 | { |
c695b6b6 | 2015 | bool vdd; |
adddaaf4 | 2016 | |
c695b6b6 VS |
2017 | if (!is_edp(intel_dp)) |
2018 | return; | |
2019 | ||
773538e8 | 2020 | pps_lock(intel_dp); |
c695b6b6 | 2021 | vdd = edp_panel_vdd_on(intel_dp); |
773538e8 | 2022 | pps_unlock(intel_dp); |
c695b6b6 | 2023 | |
e2c719b7 | 2024 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
3936fcf4 | 2025 | port_name(dp_to_dig_port(intel_dp)->port)); |
5d613501 JB |
2026 | } |
2027 | ||
4be73780 | 2028 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 2029 | { |
30add22d | 2030 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2031 | struct drm_i915_private *dev_priv = to_i915(dev); |
be2c9196 VS |
2032 | struct intel_digital_port *intel_dig_port = |
2033 | dp_to_dig_port(intel_dp); | |
2034 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
2035 | enum intel_display_power_domain power_domain; | |
5d613501 | 2036 | u32 pp; |
f0f59a00 | 2037 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
5d613501 | 2038 | |
e39b999a | 2039 | lockdep_assert_held(&dev_priv->pps_mutex); |
a0e99e68 | 2040 | |
15e899a0 | 2041 | WARN_ON(intel_dp->want_panel_vdd); |
4e6e1a54 | 2042 | |
15e899a0 | 2043 | if (!edp_have_panel_vdd(intel_dp)) |
be2c9196 | 2044 | return; |
b0665d57 | 2045 | |
3936fcf4 VS |
2046 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
2047 | port_name(intel_dig_port->port)); | |
bd943159 | 2048 | |
be2c9196 VS |
2049 | pp = ironlake_get_pp_control(intel_dp); |
2050 | pp &= ~EDP_FORCE_VDD; | |
453c5420 | 2051 | |
be2c9196 VS |
2052 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2053 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
99ea7127 | 2054 | |
be2c9196 VS |
2055 | I915_WRITE(pp_ctrl_reg, pp); |
2056 | POSTING_READ(pp_ctrl_reg); | |
90791a5c | 2057 | |
be2c9196 VS |
2058 | /* Make sure sequencer is idle before allowing subsequent activity */ |
2059 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
2060 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
e9cb81a2 | 2061 | |
5a162e22 | 2062 | if ((pp & PANEL_POWER_ON) == 0) |
d28d4731 | 2063 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
e9cb81a2 | 2064 | |
25f78f58 | 2065 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
be2c9196 | 2066 | intel_display_power_put(dev_priv, power_domain); |
bd943159 | 2067 | } |
5d613501 | 2068 | |
4be73780 | 2069 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
2070 | { |
2071 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
2072 | struct intel_dp, panel_vdd_work); | |
bd943159 | 2073 | |
773538e8 | 2074 | pps_lock(intel_dp); |
15e899a0 VS |
2075 | if (!intel_dp->want_panel_vdd) |
2076 | edp_panel_vdd_off_sync(intel_dp); | |
773538e8 | 2077 | pps_unlock(intel_dp); |
bd943159 KP |
2078 | } |
2079 | ||
aba86890 ID |
2080 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
2081 | { | |
2082 | unsigned long delay; | |
2083 | ||
2084 | /* | |
2085 | * Queue the timer to fire a long time from now (relative to the power | |
2086 | * down delay) to keep the panel power up across a sequence of | |
2087 | * operations. | |
2088 | */ | |
2089 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); | |
2090 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); | |
2091 | } | |
2092 | ||
951468f3 VS |
2093 | /* |
2094 | * Must be paired with edp_panel_vdd_on(). | |
2095 | * Must hold pps_mutex around the whole on/off sequence. | |
2096 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2097 | */ | |
4be73780 | 2098 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 2099 | { |
fac5e23e | 2100 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
e39b999a VS |
2101 | |
2102 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2103 | ||
97af61f5 KP |
2104 | if (!is_edp(intel_dp)) |
2105 | return; | |
5d613501 | 2106 | |
e2c719b7 | 2107 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
3936fcf4 | 2108 | port_name(dp_to_dig_port(intel_dp)->port)); |
f2e8b18a | 2109 | |
bd943159 KP |
2110 | intel_dp->want_panel_vdd = false; |
2111 | ||
aba86890 | 2112 | if (sync) |
4be73780 | 2113 | edp_panel_vdd_off_sync(intel_dp); |
aba86890 ID |
2114 | else |
2115 | edp_panel_vdd_schedule_off(intel_dp); | |
5d613501 JB |
2116 | } |
2117 | ||
9f0fb5be | 2118 | static void edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 2119 | { |
30add22d | 2120 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2121 | struct drm_i915_private *dev_priv = to_i915(dev); |
99ea7127 | 2122 | u32 pp; |
f0f59a00 | 2123 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2124 | |
9f0fb5be VS |
2125 | lockdep_assert_held(&dev_priv->pps_mutex); |
2126 | ||
97af61f5 | 2127 | if (!is_edp(intel_dp)) |
bd943159 | 2128 | return; |
99ea7127 | 2129 | |
3936fcf4 VS |
2130 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
2131 | port_name(dp_to_dig_port(intel_dp)->port)); | |
e39b999a | 2132 | |
e7a89ace VS |
2133 | if (WARN(edp_have_panel_power(intel_dp), |
2134 | "eDP port %c panel power already on\n", | |
2135 | port_name(dp_to_dig_port(intel_dp)->port))) | |
9f0fb5be | 2136 | return; |
9934c132 | 2137 | |
4be73780 | 2138 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 2139 | |
bf13e81b | 2140 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2141 | pp = ironlake_get_pp_control(intel_dp); |
5db94019 | 2142 | if (IS_GEN5(dev_priv)) { |
05ce1a49 KP |
2143 | /* ILK workaround: disable reset around power sequence */ |
2144 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
2145 | I915_WRITE(pp_ctrl_reg, pp); |
2146 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2147 | } |
37c6c9b0 | 2148 | |
5a162e22 | 2149 | pp |= PANEL_POWER_ON; |
5db94019 | 2150 | if (!IS_GEN5(dev_priv)) |
99ea7127 KP |
2151 | pp |= PANEL_POWER_RESET; |
2152 | ||
453c5420 JB |
2153 | I915_WRITE(pp_ctrl_reg, pp); |
2154 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2155 | |
4be73780 | 2156 | wait_panel_on(intel_dp); |
dce56b3c | 2157 | intel_dp->last_power_on = jiffies; |
9934c132 | 2158 | |
5db94019 | 2159 | if (IS_GEN5(dev_priv)) { |
05ce1a49 | 2160 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
bf13e81b JN |
2161 | I915_WRITE(pp_ctrl_reg, pp); |
2162 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2163 | } |
9f0fb5be | 2164 | } |
e39b999a | 2165 | |
9f0fb5be VS |
2166 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
2167 | { | |
2168 | if (!is_edp(intel_dp)) | |
2169 | return; | |
2170 | ||
2171 | pps_lock(intel_dp); | |
2172 | edp_panel_on(intel_dp); | |
773538e8 | 2173 | pps_unlock(intel_dp); |
9934c132 JB |
2174 | } |
2175 | ||
9f0fb5be VS |
2176 | |
2177 | static void edp_panel_off(struct intel_dp *intel_dp) | |
9934c132 | 2178 | { |
4e6e1a54 ID |
2179 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2180 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
30add22d | 2181 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2182 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e6e1a54 | 2183 | enum intel_display_power_domain power_domain; |
99ea7127 | 2184 | u32 pp; |
f0f59a00 | 2185 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2186 | |
9f0fb5be VS |
2187 | lockdep_assert_held(&dev_priv->pps_mutex); |
2188 | ||
97af61f5 KP |
2189 | if (!is_edp(intel_dp)) |
2190 | return; | |
37c6c9b0 | 2191 | |
3936fcf4 VS |
2192 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2193 | port_name(dp_to_dig_port(intel_dp)->port)); | |
37c6c9b0 | 2194 | |
3936fcf4 VS |
2195 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2196 | port_name(dp_to_dig_port(intel_dp)->port)); | |
24f3e092 | 2197 | |
453c5420 | 2198 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
2199 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2200 | * panels get very unhappy and cease to work. */ | |
5a162e22 | 2201 | pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
b3064154 | 2202 | EDP_BLC_ENABLE); |
453c5420 | 2203 | |
bf13e81b | 2204 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2205 | |
849e39f5 PZ |
2206 | intel_dp->want_panel_vdd = false; |
2207 | ||
453c5420 JB |
2208 | I915_WRITE(pp_ctrl_reg, pp); |
2209 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2210 | |
d28d4731 | 2211 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
4be73780 | 2212 | wait_panel_off(intel_dp); |
849e39f5 PZ |
2213 | |
2214 | /* We got a reference when we enabled the VDD. */ | |
25f78f58 | 2215 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4e6e1a54 | 2216 | intel_display_power_put(dev_priv, power_domain); |
9f0fb5be | 2217 | } |
e39b999a | 2218 | |
9f0fb5be VS |
2219 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2220 | { | |
2221 | if (!is_edp(intel_dp)) | |
2222 | return; | |
e39b999a | 2223 | |
9f0fb5be VS |
2224 | pps_lock(intel_dp); |
2225 | edp_panel_off(intel_dp); | |
773538e8 | 2226 | pps_unlock(intel_dp); |
9934c132 JB |
2227 | } |
2228 | ||
1250d107 JN |
2229 | /* Enable backlight in the panel power control. */ |
2230 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) | |
32f9d658 | 2231 | { |
da63a9f2 PZ |
2232 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2233 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 2234 | struct drm_i915_private *dev_priv = to_i915(dev); |
32f9d658 | 2235 | u32 pp; |
f0f59a00 | 2236 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2237 | |
01cb9ea6 JB |
2238 | /* |
2239 | * If we enable the backlight right away following a panel power | |
2240 | * on, we may see slight flicker as the panel syncs with the eDP | |
2241 | * link. So delay a bit to make sure the image is solid before | |
2242 | * allowing it to appear. | |
2243 | */ | |
4be73780 | 2244 | wait_backlight_on(intel_dp); |
e39b999a | 2245 | |
773538e8 | 2246 | pps_lock(intel_dp); |
e39b999a | 2247 | |
453c5420 | 2248 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2249 | pp |= EDP_BLC_ENABLE; |
453c5420 | 2250 | |
bf13e81b | 2251 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2252 | |
2253 | I915_WRITE(pp_ctrl_reg, pp); | |
2254 | POSTING_READ(pp_ctrl_reg); | |
e39b999a | 2255 | |
773538e8 | 2256 | pps_unlock(intel_dp); |
32f9d658 ZW |
2257 | } |
2258 | ||
1250d107 JN |
2259 | /* Enable backlight PWM and backlight PP control. */ |
2260 | void intel_edp_backlight_on(struct intel_dp *intel_dp) | |
2261 | { | |
2262 | if (!is_edp(intel_dp)) | |
2263 | return; | |
2264 | ||
2265 | DRM_DEBUG_KMS("\n"); | |
2266 | ||
2267 | intel_panel_enable_backlight(intel_dp->attached_connector); | |
2268 | _intel_edp_backlight_on(intel_dp); | |
2269 | } | |
2270 | ||
2271 | /* Disable backlight in the panel power control. */ | |
2272 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) | |
32f9d658 | 2273 | { |
30add22d | 2274 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2275 | struct drm_i915_private *dev_priv = to_i915(dev); |
32f9d658 | 2276 | u32 pp; |
f0f59a00 | 2277 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2278 | |
f01eca2e KP |
2279 | if (!is_edp(intel_dp)) |
2280 | return; | |
2281 | ||
773538e8 | 2282 | pps_lock(intel_dp); |
e39b999a | 2283 | |
453c5420 | 2284 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2285 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 2286 | |
bf13e81b | 2287 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2288 | |
2289 | I915_WRITE(pp_ctrl_reg, pp); | |
2290 | POSTING_READ(pp_ctrl_reg); | |
f7d2323c | 2291 | |
773538e8 | 2292 | pps_unlock(intel_dp); |
e39b999a VS |
2293 | |
2294 | intel_dp->last_backlight_off = jiffies; | |
f7d2323c | 2295 | edp_wait_backlight_off(intel_dp); |
1250d107 | 2296 | } |
f7d2323c | 2297 | |
1250d107 JN |
2298 | /* Disable backlight PP control and backlight PWM. */ |
2299 | void intel_edp_backlight_off(struct intel_dp *intel_dp) | |
2300 | { | |
2301 | if (!is_edp(intel_dp)) | |
2302 | return; | |
2303 | ||
2304 | DRM_DEBUG_KMS("\n"); | |
f7d2323c | 2305 | |
1250d107 | 2306 | _intel_edp_backlight_off(intel_dp); |
f7d2323c | 2307 | intel_panel_disable_backlight(intel_dp->attached_connector); |
32f9d658 | 2308 | } |
a4fc5ed6 | 2309 | |
73580fb7 JN |
2310 | /* |
2311 | * Hook for controlling the panel power control backlight through the bl_power | |
2312 | * sysfs attribute. Take care to handle multiple calls. | |
2313 | */ | |
2314 | static void intel_edp_backlight_power(struct intel_connector *connector, | |
2315 | bool enable) | |
2316 | { | |
2317 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); | |
e39b999a VS |
2318 | bool is_enabled; |
2319 | ||
773538e8 | 2320 | pps_lock(intel_dp); |
e39b999a | 2321 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
773538e8 | 2322 | pps_unlock(intel_dp); |
73580fb7 JN |
2323 | |
2324 | if (is_enabled == enable) | |
2325 | return; | |
2326 | ||
23ba9373 JN |
2327 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2328 | enable ? "enable" : "disable"); | |
73580fb7 JN |
2329 | |
2330 | if (enable) | |
2331 | _intel_edp_backlight_on(intel_dp); | |
2332 | else | |
2333 | _intel_edp_backlight_off(intel_dp); | |
2334 | } | |
2335 | ||
64e1077a VS |
2336 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
2337 | { | |
2338 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2339 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
2340 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; | |
2341 | ||
2342 | I915_STATE_WARN(cur_state != state, | |
2343 | "DP port %c state assertion failure (expected %s, current %s)\n", | |
2344 | port_name(dig_port->port), | |
87ad3212 | 2345 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2346 | } |
2347 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) | |
2348 | ||
2349 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) | |
2350 | { | |
2351 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; | |
2352 | ||
2353 | I915_STATE_WARN(cur_state != state, | |
2354 | "eDP PLL state assertion failure (expected %s, current %s)\n", | |
87ad3212 | 2355 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2356 | } |
2357 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) | |
2358 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) | |
2359 | ||
85cb48a1 ML |
2360 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp, |
2361 | struct intel_crtc_state *pipe_config) | |
d240f20f | 2362 | { |
85cb48a1 | 2363 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
64e1077a | 2364 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d240f20f | 2365 | |
64e1077a VS |
2366 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2367 | assert_dp_port_disabled(intel_dp); | |
2368 | assert_edp_pll_disabled(dev_priv); | |
2bd2ad64 | 2369 | |
abfce949 | 2370 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
85cb48a1 | 2371 | pipe_config->port_clock); |
abfce949 VS |
2372 | |
2373 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; | |
2374 | ||
85cb48a1 | 2375 | if (pipe_config->port_clock == 162000) |
abfce949 VS |
2376 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
2377 | else | |
2378 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
2379 | ||
2380 | I915_WRITE(DP_A, intel_dp->DP); | |
2381 | POSTING_READ(DP_A); | |
2382 | udelay(500); | |
2383 | ||
6b23f3e8 VS |
2384 | /* |
2385 | * [DevILK] Work around required when enabling DP PLL | |
2386 | * while a pipe is enabled going to FDI: | |
2387 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI | |
2388 | * 2. Program DP PLL enable | |
2389 | */ | |
2390 | if (IS_GEN5(dev_priv)) | |
0f0f74bc | 2391 | intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); |
6b23f3e8 | 2392 | |
0767935e | 2393 | intel_dp->DP |= DP_PLL_ENABLE; |
6fec7662 | 2394 | |
0767935e | 2395 | I915_WRITE(DP_A, intel_dp->DP); |
298b0b39 JB |
2396 | POSTING_READ(DP_A); |
2397 | udelay(200); | |
d240f20f JB |
2398 | } |
2399 | ||
2bd2ad64 | 2400 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 2401 | { |
da63a9f2 | 2402 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
64e1077a VS |
2403 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2404 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
d240f20f | 2405 | |
64e1077a VS |
2406 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2407 | assert_dp_port_disabled(intel_dp); | |
2408 | assert_edp_pll_enabled(dev_priv); | |
2bd2ad64 | 2409 | |
abfce949 VS |
2410 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
2411 | ||
6fec7662 | 2412 | intel_dp->DP &= ~DP_PLL_ENABLE; |
0767935e | 2413 | |
6fec7662 | 2414 | I915_WRITE(DP_A, intel_dp->DP); |
1af5fa1b | 2415 | POSTING_READ(DP_A); |
d240f20f JB |
2416 | udelay(200); |
2417 | } | |
2418 | ||
c7ad3810 | 2419 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 2420 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
2421 | { |
2422 | int ret, i; | |
2423 | ||
2424 | /* Should have a valid DPCD by this point */ | |
2425 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
2426 | return; | |
2427 | ||
2428 | if (mode != DRM_MODE_DPMS_ON) { | |
9d1a1031 JN |
2429 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2430 | DP_SET_POWER_D3); | |
c7ad3810 | 2431 | } else { |
357c0ae9 ID |
2432 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
2433 | ||
c7ad3810 JB |
2434 | /* |
2435 | * When turning on, we need to retry for 1ms to give the sink | |
2436 | * time to wake up. | |
2437 | */ | |
2438 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
2439 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2440 | DP_SET_POWER_D0); | |
c7ad3810 JB |
2441 | if (ret == 1) |
2442 | break; | |
2443 | msleep(1); | |
2444 | } | |
357c0ae9 ID |
2445 | |
2446 | if (ret == 1 && lspcon->active) | |
2447 | lspcon_wait_pcon_mode(lspcon); | |
c7ad3810 | 2448 | } |
f9cac721 JN |
2449 | |
2450 | if (ret != 1) | |
2451 | DRM_DEBUG_KMS("failed to %s sink power state\n", | |
2452 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); | |
c7ad3810 JB |
2453 | } |
2454 | ||
19d8fe15 DV |
2455 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2456 | enum pipe *pipe) | |
d240f20f | 2457 | { |
19d8fe15 | 2458 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 2459 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 | 2460 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2461 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d129bea ID |
2462 | enum intel_display_power_domain power_domain; |
2463 | u32 tmp; | |
6fa9a5ec | 2464 | bool ret; |
6d129bea ID |
2465 | |
2466 | power_domain = intel_display_port_power_domain(encoder); | |
6fa9a5ec | 2467 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
2468 | return false; |
2469 | ||
6fa9a5ec ID |
2470 | ret = false; |
2471 | ||
6d129bea | 2472 | tmp = I915_READ(intel_dp->output_reg); |
19d8fe15 DV |
2473 | |
2474 | if (!(tmp & DP_PORT_EN)) | |
6fa9a5ec | 2475 | goto out; |
19d8fe15 | 2476 | |
5db94019 | 2477 | if (IS_GEN7(dev_priv) && port == PORT_A) { |
19d8fe15 | 2478 | *pipe = PORT_TO_PIPE_CPT(tmp); |
6e266956 | 2479 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
adc289d7 | 2480 | enum pipe p; |
19d8fe15 | 2481 | |
adc289d7 VS |
2482 | for_each_pipe(dev_priv, p) { |
2483 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); | |
2484 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { | |
2485 | *pipe = p; | |
6fa9a5ec ID |
2486 | ret = true; |
2487 | ||
2488 | goto out; | |
19d8fe15 DV |
2489 | } |
2490 | } | |
19d8fe15 | 2491 | |
4a0833ec | 2492 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
f0f59a00 | 2493 | i915_mmio_reg_offset(intel_dp->output_reg)); |
920a14b2 | 2494 | } else if (IS_CHERRYVIEW(dev_priv)) { |
39e5fa88 VS |
2495 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
2496 | } else { | |
2497 | *pipe = PORT_TO_PIPE(tmp); | |
4a0833ec | 2498 | } |
d240f20f | 2499 | |
6fa9a5ec ID |
2500 | ret = true; |
2501 | ||
2502 | out: | |
2503 | intel_display_power_put(dev_priv, power_domain); | |
2504 | ||
2505 | return ret; | |
19d8fe15 | 2506 | } |
d240f20f | 2507 | |
045ac3b5 | 2508 | static void intel_dp_get_config(struct intel_encoder *encoder, |
5cec258b | 2509 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
2510 | { |
2511 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 2512 | u32 tmp, flags = 0; |
63000ef6 | 2513 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2514 | struct drm_i915_private *dev_priv = to_i915(dev); |
63000ef6 XZ |
2515 | enum port port = dp_to_dig_port(intel_dp)->port; |
2516 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
045ac3b5 | 2517 | |
9ed109a7 | 2518 | tmp = I915_READ(intel_dp->output_reg); |
9fcb1704 JN |
2519 | |
2520 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; | |
9ed109a7 | 2521 | |
6e266956 | 2522 | if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
b81e34c2 VS |
2523 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2524 | ||
2525 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
63000ef6 XZ |
2526 | flags |= DRM_MODE_FLAG_PHSYNC; |
2527 | else | |
2528 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2529 | |
b81e34c2 | 2530 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
63000ef6 XZ |
2531 | flags |= DRM_MODE_FLAG_PVSYNC; |
2532 | else | |
2533 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2534 | } else { | |
39e5fa88 | 2535 | if (tmp & DP_SYNC_HS_HIGH) |
63000ef6 XZ |
2536 | flags |= DRM_MODE_FLAG_PHSYNC; |
2537 | else | |
2538 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2539 | |
39e5fa88 | 2540 | if (tmp & DP_SYNC_VS_HIGH) |
63000ef6 XZ |
2541 | flags |= DRM_MODE_FLAG_PVSYNC; |
2542 | else | |
2543 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2544 | } | |
045ac3b5 | 2545 | |
2d112de7 | 2546 | pipe_config->base.adjusted_mode.flags |= flags; |
f1f644dc | 2547 | |
c99f53f7 | 2548 | if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) |
8c875fca VS |
2549 | pipe_config->limited_color_range = true; |
2550 | ||
90a6b7b0 VS |
2551 | pipe_config->lane_count = |
2552 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; | |
2553 | ||
eb14cb74 VS |
2554 | intel_dp_get_m_n(crtc, pipe_config); |
2555 | ||
18442d08 | 2556 | if (port == PORT_A) { |
b377e0df | 2557 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
f1f644dc JB |
2558 | pipe_config->port_clock = 162000; |
2559 | else | |
2560 | pipe_config->port_clock = 270000; | |
2561 | } | |
18442d08 | 2562 | |
e3b247da VS |
2563 | pipe_config->base.adjusted_mode.crtc_clock = |
2564 | intel_dotclock_calculate(pipe_config->port_clock, | |
2565 | &pipe_config->dp_m_n); | |
7f16e5c1 | 2566 | |
6aa23e65 JN |
2567 | if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
2568 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { | |
c6cd2ee2 JN |
2569 | /* |
2570 | * This is a big fat ugly hack. | |
2571 | * | |
2572 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2573 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2574 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2575 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2576 | * max, not what it tells us to use. | |
2577 | * | |
2578 | * Note: This will still be broken if the eDP panel is not lit | |
2579 | * up by the BIOS, and thus we can't get the mode at module | |
2580 | * load. | |
2581 | */ | |
2582 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
2583 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
2584 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
c6cd2ee2 | 2585 | } |
045ac3b5 JB |
2586 | } |
2587 | ||
fd6bbda9 ML |
2588 | static void intel_disable_dp(struct intel_encoder *encoder, |
2589 | struct intel_crtc_state *old_crtc_state, | |
2590 | struct drm_connector_state *old_conn_state) | |
d240f20f | 2591 | { |
e8cb4558 | 2592 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
85cb48a1 | 2593 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
495a5bb8 | 2594 | |
85cb48a1 | 2595 | if (old_crtc_state->has_audio) |
495a5bb8 | 2596 | intel_audio_codec_disable(encoder); |
6cb49835 | 2597 | |
85cb48a1 | 2598 | if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv)) |
b32c6f48 RV |
2599 | intel_psr_disable(intel_dp); |
2600 | ||
6cb49835 DV |
2601 | /* Make sure the panel is off before trying to change the mode. But also |
2602 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 2603 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 2604 | intel_edp_backlight_off(intel_dp); |
fdbc3b1f | 2605 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 2606 | intel_edp_panel_off(intel_dp); |
3739850b | 2607 | |
08aff3fe | 2608 | /* disable the port before the pipe on g4x */ |
85cb48a1 | 2609 | if (INTEL_GEN(dev_priv) < 5) |
3739850b | 2610 | intel_dp_link_down(intel_dp); |
d240f20f JB |
2611 | } |
2612 | ||
fd6bbda9 ML |
2613 | static void ilk_post_disable_dp(struct intel_encoder *encoder, |
2614 | struct intel_crtc_state *old_crtc_state, | |
2615 | struct drm_connector_state *old_conn_state) | |
d240f20f | 2616 | { |
2bd2ad64 | 2617 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2618 | enum port port = dp_to_dig_port(intel_dp)->port; |
2bd2ad64 | 2619 | |
49277c31 | 2620 | intel_dp_link_down(intel_dp); |
abfce949 VS |
2621 | |
2622 | /* Only ilk+ has port A */ | |
08aff3fe VS |
2623 | if (port == PORT_A) |
2624 | ironlake_edp_pll_off(intel_dp); | |
49277c31 VS |
2625 | } |
2626 | ||
fd6bbda9 ML |
2627 | static void vlv_post_disable_dp(struct intel_encoder *encoder, |
2628 | struct intel_crtc_state *old_crtc_state, | |
2629 | struct drm_connector_state *old_conn_state) | |
49277c31 VS |
2630 | { |
2631 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2632 | ||
2633 | intel_dp_link_down(intel_dp); | |
2bd2ad64 DV |
2634 | } |
2635 | ||
fd6bbda9 ML |
2636 | static void chv_post_disable_dp(struct intel_encoder *encoder, |
2637 | struct intel_crtc_state *old_crtc_state, | |
2638 | struct drm_connector_state *old_conn_state) | |
a8f327fb VS |
2639 | { |
2640 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2641 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2642 | struct drm_i915_private *dev_priv = to_i915(dev); |
97fd4d5c | 2643 | |
a8f327fb VS |
2644 | intel_dp_link_down(intel_dp); |
2645 | ||
2646 | mutex_lock(&dev_priv->sb_lock); | |
2647 | ||
2648 | /* Assert data lane reset */ | |
2649 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 2650 | |
a580516d | 2651 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
2652 | } |
2653 | ||
7b13b58a VS |
2654 | static void |
2655 | _intel_dp_set_link_train(struct intel_dp *intel_dp, | |
2656 | uint32_t *DP, | |
2657 | uint8_t dp_train_pat) | |
2658 | { | |
2659 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2660 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 2661 | struct drm_i915_private *dev_priv = to_i915(dev); |
7b13b58a VS |
2662 | enum port port = intel_dig_port->port; |
2663 | ||
8b0878a0 PD |
2664 | if (dp_train_pat & DP_TRAINING_PATTERN_MASK) |
2665 | DRM_DEBUG_KMS("Using DP training pattern TPS%d\n", | |
2666 | dp_train_pat & DP_TRAINING_PATTERN_MASK); | |
2667 | ||
4f8036a2 | 2668 | if (HAS_DDI(dev_priv)) { |
7b13b58a VS |
2669 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
2670 | ||
2671 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2672 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2673 | else | |
2674 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2675 | ||
2676 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2677 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2678 | case DP_TRAINING_PATTERN_DISABLE: | |
2679 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; | |
2680 | ||
2681 | break; | |
2682 | case DP_TRAINING_PATTERN_1: | |
2683 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2684 | break; | |
2685 | case DP_TRAINING_PATTERN_2: | |
2686 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2687 | break; | |
2688 | case DP_TRAINING_PATTERN_3: | |
2689 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2690 | break; | |
2691 | } | |
2692 | I915_WRITE(DP_TP_CTL(port), temp); | |
2693 | ||
5db94019 | 2694 | } else if ((IS_GEN7(dev_priv) && port == PORT_A) || |
6e266956 | 2695 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
7b13b58a VS |
2696 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2697 | ||
2698 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2699 | case DP_TRAINING_PATTERN_DISABLE: | |
2700 | *DP |= DP_LINK_TRAIN_OFF_CPT; | |
2701 | break; | |
2702 | case DP_TRAINING_PATTERN_1: | |
2703 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; | |
2704 | break; | |
2705 | case DP_TRAINING_PATTERN_2: | |
2706 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2707 | break; | |
2708 | case DP_TRAINING_PATTERN_3: | |
8b0878a0 | 2709 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
7b13b58a VS |
2710 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2711 | break; | |
2712 | } | |
2713 | ||
2714 | } else { | |
920a14b2 | 2715 | if (IS_CHERRYVIEW(dev_priv)) |
7b13b58a VS |
2716 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
2717 | else | |
2718 | *DP &= ~DP_LINK_TRAIN_MASK; | |
2719 | ||
2720 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2721 | case DP_TRAINING_PATTERN_DISABLE: | |
2722 | *DP |= DP_LINK_TRAIN_OFF; | |
2723 | break; | |
2724 | case DP_TRAINING_PATTERN_1: | |
2725 | *DP |= DP_LINK_TRAIN_PAT_1; | |
2726 | break; | |
2727 | case DP_TRAINING_PATTERN_2: | |
2728 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2729 | break; | |
2730 | case DP_TRAINING_PATTERN_3: | |
920a14b2 | 2731 | if (IS_CHERRYVIEW(dev_priv)) { |
7b13b58a VS |
2732 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
2733 | } else { | |
8b0878a0 | 2734 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
7b13b58a VS |
2735 | *DP |= DP_LINK_TRAIN_PAT_2; |
2736 | } | |
2737 | break; | |
2738 | } | |
2739 | } | |
2740 | } | |
2741 | ||
85cb48a1 ML |
2742 | static void intel_dp_enable_port(struct intel_dp *intel_dp, |
2743 | struct intel_crtc_state *old_crtc_state) | |
7b13b58a VS |
2744 | { |
2745 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 2746 | struct drm_i915_private *dev_priv = to_i915(dev); |
7b13b58a | 2747 | |
7b13b58a | 2748 | /* enable with pattern 1 (as per spec) */ |
7b13b58a | 2749 | |
8b0878a0 | 2750 | intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1); |
7b713f50 VS |
2751 | |
2752 | /* | |
2753 | * Magic for VLV/CHV. We _must_ first set up the register | |
2754 | * without actually enabling the port, and then do another | |
2755 | * write to enable the port. Otherwise link training will | |
2756 | * fail when the power sequencer is freshly used for this port. | |
2757 | */ | |
2758 | intel_dp->DP |= DP_PORT_EN; | |
85cb48a1 | 2759 | if (old_crtc_state->has_audio) |
6fec7662 | 2760 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
7b713f50 VS |
2761 | |
2762 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2763 | POSTING_READ(intel_dp->output_reg); | |
580d3811 VS |
2764 | } |
2765 | ||
85cb48a1 | 2766 | static void intel_enable_dp(struct intel_encoder *encoder, |
bbf35e9d ML |
2767 | struct intel_crtc_state *pipe_config, |
2768 | struct drm_connector_state *conn_state) | |
d240f20f | 2769 | { |
e8cb4558 DV |
2770 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2771 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2772 | struct drm_i915_private *dev_priv = to_i915(dev); |
c1dec79a | 2773 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
e8cb4558 | 2774 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
d6fbdd15 | 2775 | enum pipe pipe = crtc->pipe; |
5d613501 | 2776 | |
0c33d8d7 DV |
2777 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2778 | return; | |
5d613501 | 2779 | |
093e3f13 VS |
2780 | pps_lock(intel_dp); |
2781 | ||
920a14b2 | 2782 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
093e3f13 VS |
2783 | vlv_init_panel_power_sequencer(intel_dp); |
2784 | ||
85cb48a1 | 2785 | intel_dp_enable_port(intel_dp, pipe_config); |
093e3f13 VS |
2786 | |
2787 | edp_panel_vdd_on(intel_dp); | |
2788 | edp_panel_on(intel_dp); | |
2789 | edp_panel_vdd_off(intel_dp, true); | |
2790 | ||
2791 | pps_unlock(intel_dp); | |
2792 | ||
920a14b2 | 2793 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e0fce78f VS |
2794 | unsigned int lane_mask = 0x0; |
2795 | ||
920a14b2 | 2796 | if (IS_CHERRYVIEW(dev_priv)) |
85cb48a1 | 2797 | lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); |
e0fce78f | 2798 | |
9b6de0a1 VS |
2799 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2800 | lane_mask); | |
e0fce78f | 2801 | } |
61234fa5 | 2802 | |
f01eca2e | 2803 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 2804 | intel_dp_start_link_train(intel_dp); |
3ab9c637 | 2805 | intel_dp_stop_link_train(intel_dp); |
c1dec79a | 2806 | |
85cb48a1 | 2807 | if (pipe_config->has_audio) { |
c1dec79a | 2808 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
d6fbdd15 | 2809 | pipe_name(pipe)); |
bbf35e9d | 2810 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
c1dec79a | 2811 | } |
ab1f90f9 | 2812 | } |
89b667f8 | 2813 | |
fd6bbda9 ML |
2814 | static void g4x_enable_dp(struct intel_encoder *encoder, |
2815 | struct intel_crtc_state *pipe_config, | |
2816 | struct drm_connector_state *conn_state) | |
ecff4f3b | 2817 | { |
828f5c6e JN |
2818 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2819 | ||
bbf35e9d | 2820 | intel_enable_dp(encoder, pipe_config, conn_state); |
4be73780 | 2821 | intel_edp_backlight_on(intel_dp); |
ab1f90f9 | 2822 | } |
89b667f8 | 2823 | |
fd6bbda9 ML |
2824 | static void vlv_enable_dp(struct intel_encoder *encoder, |
2825 | struct intel_crtc_state *pipe_config, | |
2826 | struct drm_connector_state *conn_state) | |
ab1f90f9 | 2827 | { |
828f5c6e JN |
2828 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2829 | ||
4be73780 | 2830 | intel_edp_backlight_on(intel_dp); |
b32c6f48 | 2831 | intel_psr_enable(intel_dp); |
d240f20f JB |
2832 | } |
2833 | ||
fd6bbda9 ML |
2834 | static void g4x_pre_enable_dp(struct intel_encoder *encoder, |
2835 | struct intel_crtc_state *pipe_config, | |
2836 | struct drm_connector_state *conn_state) | |
ab1f90f9 JN |
2837 | { |
2838 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
d6fbdd15 | 2839 | enum port port = dp_to_dig_port(intel_dp)->port; |
ab1f90f9 | 2840 | |
85cb48a1 | 2841 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 2842 | |
d41f1efb | 2843 | /* Only ilk+ has port A */ |
abfce949 | 2844 | if (port == PORT_A) |
85cb48a1 | 2845 | ironlake_edp_pll_on(intel_dp, pipe_config); |
ab1f90f9 JN |
2846 | } |
2847 | ||
83b84597 VS |
2848 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2849 | { | |
2850 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
fac5e23e | 2851 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
83b84597 | 2852 | enum pipe pipe = intel_dp->pps_pipe; |
44cb734c | 2853 | i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); |
83b84597 VS |
2854 | |
2855 | edp_panel_vdd_off_sync(intel_dp); | |
2856 | ||
2857 | /* | |
2858 | * VLV seems to get confused when multiple power seqeuencers | |
2859 | * have the same port selected (even if only one has power/vdd | |
2860 | * enabled). The failure manifests as vlv_wait_port_ready() failing | |
2861 | * CHV on the other hand doesn't seem to mind having the same port | |
2862 | * selected in multiple power seqeuencers, but let's clear the | |
2863 | * port select always when logically disconnecting a power sequencer | |
2864 | * from a port. | |
2865 | */ | |
2866 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", | |
2867 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
2868 | I915_WRITE(pp_on_reg, 0); | |
2869 | POSTING_READ(pp_on_reg); | |
2870 | ||
2871 | intel_dp->pps_pipe = INVALID_PIPE; | |
2872 | } | |
2873 | ||
a4a5d2f8 VS |
2874 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2875 | enum pipe pipe) | |
2876 | { | |
fac5e23e | 2877 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
2878 | struct intel_encoder *encoder; |
2879 | ||
2880 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2881 | ||
ac3c12e4 VS |
2882 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2883 | return; | |
2884 | ||
19c8054c | 2885 | for_each_intel_encoder(dev, encoder) { |
a4a5d2f8 | 2886 | struct intel_dp *intel_dp; |
773538e8 | 2887 | enum port port; |
a4a5d2f8 VS |
2888 | |
2889 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2890 | continue; | |
2891 | ||
2892 | intel_dp = enc_to_intel_dp(&encoder->base); | |
773538e8 | 2893 | port = dp_to_dig_port(intel_dp)->port; |
a4a5d2f8 VS |
2894 | |
2895 | if (intel_dp->pps_pipe != pipe) | |
2896 | continue; | |
2897 | ||
2898 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", | |
773538e8 | 2899 | pipe_name(pipe), port_name(port)); |
a4a5d2f8 | 2900 | |
e02f9a06 | 2901 | WARN(encoder->base.crtc, |
034e43c6 VS |
2902 | "stealing pipe %c power sequencer from active eDP port %c\n", |
2903 | pipe_name(pipe), port_name(port)); | |
a4a5d2f8 | 2904 | |
a4a5d2f8 | 2905 | /* make sure vdd is off before we steal it */ |
83b84597 | 2906 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2907 | } |
2908 | } | |
2909 | ||
2910 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) | |
2911 | { | |
2912 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2913 | struct intel_encoder *encoder = &intel_dig_port->base; | |
2914 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2915 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 | 2916 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
a4a5d2f8 VS |
2917 | |
2918 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2919 | ||
093e3f13 VS |
2920 | if (!is_edp(intel_dp)) |
2921 | return; | |
2922 | ||
a4a5d2f8 VS |
2923 | if (intel_dp->pps_pipe == crtc->pipe) |
2924 | return; | |
2925 | ||
2926 | /* | |
2927 | * If another power sequencer was being used on this | |
2928 | * port previously make sure to turn off vdd there while | |
2929 | * we still have control of it. | |
2930 | */ | |
2931 | if (intel_dp->pps_pipe != INVALID_PIPE) | |
83b84597 | 2932 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2933 | |
2934 | /* | |
2935 | * We may be stealing the power | |
2936 | * sequencer from another port. | |
2937 | */ | |
2938 | vlv_steal_power_sequencer(dev, crtc->pipe); | |
2939 | ||
2940 | /* now it's all ours */ | |
2941 | intel_dp->pps_pipe = crtc->pipe; | |
2942 | ||
2943 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", | |
2944 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); | |
2945 | ||
2946 | /* init power sequencer on this pipe and port */ | |
36b5f425 VS |
2947 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
2948 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
a4a5d2f8 VS |
2949 | } |
2950 | ||
fd6bbda9 ML |
2951 | static void vlv_pre_enable_dp(struct intel_encoder *encoder, |
2952 | struct intel_crtc_state *pipe_config, | |
2953 | struct drm_connector_state *conn_state) | |
a4fc5ed6 | 2954 | { |
5f68c275 | 2955 | vlv_phy_pre_encoder_enable(encoder); |
ab1f90f9 | 2956 | |
bbf35e9d | 2957 | intel_enable_dp(encoder, pipe_config, conn_state); |
89b667f8 JB |
2958 | } |
2959 | ||
fd6bbda9 ML |
2960 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder, |
2961 | struct intel_crtc_state *pipe_config, | |
2962 | struct drm_connector_state *conn_state) | |
89b667f8 | 2963 | { |
85cb48a1 | 2964 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 2965 | |
6da2e616 | 2966 | vlv_phy_pre_pll_enable(encoder); |
a4fc5ed6 KP |
2967 | } |
2968 | ||
fd6bbda9 ML |
2969 | static void chv_pre_enable_dp(struct intel_encoder *encoder, |
2970 | struct intel_crtc_state *pipe_config, | |
2971 | struct drm_connector_state *conn_state) | |
e4a1d846 | 2972 | { |
e7d2a717 | 2973 | chv_phy_pre_encoder_enable(encoder); |
e4a1d846 | 2974 | |
bbf35e9d | 2975 | intel_enable_dp(encoder, pipe_config, conn_state); |
b0b33846 VS |
2976 | |
2977 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 2978 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
2979 | } |
2980 | ||
fd6bbda9 ML |
2981 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder, |
2982 | struct intel_crtc_state *pipe_config, | |
2983 | struct drm_connector_state *conn_state) | |
9197c88b | 2984 | { |
85cb48a1 | 2985 | intel_dp_prepare(encoder, pipe_config); |
625695f8 | 2986 | |
419b1b7a | 2987 | chv_phy_pre_pll_enable(encoder); |
9197c88b VS |
2988 | } |
2989 | ||
fd6bbda9 ML |
2990 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder, |
2991 | struct intel_crtc_state *pipe_config, | |
2992 | struct drm_connector_state *conn_state) | |
d6db995f | 2993 | { |
204970b5 | 2994 | chv_phy_post_pll_disable(encoder); |
d6db995f VS |
2995 | } |
2996 | ||
a4fc5ed6 KP |
2997 | /* |
2998 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
2999 | * link status information | |
3000 | */ | |
94223d04 | 3001 | bool |
93f62dad | 3002 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 3003 | { |
9f085ebb L |
3004 | return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, |
3005 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
3006 | } |
3007 | ||
1100244e | 3008 | /* These are source-specific values. */ |
94223d04 | 3009 | uint8_t |
1a2eb460 | 3010 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 3011 | { |
dd11bc10 | 3012 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
bc7d38a4 | 3013 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 3014 | |
cc3f90f0 | 3015 | if (IS_GEN9_LP(dev_priv)) |
9314726b | 3016 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
dd11bc10 | 3017 | else if (INTEL_GEN(dev_priv) >= 9) { |
06411f08 | 3018 | if (dev_priv->vbt.edp.low_vswing && port == PORT_A) |
7ad14a29 | 3019 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
5a9d1f1a | 3020 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
920a14b2 | 3021 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
bd60018a | 3022 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
5db94019 | 3023 | else if (IS_GEN7(dev_priv) && port == PORT_A) |
bd60018a | 3024 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
6e266956 | 3025 | else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) |
bd60018a | 3026 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
1a2eb460 | 3027 | else |
bd60018a | 3028 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
1a2eb460 KP |
3029 | } |
3030 | ||
94223d04 | 3031 | uint8_t |
1a2eb460 KP |
3032 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
3033 | { | |
8652744b | 3034 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
bc7d38a4 | 3035 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 3036 | |
8652744b | 3037 | if (INTEL_GEN(dev_priv) >= 9) { |
5a9d1f1a DL |
3038 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3039 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: | |
3040 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3041 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3042 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3043 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3044 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
7ad14a29 SJ |
3045 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3046 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
5a9d1f1a DL |
3047 | default: |
3048 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
3049 | } | |
8652744b | 3050 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
d6c0d722 | 3051 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3052 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3053 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3054 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3055 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3056 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3057 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3058 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
d6c0d722 | 3059 | default: |
bd60018a | 3060 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
d6c0d722 | 3061 | } |
8652744b | 3062 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e2fa6fba | 3063 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3064 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3065 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3066 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3067 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3068 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3069 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3070 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
e2fa6fba | 3071 | default: |
bd60018a | 3072 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
e2fa6fba | 3073 | } |
8652744b | 3074 | } else if (IS_GEN7(dev_priv) && port == PORT_A) { |
1a2eb460 | 3075 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3076 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3077 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3078 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3079 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3080 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
1a2eb460 | 3081 | default: |
bd60018a | 3082 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 KP |
3083 | } |
3084 | } else { | |
3085 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
3086 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3087 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3088 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3089 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3090 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3091 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3092 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
1a2eb460 | 3093 | default: |
bd60018a | 3094 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 | 3095 | } |
a4fc5ed6 KP |
3096 | } |
3097 | } | |
3098 | ||
5829975c | 3099 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
e2fa6fba | 3100 | { |
53d98725 | 3101 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
e2fa6fba P |
3102 | unsigned long demph_reg_value, preemph_reg_value, |
3103 | uniqtranscale_reg_value; | |
3104 | uint8_t train_set = intel_dp->train_set[0]; | |
e2fa6fba P |
3105 | |
3106 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3107 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e2fa6fba P |
3108 | preemph_reg_value = 0x0004000; |
3109 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3110 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3111 | demph_reg_value = 0x2B405555; |
3112 | uniqtranscale_reg_value = 0x552AB83A; | |
3113 | break; | |
bd60018a | 3114 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3115 | demph_reg_value = 0x2B404040; |
3116 | uniqtranscale_reg_value = 0x5548B83A; | |
3117 | break; | |
bd60018a | 3118 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3119 | demph_reg_value = 0x2B245555; |
3120 | uniqtranscale_reg_value = 0x5560B83A; | |
3121 | break; | |
bd60018a | 3122 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e2fa6fba P |
3123 | demph_reg_value = 0x2B405555; |
3124 | uniqtranscale_reg_value = 0x5598DA3A; | |
3125 | break; | |
3126 | default: | |
3127 | return 0; | |
3128 | } | |
3129 | break; | |
bd60018a | 3130 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e2fa6fba P |
3131 | preemph_reg_value = 0x0002000; |
3132 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3133 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3134 | demph_reg_value = 0x2B404040; |
3135 | uniqtranscale_reg_value = 0x5552B83A; | |
3136 | break; | |
bd60018a | 3137 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3138 | demph_reg_value = 0x2B404848; |
3139 | uniqtranscale_reg_value = 0x5580B83A; | |
3140 | break; | |
bd60018a | 3141 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3142 | demph_reg_value = 0x2B404040; |
3143 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3144 | break; | |
3145 | default: | |
3146 | return 0; | |
3147 | } | |
3148 | break; | |
bd60018a | 3149 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e2fa6fba P |
3150 | preemph_reg_value = 0x0000000; |
3151 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3152 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3153 | demph_reg_value = 0x2B305555; |
3154 | uniqtranscale_reg_value = 0x5570B83A; | |
3155 | break; | |
bd60018a | 3156 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3157 | demph_reg_value = 0x2B2B4040; |
3158 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3159 | break; | |
3160 | default: | |
3161 | return 0; | |
3162 | } | |
3163 | break; | |
bd60018a | 3164 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e2fa6fba P |
3165 | preemph_reg_value = 0x0006000; |
3166 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3167 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3168 | demph_reg_value = 0x1B405555; |
3169 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3170 | break; | |
3171 | default: | |
3172 | return 0; | |
3173 | } | |
3174 | break; | |
3175 | default: | |
3176 | return 0; | |
3177 | } | |
3178 | ||
53d98725 ACO |
3179 | vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, |
3180 | uniqtranscale_reg_value, 0); | |
e2fa6fba P |
3181 | |
3182 | return 0; | |
3183 | } | |
3184 | ||
5829975c | 3185 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
e4a1d846 | 3186 | { |
b7fa22d8 ACO |
3187 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3188 | u32 deemph_reg_value, margin_reg_value; | |
3189 | bool uniq_trans_scale = false; | |
e4a1d846 | 3190 | uint8_t train_set = intel_dp->train_set[0]; |
e4a1d846 CML |
3191 | |
3192 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3193 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e4a1d846 | 3194 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3195 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3196 | deemph_reg_value = 128; |
3197 | margin_reg_value = 52; | |
3198 | break; | |
bd60018a | 3199 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3200 | deemph_reg_value = 128; |
3201 | margin_reg_value = 77; | |
3202 | break; | |
bd60018a | 3203 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3204 | deemph_reg_value = 128; |
3205 | margin_reg_value = 102; | |
3206 | break; | |
bd60018a | 3207 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e4a1d846 CML |
3208 | deemph_reg_value = 128; |
3209 | margin_reg_value = 154; | |
b7fa22d8 | 3210 | uniq_trans_scale = true; |
e4a1d846 CML |
3211 | break; |
3212 | default: | |
3213 | return 0; | |
3214 | } | |
3215 | break; | |
bd60018a | 3216 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e4a1d846 | 3217 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3218 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3219 | deemph_reg_value = 85; |
3220 | margin_reg_value = 78; | |
3221 | break; | |
bd60018a | 3222 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3223 | deemph_reg_value = 85; |
3224 | margin_reg_value = 116; | |
3225 | break; | |
bd60018a | 3226 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3227 | deemph_reg_value = 85; |
3228 | margin_reg_value = 154; | |
3229 | break; | |
3230 | default: | |
3231 | return 0; | |
3232 | } | |
3233 | break; | |
bd60018a | 3234 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e4a1d846 | 3235 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3236 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3237 | deemph_reg_value = 64; |
3238 | margin_reg_value = 104; | |
3239 | break; | |
bd60018a | 3240 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3241 | deemph_reg_value = 64; |
3242 | margin_reg_value = 154; | |
3243 | break; | |
3244 | default: | |
3245 | return 0; | |
3246 | } | |
3247 | break; | |
bd60018a | 3248 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e4a1d846 | 3249 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3250 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3251 | deemph_reg_value = 43; |
3252 | margin_reg_value = 154; | |
3253 | break; | |
3254 | default: | |
3255 | return 0; | |
3256 | } | |
3257 | break; | |
3258 | default: | |
3259 | return 0; | |
3260 | } | |
3261 | ||
b7fa22d8 ACO |
3262 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
3263 | margin_reg_value, uniq_trans_scale); | |
e4a1d846 CML |
3264 | |
3265 | return 0; | |
3266 | } | |
3267 | ||
a4fc5ed6 | 3268 | static uint32_t |
5829975c | 3269 | gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 3270 | { |
3cf2efb1 | 3271 | uint32_t signal_levels = 0; |
a4fc5ed6 | 3272 | |
3cf2efb1 | 3273 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3274 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
a4fc5ed6 KP |
3275 | default: |
3276 | signal_levels |= DP_VOLTAGE_0_4; | |
3277 | break; | |
bd60018a | 3278 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
a4fc5ed6 KP |
3279 | signal_levels |= DP_VOLTAGE_0_6; |
3280 | break; | |
bd60018a | 3281 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
a4fc5ed6 KP |
3282 | signal_levels |= DP_VOLTAGE_0_8; |
3283 | break; | |
bd60018a | 3284 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
a4fc5ed6 KP |
3285 | signal_levels |= DP_VOLTAGE_1_2; |
3286 | break; | |
3287 | } | |
3cf2efb1 | 3288 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
bd60018a | 3289 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
a4fc5ed6 KP |
3290 | default: |
3291 | signal_levels |= DP_PRE_EMPHASIS_0; | |
3292 | break; | |
bd60018a | 3293 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
a4fc5ed6 KP |
3294 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3295 | break; | |
bd60018a | 3296 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
a4fc5ed6 KP |
3297 | signal_levels |= DP_PRE_EMPHASIS_6; |
3298 | break; | |
bd60018a | 3299 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
a4fc5ed6 KP |
3300 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3301 | break; | |
3302 | } | |
3303 | return signal_levels; | |
3304 | } | |
3305 | ||
e3421a18 ZW |
3306 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3307 | static uint32_t | |
5829975c | 3308 | gen6_edp_signal_levels(uint8_t train_set) |
e3421a18 | 3309 | { |
3c5a62b5 YL |
3310 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3311 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3312 | switch (signal_levels) { | |
bd60018a SJ |
3313 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3314 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3315 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
bd60018a | 3316 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3c5a62b5 | 3317 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
bd60018a SJ |
3318 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3319 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
3c5a62b5 | 3320 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
bd60018a SJ |
3321 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3322 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
3c5a62b5 | 3323 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
bd60018a SJ |
3324 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3325 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3326 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
e3421a18 | 3327 | default: |
3c5a62b5 YL |
3328 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3329 | "0x%x\n", signal_levels); | |
3330 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
3331 | } |
3332 | } | |
3333 | ||
1a2eb460 KP |
3334 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3335 | static uint32_t | |
5829975c | 3336 | gen7_edp_signal_levels(uint8_t train_set) |
1a2eb460 KP |
3337 | { |
3338 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
3339 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3340 | switch (signal_levels) { | |
bd60018a | 3341 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3342 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
bd60018a | 3343 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 | 3344 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
bd60018a | 3345 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
1a2eb460 KP |
3346 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3347 | ||
bd60018a | 3348 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3349 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
bd60018a | 3350 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3351 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3352 | ||
bd60018a | 3353 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3354 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
bd60018a | 3355 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3356 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3357 | ||
3358 | default: | |
3359 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
3360 | "0x%x\n", signal_levels); | |
3361 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
3362 | } | |
3363 | } | |
3364 | ||
94223d04 | 3365 | void |
f4eb692e | 3366 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
f0a3424e PZ |
3367 | { |
3368 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 3369 | enum port port = intel_dig_port->port; |
f0a3424e | 3370 | struct drm_device *dev = intel_dig_port->base.base.dev; |
b905a915 | 3371 | struct drm_i915_private *dev_priv = to_i915(dev); |
f8896f5d | 3372 | uint32_t signal_levels, mask = 0; |
f0a3424e PZ |
3373 | uint8_t train_set = intel_dp->train_set[0]; |
3374 | ||
4f8036a2 | 3375 | if (HAS_DDI(dev_priv)) { |
f8896f5d DW |
3376 | signal_levels = ddi_signal_levels(intel_dp); |
3377 | ||
e2d214ae | 3378 | if (IS_BROXTON(dev_priv)) |
f8896f5d DW |
3379 | signal_levels = 0; |
3380 | else | |
3381 | mask = DDI_BUF_EMP_MASK; | |
920a14b2 | 3382 | } else if (IS_CHERRYVIEW(dev_priv)) { |
5829975c | 3383 | signal_levels = chv_signal_levels(intel_dp); |
11a914c2 | 3384 | } else if (IS_VALLEYVIEW(dev_priv)) { |
5829975c | 3385 | signal_levels = vlv_signal_levels(intel_dp); |
5db94019 | 3386 | } else if (IS_GEN7(dev_priv) && port == PORT_A) { |
5829975c | 3387 | signal_levels = gen7_edp_signal_levels(train_set); |
f0a3424e | 3388 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
5db94019 | 3389 | } else if (IS_GEN6(dev_priv) && port == PORT_A) { |
5829975c | 3390 | signal_levels = gen6_edp_signal_levels(train_set); |
f0a3424e PZ |
3391 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3392 | } else { | |
5829975c | 3393 | signal_levels = gen4_signal_levels(train_set); |
f0a3424e PZ |
3394 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3395 | } | |
3396 | ||
96fb9f9b VK |
3397 | if (mask) |
3398 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
3399 | ||
3400 | DRM_DEBUG_KMS("Using vswing level %d\n", | |
3401 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); | |
3402 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", | |
3403 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
3404 | DP_TRAIN_PRE_EMPHASIS_SHIFT); | |
f0a3424e | 3405 | |
f4eb692e | 3406 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
b905a915 ACO |
3407 | |
3408 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
3409 | POSTING_READ(intel_dp->output_reg); | |
f0a3424e PZ |
3410 | } |
3411 | ||
94223d04 | 3412 | void |
e9c176d5 ACO |
3413 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
3414 | uint8_t dp_train_pat) | |
a4fc5ed6 | 3415 | { |
174edf1f | 3416 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
90a6b7b0 VS |
3417 | struct drm_i915_private *dev_priv = |
3418 | to_i915(intel_dig_port->base.base.dev); | |
a4fc5ed6 | 3419 | |
f4eb692e | 3420 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
47ea7542 | 3421 | |
f4eb692e | 3422 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
ea5b213a | 3423 | POSTING_READ(intel_dp->output_reg); |
e9c176d5 ACO |
3424 | } |
3425 | ||
94223d04 | 3426 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3ab9c637 ID |
3427 | { |
3428 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3429 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 3430 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ab9c637 ID |
3431 | enum port port = intel_dig_port->port; |
3432 | uint32_t val; | |
3433 | ||
4f8036a2 | 3434 | if (!HAS_DDI(dev_priv)) |
3ab9c637 ID |
3435 | return; |
3436 | ||
3437 | val = I915_READ(DP_TP_CTL(port)); | |
3438 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
3439 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
3440 | I915_WRITE(DP_TP_CTL(port), val); | |
3441 | ||
3442 | /* | |
3443 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
3444 | * we need to set idle transmission mode is to work around a HW issue | |
3445 | * where we enable the pipe while not in idle link-training mode. | |
3446 | * In this case there is requirement to wait for a minimum number of | |
3447 | * idle patterns to be sent. | |
3448 | */ | |
3449 | if (port == PORT_A) | |
3450 | return; | |
3451 | ||
a767017f CW |
3452 | if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port), |
3453 | DP_TP_STATUS_IDLE_DONE, | |
3454 | DP_TP_STATUS_IDLE_DONE, | |
3455 | 1)) | |
3ab9c637 ID |
3456 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
3457 | } | |
3458 | ||
a4fc5ed6 | 3459 | static void |
ea5b213a | 3460 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 3461 | { |
da63a9f2 | 3462 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1612c8bd | 3463 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
bc7d38a4 | 3464 | enum port port = intel_dig_port->port; |
da63a9f2 | 3465 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 3466 | struct drm_i915_private *dev_priv = to_i915(dev); |
ea5b213a | 3467 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 3468 | |
4f8036a2 | 3469 | if (WARN_ON(HAS_DDI(dev_priv))) |
c19b0669 PZ |
3470 | return; |
3471 | ||
0c33d8d7 | 3472 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
3473 | return; |
3474 | ||
28c97730 | 3475 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 3476 | |
5db94019 | 3477 | if ((IS_GEN7(dev_priv) && port == PORT_A) || |
6e266956 | 3478 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
e3421a18 | 3479 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1612c8bd | 3480 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
e3421a18 | 3481 | } else { |
920a14b2 | 3482 | if (IS_CHERRYVIEW(dev_priv)) |
aad3d14d VS |
3483 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
3484 | else | |
3485 | DP &= ~DP_LINK_TRAIN_MASK; | |
1612c8bd | 3486 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
e3421a18 | 3487 | } |
1612c8bd | 3488 | I915_WRITE(intel_dp->output_reg, DP); |
fe255d00 | 3489 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 3490 | |
1612c8bd VS |
3491 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3492 | I915_WRITE(intel_dp->output_reg, DP); | |
3493 | POSTING_READ(intel_dp->output_reg); | |
3494 | ||
3495 | /* | |
3496 | * HW workaround for IBX, we need to move the port | |
3497 | * to transcoder A after disabling it to allow the | |
3498 | * matching HDMI port to be enabled on transcoder A. | |
3499 | */ | |
6e266956 | 3500 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { |
0c241d5b VS |
3501 | /* |
3502 | * We get CPU/PCH FIFO underruns on the other pipe when | |
3503 | * doing the workaround. Sweep them under the rug. | |
3504 | */ | |
3505 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3506 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3507 | ||
1612c8bd VS |
3508 | /* always enable with pattern 1 (as per spec) */ |
3509 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); | |
3510 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; | |
3511 | I915_WRITE(intel_dp->output_reg, DP); | |
3512 | POSTING_READ(intel_dp->output_reg); | |
3513 | ||
3514 | DP &= ~DP_PORT_EN; | |
5bddd17f | 3515 | I915_WRITE(intel_dp->output_reg, DP); |
0ca09685 | 3516 | POSTING_READ(intel_dp->output_reg); |
0c241d5b | 3517 | |
0f0f74bc | 3518 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
3519 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
3520 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
5bddd17f EA |
3521 | } |
3522 | ||
f01eca2e | 3523 | msleep(intel_dp->panel_power_down_delay); |
6fec7662 VS |
3524 | |
3525 | intel_dp->DP = DP; | |
a4fc5ed6 KP |
3526 | } |
3527 | ||
24e807e7 | 3528 | bool |
fe5a66f9 | 3529 | intel_dp_read_dpcd(struct intel_dp *intel_dp) |
92fd8fd1 | 3530 | { |
9f085ebb L |
3531 | if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3532 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 3533 | return false; /* aux transfer failed */ |
92fd8fd1 | 3534 | |
a8e98153 | 3535 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
577c7a50 | 3536 | |
fe5a66f9 VS |
3537 | return intel_dp->dpcd[DP_DPCD_REV] != 0; |
3538 | } | |
edb39244 | 3539 | |
fe5a66f9 VS |
3540 | static bool |
3541 | intel_edp_init_dpcd(struct intel_dp *intel_dp) | |
3542 | { | |
3543 | struct drm_i915_private *dev_priv = | |
3544 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
30d9aa42 | 3545 | |
fe5a66f9 VS |
3546 | /* this function is meant to be called only once */ |
3547 | WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); | |
30d9aa42 | 3548 | |
fe5a66f9 | 3549 | if (!intel_dp_read_dpcd(intel_dp)) |
30d9aa42 SS |
3550 | return false; |
3551 | ||
12a47a42 ID |
3552 | intel_dp_read_desc(intel_dp); |
3553 | ||
fe5a66f9 VS |
3554 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
3555 | dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
3556 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
474d1ec4 | 3557 | |
fe5a66f9 VS |
3558 | /* Check if the panel supports PSR */ |
3559 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, | |
3560 | intel_dp->psr_dpcd, | |
3561 | sizeof(intel_dp->psr_dpcd)); | |
3562 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { | |
3563 | dev_priv->psr.sink_support = true; | |
3564 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); | |
3565 | } | |
86ee27b5 | 3566 | |
fe5a66f9 VS |
3567 | if (INTEL_GEN(dev_priv) >= 9 && |
3568 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { | |
3569 | uint8_t frame_sync_cap; | |
3570 | ||
3571 | dev_priv->psr.sink_support = true; | |
3572 | drm_dp_dpcd_read(&intel_dp->aux, | |
3573 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, | |
3574 | &frame_sync_cap, 1); | |
3575 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; | |
3576 | /* PSR2 needs frame sync as well */ | |
3577 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; | |
3578 | DRM_DEBUG_KMS("PSR2 %s on sink", | |
3579 | dev_priv->psr.psr2_support ? "supported" : "not supported"); | |
50003939 JN |
3580 | } |
3581 | ||
fe5a66f9 VS |
3582 | /* Read the eDP Display control capabilities registers */ |
3583 | if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && | |
3584 | drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, | |
f7170e2e DC |
3585 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == |
3586 | sizeof(intel_dp->edp_dpcd)) | |
fe5a66f9 VS |
3587 | DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), |
3588 | intel_dp->edp_dpcd); | |
06ea66b6 | 3589 | |
fc0f8e25 | 3590 | /* Intermediate frequency support */ |
fe5a66f9 | 3591 | if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */ |
94ca719e | 3592 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
ea2d8a42 VS |
3593 | int i; |
3594 | ||
9f085ebb L |
3595 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, |
3596 | sink_rates, sizeof(sink_rates)); | |
ea2d8a42 | 3597 | |
94ca719e VS |
3598 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
3599 | int val = le16_to_cpu(sink_rates[i]); | |
ea2d8a42 VS |
3600 | |
3601 | if (val == 0) | |
3602 | break; | |
3603 | ||
fd81c44e DP |
3604 | /* Value read multiplied by 200kHz gives the per-lane |
3605 | * link rate in kHz. The source rates are, however, | |
3606 | * stored in terms of LS_Clk kHz. The full conversion | |
3607 | * back to symbols is | |
3608 | * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) | |
3609 | */ | |
af77b974 | 3610 | intel_dp->sink_rates[i] = (val * 200) / 10; |
ea2d8a42 | 3611 | } |
94ca719e | 3612 | intel_dp->num_sink_rates = i; |
fc0f8e25 | 3613 | } |
0336400e | 3614 | |
fe5a66f9 VS |
3615 | return true; |
3616 | } | |
3617 | ||
3618 | ||
3619 | static bool | |
3620 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
3621 | { | |
3622 | if (!intel_dp_read_dpcd(intel_dp)) | |
3623 | return false; | |
3624 | ||
3625 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT, | |
3626 | &intel_dp->sink_count, 1) < 0) | |
3627 | return false; | |
3628 | ||
3629 | /* | |
3630 | * Sink count can change between short pulse hpd hence | |
3631 | * a member variable in intel_dp will track any changes | |
3632 | * between short pulse interrupts. | |
3633 | */ | |
3634 | intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count); | |
3635 | ||
3636 | /* | |
3637 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that | |
3638 | * a dongle is present but no display. Unless we require to know | |
3639 | * if a dongle is present or not, we don't need to update | |
3640 | * downstream port information. So, an early return here saves | |
3641 | * time from performing other operations which are not required. | |
3642 | */ | |
3643 | if (!is_edp(intel_dp) && !intel_dp->sink_count) | |
3644 | return false; | |
0336400e | 3645 | |
c726ad01 | 3646 | if (!drm_dp_is_branch(intel_dp->dpcd)) |
edb39244 AJ |
3647 | return true; /* native DP sink */ |
3648 | ||
3649 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
3650 | return true; /* no per-port downstream info */ | |
3651 | ||
9f085ebb L |
3652 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3653 | intel_dp->downstream_ports, | |
3654 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
3655 | return false; /* downstream port status fetch failed */ |
3656 | ||
3657 | return true; | |
92fd8fd1 KP |
3658 | } |
3659 | ||
0e32b39c | 3660 | static bool |
c4e3170a | 3661 | intel_dp_can_mst(struct intel_dp *intel_dp) |
0e32b39c DA |
3662 | { |
3663 | u8 buf[1]; | |
3664 | ||
7cc96139 NS |
3665 | if (!i915.enable_dp_mst) |
3666 | return false; | |
3667 | ||
0e32b39c DA |
3668 | if (!intel_dp->can_mst) |
3669 | return false; | |
3670 | ||
3671 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) | |
3672 | return false; | |
3673 | ||
c4e3170a VS |
3674 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1) |
3675 | return false; | |
0e32b39c | 3676 | |
c4e3170a VS |
3677 | return buf[0] & DP_MST_CAP; |
3678 | } | |
3679 | ||
3680 | static void | |
3681 | intel_dp_configure_mst(struct intel_dp *intel_dp) | |
3682 | { | |
3683 | if (!i915.enable_dp_mst) | |
3684 | return; | |
3685 | ||
3686 | if (!intel_dp->can_mst) | |
3687 | return; | |
3688 | ||
3689 | intel_dp->is_mst = intel_dp_can_mst(intel_dp); | |
3690 | ||
3691 | if (intel_dp->is_mst) | |
3692 | DRM_DEBUG_KMS("Sink is MST capable\n"); | |
3693 | else | |
3694 | DRM_DEBUG_KMS("Sink is not MST capable\n"); | |
3695 | ||
3696 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
3697 | intel_dp->is_mst); | |
0e32b39c DA |
3698 | } |
3699 | ||
e5a1cab5 | 3700 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
d2e216d0 | 3701 | { |
082dcc7c | 3702 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
0f0f74bc | 3703 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c | 3704 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
ad9dc91b | 3705 | u8 buf; |
e5a1cab5 | 3706 | int ret = 0; |
c6297843 RV |
3707 | int count = 0; |
3708 | int attempts = 10; | |
d2e216d0 | 3709 | |
082dcc7c RV |
3710 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
3711 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); | |
e5a1cab5 RV |
3712 | ret = -EIO; |
3713 | goto out; | |
4373f0f2 PZ |
3714 | } |
3715 | ||
082dcc7c | 3716 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
e5a1cab5 | 3717 | buf & ~DP_TEST_SINK_START) < 0) { |
082dcc7c | 3718 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
e5a1cab5 RV |
3719 | ret = -EIO; |
3720 | goto out; | |
3721 | } | |
d2e216d0 | 3722 | |
c6297843 | 3723 | do { |
0f0f74bc | 3724 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
c6297843 RV |
3725 | |
3726 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
3727 | DP_TEST_SINK_MISC, &buf) < 0) { | |
3728 | ret = -EIO; | |
3729 | goto out; | |
3730 | } | |
3731 | count = buf & DP_TEST_COUNT_MASK; | |
3732 | } while (--attempts && count); | |
3733 | ||
3734 | if (attempts == 0) { | |
dc5a9037 | 3735 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
c6297843 RV |
3736 | ret = -ETIMEDOUT; |
3737 | } | |
3738 | ||
e5a1cab5 | 3739 | out: |
082dcc7c | 3740 | hsw_enable_ips(intel_crtc); |
e5a1cab5 | 3741 | return ret; |
082dcc7c RV |
3742 | } |
3743 | ||
3744 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) | |
3745 | { | |
3746 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
0f0f74bc | 3747 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c RV |
3748 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3749 | u8 buf; | |
e5a1cab5 RV |
3750 | int ret; |
3751 | ||
082dcc7c RV |
3752 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
3753 | return -EIO; | |
3754 | ||
3755 | if (!(buf & DP_TEST_CRC_SUPPORTED)) | |
3756 | return -ENOTTY; | |
3757 | ||
3758 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) | |
3759 | return -EIO; | |
3760 | ||
6d8175da RV |
3761 | if (buf & DP_TEST_SINK_START) { |
3762 | ret = intel_dp_sink_crc_stop(intel_dp); | |
3763 | if (ret) | |
3764 | return ret; | |
3765 | } | |
3766 | ||
082dcc7c | 3767 | hsw_disable_ips(intel_crtc); |
1dda5f93 | 3768 | |
9d1a1031 | 3769 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
082dcc7c RV |
3770 | buf | DP_TEST_SINK_START) < 0) { |
3771 | hsw_enable_ips(intel_crtc); | |
3772 | return -EIO; | |
4373f0f2 PZ |
3773 | } |
3774 | ||
0f0f74bc | 3775 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
082dcc7c RV |
3776 | return 0; |
3777 | } | |
3778 | ||
3779 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) | |
3780 | { | |
3781 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
0f0f74bc | 3782 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c RV |
3783 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3784 | u8 buf; | |
621d4c76 | 3785 | int count, ret; |
082dcc7c | 3786 | int attempts = 6; |
082dcc7c RV |
3787 | |
3788 | ret = intel_dp_sink_crc_start(intel_dp); | |
3789 | if (ret) | |
3790 | return ret; | |
3791 | ||
ad9dc91b | 3792 | do { |
0f0f74bc | 3793 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
621d4c76 | 3794 | |
1dda5f93 | 3795 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4373f0f2 PZ |
3796 | DP_TEST_SINK_MISC, &buf) < 0) { |
3797 | ret = -EIO; | |
afe0d67e | 3798 | goto stop; |
4373f0f2 | 3799 | } |
621d4c76 | 3800 | count = buf & DP_TEST_COUNT_MASK; |
aabc95dc | 3801 | |
7e38eeff | 3802 | } while (--attempts && count == 0); |
ad9dc91b RV |
3803 | |
3804 | if (attempts == 0) { | |
7e38eeff RV |
3805 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
3806 | ret = -ETIMEDOUT; | |
3807 | goto stop; | |
3808 | } | |
3809 | ||
3810 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { | |
3811 | ret = -EIO; | |
3812 | goto stop; | |
ad9dc91b | 3813 | } |
d2e216d0 | 3814 | |
afe0d67e | 3815 | stop: |
082dcc7c | 3816 | intel_dp_sink_crc_stop(intel_dp); |
4373f0f2 | 3817 | return ret; |
d2e216d0 RV |
3818 | } |
3819 | ||
a60f0e38 JB |
3820 | static bool |
3821 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3822 | { | |
9f085ebb | 3823 | return drm_dp_dpcd_read(&intel_dp->aux, |
9d1a1031 JN |
3824 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
3825 | sink_irq_vector, 1) == 1; | |
a60f0e38 JB |
3826 | } |
3827 | ||
0e32b39c DA |
3828 | static bool |
3829 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3830 | { | |
3831 | int ret; | |
3832 | ||
9f085ebb | 3833 | ret = drm_dp_dpcd_read(&intel_dp->aux, |
0e32b39c DA |
3834 | DP_SINK_COUNT_ESI, |
3835 | sink_irq_vector, 14); | |
3836 | if (ret != 14) | |
3837 | return false; | |
3838 | ||
3839 | return true; | |
3840 | } | |
3841 | ||
c5d5ab7a TP |
3842 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
3843 | { | |
3844 | uint8_t test_result = DP_TEST_ACK; | |
3845 | return test_result; | |
3846 | } | |
3847 | ||
3848 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) | |
3849 | { | |
3850 | uint8_t test_result = DP_TEST_NAK; | |
3851 | return test_result; | |
3852 | } | |
3853 | ||
3854 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) | |
a60f0e38 | 3855 | { |
c5d5ab7a | 3856 | uint8_t test_result = DP_TEST_NAK; |
559be30c TP |
3857 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
3858 | struct drm_connector *connector = &intel_connector->base; | |
3859 | ||
3860 | if (intel_connector->detect_edid == NULL || | |
ac6f2e29 | 3861 | connector->edid_corrupt || |
559be30c TP |
3862 | intel_dp->aux.i2c_defer_count > 6) { |
3863 | /* Check EDID read for NACKs, DEFERs and corruption | |
3864 | * (DP CTS 1.2 Core r1.1) | |
3865 | * 4.2.2.4 : Failed EDID read, I2C_NAK | |
3866 | * 4.2.2.5 : Failed EDID read, I2C_DEFER | |
3867 | * 4.2.2.6 : EDID corruption detected | |
3868 | * Use failsafe mode for all cases | |
3869 | */ | |
3870 | if (intel_dp->aux.i2c_nack_count > 0 || | |
3871 | intel_dp->aux.i2c_defer_count > 0) | |
3872 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", | |
3873 | intel_dp->aux.i2c_nack_count, | |
3874 | intel_dp->aux.i2c_defer_count); | |
3875 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; | |
3876 | } else { | |
f79b468e TS |
3877 | struct edid *block = intel_connector->detect_edid; |
3878 | ||
3879 | /* We have to write the checksum | |
3880 | * of the last block read | |
3881 | */ | |
3882 | block += intel_connector->detect_edid->extensions; | |
3883 | ||
559be30c TP |
3884 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
3885 | DP_TEST_EDID_CHECKSUM, | |
f79b468e | 3886 | &block->checksum, |
5a1cc655 | 3887 | 1)) |
559be30c TP |
3888 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
3889 | ||
3890 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; | |
3891 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; | |
3892 | } | |
3893 | ||
3894 | /* Set test active flag here so userspace doesn't interrupt things */ | |
3895 | intel_dp->compliance_test_active = 1; | |
3896 | ||
c5d5ab7a TP |
3897 | return test_result; |
3898 | } | |
3899 | ||
3900 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) | |
a60f0e38 | 3901 | { |
c5d5ab7a TP |
3902 | uint8_t test_result = DP_TEST_NAK; |
3903 | return test_result; | |
3904 | } | |
3905 | ||
3906 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
3907 | { | |
3908 | uint8_t response = DP_TEST_NAK; | |
3909 | uint8_t rxdata = 0; | |
3910 | int status = 0; | |
3911 | ||
c5d5ab7a TP |
3912 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
3913 | if (status <= 0) { | |
3914 | DRM_DEBUG_KMS("Could not read test request from sink\n"); | |
3915 | goto update_status; | |
3916 | } | |
3917 | ||
3918 | switch (rxdata) { | |
3919 | case DP_TEST_LINK_TRAINING: | |
3920 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); | |
3921 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; | |
3922 | response = intel_dp_autotest_link_training(intel_dp); | |
3923 | break; | |
3924 | case DP_TEST_LINK_VIDEO_PATTERN: | |
3925 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); | |
3926 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; | |
3927 | response = intel_dp_autotest_video_pattern(intel_dp); | |
3928 | break; | |
3929 | case DP_TEST_LINK_EDID_READ: | |
3930 | DRM_DEBUG_KMS("EDID test requested\n"); | |
3931 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; | |
3932 | response = intel_dp_autotest_edid(intel_dp); | |
3933 | break; | |
3934 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
3935 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); | |
3936 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; | |
3937 | response = intel_dp_autotest_phy_pattern(intel_dp); | |
3938 | break; | |
3939 | default: | |
3940 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); | |
3941 | break; | |
3942 | } | |
3943 | ||
3944 | update_status: | |
3945 | status = drm_dp_dpcd_write(&intel_dp->aux, | |
3946 | DP_TEST_RESPONSE, | |
3947 | &response, 1); | |
3948 | if (status <= 0) | |
3949 | DRM_DEBUG_KMS("Could not write test response to sink\n"); | |
a60f0e38 JB |
3950 | } |
3951 | ||
0e32b39c DA |
3952 | static int |
3953 | intel_dp_check_mst_status(struct intel_dp *intel_dp) | |
3954 | { | |
3955 | bool bret; | |
3956 | ||
3957 | if (intel_dp->is_mst) { | |
3958 | u8 esi[16] = { 0 }; | |
3959 | int ret = 0; | |
3960 | int retry; | |
3961 | bool handled; | |
3962 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
3963 | go_again: | |
3964 | if (bret == true) { | |
3965 | ||
3966 | /* check link status - esi[10] = 0x200c */ | |
19e0b4ca | 3967 | if (intel_dp->active_mst_links && |
901c2daf | 3968 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
0e32b39c DA |
3969 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
3970 | intel_dp_start_link_train(intel_dp); | |
0e32b39c DA |
3971 | intel_dp_stop_link_train(intel_dp); |
3972 | } | |
3973 | ||
6f34cc39 | 3974 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
0e32b39c DA |
3975 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
3976 | ||
3977 | if (handled) { | |
3978 | for (retry = 0; retry < 3; retry++) { | |
3979 | int wret; | |
3980 | wret = drm_dp_dpcd_write(&intel_dp->aux, | |
3981 | DP_SINK_COUNT_ESI+1, | |
3982 | &esi[1], 3); | |
3983 | if (wret == 3) { | |
3984 | break; | |
3985 | } | |
3986 | } | |
3987 | ||
3988 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
3989 | if (bret == true) { | |
6f34cc39 | 3990 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
0e32b39c DA |
3991 | goto go_again; |
3992 | } | |
3993 | } else | |
3994 | ret = 0; | |
3995 | ||
3996 | return ret; | |
3997 | } else { | |
3998 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3999 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); | |
4000 | intel_dp->is_mst = false; | |
4001 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
4002 | /* send a hotplug event */ | |
4003 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); | |
4004 | } | |
4005 | } | |
4006 | return -EINVAL; | |
4007 | } | |
4008 | ||
bfd02b3c VS |
4009 | static void |
4010 | intel_dp_retrain_link(struct intel_dp *intel_dp) | |
4011 | { | |
4012 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; | |
4013 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
4014 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
4015 | ||
4016 | /* Suppress underruns caused by re-training */ | |
4017 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); | |
4018 | if (crtc->config->has_pch_encoder) | |
4019 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
4020 | intel_crtc_pch_transcoder(crtc), false); | |
4021 | ||
4022 | intel_dp_start_link_train(intel_dp); | |
4023 | intel_dp_stop_link_train(intel_dp); | |
4024 | ||
4025 | /* Keep underrun reporting disabled until things are stable */ | |
0f0f74bc | 4026 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
bfd02b3c VS |
4027 | |
4028 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); | |
4029 | if (crtc->config->has_pch_encoder) | |
4030 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
4031 | intel_crtc_pch_transcoder(crtc), true); | |
4032 | } | |
4033 | ||
5c9114d0 SS |
4034 | static void |
4035 | intel_dp_check_link_status(struct intel_dp *intel_dp) | |
4036 | { | |
4037 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; | |
4038 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
4039 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
4040 | ||
4041 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
4042 | ||
4043 | if (!intel_dp_get_link_status(intel_dp, link_status)) { | |
4044 | DRM_ERROR("Failed to get link status\n"); | |
4045 | return; | |
4046 | } | |
4047 | ||
4048 | if (!intel_encoder->base.crtc) | |
4049 | return; | |
4050 | ||
4051 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) | |
4052 | return; | |
4053 | ||
d4cb3fd9 MA |
4054 | /* FIXME: we need to synchronize this sort of stuff with hardware |
4055 | * readout */ | |
4056 | if (WARN_ON_ONCE(!intel_dp->lane_count)) | |
4057 | return; | |
4058 | ||
5c9114d0 SS |
4059 | /* if link training is requested we should perform it always */ |
4060 | if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || | |
4061 | (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { | |
4062 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", | |
4063 | intel_encoder->base.name); | |
bfd02b3c VS |
4064 | |
4065 | intel_dp_retrain_link(intel_dp); | |
5c9114d0 SS |
4066 | } |
4067 | } | |
4068 | ||
a4fc5ed6 KP |
4069 | /* |
4070 | * According to DP spec | |
4071 | * 5.1.2: | |
4072 | * 1. Read DPCD | |
4073 | * 2. Configure link according to Receiver Capabilities | |
4074 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
4075 | * 4. Check link status on receipt of hot-plug interrupt | |
39ff747b SS |
4076 | * |
4077 | * intel_dp_short_pulse - handles short pulse interrupts | |
4078 | * when full detection is not required. | |
4079 | * Returns %true if short pulse is handled and full detection | |
4080 | * is NOT required and %false otherwise. | |
a4fc5ed6 | 4081 | */ |
39ff747b | 4082 | static bool |
5c9114d0 | 4083 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
a4fc5ed6 | 4084 | { |
5b215bcf | 4085 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
65fbb4e7 | 4086 | u8 sink_irq_vector = 0; |
39ff747b SS |
4087 | u8 old_sink_count = intel_dp->sink_count; |
4088 | bool ret; | |
5b215bcf | 4089 | |
4df6960e SS |
4090 | /* |
4091 | * Clearing compliance test variables to allow capturing | |
4092 | * of values for next automated test request. | |
4093 | */ | |
4094 | intel_dp->compliance_test_active = 0; | |
4095 | intel_dp->compliance_test_type = 0; | |
4096 | intel_dp->compliance_test_data = 0; | |
4097 | ||
39ff747b SS |
4098 | /* |
4099 | * Now read the DPCD to see if it's actually running | |
4100 | * If the current value of sink count doesn't match with | |
4101 | * the value that was stored earlier or dpcd read failed | |
4102 | * we need to do full detection | |
4103 | */ | |
4104 | ret = intel_dp_get_dpcd(intel_dp); | |
4105 | ||
4106 | if ((old_sink_count != intel_dp->sink_count) || !ret) { | |
4107 | /* No need to proceed if we are going to do full detect */ | |
4108 | return false; | |
59cd09e1 JB |
4109 | } |
4110 | ||
a60f0e38 JB |
4111 | /* Try to read the source of the interrupt */ |
4112 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
4113 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
4114 | sink_irq_vector != 0) { | |
a60f0e38 | 4115 | /* Clear interrupt source */ |
9d1a1031 JN |
4116 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4117 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4118 | sink_irq_vector); | |
a60f0e38 JB |
4119 | |
4120 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
09b1eb13 | 4121 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
a60f0e38 JB |
4122 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4123 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4124 | } | |
4125 | ||
5c9114d0 SS |
4126 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
4127 | intel_dp_check_link_status(intel_dp); | |
4128 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
39ff747b SS |
4129 | |
4130 | return true; | |
a4fc5ed6 | 4131 | } |
a4fc5ed6 | 4132 | |
caf9ab24 | 4133 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 4134 | static enum drm_connector_status |
26d61aad | 4135 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 4136 | { |
caf9ab24 | 4137 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
4138 | uint8_t type; |
4139 | ||
4140 | if (!intel_dp_get_dpcd(intel_dp)) | |
4141 | return connector_status_disconnected; | |
4142 | ||
1034ce70 SS |
4143 | if (is_edp(intel_dp)) |
4144 | return connector_status_connected; | |
4145 | ||
caf9ab24 | 4146 | /* if there's no downstream port, we're done */ |
c726ad01 | 4147 | if (!drm_dp_is_branch(dpcd)) |
26d61aad | 4148 | return connector_status_connected; |
caf9ab24 AJ |
4149 | |
4150 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
4151 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4152 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
9d1a1031 | 4153 | |
30d9aa42 SS |
4154 | return intel_dp->sink_count ? |
4155 | connector_status_connected : connector_status_disconnected; | |
caf9ab24 AJ |
4156 | } |
4157 | ||
c4e3170a VS |
4158 | if (intel_dp_can_mst(intel_dp)) |
4159 | return connector_status_connected; | |
4160 | ||
caf9ab24 | 4161 | /* If no HPD, poke DDC gently */ |
0b99836f | 4162 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 4163 | return connector_status_connected; |
caf9ab24 AJ |
4164 | |
4165 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
4166 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4167 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
4168 | if (type == DP_DS_PORT_TYPE_VGA || | |
4169 | type == DP_DS_PORT_TYPE_NON_EDID) | |
4170 | return connector_status_unknown; | |
4171 | } else { | |
4172 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
4173 | DP_DWN_STRM_PORT_TYPE_MASK; | |
4174 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
4175 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
4176 | return connector_status_unknown; | |
4177 | } | |
caf9ab24 AJ |
4178 | |
4179 | /* Anything else is out of spec, warn and ignore */ | |
4180 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 4181 | return connector_status_disconnected; |
71ba9000 AJ |
4182 | } |
4183 | ||
d410b56d CW |
4184 | static enum drm_connector_status |
4185 | edp_detect(struct intel_dp *intel_dp) | |
4186 | { | |
4187 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
4188 | enum drm_connector_status status; | |
4189 | ||
4190 | status = intel_panel_detect(dev); | |
4191 | if (status == connector_status_unknown) | |
4192 | status = connector_status_connected; | |
4193 | ||
4194 | return status; | |
4195 | } | |
4196 | ||
b93433cc JN |
4197 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
4198 | struct intel_digital_port *port) | |
5eb08b69 | 4199 | { |
b93433cc | 4200 | u32 bit; |
01cb9ea6 | 4201 | |
0df53b77 JN |
4202 | switch (port->port) { |
4203 | case PORT_A: | |
4204 | return true; | |
4205 | case PORT_B: | |
4206 | bit = SDE_PORTB_HOTPLUG; | |
4207 | break; | |
4208 | case PORT_C: | |
4209 | bit = SDE_PORTC_HOTPLUG; | |
4210 | break; | |
4211 | case PORT_D: | |
4212 | bit = SDE_PORTD_HOTPLUG; | |
4213 | break; | |
4214 | default: | |
4215 | MISSING_CASE(port->port); | |
4216 | return false; | |
4217 | } | |
4218 | ||
4219 | return I915_READ(SDEISR) & bit; | |
4220 | } | |
4221 | ||
4222 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, | |
4223 | struct intel_digital_port *port) | |
4224 | { | |
4225 | u32 bit; | |
4226 | ||
4227 | switch (port->port) { | |
4228 | case PORT_A: | |
4229 | return true; | |
4230 | case PORT_B: | |
4231 | bit = SDE_PORTB_HOTPLUG_CPT; | |
4232 | break; | |
4233 | case PORT_C: | |
4234 | bit = SDE_PORTC_HOTPLUG_CPT; | |
4235 | break; | |
4236 | case PORT_D: | |
4237 | bit = SDE_PORTD_HOTPLUG_CPT; | |
4238 | break; | |
a78695d3 JN |
4239 | case PORT_E: |
4240 | bit = SDE_PORTE_HOTPLUG_SPT; | |
4241 | break; | |
0df53b77 JN |
4242 | default: |
4243 | MISSING_CASE(port->port); | |
4244 | return false; | |
b93433cc | 4245 | } |
1b469639 | 4246 | |
b93433cc | 4247 | return I915_READ(SDEISR) & bit; |
5eb08b69 ZW |
4248 | } |
4249 | ||
7e66bcf2 | 4250 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
1d245987 | 4251 | struct intel_digital_port *port) |
a4fc5ed6 | 4252 | { |
9642c81c | 4253 | u32 bit; |
5eb08b69 | 4254 | |
9642c81c JN |
4255 | switch (port->port) { |
4256 | case PORT_B: | |
4257 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; | |
4258 | break; | |
4259 | case PORT_C: | |
4260 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; | |
4261 | break; | |
4262 | case PORT_D: | |
4263 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | |
4264 | break; | |
4265 | default: | |
4266 | MISSING_CASE(port->port); | |
4267 | return false; | |
4268 | } | |
4269 | ||
4270 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
4271 | } | |
4272 | ||
0780cd36 VS |
4273 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
4274 | struct intel_digital_port *port) | |
9642c81c JN |
4275 | { |
4276 | u32 bit; | |
4277 | ||
4278 | switch (port->port) { | |
4279 | case PORT_B: | |
0780cd36 | 4280 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4281 | break; |
4282 | case PORT_C: | |
0780cd36 | 4283 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4284 | break; |
4285 | case PORT_D: | |
0780cd36 | 4286 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4287 | break; |
4288 | default: | |
4289 | MISSING_CASE(port->port); | |
4290 | return false; | |
a4fc5ed6 KP |
4291 | } |
4292 | ||
1d245987 | 4293 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
2a592bec DA |
4294 | } |
4295 | ||
e464bfde | 4296 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
e2ec35a5 | 4297 | struct intel_digital_port *intel_dig_port) |
e464bfde | 4298 | { |
e2ec35a5 SJ |
4299 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4300 | enum port port; | |
e464bfde JN |
4301 | u32 bit; |
4302 | ||
e2ec35a5 SJ |
4303 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
4304 | switch (port) { | |
e464bfde JN |
4305 | case PORT_A: |
4306 | bit = BXT_DE_PORT_HP_DDIA; | |
4307 | break; | |
4308 | case PORT_B: | |
4309 | bit = BXT_DE_PORT_HP_DDIB; | |
4310 | break; | |
4311 | case PORT_C: | |
4312 | bit = BXT_DE_PORT_HP_DDIC; | |
4313 | break; | |
4314 | default: | |
e2ec35a5 | 4315 | MISSING_CASE(port); |
e464bfde JN |
4316 | return false; |
4317 | } | |
4318 | ||
4319 | return I915_READ(GEN8_DE_PORT_ISR) & bit; | |
4320 | } | |
4321 | ||
7e66bcf2 JN |
4322 | /* |
4323 | * intel_digital_port_connected - is the specified port connected? | |
4324 | * @dev_priv: i915 private structure | |
4325 | * @port: the port to test | |
4326 | * | |
4327 | * Return %true if @port is connected, %false otherwise. | |
4328 | */ | |
23f889bd | 4329 | static bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
7e66bcf2 JN |
4330 | struct intel_digital_port *port) |
4331 | { | |
0df53b77 | 4332 | if (HAS_PCH_IBX(dev_priv)) |
7e66bcf2 | 4333 | return ibx_digital_port_connected(dev_priv, port); |
22824fac | 4334 | else if (HAS_PCH_SPLIT(dev_priv)) |
0df53b77 | 4335 | return cpt_digital_port_connected(dev_priv, port); |
cc3f90f0 | 4336 | else if (IS_GEN9_LP(dev_priv)) |
e464bfde | 4337 | return bxt_digital_port_connected(dev_priv, port); |
0780cd36 VS |
4338 | else if (IS_GM45(dev_priv)) |
4339 | return gm45_digital_port_connected(dev_priv, port); | |
7e66bcf2 JN |
4340 | else |
4341 | return g4x_digital_port_connected(dev_priv, port); | |
4342 | } | |
4343 | ||
8c241fef | 4344 | static struct edid * |
beb60608 | 4345 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 4346 | { |
beb60608 | 4347 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
d6f24d0f | 4348 | |
9cd300e0 JN |
4349 | /* use cached edid if we have one */ |
4350 | if (intel_connector->edid) { | |
9cd300e0 JN |
4351 | /* invalid edid */ |
4352 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
4353 | return NULL; |
4354 | ||
55e9edeb | 4355 | return drm_edid_duplicate(intel_connector->edid); |
beb60608 CW |
4356 | } else |
4357 | return drm_get_edid(&intel_connector->base, | |
4358 | &intel_dp->aux.ddc); | |
4359 | } | |
8c241fef | 4360 | |
beb60608 CW |
4361 | static void |
4362 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
4363 | { | |
4364 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
4365 | struct edid *edid; | |
8c241fef | 4366 | |
f21a2198 | 4367 | intel_dp_unset_edid(intel_dp); |
beb60608 CW |
4368 | edid = intel_dp_get_edid(intel_dp); |
4369 | intel_connector->detect_edid = edid; | |
4370 | ||
4371 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) | |
4372 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; | |
4373 | else | |
4374 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
8c241fef KP |
4375 | } |
4376 | ||
beb60608 CW |
4377 | static void |
4378 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 4379 | { |
beb60608 | 4380 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8c241fef | 4381 | |
beb60608 CW |
4382 | kfree(intel_connector->detect_edid); |
4383 | intel_connector->detect_edid = NULL; | |
9cd300e0 | 4384 | |
beb60608 CW |
4385 | intel_dp->has_audio = false; |
4386 | } | |
d6f24d0f | 4387 | |
5cb651a7 | 4388 | static enum drm_connector_status |
f21a2198 | 4389 | intel_dp_long_pulse(struct intel_connector *intel_connector) |
a9756bb5 | 4390 | { |
f21a2198 | 4391 | struct drm_connector *connector = &intel_connector->base; |
a9756bb5 | 4392 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
d63885da PZ |
4393 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4394 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 4395 | struct drm_device *dev = connector->dev; |
a9756bb5 | 4396 | enum drm_connector_status status; |
671dedd2 | 4397 | enum intel_display_power_domain power_domain; |
65fbb4e7 | 4398 | u8 sink_irq_vector = 0; |
a9756bb5 | 4399 | |
25f78f58 VS |
4400 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4401 | intel_display_power_get(to_i915(dev), power_domain); | |
a9756bb5 | 4402 | |
d410b56d CW |
4403 | /* Can't disconnect eDP, but you can close the lid... */ |
4404 | if (is_edp(intel_dp)) | |
4405 | status = edp_detect(intel_dp); | |
c555a81d ACO |
4406 | else if (intel_digital_port_connected(to_i915(dev), |
4407 | dp_to_dig_port(intel_dp))) | |
4408 | status = intel_dp_detect_dpcd(intel_dp); | |
a9756bb5 | 4409 | else |
c555a81d ACO |
4410 | status = connector_status_disconnected; |
4411 | ||
5cb651a7 | 4412 | if (status == connector_status_disconnected) { |
4df6960e SS |
4413 | intel_dp->compliance_test_active = 0; |
4414 | intel_dp->compliance_test_type = 0; | |
4415 | intel_dp->compliance_test_data = 0; | |
4416 | ||
0e505a08 | 4417 | if (intel_dp->is_mst) { |
4418 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4419 | intel_dp->is_mst, | |
4420 | intel_dp->mst_mgr.mst_state); | |
4421 | intel_dp->is_mst = false; | |
4422 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4423 | intel_dp->is_mst); | |
4424 | } | |
4425 | ||
c8c8fb33 | 4426 | goto out; |
4df6960e | 4427 | } |
a9756bb5 | 4428 | |
f21a2198 | 4429 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
cca0502b | 4430 | intel_encoder->type = INTEL_OUTPUT_DP; |
f21a2198 | 4431 | |
fe5a66f9 VS |
4432 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
4433 | yesno(intel_dp_source_supports_hbr2(intel_dp)), | |
4434 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); | |
4435 | ||
f482984a MN |
4436 | /* Set the max lane count for sink */ |
4437 | intel_dp->max_sink_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); | |
4438 | ||
4439 | /* Set the max link BW for sink */ | |
4440 | intel_dp->max_sink_link_bw = intel_dp_max_link_bw(intel_dp); | |
4441 | ||
fe5a66f9 VS |
4442 | intel_dp_print_rates(intel_dp); |
4443 | ||
7b3fc170 | 4444 | intel_dp_read_desc(intel_dp); |
0e390a33 | 4445 | |
c4e3170a VS |
4446 | intel_dp_configure_mst(intel_dp); |
4447 | ||
4448 | if (intel_dp->is_mst) { | |
f21a2198 SS |
4449 | /* |
4450 | * If we are in MST mode then this connector | |
4451 | * won't appear connected or have anything | |
4452 | * with EDID on it | |
4453 | */ | |
0e32b39c DA |
4454 | status = connector_status_disconnected; |
4455 | goto out; | |
7d23e3c3 SS |
4456 | } else if (connector->status == connector_status_connected) { |
4457 | /* | |
4458 | * If display was connected already and is still connected | |
4459 | * check links status, there has been known issues of | |
4460 | * link loss triggerring long pulse!!!! | |
4461 | */ | |
4462 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); | |
4463 | intel_dp_check_link_status(intel_dp); | |
4464 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
4465 | goto out; | |
0e32b39c DA |
4466 | } |
4467 | ||
4df6960e SS |
4468 | /* |
4469 | * Clearing NACK and defer counts to get their exact values | |
4470 | * while reading EDID which are required by Compliance tests | |
4471 | * 4.2.2.4 and 4.2.2.5 | |
4472 | */ | |
4473 | intel_dp->aux.i2c_nack_count = 0; | |
4474 | intel_dp->aux.i2c_defer_count = 0; | |
4475 | ||
beb60608 | 4476 | intel_dp_set_edid(intel_dp); |
5cb651a7 VS |
4477 | if (is_edp(intel_dp) || intel_connector->detect_edid) |
4478 | status = connector_status_connected; | |
7d23e3c3 | 4479 | intel_dp->detect_done = true; |
c8c8fb33 | 4480 | |
09b1eb13 TP |
4481 | /* Try to read the source of the interrupt */ |
4482 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
4483 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
4484 | sink_irq_vector != 0) { | |
09b1eb13 TP |
4485 | /* Clear interrupt source */ |
4486 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
4487 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4488 | sink_irq_vector); | |
4489 | ||
4490 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
4491 | intel_dp_handle_test_request(intel_dp); | |
4492 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
4493 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4494 | } | |
4495 | ||
c8c8fb33 | 4496 | out: |
5cb651a7 | 4497 | if (status != connector_status_connected && !intel_dp->is_mst) |
f21a2198 | 4498 | intel_dp_unset_edid(intel_dp); |
7d23e3c3 | 4499 | |
25f78f58 | 4500 | intel_display_power_put(to_i915(dev), power_domain); |
5cb651a7 | 4501 | return status; |
f21a2198 SS |
4502 | } |
4503 | ||
4504 | static enum drm_connector_status | |
4505 | intel_dp_detect(struct drm_connector *connector, bool force) | |
4506 | { | |
4507 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
5cb651a7 | 4508 | enum drm_connector_status status = connector->status; |
f21a2198 SS |
4509 | |
4510 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4511 | connector->base.id, connector->name); | |
4512 | ||
7d23e3c3 SS |
4513 | /* If full detect is not performed yet, do a full detect */ |
4514 | if (!intel_dp->detect_done) | |
5cb651a7 | 4515 | status = intel_dp_long_pulse(intel_dp->attached_connector); |
7d23e3c3 SS |
4516 | |
4517 | intel_dp->detect_done = false; | |
f21a2198 | 4518 | |
5cb651a7 | 4519 | return status; |
a4fc5ed6 KP |
4520 | } |
4521 | ||
beb60608 CW |
4522 | static void |
4523 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 4524 | { |
df0e9248 | 4525 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
beb60608 | 4526 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
25f78f58 | 4527 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
671dedd2 | 4528 | enum intel_display_power_domain power_domain; |
a4fc5ed6 | 4529 | |
beb60608 CW |
4530 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4531 | connector->base.id, connector->name); | |
4532 | intel_dp_unset_edid(intel_dp); | |
a4fc5ed6 | 4533 | |
beb60608 CW |
4534 | if (connector->status != connector_status_connected) |
4535 | return; | |
671dedd2 | 4536 | |
25f78f58 VS |
4537 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4538 | intel_display_power_get(dev_priv, power_domain); | |
beb60608 CW |
4539 | |
4540 | intel_dp_set_edid(intel_dp); | |
4541 | ||
25f78f58 | 4542 | intel_display_power_put(dev_priv, power_domain); |
beb60608 CW |
4543 | |
4544 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
cca0502b | 4545 | intel_encoder->type = INTEL_OUTPUT_DP; |
beb60608 CW |
4546 | } |
4547 | ||
4548 | static int intel_dp_get_modes(struct drm_connector *connector) | |
4549 | { | |
4550 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4551 | struct edid *edid; | |
4552 | ||
4553 | edid = intel_connector->detect_edid; | |
4554 | if (edid) { | |
4555 | int ret = intel_connector_update_modes(connector, edid); | |
4556 | if (ret) | |
4557 | return ret; | |
4558 | } | |
32f9d658 | 4559 | |
f8779fda | 4560 | /* if eDP has no EDID, fall back to fixed mode */ |
beb60608 CW |
4561 | if (is_edp(intel_attached_dp(connector)) && |
4562 | intel_connector->panel.fixed_mode) { | |
f8779fda | 4563 | struct drm_display_mode *mode; |
beb60608 CW |
4564 | |
4565 | mode = drm_mode_duplicate(connector->dev, | |
dd06f90e | 4566 | intel_connector->panel.fixed_mode); |
f8779fda | 4567 | if (mode) { |
32f9d658 ZW |
4568 | drm_mode_probed_add(connector, mode); |
4569 | return 1; | |
4570 | } | |
4571 | } | |
beb60608 | 4572 | |
32f9d658 | 4573 | return 0; |
a4fc5ed6 KP |
4574 | } |
4575 | ||
1aad7ac0 CW |
4576 | static bool |
4577 | intel_dp_detect_audio(struct drm_connector *connector) | |
4578 | { | |
1aad7ac0 | 4579 | bool has_audio = false; |
beb60608 | 4580 | struct edid *edid; |
1aad7ac0 | 4581 | |
beb60608 CW |
4582 | edid = to_intel_connector(connector)->detect_edid; |
4583 | if (edid) | |
1aad7ac0 | 4584 | has_audio = drm_detect_monitor_audio(edid); |
671dedd2 | 4585 | |
1aad7ac0 CW |
4586 | return has_audio; |
4587 | } | |
4588 | ||
f684960e CW |
4589 | static int |
4590 | intel_dp_set_property(struct drm_connector *connector, | |
4591 | struct drm_property *property, | |
4592 | uint64_t val) | |
4593 | { | |
fac5e23e | 4594 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
53b41837 | 4595 | struct intel_connector *intel_connector = to_intel_connector(connector); |
da63a9f2 PZ |
4596 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
4597 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
f684960e CW |
4598 | int ret; |
4599 | ||
662595df | 4600 | ret = drm_object_property_set_value(&connector->base, property, val); |
f684960e CW |
4601 | if (ret) |
4602 | return ret; | |
4603 | ||
3f43c48d | 4604 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
4605 | int i = val; |
4606 | bool has_audio; | |
4607 | ||
4608 | if (i == intel_dp->force_audio) | |
f684960e CW |
4609 | return 0; |
4610 | ||
1aad7ac0 | 4611 | intel_dp->force_audio = i; |
f684960e | 4612 | |
c3e5f67b | 4613 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
4614 | has_audio = intel_dp_detect_audio(connector); |
4615 | else | |
c3e5f67b | 4616 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
4617 | |
4618 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
4619 | return 0; |
4620 | ||
1aad7ac0 | 4621 | intel_dp->has_audio = has_audio; |
f684960e CW |
4622 | goto done; |
4623 | } | |
4624 | ||
e953fd7b | 4625 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 | 4626 | bool old_auto = intel_dp->color_range_auto; |
0f2a2a75 | 4627 | bool old_range = intel_dp->limited_color_range; |
ae4edb80 | 4628 | |
55bc60db VS |
4629 | switch (val) { |
4630 | case INTEL_BROADCAST_RGB_AUTO: | |
4631 | intel_dp->color_range_auto = true; | |
4632 | break; | |
4633 | case INTEL_BROADCAST_RGB_FULL: | |
4634 | intel_dp->color_range_auto = false; | |
0f2a2a75 | 4635 | intel_dp->limited_color_range = false; |
55bc60db VS |
4636 | break; |
4637 | case INTEL_BROADCAST_RGB_LIMITED: | |
4638 | intel_dp->color_range_auto = false; | |
0f2a2a75 | 4639 | intel_dp->limited_color_range = true; |
55bc60db VS |
4640 | break; |
4641 | default: | |
4642 | return -EINVAL; | |
4643 | } | |
ae4edb80 DV |
4644 | |
4645 | if (old_auto == intel_dp->color_range_auto && | |
0f2a2a75 | 4646 | old_range == intel_dp->limited_color_range) |
ae4edb80 DV |
4647 | return 0; |
4648 | ||
e953fd7b CW |
4649 | goto done; |
4650 | } | |
4651 | ||
53b41837 YN |
4652 | if (is_edp(intel_dp) && |
4653 | property == connector->dev->mode_config.scaling_mode_property) { | |
4654 | if (val == DRM_MODE_SCALE_NONE) { | |
4655 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
4656 | return -EINVAL; | |
4657 | } | |
234126c6 VS |
4658 | if (HAS_GMCH_DISPLAY(dev_priv) && |
4659 | val == DRM_MODE_SCALE_CENTER) { | |
4660 | DRM_DEBUG_KMS("centering not supported\n"); | |
4661 | return -EINVAL; | |
4662 | } | |
53b41837 YN |
4663 | |
4664 | if (intel_connector->panel.fitting_mode == val) { | |
4665 | /* the eDP scaling property is not changed */ | |
4666 | return 0; | |
4667 | } | |
4668 | intel_connector->panel.fitting_mode = val; | |
4669 | ||
4670 | goto done; | |
4671 | } | |
4672 | ||
f684960e CW |
4673 | return -EINVAL; |
4674 | ||
4675 | done: | |
c0c36b94 CW |
4676 | if (intel_encoder->base.crtc) |
4677 | intel_crtc_restore_mode(intel_encoder->base.crtc); | |
f684960e CW |
4678 | |
4679 | return 0; | |
4680 | } | |
4681 | ||
7a418e34 CW |
4682 | static int |
4683 | intel_dp_connector_register(struct drm_connector *connector) | |
4684 | { | |
4685 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1ebaa0b9 CW |
4686 | int ret; |
4687 | ||
4688 | ret = intel_connector_register(connector); | |
4689 | if (ret) | |
4690 | return ret; | |
7a418e34 CW |
4691 | |
4692 | i915_debugfs_connector_add(connector); | |
4693 | ||
4694 | DRM_DEBUG_KMS("registering %s bus for %s\n", | |
4695 | intel_dp->aux.name, connector->kdev->kobj.name); | |
4696 | ||
4697 | intel_dp->aux.dev = connector->kdev; | |
4698 | return drm_dp_aux_register(&intel_dp->aux); | |
4699 | } | |
4700 | ||
c191eca1 CW |
4701 | static void |
4702 | intel_dp_connector_unregister(struct drm_connector *connector) | |
4703 | { | |
4704 | drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); | |
4705 | intel_connector_unregister(connector); | |
4706 | } | |
4707 | ||
a4fc5ed6 | 4708 | static void |
73845adf | 4709 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 4710 | { |
1d508706 | 4711 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 4712 | |
10e972d3 | 4713 | kfree(intel_connector->detect_edid); |
beb60608 | 4714 | |
9cd300e0 JN |
4715 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4716 | kfree(intel_connector->edid); | |
4717 | ||
acd8db10 PZ |
4718 | /* Can't call is_edp() since the encoder may have been destroyed |
4719 | * already. */ | |
4720 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
1d508706 | 4721 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 4722 | |
a4fc5ed6 | 4723 | drm_connector_cleanup(connector); |
55f78c43 | 4724 | kfree(connector); |
a4fc5ed6 KP |
4725 | } |
4726 | ||
00c09d70 | 4727 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 4728 | { |
da63a9f2 PZ |
4729 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4730 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
24d05927 | 4731 | |
0e32b39c | 4732 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
bd943159 KP |
4733 | if (is_edp(intel_dp)) { |
4734 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
951468f3 VS |
4735 | /* |
4736 | * vdd might still be enabled do to the delayed vdd off. | |
4737 | * Make sure vdd is actually turned off here. | |
4738 | */ | |
773538e8 | 4739 | pps_lock(intel_dp); |
4be73780 | 4740 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 VS |
4741 | pps_unlock(intel_dp); |
4742 | ||
01527b31 CT |
4743 | if (intel_dp->edp_notifier.notifier_call) { |
4744 | unregister_reboot_notifier(&intel_dp->edp_notifier); | |
4745 | intel_dp->edp_notifier.notifier_call = NULL; | |
4746 | } | |
bd943159 | 4747 | } |
99681886 CW |
4748 | |
4749 | intel_dp_aux_fini(intel_dp); | |
4750 | ||
c8bd0e49 | 4751 | drm_encoder_cleanup(encoder); |
da63a9f2 | 4752 | kfree(intel_dig_port); |
24d05927 DV |
4753 | } |
4754 | ||
bf93ba67 | 4755 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
07f9cd0b ID |
4756 | { |
4757 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
4758 | ||
4759 | if (!is_edp(intel_dp)) | |
4760 | return; | |
4761 | ||
951468f3 VS |
4762 | /* |
4763 | * vdd might still be enabled do to the delayed vdd off. | |
4764 | * Make sure vdd is actually turned off here. | |
4765 | */ | |
afa4e53a | 4766 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
773538e8 | 4767 | pps_lock(intel_dp); |
07f9cd0b | 4768 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 | 4769 | pps_unlock(intel_dp); |
07f9cd0b ID |
4770 | } |
4771 | ||
49e6bc51 VS |
4772 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
4773 | { | |
4774 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4775 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 4776 | struct drm_i915_private *dev_priv = to_i915(dev); |
49e6bc51 VS |
4777 | enum intel_display_power_domain power_domain; |
4778 | ||
4779 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4780 | ||
4781 | if (!edp_have_panel_vdd(intel_dp)) | |
4782 | return; | |
4783 | ||
4784 | /* | |
4785 | * The VDD bit needs a power domain reference, so if the bit is | |
4786 | * already enabled when we boot or resume, grab this reference and | |
4787 | * schedule a vdd off, so we don't hold on to the reference | |
4788 | * indefinitely. | |
4789 | */ | |
4790 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); | |
25f78f58 | 4791 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
49e6bc51 VS |
4792 | intel_display_power_get(dev_priv, power_domain); |
4793 | ||
4794 | edp_panel_vdd_schedule_off(intel_dp); | |
4795 | } | |
4796 | ||
bf93ba67 | 4797 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
6d93c0c4 | 4798 | { |
64989ca4 | 4799 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
dd75f6dd ID |
4800 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4801 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); | |
64989ca4 VS |
4802 | |
4803 | if (!HAS_DDI(dev_priv)) | |
4804 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
49e6bc51 | 4805 | |
dd75f6dd | 4806 | if (lspcon->active) |
910530c0 SS |
4807 | lspcon_resume(lspcon); |
4808 | ||
49e6bc51 VS |
4809 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) |
4810 | return; | |
4811 | ||
49e6bc51 VS |
4812 | pps_lock(intel_dp); |
4813 | ||
335f752b ID |
4814 | /* Reinit the power sequencer, in case BIOS did something with it. */ |
4815 | intel_dp_pps_init(encoder->dev, intel_dp); | |
49e6bc51 VS |
4816 | intel_edp_panel_vdd_sanitize(intel_dp); |
4817 | ||
4818 | pps_unlock(intel_dp); | |
6d93c0c4 ID |
4819 | } |
4820 | ||
a4fc5ed6 | 4821 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
4d688a2a | 4822 | .dpms = drm_atomic_helper_connector_dpms, |
a4fc5ed6 | 4823 | .detect = intel_dp_detect, |
beb60608 | 4824 | .force = intel_dp_force, |
a4fc5ed6 | 4825 | .fill_modes = drm_helper_probe_single_connector_modes, |
f684960e | 4826 | .set_property = intel_dp_set_property, |
2545e4a6 | 4827 | .atomic_get_property = intel_connector_atomic_get_property, |
7a418e34 | 4828 | .late_register = intel_dp_connector_register, |
c191eca1 | 4829 | .early_unregister = intel_dp_connector_unregister, |
73845adf | 4830 | .destroy = intel_dp_connector_destroy, |
c6f95f27 | 4831 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 4832 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
a4fc5ed6 KP |
4833 | }; |
4834 | ||
4835 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
4836 | .get_modes = intel_dp_get_modes, | |
4837 | .mode_valid = intel_dp_mode_valid, | |
a4fc5ed6 KP |
4838 | }; |
4839 | ||
a4fc5ed6 | 4840 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
6d93c0c4 | 4841 | .reset = intel_dp_encoder_reset, |
24d05927 | 4842 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
4843 | }; |
4844 | ||
b2c5c181 | 4845 | enum irqreturn |
13cf5504 DA |
4846 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
4847 | { | |
4848 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1c767b33 | 4849 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
0e32b39c | 4850 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 4851 | struct drm_i915_private *dev_priv = to_i915(dev); |
1c767b33 | 4852 | enum intel_display_power_domain power_domain; |
b2c5c181 | 4853 | enum irqreturn ret = IRQ_NONE; |
1c767b33 | 4854 | |
2540058f TI |
4855 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
4856 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) | |
cca0502b | 4857 | intel_dig_port->base.type = INTEL_OUTPUT_DP; |
13cf5504 | 4858 | |
7a7f84cc VS |
4859 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
4860 | /* | |
4861 | * vdd off can generate a long pulse on eDP which | |
4862 | * would require vdd on to handle it, and thus we | |
4863 | * would end up in an endless cycle of | |
4864 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." | |
4865 | */ | |
4866 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", | |
4867 | port_name(intel_dig_port->port)); | |
a8b3d52f | 4868 | return IRQ_HANDLED; |
7a7f84cc VS |
4869 | } |
4870 | ||
26fbb774 VS |
4871 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
4872 | port_name(intel_dig_port->port), | |
0e32b39c | 4873 | long_hpd ? "long" : "short"); |
13cf5504 | 4874 | |
27d4efc5 VS |
4875 | if (long_hpd) { |
4876 | intel_dp->detect_done = false; | |
4877 | return IRQ_NONE; | |
4878 | } | |
4879 | ||
25f78f58 | 4880 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1c767b33 ID |
4881 | intel_display_power_get(dev_priv, power_domain); |
4882 | ||
27d4efc5 VS |
4883 | if (intel_dp->is_mst) { |
4884 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { | |
4885 | /* | |
4886 | * If we were in MST mode, and device is not | |
4887 | * there, get out of MST mode | |
4888 | */ | |
4889 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4890 | intel_dp->is_mst, intel_dp->mst_mgr.mst_state); | |
4891 | intel_dp->is_mst = false; | |
4892 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4893 | intel_dp->is_mst); | |
4894 | intel_dp->detect_done = false; | |
4895 | goto put_power; | |
0e32b39c | 4896 | } |
27d4efc5 | 4897 | } |
0e32b39c | 4898 | |
27d4efc5 VS |
4899 | if (!intel_dp->is_mst) { |
4900 | if (!intel_dp_short_pulse(intel_dp)) { | |
4901 | intel_dp->detect_done = false; | |
4902 | goto put_power; | |
39ff747b | 4903 | } |
0e32b39c | 4904 | } |
b2c5c181 DV |
4905 | |
4906 | ret = IRQ_HANDLED; | |
4907 | ||
1c767b33 ID |
4908 | put_power: |
4909 | intel_display_power_put(dev_priv, power_domain); | |
4910 | ||
4911 | return ret; | |
13cf5504 DA |
4912 | } |
4913 | ||
477ec328 | 4914 | /* check the VBT to see whether the eDP is on another port */ |
dd11bc10 | 4915 | bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port) |
36e83a18 | 4916 | { |
53ce81a7 VS |
4917 | /* |
4918 | * eDP not supported on g4x. so bail out early just | |
4919 | * for a bit extra safety in case the VBT is bonkers. | |
4920 | */ | |
dd11bc10 | 4921 | if (INTEL_GEN(dev_priv) < 5) |
53ce81a7 VS |
4922 | return false; |
4923 | ||
3b32a35b VS |
4924 | if (port == PORT_A) |
4925 | return true; | |
4926 | ||
951d9efe | 4927 | return intel_bios_is_port_edp(dev_priv, port); |
36e83a18 ZY |
4928 | } |
4929 | ||
0e32b39c | 4930 | void |
f684960e CW |
4931 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
4932 | { | |
53b41837 YN |
4933 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4934 | ||
3f43c48d | 4935 | intel_attach_force_audio_property(connector); |
e953fd7b | 4936 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 4937 | intel_dp->color_range_auto = true; |
53b41837 YN |
4938 | |
4939 | if (is_edp(intel_dp)) { | |
4940 | drm_mode_create_scaling_mode_property(connector->dev); | |
6de6d846 RC |
4941 | drm_object_attach_property( |
4942 | &connector->base, | |
53b41837 | 4943 | connector->dev->mode_config.scaling_mode_property, |
8e740cd1 YN |
4944 | DRM_MODE_SCALE_ASPECT); |
4945 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
53b41837 | 4946 | } |
f684960e CW |
4947 | } |
4948 | ||
dada1a9f ID |
4949 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
4950 | { | |
d28d4731 | 4951 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
dada1a9f ID |
4952 | intel_dp->last_power_on = jiffies; |
4953 | intel_dp->last_backlight_off = jiffies; | |
4954 | } | |
4955 | ||
67a54566 | 4956 | static void |
54648618 ID |
4957 | intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, |
4958 | struct intel_dp *intel_dp, struct edp_power_seq *seq) | |
67a54566 | 4959 | { |
b0a08bec | 4960 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
8e8232d5 | 4961 | struct pps_registers regs; |
453c5420 | 4962 | |
8e8232d5 | 4963 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
67a54566 DV |
4964 | |
4965 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
4966 | * the very first thing. */ | |
b0a08bec | 4967 | pp_ctl = ironlake_get_pp_control(intel_dp); |
67a54566 | 4968 | |
8e8232d5 ID |
4969 | pp_on = I915_READ(regs.pp_on); |
4970 | pp_off = I915_READ(regs.pp_off); | |
cc3f90f0 | 4971 | if (!IS_GEN9_LP(dev_priv)) { |
8e8232d5 ID |
4972 | I915_WRITE(regs.pp_ctrl, pp_ctl); |
4973 | pp_div = I915_READ(regs.pp_div); | |
b0a08bec | 4974 | } |
67a54566 DV |
4975 | |
4976 | /* Pull timing values out of registers */ | |
54648618 ID |
4977 | seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
4978 | PANEL_POWER_UP_DELAY_SHIFT; | |
67a54566 | 4979 | |
54648618 ID |
4980 | seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
4981 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
67a54566 | 4982 | |
54648618 ID |
4983 | seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
4984 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
67a54566 | 4985 | |
54648618 ID |
4986 | seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
4987 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
67a54566 | 4988 | |
cc3f90f0 | 4989 | if (IS_GEN9_LP(dev_priv)) { |
b0a08bec VK |
4990 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
4991 | BXT_POWER_CYCLE_DELAY_SHIFT; | |
4992 | if (tmp > 0) | |
54648618 | 4993 | seq->t11_t12 = (tmp - 1) * 1000; |
b0a08bec | 4994 | else |
54648618 | 4995 | seq->t11_t12 = 0; |
b0a08bec | 4996 | } else { |
54648618 | 4997 | seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
67a54566 | 4998 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
b0a08bec | 4999 | } |
54648618 ID |
5000 | } |
5001 | ||
de9c1b6b ID |
5002 | static void |
5003 | intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) | |
5004 | { | |
5005 | DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
5006 | state_name, | |
5007 | seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); | |
5008 | } | |
5009 | ||
5010 | static void | |
5011 | intel_pps_verify_state(struct drm_i915_private *dev_priv, | |
5012 | struct intel_dp *intel_dp) | |
5013 | { | |
5014 | struct edp_power_seq hw; | |
5015 | struct edp_power_seq *sw = &intel_dp->pps_delays; | |
5016 | ||
5017 | intel_pps_readout_hw_state(dev_priv, intel_dp, &hw); | |
5018 | ||
5019 | if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || | |
5020 | hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { | |
5021 | DRM_ERROR("PPS state mismatch\n"); | |
5022 | intel_pps_dump_state("sw", sw); | |
5023 | intel_pps_dump_state("hw", &hw); | |
5024 | } | |
5025 | } | |
5026 | ||
54648618 ID |
5027 | static void |
5028 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
5029 | struct intel_dp *intel_dp) | |
5030 | { | |
fac5e23e | 5031 | struct drm_i915_private *dev_priv = to_i915(dev); |
54648618 ID |
5032 | struct edp_power_seq cur, vbt, spec, |
5033 | *final = &intel_dp->pps_delays; | |
5034 | ||
5035 | lockdep_assert_held(&dev_priv->pps_mutex); | |
5036 | ||
5037 | /* already initialized? */ | |
5038 | if (final->t11_t12 != 0) | |
5039 | return; | |
5040 | ||
5041 | intel_pps_readout_hw_state(dev_priv, intel_dp, &cur); | |
67a54566 | 5042 | |
de9c1b6b | 5043 | intel_pps_dump_state("cur", &cur); |
67a54566 | 5044 | |
6aa23e65 | 5045 | vbt = dev_priv->vbt.edp.pps; |
67a54566 DV |
5046 | |
5047 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
5048 | * our hw here, which are all in 100usec. */ | |
5049 | spec.t1_t3 = 210 * 10; | |
5050 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
5051 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
5052 | spec.t10 = 500 * 10; | |
5053 | /* This one is special and actually in units of 100ms, but zero | |
5054 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
5055 | * table multiplies it with 1000 to make it in units of 100usec, | |
5056 | * too. */ | |
5057 | spec.t11_t12 = (510 + 100) * 10; | |
5058 | ||
de9c1b6b | 5059 | intel_pps_dump_state("vbt", &vbt); |
67a54566 DV |
5060 | |
5061 | /* Use the max of the register settings and vbt. If both are | |
5062 | * unset, fall back to the spec limits. */ | |
36b5f425 | 5063 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
67a54566 DV |
5064 | spec.field : \ |
5065 | max(cur.field, vbt.field)) | |
5066 | assign_final(t1_t3); | |
5067 | assign_final(t8); | |
5068 | assign_final(t9); | |
5069 | assign_final(t10); | |
5070 | assign_final(t11_t12); | |
5071 | #undef assign_final | |
5072 | ||
36b5f425 | 5073 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
67a54566 DV |
5074 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
5075 | intel_dp->backlight_on_delay = get_delay(t8); | |
5076 | intel_dp->backlight_off_delay = get_delay(t9); | |
5077 | intel_dp->panel_power_down_delay = get_delay(t10); | |
5078 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
5079 | #undef get_delay | |
5080 | ||
f30d26e4 JN |
5081 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
5082 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
5083 | intel_dp->panel_power_cycle_delay); | |
5084 | ||
5085 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
5086 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
de9c1b6b ID |
5087 | |
5088 | /* | |
5089 | * We override the HW backlight delays to 1 because we do manual waits | |
5090 | * on them. For T8, even BSpec recommends doing it. For T9, if we | |
5091 | * don't do this, we'll end up waiting for the backlight off delay | |
5092 | * twice: once when we do the manual sleep, and once when we disable | |
5093 | * the panel and wait for the PP_STATUS bit to become zero. | |
5094 | */ | |
5095 | final->t8 = 1; | |
5096 | final->t9 = 1; | |
f30d26e4 JN |
5097 | } |
5098 | ||
5099 | static void | |
5100 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
36b5f425 | 5101 | struct intel_dp *intel_dp) |
f30d26e4 | 5102 | { |
fac5e23e | 5103 | struct drm_i915_private *dev_priv = to_i915(dev); |
453c5420 | 5104 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
e7dc33f3 | 5105 | int div = dev_priv->rawclk_freq / 1000; |
8e8232d5 | 5106 | struct pps_registers regs; |
ad933b56 | 5107 | enum port port = dp_to_dig_port(intel_dp)->port; |
36b5f425 | 5108 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
453c5420 | 5109 | |
e39b999a | 5110 | lockdep_assert_held(&dev_priv->pps_mutex); |
453c5420 | 5111 | |
8e8232d5 | 5112 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
453c5420 | 5113 | |
f30d26e4 | 5114 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
de9c1b6b ID |
5115 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
5116 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 5117 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
5118 | /* Compute the divisor for the pp clock, simply match the Bspec |
5119 | * formula. */ | |
cc3f90f0 | 5120 | if (IS_GEN9_LP(dev_priv)) { |
8e8232d5 | 5121 | pp_div = I915_READ(regs.pp_ctrl); |
b0a08bec VK |
5122 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
5123 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) | |
5124 | << BXT_POWER_CYCLE_DELAY_SHIFT); | |
5125 | } else { | |
5126 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; | |
5127 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) | |
5128 | << PANEL_POWER_CYCLE_DELAY_SHIFT); | |
5129 | } | |
67a54566 DV |
5130 | |
5131 | /* Haswell doesn't have any port selection bits for the panel | |
5132 | * power sequencer any more. */ | |
920a14b2 | 5133 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
ad933b56 | 5134 | port_sel = PANEL_PORT_SELECT_VLV(port); |
6e266956 | 5135 | } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
ad933b56 | 5136 | if (port == PORT_A) |
a24c144c | 5137 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 5138 | else |
a24c144c | 5139 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
5140 | } |
5141 | ||
453c5420 JB |
5142 | pp_on |= port_sel; |
5143 | ||
8e8232d5 ID |
5144 | I915_WRITE(regs.pp_on, pp_on); |
5145 | I915_WRITE(regs.pp_off, pp_off); | |
cc3f90f0 | 5146 | if (IS_GEN9_LP(dev_priv)) |
8e8232d5 | 5147 | I915_WRITE(regs.pp_ctrl, pp_div); |
b0a08bec | 5148 | else |
8e8232d5 | 5149 | I915_WRITE(regs.pp_div, pp_div); |
67a54566 | 5150 | |
67a54566 | 5151 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
8e8232d5 ID |
5152 | I915_READ(regs.pp_on), |
5153 | I915_READ(regs.pp_off), | |
cc3f90f0 | 5154 | IS_GEN9_LP(dev_priv) ? |
8e8232d5 ID |
5155 | (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : |
5156 | I915_READ(regs.pp_div)); | |
f684960e CW |
5157 | } |
5158 | ||
335f752b ID |
5159 | static void intel_dp_pps_init(struct drm_device *dev, |
5160 | struct intel_dp *intel_dp) | |
5161 | { | |
920a14b2 TU |
5162 | struct drm_i915_private *dev_priv = to_i915(dev); |
5163 | ||
5164 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
335f752b ID |
5165 | vlv_initial_power_sequencer_setup(intel_dp); |
5166 | } else { | |
5167 | intel_dp_init_panel_power_sequencer(dev, intel_dp); | |
5168 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
5169 | } | |
5170 | } | |
5171 | ||
b33a2815 VK |
5172 | /** |
5173 | * intel_dp_set_drrs_state - program registers for RR switch to take effect | |
5423adf1 | 5174 | * @dev_priv: i915 device |
e896402c | 5175 | * @crtc_state: a pointer to the active intel_crtc_state |
b33a2815 VK |
5176 | * @refresh_rate: RR to be programmed |
5177 | * | |
5178 | * This function gets called when refresh rate (RR) has to be changed from | |
5179 | * one frequency to another. Switches can be between high and low RR | |
5180 | * supported by the panel or to any other RR based on media playback (in | |
5181 | * this case, RR value needs to be passed from user space). | |
5182 | * | |
5183 | * The caller of this function needs to take a lock on dev_priv->drrs. | |
5184 | */ | |
85cb48a1 ML |
5185 | static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, |
5186 | struct intel_crtc_state *crtc_state, | |
5187 | int refresh_rate) | |
439d7ac0 | 5188 | { |
439d7ac0 | 5189 | struct intel_encoder *encoder; |
96178eeb VK |
5190 | struct intel_digital_port *dig_port = NULL; |
5191 | struct intel_dp *intel_dp = dev_priv->drrs.dp; | |
85cb48a1 | 5192 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
96178eeb | 5193 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
439d7ac0 PB |
5194 | |
5195 | if (refresh_rate <= 0) { | |
5196 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); | |
5197 | return; | |
5198 | } | |
5199 | ||
96178eeb VK |
5200 | if (intel_dp == NULL) { |
5201 | DRM_DEBUG_KMS("DRRS not supported.\n"); | |
439d7ac0 PB |
5202 | return; |
5203 | } | |
5204 | ||
1fcc9d1c | 5205 | /* |
e4d59f6b RV |
5206 | * FIXME: This needs proper synchronization with psr state for some |
5207 | * platforms that cannot have PSR and DRRS enabled at the same time. | |
1fcc9d1c | 5208 | */ |
439d7ac0 | 5209 | |
96178eeb VK |
5210 | dig_port = dp_to_dig_port(intel_dp); |
5211 | encoder = &dig_port->base; | |
723f9aab | 5212 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
439d7ac0 PB |
5213 | |
5214 | if (!intel_crtc) { | |
5215 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); | |
5216 | return; | |
5217 | } | |
5218 | ||
96178eeb | 5219 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
439d7ac0 PB |
5220 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5221 | return; | |
5222 | } | |
5223 | ||
96178eeb VK |
5224 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5225 | refresh_rate) | |
439d7ac0 PB |
5226 | index = DRRS_LOW_RR; |
5227 | ||
96178eeb | 5228 | if (index == dev_priv->drrs.refresh_rate_type) { |
439d7ac0 PB |
5229 | DRM_DEBUG_KMS( |
5230 | "DRRS requested for previously set RR...ignoring\n"); | |
5231 | return; | |
5232 | } | |
5233 | ||
85cb48a1 | 5234 | if (!crtc_state->base.active) { |
439d7ac0 PB |
5235 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
5236 | return; | |
5237 | } | |
5238 | ||
85cb48a1 | 5239 | if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { |
a4c30b1d VK |
5240 | switch (index) { |
5241 | case DRRS_HIGH_RR: | |
5242 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
5243 | break; | |
5244 | case DRRS_LOW_RR: | |
5245 | intel_dp_set_m_n(intel_crtc, M2_N2); | |
5246 | break; | |
5247 | case DRRS_MAX_RR: | |
5248 | default: | |
5249 | DRM_ERROR("Unsupported refreshrate type\n"); | |
5250 | } | |
85cb48a1 ML |
5251 | } else if (INTEL_GEN(dev_priv) > 6) { |
5252 | i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); | |
649636ef | 5253 | u32 val; |
a4c30b1d | 5254 | |
649636ef | 5255 | val = I915_READ(reg); |
439d7ac0 | 5256 | if (index > DRRS_HIGH_RR) { |
85cb48a1 | 5257 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
5258 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5259 | else | |
5260 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 5261 | } else { |
85cb48a1 | 5262 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
5263 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5264 | else | |
5265 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 PB |
5266 | } |
5267 | I915_WRITE(reg, val); | |
5268 | } | |
5269 | ||
4e9ac947 VK |
5270 | dev_priv->drrs.refresh_rate_type = index; |
5271 | ||
5272 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); | |
5273 | } | |
5274 | ||
b33a2815 VK |
5275 | /** |
5276 | * intel_edp_drrs_enable - init drrs struct if supported | |
5277 | * @intel_dp: DP struct | |
5423adf1 | 5278 | * @crtc_state: A pointer to the active crtc state. |
b33a2815 VK |
5279 | * |
5280 | * Initializes frontbuffer_bits and drrs.dp | |
5281 | */ | |
85cb48a1 ML |
5282 | void intel_edp_drrs_enable(struct intel_dp *intel_dp, |
5283 | struct intel_crtc_state *crtc_state) | |
c395578e VK |
5284 | { |
5285 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 5286 | struct drm_i915_private *dev_priv = to_i915(dev); |
c395578e | 5287 | |
85cb48a1 | 5288 | if (!crtc_state->has_drrs) { |
c395578e VK |
5289 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
5290 | return; | |
5291 | } | |
5292 | ||
5293 | mutex_lock(&dev_priv->drrs.mutex); | |
5294 | if (WARN_ON(dev_priv->drrs.dp)) { | |
5295 | DRM_ERROR("DRRS already enabled\n"); | |
5296 | goto unlock; | |
5297 | } | |
5298 | ||
5299 | dev_priv->drrs.busy_frontbuffer_bits = 0; | |
5300 | ||
5301 | dev_priv->drrs.dp = intel_dp; | |
5302 | ||
5303 | unlock: | |
5304 | mutex_unlock(&dev_priv->drrs.mutex); | |
5305 | } | |
5306 | ||
b33a2815 VK |
5307 | /** |
5308 | * intel_edp_drrs_disable - Disable DRRS | |
5309 | * @intel_dp: DP struct | |
5423adf1 | 5310 | * @old_crtc_state: Pointer to old crtc_state. |
b33a2815 VK |
5311 | * |
5312 | */ | |
85cb48a1 ML |
5313 | void intel_edp_drrs_disable(struct intel_dp *intel_dp, |
5314 | struct intel_crtc_state *old_crtc_state) | |
c395578e VK |
5315 | { |
5316 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 5317 | struct drm_i915_private *dev_priv = to_i915(dev); |
c395578e | 5318 | |
85cb48a1 | 5319 | if (!old_crtc_state->has_drrs) |
c395578e VK |
5320 | return; |
5321 | ||
5322 | mutex_lock(&dev_priv->drrs.mutex); | |
5323 | if (!dev_priv->drrs.dp) { | |
5324 | mutex_unlock(&dev_priv->drrs.mutex); | |
5325 | return; | |
5326 | } | |
5327 | ||
5328 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) | |
85cb48a1 ML |
5329 | intel_dp_set_drrs_state(dev_priv, old_crtc_state, |
5330 | intel_dp->attached_connector->panel.fixed_mode->vrefresh); | |
c395578e VK |
5331 | |
5332 | dev_priv->drrs.dp = NULL; | |
5333 | mutex_unlock(&dev_priv->drrs.mutex); | |
5334 | ||
5335 | cancel_delayed_work_sync(&dev_priv->drrs.work); | |
5336 | } | |
5337 | ||
4e9ac947 VK |
5338 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5339 | { | |
5340 | struct drm_i915_private *dev_priv = | |
5341 | container_of(work, typeof(*dev_priv), drrs.work.work); | |
5342 | struct intel_dp *intel_dp; | |
5343 | ||
5344 | mutex_lock(&dev_priv->drrs.mutex); | |
5345 | ||
5346 | intel_dp = dev_priv->drrs.dp; | |
5347 | ||
5348 | if (!intel_dp) | |
5349 | goto unlock; | |
5350 | ||
439d7ac0 | 5351 | /* |
4e9ac947 VK |
5352 | * The delayed work can race with an invalidate hence we need to |
5353 | * recheck. | |
439d7ac0 PB |
5354 | */ |
5355 | ||
4e9ac947 VK |
5356 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5357 | goto unlock; | |
439d7ac0 | 5358 | |
85cb48a1 ML |
5359 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { |
5360 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; | |
5361 | ||
5362 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, | |
5363 | intel_dp->attached_connector->panel.downclock_mode->vrefresh); | |
5364 | } | |
439d7ac0 | 5365 | |
4e9ac947 | 5366 | unlock: |
4e9ac947 | 5367 | mutex_unlock(&dev_priv->drrs.mutex); |
439d7ac0 PB |
5368 | } |
5369 | ||
b33a2815 | 5370 | /** |
0ddfd203 | 5371 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5748b6a1 | 5372 | * @dev_priv: i915 device |
b33a2815 VK |
5373 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5374 | * | |
0ddfd203 R |
5375 | * This function gets called everytime rendering on the given planes start. |
5376 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). | |
b33a2815 VK |
5377 | * |
5378 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5379 | */ | |
5748b6a1 CW |
5380 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
5381 | unsigned int frontbuffer_bits) | |
a93fad0f | 5382 | { |
a93fad0f VK |
5383 | struct drm_crtc *crtc; |
5384 | enum pipe pipe; | |
5385 | ||
9da7d693 | 5386 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5387 | return; |
5388 | ||
88f933a8 | 5389 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5390 | |
a93fad0f | 5391 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5392 | if (!dev_priv->drrs.dp) { |
5393 | mutex_unlock(&dev_priv->drrs.mutex); | |
5394 | return; | |
5395 | } | |
5396 | ||
a93fad0f VK |
5397 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5398 | pipe = to_intel_crtc(crtc)->pipe; | |
5399 | ||
c1d038c6 DV |
5400 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5401 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; | |
5402 | ||
0ddfd203 | 5403 | /* invalidate means busy screen hence upclock */ |
c1d038c6 | 5404 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
5405 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
5406 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
a93fad0f | 5407 | |
a93fad0f VK |
5408 | mutex_unlock(&dev_priv->drrs.mutex); |
5409 | } | |
5410 | ||
b33a2815 | 5411 | /** |
0ddfd203 | 5412 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5748b6a1 | 5413 | * @dev_priv: i915 device |
b33a2815 VK |
5414 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5415 | * | |
0ddfd203 R |
5416 | * This function gets called every time rendering on the given planes has |
5417 | * completed or flip on a crtc is completed. So DRRS should be upclocked | |
5418 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, | |
5419 | * if no other planes are dirty. | |
b33a2815 VK |
5420 | * |
5421 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5422 | */ | |
5748b6a1 CW |
5423 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, |
5424 | unsigned int frontbuffer_bits) | |
a93fad0f | 5425 | { |
a93fad0f VK |
5426 | struct drm_crtc *crtc; |
5427 | enum pipe pipe; | |
5428 | ||
9da7d693 | 5429 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5430 | return; |
5431 | ||
88f933a8 | 5432 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5433 | |
a93fad0f | 5434 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5435 | if (!dev_priv->drrs.dp) { |
5436 | mutex_unlock(&dev_priv->drrs.mutex); | |
5437 | return; | |
5438 | } | |
5439 | ||
a93fad0f VK |
5440 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5441 | pipe = to_intel_crtc(crtc)->pipe; | |
c1d038c6 DV |
5442 | |
5443 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
a93fad0f VK |
5444 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5445 | ||
0ddfd203 | 5446 | /* flush means busy screen hence upclock */ |
c1d038c6 | 5447 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
5448 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
5449 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
0ddfd203 R |
5450 | |
5451 | /* | |
5452 | * flush also means no more activity hence schedule downclock, if all | |
5453 | * other fbs are quiescent too | |
5454 | */ | |
5455 | if (!dev_priv->drrs.busy_frontbuffer_bits) | |
a93fad0f VK |
5456 | schedule_delayed_work(&dev_priv->drrs.work, |
5457 | msecs_to_jiffies(1000)); | |
5458 | mutex_unlock(&dev_priv->drrs.mutex); | |
5459 | } | |
5460 | ||
b33a2815 VK |
5461 | /** |
5462 | * DOC: Display Refresh Rate Switching (DRRS) | |
5463 | * | |
5464 | * Display Refresh Rate Switching (DRRS) is a power conservation feature | |
5465 | * which enables swtching between low and high refresh rates, | |
5466 | * dynamically, based on the usage scenario. This feature is applicable | |
5467 | * for internal panels. | |
5468 | * | |
5469 | * Indication that the panel supports DRRS is given by the panel EDID, which | |
5470 | * would list multiple refresh rates for one resolution. | |
5471 | * | |
5472 | * DRRS is of 2 types - static and seamless. | |
5473 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset | |
5474 | * (may appear as a blink on screen) and is used in dock-undock scenario. | |
5475 | * Seamless DRRS involves changing RR without any visual effect to the user | |
5476 | * and can be used during normal system usage. This is done by programming | |
5477 | * certain registers. | |
5478 | * | |
5479 | * Support for static/seamless DRRS may be indicated in the VBT based on | |
5480 | * inputs from the panel spec. | |
5481 | * | |
5482 | * DRRS saves power by switching to low RR based on usage scenarios. | |
5483 | * | |
2e7a5701 DV |
5484 | * The implementation is based on frontbuffer tracking implementation. When |
5485 | * there is a disturbance on the screen triggered by user activity or a periodic | |
5486 | * system activity, DRRS is disabled (RR is changed to high RR). When there is | |
5487 | * no movement on screen, after a timeout of 1 second, a switch to low RR is | |
5488 | * made. | |
5489 | * | |
5490 | * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() | |
5491 | * and intel_edp_drrs_flush() are called. | |
b33a2815 VK |
5492 | * |
5493 | * DRRS can be further extended to support other internal panels and also | |
5494 | * the scenario of video playback wherein RR is set based on the rate | |
5495 | * requested by userspace. | |
5496 | */ | |
5497 | ||
5498 | /** | |
5499 | * intel_dp_drrs_init - Init basic DRRS work and mutex. | |
5500 | * @intel_connector: eDP connector | |
5501 | * @fixed_mode: preferred mode of panel | |
5502 | * | |
5503 | * This function is called only once at driver load to initialize basic | |
5504 | * DRRS stuff. | |
5505 | * | |
5506 | * Returns: | |
5507 | * Downclock mode if panel supports it, else return NULL. | |
5508 | * DRRS support is determined by the presence of downclock mode (apart | |
5509 | * from VBT setting). | |
5510 | */ | |
4f9db5b5 | 5511 | static struct drm_display_mode * |
96178eeb VK |
5512 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5513 | struct drm_display_mode *fixed_mode) | |
4f9db5b5 PB |
5514 | { |
5515 | struct drm_connector *connector = &intel_connector->base; | |
96178eeb | 5516 | struct drm_device *dev = connector->dev; |
fac5e23e | 5517 | struct drm_i915_private *dev_priv = to_i915(dev); |
4f9db5b5 PB |
5518 | struct drm_display_mode *downclock_mode = NULL; |
5519 | ||
9da7d693 DV |
5520 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5521 | mutex_init(&dev_priv->drrs.mutex); | |
5522 | ||
dd11bc10 | 5523 | if (INTEL_GEN(dev_priv) <= 6) { |
4f9db5b5 PB |
5524 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
5525 | return NULL; | |
5526 | } | |
5527 | ||
5528 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
4079b8d1 | 5529 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
4f9db5b5 PB |
5530 | return NULL; |
5531 | } | |
5532 | ||
5533 | downclock_mode = intel_find_panel_downclock | |
5534 | (dev, fixed_mode, connector); | |
5535 | ||
5536 | if (!downclock_mode) { | |
a1d26342 | 5537 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
4f9db5b5 PB |
5538 | return NULL; |
5539 | } | |
5540 | ||
96178eeb | 5541 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
4f9db5b5 | 5542 | |
96178eeb | 5543 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
4079b8d1 | 5544 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
4f9db5b5 PB |
5545 | return downclock_mode; |
5546 | } | |
5547 | ||
ed92f0b2 | 5548 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 5549 | struct intel_connector *intel_connector) |
ed92f0b2 PZ |
5550 | { |
5551 | struct drm_connector *connector = &intel_connector->base; | |
5552 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
63635217 PZ |
5553 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5554 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 5555 | struct drm_i915_private *dev_priv = to_i915(dev); |
ed92f0b2 | 5556 | struct drm_display_mode *fixed_mode = NULL; |
4f9db5b5 | 5557 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 PZ |
5558 | bool has_dpcd; |
5559 | struct drm_display_mode *scan; | |
5560 | struct edid *edid; | |
6517d273 | 5561 | enum pipe pipe = INVALID_PIPE; |
ed92f0b2 PZ |
5562 | |
5563 | if (!is_edp(intel_dp)) | |
5564 | return true; | |
5565 | ||
97a824e1 ID |
5566 | /* |
5567 | * On IBX/CPT we may get here with LVDS already registered. Since the | |
5568 | * driver uses the only internal power sequencer available for both | |
5569 | * eDP and LVDS bail out early in this case to prevent interfering | |
5570 | * with an already powered-on LVDS power sequencer. | |
5571 | */ | |
5572 | if (intel_get_lvds_encoder(dev)) { | |
5573 | WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); | |
5574 | DRM_INFO("LVDS was detected, not registering eDP\n"); | |
5575 | ||
5576 | return false; | |
5577 | } | |
5578 | ||
49e6bc51 | 5579 | pps_lock(intel_dp); |
b4d06ede ID |
5580 | |
5581 | intel_dp_init_panel_power_timestamps(intel_dp); | |
335f752b | 5582 | intel_dp_pps_init(dev, intel_dp); |
49e6bc51 | 5583 | intel_edp_panel_vdd_sanitize(intel_dp); |
b4d06ede | 5584 | |
49e6bc51 | 5585 | pps_unlock(intel_dp); |
63635217 | 5586 | |
ed92f0b2 | 5587 | /* Cache DPCD and EDID for edp. */ |
fe5a66f9 | 5588 | has_dpcd = intel_edp_init_dpcd(intel_dp); |
ed92f0b2 | 5589 | |
fe5a66f9 | 5590 | if (!has_dpcd) { |
ed92f0b2 PZ |
5591 | /* if this fails, presume the device is a ghost */ |
5592 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
b4d06ede | 5593 | goto out_vdd_off; |
ed92f0b2 PZ |
5594 | } |
5595 | ||
060c8778 | 5596 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 5597 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
5598 | if (edid) { |
5599 | if (drm_add_edid_modes(connector, edid)) { | |
5600 | drm_mode_connector_update_edid_property(connector, | |
5601 | edid); | |
5602 | drm_edid_to_eld(connector, edid); | |
5603 | } else { | |
5604 | kfree(edid); | |
5605 | edid = ERR_PTR(-EINVAL); | |
5606 | } | |
5607 | } else { | |
5608 | edid = ERR_PTR(-ENOENT); | |
5609 | } | |
5610 | intel_connector->edid = edid; | |
5611 | ||
5612 | /* prefer fixed mode from EDID if available */ | |
5613 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
5614 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
5615 | fixed_mode = drm_mode_duplicate(dev, scan); | |
4f9db5b5 | 5616 | downclock_mode = intel_dp_drrs_init( |
4f9db5b5 | 5617 | intel_connector, fixed_mode); |
ed92f0b2 PZ |
5618 | break; |
5619 | } | |
5620 | } | |
5621 | ||
5622 | /* fallback to VBT if available for eDP */ | |
5623 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
5624 | fixed_mode = drm_mode_duplicate(dev, | |
5625 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
df457245 | 5626 | if (fixed_mode) { |
ed92f0b2 | 5627 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
df457245 VS |
5628 | connector->display_info.width_mm = fixed_mode->width_mm; |
5629 | connector->display_info.height_mm = fixed_mode->height_mm; | |
5630 | } | |
ed92f0b2 | 5631 | } |
060c8778 | 5632 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 5633 | |
920a14b2 | 5634 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
01527b31 CT |
5635 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
5636 | register_reboot_notifier(&intel_dp->edp_notifier); | |
6517d273 VS |
5637 | |
5638 | /* | |
5639 | * Figure out the current pipe for the initial backlight setup. | |
5640 | * If the current pipe isn't valid, try the PPS pipe, and if that | |
5641 | * fails just assume pipe A. | |
5642 | */ | |
920a14b2 | 5643 | if (IS_CHERRYVIEW(dev_priv)) |
6517d273 VS |
5644 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); |
5645 | else | |
5646 | pipe = PORT_TO_PIPE(intel_dp->DP); | |
5647 | ||
5648 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5649 | pipe = intel_dp->pps_pipe; | |
5650 | ||
5651 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5652 | pipe = PIPE_A; | |
5653 | ||
5654 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", | |
5655 | pipe_name(pipe)); | |
01527b31 CT |
5656 | } |
5657 | ||
4f9db5b5 | 5658 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5507faeb | 5659 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
6517d273 | 5660 | intel_panel_setup_backlight(connector, pipe); |
ed92f0b2 PZ |
5661 | |
5662 | return true; | |
b4d06ede ID |
5663 | |
5664 | out_vdd_off: | |
5665 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
5666 | /* | |
5667 | * vdd might still be enabled do to the delayed vdd off. | |
5668 | * Make sure vdd is actually turned off here. | |
5669 | */ | |
5670 | pps_lock(intel_dp); | |
5671 | edp_panel_vdd_off_sync(intel_dp); | |
5672 | pps_unlock(intel_dp); | |
5673 | ||
5674 | return false; | |
ed92f0b2 PZ |
5675 | } |
5676 | ||
16c25533 | 5677 | bool |
f0fec3f2 PZ |
5678 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5679 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 5680 | { |
f0fec3f2 PZ |
5681 | struct drm_connector *connector = &intel_connector->base; |
5682 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
5683 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
5684 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 5685 | struct drm_i915_private *dev_priv = to_i915(dev); |
174edf1f | 5686 | enum port port = intel_dig_port->port; |
7a418e34 | 5687 | int type; |
a4fc5ed6 | 5688 | |
ccb1a831 VS |
5689 | if (WARN(intel_dig_port->max_lanes < 1, |
5690 | "Not enough lanes (%d) for DP on port %c\n", | |
5691 | intel_dig_port->max_lanes, port_name(port))) | |
5692 | return false; | |
5693 | ||
a4a5d2f8 VS |
5694 | intel_dp->pps_pipe = INVALID_PIPE; |
5695 | ||
ec5b01dd | 5696 | /* intel_dp vfuncs */ |
dd11bc10 | 5697 | if (INTEL_GEN(dev_priv) >= 9) |
b6b5e383 | 5698 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
8652744b | 5699 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ec5b01dd | 5700 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
6e266956 | 5701 | else if (HAS_PCH_SPLIT(dev_priv)) |
ec5b01dd DL |
5702 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
5703 | else | |
6ffb1be7 | 5704 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; |
ec5b01dd | 5705 | |
dd11bc10 | 5706 | if (INTEL_GEN(dev_priv) >= 9) |
b9ca5fad DL |
5707 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
5708 | else | |
6ffb1be7 | 5709 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; |
153b1100 | 5710 | |
4f8036a2 | 5711 | if (HAS_DDI(dev_priv)) |
ad64217b ACO |
5712 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; |
5713 | ||
0767935e DV |
5714 | /* Preserve the current hw state. */ |
5715 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 5716 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 5717 | |
dd11bc10 | 5718 | if (intel_dp_is_edp(dev_priv, port)) |
b329530c | 5719 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
5720 | else |
5721 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 5722 | |
f7d24902 ID |
5723 | /* |
5724 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
5725 | * for DP the encoder type can be set by the caller to | |
5726 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
5727 | */ | |
5728 | if (type == DRM_MODE_CONNECTOR_eDP) | |
5729 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
5730 | ||
c17ed5b5 | 5731 | /* eDP only on port B and/or C on vlv/chv */ |
920a14b2 | 5732 | if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 5733 | is_edp(intel_dp) && port != PORT_B && port != PORT_C)) |
c17ed5b5 VS |
5734 | return false; |
5735 | ||
e7281eab ID |
5736 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
5737 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
5738 | port_name(port)); | |
5739 | ||
b329530c | 5740 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
5741 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
5742 | ||
a4fc5ed6 KP |
5743 | connector->interlace_allowed = true; |
5744 | connector->doublescan_allowed = 0; | |
5745 | ||
b6339585 | 5746 | intel_dp_aux_init(intel_dp); |
7a418e34 | 5747 | |
f0fec3f2 | 5748 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 5749 | edp_panel_vdd_work); |
a4fc5ed6 | 5750 | |
df0e9248 | 5751 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 | 5752 | |
4f8036a2 | 5753 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
5754 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
5755 | else | |
5756 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
5757 | ||
0b99836f | 5758 | /* Set up the hotplug pin. */ |
ab9d7c30 PZ |
5759 | switch (port) { |
5760 | case PORT_A: | |
1d843f9d | 5761 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
5762 | break; |
5763 | case PORT_B: | |
1d843f9d | 5764 | intel_encoder->hpd_pin = HPD_PORT_B; |
e2d214ae | 5765 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
cf1d5883 | 5766 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
5767 | break; |
5768 | case PORT_C: | |
1d843f9d | 5769 | intel_encoder->hpd_pin = HPD_PORT_C; |
ab9d7c30 PZ |
5770 | break; |
5771 | case PORT_D: | |
1d843f9d | 5772 | intel_encoder->hpd_pin = HPD_PORT_D; |
ab9d7c30 | 5773 | break; |
26951caf XZ |
5774 | case PORT_E: |
5775 | intel_encoder->hpd_pin = HPD_PORT_E; | |
5776 | break; | |
ab9d7c30 | 5777 | default: |
ad1c0b19 | 5778 | BUG(); |
5eb08b69 ZW |
5779 | } |
5780 | ||
0e32b39c | 5781 | /* init MST on ports that can support it */ |
56b857a5 | 5782 | if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) && |
0c9b3715 JN |
5783 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
5784 | intel_dp_mst_encoder_init(intel_dig_port, | |
5785 | intel_connector->base.base.id); | |
0e32b39c | 5786 | |
36b5f425 | 5787 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
a121f4e5 VS |
5788 | intel_dp_aux_fini(intel_dp); |
5789 | intel_dp_mst_encoder_cleanup(intel_dig_port); | |
5790 | goto fail; | |
b2f246a8 | 5791 | } |
32f9d658 | 5792 | |
f684960e CW |
5793 | intel_dp_add_properties(intel_dp, connector); |
5794 | ||
a4fc5ed6 KP |
5795 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
5796 | * 0xd. Failure to do so will result in spurious interrupts being | |
5797 | * generated on the port when a cable is not attached. | |
5798 | */ | |
50a0bc90 | 5799 | if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { |
a4fc5ed6 KP |
5800 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
5801 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
5802 | } | |
16c25533 PZ |
5803 | |
5804 | return true; | |
a121f4e5 VS |
5805 | |
5806 | fail: | |
a121f4e5 VS |
5807 | drm_connector_cleanup(connector); |
5808 | ||
5809 | return false; | |
a4fc5ed6 | 5810 | } |
f0fec3f2 | 5811 | |
c39055b0 | 5812 | bool intel_dp_init(struct drm_i915_private *dev_priv, |
457c52d8 CW |
5813 | i915_reg_t output_reg, |
5814 | enum port port) | |
f0fec3f2 PZ |
5815 | { |
5816 | struct intel_digital_port *intel_dig_port; | |
5817 | struct intel_encoder *intel_encoder; | |
5818 | struct drm_encoder *encoder; | |
5819 | struct intel_connector *intel_connector; | |
5820 | ||
b14c5679 | 5821 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 | 5822 | if (!intel_dig_port) |
457c52d8 | 5823 | return false; |
f0fec3f2 | 5824 | |
08d9bc92 | 5825 | intel_connector = intel_connector_alloc(); |
11aee0f6 SM |
5826 | if (!intel_connector) |
5827 | goto err_connector_alloc; | |
f0fec3f2 PZ |
5828 | |
5829 | intel_encoder = &intel_dig_port->base; | |
5830 | encoder = &intel_encoder->base; | |
5831 | ||
c39055b0 ACO |
5832 | if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
5833 | &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
5834 | "DP %c", port_name(port))) | |
893da0c9 | 5835 | goto err_encoder_init; |
f0fec3f2 | 5836 | |
5bfe2ac0 | 5837 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 5838 | intel_encoder->disable = intel_disable_dp; |
00c09d70 | 5839 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 5840 | intel_encoder->get_config = intel_dp_get_config; |
07f9cd0b | 5841 | intel_encoder->suspend = intel_dp_encoder_suspend; |
920a14b2 | 5842 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 5843 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
e4a1d846 CML |
5844 | intel_encoder->pre_enable = chv_pre_enable_dp; |
5845 | intel_encoder->enable = vlv_enable_dp; | |
580d3811 | 5846 | intel_encoder->post_disable = chv_post_disable_dp; |
d6db995f | 5847 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
11a914c2 | 5848 | } else if (IS_VALLEYVIEW(dev_priv)) { |
ecff4f3b | 5849 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
5850 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
5851 | intel_encoder->enable = vlv_enable_dp; | |
49277c31 | 5852 | intel_encoder->post_disable = vlv_post_disable_dp; |
ab1f90f9 | 5853 | } else { |
ecff4f3b JN |
5854 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
5855 | intel_encoder->enable = g4x_enable_dp; | |
dd11bc10 | 5856 | if (INTEL_GEN(dev_priv) >= 5) |
08aff3fe | 5857 | intel_encoder->post_disable = ilk_post_disable_dp; |
ab1f90f9 | 5858 | } |
f0fec3f2 | 5859 | |
174edf1f | 5860 | intel_dig_port->port = port; |
f0fec3f2 | 5861 | intel_dig_port->dp.output_reg = output_reg; |
ccb1a831 | 5862 | intel_dig_port->max_lanes = 4; |
f0fec3f2 | 5863 | |
cca0502b | 5864 | intel_encoder->type = INTEL_OUTPUT_DP; |
920a14b2 | 5865 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 VS |
5866 | if (port == PORT_D) |
5867 | intel_encoder->crtc_mask = 1 << 2; | |
5868 | else | |
5869 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
5870 | } else { | |
5871 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
5872 | } | |
bc079e8b | 5873 | intel_encoder->cloneable = 0; |
03cdc1d4 | 5874 | intel_encoder->port = port; |
f0fec3f2 | 5875 | |
13cf5504 | 5876 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
5fcece80 | 5877 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
13cf5504 | 5878 | |
11aee0f6 SM |
5879 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
5880 | goto err_init_connector; | |
5881 | ||
457c52d8 | 5882 | return true; |
11aee0f6 SM |
5883 | |
5884 | err_init_connector: | |
5885 | drm_encoder_cleanup(encoder); | |
893da0c9 | 5886 | err_encoder_init: |
11aee0f6 SM |
5887 | kfree(intel_connector); |
5888 | err_connector_alloc: | |
5889 | kfree(intel_dig_port); | |
457c52d8 | 5890 | return false; |
f0fec3f2 | 5891 | } |
0e32b39c DA |
5892 | |
5893 | void intel_dp_mst_suspend(struct drm_device *dev) | |
5894 | { | |
fac5e23e | 5895 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
5896 | int i; |
5897 | ||
5898 | /* disable MST */ | |
5899 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 5900 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 VS |
5901 | |
5902 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) | |
0e32b39c DA |
5903 | continue; |
5904 | ||
5aa56969 VS |
5905 | if (intel_dig_port->dp.is_mst) |
5906 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); | |
0e32b39c DA |
5907 | } |
5908 | } | |
5909 | ||
5910 | void intel_dp_mst_resume(struct drm_device *dev) | |
5911 | { | |
fac5e23e | 5912 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
5913 | int i; |
5914 | ||
5915 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 5916 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 | 5917 | int ret; |
0e32b39c | 5918 | |
5aa56969 VS |
5919 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) |
5920 | continue; | |
0e32b39c | 5921 | |
5aa56969 VS |
5922 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
5923 | if (ret) | |
5924 | intel_dp_check_mst_status(&intel_dig_port->dp); | |
0e32b39c DA |
5925 | } |
5926 | } |