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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
01527b31 CT |
31 | #include <linux/notifier.h> |
32 | #include <linux/reboot.h> | |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_crtc_helper.h> | |
37 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 38 | #include "intel_drv.h" |
760285e7 | 39 | #include <drm/i915_drm.h> |
a4fc5ed6 | 40 | #include "i915_drv.h" |
a4fc5ed6 | 41 | |
a4fc5ed6 KP |
42 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
43 | ||
559be30c TP |
44 | /* Compliance test status bits */ |
45 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 | |
46 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
47 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
48 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
49 | ||
9dd4ffdf | 50 | struct dp_link_dpll { |
840b32b7 | 51 | int clock; |
9dd4ffdf CML |
52 | struct dpll dpll; |
53 | }; | |
54 | ||
55 | static const struct dp_link_dpll gen4_dpll[] = { | |
840b32b7 | 56 | { 162000, |
9dd4ffdf | 57 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
840b32b7 | 58 | { 270000, |
9dd4ffdf CML |
59 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
60 | }; | |
61 | ||
62 | static const struct dp_link_dpll pch_dpll[] = { | |
840b32b7 | 63 | { 162000, |
9dd4ffdf | 64 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
840b32b7 | 65 | { 270000, |
9dd4ffdf CML |
66 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
67 | }; | |
68 | ||
65ce4bf5 | 69 | static const struct dp_link_dpll vlv_dpll[] = { |
840b32b7 | 70 | { 162000, |
58f6e632 | 71 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
840b32b7 | 72 | { 270000, |
65ce4bf5 CML |
73 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
74 | }; | |
75 | ||
ef9348c8 CML |
76 | /* |
77 | * CHV supports eDP 1.4 that have more link rates. | |
78 | * Below only provides the fixed rate but exclude variable rate. | |
79 | */ | |
80 | static const struct dp_link_dpll chv_dpll[] = { | |
81 | /* | |
82 | * CHV requires to program fractional division for m2. | |
83 | * m2 is stored in fixed point format using formula below | |
84 | * (m2_int << 22) | m2_fraction | |
85 | */ | |
840b32b7 | 86 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
ef9348c8 | 87 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
840b32b7 | 88 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 | 89 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
840b32b7 | 90 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 CML |
91 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
92 | }; | |
637a9c63 | 93 | |
64987fc5 SJ |
94 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
95 | 324000, 432000, 540000 }; | |
637a9c63 | 96 | static const int skl_rates[] = { 162000, 216000, 270000, |
f4896f15 VS |
97 | 324000, 432000, 540000 }; |
98 | static const int default_rates[] = { 162000, 270000, 540000 }; | |
ef9348c8 | 99 | |
cfcb0fc9 JB |
100 | /** |
101 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
102 | * @intel_dp: DP struct | |
103 | * | |
104 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
105 | * will return true, and false otherwise. | |
106 | */ | |
107 | static bool is_edp(struct intel_dp *intel_dp) | |
108 | { | |
da63a9f2 PZ |
109 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
110 | ||
111 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
112 | } |
113 | ||
68b4d824 | 114 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 115 | { |
68b4d824 ID |
116 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
117 | ||
118 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
119 | } |
120 | ||
df0e9248 CW |
121 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
122 | { | |
fa90ecef | 123 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
124 | } |
125 | ||
ea5b213a | 126 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
1e0560e0 | 127 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 128 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
093e3f13 | 129 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
a8c3344e VS |
130 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
131 | enum pipe pipe); | |
f21a2198 | 132 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
a4fc5ed6 | 133 | |
ed4e9c1d VS |
134 | static int |
135 | intel_dp_max_link_bw(struct intel_dp *intel_dp) | |
a4fc5ed6 | 136 | { |
7183dc29 | 137 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
138 | |
139 | switch (max_link_bw) { | |
140 | case DP_LINK_BW_1_62: | |
141 | case DP_LINK_BW_2_7: | |
1db10e28 | 142 | case DP_LINK_BW_5_4: |
d4eead50 | 143 | break; |
a4fc5ed6 | 144 | default: |
d4eead50 ID |
145 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
146 | max_link_bw); | |
a4fc5ed6 KP |
147 | max_link_bw = DP_LINK_BW_1_62; |
148 | break; | |
149 | } | |
150 | return max_link_bw; | |
151 | } | |
152 | ||
eeb6324d PZ |
153 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
154 | { | |
155 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
eeb6324d PZ |
156 | u8 source_max, sink_max; |
157 | ||
ccb1a831 | 158 | source_max = intel_dig_port->max_lanes; |
eeb6324d PZ |
159 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
160 | ||
161 | return min(source_max, sink_max); | |
162 | } | |
163 | ||
cd9dde44 AJ |
164 | /* |
165 | * The units on the numbers in the next two are... bizarre. Examples will | |
166 | * make it clearer; this one parallels an example in the eDP spec. | |
167 | * | |
168 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
169 | * | |
170 | * 270000 * 1 * 8 / 10 == 216000 | |
171 | * | |
172 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
173 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
174 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
175 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
176 | * | |
177 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
178 | * get the result in decakilobits instead of kilobits. | |
179 | */ | |
180 | ||
a4fc5ed6 | 181 | static int |
c898261c | 182 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 183 | { |
cd9dde44 | 184 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
185 | } |
186 | ||
fe27d53e DA |
187 | static int |
188 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
189 | { | |
190 | return (max_link_clock * max_lanes * 8) / 10; | |
191 | } | |
192 | ||
70ec0645 MK |
193 | static int |
194 | intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) | |
195 | { | |
196 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
197 | struct intel_encoder *encoder = &intel_dig_port->base; | |
198 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
199 | int max_dotclk = dev_priv->max_dotclk_freq; | |
200 | int ds_max_dotclk; | |
201 | ||
202 | int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
203 | ||
204 | if (type != DP_DS_PORT_TYPE_VGA) | |
205 | return max_dotclk; | |
206 | ||
207 | ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, | |
208 | intel_dp->downstream_ports); | |
209 | ||
210 | if (ds_max_dotclk != 0) | |
211 | max_dotclk = min(max_dotclk, ds_max_dotclk); | |
212 | ||
213 | return max_dotclk; | |
214 | } | |
215 | ||
40dba341 NM |
216 | static int |
217 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) | |
218 | { | |
219 | if (intel_dp->num_sink_rates) { | |
220 | *sink_rates = intel_dp->sink_rates; | |
221 | return intel_dp->num_sink_rates; | |
222 | } | |
223 | ||
224 | *sink_rates = default_rates; | |
225 | ||
226 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; | |
227 | } | |
228 | ||
229 | static int | |
230 | intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) | |
231 | { | |
232 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
233 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
234 | int size; | |
235 | ||
236 | if (IS_BROXTON(dev_priv)) { | |
237 | *source_rates = bxt_rates; | |
238 | size = ARRAY_SIZE(bxt_rates); | |
239 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { | |
240 | *source_rates = skl_rates; | |
241 | size = ARRAY_SIZE(skl_rates); | |
242 | } else { | |
243 | *source_rates = default_rates; | |
244 | size = ARRAY_SIZE(default_rates); | |
245 | } | |
246 | ||
247 | /* This depends on the fact that 5.4 is last value in the array */ | |
248 | if (!intel_dp_source_supports_hbr2(intel_dp)) | |
249 | size--; | |
250 | ||
251 | return size; | |
252 | } | |
253 | ||
254 | static int intersect_rates(const int *source_rates, int source_len, | |
255 | const int *sink_rates, int sink_len, | |
256 | int *common_rates) | |
257 | { | |
258 | int i = 0, j = 0, k = 0; | |
259 | ||
260 | while (i < source_len && j < sink_len) { | |
261 | if (source_rates[i] == sink_rates[j]) { | |
262 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) | |
263 | return k; | |
264 | common_rates[k] = source_rates[i]; | |
265 | ++k; | |
266 | ++i; | |
267 | ++j; | |
268 | } else if (source_rates[i] < sink_rates[j]) { | |
269 | ++i; | |
270 | } else { | |
271 | ++j; | |
272 | } | |
273 | } | |
274 | return k; | |
275 | } | |
276 | ||
277 | static int intel_dp_common_rates(struct intel_dp *intel_dp, | |
278 | int *common_rates) | |
279 | { | |
280 | const int *source_rates, *sink_rates; | |
281 | int source_len, sink_len; | |
282 | ||
283 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); | |
284 | source_len = intel_dp_source_rates(intel_dp, &source_rates); | |
285 | ||
286 | return intersect_rates(source_rates, source_len, | |
287 | sink_rates, sink_len, | |
288 | common_rates); | |
289 | } | |
290 | ||
c19de8eb | 291 | static enum drm_mode_status |
a4fc5ed6 KP |
292 | intel_dp_mode_valid(struct drm_connector *connector, |
293 | struct drm_display_mode *mode) | |
294 | { | |
df0e9248 | 295 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
296 | struct intel_connector *intel_connector = to_intel_connector(connector); |
297 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
298 | int target_clock = mode->clock; |
299 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
70ec0645 MK |
300 | int max_dotclk; |
301 | ||
302 | max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); | |
a4fc5ed6 | 303 | |
dd06f90e JN |
304 | if (is_edp(intel_dp) && fixed_mode) { |
305 | if (mode->hdisplay > fixed_mode->hdisplay) | |
7de56f43 ZY |
306 | return MODE_PANEL; |
307 | ||
dd06f90e | 308 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 309 | return MODE_PANEL; |
03afc4a2 DV |
310 | |
311 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
312 | } |
313 | ||
50fec21a | 314 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
eeb6324d | 315 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 DV |
316 | |
317 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
318 | mode_rate = intel_dp_link_required(target_clock, 18); | |
319 | ||
799487f5 | 320 | if (mode_rate > max_rate || target_clock > max_dotclk) |
c4867936 | 321 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
322 | |
323 | if (mode->clock < 10000) | |
324 | return MODE_CLOCK_LOW; | |
325 | ||
0af78a2b DV |
326 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
327 | return MODE_H_ILLEGAL; | |
328 | ||
a4fc5ed6 KP |
329 | return MODE_OK; |
330 | } | |
331 | ||
a4f1289e | 332 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
a4fc5ed6 KP |
333 | { |
334 | int i; | |
335 | uint32_t v = 0; | |
336 | ||
337 | if (src_bytes > 4) | |
338 | src_bytes = 4; | |
339 | for (i = 0; i < src_bytes; i++) | |
340 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
341 | return v; | |
342 | } | |
343 | ||
c2af70e2 | 344 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
a4fc5ed6 KP |
345 | { |
346 | int i; | |
347 | if (dst_bytes > 4) | |
348 | dst_bytes = 4; | |
349 | for (i = 0; i < dst_bytes; i++) | |
350 | dst[i] = src >> ((3-i) * 8); | |
351 | } | |
352 | ||
bf13e81b JN |
353 | static void |
354 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
36b5f425 | 355 | struct intel_dp *intel_dp); |
bf13e81b JN |
356 | static void |
357 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
8581f1b5 VS |
358 | struct intel_dp *intel_dp, |
359 | bool force_disable_vdd); | |
335f752b ID |
360 | static void |
361 | intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp); | |
bf13e81b | 362 | |
773538e8 VS |
363 | static void pps_lock(struct intel_dp *intel_dp) |
364 | { | |
365 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
366 | struct intel_encoder *encoder = &intel_dig_port->base; | |
367 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 368 | struct drm_i915_private *dev_priv = to_i915(dev); |
773538e8 VS |
369 | enum intel_display_power_domain power_domain; |
370 | ||
371 | /* | |
372 | * See vlv_power_sequencer_reset() why we need | |
373 | * a power domain reference here. | |
374 | */ | |
25f78f58 | 375 | power_domain = intel_display_port_aux_power_domain(encoder); |
773538e8 VS |
376 | intel_display_power_get(dev_priv, power_domain); |
377 | ||
378 | mutex_lock(&dev_priv->pps_mutex); | |
379 | } | |
380 | ||
381 | static void pps_unlock(struct intel_dp *intel_dp) | |
382 | { | |
383 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
384 | struct intel_encoder *encoder = &intel_dig_port->base; | |
385 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 386 | struct drm_i915_private *dev_priv = to_i915(dev); |
773538e8 VS |
387 | enum intel_display_power_domain power_domain; |
388 | ||
389 | mutex_unlock(&dev_priv->pps_mutex); | |
390 | ||
25f78f58 | 391 | power_domain = intel_display_port_aux_power_domain(encoder); |
773538e8 VS |
392 | intel_display_power_put(dev_priv, power_domain); |
393 | } | |
394 | ||
961a0db0 VS |
395 | static void |
396 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) | |
397 | { | |
398 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
30ad9814 | 399 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
961a0db0 | 400 | enum pipe pipe = intel_dp->pps_pipe; |
0047eedc VS |
401 | bool pll_enabled, release_cl_override = false; |
402 | enum dpio_phy phy = DPIO_PHY(pipe); | |
403 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); | |
961a0db0 VS |
404 | uint32_t DP; |
405 | ||
406 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, | |
407 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", | |
408 | pipe_name(pipe), port_name(intel_dig_port->port))) | |
409 | return; | |
410 | ||
411 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", | |
412 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
413 | ||
414 | /* Preserve the BIOS-computed detected bit. This is | |
415 | * supposed to be read-only. | |
416 | */ | |
417 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
418 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
419 | DP |= DP_PORT_WIDTH(1); | |
420 | DP |= DP_LINK_TRAIN_PAT_1; | |
421 | ||
920a14b2 | 422 | if (IS_CHERRYVIEW(dev_priv)) |
961a0db0 VS |
423 | DP |= DP_PIPE_SELECT_CHV(pipe); |
424 | else if (pipe == PIPE_B) | |
425 | DP |= DP_PIPEB_SELECT; | |
426 | ||
d288f65f VS |
427 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
428 | ||
429 | /* | |
430 | * The DPLL for the pipe must be enabled for this to work. | |
431 | * So enable temporarily it if it's not already enabled. | |
432 | */ | |
0047eedc | 433 | if (!pll_enabled) { |
920a14b2 | 434 | release_cl_override = IS_CHERRYVIEW(dev_priv) && |
0047eedc VS |
435 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
436 | ||
30ad9814 | 437 | if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ? |
3f36b937 TU |
438 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
439 | DRM_ERROR("Failed to force on pll for pipe %c!\n", | |
440 | pipe_name(pipe)); | |
441 | return; | |
442 | } | |
0047eedc | 443 | } |
d288f65f | 444 | |
961a0db0 VS |
445 | /* |
446 | * Similar magic as in intel_dp_enable_port(). | |
447 | * We _must_ do this port enable + disable trick | |
448 | * to make this power seqeuencer lock onto the port. | |
449 | * Otherwise even VDD force bit won't work. | |
450 | */ | |
451 | I915_WRITE(intel_dp->output_reg, DP); | |
452 | POSTING_READ(intel_dp->output_reg); | |
453 | ||
454 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); | |
455 | POSTING_READ(intel_dp->output_reg); | |
456 | ||
457 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); | |
458 | POSTING_READ(intel_dp->output_reg); | |
d288f65f | 459 | |
0047eedc | 460 | if (!pll_enabled) { |
30ad9814 | 461 | vlv_force_pll_off(dev_priv, pipe); |
0047eedc VS |
462 | |
463 | if (release_cl_override) | |
464 | chv_phy_powergate_ch(dev_priv, phy, ch, false); | |
465 | } | |
961a0db0 VS |
466 | } |
467 | ||
bf13e81b JN |
468 | static enum pipe |
469 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
470 | { | |
471 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bf13e81b | 472 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 473 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
474 | struct intel_encoder *encoder; |
475 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); | |
a8c3344e | 476 | enum pipe pipe; |
bf13e81b | 477 | |
e39b999a | 478 | lockdep_assert_held(&dev_priv->pps_mutex); |
bf13e81b | 479 | |
a8c3344e VS |
480 | /* We should never land here with regular DP ports */ |
481 | WARN_ON(!is_edp(intel_dp)); | |
482 | ||
a4a5d2f8 VS |
483 | if (intel_dp->pps_pipe != INVALID_PIPE) |
484 | return intel_dp->pps_pipe; | |
485 | ||
486 | /* | |
487 | * We don't have power sequencer currently. | |
488 | * Pick one that's not used by other ports. | |
489 | */ | |
19c8054c | 490 | for_each_intel_encoder(dev, encoder) { |
a4a5d2f8 VS |
491 | struct intel_dp *tmp; |
492 | ||
493 | if (encoder->type != INTEL_OUTPUT_EDP) | |
494 | continue; | |
495 | ||
496 | tmp = enc_to_intel_dp(&encoder->base); | |
497 | ||
498 | if (tmp->pps_pipe != INVALID_PIPE) | |
499 | pipes &= ~(1 << tmp->pps_pipe); | |
500 | } | |
501 | ||
502 | /* | |
503 | * Didn't find one. This should not happen since there | |
504 | * are two power sequencers and up to two eDP ports. | |
505 | */ | |
506 | if (WARN_ON(pipes == 0)) | |
a8c3344e VS |
507 | pipe = PIPE_A; |
508 | else | |
509 | pipe = ffs(pipes) - 1; | |
a4a5d2f8 | 510 | |
a8c3344e VS |
511 | vlv_steal_power_sequencer(dev, pipe); |
512 | intel_dp->pps_pipe = pipe; | |
a4a5d2f8 VS |
513 | |
514 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", | |
515 | pipe_name(intel_dp->pps_pipe), | |
516 | port_name(intel_dig_port->port)); | |
517 | ||
518 | /* init power sequencer on this pipe and port */ | |
36b5f425 | 519 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
8581f1b5 | 520 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true); |
a4a5d2f8 | 521 | |
961a0db0 VS |
522 | /* |
523 | * Even vdd force doesn't work until we've made | |
524 | * the power sequencer lock in on the port. | |
525 | */ | |
526 | vlv_power_sequencer_kick(intel_dp); | |
a4a5d2f8 VS |
527 | |
528 | return intel_dp->pps_pipe; | |
529 | } | |
530 | ||
78597996 ID |
531 | static int |
532 | bxt_power_sequencer_idx(struct intel_dp *intel_dp) | |
533 | { | |
534 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
535 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 536 | struct drm_i915_private *dev_priv = to_i915(dev); |
78597996 ID |
537 | |
538 | lockdep_assert_held(&dev_priv->pps_mutex); | |
539 | ||
540 | /* We should never land here with regular DP ports */ | |
541 | WARN_ON(!is_edp(intel_dp)); | |
542 | ||
543 | /* | |
544 | * TODO: BXT has 2 PPS instances. The correct port->PPS instance | |
545 | * mapping needs to be retrieved from VBT, for now just hard-code to | |
546 | * use instance #0 always. | |
547 | */ | |
548 | if (!intel_dp->pps_reset) | |
549 | return 0; | |
550 | ||
551 | intel_dp->pps_reset = false; | |
552 | ||
553 | /* | |
554 | * Only the HW needs to be reprogrammed, the SW state is fixed and | |
555 | * has been setup during connector init. | |
556 | */ | |
8581f1b5 | 557 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false); |
78597996 ID |
558 | |
559 | return 0; | |
560 | } | |
561 | ||
6491ab27 VS |
562 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
563 | enum pipe pipe); | |
564 | ||
565 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, | |
566 | enum pipe pipe) | |
567 | { | |
44cb734c | 568 | return I915_READ(PP_STATUS(pipe)) & PP_ON; |
6491ab27 VS |
569 | } |
570 | ||
571 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, | |
572 | enum pipe pipe) | |
573 | { | |
44cb734c | 574 | return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
6491ab27 VS |
575 | } |
576 | ||
577 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, | |
578 | enum pipe pipe) | |
579 | { | |
580 | return true; | |
581 | } | |
bf13e81b | 582 | |
a4a5d2f8 | 583 | static enum pipe |
6491ab27 VS |
584 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
585 | enum port port, | |
586 | vlv_pipe_check pipe_check) | |
a4a5d2f8 VS |
587 | { |
588 | enum pipe pipe; | |
bf13e81b | 589 | |
bf13e81b | 590 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
44cb734c | 591 | u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & |
bf13e81b | 592 | PANEL_PORT_SELECT_MASK; |
a4a5d2f8 VS |
593 | |
594 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) | |
595 | continue; | |
596 | ||
6491ab27 VS |
597 | if (!pipe_check(dev_priv, pipe)) |
598 | continue; | |
599 | ||
a4a5d2f8 | 600 | return pipe; |
bf13e81b JN |
601 | } |
602 | ||
a4a5d2f8 VS |
603 | return INVALID_PIPE; |
604 | } | |
605 | ||
606 | static void | |
607 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) | |
608 | { | |
609 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
610 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 611 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
612 | enum port port = intel_dig_port->port; |
613 | ||
614 | lockdep_assert_held(&dev_priv->pps_mutex); | |
615 | ||
616 | /* try to find a pipe with this port selected */ | |
6491ab27 VS |
617 | /* first pick one where the panel is on */ |
618 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
619 | vlv_pipe_has_pp_on); | |
620 | /* didn't find one? pick one where vdd is on */ | |
621 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
622 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
623 | vlv_pipe_has_vdd_on); | |
624 | /* didn't find one? pick one with just the correct port */ | |
625 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
626 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
627 | vlv_pipe_any); | |
a4a5d2f8 VS |
628 | |
629 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ | |
630 | if (intel_dp->pps_pipe == INVALID_PIPE) { | |
631 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", | |
632 | port_name(port)); | |
633 | return; | |
bf13e81b JN |
634 | } |
635 | ||
a4a5d2f8 VS |
636 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
637 | port_name(port), pipe_name(intel_dp->pps_pipe)); | |
638 | ||
36b5f425 | 639 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
8581f1b5 | 640 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false); |
bf13e81b JN |
641 | } |
642 | ||
78597996 | 643 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) |
773538e8 | 644 | { |
91c8a326 | 645 | struct drm_device *dev = &dev_priv->drm; |
773538e8 VS |
646 | struct intel_encoder *encoder; |
647 | ||
920a14b2 | 648 | if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
e2d214ae | 649 | !IS_BROXTON(dev_priv))) |
773538e8 VS |
650 | return; |
651 | ||
652 | /* | |
653 | * We can't grab pps_mutex here due to deadlock with power_domain | |
654 | * mutex when power_domain functions are called while holding pps_mutex. | |
655 | * That also means that in order to use pps_pipe the code needs to | |
656 | * hold both a power domain reference and pps_mutex, and the power domain | |
657 | * reference get/put must be done while _not_ holding pps_mutex. | |
658 | * pps_{lock,unlock}() do these steps in the correct order, so one | |
659 | * should use them always. | |
660 | */ | |
661 | ||
19c8054c | 662 | for_each_intel_encoder(dev, encoder) { |
773538e8 VS |
663 | struct intel_dp *intel_dp; |
664 | ||
665 | if (encoder->type != INTEL_OUTPUT_EDP) | |
666 | continue; | |
667 | ||
668 | intel_dp = enc_to_intel_dp(&encoder->base); | |
e2d214ae | 669 | if (IS_BROXTON(dev_priv)) |
78597996 ID |
670 | intel_dp->pps_reset = true; |
671 | else | |
672 | intel_dp->pps_pipe = INVALID_PIPE; | |
773538e8 | 673 | } |
bf13e81b JN |
674 | } |
675 | ||
8e8232d5 ID |
676 | struct pps_registers { |
677 | i915_reg_t pp_ctrl; | |
678 | i915_reg_t pp_stat; | |
679 | i915_reg_t pp_on; | |
680 | i915_reg_t pp_off; | |
681 | i915_reg_t pp_div; | |
682 | }; | |
683 | ||
684 | static void intel_pps_get_registers(struct drm_i915_private *dev_priv, | |
685 | struct intel_dp *intel_dp, | |
686 | struct pps_registers *regs) | |
687 | { | |
44cb734c ID |
688 | int pps_idx = 0; |
689 | ||
8e8232d5 ID |
690 | memset(regs, 0, sizeof(*regs)); |
691 | ||
44cb734c ID |
692 | if (IS_BROXTON(dev_priv)) |
693 | pps_idx = bxt_power_sequencer_idx(intel_dp); | |
694 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
695 | pps_idx = vlv_power_sequencer_pipe(intel_dp); | |
8e8232d5 | 696 | |
44cb734c ID |
697 | regs->pp_ctrl = PP_CONTROL(pps_idx); |
698 | regs->pp_stat = PP_STATUS(pps_idx); | |
699 | regs->pp_on = PP_ON_DELAYS(pps_idx); | |
700 | regs->pp_off = PP_OFF_DELAYS(pps_idx); | |
701 | if (!IS_BROXTON(dev_priv)) | |
702 | regs->pp_div = PP_DIVISOR(pps_idx); | |
8e8232d5 ID |
703 | } |
704 | ||
f0f59a00 VS |
705 | static i915_reg_t |
706 | _pp_ctrl_reg(struct intel_dp *intel_dp) | |
bf13e81b | 707 | { |
8e8232d5 | 708 | struct pps_registers regs; |
bf13e81b | 709 | |
8e8232d5 ID |
710 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
711 | ®s); | |
712 | ||
713 | return regs.pp_ctrl; | |
bf13e81b JN |
714 | } |
715 | ||
f0f59a00 VS |
716 | static i915_reg_t |
717 | _pp_stat_reg(struct intel_dp *intel_dp) | |
bf13e81b | 718 | { |
8e8232d5 | 719 | struct pps_registers regs; |
bf13e81b | 720 | |
8e8232d5 ID |
721 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
722 | ®s); | |
723 | ||
724 | return regs.pp_stat; | |
bf13e81b JN |
725 | } |
726 | ||
01527b31 CT |
727 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
728 | This function only applicable when panel PM state is not to be tracked */ | |
729 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, | |
730 | void *unused) | |
731 | { | |
732 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), | |
733 | edp_notifier); | |
734 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 735 | struct drm_i915_private *dev_priv = to_i915(dev); |
01527b31 CT |
736 | |
737 | if (!is_edp(intel_dp) || code != SYS_RESTART) | |
738 | return 0; | |
739 | ||
773538e8 | 740 | pps_lock(intel_dp); |
e39b999a | 741 | |
920a14b2 | 742 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e39b999a | 743 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
f0f59a00 | 744 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
649636ef | 745 | u32 pp_div; |
e39b999a | 746 | |
44cb734c ID |
747 | pp_ctrl_reg = PP_CONTROL(pipe); |
748 | pp_div_reg = PP_DIVISOR(pipe); | |
01527b31 CT |
749 | pp_div = I915_READ(pp_div_reg); |
750 | pp_div &= PP_REFERENCE_DIVIDER_MASK; | |
751 | ||
752 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ | |
753 | I915_WRITE(pp_div_reg, pp_div | 0x1F); | |
754 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); | |
755 | msleep(intel_dp->panel_power_cycle_delay); | |
756 | } | |
757 | ||
773538e8 | 758 | pps_unlock(intel_dp); |
e39b999a | 759 | |
01527b31 CT |
760 | return 0; |
761 | } | |
762 | ||
4be73780 | 763 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 764 | { |
30add22d | 765 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 766 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 767 | |
e39b999a VS |
768 | lockdep_assert_held(&dev_priv->pps_mutex); |
769 | ||
920a14b2 | 770 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
771 | intel_dp->pps_pipe == INVALID_PIPE) |
772 | return false; | |
773 | ||
bf13e81b | 774 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
775 | } |
776 | ||
4be73780 | 777 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 778 | { |
30add22d | 779 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 780 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 781 | |
e39b999a VS |
782 | lockdep_assert_held(&dev_priv->pps_mutex); |
783 | ||
920a14b2 | 784 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
785 | intel_dp->pps_pipe == INVALID_PIPE) |
786 | return false; | |
787 | ||
773538e8 | 788 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
ebf33b18 KP |
789 | } |
790 | ||
9b984dae KP |
791 | static void |
792 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
793 | { | |
30add22d | 794 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 795 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 796 | |
9b984dae KP |
797 | if (!is_edp(intel_dp)) |
798 | return; | |
453c5420 | 799 | |
4be73780 | 800 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
801 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
802 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
803 | I915_READ(_pp_stat_reg(intel_dp)), |
804 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
805 | } |
806 | } | |
807 | ||
9ee32fea DV |
808 | static uint32_t |
809 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
810 | { | |
811 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
812 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 813 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 814 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
815 | uint32_t status; |
816 | bool done; | |
817 | ||
ef04f00d | 818 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 819 | if (has_aux_irq) |
b18ac466 | 820 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 821 | msecs_to_jiffies_timeout(10)); |
9ee32fea | 822 | else |
713a6b66 | 823 | done = wait_for(C, 10) == 0; |
9ee32fea DV |
824 | if (!done) |
825 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
826 | has_aux_irq); | |
827 | #undef C | |
828 | ||
829 | return status; | |
830 | } | |
831 | ||
6ffb1be7 | 832 | static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 833 | { |
174edf1f | 834 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
e7dc33f3 | 835 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
9ee32fea | 836 | |
a457f54b VS |
837 | if (index) |
838 | return 0; | |
839 | ||
ec5b01dd DL |
840 | /* |
841 | * The clock divider is based off the hrawclk, and would like to run at | |
a457f54b | 842 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
a4fc5ed6 | 843 | */ |
a457f54b | 844 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
ec5b01dd DL |
845 | } |
846 | ||
847 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
848 | { | |
849 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 850 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd DL |
851 | |
852 | if (index) | |
853 | return 0; | |
854 | ||
a457f54b VS |
855 | /* |
856 | * The clock divider is based off the cdclk or PCH rawclk, and would | |
857 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and | |
858 | * divide by 2000 and use that | |
859 | */ | |
e7dc33f3 | 860 | if (intel_dig_port->port == PORT_A) |
fce18c4c | 861 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
e7dc33f3 VS |
862 | else |
863 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); | |
ec5b01dd DL |
864 | } |
865 | ||
866 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
867 | { | |
868 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 869 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd | 870 | |
a457f54b | 871 | if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { |
2c55c336 | 872 | /* Workaround for non-ULT HSW */ |
bc86625a CW |
873 | switch (index) { |
874 | case 0: return 63; | |
875 | case 1: return 72; | |
876 | default: return 0; | |
877 | } | |
2c55c336 | 878 | } |
a457f54b VS |
879 | |
880 | return ilk_get_aux_clock_divider(intel_dp, index); | |
b84a1cf8 RV |
881 | } |
882 | ||
b6b5e383 DL |
883 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
884 | { | |
885 | /* | |
886 | * SKL doesn't need us to program the AUX clock divider (Hardware will | |
887 | * derive the clock from CDCLK automatically). We still implement the | |
888 | * get_aux_clock_divider vfunc to plug-in into the existing code. | |
889 | */ | |
890 | return index ? 0 : 1; | |
891 | } | |
892 | ||
6ffb1be7 VS |
893 | static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
894 | bool has_aux_irq, | |
895 | int send_bytes, | |
896 | uint32_t aux_clock_divider) | |
5ed12a19 DL |
897 | { |
898 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
8652744b TU |
899 | struct drm_i915_private *dev_priv = |
900 | to_i915(intel_dig_port->base.base.dev); | |
5ed12a19 DL |
901 | uint32_t precharge, timeout; |
902 | ||
8652744b | 903 | if (IS_GEN6(dev_priv)) |
5ed12a19 DL |
904 | precharge = 3; |
905 | else | |
906 | precharge = 5; | |
907 | ||
8652744b | 908 | if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A) |
5ed12a19 DL |
909 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
910 | else | |
911 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
912 | ||
913 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 914 | DP_AUX_CH_CTL_DONE | |
5ed12a19 | 915 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
788d4433 | 916 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 917 | timeout | |
788d4433 | 918 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
919 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
920 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 921 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
922 | } |
923 | ||
b9ca5fad DL |
924 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
925 | bool has_aux_irq, | |
926 | int send_bytes, | |
927 | uint32_t unused) | |
928 | { | |
929 | return DP_AUX_CH_CTL_SEND_BUSY | | |
930 | DP_AUX_CH_CTL_DONE | | |
931 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | | |
932 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
933 | DP_AUX_CH_CTL_TIME_OUT_1600us | | |
934 | DP_AUX_CH_CTL_RECEIVE_ERROR | | |
935 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
d4dcbdce | 936 | DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | |
b9ca5fad DL |
937 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
938 | } | |
939 | ||
b84a1cf8 RV |
940 | static int |
941 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
bd9f74a5 | 942 | const uint8_t *send, int send_bytes, |
b84a1cf8 RV |
943 | uint8_t *recv, int recv_size) |
944 | { | |
945 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
0031fb96 TU |
946 | struct drm_i915_private *dev_priv = |
947 | to_i915(intel_dig_port->base.base.dev); | |
f0f59a00 | 948 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
bc86625a | 949 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
950 | int i, ret, recv_bytes; |
951 | uint32_t status; | |
5ed12a19 | 952 | int try, clock = 0; |
0031fb96 | 953 | bool has_aux_irq = HAS_AUX_IRQ(dev_priv); |
884f19e9 JN |
954 | bool vdd; |
955 | ||
773538e8 | 956 | pps_lock(intel_dp); |
e39b999a | 957 | |
72c3500a VS |
958 | /* |
959 | * We will be called with VDD already enabled for dpcd/edid/oui reads. | |
960 | * In such cases we want to leave VDD enabled and it's up to upper layers | |
961 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off | |
962 | * ourselves. | |
963 | */ | |
1e0560e0 | 964 | vdd = edp_panel_vdd_on(intel_dp); |
b84a1cf8 RV |
965 | |
966 | /* dp aux is extremely sensitive to irq latency, hence request the | |
967 | * lowest possible wakeup latency and so prevent the cpu from going into | |
968 | * deep sleep states. | |
969 | */ | |
970 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
971 | ||
972 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 973 | |
11bee43e JB |
974 | /* Try to wait for any previous AUX channel activity */ |
975 | for (try = 0; try < 3; try++) { | |
ef04f00d | 976 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
977 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
978 | break; | |
979 | msleep(1); | |
980 | } | |
981 | ||
982 | if (try == 3) { | |
02196c77 MK |
983 | static u32 last_status = -1; |
984 | const u32 status = I915_READ(ch_ctl); | |
985 | ||
986 | if (status != last_status) { | |
987 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
988 | status); | |
989 | last_status = status; | |
990 | } | |
991 | ||
9ee32fea DV |
992 | ret = -EBUSY; |
993 | goto out; | |
4f7f7b7e CW |
994 | } |
995 | ||
46a5ae9f PZ |
996 | /* Only 5 data registers! */ |
997 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
998 | ret = -E2BIG; | |
999 | goto out; | |
1000 | } | |
1001 | ||
ec5b01dd | 1002 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
153b1100 DL |
1003 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
1004 | has_aux_irq, | |
1005 | send_bytes, | |
1006 | aux_clock_divider); | |
5ed12a19 | 1007 | |
bc86625a CW |
1008 | /* Must try at least 3 times according to DP spec */ |
1009 | for (try = 0; try < 5; try++) { | |
1010 | /* Load the send data into the aux channel data registers */ | |
1011 | for (i = 0; i < send_bytes; i += 4) | |
330e20ec | 1012 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
a4f1289e RV |
1013 | intel_dp_pack_aux(send + i, |
1014 | send_bytes - i)); | |
bc86625a CW |
1015 | |
1016 | /* Send the command and wait for it to complete */ | |
5ed12a19 | 1017 | I915_WRITE(ch_ctl, send_ctl); |
bc86625a CW |
1018 | |
1019 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
1020 | ||
1021 | /* Clear done status and any errors */ | |
1022 | I915_WRITE(ch_ctl, | |
1023 | status | | |
1024 | DP_AUX_CH_CTL_DONE | | |
1025 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
1026 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
1027 | ||
74ebf294 | 1028 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
bc86625a | 1029 | continue; |
74ebf294 TP |
1030 | |
1031 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 | |
1032 | * 400us delay required for errors and timeouts | |
1033 | * Timeout errors from the HW already meet this | |
1034 | * requirement so skip to next iteration | |
1035 | */ | |
1036 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { | |
1037 | usleep_range(400, 500); | |
bc86625a | 1038 | continue; |
74ebf294 | 1039 | } |
bc86625a | 1040 | if (status & DP_AUX_CH_CTL_DONE) |
e058c945 | 1041 | goto done; |
bc86625a | 1042 | } |
a4fc5ed6 KP |
1043 | } |
1044 | ||
a4fc5ed6 | 1045 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 1046 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
1047 | ret = -EBUSY; |
1048 | goto out; | |
a4fc5ed6 KP |
1049 | } |
1050 | ||
e058c945 | 1051 | done: |
a4fc5ed6 KP |
1052 | /* Check for timeout or receive error. |
1053 | * Timeouts occur when the sink is not connected | |
1054 | */ | |
a5b3da54 | 1055 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 1056 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
1057 | ret = -EIO; |
1058 | goto out; | |
a5b3da54 | 1059 | } |
1ae8c0a5 KP |
1060 | |
1061 | /* Timeouts occur when the device isn't connected, so they're | |
1062 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 1063 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 1064 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
1065 | ret = -ETIMEDOUT; |
1066 | goto out; | |
a4fc5ed6 KP |
1067 | } |
1068 | ||
1069 | /* Unload any bytes sent back from the other side */ | |
1070 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
1071 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
14e01889 RV |
1072 | |
1073 | /* | |
1074 | * By BSpec: "Message sizes of 0 or >20 are not allowed." | |
1075 | * We have no idea of what happened so we return -EBUSY so | |
1076 | * drm layer takes care for the necessary retries. | |
1077 | */ | |
1078 | if (recv_bytes == 0 || recv_bytes > 20) { | |
1079 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", | |
1080 | recv_bytes); | |
1081 | /* | |
1082 | * FIXME: This patch was created on top of a series that | |
1083 | * organize the retries at drm level. There EBUSY should | |
1084 | * also take care for 1ms wait before retrying. | |
1085 | * That aux retries re-org is still needed and after that is | |
1086 | * merged we remove this sleep from here. | |
1087 | */ | |
1088 | usleep_range(1000, 1500); | |
1089 | ret = -EBUSY; | |
1090 | goto out; | |
1091 | } | |
1092 | ||
a4fc5ed6 KP |
1093 | if (recv_bytes > recv_size) |
1094 | recv_bytes = recv_size; | |
0206e353 | 1095 | |
4f7f7b7e | 1096 | for (i = 0; i < recv_bytes; i += 4) |
330e20ec | 1097 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
a4f1289e | 1098 | recv + i, recv_bytes - i); |
a4fc5ed6 | 1099 | |
9ee32fea DV |
1100 | ret = recv_bytes; |
1101 | out: | |
1102 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
1103 | ||
884f19e9 JN |
1104 | if (vdd) |
1105 | edp_panel_vdd_off(intel_dp, false); | |
1106 | ||
773538e8 | 1107 | pps_unlock(intel_dp); |
e39b999a | 1108 | |
9ee32fea | 1109 | return ret; |
a4fc5ed6 KP |
1110 | } |
1111 | ||
a6c8aff0 JN |
1112 | #define BARE_ADDRESS_SIZE 3 |
1113 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
9d1a1031 JN |
1114 | static ssize_t |
1115 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 1116 | { |
9d1a1031 JN |
1117 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
1118 | uint8_t txbuf[20], rxbuf[20]; | |
1119 | size_t txsize, rxsize; | |
a4fc5ed6 | 1120 | int ret; |
a4fc5ed6 | 1121 | |
d2d9cbbd VS |
1122 | txbuf[0] = (msg->request << 4) | |
1123 | ((msg->address >> 16) & 0xf); | |
1124 | txbuf[1] = (msg->address >> 8) & 0xff; | |
9d1a1031 JN |
1125 | txbuf[2] = msg->address & 0xff; |
1126 | txbuf[3] = msg->size - 1; | |
46a5ae9f | 1127 | |
9d1a1031 JN |
1128 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
1129 | case DP_AUX_NATIVE_WRITE: | |
1130 | case DP_AUX_I2C_WRITE: | |
c1e74122 | 1131 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
a6c8aff0 | 1132 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
a1ddefd8 | 1133 | rxsize = 2; /* 0 or 1 data bytes */ |
f51a44b9 | 1134 | |
9d1a1031 JN |
1135 | if (WARN_ON(txsize > 20)) |
1136 | return -E2BIG; | |
a4fc5ed6 | 1137 | |
dd788090 VS |
1138 | WARN_ON(!msg->buffer != !msg->size); |
1139 | ||
d81a67cc ID |
1140 | if (msg->buffer) |
1141 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); | |
a4fc5ed6 | 1142 | |
9d1a1031 JN |
1143 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1144 | if (ret > 0) { | |
1145 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 1146 | |
a1ddefd8 JN |
1147 | if (ret > 1) { |
1148 | /* Number of bytes written in a short write. */ | |
1149 | ret = clamp_t(int, rxbuf[1], 0, msg->size); | |
1150 | } else { | |
1151 | /* Return payload size. */ | |
1152 | ret = msg->size; | |
1153 | } | |
9d1a1031 JN |
1154 | } |
1155 | break; | |
46a5ae9f | 1156 | |
9d1a1031 JN |
1157 | case DP_AUX_NATIVE_READ: |
1158 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 1159 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 1160 | rxsize = msg->size + 1; |
a4fc5ed6 | 1161 | |
9d1a1031 JN |
1162 | if (WARN_ON(rxsize > 20)) |
1163 | return -E2BIG; | |
a4fc5ed6 | 1164 | |
9d1a1031 JN |
1165 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1166 | if (ret > 0) { | |
1167 | msg->reply = rxbuf[0] >> 4; | |
1168 | /* | |
1169 | * Assume happy day, and copy the data. The caller is | |
1170 | * expected to check msg->reply before touching it. | |
1171 | * | |
1172 | * Return payload size. | |
1173 | */ | |
1174 | ret--; | |
1175 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 1176 | } |
9d1a1031 JN |
1177 | break; |
1178 | ||
1179 | default: | |
1180 | ret = -EINVAL; | |
1181 | break; | |
a4fc5ed6 | 1182 | } |
f51a44b9 | 1183 | |
9d1a1031 | 1184 | return ret; |
a4fc5ed6 KP |
1185 | } |
1186 | ||
8f7ce038 VS |
1187 | static enum port intel_aux_port(struct drm_i915_private *dev_priv, |
1188 | enum port port) | |
1189 | { | |
1190 | const struct ddi_vbt_port_info *info = | |
1191 | &dev_priv->vbt.ddi_port_info[port]; | |
1192 | enum port aux_port; | |
1193 | ||
1194 | if (!info->alternate_aux_channel) { | |
1195 | DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n", | |
1196 | port_name(port), port_name(port)); | |
1197 | return port; | |
1198 | } | |
1199 | ||
1200 | switch (info->alternate_aux_channel) { | |
1201 | case DP_AUX_A: | |
1202 | aux_port = PORT_A; | |
1203 | break; | |
1204 | case DP_AUX_B: | |
1205 | aux_port = PORT_B; | |
1206 | break; | |
1207 | case DP_AUX_C: | |
1208 | aux_port = PORT_C; | |
1209 | break; | |
1210 | case DP_AUX_D: | |
1211 | aux_port = PORT_D; | |
1212 | break; | |
1213 | default: | |
1214 | MISSING_CASE(info->alternate_aux_channel); | |
1215 | aux_port = PORT_A; | |
1216 | break; | |
1217 | } | |
1218 | ||
1219 | DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n", | |
1220 | port_name(aux_port), port_name(port)); | |
1221 | ||
1222 | return aux_port; | |
1223 | } | |
1224 | ||
f0f59a00 | 1225 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1226 | enum port port) |
da00bdcf VS |
1227 | { |
1228 | switch (port) { | |
1229 | case PORT_B: | |
1230 | case PORT_C: | |
1231 | case PORT_D: | |
1232 | return DP_AUX_CH_CTL(port); | |
1233 | default: | |
1234 | MISSING_CASE(port); | |
1235 | return DP_AUX_CH_CTL(PORT_B); | |
1236 | } | |
1237 | } | |
1238 | ||
f0f59a00 | 1239 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1240 | enum port port, int index) |
330e20ec VS |
1241 | { |
1242 | switch (port) { | |
1243 | case PORT_B: | |
1244 | case PORT_C: | |
1245 | case PORT_D: | |
1246 | return DP_AUX_CH_DATA(port, index); | |
1247 | default: | |
1248 | MISSING_CASE(port); | |
1249 | return DP_AUX_CH_DATA(PORT_B, index); | |
1250 | } | |
1251 | } | |
1252 | ||
f0f59a00 | 1253 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1254 | enum port port) |
da00bdcf VS |
1255 | { |
1256 | switch (port) { | |
1257 | case PORT_A: | |
1258 | return DP_AUX_CH_CTL(port); | |
1259 | case PORT_B: | |
1260 | case PORT_C: | |
1261 | case PORT_D: | |
1262 | return PCH_DP_AUX_CH_CTL(port); | |
1263 | default: | |
1264 | MISSING_CASE(port); | |
1265 | return DP_AUX_CH_CTL(PORT_A); | |
1266 | } | |
1267 | } | |
1268 | ||
f0f59a00 | 1269 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1270 | enum port port, int index) |
330e20ec VS |
1271 | { |
1272 | switch (port) { | |
1273 | case PORT_A: | |
1274 | return DP_AUX_CH_DATA(port, index); | |
1275 | case PORT_B: | |
1276 | case PORT_C: | |
1277 | case PORT_D: | |
1278 | return PCH_DP_AUX_CH_DATA(port, index); | |
1279 | default: | |
1280 | MISSING_CASE(port); | |
1281 | return DP_AUX_CH_DATA(PORT_A, index); | |
1282 | } | |
1283 | } | |
1284 | ||
f0f59a00 | 1285 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1286 | enum port port) |
da00bdcf | 1287 | { |
da00bdcf VS |
1288 | switch (port) { |
1289 | case PORT_A: | |
1290 | case PORT_B: | |
1291 | case PORT_C: | |
1292 | case PORT_D: | |
1293 | return DP_AUX_CH_CTL(port); | |
1294 | default: | |
1295 | MISSING_CASE(port); | |
1296 | return DP_AUX_CH_CTL(PORT_A); | |
1297 | } | |
1298 | } | |
1299 | ||
f0f59a00 | 1300 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1301 | enum port port, int index) |
330e20ec | 1302 | { |
330e20ec VS |
1303 | switch (port) { |
1304 | case PORT_A: | |
1305 | case PORT_B: | |
1306 | case PORT_C: | |
1307 | case PORT_D: | |
1308 | return DP_AUX_CH_DATA(port, index); | |
1309 | default: | |
1310 | MISSING_CASE(port); | |
1311 | return DP_AUX_CH_DATA(PORT_A, index); | |
1312 | } | |
1313 | } | |
1314 | ||
f0f59a00 | 1315 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1316 | enum port port) |
330e20ec VS |
1317 | { |
1318 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1319 | return skl_aux_ctl_reg(dev_priv, port); | |
1320 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1321 | return ilk_aux_ctl_reg(dev_priv, port); | |
1322 | else | |
1323 | return g4x_aux_ctl_reg(dev_priv, port); | |
1324 | } | |
1325 | ||
f0f59a00 | 1326 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1327 | enum port port, int index) |
330e20ec VS |
1328 | { |
1329 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1330 | return skl_aux_data_reg(dev_priv, port, index); | |
1331 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1332 | return ilk_aux_data_reg(dev_priv, port, index); | |
1333 | else | |
1334 | return g4x_aux_data_reg(dev_priv, port, index); | |
1335 | } | |
1336 | ||
1337 | static void intel_aux_reg_init(struct intel_dp *intel_dp) | |
1338 | { | |
1339 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); | |
8f7ce038 VS |
1340 | enum port port = intel_aux_port(dev_priv, |
1341 | dp_to_dig_port(intel_dp)->port); | |
330e20ec VS |
1342 | int i; |
1343 | ||
1344 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); | |
1345 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) | |
1346 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); | |
1347 | } | |
1348 | ||
9d1a1031 | 1349 | static void |
a121f4e5 VS |
1350 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
1351 | { | |
a121f4e5 VS |
1352 | kfree(intel_dp->aux.name); |
1353 | } | |
1354 | ||
7a418e34 | 1355 | static void |
b6339585 | 1356 | intel_dp_aux_init(struct intel_dp *intel_dp) |
9d1a1031 | 1357 | { |
33ad6626 JN |
1358 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1359 | enum port port = intel_dig_port->port; | |
ab2c0672 | 1360 | |
330e20ec | 1361 | intel_aux_reg_init(intel_dp); |
7a418e34 | 1362 | drm_dp_aux_init(&intel_dp->aux); |
8316f337 | 1363 | |
7a418e34 | 1364 | /* Failure to allocate our preferred name is not critical */ |
a121f4e5 | 1365 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
9d1a1031 | 1366 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
a4fc5ed6 KP |
1367 | } |
1368 | ||
e588fa18 | 1369 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
ed63baaf | 1370 | { |
e588fa18 | 1371 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
577c5430 | 1372 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
e588fa18 | 1373 | |
577c5430 NM |
1374 | if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || |
1375 | IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9)) | |
ed63baaf TS |
1376 | return true; |
1377 | else | |
1378 | return false; | |
1379 | } | |
1380 | ||
c6bb3538 DV |
1381 | static void |
1382 | intel_dp_set_clock(struct intel_encoder *encoder, | |
840b32b7 | 1383 | struct intel_crtc_state *pipe_config) |
c6bb3538 DV |
1384 | { |
1385 | struct drm_device *dev = encoder->base.dev; | |
6e266956 | 1386 | struct drm_i915_private *dev_priv = to_i915(dev); |
9dd4ffdf CML |
1387 | const struct dp_link_dpll *divisor = NULL; |
1388 | int i, count = 0; | |
c6bb3538 | 1389 | |
9beb5fea | 1390 | if (IS_G4X(dev_priv)) { |
9dd4ffdf CML |
1391 | divisor = gen4_dpll; |
1392 | count = ARRAY_SIZE(gen4_dpll); | |
6e266956 | 1393 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
9dd4ffdf CML |
1394 | divisor = pch_dpll; |
1395 | count = ARRAY_SIZE(pch_dpll); | |
920a14b2 | 1396 | } else if (IS_CHERRYVIEW(dev_priv)) { |
ef9348c8 CML |
1397 | divisor = chv_dpll; |
1398 | count = ARRAY_SIZE(chv_dpll); | |
11a914c2 | 1399 | } else if (IS_VALLEYVIEW(dev_priv)) { |
65ce4bf5 CML |
1400 | divisor = vlv_dpll; |
1401 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 1402 | } |
9dd4ffdf CML |
1403 | |
1404 | if (divisor && count) { | |
1405 | for (i = 0; i < count; i++) { | |
840b32b7 | 1406 | if (pipe_config->port_clock == divisor[i].clock) { |
9dd4ffdf CML |
1407 | pipe_config->dpll = divisor[i].dpll; |
1408 | pipe_config->clock_set = true; | |
1409 | break; | |
1410 | } | |
1411 | } | |
c6bb3538 DV |
1412 | } |
1413 | } | |
1414 | ||
0336400e VS |
1415 | static void snprintf_int_array(char *str, size_t len, |
1416 | const int *array, int nelem) | |
1417 | { | |
1418 | int i; | |
1419 | ||
1420 | str[0] = '\0'; | |
1421 | ||
1422 | for (i = 0; i < nelem; i++) { | |
b2f505be | 1423 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
0336400e VS |
1424 | if (r >= len) |
1425 | return; | |
1426 | str += r; | |
1427 | len -= r; | |
1428 | } | |
1429 | } | |
1430 | ||
1431 | static void intel_dp_print_rates(struct intel_dp *intel_dp) | |
1432 | { | |
0336400e | 1433 | const int *source_rates, *sink_rates; |
94ca719e VS |
1434 | int source_len, sink_len, common_len; |
1435 | int common_rates[DP_MAX_SUPPORTED_RATES]; | |
0336400e VS |
1436 | char str[128]; /* FIXME: too big for stack? */ |
1437 | ||
1438 | if ((drm_debug & DRM_UT_KMS) == 0) | |
1439 | return; | |
1440 | ||
e588fa18 | 1441 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
0336400e VS |
1442 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
1443 | DRM_DEBUG_KMS("source rates: %s\n", str); | |
1444 | ||
1445 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); | |
1446 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); | |
1447 | DRM_DEBUG_KMS("sink rates: %s\n", str); | |
1448 | ||
94ca719e VS |
1449 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1450 | snprintf_int_array(str, sizeof(str), common_rates, common_len); | |
1451 | DRM_DEBUG_KMS("common rates: %s\n", str); | |
0336400e VS |
1452 | } |
1453 | ||
489375c8 | 1454 | bool |
7b3fc170 | 1455 | __intel_dp_read_desc(struct intel_dp *intel_dp, struct intel_dp_desc *desc) |
0e390a33 | 1456 | { |
7b3fc170 ID |
1457 | u32 base = drm_dp_is_branch(intel_dp->dpcd) ? DP_BRANCH_OUI : |
1458 | DP_SINK_OUI; | |
0e390a33 | 1459 | |
7b3fc170 ID |
1460 | return drm_dp_dpcd_read(&intel_dp->aux, base, desc, sizeof(*desc)) == |
1461 | sizeof(*desc); | |
0e390a33 MK |
1462 | } |
1463 | ||
12a47a42 | 1464 | bool intel_dp_read_desc(struct intel_dp *intel_dp) |
1a2724fa | 1465 | { |
7b3fc170 ID |
1466 | struct intel_dp_desc *desc = &intel_dp->desc; |
1467 | bool oui_sup = intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & | |
1468 | DP_OUI_SUPPORT; | |
1469 | int dev_id_len; | |
1a2724fa | 1470 | |
7b3fc170 ID |
1471 | if (!__intel_dp_read_desc(intel_dp, desc)) |
1472 | return false; | |
1a2724fa | 1473 | |
7b3fc170 ID |
1474 | dev_id_len = strnlen(desc->device_id, sizeof(desc->device_id)); |
1475 | DRM_DEBUG_KMS("DP %s: OUI %*phD%s dev-ID %*pE HW-rev %d.%d SW-rev %d.%d\n", | |
1476 | drm_dp_is_branch(intel_dp->dpcd) ? "branch" : "sink", | |
1477 | (int)sizeof(desc->oui), desc->oui, oui_sup ? "" : "(NS)", | |
1478 | dev_id_len, desc->device_id, | |
1479 | desc->hw_rev >> 4, desc->hw_rev & 0xf, | |
1480 | desc->sw_major_rev, desc->sw_minor_rev); | |
1a2724fa | 1481 | |
7b3fc170 | 1482 | return true; |
1a2724fa MK |
1483 | } |
1484 | ||
f4896f15 | 1485 | static int rate_to_index(int find, const int *rates) |
a8f3ef61 SJ |
1486 | { |
1487 | int i = 0; | |
1488 | ||
1489 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) | |
1490 | if (find == rates[i]) | |
1491 | break; | |
1492 | ||
1493 | return i; | |
1494 | } | |
1495 | ||
50fec21a VS |
1496 | int |
1497 | intel_dp_max_link_rate(struct intel_dp *intel_dp) | |
1498 | { | |
1499 | int rates[DP_MAX_SUPPORTED_RATES] = {}; | |
1500 | int len; | |
1501 | ||
94ca719e | 1502 | len = intel_dp_common_rates(intel_dp, rates); |
50fec21a VS |
1503 | if (WARN_ON(len <= 0)) |
1504 | return 162000; | |
1505 | ||
1354f734 | 1506 | return rates[len - 1]; |
50fec21a VS |
1507 | } |
1508 | ||
ed4e9c1d VS |
1509 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1510 | { | |
94ca719e | 1511 | return rate_to_index(rate, intel_dp->sink_rates); |
ed4e9c1d VS |
1512 | } |
1513 | ||
94223d04 ACO |
1514 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1515 | uint8_t *link_bw, uint8_t *rate_select) | |
04a60f9f VS |
1516 | { |
1517 | if (intel_dp->num_sink_rates) { | |
1518 | *link_bw = 0; | |
1519 | *rate_select = | |
1520 | intel_dp_rate_select(intel_dp, port_clock); | |
1521 | } else { | |
1522 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); | |
1523 | *rate_select = 0; | |
1524 | } | |
1525 | } | |
1526 | ||
f580bea9 JN |
1527 | static int intel_dp_compute_bpp(struct intel_dp *intel_dp, |
1528 | struct intel_crtc_state *pipe_config) | |
f9bb705e MK |
1529 | { |
1530 | int bpp, bpc; | |
1531 | ||
1532 | bpp = pipe_config->pipe_bpp; | |
1533 | bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports); | |
1534 | ||
1535 | if (bpc > 0) | |
1536 | bpp = min(bpp, 3*bpc); | |
1537 | ||
1538 | return bpp; | |
1539 | } | |
1540 | ||
00c09d70 | 1541 | bool |
5bfe2ac0 | 1542 | intel_dp_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
1543 | struct intel_crtc_state *pipe_config, |
1544 | struct drm_connector_state *conn_state) | |
a4fc5ed6 | 1545 | { |
dd11bc10 | 1546 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2d112de7 | 1547 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
5bfe2ac0 | 1548 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1549 | enum port port = dp_to_dig_port(intel_dp)->port; |
84556d58 | 1550 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
dd06f90e | 1551 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
a4fc5ed6 | 1552 | int lane_count, clock; |
56071a20 | 1553 | int min_lane_count = 1; |
eeb6324d | 1554 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
06ea66b6 | 1555 | /* Conveniently, the link BW constants become indices with a shift...*/ |
56071a20 | 1556 | int min_clock = 0; |
a8f3ef61 | 1557 | int max_clock; |
083f9560 | 1558 | int bpp, mode_rate; |
ff9a6750 | 1559 | int link_avail, link_clock; |
94ca719e VS |
1560 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
1561 | int common_len; | |
04a60f9f | 1562 | uint8_t link_bw, rate_select; |
a8f3ef61 | 1563 | |
94ca719e | 1564 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
a8f3ef61 SJ |
1565 | |
1566 | /* No common link rates between source and sink */ | |
94ca719e | 1567 | WARN_ON(common_len <= 0); |
a8f3ef61 | 1568 | |
94ca719e | 1569 | max_clock = common_len - 1; |
a4fc5ed6 | 1570 | |
4f8036a2 | 1571 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) |
5bfe2ac0 DV |
1572 | pipe_config->has_pch_encoder = true; |
1573 | ||
f769cd24 | 1574 | pipe_config->has_drrs = false; |
9fcb1704 | 1575 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
a4fc5ed6 | 1576 | |
dd06f90e JN |
1577 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
1578 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
1579 | adjusted_mode); | |
a1b2278e | 1580 | |
dd11bc10 | 1581 | if (INTEL_GEN(dev_priv) >= 9) { |
a1b2278e | 1582 | int ret; |
e435d6e5 | 1583 | ret = skl_update_scaler_crtc(pipe_config); |
a1b2278e CK |
1584 | if (ret) |
1585 | return ret; | |
1586 | } | |
1587 | ||
49cff963 | 1588 | if (HAS_GMCH_DISPLAY(dev_priv)) |
2dd24552 JB |
1589 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
1590 | intel_connector->panel.fitting_mode); | |
1591 | else | |
b074cec8 JB |
1592 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
1593 | intel_connector->panel.fitting_mode); | |
0d3a1bee ZY |
1594 | } |
1595 | ||
cb1793ce | 1596 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
1597 | return false; |
1598 | ||
083f9560 | 1599 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
a8f3ef61 | 1600 | "max bw %d pixel clock %iKHz\n", |
94ca719e | 1601 | max_lane_count, common_rates[max_clock], |
241bfc38 | 1602 | adjusted_mode->crtc_clock); |
083f9560 | 1603 | |
36008365 DV |
1604 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1605 | * bpc in between. */ | |
f9bb705e | 1606 | bpp = intel_dp_compute_bpp(intel_dp, pipe_config); |
56071a20 | 1607 | if (is_edp(intel_dp)) { |
22ce5628 TS |
1608 | |
1609 | /* Get bpp from vbt only for panels that dont have bpp in edid */ | |
1610 | if (intel_connector->base.display_info.bpc == 0 && | |
6aa23e65 | 1611 | (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { |
56071a20 | 1612 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
6aa23e65 JN |
1613 | dev_priv->vbt.edp.bpp); |
1614 | bpp = dev_priv->vbt.edp.bpp; | |
56071a20 JN |
1615 | } |
1616 | ||
344c5bbc JN |
1617 | /* |
1618 | * Use the maximum clock and number of lanes the eDP panel | |
1619 | * advertizes being capable of. The panels are generally | |
1620 | * designed to support only a single clock and lane | |
1621 | * configuration, and typically these values correspond to the | |
1622 | * native resolution of the panel. | |
1623 | */ | |
1624 | min_lane_count = max_lane_count; | |
1625 | min_clock = max_clock; | |
7984211e | 1626 | } |
657445fe | 1627 | |
36008365 | 1628 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
1629 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1630 | bpp); | |
36008365 | 1631 | |
c6930992 | 1632 | for (clock = min_clock; clock <= max_clock; clock++) { |
a8f3ef61 SJ |
1633 | for (lane_count = min_lane_count; |
1634 | lane_count <= max_lane_count; | |
1635 | lane_count <<= 1) { | |
1636 | ||
94ca719e | 1637 | link_clock = common_rates[clock]; |
36008365 DV |
1638 | link_avail = intel_dp_max_data_rate(link_clock, |
1639 | lane_count); | |
1640 | ||
1641 | if (mode_rate <= link_avail) { | |
1642 | goto found; | |
1643 | } | |
1644 | } | |
1645 | } | |
1646 | } | |
c4867936 | 1647 | |
36008365 | 1648 | return false; |
3685a8f3 | 1649 | |
36008365 | 1650 | found: |
55bc60db VS |
1651 | if (intel_dp->color_range_auto) { |
1652 | /* | |
1653 | * See: | |
1654 | * CEA-861-E - 5.1 Default Encoding Parameters | |
1655 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
1656 | */ | |
0f2a2a75 VS |
1657 | pipe_config->limited_color_range = |
1658 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; | |
1659 | } else { | |
1660 | pipe_config->limited_color_range = | |
1661 | intel_dp->limited_color_range; | |
55bc60db VS |
1662 | } |
1663 | ||
90a6b7b0 | 1664 | pipe_config->lane_count = lane_count; |
a8f3ef61 | 1665 | |
657445fe | 1666 | pipe_config->pipe_bpp = bpp; |
94ca719e | 1667 | pipe_config->port_clock = common_rates[clock]; |
a4fc5ed6 | 1668 | |
04a60f9f VS |
1669 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
1670 | &link_bw, &rate_select); | |
1671 | ||
1672 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", | |
1673 | link_bw, rate_select, pipe_config->lane_count, | |
ff9a6750 | 1674 | pipe_config->port_clock, bpp); |
36008365 DV |
1675 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1676 | mode_rate, link_avail); | |
a4fc5ed6 | 1677 | |
03afc4a2 | 1678 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
1679 | adjusted_mode->crtc_clock, |
1680 | pipe_config->port_clock, | |
03afc4a2 | 1681 | &pipe_config->dp_m_n); |
9d1a455b | 1682 | |
439d7ac0 | 1683 | if (intel_connector->panel.downclock_mode != NULL && |
96178eeb | 1684 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
f769cd24 | 1685 | pipe_config->has_drrs = true; |
439d7ac0 PB |
1686 | intel_link_compute_m_n(bpp, lane_count, |
1687 | intel_connector->panel.downclock_mode->clock, | |
1688 | pipe_config->port_clock, | |
1689 | &pipe_config->dp_m2_n2); | |
1690 | } | |
1691 | ||
14d41b3b VS |
1692 | /* |
1693 | * DPLL0 VCO may need to be adjusted to get the correct | |
1694 | * clock for eDP. This will affect cdclk as well. | |
1695 | */ | |
1696 | if (is_edp(intel_dp) && | |
1697 | (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) { | |
1698 | int vco; | |
1699 | ||
1700 | switch (pipe_config->port_clock / 2) { | |
1701 | case 108000: | |
1702 | case 216000: | |
63911d72 | 1703 | vco = 8640000; |
14d41b3b VS |
1704 | break; |
1705 | default: | |
63911d72 | 1706 | vco = 8100000; |
14d41b3b VS |
1707 | break; |
1708 | } | |
1709 | ||
1710 | to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco; | |
1711 | } | |
1712 | ||
4f8036a2 | 1713 | if (!HAS_DDI(dev_priv)) |
840b32b7 | 1714 | intel_dp_set_clock(encoder, pipe_config); |
c6bb3538 | 1715 | |
03afc4a2 | 1716 | return true; |
a4fc5ed6 KP |
1717 | } |
1718 | ||
901c2daf | 1719 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
dfa10480 ACO |
1720 | int link_rate, uint8_t lane_count, |
1721 | bool link_mst) | |
901c2daf | 1722 | { |
dfa10480 ACO |
1723 | intel_dp->link_rate = link_rate; |
1724 | intel_dp->lane_count = lane_count; | |
1725 | intel_dp->link_mst = link_mst; | |
901c2daf VS |
1726 | } |
1727 | ||
85cb48a1 ML |
1728 | static void intel_dp_prepare(struct intel_encoder *encoder, |
1729 | struct intel_crtc_state *pipe_config) | |
a4fc5ed6 | 1730 | { |
b934223d | 1731 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1732 | struct drm_i915_private *dev_priv = to_i915(dev); |
b934223d | 1733 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1734 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d | 1735 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
85cb48a1 | 1736 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
a4fc5ed6 | 1737 | |
dfa10480 ACO |
1738 | intel_dp_set_link_params(intel_dp, pipe_config->port_clock, |
1739 | pipe_config->lane_count, | |
1740 | intel_crtc_has_type(pipe_config, | |
1741 | INTEL_OUTPUT_DP_MST)); | |
901c2daf | 1742 | |
417e822d | 1743 | /* |
1a2eb460 | 1744 | * There are four kinds of DP registers: |
417e822d KP |
1745 | * |
1746 | * IBX PCH | |
1a2eb460 KP |
1747 | * SNB CPU |
1748 | * IVB CPU | |
417e822d KP |
1749 | * CPT PCH |
1750 | * | |
1751 | * IBX PCH and CPU are the same for almost everything, | |
1752 | * except that the CPU DP PLL is configured in this | |
1753 | * register | |
1754 | * | |
1755 | * CPT PCH is quite different, having many bits moved | |
1756 | * to the TRANS_DP_CTL register instead. That | |
1757 | * configuration happens (oddly) in ironlake_pch_enable | |
1758 | */ | |
9c9e7927 | 1759 | |
417e822d KP |
1760 | /* Preserve the BIOS-computed detected bit. This is |
1761 | * supposed to be read-only. | |
1762 | */ | |
1763 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 1764 | |
417e822d | 1765 | /* Handle DP bits in common between all three register formats */ |
417e822d | 1766 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
85cb48a1 | 1767 | intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); |
a4fc5ed6 | 1768 | |
417e822d | 1769 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 1770 | |
5db94019 | 1771 | if (IS_GEN7(dev_priv) && port == PORT_A) { |
1a2eb460 KP |
1772 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1773 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1774 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1775 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1776 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
1777 | ||
6aba5b6c | 1778 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
1779 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1780 | ||
7c62a164 | 1781 | intel_dp->DP |= crtc->pipe << 29; |
6e266956 | 1782 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
e3ef4479 VS |
1783 | u32 trans_dp; |
1784 | ||
39e5fa88 | 1785 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3ef4479 VS |
1786 | |
1787 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
1788 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
1789 | trans_dp |= TRANS_DP_ENH_FRAMING; | |
1790 | else | |
1791 | trans_dp &= ~TRANS_DP_ENH_FRAMING; | |
1792 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); | |
39e5fa88 | 1793 | } else { |
c99f53f7 | 1794 | if (IS_G4X(dev_priv) && pipe_config->limited_color_range) |
0f2a2a75 | 1795 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
417e822d KP |
1796 | |
1797 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
1798 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1799 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1800 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1801 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
1802 | ||
6aba5b6c | 1803 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
1804 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1805 | ||
920a14b2 | 1806 | if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 1807 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
39e5fa88 VS |
1808 | else if (crtc->pipe == PIPE_B) |
1809 | intel_dp->DP |= DP_PIPEB_SELECT; | |
32f9d658 | 1810 | } |
a4fc5ed6 KP |
1811 | } |
1812 | ||
ffd6749d PZ |
1813 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1814 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 1815 | |
1a5ef5b7 PZ |
1816 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1817 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 1818 | |
ffd6749d PZ |
1819 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1820 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 1821 | |
de9c1b6b ID |
1822 | static void intel_pps_verify_state(struct drm_i915_private *dev_priv, |
1823 | struct intel_dp *intel_dp); | |
1824 | ||
4be73780 | 1825 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
1826 | u32 mask, |
1827 | u32 value) | |
bd943159 | 1828 | { |
30add22d | 1829 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 1830 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1831 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
453c5420 | 1832 | |
e39b999a VS |
1833 | lockdep_assert_held(&dev_priv->pps_mutex); |
1834 | ||
de9c1b6b ID |
1835 | intel_pps_verify_state(dev_priv, intel_dp); |
1836 | ||
bf13e81b JN |
1837 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1838 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 1839 | |
99ea7127 | 1840 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
1841 | mask, value, |
1842 | I915_READ(pp_stat_reg), | |
1843 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1844 | |
9036ff06 CW |
1845 | if (intel_wait_for_register(dev_priv, |
1846 | pp_stat_reg, mask, value, | |
1847 | 5000)) | |
99ea7127 | 1848 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
1849 | I915_READ(pp_stat_reg), |
1850 | I915_READ(pp_ctrl_reg)); | |
54c136d4 CW |
1851 | |
1852 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 1853 | } |
32ce697c | 1854 | |
4be73780 | 1855 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
1856 | { |
1857 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 1858 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
1859 | } |
1860 | ||
4be73780 | 1861 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
1862 | { |
1863 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 1864 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
1865 | } |
1866 | ||
4be73780 | 1867 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 | 1868 | { |
d28d4731 AK |
1869 | ktime_t panel_power_on_time; |
1870 | s64 panel_power_off_duration; | |
1871 | ||
99ea7127 | 1872 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
dce56b3c | 1873 | |
d28d4731 AK |
1874 | /* take the difference of currrent time and panel power off time |
1875 | * and then make panel wait for t11_t12 if needed. */ | |
1876 | panel_power_on_time = ktime_get_boottime(); | |
1877 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); | |
1878 | ||
dce56b3c PZ |
1879 | /* When we disable the VDD override bit last we have to do the manual |
1880 | * wait. */ | |
d28d4731 AK |
1881 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
1882 | wait_remaining_ms_from_jiffies(jiffies, | |
1883 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); | |
dce56b3c | 1884 | |
4be73780 | 1885 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
1886 | } |
1887 | ||
4be73780 | 1888 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
1889 | { |
1890 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
1891 | intel_dp->backlight_on_delay); | |
1892 | } | |
1893 | ||
4be73780 | 1894 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
1895 | { |
1896 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
1897 | intel_dp->backlight_off_delay); | |
1898 | } | |
99ea7127 | 1899 | |
832dd3c1 KP |
1900 | /* Read the current pp_control value, unlocking the register if it |
1901 | * is locked | |
1902 | */ | |
1903 | ||
453c5420 | 1904 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 1905 | { |
453c5420 | 1906 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 1907 | struct drm_i915_private *dev_priv = to_i915(dev); |
453c5420 | 1908 | u32 control; |
832dd3c1 | 1909 | |
e39b999a VS |
1910 | lockdep_assert_held(&dev_priv->pps_mutex); |
1911 | ||
bf13e81b | 1912 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
8090ba8c ID |
1913 | if (WARN_ON(!HAS_DDI(dev_priv) && |
1914 | (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { | |
b0a08bec VK |
1915 | control &= ~PANEL_UNLOCK_MASK; |
1916 | control |= PANEL_UNLOCK_REGS; | |
1917 | } | |
832dd3c1 | 1918 | return control; |
bd943159 KP |
1919 | } |
1920 | ||
951468f3 VS |
1921 | /* |
1922 | * Must be paired with edp_panel_vdd_off(). | |
1923 | * Must hold pps_mutex around the whole on/off sequence. | |
1924 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
1925 | */ | |
1e0560e0 | 1926 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 1927 | { |
30add22d | 1928 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4e6e1a54 ID |
1929 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1930 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fac5e23e | 1931 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e6e1a54 | 1932 | enum intel_display_power_domain power_domain; |
5d613501 | 1933 | u32 pp; |
f0f59a00 | 1934 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 1935 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 1936 | |
e39b999a VS |
1937 | lockdep_assert_held(&dev_priv->pps_mutex); |
1938 | ||
97af61f5 | 1939 | if (!is_edp(intel_dp)) |
adddaaf4 | 1940 | return false; |
bd943159 | 1941 | |
2c623c11 | 1942 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
bd943159 | 1943 | intel_dp->want_panel_vdd = true; |
99ea7127 | 1944 | |
4be73780 | 1945 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 1946 | return need_to_disable; |
b0665d57 | 1947 | |
25f78f58 | 1948 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4e6e1a54 | 1949 | intel_display_power_get(dev_priv, power_domain); |
e9cb81a2 | 1950 | |
3936fcf4 VS |
1951 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
1952 | port_name(intel_dig_port->port)); | |
bd943159 | 1953 | |
4be73780 DV |
1954 | if (!edp_have_panel_power(intel_dp)) |
1955 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 1956 | |
453c5420 | 1957 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 1958 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 1959 | |
bf13e81b JN |
1960 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1961 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
1962 | |
1963 | I915_WRITE(pp_ctrl_reg, pp); | |
1964 | POSTING_READ(pp_ctrl_reg); | |
1965 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1966 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
1967 | /* |
1968 | * If the panel wasn't on, delay before accessing aux channel | |
1969 | */ | |
4be73780 | 1970 | if (!edp_have_panel_power(intel_dp)) { |
3936fcf4 VS |
1971 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
1972 | port_name(intel_dig_port->port)); | |
f01eca2e | 1973 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 1974 | } |
adddaaf4 JN |
1975 | |
1976 | return need_to_disable; | |
1977 | } | |
1978 | ||
951468f3 VS |
1979 | /* |
1980 | * Must be paired with intel_edp_panel_vdd_off() or | |
1981 | * intel_edp_panel_off(). | |
1982 | * Nested calls to these functions are not allowed since | |
1983 | * we drop the lock. Caller must use some higher level | |
1984 | * locking to prevent nested calls from other threads. | |
1985 | */ | |
b80d6c78 | 1986 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 | 1987 | { |
c695b6b6 | 1988 | bool vdd; |
adddaaf4 | 1989 | |
c695b6b6 VS |
1990 | if (!is_edp(intel_dp)) |
1991 | return; | |
1992 | ||
773538e8 | 1993 | pps_lock(intel_dp); |
c695b6b6 | 1994 | vdd = edp_panel_vdd_on(intel_dp); |
773538e8 | 1995 | pps_unlock(intel_dp); |
c695b6b6 | 1996 | |
e2c719b7 | 1997 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
3936fcf4 | 1998 | port_name(dp_to_dig_port(intel_dp)->port)); |
5d613501 JB |
1999 | } |
2000 | ||
4be73780 | 2001 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 2002 | { |
30add22d | 2003 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2004 | struct drm_i915_private *dev_priv = to_i915(dev); |
be2c9196 VS |
2005 | struct intel_digital_port *intel_dig_port = |
2006 | dp_to_dig_port(intel_dp); | |
2007 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
2008 | enum intel_display_power_domain power_domain; | |
5d613501 | 2009 | u32 pp; |
f0f59a00 | 2010 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
5d613501 | 2011 | |
e39b999a | 2012 | lockdep_assert_held(&dev_priv->pps_mutex); |
a0e99e68 | 2013 | |
15e899a0 | 2014 | WARN_ON(intel_dp->want_panel_vdd); |
4e6e1a54 | 2015 | |
15e899a0 | 2016 | if (!edp_have_panel_vdd(intel_dp)) |
be2c9196 | 2017 | return; |
b0665d57 | 2018 | |
3936fcf4 VS |
2019 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
2020 | port_name(intel_dig_port->port)); | |
bd943159 | 2021 | |
be2c9196 VS |
2022 | pp = ironlake_get_pp_control(intel_dp); |
2023 | pp &= ~EDP_FORCE_VDD; | |
453c5420 | 2024 | |
be2c9196 VS |
2025 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2026 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
99ea7127 | 2027 | |
be2c9196 VS |
2028 | I915_WRITE(pp_ctrl_reg, pp); |
2029 | POSTING_READ(pp_ctrl_reg); | |
90791a5c | 2030 | |
be2c9196 VS |
2031 | /* Make sure sequencer is idle before allowing subsequent activity */ |
2032 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
2033 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
e9cb81a2 | 2034 | |
5a162e22 | 2035 | if ((pp & PANEL_POWER_ON) == 0) |
d28d4731 | 2036 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
e9cb81a2 | 2037 | |
25f78f58 | 2038 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
be2c9196 | 2039 | intel_display_power_put(dev_priv, power_domain); |
bd943159 | 2040 | } |
5d613501 | 2041 | |
4be73780 | 2042 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
2043 | { |
2044 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
2045 | struct intel_dp, panel_vdd_work); | |
bd943159 | 2046 | |
773538e8 | 2047 | pps_lock(intel_dp); |
15e899a0 VS |
2048 | if (!intel_dp->want_panel_vdd) |
2049 | edp_panel_vdd_off_sync(intel_dp); | |
773538e8 | 2050 | pps_unlock(intel_dp); |
bd943159 KP |
2051 | } |
2052 | ||
aba86890 ID |
2053 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
2054 | { | |
2055 | unsigned long delay; | |
2056 | ||
2057 | /* | |
2058 | * Queue the timer to fire a long time from now (relative to the power | |
2059 | * down delay) to keep the panel power up across a sequence of | |
2060 | * operations. | |
2061 | */ | |
2062 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); | |
2063 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); | |
2064 | } | |
2065 | ||
951468f3 VS |
2066 | /* |
2067 | * Must be paired with edp_panel_vdd_on(). | |
2068 | * Must hold pps_mutex around the whole on/off sequence. | |
2069 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2070 | */ | |
4be73780 | 2071 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 2072 | { |
fac5e23e | 2073 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
e39b999a VS |
2074 | |
2075 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2076 | ||
97af61f5 KP |
2077 | if (!is_edp(intel_dp)) |
2078 | return; | |
5d613501 | 2079 | |
e2c719b7 | 2080 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
3936fcf4 | 2081 | port_name(dp_to_dig_port(intel_dp)->port)); |
f2e8b18a | 2082 | |
bd943159 KP |
2083 | intel_dp->want_panel_vdd = false; |
2084 | ||
aba86890 | 2085 | if (sync) |
4be73780 | 2086 | edp_panel_vdd_off_sync(intel_dp); |
aba86890 ID |
2087 | else |
2088 | edp_panel_vdd_schedule_off(intel_dp); | |
5d613501 JB |
2089 | } |
2090 | ||
9f0fb5be | 2091 | static void edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 2092 | { |
30add22d | 2093 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2094 | struct drm_i915_private *dev_priv = to_i915(dev); |
99ea7127 | 2095 | u32 pp; |
f0f59a00 | 2096 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2097 | |
9f0fb5be VS |
2098 | lockdep_assert_held(&dev_priv->pps_mutex); |
2099 | ||
97af61f5 | 2100 | if (!is_edp(intel_dp)) |
bd943159 | 2101 | return; |
99ea7127 | 2102 | |
3936fcf4 VS |
2103 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
2104 | port_name(dp_to_dig_port(intel_dp)->port)); | |
e39b999a | 2105 | |
e7a89ace VS |
2106 | if (WARN(edp_have_panel_power(intel_dp), |
2107 | "eDP port %c panel power already on\n", | |
2108 | port_name(dp_to_dig_port(intel_dp)->port))) | |
9f0fb5be | 2109 | return; |
9934c132 | 2110 | |
4be73780 | 2111 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 2112 | |
bf13e81b | 2113 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2114 | pp = ironlake_get_pp_control(intel_dp); |
5db94019 | 2115 | if (IS_GEN5(dev_priv)) { |
05ce1a49 KP |
2116 | /* ILK workaround: disable reset around power sequence */ |
2117 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
2118 | I915_WRITE(pp_ctrl_reg, pp); |
2119 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2120 | } |
37c6c9b0 | 2121 | |
5a162e22 | 2122 | pp |= PANEL_POWER_ON; |
5db94019 | 2123 | if (!IS_GEN5(dev_priv)) |
99ea7127 KP |
2124 | pp |= PANEL_POWER_RESET; |
2125 | ||
453c5420 JB |
2126 | I915_WRITE(pp_ctrl_reg, pp); |
2127 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2128 | |
4be73780 | 2129 | wait_panel_on(intel_dp); |
dce56b3c | 2130 | intel_dp->last_power_on = jiffies; |
9934c132 | 2131 | |
5db94019 | 2132 | if (IS_GEN5(dev_priv)) { |
05ce1a49 | 2133 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
bf13e81b JN |
2134 | I915_WRITE(pp_ctrl_reg, pp); |
2135 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2136 | } |
9f0fb5be | 2137 | } |
e39b999a | 2138 | |
9f0fb5be VS |
2139 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
2140 | { | |
2141 | if (!is_edp(intel_dp)) | |
2142 | return; | |
2143 | ||
2144 | pps_lock(intel_dp); | |
2145 | edp_panel_on(intel_dp); | |
773538e8 | 2146 | pps_unlock(intel_dp); |
9934c132 JB |
2147 | } |
2148 | ||
9f0fb5be VS |
2149 | |
2150 | static void edp_panel_off(struct intel_dp *intel_dp) | |
9934c132 | 2151 | { |
4e6e1a54 ID |
2152 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2153 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
30add22d | 2154 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2155 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e6e1a54 | 2156 | enum intel_display_power_domain power_domain; |
99ea7127 | 2157 | u32 pp; |
f0f59a00 | 2158 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2159 | |
9f0fb5be VS |
2160 | lockdep_assert_held(&dev_priv->pps_mutex); |
2161 | ||
97af61f5 KP |
2162 | if (!is_edp(intel_dp)) |
2163 | return; | |
37c6c9b0 | 2164 | |
3936fcf4 VS |
2165 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2166 | port_name(dp_to_dig_port(intel_dp)->port)); | |
37c6c9b0 | 2167 | |
3936fcf4 VS |
2168 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2169 | port_name(dp_to_dig_port(intel_dp)->port)); | |
24f3e092 | 2170 | |
453c5420 | 2171 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
2172 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2173 | * panels get very unhappy and cease to work. */ | |
5a162e22 | 2174 | pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
b3064154 | 2175 | EDP_BLC_ENABLE); |
453c5420 | 2176 | |
bf13e81b | 2177 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2178 | |
849e39f5 PZ |
2179 | intel_dp->want_panel_vdd = false; |
2180 | ||
453c5420 JB |
2181 | I915_WRITE(pp_ctrl_reg, pp); |
2182 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2183 | |
d28d4731 | 2184 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
4be73780 | 2185 | wait_panel_off(intel_dp); |
849e39f5 PZ |
2186 | |
2187 | /* We got a reference when we enabled the VDD. */ | |
25f78f58 | 2188 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4e6e1a54 | 2189 | intel_display_power_put(dev_priv, power_domain); |
9f0fb5be | 2190 | } |
e39b999a | 2191 | |
9f0fb5be VS |
2192 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2193 | { | |
2194 | if (!is_edp(intel_dp)) | |
2195 | return; | |
e39b999a | 2196 | |
9f0fb5be VS |
2197 | pps_lock(intel_dp); |
2198 | edp_panel_off(intel_dp); | |
773538e8 | 2199 | pps_unlock(intel_dp); |
9934c132 JB |
2200 | } |
2201 | ||
1250d107 JN |
2202 | /* Enable backlight in the panel power control. */ |
2203 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) | |
32f9d658 | 2204 | { |
da63a9f2 PZ |
2205 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2206 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 2207 | struct drm_i915_private *dev_priv = to_i915(dev); |
32f9d658 | 2208 | u32 pp; |
f0f59a00 | 2209 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2210 | |
01cb9ea6 JB |
2211 | /* |
2212 | * If we enable the backlight right away following a panel power | |
2213 | * on, we may see slight flicker as the panel syncs with the eDP | |
2214 | * link. So delay a bit to make sure the image is solid before | |
2215 | * allowing it to appear. | |
2216 | */ | |
4be73780 | 2217 | wait_backlight_on(intel_dp); |
e39b999a | 2218 | |
773538e8 | 2219 | pps_lock(intel_dp); |
e39b999a | 2220 | |
453c5420 | 2221 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2222 | pp |= EDP_BLC_ENABLE; |
453c5420 | 2223 | |
bf13e81b | 2224 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2225 | |
2226 | I915_WRITE(pp_ctrl_reg, pp); | |
2227 | POSTING_READ(pp_ctrl_reg); | |
e39b999a | 2228 | |
773538e8 | 2229 | pps_unlock(intel_dp); |
32f9d658 ZW |
2230 | } |
2231 | ||
1250d107 JN |
2232 | /* Enable backlight PWM and backlight PP control. */ |
2233 | void intel_edp_backlight_on(struct intel_dp *intel_dp) | |
2234 | { | |
2235 | if (!is_edp(intel_dp)) | |
2236 | return; | |
2237 | ||
2238 | DRM_DEBUG_KMS("\n"); | |
2239 | ||
2240 | intel_panel_enable_backlight(intel_dp->attached_connector); | |
2241 | _intel_edp_backlight_on(intel_dp); | |
2242 | } | |
2243 | ||
2244 | /* Disable backlight in the panel power control. */ | |
2245 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) | |
32f9d658 | 2246 | { |
30add22d | 2247 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2248 | struct drm_i915_private *dev_priv = to_i915(dev); |
32f9d658 | 2249 | u32 pp; |
f0f59a00 | 2250 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2251 | |
f01eca2e KP |
2252 | if (!is_edp(intel_dp)) |
2253 | return; | |
2254 | ||
773538e8 | 2255 | pps_lock(intel_dp); |
e39b999a | 2256 | |
453c5420 | 2257 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2258 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 2259 | |
bf13e81b | 2260 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2261 | |
2262 | I915_WRITE(pp_ctrl_reg, pp); | |
2263 | POSTING_READ(pp_ctrl_reg); | |
f7d2323c | 2264 | |
773538e8 | 2265 | pps_unlock(intel_dp); |
e39b999a VS |
2266 | |
2267 | intel_dp->last_backlight_off = jiffies; | |
f7d2323c | 2268 | edp_wait_backlight_off(intel_dp); |
1250d107 | 2269 | } |
f7d2323c | 2270 | |
1250d107 JN |
2271 | /* Disable backlight PP control and backlight PWM. */ |
2272 | void intel_edp_backlight_off(struct intel_dp *intel_dp) | |
2273 | { | |
2274 | if (!is_edp(intel_dp)) | |
2275 | return; | |
2276 | ||
2277 | DRM_DEBUG_KMS("\n"); | |
f7d2323c | 2278 | |
1250d107 | 2279 | _intel_edp_backlight_off(intel_dp); |
f7d2323c | 2280 | intel_panel_disable_backlight(intel_dp->attached_connector); |
32f9d658 | 2281 | } |
a4fc5ed6 | 2282 | |
73580fb7 JN |
2283 | /* |
2284 | * Hook for controlling the panel power control backlight through the bl_power | |
2285 | * sysfs attribute. Take care to handle multiple calls. | |
2286 | */ | |
2287 | static void intel_edp_backlight_power(struct intel_connector *connector, | |
2288 | bool enable) | |
2289 | { | |
2290 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); | |
e39b999a VS |
2291 | bool is_enabled; |
2292 | ||
773538e8 | 2293 | pps_lock(intel_dp); |
e39b999a | 2294 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
773538e8 | 2295 | pps_unlock(intel_dp); |
73580fb7 JN |
2296 | |
2297 | if (is_enabled == enable) | |
2298 | return; | |
2299 | ||
23ba9373 JN |
2300 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2301 | enable ? "enable" : "disable"); | |
73580fb7 JN |
2302 | |
2303 | if (enable) | |
2304 | _intel_edp_backlight_on(intel_dp); | |
2305 | else | |
2306 | _intel_edp_backlight_off(intel_dp); | |
2307 | } | |
2308 | ||
64e1077a VS |
2309 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
2310 | { | |
2311 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2312 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
2313 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; | |
2314 | ||
2315 | I915_STATE_WARN(cur_state != state, | |
2316 | "DP port %c state assertion failure (expected %s, current %s)\n", | |
2317 | port_name(dig_port->port), | |
87ad3212 | 2318 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2319 | } |
2320 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) | |
2321 | ||
2322 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) | |
2323 | { | |
2324 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; | |
2325 | ||
2326 | I915_STATE_WARN(cur_state != state, | |
2327 | "eDP PLL state assertion failure (expected %s, current %s)\n", | |
87ad3212 | 2328 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2329 | } |
2330 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) | |
2331 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) | |
2332 | ||
85cb48a1 ML |
2333 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp, |
2334 | struct intel_crtc_state *pipe_config) | |
d240f20f | 2335 | { |
85cb48a1 | 2336 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
64e1077a | 2337 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d240f20f | 2338 | |
64e1077a VS |
2339 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2340 | assert_dp_port_disabled(intel_dp); | |
2341 | assert_edp_pll_disabled(dev_priv); | |
2bd2ad64 | 2342 | |
abfce949 | 2343 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
85cb48a1 | 2344 | pipe_config->port_clock); |
abfce949 VS |
2345 | |
2346 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; | |
2347 | ||
85cb48a1 | 2348 | if (pipe_config->port_clock == 162000) |
abfce949 VS |
2349 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
2350 | else | |
2351 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
2352 | ||
2353 | I915_WRITE(DP_A, intel_dp->DP); | |
2354 | POSTING_READ(DP_A); | |
2355 | udelay(500); | |
2356 | ||
6b23f3e8 VS |
2357 | /* |
2358 | * [DevILK] Work around required when enabling DP PLL | |
2359 | * while a pipe is enabled going to FDI: | |
2360 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI | |
2361 | * 2. Program DP PLL enable | |
2362 | */ | |
2363 | if (IS_GEN5(dev_priv)) | |
0f0f74bc | 2364 | intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); |
6b23f3e8 | 2365 | |
0767935e | 2366 | intel_dp->DP |= DP_PLL_ENABLE; |
6fec7662 | 2367 | |
0767935e | 2368 | I915_WRITE(DP_A, intel_dp->DP); |
298b0b39 JB |
2369 | POSTING_READ(DP_A); |
2370 | udelay(200); | |
d240f20f JB |
2371 | } |
2372 | ||
2bd2ad64 | 2373 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 2374 | { |
da63a9f2 | 2375 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
64e1077a VS |
2376 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2377 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
d240f20f | 2378 | |
64e1077a VS |
2379 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2380 | assert_dp_port_disabled(intel_dp); | |
2381 | assert_edp_pll_enabled(dev_priv); | |
2bd2ad64 | 2382 | |
abfce949 VS |
2383 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
2384 | ||
6fec7662 | 2385 | intel_dp->DP &= ~DP_PLL_ENABLE; |
0767935e | 2386 | |
6fec7662 | 2387 | I915_WRITE(DP_A, intel_dp->DP); |
1af5fa1b | 2388 | POSTING_READ(DP_A); |
d240f20f JB |
2389 | udelay(200); |
2390 | } | |
2391 | ||
c7ad3810 | 2392 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 2393 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
2394 | { |
2395 | int ret, i; | |
2396 | ||
2397 | /* Should have a valid DPCD by this point */ | |
2398 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
2399 | return; | |
2400 | ||
2401 | if (mode != DRM_MODE_DPMS_ON) { | |
9d1a1031 JN |
2402 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2403 | DP_SET_POWER_D3); | |
c7ad3810 JB |
2404 | } else { |
2405 | /* | |
2406 | * When turning on, we need to retry for 1ms to give the sink | |
2407 | * time to wake up. | |
2408 | */ | |
2409 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
2410 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2411 | DP_SET_POWER_D0); | |
c7ad3810 JB |
2412 | if (ret == 1) |
2413 | break; | |
2414 | msleep(1); | |
2415 | } | |
2416 | } | |
f9cac721 JN |
2417 | |
2418 | if (ret != 1) | |
2419 | DRM_DEBUG_KMS("failed to %s sink power state\n", | |
2420 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); | |
c7ad3810 JB |
2421 | } |
2422 | ||
19d8fe15 DV |
2423 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2424 | enum pipe *pipe) | |
d240f20f | 2425 | { |
19d8fe15 | 2426 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 2427 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 | 2428 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2429 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d129bea ID |
2430 | enum intel_display_power_domain power_domain; |
2431 | u32 tmp; | |
6fa9a5ec | 2432 | bool ret; |
6d129bea ID |
2433 | |
2434 | power_domain = intel_display_port_power_domain(encoder); | |
6fa9a5ec | 2435 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
2436 | return false; |
2437 | ||
6fa9a5ec ID |
2438 | ret = false; |
2439 | ||
6d129bea | 2440 | tmp = I915_READ(intel_dp->output_reg); |
19d8fe15 DV |
2441 | |
2442 | if (!(tmp & DP_PORT_EN)) | |
6fa9a5ec | 2443 | goto out; |
19d8fe15 | 2444 | |
5db94019 | 2445 | if (IS_GEN7(dev_priv) && port == PORT_A) { |
19d8fe15 | 2446 | *pipe = PORT_TO_PIPE_CPT(tmp); |
6e266956 | 2447 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
adc289d7 | 2448 | enum pipe p; |
19d8fe15 | 2449 | |
adc289d7 VS |
2450 | for_each_pipe(dev_priv, p) { |
2451 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); | |
2452 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { | |
2453 | *pipe = p; | |
6fa9a5ec ID |
2454 | ret = true; |
2455 | ||
2456 | goto out; | |
19d8fe15 DV |
2457 | } |
2458 | } | |
19d8fe15 | 2459 | |
4a0833ec | 2460 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
f0f59a00 | 2461 | i915_mmio_reg_offset(intel_dp->output_reg)); |
920a14b2 | 2462 | } else if (IS_CHERRYVIEW(dev_priv)) { |
39e5fa88 VS |
2463 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
2464 | } else { | |
2465 | *pipe = PORT_TO_PIPE(tmp); | |
4a0833ec | 2466 | } |
d240f20f | 2467 | |
6fa9a5ec ID |
2468 | ret = true; |
2469 | ||
2470 | out: | |
2471 | intel_display_power_put(dev_priv, power_domain); | |
2472 | ||
2473 | return ret; | |
19d8fe15 | 2474 | } |
d240f20f | 2475 | |
045ac3b5 | 2476 | static void intel_dp_get_config(struct intel_encoder *encoder, |
5cec258b | 2477 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
2478 | { |
2479 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 2480 | u32 tmp, flags = 0; |
63000ef6 | 2481 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2482 | struct drm_i915_private *dev_priv = to_i915(dev); |
63000ef6 XZ |
2483 | enum port port = dp_to_dig_port(intel_dp)->port; |
2484 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
045ac3b5 | 2485 | |
9ed109a7 | 2486 | tmp = I915_READ(intel_dp->output_reg); |
9fcb1704 JN |
2487 | |
2488 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; | |
9ed109a7 | 2489 | |
6e266956 | 2490 | if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
b81e34c2 VS |
2491 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2492 | ||
2493 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
63000ef6 XZ |
2494 | flags |= DRM_MODE_FLAG_PHSYNC; |
2495 | else | |
2496 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2497 | |
b81e34c2 | 2498 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
63000ef6 XZ |
2499 | flags |= DRM_MODE_FLAG_PVSYNC; |
2500 | else | |
2501 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2502 | } else { | |
39e5fa88 | 2503 | if (tmp & DP_SYNC_HS_HIGH) |
63000ef6 XZ |
2504 | flags |= DRM_MODE_FLAG_PHSYNC; |
2505 | else | |
2506 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2507 | |
39e5fa88 | 2508 | if (tmp & DP_SYNC_VS_HIGH) |
63000ef6 XZ |
2509 | flags |= DRM_MODE_FLAG_PVSYNC; |
2510 | else | |
2511 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2512 | } | |
045ac3b5 | 2513 | |
2d112de7 | 2514 | pipe_config->base.adjusted_mode.flags |= flags; |
f1f644dc | 2515 | |
c99f53f7 | 2516 | if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) |
8c875fca VS |
2517 | pipe_config->limited_color_range = true; |
2518 | ||
90a6b7b0 VS |
2519 | pipe_config->lane_count = |
2520 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; | |
2521 | ||
eb14cb74 VS |
2522 | intel_dp_get_m_n(crtc, pipe_config); |
2523 | ||
18442d08 | 2524 | if (port == PORT_A) { |
b377e0df | 2525 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
f1f644dc JB |
2526 | pipe_config->port_clock = 162000; |
2527 | else | |
2528 | pipe_config->port_clock = 270000; | |
2529 | } | |
18442d08 | 2530 | |
e3b247da VS |
2531 | pipe_config->base.adjusted_mode.crtc_clock = |
2532 | intel_dotclock_calculate(pipe_config->port_clock, | |
2533 | &pipe_config->dp_m_n); | |
7f16e5c1 | 2534 | |
6aa23e65 JN |
2535 | if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
2536 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { | |
c6cd2ee2 JN |
2537 | /* |
2538 | * This is a big fat ugly hack. | |
2539 | * | |
2540 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2541 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2542 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2543 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2544 | * max, not what it tells us to use. | |
2545 | * | |
2546 | * Note: This will still be broken if the eDP panel is not lit | |
2547 | * up by the BIOS, and thus we can't get the mode at module | |
2548 | * load. | |
2549 | */ | |
2550 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
2551 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
2552 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
c6cd2ee2 | 2553 | } |
045ac3b5 JB |
2554 | } |
2555 | ||
fd6bbda9 ML |
2556 | static void intel_disable_dp(struct intel_encoder *encoder, |
2557 | struct intel_crtc_state *old_crtc_state, | |
2558 | struct drm_connector_state *old_conn_state) | |
d240f20f | 2559 | { |
e8cb4558 | 2560 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
85cb48a1 | 2561 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
495a5bb8 | 2562 | |
85cb48a1 | 2563 | if (old_crtc_state->has_audio) |
495a5bb8 | 2564 | intel_audio_codec_disable(encoder); |
6cb49835 | 2565 | |
85cb48a1 | 2566 | if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv)) |
b32c6f48 RV |
2567 | intel_psr_disable(intel_dp); |
2568 | ||
6cb49835 DV |
2569 | /* Make sure the panel is off before trying to change the mode. But also |
2570 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 2571 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 2572 | intel_edp_backlight_off(intel_dp); |
fdbc3b1f | 2573 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 2574 | intel_edp_panel_off(intel_dp); |
3739850b | 2575 | |
08aff3fe | 2576 | /* disable the port before the pipe on g4x */ |
85cb48a1 | 2577 | if (INTEL_GEN(dev_priv) < 5) |
3739850b | 2578 | intel_dp_link_down(intel_dp); |
d240f20f JB |
2579 | } |
2580 | ||
fd6bbda9 ML |
2581 | static void ilk_post_disable_dp(struct intel_encoder *encoder, |
2582 | struct intel_crtc_state *old_crtc_state, | |
2583 | struct drm_connector_state *old_conn_state) | |
d240f20f | 2584 | { |
2bd2ad64 | 2585 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2586 | enum port port = dp_to_dig_port(intel_dp)->port; |
2bd2ad64 | 2587 | |
49277c31 | 2588 | intel_dp_link_down(intel_dp); |
abfce949 VS |
2589 | |
2590 | /* Only ilk+ has port A */ | |
08aff3fe VS |
2591 | if (port == PORT_A) |
2592 | ironlake_edp_pll_off(intel_dp); | |
49277c31 VS |
2593 | } |
2594 | ||
fd6bbda9 ML |
2595 | static void vlv_post_disable_dp(struct intel_encoder *encoder, |
2596 | struct intel_crtc_state *old_crtc_state, | |
2597 | struct drm_connector_state *old_conn_state) | |
49277c31 VS |
2598 | { |
2599 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2600 | ||
2601 | intel_dp_link_down(intel_dp); | |
2bd2ad64 DV |
2602 | } |
2603 | ||
fd6bbda9 ML |
2604 | static void chv_post_disable_dp(struct intel_encoder *encoder, |
2605 | struct intel_crtc_state *old_crtc_state, | |
2606 | struct drm_connector_state *old_conn_state) | |
a8f327fb VS |
2607 | { |
2608 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2609 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2610 | struct drm_i915_private *dev_priv = to_i915(dev); |
97fd4d5c | 2611 | |
a8f327fb VS |
2612 | intel_dp_link_down(intel_dp); |
2613 | ||
2614 | mutex_lock(&dev_priv->sb_lock); | |
2615 | ||
2616 | /* Assert data lane reset */ | |
2617 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 2618 | |
a580516d | 2619 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
2620 | } |
2621 | ||
7b13b58a VS |
2622 | static void |
2623 | _intel_dp_set_link_train(struct intel_dp *intel_dp, | |
2624 | uint32_t *DP, | |
2625 | uint8_t dp_train_pat) | |
2626 | { | |
2627 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2628 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 2629 | struct drm_i915_private *dev_priv = to_i915(dev); |
7b13b58a VS |
2630 | enum port port = intel_dig_port->port; |
2631 | ||
8b0878a0 PD |
2632 | if (dp_train_pat & DP_TRAINING_PATTERN_MASK) |
2633 | DRM_DEBUG_KMS("Using DP training pattern TPS%d\n", | |
2634 | dp_train_pat & DP_TRAINING_PATTERN_MASK); | |
2635 | ||
4f8036a2 | 2636 | if (HAS_DDI(dev_priv)) { |
7b13b58a VS |
2637 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
2638 | ||
2639 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2640 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2641 | else | |
2642 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2643 | ||
2644 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2645 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2646 | case DP_TRAINING_PATTERN_DISABLE: | |
2647 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; | |
2648 | ||
2649 | break; | |
2650 | case DP_TRAINING_PATTERN_1: | |
2651 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2652 | break; | |
2653 | case DP_TRAINING_PATTERN_2: | |
2654 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2655 | break; | |
2656 | case DP_TRAINING_PATTERN_3: | |
2657 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2658 | break; | |
2659 | } | |
2660 | I915_WRITE(DP_TP_CTL(port), temp); | |
2661 | ||
5db94019 | 2662 | } else if ((IS_GEN7(dev_priv) && port == PORT_A) || |
6e266956 | 2663 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
7b13b58a VS |
2664 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2665 | ||
2666 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2667 | case DP_TRAINING_PATTERN_DISABLE: | |
2668 | *DP |= DP_LINK_TRAIN_OFF_CPT; | |
2669 | break; | |
2670 | case DP_TRAINING_PATTERN_1: | |
2671 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; | |
2672 | break; | |
2673 | case DP_TRAINING_PATTERN_2: | |
2674 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2675 | break; | |
2676 | case DP_TRAINING_PATTERN_3: | |
8b0878a0 | 2677 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
7b13b58a VS |
2678 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2679 | break; | |
2680 | } | |
2681 | ||
2682 | } else { | |
920a14b2 | 2683 | if (IS_CHERRYVIEW(dev_priv)) |
7b13b58a VS |
2684 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
2685 | else | |
2686 | *DP &= ~DP_LINK_TRAIN_MASK; | |
2687 | ||
2688 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2689 | case DP_TRAINING_PATTERN_DISABLE: | |
2690 | *DP |= DP_LINK_TRAIN_OFF; | |
2691 | break; | |
2692 | case DP_TRAINING_PATTERN_1: | |
2693 | *DP |= DP_LINK_TRAIN_PAT_1; | |
2694 | break; | |
2695 | case DP_TRAINING_PATTERN_2: | |
2696 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2697 | break; | |
2698 | case DP_TRAINING_PATTERN_3: | |
920a14b2 | 2699 | if (IS_CHERRYVIEW(dev_priv)) { |
7b13b58a VS |
2700 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
2701 | } else { | |
8b0878a0 | 2702 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
7b13b58a VS |
2703 | *DP |= DP_LINK_TRAIN_PAT_2; |
2704 | } | |
2705 | break; | |
2706 | } | |
2707 | } | |
2708 | } | |
2709 | ||
85cb48a1 ML |
2710 | static void intel_dp_enable_port(struct intel_dp *intel_dp, |
2711 | struct intel_crtc_state *old_crtc_state) | |
7b13b58a VS |
2712 | { |
2713 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 2714 | struct drm_i915_private *dev_priv = to_i915(dev); |
7b13b58a | 2715 | |
7b13b58a | 2716 | /* enable with pattern 1 (as per spec) */ |
7b13b58a | 2717 | |
8b0878a0 | 2718 | intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1); |
7b713f50 VS |
2719 | |
2720 | /* | |
2721 | * Magic for VLV/CHV. We _must_ first set up the register | |
2722 | * without actually enabling the port, and then do another | |
2723 | * write to enable the port. Otherwise link training will | |
2724 | * fail when the power sequencer is freshly used for this port. | |
2725 | */ | |
2726 | intel_dp->DP |= DP_PORT_EN; | |
85cb48a1 | 2727 | if (old_crtc_state->has_audio) |
6fec7662 | 2728 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
7b713f50 VS |
2729 | |
2730 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2731 | POSTING_READ(intel_dp->output_reg); | |
580d3811 VS |
2732 | } |
2733 | ||
85cb48a1 | 2734 | static void intel_enable_dp(struct intel_encoder *encoder, |
bbf35e9d ML |
2735 | struct intel_crtc_state *pipe_config, |
2736 | struct drm_connector_state *conn_state) | |
d240f20f | 2737 | { |
e8cb4558 DV |
2738 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2739 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2740 | struct drm_i915_private *dev_priv = to_i915(dev); |
c1dec79a | 2741 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
e8cb4558 | 2742 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
d6fbdd15 | 2743 | enum pipe pipe = crtc->pipe; |
5d613501 | 2744 | |
0c33d8d7 DV |
2745 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2746 | return; | |
5d613501 | 2747 | |
093e3f13 VS |
2748 | pps_lock(intel_dp); |
2749 | ||
920a14b2 | 2750 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
093e3f13 VS |
2751 | vlv_init_panel_power_sequencer(intel_dp); |
2752 | ||
85cb48a1 | 2753 | intel_dp_enable_port(intel_dp, pipe_config); |
093e3f13 VS |
2754 | |
2755 | edp_panel_vdd_on(intel_dp); | |
2756 | edp_panel_on(intel_dp); | |
2757 | edp_panel_vdd_off(intel_dp, true); | |
2758 | ||
2759 | pps_unlock(intel_dp); | |
2760 | ||
920a14b2 | 2761 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e0fce78f VS |
2762 | unsigned int lane_mask = 0x0; |
2763 | ||
920a14b2 | 2764 | if (IS_CHERRYVIEW(dev_priv)) |
85cb48a1 | 2765 | lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); |
e0fce78f | 2766 | |
9b6de0a1 VS |
2767 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2768 | lane_mask); | |
e0fce78f | 2769 | } |
61234fa5 | 2770 | |
f01eca2e | 2771 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 2772 | intel_dp_start_link_train(intel_dp); |
3ab9c637 | 2773 | intel_dp_stop_link_train(intel_dp); |
c1dec79a | 2774 | |
85cb48a1 | 2775 | if (pipe_config->has_audio) { |
c1dec79a | 2776 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
d6fbdd15 | 2777 | pipe_name(pipe)); |
bbf35e9d | 2778 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
c1dec79a | 2779 | } |
ab1f90f9 | 2780 | } |
89b667f8 | 2781 | |
fd6bbda9 ML |
2782 | static void g4x_enable_dp(struct intel_encoder *encoder, |
2783 | struct intel_crtc_state *pipe_config, | |
2784 | struct drm_connector_state *conn_state) | |
ecff4f3b | 2785 | { |
828f5c6e JN |
2786 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2787 | ||
bbf35e9d | 2788 | intel_enable_dp(encoder, pipe_config, conn_state); |
4be73780 | 2789 | intel_edp_backlight_on(intel_dp); |
ab1f90f9 | 2790 | } |
89b667f8 | 2791 | |
fd6bbda9 ML |
2792 | static void vlv_enable_dp(struct intel_encoder *encoder, |
2793 | struct intel_crtc_state *pipe_config, | |
2794 | struct drm_connector_state *conn_state) | |
ab1f90f9 | 2795 | { |
828f5c6e JN |
2796 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2797 | ||
4be73780 | 2798 | intel_edp_backlight_on(intel_dp); |
b32c6f48 | 2799 | intel_psr_enable(intel_dp); |
d240f20f JB |
2800 | } |
2801 | ||
fd6bbda9 ML |
2802 | static void g4x_pre_enable_dp(struct intel_encoder *encoder, |
2803 | struct intel_crtc_state *pipe_config, | |
2804 | struct drm_connector_state *conn_state) | |
ab1f90f9 JN |
2805 | { |
2806 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
d6fbdd15 | 2807 | enum port port = dp_to_dig_port(intel_dp)->port; |
ab1f90f9 | 2808 | |
85cb48a1 | 2809 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 2810 | |
d41f1efb | 2811 | /* Only ilk+ has port A */ |
abfce949 | 2812 | if (port == PORT_A) |
85cb48a1 | 2813 | ironlake_edp_pll_on(intel_dp, pipe_config); |
ab1f90f9 JN |
2814 | } |
2815 | ||
83b84597 VS |
2816 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2817 | { | |
2818 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
fac5e23e | 2819 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
83b84597 | 2820 | enum pipe pipe = intel_dp->pps_pipe; |
44cb734c | 2821 | i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); |
83b84597 | 2822 | |
c10eaed4 VS |
2823 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2824 | return; | |
2825 | ||
83b84597 VS |
2826 | edp_panel_vdd_off_sync(intel_dp); |
2827 | ||
2828 | /* | |
2829 | * VLV seems to get confused when multiple power seqeuencers | |
2830 | * have the same port selected (even if only one has power/vdd | |
2831 | * enabled). The failure manifests as vlv_wait_port_ready() failing | |
2832 | * CHV on the other hand doesn't seem to mind having the same port | |
2833 | * selected in multiple power seqeuencers, but let's clear the | |
2834 | * port select always when logically disconnecting a power sequencer | |
2835 | * from a port. | |
2836 | */ | |
2837 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", | |
2838 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
2839 | I915_WRITE(pp_on_reg, 0); | |
2840 | POSTING_READ(pp_on_reg); | |
2841 | ||
2842 | intel_dp->pps_pipe = INVALID_PIPE; | |
2843 | } | |
2844 | ||
a4a5d2f8 VS |
2845 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2846 | enum pipe pipe) | |
2847 | { | |
fac5e23e | 2848 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
2849 | struct intel_encoder *encoder; |
2850 | ||
2851 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2852 | ||
19c8054c | 2853 | for_each_intel_encoder(dev, encoder) { |
a4a5d2f8 | 2854 | struct intel_dp *intel_dp; |
773538e8 | 2855 | enum port port; |
a4a5d2f8 VS |
2856 | |
2857 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2858 | continue; | |
2859 | ||
2860 | intel_dp = enc_to_intel_dp(&encoder->base); | |
773538e8 | 2861 | port = dp_to_dig_port(intel_dp)->port; |
a4a5d2f8 VS |
2862 | |
2863 | if (intel_dp->pps_pipe != pipe) | |
2864 | continue; | |
2865 | ||
2866 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", | |
773538e8 | 2867 | pipe_name(pipe), port_name(port)); |
a4a5d2f8 | 2868 | |
e02f9a06 | 2869 | WARN(encoder->base.crtc, |
034e43c6 VS |
2870 | "stealing pipe %c power sequencer from active eDP port %c\n", |
2871 | pipe_name(pipe), port_name(port)); | |
a4a5d2f8 | 2872 | |
a4a5d2f8 | 2873 | /* make sure vdd is off before we steal it */ |
83b84597 | 2874 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2875 | } |
2876 | } | |
2877 | ||
2878 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) | |
2879 | { | |
2880 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2881 | struct intel_encoder *encoder = &intel_dig_port->base; | |
2882 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2883 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 | 2884 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
a4a5d2f8 VS |
2885 | |
2886 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2887 | ||
093e3f13 VS |
2888 | if (!is_edp(intel_dp)) |
2889 | return; | |
2890 | ||
a4a5d2f8 VS |
2891 | if (intel_dp->pps_pipe == crtc->pipe) |
2892 | return; | |
2893 | ||
2894 | /* | |
2895 | * If another power sequencer was being used on this | |
2896 | * port previously make sure to turn off vdd there while | |
2897 | * we still have control of it. | |
2898 | */ | |
2899 | if (intel_dp->pps_pipe != INVALID_PIPE) | |
83b84597 | 2900 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2901 | |
2902 | /* | |
2903 | * We may be stealing the power | |
2904 | * sequencer from another port. | |
2905 | */ | |
2906 | vlv_steal_power_sequencer(dev, crtc->pipe); | |
2907 | ||
2908 | /* now it's all ours */ | |
2909 | intel_dp->pps_pipe = crtc->pipe; | |
2910 | ||
2911 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", | |
2912 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); | |
2913 | ||
2914 | /* init power sequencer on this pipe and port */ | |
36b5f425 | 2915 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
8581f1b5 | 2916 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true); |
a4a5d2f8 VS |
2917 | } |
2918 | ||
fd6bbda9 ML |
2919 | static void vlv_pre_enable_dp(struct intel_encoder *encoder, |
2920 | struct intel_crtc_state *pipe_config, | |
2921 | struct drm_connector_state *conn_state) | |
a4fc5ed6 | 2922 | { |
5f68c275 | 2923 | vlv_phy_pre_encoder_enable(encoder); |
ab1f90f9 | 2924 | |
bbf35e9d | 2925 | intel_enable_dp(encoder, pipe_config, conn_state); |
89b667f8 JB |
2926 | } |
2927 | ||
fd6bbda9 ML |
2928 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder, |
2929 | struct intel_crtc_state *pipe_config, | |
2930 | struct drm_connector_state *conn_state) | |
89b667f8 | 2931 | { |
85cb48a1 | 2932 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 2933 | |
6da2e616 | 2934 | vlv_phy_pre_pll_enable(encoder); |
a4fc5ed6 KP |
2935 | } |
2936 | ||
fd6bbda9 ML |
2937 | static void chv_pre_enable_dp(struct intel_encoder *encoder, |
2938 | struct intel_crtc_state *pipe_config, | |
2939 | struct drm_connector_state *conn_state) | |
e4a1d846 | 2940 | { |
e7d2a717 | 2941 | chv_phy_pre_encoder_enable(encoder); |
e4a1d846 | 2942 | |
bbf35e9d | 2943 | intel_enable_dp(encoder, pipe_config, conn_state); |
b0b33846 VS |
2944 | |
2945 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 2946 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
2947 | } |
2948 | ||
fd6bbda9 ML |
2949 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder, |
2950 | struct intel_crtc_state *pipe_config, | |
2951 | struct drm_connector_state *conn_state) | |
9197c88b | 2952 | { |
85cb48a1 | 2953 | intel_dp_prepare(encoder, pipe_config); |
625695f8 | 2954 | |
419b1b7a | 2955 | chv_phy_pre_pll_enable(encoder); |
9197c88b VS |
2956 | } |
2957 | ||
fd6bbda9 ML |
2958 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder, |
2959 | struct intel_crtc_state *pipe_config, | |
2960 | struct drm_connector_state *conn_state) | |
d6db995f | 2961 | { |
204970b5 | 2962 | chv_phy_post_pll_disable(encoder); |
d6db995f VS |
2963 | } |
2964 | ||
a4fc5ed6 KP |
2965 | /* |
2966 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
2967 | * link status information | |
2968 | */ | |
94223d04 | 2969 | bool |
93f62dad | 2970 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 2971 | { |
9f085ebb L |
2972 | return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, |
2973 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
2974 | } |
2975 | ||
1100244e | 2976 | /* These are source-specific values. */ |
94223d04 | 2977 | uint8_t |
1a2eb460 | 2978 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 2979 | { |
dd11bc10 | 2980 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
bc7d38a4 | 2981 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 2982 | |
e2d214ae | 2983 | if (IS_BROXTON(dev_priv)) |
9314726b | 2984 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
dd11bc10 | 2985 | else if (INTEL_GEN(dev_priv) >= 9) { |
06411f08 | 2986 | if (dev_priv->vbt.edp.low_vswing && port == PORT_A) |
7ad14a29 | 2987 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
5a9d1f1a | 2988 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
920a14b2 | 2989 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
bd60018a | 2990 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
5db94019 | 2991 | else if (IS_GEN7(dev_priv) && port == PORT_A) |
bd60018a | 2992 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
6e266956 | 2993 | else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) |
bd60018a | 2994 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
1a2eb460 | 2995 | else |
bd60018a | 2996 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
1a2eb460 KP |
2997 | } |
2998 | ||
94223d04 | 2999 | uint8_t |
1a2eb460 KP |
3000 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
3001 | { | |
8652744b | 3002 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
bc7d38a4 | 3003 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 3004 | |
8652744b | 3005 | if (INTEL_GEN(dev_priv) >= 9) { |
5a9d1f1a DL |
3006 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3007 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: | |
3008 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3009 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3010 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3011 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3012 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
7ad14a29 SJ |
3013 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3014 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
5a9d1f1a DL |
3015 | default: |
3016 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
3017 | } | |
8652744b | 3018 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
d6c0d722 | 3019 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3020 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3021 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3022 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3023 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3024 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3025 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3026 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
d6c0d722 | 3027 | default: |
bd60018a | 3028 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
d6c0d722 | 3029 | } |
8652744b | 3030 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e2fa6fba | 3031 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3032 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3033 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3034 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3035 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3036 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3037 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3038 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
e2fa6fba | 3039 | default: |
bd60018a | 3040 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
e2fa6fba | 3041 | } |
8652744b | 3042 | } else if (IS_GEN7(dev_priv) && port == PORT_A) { |
1a2eb460 | 3043 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3044 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3045 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3046 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3047 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3048 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
1a2eb460 | 3049 | default: |
bd60018a | 3050 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 KP |
3051 | } |
3052 | } else { | |
3053 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
3054 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3055 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3056 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3057 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3058 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3059 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3060 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
1a2eb460 | 3061 | default: |
bd60018a | 3062 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 | 3063 | } |
a4fc5ed6 KP |
3064 | } |
3065 | } | |
3066 | ||
5829975c | 3067 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
e2fa6fba | 3068 | { |
53d98725 | 3069 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
e2fa6fba P |
3070 | unsigned long demph_reg_value, preemph_reg_value, |
3071 | uniqtranscale_reg_value; | |
3072 | uint8_t train_set = intel_dp->train_set[0]; | |
e2fa6fba P |
3073 | |
3074 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3075 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e2fa6fba P |
3076 | preemph_reg_value = 0x0004000; |
3077 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3078 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3079 | demph_reg_value = 0x2B405555; |
3080 | uniqtranscale_reg_value = 0x552AB83A; | |
3081 | break; | |
bd60018a | 3082 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3083 | demph_reg_value = 0x2B404040; |
3084 | uniqtranscale_reg_value = 0x5548B83A; | |
3085 | break; | |
bd60018a | 3086 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3087 | demph_reg_value = 0x2B245555; |
3088 | uniqtranscale_reg_value = 0x5560B83A; | |
3089 | break; | |
bd60018a | 3090 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e2fa6fba P |
3091 | demph_reg_value = 0x2B405555; |
3092 | uniqtranscale_reg_value = 0x5598DA3A; | |
3093 | break; | |
3094 | default: | |
3095 | return 0; | |
3096 | } | |
3097 | break; | |
bd60018a | 3098 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e2fa6fba P |
3099 | preemph_reg_value = 0x0002000; |
3100 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3101 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3102 | demph_reg_value = 0x2B404040; |
3103 | uniqtranscale_reg_value = 0x5552B83A; | |
3104 | break; | |
bd60018a | 3105 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3106 | demph_reg_value = 0x2B404848; |
3107 | uniqtranscale_reg_value = 0x5580B83A; | |
3108 | break; | |
bd60018a | 3109 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3110 | demph_reg_value = 0x2B404040; |
3111 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3112 | break; | |
3113 | default: | |
3114 | return 0; | |
3115 | } | |
3116 | break; | |
bd60018a | 3117 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e2fa6fba P |
3118 | preemph_reg_value = 0x0000000; |
3119 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3120 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3121 | demph_reg_value = 0x2B305555; |
3122 | uniqtranscale_reg_value = 0x5570B83A; | |
3123 | break; | |
bd60018a | 3124 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3125 | demph_reg_value = 0x2B2B4040; |
3126 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3127 | break; | |
3128 | default: | |
3129 | return 0; | |
3130 | } | |
3131 | break; | |
bd60018a | 3132 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e2fa6fba P |
3133 | preemph_reg_value = 0x0006000; |
3134 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3135 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3136 | demph_reg_value = 0x1B405555; |
3137 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3138 | break; | |
3139 | default: | |
3140 | return 0; | |
3141 | } | |
3142 | break; | |
3143 | default: | |
3144 | return 0; | |
3145 | } | |
3146 | ||
53d98725 ACO |
3147 | vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, |
3148 | uniqtranscale_reg_value, 0); | |
e2fa6fba P |
3149 | |
3150 | return 0; | |
3151 | } | |
3152 | ||
5829975c | 3153 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
e4a1d846 | 3154 | { |
b7fa22d8 ACO |
3155 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3156 | u32 deemph_reg_value, margin_reg_value; | |
3157 | bool uniq_trans_scale = false; | |
e4a1d846 | 3158 | uint8_t train_set = intel_dp->train_set[0]; |
e4a1d846 CML |
3159 | |
3160 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3161 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e4a1d846 | 3162 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3163 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3164 | deemph_reg_value = 128; |
3165 | margin_reg_value = 52; | |
3166 | break; | |
bd60018a | 3167 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3168 | deemph_reg_value = 128; |
3169 | margin_reg_value = 77; | |
3170 | break; | |
bd60018a | 3171 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3172 | deemph_reg_value = 128; |
3173 | margin_reg_value = 102; | |
3174 | break; | |
bd60018a | 3175 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e4a1d846 CML |
3176 | deemph_reg_value = 128; |
3177 | margin_reg_value = 154; | |
b7fa22d8 | 3178 | uniq_trans_scale = true; |
e4a1d846 CML |
3179 | break; |
3180 | default: | |
3181 | return 0; | |
3182 | } | |
3183 | break; | |
bd60018a | 3184 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e4a1d846 | 3185 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3186 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3187 | deemph_reg_value = 85; |
3188 | margin_reg_value = 78; | |
3189 | break; | |
bd60018a | 3190 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3191 | deemph_reg_value = 85; |
3192 | margin_reg_value = 116; | |
3193 | break; | |
bd60018a | 3194 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3195 | deemph_reg_value = 85; |
3196 | margin_reg_value = 154; | |
3197 | break; | |
3198 | default: | |
3199 | return 0; | |
3200 | } | |
3201 | break; | |
bd60018a | 3202 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e4a1d846 | 3203 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3204 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3205 | deemph_reg_value = 64; |
3206 | margin_reg_value = 104; | |
3207 | break; | |
bd60018a | 3208 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3209 | deemph_reg_value = 64; |
3210 | margin_reg_value = 154; | |
3211 | break; | |
3212 | default: | |
3213 | return 0; | |
3214 | } | |
3215 | break; | |
bd60018a | 3216 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e4a1d846 | 3217 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3218 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3219 | deemph_reg_value = 43; |
3220 | margin_reg_value = 154; | |
3221 | break; | |
3222 | default: | |
3223 | return 0; | |
3224 | } | |
3225 | break; | |
3226 | default: | |
3227 | return 0; | |
3228 | } | |
3229 | ||
b7fa22d8 ACO |
3230 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
3231 | margin_reg_value, uniq_trans_scale); | |
e4a1d846 CML |
3232 | |
3233 | return 0; | |
3234 | } | |
3235 | ||
a4fc5ed6 | 3236 | static uint32_t |
5829975c | 3237 | gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 3238 | { |
3cf2efb1 | 3239 | uint32_t signal_levels = 0; |
a4fc5ed6 | 3240 | |
3cf2efb1 | 3241 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3242 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
a4fc5ed6 KP |
3243 | default: |
3244 | signal_levels |= DP_VOLTAGE_0_4; | |
3245 | break; | |
bd60018a | 3246 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
a4fc5ed6 KP |
3247 | signal_levels |= DP_VOLTAGE_0_6; |
3248 | break; | |
bd60018a | 3249 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
a4fc5ed6 KP |
3250 | signal_levels |= DP_VOLTAGE_0_8; |
3251 | break; | |
bd60018a | 3252 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
a4fc5ed6 KP |
3253 | signal_levels |= DP_VOLTAGE_1_2; |
3254 | break; | |
3255 | } | |
3cf2efb1 | 3256 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
bd60018a | 3257 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
a4fc5ed6 KP |
3258 | default: |
3259 | signal_levels |= DP_PRE_EMPHASIS_0; | |
3260 | break; | |
bd60018a | 3261 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
a4fc5ed6 KP |
3262 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3263 | break; | |
bd60018a | 3264 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
a4fc5ed6 KP |
3265 | signal_levels |= DP_PRE_EMPHASIS_6; |
3266 | break; | |
bd60018a | 3267 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
a4fc5ed6 KP |
3268 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3269 | break; | |
3270 | } | |
3271 | return signal_levels; | |
3272 | } | |
3273 | ||
e3421a18 ZW |
3274 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3275 | static uint32_t | |
5829975c | 3276 | gen6_edp_signal_levels(uint8_t train_set) |
e3421a18 | 3277 | { |
3c5a62b5 YL |
3278 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3279 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3280 | switch (signal_levels) { | |
bd60018a SJ |
3281 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3282 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3283 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
bd60018a | 3284 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3c5a62b5 | 3285 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
bd60018a SJ |
3286 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3287 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
3c5a62b5 | 3288 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
bd60018a SJ |
3289 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3290 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
3c5a62b5 | 3291 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
bd60018a SJ |
3292 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3293 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3294 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
e3421a18 | 3295 | default: |
3c5a62b5 YL |
3296 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3297 | "0x%x\n", signal_levels); | |
3298 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
3299 | } |
3300 | } | |
3301 | ||
1a2eb460 KP |
3302 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3303 | static uint32_t | |
5829975c | 3304 | gen7_edp_signal_levels(uint8_t train_set) |
1a2eb460 KP |
3305 | { |
3306 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
3307 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3308 | switch (signal_levels) { | |
bd60018a | 3309 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3310 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
bd60018a | 3311 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 | 3312 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
bd60018a | 3313 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
1a2eb460 KP |
3314 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3315 | ||
bd60018a | 3316 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3317 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
bd60018a | 3318 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3319 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3320 | ||
bd60018a | 3321 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3322 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
bd60018a | 3323 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3324 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3325 | ||
3326 | default: | |
3327 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
3328 | "0x%x\n", signal_levels); | |
3329 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
3330 | } | |
3331 | } | |
3332 | ||
94223d04 | 3333 | void |
f4eb692e | 3334 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
f0a3424e PZ |
3335 | { |
3336 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 3337 | enum port port = intel_dig_port->port; |
f0a3424e | 3338 | struct drm_device *dev = intel_dig_port->base.base.dev; |
b905a915 | 3339 | struct drm_i915_private *dev_priv = to_i915(dev); |
f8896f5d | 3340 | uint32_t signal_levels, mask = 0; |
f0a3424e PZ |
3341 | uint8_t train_set = intel_dp->train_set[0]; |
3342 | ||
4f8036a2 | 3343 | if (HAS_DDI(dev_priv)) { |
f8896f5d DW |
3344 | signal_levels = ddi_signal_levels(intel_dp); |
3345 | ||
e2d214ae | 3346 | if (IS_BROXTON(dev_priv)) |
f8896f5d DW |
3347 | signal_levels = 0; |
3348 | else | |
3349 | mask = DDI_BUF_EMP_MASK; | |
920a14b2 | 3350 | } else if (IS_CHERRYVIEW(dev_priv)) { |
5829975c | 3351 | signal_levels = chv_signal_levels(intel_dp); |
11a914c2 | 3352 | } else if (IS_VALLEYVIEW(dev_priv)) { |
5829975c | 3353 | signal_levels = vlv_signal_levels(intel_dp); |
5db94019 | 3354 | } else if (IS_GEN7(dev_priv) && port == PORT_A) { |
5829975c | 3355 | signal_levels = gen7_edp_signal_levels(train_set); |
f0a3424e | 3356 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
5db94019 | 3357 | } else if (IS_GEN6(dev_priv) && port == PORT_A) { |
5829975c | 3358 | signal_levels = gen6_edp_signal_levels(train_set); |
f0a3424e PZ |
3359 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3360 | } else { | |
5829975c | 3361 | signal_levels = gen4_signal_levels(train_set); |
f0a3424e PZ |
3362 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3363 | } | |
3364 | ||
96fb9f9b VK |
3365 | if (mask) |
3366 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
3367 | ||
3368 | DRM_DEBUG_KMS("Using vswing level %d\n", | |
3369 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); | |
3370 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", | |
3371 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
3372 | DP_TRAIN_PRE_EMPHASIS_SHIFT); | |
f0a3424e | 3373 | |
f4eb692e | 3374 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
b905a915 ACO |
3375 | |
3376 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
3377 | POSTING_READ(intel_dp->output_reg); | |
f0a3424e PZ |
3378 | } |
3379 | ||
94223d04 | 3380 | void |
e9c176d5 ACO |
3381 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
3382 | uint8_t dp_train_pat) | |
a4fc5ed6 | 3383 | { |
174edf1f | 3384 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
90a6b7b0 VS |
3385 | struct drm_i915_private *dev_priv = |
3386 | to_i915(intel_dig_port->base.base.dev); | |
a4fc5ed6 | 3387 | |
f4eb692e | 3388 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
47ea7542 | 3389 | |
f4eb692e | 3390 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
ea5b213a | 3391 | POSTING_READ(intel_dp->output_reg); |
e9c176d5 ACO |
3392 | } |
3393 | ||
94223d04 | 3394 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3ab9c637 ID |
3395 | { |
3396 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3397 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 3398 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ab9c637 ID |
3399 | enum port port = intel_dig_port->port; |
3400 | uint32_t val; | |
3401 | ||
4f8036a2 | 3402 | if (!HAS_DDI(dev_priv)) |
3ab9c637 ID |
3403 | return; |
3404 | ||
3405 | val = I915_READ(DP_TP_CTL(port)); | |
3406 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
3407 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
3408 | I915_WRITE(DP_TP_CTL(port), val); | |
3409 | ||
3410 | /* | |
3411 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
3412 | * we need to set idle transmission mode is to work around a HW issue | |
3413 | * where we enable the pipe while not in idle link-training mode. | |
3414 | * In this case there is requirement to wait for a minimum number of | |
3415 | * idle patterns to be sent. | |
3416 | */ | |
3417 | if (port == PORT_A) | |
3418 | return; | |
3419 | ||
a767017f CW |
3420 | if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port), |
3421 | DP_TP_STATUS_IDLE_DONE, | |
3422 | DP_TP_STATUS_IDLE_DONE, | |
3423 | 1)) | |
3ab9c637 ID |
3424 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
3425 | } | |
3426 | ||
a4fc5ed6 | 3427 | static void |
ea5b213a | 3428 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 3429 | { |
da63a9f2 | 3430 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1612c8bd | 3431 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
bc7d38a4 | 3432 | enum port port = intel_dig_port->port; |
da63a9f2 | 3433 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 3434 | struct drm_i915_private *dev_priv = to_i915(dev); |
ea5b213a | 3435 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 3436 | |
4f8036a2 | 3437 | if (WARN_ON(HAS_DDI(dev_priv))) |
c19b0669 PZ |
3438 | return; |
3439 | ||
0c33d8d7 | 3440 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
3441 | return; |
3442 | ||
28c97730 | 3443 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 3444 | |
5db94019 | 3445 | if ((IS_GEN7(dev_priv) && port == PORT_A) || |
6e266956 | 3446 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
e3421a18 | 3447 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1612c8bd | 3448 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
e3421a18 | 3449 | } else { |
920a14b2 | 3450 | if (IS_CHERRYVIEW(dev_priv)) |
aad3d14d VS |
3451 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
3452 | else | |
3453 | DP &= ~DP_LINK_TRAIN_MASK; | |
1612c8bd | 3454 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
e3421a18 | 3455 | } |
1612c8bd | 3456 | I915_WRITE(intel_dp->output_reg, DP); |
fe255d00 | 3457 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 3458 | |
1612c8bd VS |
3459 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3460 | I915_WRITE(intel_dp->output_reg, DP); | |
3461 | POSTING_READ(intel_dp->output_reg); | |
3462 | ||
3463 | /* | |
3464 | * HW workaround for IBX, we need to move the port | |
3465 | * to transcoder A after disabling it to allow the | |
3466 | * matching HDMI port to be enabled on transcoder A. | |
3467 | */ | |
6e266956 | 3468 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { |
0c241d5b VS |
3469 | /* |
3470 | * We get CPU/PCH FIFO underruns on the other pipe when | |
3471 | * doing the workaround. Sweep them under the rug. | |
3472 | */ | |
3473 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3474 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3475 | ||
1612c8bd VS |
3476 | /* always enable with pattern 1 (as per spec) */ |
3477 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); | |
3478 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; | |
3479 | I915_WRITE(intel_dp->output_reg, DP); | |
3480 | POSTING_READ(intel_dp->output_reg); | |
3481 | ||
3482 | DP &= ~DP_PORT_EN; | |
5bddd17f | 3483 | I915_WRITE(intel_dp->output_reg, DP); |
0ca09685 | 3484 | POSTING_READ(intel_dp->output_reg); |
0c241d5b | 3485 | |
0f0f74bc | 3486 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
3487 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
3488 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
5bddd17f EA |
3489 | } |
3490 | ||
f01eca2e | 3491 | msleep(intel_dp->panel_power_down_delay); |
6fec7662 VS |
3492 | |
3493 | intel_dp->DP = DP; | |
a4fc5ed6 KP |
3494 | } |
3495 | ||
24e807e7 | 3496 | bool |
fe5a66f9 | 3497 | intel_dp_read_dpcd(struct intel_dp *intel_dp) |
92fd8fd1 | 3498 | { |
9f085ebb L |
3499 | if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3500 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 3501 | return false; /* aux transfer failed */ |
92fd8fd1 | 3502 | |
a8e98153 | 3503 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
577c7a50 | 3504 | |
fe5a66f9 VS |
3505 | return intel_dp->dpcd[DP_DPCD_REV] != 0; |
3506 | } | |
edb39244 | 3507 | |
fe5a66f9 VS |
3508 | static bool |
3509 | intel_edp_init_dpcd(struct intel_dp *intel_dp) | |
3510 | { | |
3511 | struct drm_i915_private *dev_priv = | |
3512 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
30d9aa42 | 3513 | |
fe5a66f9 VS |
3514 | /* this function is meant to be called only once */ |
3515 | WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); | |
30d9aa42 | 3516 | |
fe5a66f9 | 3517 | if (!intel_dp_read_dpcd(intel_dp)) |
30d9aa42 SS |
3518 | return false; |
3519 | ||
12a47a42 ID |
3520 | intel_dp_read_desc(intel_dp); |
3521 | ||
fe5a66f9 VS |
3522 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
3523 | dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
3524 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
474d1ec4 | 3525 | |
fe5a66f9 VS |
3526 | /* Check if the panel supports PSR */ |
3527 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, | |
3528 | intel_dp->psr_dpcd, | |
3529 | sizeof(intel_dp->psr_dpcd)); | |
3530 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { | |
3531 | dev_priv->psr.sink_support = true; | |
3532 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); | |
3533 | } | |
86ee27b5 | 3534 | |
fe5a66f9 VS |
3535 | if (INTEL_GEN(dev_priv) >= 9 && |
3536 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { | |
3537 | uint8_t frame_sync_cap; | |
3538 | ||
3539 | dev_priv->psr.sink_support = true; | |
3540 | drm_dp_dpcd_read(&intel_dp->aux, | |
3541 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, | |
3542 | &frame_sync_cap, 1); | |
3543 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; | |
3544 | /* PSR2 needs frame sync as well */ | |
3545 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; | |
3546 | DRM_DEBUG_KMS("PSR2 %s on sink", | |
3547 | dev_priv->psr.psr2_support ? "supported" : "not supported"); | |
50003939 JN |
3548 | } |
3549 | ||
fe5a66f9 VS |
3550 | /* Read the eDP Display control capabilities registers */ |
3551 | if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && | |
3552 | drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, | |
f7170e2e DC |
3553 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == |
3554 | sizeof(intel_dp->edp_dpcd)) | |
fe5a66f9 VS |
3555 | DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), |
3556 | intel_dp->edp_dpcd); | |
06ea66b6 | 3557 | |
fc0f8e25 | 3558 | /* Intermediate frequency support */ |
fe5a66f9 | 3559 | if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */ |
94ca719e | 3560 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
ea2d8a42 VS |
3561 | int i; |
3562 | ||
9f085ebb L |
3563 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, |
3564 | sink_rates, sizeof(sink_rates)); | |
ea2d8a42 | 3565 | |
94ca719e VS |
3566 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
3567 | int val = le16_to_cpu(sink_rates[i]); | |
ea2d8a42 VS |
3568 | |
3569 | if (val == 0) | |
3570 | break; | |
3571 | ||
af77b974 SJ |
3572 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
3573 | intel_dp->sink_rates[i] = (val * 200) / 10; | |
ea2d8a42 | 3574 | } |
94ca719e | 3575 | intel_dp->num_sink_rates = i; |
fc0f8e25 | 3576 | } |
0336400e | 3577 | |
fe5a66f9 VS |
3578 | return true; |
3579 | } | |
3580 | ||
3581 | ||
3582 | static bool | |
3583 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
3584 | { | |
3585 | if (!intel_dp_read_dpcd(intel_dp)) | |
3586 | return false; | |
3587 | ||
3588 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT, | |
3589 | &intel_dp->sink_count, 1) < 0) | |
3590 | return false; | |
3591 | ||
3592 | /* | |
3593 | * Sink count can change between short pulse hpd hence | |
3594 | * a member variable in intel_dp will track any changes | |
3595 | * between short pulse interrupts. | |
3596 | */ | |
3597 | intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count); | |
3598 | ||
3599 | /* | |
3600 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that | |
3601 | * a dongle is present but no display. Unless we require to know | |
3602 | * if a dongle is present or not, we don't need to update | |
3603 | * downstream port information. So, an early return here saves | |
3604 | * time from performing other operations which are not required. | |
3605 | */ | |
3606 | if (!is_edp(intel_dp) && !intel_dp->sink_count) | |
3607 | return false; | |
0336400e | 3608 | |
c726ad01 | 3609 | if (!drm_dp_is_branch(intel_dp->dpcd)) |
edb39244 AJ |
3610 | return true; /* native DP sink */ |
3611 | ||
3612 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
3613 | return true; /* no per-port downstream info */ | |
3614 | ||
9f085ebb L |
3615 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3616 | intel_dp->downstream_ports, | |
3617 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
3618 | return false; /* downstream port status fetch failed */ |
3619 | ||
3620 | return true; | |
92fd8fd1 KP |
3621 | } |
3622 | ||
0e32b39c | 3623 | static bool |
c4e3170a | 3624 | intel_dp_can_mst(struct intel_dp *intel_dp) |
0e32b39c DA |
3625 | { |
3626 | u8 buf[1]; | |
3627 | ||
7cc96139 NS |
3628 | if (!i915.enable_dp_mst) |
3629 | return false; | |
3630 | ||
0e32b39c DA |
3631 | if (!intel_dp->can_mst) |
3632 | return false; | |
3633 | ||
3634 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) | |
3635 | return false; | |
3636 | ||
c4e3170a VS |
3637 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1) |
3638 | return false; | |
0e32b39c | 3639 | |
c4e3170a VS |
3640 | return buf[0] & DP_MST_CAP; |
3641 | } | |
3642 | ||
3643 | static void | |
3644 | intel_dp_configure_mst(struct intel_dp *intel_dp) | |
3645 | { | |
3646 | if (!i915.enable_dp_mst) | |
3647 | return; | |
3648 | ||
3649 | if (!intel_dp->can_mst) | |
3650 | return; | |
3651 | ||
3652 | intel_dp->is_mst = intel_dp_can_mst(intel_dp); | |
3653 | ||
3654 | if (intel_dp->is_mst) | |
3655 | DRM_DEBUG_KMS("Sink is MST capable\n"); | |
3656 | else | |
3657 | DRM_DEBUG_KMS("Sink is not MST capable\n"); | |
3658 | ||
3659 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
3660 | intel_dp->is_mst); | |
0e32b39c DA |
3661 | } |
3662 | ||
e5a1cab5 | 3663 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
d2e216d0 | 3664 | { |
082dcc7c | 3665 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
0f0f74bc | 3666 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c | 3667 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
ad9dc91b | 3668 | u8 buf; |
e5a1cab5 | 3669 | int ret = 0; |
c6297843 RV |
3670 | int count = 0; |
3671 | int attempts = 10; | |
d2e216d0 | 3672 | |
082dcc7c RV |
3673 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
3674 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); | |
e5a1cab5 RV |
3675 | ret = -EIO; |
3676 | goto out; | |
4373f0f2 PZ |
3677 | } |
3678 | ||
082dcc7c | 3679 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
e5a1cab5 | 3680 | buf & ~DP_TEST_SINK_START) < 0) { |
082dcc7c | 3681 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
e5a1cab5 RV |
3682 | ret = -EIO; |
3683 | goto out; | |
3684 | } | |
d2e216d0 | 3685 | |
c6297843 | 3686 | do { |
0f0f74bc | 3687 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
c6297843 RV |
3688 | |
3689 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
3690 | DP_TEST_SINK_MISC, &buf) < 0) { | |
3691 | ret = -EIO; | |
3692 | goto out; | |
3693 | } | |
3694 | count = buf & DP_TEST_COUNT_MASK; | |
3695 | } while (--attempts && count); | |
3696 | ||
3697 | if (attempts == 0) { | |
dc5a9037 | 3698 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
c6297843 RV |
3699 | ret = -ETIMEDOUT; |
3700 | } | |
3701 | ||
e5a1cab5 | 3702 | out: |
082dcc7c | 3703 | hsw_enable_ips(intel_crtc); |
e5a1cab5 | 3704 | return ret; |
082dcc7c RV |
3705 | } |
3706 | ||
3707 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) | |
3708 | { | |
3709 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
0f0f74bc | 3710 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c RV |
3711 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3712 | u8 buf; | |
e5a1cab5 RV |
3713 | int ret; |
3714 | ||
082dcc7c RV |
3715 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
3716 | return -EIO; | |
3717 | ||
3718 | if (!(buf & DP_TEST_CRC_SUPPORTED)) | |
3719 | return -ENOTTY; | |
3720 | ||
3721 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) | |
3722 | return -EIO; | |
3723 | ||
6d8175da RV |
3724 | if (buf & DP_TEST_SINK_START) { |
3725 | ret = intel_dp_sink_crc_stop(intel_dp); | |
3726 | if (ret) | |
3727 | return ret; | |
3728 | } | |
3729 | ||
082dcc7c | 3730 | hsw_disable_ips(intel_crtc); |
1dda5f93 | 3731 | |
9d1a1031 | 3732 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
082dcc7c RV |
3733 | buf | DP_TEST_SINK_START) < 0) { |
3734 | hsw_enable_ips(intel_crtc); | |
3735 | return -EIO; | |
4373f0f2 PZ |
3736 | } |
3737 | ||
0f0f74bc | 3738 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
082dcc7c RV |
3739 | return 0; |
3740 | } | |
3741 | ||
3742 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) | |
3743 | { | |
3744 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
0f0f74bc | 3745 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c RV |
3746 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3747 | u8 buf; | |
621d4c76 | 3748 | int count, ret; |
082dcc7c | 3749 | int attempts = 6; |
082dcc7c RV |
3750 | |
3751 | ret = intel_dp_sink_crc_start(intel_dp); | |
3752 | if (ret) | |
3753 | return ret; | |
3754 | ||
ad9dc91b | 3755 | do { |
0f0f74bc | 3756 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
621d4c76 | 3757 | |
1dda5f93 | 3758 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4373f0f2 PZ |
3759 | DP_TEST_SINK_MISC, &buf) < 0) { |
3760 | ret = -EIO; | |
afe0d67e | 3761 | goto stop; |
4373f0f2 | 3762 | } |
621d4c76 | 3763 | count = buf & DP_TEST_COUNT_MASK; |
aabc95dc | 3764 | |
7e38eeff | 3765 | } while (--attempts && count == 0); |
ad9dc91b RV |
3766 | |
3767 | if (attempts == 0) { | |
7e38eeff RV |
3768 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
3769 | ret = -ETIMEDOUT; | |
3770 | goto stop; | |
3771 | } | |
3772 | ||
3773 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { | |
3774 | ret = -EIO; | |
3775 | goto stop; | |
ad9dc91b | 3776 | } |
d2e216d0 | 3777 | |
afe0d67e | 3778 | stop: |
082dcc7c | 3779 | intel_dp_sink_crc_stop(intel_dp); |
4373f0f2 | 3780 | return ret; |
d2e216d0 RV |
3781 | } |
3782 | ||
a60f0e38 JB |
3783 | static bool |
3784 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3785 | { | |
9f085ebb | 3786 | return drm_dp_dpcd_read(&intel_dp->aux, |
9d1a1031 JN |
3787 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
3788 | sink_irq_vector, 1) == 1; | |
a60f0e38 JB |
3789 | } |
3790 | ||
0e32b39c DA |
3791 | static bool |
3792 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3793 | { | |
3794 | int ret; | |
3795 | ||
9f085ebb | 3796 | ret = drm_dp_dpcd_read(&intel_dp->aux, |
0e32b39c DA |
3797 | DP_SINK_COUNT_ESI, |
3798 | sink_irq_vector, 14); | |
3799 | if (ret != 14) | |
3800 | return false; | |
3801 | ||
3802 | return true; | |
3803 | } | |
3804 | ||
c5d5ab7a TP |
3805 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
3806 | { | |
3807 | uint8_t test_result = DP_TEST_ACK; | |
3808 | return test_result; | |
3809 | } | |
3810 | ||
3811 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) | |
3812 | { | |
3813 | uint8_t test_result = DP_TEST_NAK; | |
3814 | return test_result; | |
3815 | } | |
3816 | ||
3817 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) | |
a60f0e38 | 3818 | { |
c5d5ab7a | 3819 | uint8_t test_result = DP_TEST_NAK; |
559be30c TP |
3820 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
3821 | struct drm_connector *connector = &intel_connector->base; | |
3822 | ||
3823 | if (intel_connector->detect_edid == NULL || | |
ac6f2e29 | 3824 | connector->edid_corrupt || |
559be30c TP |
3825 | intel_dp->aux.i2c_defer_count > 6) { |
3826 | /* Check EDID read for NACKs, DEFERs and corruption | |
3827 | * (DP CTS 1.2 Core r1.1) | |
3828 | * 4.2.2.4 : Failed EDID read, I2C_NAK | |
3829 | * 4.2.2.5 : Failed EDID read, I2C_DEFER | |
3830 | * 4.2.2.6 : EDID corruption detected | |
3831 | * Use failsafe mode for all cases | |
3832 | */ | |
3833 | if (intel_dp->aux.i2c_nack_count > 0 || | |
3834 | intel_dp->aux.i2c_defer_count > 0) | |
3835 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", | |
3836 | intel_dp->aux.i2c_nack_count, | |
3837 | intel_dp->aux.i2c_defer_count); | |
3838 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; | |
3839 | } else { | |
f79b468e TS |
3840 | struct edid *block = intel_connector->detect_edid; |
3841 | ||
3842 | /* We have to write the checksum | |
3843 | * of the last block read | |
3844 | */ | |
3845 | block += intel_connector->detect_edid->extensions; | |
3846 | ||
559be30c TP |
3847 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
3848 | DP_TEST_EDID_CHECKSUM, | |
f79b468e | 3849 | &block->checksum, |
5a1cc655 | 3850 | 1)) |
559be30c TP |
3851 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
3852 | ||
3853 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; | |
3854 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; | |
3855 | } | |
3856 | ||
3857 | /* Set test active flag here so userspace doesn't interrupt things */ | |
3858 | intel_dp->compliance_test_active = 1; | |
3859 | ||
c5d5ab7a TP |
3860 | return test_result; |
3861 | } | |
3862 | ||
3863 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) | |
a60f0e38 | 3864 | { |
c5d5ab7a TP |
3865 | uint8_t test_result = DP_TEST_NAK; |
3866 | return test_result; | |
3867 | } | |
3868 | ||
3869 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
3870 | { | |
3871 | uint8_t response = DP_TEST_NAK; | |
3872 | uint8_t rxdata = 0; | |
3873 | int status = 0; | |
3874 | ||
c5d5ab7a TP |
3875 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
3876 | if (status <= 0) { | |
3877 | DRM_DEBUG_KMS("Could not read test request from sink\n"); | |
3878 | goto update_status; | |
3879 | } | |
3880 | ||
3881 | switch (rxdata) { | |
3882 | case DP_TEST_LINK_TRAINING: | |
3883 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); | |
3884 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; | |
3885 | response = intel_dp_autotest_link_training(intel_dp); | |
3886 | break; | |
3887 | case DP_TEST_LINK_VIDEO_PATTERN: | |
3888 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); | |
3889 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; | |
3890 | response = intel_dp_autotest_video_pattern(intel_dp); | |
3891 | break; | |
3892 | case DP_TEST_LINK_EDID_READ: | |
3893 | DRM_DEBUG_KMS("EDID test requested\n"); | |
3894 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; | |
3895 | response = intel_dp_autotest_edid(intel_dp); | |
3896 | break; | |
3897 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
3898 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); | |
3899 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; | |
3900 | response = intel_dp_autotest_phy_pattern(intel_dp); | |
3901 | break; | |
3902 | default: | |
3903 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); | |
3904 | break; | |
3905 | } | |
3906 | ||
3907 | update_status: | |
3908 | status = drm_dp_dpcd_write(&intel_dp->aux, | |
3909 | DP_TEST_RESPONSE, | |
3910 | &response, 1); | |
3911 | if (status <= 0) | |
3912 | DRM_DEBUG_KMS("Could not write test response to sink\n"); | |
a60f0e38 JB |
3913 | } |
3914 | ||
0e32b39c DA |
3915 | static int |
3916 | intel_dp_check_mst_status(struct intel_dp *intel_dp) | |
3917 | { | |
3918 | bool bret; | |
3919 | ||
3920 | if (intel_dp->is_mst) { | |
3921 | u8 esi[16] = { 0 }; | |
3922 | int ret = 0; | |
3923 | int retry; | |
3924 | bool handled; | |
3925 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
3926 | go_again: | |
3927 | if (bret == true) { | |
3928 | ||
3929 | /* check link status - esi[10] = 0x200c */ | |
19e0b4ca | 3930 | if (intel_dp->active_mst_links && |
901c2daf | 3931 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
0e32b39c DA |
3932 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
3933 | intel_dp_start_link_train(intel_dp); | |
0e32b39c DA |
3934 | intel_dp_stop_link_train(intel_dp); |
3935 | } | |
3936 | ||
6f34cc39 | 3937 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
0e32b39c DA |
3938 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
3939 | ||
3940 | if (handled) { | |
3941 | for (retry = 0; retry < 3; retry++) { | |
3942 | int wret; | |
3943 | wret = drm_dp_dpcd_write(&intel_dp->aux, | |
3944 | DP_SINK_COUNT_ESI+1, | |
3945 | &esi[1], 3); | |
3946 | if (wret == 3) { | |
3947 | break; | |
3948 | } | |
3949 | } | |
3950 | ||
3951 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
3952 | if (bret == true) { | |
6f34cc39 | 3953 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
0e32b39c DA |
3954 | goto go_again; |
3955 | } | |
3956 | } else | |
3957 | ret = 0; | |
3958 | ||
3959 | return ret; | |
3960 | } else { | |
3961 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3962 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); | |
3963 | intel_dp->is_mst = false; | |
3964 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
3965 | /* send a hotplug event */ | |
3966 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); | |
3967 | } | |
3968 | } | |
3969 | return -EINVAL; | |
3970 | } | |
3971 | ||
bfd02b3c VS |
3972 | static void |
3973 | intel_dp_retrain_link(struct intel_dp *intel_dp) | |
3974 | { | |
3975 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; | |
3976 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
3977 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
3978 | ||
3979 | /* Suppress underruns caused by re-training */ | |
3980 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); | |
3981 | if (crtc->config->has_pch_encoder) | |
3982 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
3983 | intel_crtc_pch_transcoder(crtc), false); | |
3984 | ||
3985 | intel_dp_start_link_train(intel_dp); | |
3986 | intel_dp_stop_link_train(intel_dp); | |
3987 | ||
3988 | /* Keep underrun reporting disabled until things are stable */ | |
0f0f74bc | 3989 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
bfd02b3c VS |
3990 | |
3991 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); | |
3992 | if (crtc->config->has_pch_encoder) | |
3993 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
3994 | intel_crtc_pch_transcoder(crtc), true); | |
3995 | } | |
3996 | ||
5c9114d0 SS |
3997 | static void |
3998 | intel_dp_check_link_status(struct intel_dp *intel_dp) | |
3999 | { | |
4000 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; | |
4001 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
4002 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
4003 | ||
4004 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
4005 | ||
4006 | if (!intel_dp_get_link_status(intel_dp, link_status)) { | |
4007 | DRM_ERROR("Failed to get link status\n"); | |
4008 | return; | |
4009 | } | |
4010 | ||
4011 | if (!intel_encoder->base.crtc) | |
4012 | return; | |
4013 | ||
4014 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) | |
4015 | return; | |
4016 | ||
d4cb3fd9 | 4017 | /* FIXME: we need to synchronize this sort of stuff with hardware |
2c57b18a DV |
4018 | * readout. Currently fast link training doesn't work on boot-up. */ |
4019 | if (!intel_dp->lane_count) | |
d4cb3fd9 MA |
4020 | return; |
4021 | ||
5c9114d0 SS |
4022 | /* if link training is requested we should perform it always */ |
4023 | if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || | |
4024 | (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { | |
4025 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", | |
4026 | intel_encoder->base.name); | |
bfd02b3c VS |
4027 | |
4028 | intel_dp_retrain_link(intel_dp); | |
5c9114d0 SS |
4029 | } |
4030 | } | |
4031 | ||
a4fc5ed6 KP |
4032 | /* |
4033 | * According to DP spec | |
4034 | * 5.1.2: | |
4035 | * 1. Read DPCD | |
4036 | * 2. Configure link according to Receiver Capabilities | |
4037 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
4038 | * 4. Check link status on receipt of hot-plug interrupt | |
39ff747b SS |
4039 | * |
4040 | * intel_dp_short_pulse - handles short pulse interrupts | |
4041 | * when full detection is not required. | |
4042 | * Returns %true if short pulse is handled and full detection | |
4043 | * is NOT required and %false otherwise. | |
a4fc5ed6 | 4044 | */ |
39ff747b | 4045 | static bool |
5c9114d0 | 4046 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
a4fc5ed6 | 4047 | { |
5b215bcf | 4048 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
65fbb4e7 | 4049 | u8 sink_irq_vector = 0; |
39ff747b SS |
4050 | u8 old_sink_count = intel_dp->sink_count; |
4051 | bool ret; | |
5b215bcf | 4052 | |
4df6960e SS |
4053 | /* |
4054 | * Clearing compliance test variables to allow capturing | |
4055 | * of values for next automated test request. | |
4056 | */ | |
4057 | intel_dp->compliance_test_active = 0; | |
4058 | intel_dp->compliance_test_type = 0; | |
4059 | intel_dp->compliance_test_data = 0; | |
4060 | ||
39ff747b SS |
4061 | /* |
4062 | * Now read the DPCD to see if it's actually running | |
4063 | * If the current value of sink count doesn't match with | |
4064 | * the value that was stored earlier or dpcd read failed | |
4065 | * we need to do full detection | |
4066 | */ | |
4067 | ret = intel_dp_get_dpcd(intel_dp); | |
4068 | ||
4069 | if ((old_sink_count != intel_dp->sink_count) || !ret) { | |
4070 | /* No need to proceed if we are going to do full detect */ | |
4071 | return false; | |
59cd09e1 JB |
4072 | } |
4073 | ||
a60f0e38 JB |
4074 | /* Try to read the source of the interrupt */ |
4075 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
4076 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
4077 | sink_irq_vector != 0) { | |
a60f0e38 | 4078 | /* Clear interrupt source */ |
9d1a1031 JN |
4079 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4080 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4081 | sink_irq_vector); | |
a60f0e38 JB |
4082 | |
4083 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
09b1eb13 | 4084 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
a60f0e38 JB |
4085 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4086 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4087 | } | |
4088 | ||
5c9114d0 SS |
4089 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
4090 | intel_dp_check_link_status(intel_dp); | |
4091 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
39ff747b SS |
4092 | |
4093 | return true; | |
a4fc5ed6 | 4094 | } |
a4fc5ed6 | 4095 | |
caf9ab24 | 4096 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 4097 | static enum drm_connector_status |
26d61aad | 4098 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 4099 | { |
caf9ab24 | 4100 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
4101 | uint8_t type; |
4102 | ||
4103 | if (!intel_dp_get_dpcd(intel_dp)) | |
4104 | return connector_status_disconnected; | |
4105 | ||
1034ce70 SS |
4106 | if (is_edp(intel_dp)) |
4107 | return connector_status_connected; | |
4108 | ||
caf9ab24 | 4109 | /* if there's no downstream port, we're done */ |
c726ad01 | 4110 | if (!drm_dp_is_branch(dpcd)) |
26d61aad | 4111 | return connector_status_connected; |
caf9ab24 AJ |
4112 | |
4113 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
4114 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4115 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
9d1a1031 | 4116 | |
30d9aa42 SS |
4117 | return intel_dp->sink_count ? |
4118 | connector_status_connected : connector_status_disconnected; | |
caf9ab24 AJ |
4119 | } |
4120 | ||
c4e3170a VS |
4121 | if (intel_dp_can_mst(intel_dp)) |
4122 | return connector_status_connected; | |
4123 | ||
caf9ab24 | 4124 | /* If no HPD, poke DDC gently */ |
0b99836f | 4125 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 4126 | return connector_status_connected; |
caf9ab24 AJ |
4127 | |
4128 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
4129 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4130 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
4131 | if (type == DP_DS_PORT_TYPE_VGA || | |
4132 | type == DP_DS_PORT_TYPE_NON_EDID) | |
4133 | return connector_status_unknown; | |
4134 | } else { | |
4135 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
4136 | DP_DWN_STRM_PORT_TYPE_MASK; | |
4137 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
4138 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
4139 | return connector_status_unknown; | |
4140 | } | |
caf9ab24 AJ |
4141 | |
4142 | /* Anything else is out of spec, warn and ignore */ | |
4143 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 4144 | return connector_status_disconnected; |
71ba9000 AJ |
4145 | } |
4146 | ||
d410b56d CW |
4147 | static enum drm_connector_status |
4148 | edp_detect(struct intel_dp *intel_dp) | |
4149 | { | |
4150 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
4151 | enum drm_connector_status status; | |
4152 | ||
4153 | status = intel_panel_detect(dev); | |
4154 | if (status == connector_status_unknown) | |
4155 | status = connector_status_connected; | |
4156 | ||
4157 | return status; | |
4158 | } | |
4159 | ||
b93433cc JN |
4160 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
4161 | struct intel_digital_port *port) | |
5eb08b69 | 4162 | { |
b93433cc | 4163 | u32 bit; |
01cb9ea6 | 4164 | |
0df53b77 JN |
4165 | switch (port->port) { |
4166 | case PORT_A: | |
4167 | return true; | |
4168 | case PORT_B: | |
4169 | bit = SDE_PORTB_HOTPLUG; | |
4170 | break; | |
4171 | case PORT_C: | |
4172 | bit = SDE_PORTC_HOTPLUG; | |
4173 | break; | |
4174 | case PORT_D: | |
4175 | bit = SDE_PORTD_HOTPLUG; | |
4176 | break; | |
4177 | default: | |
4178 | MISSING_CASE(port->port); | |
4179 | return false; | |
4180 | } | |
4181 | ||
4182 | return I915_READ(SDEISR) & bit; | |
4183 | } | |
4184 | ||
4185 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, | |
4186 | struct intel_digital_port *port) | |
4187 | { | |
4188 | u32 bit; | |
4189 | ||
4190 | switch (port->port) { | |
4191 | case PORT_A: | |
4192 | return true; | |
4193 | case PORT_B: | |
4194 | bit = SDE_PORTB_HOTPLUG_CPT; | |
4195 | break; | |
4196 | case PORT_C: | |
4197 | bit = SDE_PORTC_HOTPLUG_CPT; | |
4198 | break; | |
4199 | case PORT_D: | |
4200 | bit = SDE_PORTD_HOTPLUG_CPT; | |
4201 | break; | |
a78695d3 JN |
4202 | case PORT_E: |
4203 | bit = SDE_PORTE_HOTPLUG_SPT; | |
4204 | break; | |
0df53b77 JN |
4205 | default: |
4206 | MISSING_CASE(port->port); | |
4207 | return false; | |
b93433cc | 4208 | } |
1b469639 | 4209 | |
b93433cc | 4210 | return I915_READ(SDEISR) & bit; |
5eb08b69 ZW |
4211 | } |
4212 | ||
7e66bcf2 | 4213 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
1d245987 | 4214 | struct intel_digital_port *port) |
a4fc5ed6 | 4215 | { |
9642c81c | 4216 | u32 bit; |
5eb08b69 | 4217 | |
9642c81c JN |
4218 | switch (port->port) { |
4219 | case PORT_B: | |
4220 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; | |
4221 | break; | |
4222 | case PORT_C: | |
4223 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; | |
4224 | break; | |
4225 | case PORT_D: | |
4226 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | |
4227 | break; | |
4228 | default: | |
4229 | MISSING_CASE(port->port); | |
4230 | return false; | |
4231 | } | |
4232 | ||
4233 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
4234 | } | |
4235 | ||
0780cd36 VS |
4236 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
4237 | struct intel_digital_port *port) | |
9642c81c JN |
4238 | { |
4239 | u32 bit; | |
4240 | ||
4241 | switch (port->port) { | |
4242 | case PORT_B: | |
0780cd36 | 4243 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4244 | break; |
4245 | case PORT_C: | |
0780cd36 | 4246 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4247 | break; |
4248 | case PORT_D: | |
0780cd36 | 4249 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4250 | break; |
4251 | default: | |
4252 | MISSING_CASE(port->port); | |
4253 | return false; | |
a4fc5ed6 KP |
4254 | } |
4255 | ||
1d245987 | 4256 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
2a592bec DA |
4257 | } |
4258 | ||
e464bfde | 4259 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
e2ec35a5 | 4260 | struct intel_digital_port *intel_dig_port) |
e464bfde | 4261 | { |
e2ec35a5 SJ |
4262 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4263 | enum port port; | |
e464bfde JN |
4264 | u32 bit; |
4265 | ||
e2ec35a5 SJ |
4266 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
4267 | switch (port) { | |
e464bfde JN |
4268 | case PORT_A: |
4269 | bit = BXT_DE_PORT_HP_DDIA; | |
4270 | break; | |
4271 | case PORT_B: | |
4272 | bit = BXT_DE_PORT_HP_DDIB; | |
4273 | break; | |
4274 | case PORT_C: | |
4275 | bit = BXT_DE_PORT_HP_DDIC; | |
4276 | break; | |
4277 | default: | |
e2ec35a5 | 4278 | MISSING_CASE(port); |
e464bfde JN |
4279 | return false; |
4280 | } | |
4281 | ||
4282 | return I915_READ(GEN8_DE_PORT_ISR) & bit; | |
4283 | } | |
4284 | ||
7e66bcf2 JN |
4285 | /* |
4286 | * intel_digital_port_connected - is the specified port connected? | |
4287 | * @dev_priv: i915 private structure | |
4288 | * @port: the port to test | |
4289 | * | |
4290 | * Return %true if @port is connected, %false otherwise. | |
4291 | */ | |
67b1bf9c ID |
4292 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
4293 | struct intel_digital_port *port) | |
7e66bcf2 | 4294 | { |
0df53b77 | 4295 | if (HAS_PCH_IBX(dev_priv)) |
7e66bcf2 | 4296 | return ibx_digital_port_connected(dev_priv, port); |
22824fac | 4297 | else if (HAS_PCH_SPLIT(dev_priv)) |
0df53b77 | 4298 | return cpt_digital_port_connected(dev_priv, port); |
e464bfde JN |
4299 | else if (IS_BROXTON(dev_priv)) |
4300 | return bxt_digital_port_connected(dev_priv, port); | |
0780cd36 VS |
4301 | else if (IS_GM45(dev_priv)) |
4302 | return gm45_digital_port_connected(dev_priv, port); | |
7e66bcf2 JN |
4303 | else |
4304 | return g4x_digital_port_connected(dev_priv, port); | |
4305 | } | |
4306 | ||
8c241fef | 4307 | static struct edid * |
beb60608 | 4308 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 4309 | { |
beb60608 | 4310 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
d6f24d0f | 4311 | |
9cd300e0 JN |
4312 | /* use cached edid if we have one */ |
4313 | if (intel_connector->edid) { | |
9cd300e0 JN |
4314 | /* invalid edid */ |
4315 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
4316 | return NULL; |
4317 | ||
55e9edeb | 4318 | return drm_edid_duplicate(intel_connector->edid); |
beb60608 CW |
4319 | } else |
4320 | return drm_get_edid(&intel_connector->base, | |
4321 | &intel_dp->aux.ddc); | |
4322 | } | |
8c241fef | 4323 | |
beb60608 CW |
4324 | static void |
4325 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
4326 | { | |
4327 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
4328 | struct edid *edid; | |
8c241fef | 4329 | |
f21a2198 | 4330 | intel_dp_unset_edid(intel_dp); |
beb60608 CW |
4331 | edid = intel_dp_get_edid(intel_dp); |
4332 | intel_connector->detect_edid = edid; | |
4333 | ||
4334 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) | |
4335 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; | |
4336 | else | |
4337 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
8c241fef KP |
4338 | } |
4339 | ||
beb60608 CW |
4340 | static void |
4341 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 4342 | { |
beb60608 | 4343 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8c241fef | 4344 | |
beb60608 CW |
4345 | kfree(intel_connector->detect_edid); |
4346 | intel_connector->detect_edid = NULL; | |
9cd300e0 | 4347 | |
beb60608 CW |
4348 | intel_dp->has_audio = false; |
4349 | } | |
d6f24d0f | 4350 | |
5cb651a7 | 4351 | static enum drm_connector_status |
f21a2198 | 4352 | intel_dp_long_pulse(struct intel_connector *intel_connector) |
a9756bb5 | 4353 | { |
f21a2198 | 4354 | struct drm_connector *connector = &intel_connector->base; |
a9756bb5 | 4355 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
d63885da PZ |
4356 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4357 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 4358 | struct drm_device *dev = connector->dev; |
a9756bb5 | 4359 | enum drm_connector_status status; |
671dedd2 | 4360 | enum intel_display_power_domain power_domain; |
65fbb4e7 | 4361 | u8 sink_irq_vector = 0; |
a9756bb5 | 4362 | |
25f78f58 VS |
4363 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4364 | intel_display_power_get(to_i915(dev), power_domain); | |
a9756bb5 | 4365 | |
d410b56d CW |
4366 | /* Can't disconnect eDP, but you can close the lid... */ |
4367 | if (is_edp(intel_dp)) | |
4368 | status = edp_detect(intel_dp); | |
c555a81d ACO |
4369 | else if (intel_digital_port_connected(to_i915(dev), |
4370 | dp_to_dig_port(intel_dp))) | |
4371 | status = intel_dp_detect_dpcd(intel_dp); | |
a9756bb5 | 4372 | else |
c555a81d ACO |
4373 | status = connector_status_disconnected; |
4374 | ||
5cb651a7 | 4375 | if (status == connector_status_disconnected) { |
4df6960e SS |
4376 | intel_dp->compliance_test_active = 0; |
4377 | intel_dp->compliance_test_type = 0; | |
4378 | intel_dp->compliance_test_data = 0; | |
4379 | ||
0e505a08 | 4380 | if (intel_dp->is_mst) { |
4381 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4382 | intel_dp->is_mst, | |
4383 | intel_dp->mst_mgr.mst_state); | |
4384 | intel_dp->is_mst = false; | |
4385 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4386 | intel_dp->is_mst); | |
4387 | } | |
4388 | ||
c8c8fb33 | 4389 | goto out; |
4df6960e | 4390 | } |
a9756bb5 | 4391 | |
f21a2198 | 4392 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
cca0502b | 4393 | intel_encoder->type = INTEL_OUTPUT_DP; |
f21a2198 | 4394 | |
fe5a66f9 VS |
4395 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
4396 | yesno(intel_dp_source_supports_hbr2(intel_dp)), | |
4397 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); | |
4398 | ||
4399 | intel_dp_print_rates(intel_dp); | |
4400 | ||
7b3fc170 | 4401 | intel_dp_read_desc(intel_dp); |
0e390a33 | 4402 | |
c4e3170a VS |
4403 | intel_dp_configure_mst(intel_dp); |
4404 | ||
4405 | if (intel_dp->is_mst) { | |
f21a2198 SS |
4406 | /* |
4407 | * If we are in MST mode then this connector | |
4408 | * won't appear connected or have anything | |
4409 | * with EDID on it | |
4410 | */ | |
0e32b39c DA |
4411 | status = connector_status_disconnected; |
4412 | goto out; | |
7d23e3c3 SS |
4413 | } else if (connector->status == connector_status_connected) { |
4414 | /* | |
4415 | * If display was connected already and is still connected | |
4416 | * check links status, there has been known issues of | |
4417 | * link loss triggerring long pulse!!!! | |
4418 | */ | |
4419 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); | |
4420 | intel_dp_check_link_status(intel_dp); | |
4421 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
4422 | goto out; | |
0e32b39c DA |
4423 | } |
4424 | ||
4df6960e SS |
4425 | /* |
4426 | * Clearing NACK and defer counts to get their exact values | |
4427 | * while reading EDID which are required by Compliance tests | |
4428 | * 4.2.2.4 and 4.2.2.5 | |
4429 | */ | |
4430 | intel_dp->aux.i2c_nack_count = 0; | |
4431 | intel_dp->aux.i2c_defer_count = 0; | |
4432 | ||
beb60608 | 4433 | intel_dp_set_edid(intel_dp); |
5cb651a7 VS |
4434 | if (is_edp(intel_dp) || intel_connector->detect_edid) |
4435 | status = connector_status_connected; | |
7d23e3c3 | 4436 | intel_dp->detect_done = true; |
c8c8fb33 | 4437 | |
09b1eb13 TP |
4438 | /* Try to read the source of the interrupt */ |
4439 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
4440 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
4441 | sink_irq_vector != 0) { | |
09b1eb13 TP |
4442 | /* Clear interrupt source */ |
4443 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
4444 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4445 | sink_irq_vector); | |
4446 | ||
4447 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
4448 | intel_dp_handle_test_request(intel_dp); | |
4449 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
4450 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4451 | } | |
4452 | ||
c8c8fb33 | 4453 | out: |
5cb651a7 | 4454 | if (status != connector_status_connected && !intel_dp->is_mst) |
f21a2198 | 4455 | intel_dp_unset_edid(intel_dp); |
7d23e3c3 | 4456 | |
25f78f58 | 4457 | intel_display_power_put(to_i915(dev), power_domain); |
5cb651a7 | 4458 | return status; |
f21a2198 SS |
4459 | } |
4460 | ||
4461 | static enum drm_connector_status | |
4462 | intel_dp_detect(struct drm_connector *connector, bool force) | |
4463 | { | |
4464 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
5cb651a7 | 4465 | enum drm_connector_status status = connector->status; |
f21a2198 SS |
4466 | |
4467 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4468 | connector->base.id, connector->name); | |
4469 | ||
7d23e3c3 SS |
4470 | /* If full detect is not performed yet, do a full detect */ |
4471 | if (!intel_dp->detect_done) | |
5cb651a7 | 4472 | status = intel_dp_long_pulse(intel_dp->attached_connector); |
7d23e3c3 SS |
4473 | |
4474 | intel_dp->detect_done = false; | |
f21a2198 | 4475 | |
5cb651a7 | 4476 | return status; |
a4fc5ed6 KP |
4477 | } |
4478 | ||
beb60608 CW |
4479 | static void |
4480 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 4481 | { |
df0e9248 | 4482 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
beb60608 | 4483 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
25f78f58 | 4484 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
671dedd2 | 4485 | enum intel_display_power_domain power_domain; |
a4fc5ed6 | 4486 | |
beb60608 CW |
4487 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4488 | connector->base.id, connector->name); | |
4489 | intel_dp_unset_edid(intel_dp); | |
a4fc5ed6 | 4490 | |
beb60608 CW |
4491 | if (connector->status != connector_status_connected) |
4492 | return; | |
671dedd2 | 4493 | |
25f78f58 VS |
4494 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4495 | intel_display_power_get(dev_priv, power_domain); | |
beb60608 CW |
4496 | |
4497 | intel_dp_set_edid(intel_dp); | |
4498 | ||
25f78f58 | 4499 | intel_display_power_put(dev_priv, power_domain); |
beb60608 CW |
4500 | |
4501 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
cca0502b | 4502 | intel_encoder->type = INTEL_OUTPUT_DP; |
beb60608 CW |
4503 | } |
4504 | ||
4505 | static int intel_dp_get_modes(struct drm_connector *connector) | |
4506 | { | |
4507 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4508 | struct edid *edid; | |
4509 | ||
4510 | edid = intel_connector->detect_edid; | |
4511 | if (edid) { | |
4512 | int ret = intel_connector_update_modes(connector, edid); | |
4513 | if (ret) | |
4514 | return ret; | |
4515 | } | |
32f9d658 | 4516 | |
f8779fda | 4517 | /* if eDP has no EDID, fall back to fixed mode */ |
beb60608 CW |
4518 | if (is_edp(intel_attached_dp(connector)) && |
4519 | intel_connector->panel.fixed_mode) { | |
f8779fda | 4520 | struct drm_display_mode *mode; |
beb60608 CW |
4521 | |
4522 | mode = drm_mode_duplicate(connector->dev, | |
dd06f90e | 4523 | intel_connector->panel.fixed_mode); |
f8779fda | 4524 | if (mode) { |
32f9d658 ZW |
4525 | drm_mode_probed_add(connector, mode); |
4526 | return 1; | |
4527 | } | |
4528 | } | |
beb60608 | 4529 | |
32f9d658 | 4530 | return 0; |
a4fc5ed6 KP |
4531 | } |
4532 | ||
1aad7ac0 CW |
4533 | static bool |
4534 | intel_dp_detect_audio(struct drm_connector *connector) | |
4535 | { | |
1aad7ac0 | 4536 | bool has_audio = false; |
beb60608 | 4537 | struct edid *edid; |
1aad7ac0 | 4538 | |
beb60608 CW |
4539 | edid = to_intel_connector(connector)->detect_edid; |
4540 | if (edid) | |
1aad7ac0 | 4541 | has_audio = drm_detect_monitor_audio(edid); |
671dedd2 | 4542 | |
1aad7ac0 CW |
4543 | return has_audio; |
4544 | } | |
4545 | ||
f684960e CW |
4546 | static int |
4547 | intel_dp_set_property(struct drm_connector *connector, | |
4548 | struct drm_property *property, | |
4549 | uint64_t val) | |
4550 | { | |
fac5e23e | 4551 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
53b41837 | 4552 | struct intel_connector *intel_connector = to_intel_connector(connector); |
da63a9f2 PZ |
4553 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
4554 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
f684960e CW |
4555 | int ret; |
4556 | ||
662595df | 4557 | ret = drm_object_property_set_value(&connector->base, property, val); |
f684960e CW |
4558 | if (ret) |
4559 | return ret; | |
4560 | ||
3f43c48d | 4561 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
4562 | int i = val; |
4563 | bool has_audio; | |
4564 | ||
4565 | if (i == intel_dp->force_audio) | |
f684960e CW |
4566 | return 0; |
4567 | ||
1aad7ac0 | 4568 | intel_dp->force_audio = i; |
f684960e | 4569 | |
c3e5f67b | 4570 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
4571 | has_audio = intel_dp_detect_audio(connector); |
4572 | else | |
c3e5f67b | 4573 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
4574 | |
4575 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
4576 | return 0; |
4577 | ||
1aad7ac0 | 4578 | intel_dp->has_audio = has_audio; |
f684960e CW |
4579 | goto done; |
4580 | } | |
4581 | ||
e953fd7b | 4582 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 | 4583 | bool old_auto = intel_dp->color_range_auto; |
0f2a2a75 | 4584 | bool old_range = intel_dp->limited_color_range; |
ae4edb80 | 4585 | |
55bc60db VS |
4586 | switch (val) { |
4587 | case INTEL_BROADCAST_RGB_AUTO: | |
4588 | intel_dp->color_range_auto = true; | |
4589 | break; | |
4590 | case INTEL_BROADCAST_RGB_FULL: | |
4591 | intel_dp->color_range_auto = false; | |
0f2a2a75 | 4592 | intel_dp->limited_color_range = false; |
55bc60db VS |
4593 | break; |
4594 | case INTEL_BROADCAST_RGB_LIMITED: | |
4595 | intel_dp->color_range_auto = false; | |
0f2a2a75 | 4596 | intel_dp->limited_color_range = true; |
55bc60db VS |
4597 | break; |
4598 | default: | |
4599 | return -EINVAL; | |
4600 | } | |
ae4edb80 DV |
4601 | |
4602 | if (old_auto == intel_dp->color_range_auto && | |
0f2a2a75 | 4603 | old_range == intel_dp->limited_color_range) |
ae4edb80 DV |
4604 | return 0; |
4605 | ||
e953fd7b CW |
4606 | goto done; |
4607 | } | |
4608 | ||
53b41837 YN |
4609 | if (is_edp(intel_dp) && |
4610 | property == connector->dev->mode_config.scaling_mode_property) { | |
4611 | if (val == DRM_MODE_SCALE_NONE) { | |
4612 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
4613 | return -EINVAL; | |
4614 | } | |
234126c6 VS |
4615 | if (HAS_GMCH_DISPLAY(dev_priv) && |
4616 | val == DRM_MODE_SCALE_CENTER) { | |
4617 | DRM_DEBUG_KMS("centering not supported\n"); | |
4618 | return -EINVAL; | |
4619 | } | |
53b41837 YN |
4620 | |
4621 | if (intel_connector->panel.fitting_mode == val) { | |
4622 | /* the eDP scaling property is not changed */ | |
4623 | return 0; | |
4624 | } | |
4625 | intel_connector->panel.fitting_mode = val; | |
4626 | ||
4627 | goto done; | |
4628 | } | |
4629 | ||
f684960e CW |
4630 | return -EINVAL; |
4631 | ||
4632 | done: | |
c0c36b94 CW |
4633 | if (intel_encoder->base.crtc) |
4634 | intel_crtc_restore_mode(intel_encoder->base.crtc); | |
f684960e CW |
4635 | |
4636 | return 0; | |
4637 | } | |
4638 | ||
7a418e34 CW |
4639 | static int |
4640 | intel_dp_connector_register(struct drm_connector *connector) | |
4641 | { | |
4642 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1ebaa0b9 CW |
4643 | int ret; |
4644 | ||
4645 | ret = intel_connector_register(connector); | |
4646 | if (ret) | |
4647 | return ret; | |
7a418e34 CW |
4648 | |
4649 | i915_debugfs_connector_add(connector); | |
4650 | ||
4651 | DRM_DEBUG_KMS("registering %s bus for %s\n", | |
4652 | intel_dp->aux.name, connector->kdev->kobj.name); | |
4653 | ||
4654 | intel_dp->aux.dev = connector->kdev; | |
4655 | return drm_dp_aux_register(&intel_dp->aux); | |
4656 | } | |
4657 | ||
c191eca1 CW |
4658 | static void |
4659 | intel_dp_connector_unregister(struct drm_connector *connector) | |
4660 | { | |
4661 | drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); | |
4662 | intel_connector_unregister(connector); | |
4663 | } | |
4664 | ||
a4fc5ed6 | 4665 | static void |
73845adf | 4666 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 4667 | { |
1d508706 | 4668 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 4669 | |
10e972d3 | 4670 | kfree(intel_connector->detect_edid); |
beb60608 | 4671 | |
9cd300e0 JN |
4672 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4673 | kfree(intel_connector->edid); | |
4674 | ||
acd8db10 PZ |
4675 | /* Can't call is_edp() since the encoder may have been destroyed |
4676 | * already. */ | |
4677 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
1d508706 | 4678 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 4679 | |
a4fc5ed6 | 4680 | drm_connector_cleanup(connector); |
55f78c43 | 4681 | kfree(connector); |
a4fc5ed6 KP |
4682 | } |
4683 | ||
00c09d70 | 4684 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 4685 | { |
da63a9f2 PZ |
4686 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4687 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
24d05927 | 4688 | |
0e32b39c | 4689 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
bd943159 KP |
4690 | if (is_edp(intel_dp)) { |
4691 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
951468f3 VS |
4692 | /* |
4693 | * vdd might still be enabled do to the delayed vdd off. | |
4694 | * Make sure vdd is actually turned off here. | |
4695 | */ | |
773538e8 | 4696 | pps_lock(intel_dp); |
4be73780 | 4697 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 VS |
4698 | pps_unlock(intel_dp); |
4699 | ||
01527b31 CT |
4700 | if (intel_dp->edp_notifier.notifier_call) { |
4701 | unregister_reboot_notifier(&intel_dp->edp_notifier); | |
4702 | intel_dp->edp_notifier.notifier_call = NULL; | |
4703 | } | |
bd943159 | 4704 | } |
99681886 CW |
4705 | |
4706 | intel_dp_aux_fini(intel_dp); | |
4707 | ||
c8bd0e49 | 4708 | drm_encoder_cleanup(encoder); |
da63a9f2 | 4709 | kfree(intel_dig_port); |
24d05927 DV |
4710 | } |
4711 | ||
bf93ba67 | 4712 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
07f9cd0b ID |
4713 | { |
4714 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
4715 | ||
4716 | if (!is_edp(intel_dp)) | |
4717 | return; | |
4718 | ||
951468f3 VS |
4719 | /* |
4720 | * vdd might still be enabled do to the delayed vdd off. | |
4721 | * Make sure vdd is actually turned off here. | |
4722 | */ | |
afa4e53a | 4723 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
773538e8 | 4724 | pps_lock(intel_dp); |
07f9cd0b | 4725 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 | 4726 | pps_unlock(intel_dp); |
07f9cd0b ID |
4727 | } |
4728 | ||
49e6bc51 VS |
4729 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
4730 | { | |
4731 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4732 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 4733 | struct drm_i915_private *dev_priv = to_i915(dev); |
49e6bc51 VS |
4734 | enum intel_display_power_domain power_domain; |
4735 | ||
4736 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4737 | ||
4738 | if (!edp_have_panel_vdd(intel_dp)) | |
4739 | return; | |
4740 | ||
4741 | /* | |
4742 | * The VDD bit needs a power domain reference, so if the bit is | |
4743 | * already enabled when we boot or resume, grab this reference and | |
4744 | * schedule a vdd off, so we don't hold on to the reference | |
4745 | * indefinitely. | |
4746 | */ | |
4747 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); | |
25f78f58 | 4748 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
49e6bc51 VS |
4749 | intel_display_power_get(dev_priv, power_domain); |
4750 | ||
4751 | edp_panel_vdd_schedule_off(intel_dp); | |
4752 | } | |
4753 | ||
bf93ba67 | 4754 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
6d93c0c4 | 4755 | { |
64989ca4 | 4756 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
910530c0 SS |
4757 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4758 | struct intel_lspcon *lspcon = &intel_dig_port->lspcon; | |
4759 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
64989ca4 VS |
4760 | |
4761 | if (!HAS_DDI(dev_priv)) | |
4762 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
49e6bc51 | 4763 | |
910530c0 SS |
4764 | if (IS_GEN9(dev_priv) && lspcon->active) |
4765 | lspcon_resume(lspcon); | |
4766 | ||
49e6bc51 VS |
4767 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) |
4768 | return; | |
4769 | ||
49e6bc51 VS |
4770 | pps_lock(intel_dp); |
4771 | ||
335f752b ID |
4772 | /* Reinit the power sequencer, in case BIOS did something with it. */ |
4773 | intel_dp_pps_init(encoder->dev, intel_dp); | |
49e6bc51 VS |
4774 | intel_edp_panel_vdd_sanitize(intel_dp); |
4775 | ||
4776 | pps_unlock(intel_dp); | |
6d93c0c4 ID |
4777 | } |
4778 | ||
a4fc5ed6 | 4779 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
4d688a2a | 4780 | .dpms = drm_atomic_helper_connector_dpms, |
a4fc5ed6 | 4781 | .detect = intel_dp_detect, |
beb60608 | 4782 | .force = intel_dp_force, |
a4fc5ed6 | 4783 | .fill_modes = drm_helper_probe_single_connector_modes, |
f684960e | 4784 | .set_property = intel_dp_set_property, |
2545e4a6 | 4785 | .atomic_get_property = intel_connector_atomic_get_property, |
7a418e34 | 4786 | .late_register = intel_dp_connector_register, |
c191eca1 | 4787 | .early_unregister = intel_dp_connector_unregister, |
73845adf | 4788 | .destroy = intel_dp_connector_destroy, |
c6f95f27 | 4789 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 4790 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
a4fc5ed6 KP |
4791 | }; |
4792 | ||
4793 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
4794 | .get_modes = intel_dp_get_modes, | |
4795 | .mode_valid = intel_dp_mode_valid, | |
a4fc5ed6 KP |
4796 | }; |
4797 | ||
a4fc5ed6 | 4798 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
6d93c0c4 | 4799 | .reset = intel_dp_encoder_reset, |
24d05927 | 4800 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
4801 | }; |
4802 | ||
b2c5c181 | 4803 | enum irqreturn |
13cf5504 DA |
4804 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
4805 | { | |
4806 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1c767b33 | 4807 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
0e32b39c | 4808 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 4809 | struct drm_i915_private *dev_priv = to_i915(dev); |
1c767b33 | 4810 | enum intel_display_power_domain power_domain; |
b2c5c181 | 4811 | enum irqreturn ret = IRQ_NONE; |
1c767b33 | 4812 | |
2540058f TI |
4813 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
4814 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) | |
cca0502b | 4815 | intel_dig_port->base.type = INTEL_OUTPUT_DP; |
13cf5504 | 4816 | |
7a7f84cc VS |
4817 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
4818 | /* | |
4819 | * vdd off can generate a long pulse on eDP which | |
4820 | * would require vdd on to handle it, and thus we | |
4821 | * would end up in an endless cycle of | |
4822 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." | |
4823 | */ | |
4824 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", | |
4825 | port_name(intel_dig_port->port)); | |
a8b3d52f | 4826 | return IRQ_HANDLED; |
7a7f84cc VS |
4827 | } |
4828 | ||
26fbb774 VS |
4829 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
4830 | port_name(intel_dig_port->port), | |
0e32b39c | 4831 | long_hpd ? "long" : "short"); |
13cf5504 | 4832 | |
27d4efc5 VS |
4833 | if (long_hpd) { |
4834 | intel_dp->detect_done = false; | |
4835 | return IRQ_NONE; | |
4836 | } | |
4837 | ||
25f78f58 | 4838 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1c767b33 ID |
4839 | intel_display_power_get(dev_priv, power_domain); |
4840 | ||
27d4efc5 VS |
4841 | if (intel_dp->is_mst) { |
4842 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { | |
4843 | /* | |
4844 | * If we were in MST mode, and device is not | |
4845 | * there, get out of MST mode | |
4846 | */ | |
4847 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4848 | intel_dp->is_mst, intel_dp->mst_mgr.mst_state); | |
4849 | intel_dp->is_mst = false; | |
4850 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4851 | intel_dp->is_mst); | |
4852 | intel_dp->detect_done = false; | |
4853 | goto put_power; | |
0e32b39c | 4854 | } |
27d4efc5 | 4855 | } |
0e32b39c | 4856 | |
27d4efc5 VS |
4857 | if (!intel_dp->is_mst) { |
4858 | if (!intel_dp_short_pulse(intel_dp)) { | |
4859 | intel_dp->detect_done = false; | |
4860 | goto put_power; | |
39ff747b | 4861 | } |
0e32b39c | 4862 | } |
b2c5c181 DV |
4863 | |
4864 | ret = IRQ_HANDLED; | |
4865 | ||
1c767b33 ID |
4866 | put_power: |
4867 | intel_display_power_put(dev_priv, power_domain); | |
4868 | ||
4869 | return ret; | |
13cf5504 DA |
4870 | } |
4871 | ||
477ec328 | 4872 | /* check the VBT to see whether the eDP is on another port */ |
dd11bc10 | 4873 | bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port) |
36e83a18 | 4874 | { |
53ce81a7 VS |
4875 | /* |
4876 | * eDP not supported on g4x. so bail out early just | |
4877 | * for a bit extra safety in case the VBT is bonkers. | |
4878 | */ | |
dd11bc10 | 4879 | if (INTEL_GEN(dev_priv) < 5) |
53ce81a7 VS |
4880 | return false; |
4881 | ||
3b32a35b VS |
4882 | if (port == PORT_A) |
4883 | return true; | |
4884 | ||
951d9efe | 4885 | return intel_bios_is_port_edp(dev_priv, port); |
36e83a18 ZY |
4886 | } |
4887 | ||
0e32b39c | 4888 | void |
f684960e CW |
4889 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
4890 | { | |
53b41837 YN |
4891 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4892 | ||
3f43c48d | 4893 | intel_attach_force_audio_property(connector); |
e953fd7b | 4894 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 4895 | intel_dp->color_range_auto = true; |
53b41837 YN |
4896 | |
4897 | if (is_edp(intel_dp)) { | |
4898 | drm_mode_create_scaling_mode_property(connector->dev); | |
6de6d846 RC |
4899 | drm_object_attach_property( |
4900 | &connector->base, | |
53b41837 | 4901 | connector->dev->mode_config.scaling_mode_property, |
8e740cd1 YN |
4902 | DRM_MODE_SCALE_ASPECT); |
4903 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
53b41837 | 4904 | } |
f684960e CW |
4905 | } |
4906 | ||
dada1a9f ID |
4907 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
4908 | { | |
d28d4731 | 4909 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
dada1a9f ID |
4910 | intel_dp->last_power_on = jiffies; |
4911 | intel_dp->last_backlight_off = jiffies; | |
4912 | } | |
4913 | ||
67a54566 | 4914 | static void |
54648618 ID |
4915 | intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, |
4916 | struct intel_dp *intel_dp, struct edp_power_seq *seq) | |
67a54566 | 4917 | { |
b0a08bec | 4918 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
8e8232d5 | 4919 | struct pps_registers regs; |
453c5420 | 4920 | |
8e8232d5 | 4921 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
67a54566 DV |
4922 | |
4923 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
4924 | * the very first thing. */ | |
b0a08bec | 4925 | pp_ctl = ironlake_get_pp_control(intel_dp); |
67a54566 | 4926 | |
8e8232d5 ID |
4927 | pp_on = I915_READ(regs.pp_on); |
4928 | pp_off = I915_READ(regs.pp_off); | |
54648618 | 4929 | if (!IS_BROXTON(dev_priv)) { |
8e8232d5 ID |
4930 | I915_WRITE(regs.pp_ctrl, pp_ctl); |
4931 | pp_div = I915_READ(regs.pp_div); | |
b0a08bec | 4932 | } |
67a54566 DV |
4933 | |
4934 | /* Pull timing values out of registers */ | |
54648618 ID |
4935 | seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
4936 | PANEL_POWER_UP_DELAY_SHIFT; | |
67a54566 | 4937 | |
54648618 ID |
4938 | seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
4939 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
67a54566 | 4940 | |
54648618 ID |
4941 | seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
4942 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
67a54566 | 4943 | |
54648618 ID |
4944 | seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
4945 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
67a54566 | 4946 | |
54648618 | 4947 | if (IS_BROXTON(dev_priv)) { |
b0a08bec VK |
4948 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
4949 | BXT_POWER_CYCLE_DELAY_SHIFT; | |
4950 | if (tmp > 0) | |
54648618 | 4951 | seq->t11_t12 = (tmp - 1) * 1000; |
b0a08bec | 4952 | else |
54648618 | 4953 | seq->t11_t12 = 0; |
b0a08bec | 4954 | } else { |
54648618 | 4955 | seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
67a54566 | 4956 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
b0a08bec | 4957 | } |
54648618 ID |
4958 | } |
4959 | ||
de9c1b6b ID |
4960 | static void |
4961 | intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) | |
4962 | { | |
4963 | DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
4964 | state_name, | |
4965 | seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); | |
4966 | } | |
4967 | ||
4968 | static void | |
4969 | intel_pps_verify_state(struct drm_i915_private *dev_priv, | |
4970 | struct intel_dp *intel_dp) | |
4971 | { | |
4972 | struct edp_power_seq hw; | |
4973 | struct edp_power_seq *sw = &intel_dp->pps_delays; | |
4974 | ||
4975 | intel_pps_readout_hw_state(dev_priv, intel_dp, &hw); | |
4976 | ||
4977 | if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || | |
4978 | hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { | |
4979 | DRM_ERROR("PPS state mismatch\n"); | |
4980 | intel_pps_dump_state("sw", sw); | |
4981 | intel_pps_dump_state("hw", &hw); | |
4982 | } | |
4983 | } | |
4984 | ||
54648618 ID |
4985 | static void |
4986 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
4987 | struct intel_dp *intel_dp) | |
4988 | { | |
fac5e23e | 4989 | struct drm_i915_private *dev_priv = to_i915(dev); |
54648618 ID |
4990 | struct edp_power_seq cur, vbt, spec, |
4991 | *final = &intel_dp->pps_delays; | |
4992 | ||
4993 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4994 | ||
4995 | /* already initialized? */ | |
4996 | if (final->t11_t12 != 0) | |
4997 | return; | |
4998 | ||
4999 | intel_pps_readout_hw_state(dev_priv, intel_dp, &cur); | |
67a54566 | 5000 | |
de9c1b6b | 5001 | intel_pps_dump_state("cur", &cur); |
67a54566 | 5002 | |
6aa23e65 | 5003 | vbt = dev_priv->vbt.edp.pps; |
67a54566 DV |
5004 | |
5005 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
5006 | * our hw here, which are all in 100usec. */ | |
5007 | spec.t1_t3 = 210 * 10; | |
5008 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
5009 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
5010 | spec.t10 = 500 * 10; | |
5011 | /* This one is special and actually in units of 100ms, but zero | |
5012 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
5013 | * table multiplies it with 1000 to make it in units of 100usec, | |
5014 | * too. */ | |
5015 | spec.t11_t12 = (510 + 100) * 10; | |
5016 | ||
de9c1b6b | 5017 | intel_pps_dump_state("vbt", &vbt); |
67a54566 DV |
5018 | |
5019 | /* Use the max of the register settings and vbt. If both are | |
5020 | * unset, fall back to the spec limits. */ | |
36b5f425 | 5021 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
67a54566 DV |
5022 | spec.field : \ |
5023 | max(cur.field, vbt.field)) | |
5024 | assign_final(t1_t3); | |
5025 | assign_final(t8); | |
5026 | assign_final(t9); | |
5027 | assign_final(t10); | |
5028 | assign_final(t11_t12); | |
5029 | #undef assign_final | |
5030 | ||
36b5f425 | 5031 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
67a54566 DV |
5032 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
5033 | intel_dp->backlight_on_delay = get_delay(t8); | |
5034 | intel_dp->backlight_off_delay = get_delay(t9); | |
5035 | intel_dp->panel_power_down_delay = get_delay(t10); | |
5036 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
5037 | #undef get_delay | |
5038 | ||
f30d26e4 JN |
5039 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
5040 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
5041 | intel_dp->panel_power_cycle_delay); | |
5042 | ||
5043 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
5044 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
de9c1b6b ID |
5045 | |
5046 | /* | |
5047 | * We override the HW backlight delays to 1 because we do manual waits | |
5048 | * on them. For T8, even BSpec recommends doing it. For T9, if we | |
5049 | * don't do this, we'll end up waiting for the backlight off delay | |
5050 | * twice: once when we do the manual sleep, and once when we disable | |
5051 | * the panel and wait for the PP_STATUS bit to become zero. | |
5052 | */ | |
5053 | final->t8 = 1; | |
5054 | final->t9 = 1; | |
f30d26e4 JN |
5055 | } |
5056 | ||
5057 | static void | |
5058 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
8581f1b5 VS |
5059 | struct intel_dp *intel_dp, |
5060 | bool force_disable_vdd) | |
f30d26e4 | 5061 | { |
fac5e23e | 5062 | struct drm_i915_private *dev_priv = to_i915(dev); |
453c5420 | 5063 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
e7dc33f3 | 5064 | int div = dev_priv->rawclk_freq / 1000; |
8e8232d5 | 5065 | struct pps_registers regs; |
ad933b56 | 5066 | enum port port = dp_to_dig_port(intel_dp)->port; |
36b5f425 | 5067 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
453c5420 | 5068 | |
e39b999a | 5069 | lockdep_assert_held(&dev_priv->pps_mutex); |
453c5420 | 5070 | |
8e8232d5 | 5071 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
453c5420 | 5072 | |
8581f1b5 VS |
5073 | /* |
5074 | * On some VLV machines the BIOS can leave the VDD | |
5075 | * enabled even on power seqeuencers which aren't | |
5076 | * hooked up to any port. This would mess up the | |
5077 | * power domain tracking the first time we pick | |
5078 | * one of these power sequencers for use since | |
5079 | * edp_panel_vdd_on() would notice that the VDD was | |
5080 | * already on and therefore wouldn't grab the power | |
5081 | * domain reference. Disable VDD first to avoid this. | |
5082 | * This also avoids spuriously turning the VDD on as | |
5083 | * soon as the new power seqeuencer gets initialized. | |
5084 | */ | |
5085 | if (force_disable_vdd) { | |
5086 | u32 pp = ironlake_get_pp_control(intel_dp); | |
5087 | ||
5088 | WARN(pp & PANEL_POWER_ON, "Panel power already on\n"); | |
5089 | ||
5090 | if (pp & EDP_FORCE_VDD) | |
5091 | DRM_DEBUG_KMS("VDD already on, disabling first\n"); | |
5092 | ||
5093 | pp &= ~EDP_FORCE_VDD; | |
5094 | ||
5095 | I915_WRITE(regs.pp_ctrl, pp); | |
5096 | } | |
5097 | ||
f30d26e4 | 5098 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
de9c1b6b ID |
5099 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
5100 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 5101 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
5102 | /* Compute the divisor for the pp clock, simply match the Bspec |
5103 | * formula. */ | |
e2d214ae | 5104 | if (IS_BROXTON(dev_priv)) { |
8e8232d5 | 5105 | pp_div = I915_READ(regs.pp_ctrl); |
b0a08bec VK |
5106 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
5107 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) | |
5108 | << BXT_POWER_CYCLE_DELAY_SHIFT); | |
5109 | } else { | |
5110 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; | |
5111 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) | |
5112 | << PANEL_POWER_CYCLE_DELAY_SHIFT); | |
5113 | } | |
67a54566 DV |
5114 | |
5115 | /* Haswell doesn't have any port selection bits for the panel | |
5116 | * power sequencer any more. */ | |
920a14b2 | 5117 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
ad933b56 | 5118 | port_sel = PANEL_PORT_SELECT_VLV(port); |
6e266956 | 5119 | } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
ad933b56 | 5120 | if (port == PORT_A) |
a24c144c | 5121 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 5122 | else |
a24c144c | 5123 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
5124 | } |
5125 | ||
453c5420 JB |
5126 | pp_on |= port_sel; |
5127 | ||
8e8232d5 ID |
5128 | I915_WRITE(regs.pp_on, pp_on); |
5129 | I915_WRITE(regs.pp_off, pp_off); | |
e2d214ae | 5130 | if (IS_BROXTON(dev_priv)) |
8e8232d5 | 5131 | I915_WRITE(regs.pp_ctrl, pp_div); |
b0a08bec | 5132 | else |
8e8232d5 | 5133 | I915_WRITE(regs.pp_div, pp_div); |
67a54566 | 5134 | |
67a54566 | 5135 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
8e8232d5 ID |
5136 | I915_READ(regs.pp_on), |
5137 | I915_READ(regs.pp_off), | |
e2d214ae | 5138 | IS_BROXTON(dev_priv) ? |
8e8232d5 ID |
5139 | (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : |
5140 | I915_READ(regs.pp_div)); | |
f684960e CW |
5141 | } |
5142 | ||
335f752b ID |
5143 | static void intel_dp_pps_init(struct drm_device *dev, |
5144 | struct intel_dp *intel_dp) | |
5145 | { | |
920a14b2 TU |
5146 | struct drm_i915_private *dev_priv = to_i915(dev); |
5147 | ||
5148 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
335f752b ID |
5149 | vlv_initial_power_sequencer_setup(intel_dp); |
5150 | } else { | |
5151 | intel_dp_init_panel_power_sequencer(dev, intel_dp); | |
8581f1b5 | 5152 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false); |
335f752b ID |
5153 | } |
5154 | } | |
5155 | ||
b33a2815 VK |
5156 | /** |
5157 | * intel_dp_set_drrs_state - program registers for RR switch to take effect | |
5423adf1 | 5158 | * @dev_priv: i915 device |
e896402c | 5159 | * @crtc_state: a pointer to the active intel_crtc_state |
b33a2815 VK |
5160 | * @refresh_rate: RR to be programmed |
5161 | * | |
5162 | * This function gets called when refresh rate (RR) has to be changed from | |
5163 | * one frequency to another. Switches can be between high and low RR | |
5164 | * supported by the panel or to any other RR based on media playback (in | |
5165 | * this case, RR value needs to be passed from user space). | |
5166 | * | |
5167 | * The caller of this function needs to take a lock on dev_priv->drrs. | |
5168 | */ | |
85cb48a1 ML |
5169 | static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, |
5170 | struct intel_crtc_state *crtc_state, | |
5171 | int refresh_rate) | |
439d7ac0 | 5172 | { |
439d7ac0 | 5173 | struct intel_encoder *encoder; |
96178eeb VK |
5174 | struct intel_digital_port *dig_port = NULL; |
5175 | struct intel_dp *intel_dp = dev_priv->drrs.dp; | |
85cb48a1 | 5176 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
96178eeb | 5177 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
439d7ac0 PB |
5178 | |
5179 | if (refresh_rate <= 0) { | |
5180 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); | |
5181 | return; | |
5182 | } | |
5183 | ||
96178eeb VK |
5184 | if (intel_dp == NULL) { |
5185 | DRM_DEBUG_KMS("DRRS not supported.\n"); | |
439d7ac0 PB |
5186 | return; |
5187 | } | |
5188 | ||
1fcc9d1c | 5189 | /* |
e4d59f6b RV |
5190 | * FIXME: This needs proper synchronization with psr state for some |
5191 | * platforms that cannot have PSR and DRRS enabled at the same time. | |
1fcc9d1c | 5192 | */ |
439d7ac0 | 5193 | |
96178eeb VK |
5194 | dig_port = dp_to_dig_port(intel_dp); |
5195 | encoder = &dig_port->base; | |
723f9aab | 5196 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
439d7ac0 PB |
5197 | |
5198 | if (!intel_crtc) { | |
5199 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); | |
5200 | return; | |
5201 | } | |
5202 | ||
96178eeb | 5203 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
439d7ac0 PB |
5204 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5205 | return; | |
5206 | } | |
5207 | ||
96178eeb VK |
5208 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5209 | refresh_rate) | |
439d7ac0 PB |
5210 | index = DRRS_LOW_RR; |
5211 | ||
96178eeb | 5212 | if (index == dev_priv->drrs.refresh_rate_type) { |
439d7ac0 PB |
5213 | DRM_DEBUG_KMS( |
5214 | "DRRS requested for previously set RR...ignoring\n"); | |
5215 | return; | |
5216 | } | |
5217 | ||
85cb48a1 | 5218 | if (!crtc_state->base.active) { |
439d7ac0 PB |
5219 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
5220 | return; | |
5221 | } | |
5222 | ||
85cb48a1 | 5223 | if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { |
a4c30b1d VK |
5224 | switch (index) { |
5225 | case DRRS_HIGH_RR: | |
5226 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
5227 | break; | |
5228 | case DRRS_LOW_RR: | |
5229 | intel_dp_set_m_n(intel_crtc, M2_N2); | |
5230 | break; | |
5231 | case DRRS_MAX_RR: | |
5232 | default: | |
5233 | DRM_ERROR("Unsupported refreshrate type\n"); | |
5234 | } | |
85cb48a1 ML |
5235 | } else if (INTEL_GEN(dev_priv) > 6) { |
5236 | i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); | |
649636ef | 5237 | u32 val; |
a4c30b1d | 5238 | |
649636ef | 5239 | val = I915_READ(reg); |
439d7ac0 | 5240 | if (index > DRRS_HIGH_RR) { |
85cb48a1 | 5241 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
5242 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5243 | else | |
5244 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 5245 | } else { |
85cb48a1 | 5246 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
5247 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5248 | else | |
5249 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 PB |
5250 | } |
5251 | I915_WRITE(reg, val); | |
5252 | } | |
5253 | ||
4e9ac947 VK |
5254 | dev_priv->drrs.refresh_rate_type = index; |
5255 | ||
5256 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); | |
5257 | } | |
5258 | ||
b33a2815 VK |
5259 | /** |
5260 | * intel_edp_drrs_enable - init drrs struct if supported | |
5261 | * @intel_dp: DP struct | |
5423adf1 | 5262 | * @crtc_state: A pointer to the active crtc state. |
b33a2815 VK |
5263 | * |
5264 | * Initializes frontbuffer_bits and drrs.dp | |
5265 | */ | |
85cb48a1 ML |
5266 | void intel_edp_drrs_enable(struct intel_dp *intel_dp, |
5267 | struct intel_crtc_state *crtc_state) | |
c395578e VK |
5268 | { |
5269 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 5270 | struct drm_i915_private *dev_priv = to_i915(dev); |
c395578e | 5271 | |
85cb48a1 | 5272 | if (!crtc_state->has_drrs) { |
c395578e VK |
5273 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
5274 | return; | |
5275 | } | |
5276 | ||
5277 | mutex_lock(&dev_priv->drrs.mutex); | |
5278 | if (WARN_ON(dev_priv->drrs.dp)) { | |
5279 | DRM_ERROR("DRRS already enabled\n"); | |
5280 | goto unlock; | |
5281 | } | |
5282 | ||
5283 | dev_priv->drrs.busy_frontbuffer_bits = 0; | |
5284 | ||
5285 | dev_priv->drrs.dp = intel_dp; | |
5286 | ||
5287 | unlock: | |
5288 | mutex_unlock(&dev_priv->drrs.mutex); | |
5289 | } | |
5290 | ||
b33a2815 VK |
5291 | /** |
5292 | * intel_edp_drrs_disable - Disable DRRS | |
5293 | * @intel_dp: DP struct | |
5423adf1 | 5294 | * @old_crtc_state: Pointer to old crtc_state. |
b33a2815 VK |
5295 | * |
5296 | */ | |
85cb48a1 ML |
5297 | void intel_edp_drrs_disable(struct intel_dp *intel_dp, |
5298 | struct intel_crtc_state *old_crtc_state) | |
c395578e VK |
5299 | { |
5300 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 5301 | struct drm_i915_private *dev_priv = to_i915(dev); |
c395578e | 5302 | |
85cb48a1 | 5303 | if (!old_crtc_state->has_drrs) |
c395578e VK |
5304 | return; |
5305 | ||
5306 | mutex_lock(&dev_priv->drrs.mutex); | |
5307 | if (!dev_priv->drrs.dp) { | |
5308 | mutex_unlock(&dev_priv->drrs.mutex); | |
5309 | return; | |
5310 | } | |
5311 | ||
5312 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) | |
85cb48a1 ML |
5313 | intel_dp_set_drrs_state(dev_priv, old_crtc_state, |
5314 | intel_dp->attached_connector->panel.fixed_mode->vrefresh); | |
c395578e VK |
5315 | |
5316 | dev_priv->drrs.dp = NULL; | |
5317 | mutex_unlock(&dev_priv->drrs.mutex); | |
5318 | ||
5319 | cancel_delayed_work_sync(&dev_priv->drrs.work); | |
5320 | } | |
5321 | ||
4e9ac947 VK |
5322 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5323 | { | |
5324 | struct drm_i915_private *dev_priv = | |
5325 | container_of(work, typeof(*dev_priv), drrs.work.work); | |
5326 | struct intel_dp *intel_dp; | |
5327 | ||
5328 | mutex_lock(&dev_priv->drrs.mutex); | |
5329 | ||
5330 | intel_dp = dev_priv->drrs.dp; | |
5331 | ||
5332 | if (!intel_dp) | |
5333 | goto unlock; | |
5334 | ||
439d7ac0 | 5335 | /* |
4e9ac947 VK |
5336 | * The delayed work can race with an invalidate hence we need to |
5337 | * recheck. | |
439d7ac0 PB |
5338 | */ |
5339 | ||
4e9ac947 VK |
5340 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5341 | goto unlock; | |
439d7ac0 | 5342 | |
85cb48a1 ML |
5343 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { |
5344 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; | |
5345 | ||
5346 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, | |
5347 | intel_dp->attached_connector->panel.downclock_mode->vrefresh); | |
5348 | } | |
439d7ac0 | 5349 | |
4e9ac947 | 5350 | unlock: |
4e9ac947 | 5351 | mutex_unlock(&dev_priv->drrs.mutex); |
439d7ac0 PB |
5352 | } |
5353 | ||
b33a2815 | 5354 | /** |
0ddfd203 | 5355 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5748b6a1 | 5356 | * @dev_priv: i915 device |
b33a2815 VK |
5357 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5358 | * | |
0ddfd203 R |
5359 | * This function gets called everytime rendering on the given planes start. |
5360 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). | |
b33a2815 VK |
5361 | * |
5362 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5363 | */ | |
5748b6a1 CW |
5364 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
5365 | unsigned int frontbuffer_bits) | |
a93fad0f | 5366 | { |
a93fad0f VK |
5367 | struct drm_crtc *crtc; |
5368 | enum pipe pipe; | |
5369 | ||
9da7d693 | 5370 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5371 | return; |
5372 | ||
88f933a8 | 5373 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5374 | |
a93fad0f | 5375 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5376 | if (!dev_priv->drrs.dp) { |
5377 | mutex_unlock(&dev_priv->drrs.mutex); | |
5378 | return; | |
5379 | } | |
5380 | ||
a93fad0f VK |
5381 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5382 | pipe = to_intel_crtc(crtc)->pipe; | |
5383 | ||
c1d038c6 DV |
5384 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5385 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; | |
5386 | ||
0ddfd203 | 5387 | /* invalidate means busy screen hence upclock */ |
c1d038c6 | 5388 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
5389 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
5390 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
a93fad0f | 5391 | |
a93fad0f VK |
5392 | mutex_unlock(&dev_priv->drrs.mutex); |
5393 | } | |
5394 | ||
b33a2815 | 5395 | /** |
0ddfd203 | 5396 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5748b6a1 | 5397 | * @dev_priv: i915 device |
b33a2815 VK |
5398 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5399 | * | |
0ddfd203 R |
5400 | * This function gets called every time rendering on the given planes has |
5401 | * completed or flip on a crtc is completed. So DRRS should be upclocked | |
5402 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, | |
5403 | * if no other planes are dirty. | |
b33a2815 VK |
5404 | * |
5405 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5406 | */ | |
5748b6a1 CW |
5407 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, |
5408 | unsigned int frontbuffer_bits) | |
a93fad0f | 5409 | { |
a93fad0f VK |
5410 | struct drm_crtc *crtc; |
5411 | enum pipe pipe; | |
5412 | ||
9da7d693 | 5413 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5414 | return; |
5415 | ||
88f933a8 | 5416 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5417 | |
a93fad0f | 5418 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5419 | if (!dev_priv->drrs.dp) { |
5420 | mutex_unlock(&dev_priv->drrs.mutex); | |
5421 | return; | |
5422 | } | |
5423 | ||
a93fad0f VK |
5424 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5425 | pipe = to_intel_crtc(crtc)->pipe; | |
c1d038c6 DV |
5426 | |
5427 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
a93fad0f VK |
5428 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5429 | ||
0ddfd203 | 5430 | /* flush means busy screen hence upclock */ |
c1d038c6 | 5431 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
5432 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
5433 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
0ddfd203 R |
5434 | |
5435 | /* | |
5436 | * flush also means no more activity hence schedule downclock, if all | |
5437 | * other fbs are quiescent too | |
5438 | */ | |
5439 | if (!dev_priv->drrs.busy_frontbuffer_bits) | |
a93fad0f VK |
5440 | schedule_delayed_work(&dev_priv->drrs.work, |
5441 | msecs_to_jiffies(1000)); | |
5442 | mutex_unlock(&dev_priv->drrs.mutex); | |
5443 | } | |
5444 | ||
b33a2815 VK |
5445 | /** |
5446 | * DOC: Display Refresh Rate Switching (DRRS) | |
5447 | * | |
5448 | * Display Refresh Rate Switching (DRRS) is a power conservation feature | |
5449 | * which enables swtching between low and high refresh rates, | |
5450 | * dynamically, based on the usage scenario. This feature is applicable | |
5451 | * for internal panels. | |
5452 | * | |
5453 | * Indication that the panel supports DRRS is given by the panel EDID, which | |
5454 | * would list multiple refresh rates for one resolution. | |
5455 | * | |
5456 | * DRRS is of 2 types - static and seamless. | |
5457 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset | |
5458 | * (may appear as a blink on screen) and is used in dock-undock scenario. | |
5459 | * Seamless DRRS involves changing RR without any visual effect to the user | |
5460 | * and can be used during normal system usage. This is done by programming | |
5461 | * certain registers. | |
5462 | * | |
5463 | * Support for static/seamless DRRS may be indicated in the VBT based on | |
5464 | * inputs from the panel spec. | |
5465 | * | |
5466 | * DRRS saves power by switching to low RR based on usage scenarios. | |
5467 | * | |
2e7a5701 DV |
5468 | * The implementation is based on frontbuffer tracking implementation. When |
5469 | * there is a disturbance on the screen triggered by user activity or a periodic | |
5470 | * system activity, DRRS is disabled (RR is changed to high RR). When there is | |
5471 | * no movement on screen, after a timeout of 1 second, a switch to low RR is | |
5472 | * made. | |
5473 | * | |
5474 | * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() | |
5475 | * and intel_edp_drrs_flush() are called. | |
b33a2815 VK |
5476 | * |
5477 | * DRRS can be further extended to support other internal panels and also | |
5478 | * the scenario of video playback wherein RR is set based on the rate | |
5479 | * requested by userspace. | |
5480 | */ | |
5481 | ||
5482 | /** | |
5483 | * intel_dp_drrs_init - Init basic DRRS work and mutex. | |
5484 | * @intel_connector: eDP connector | |
5485 | * @fixed_mode: preferred mode of panel | |
5486 | * | |
5487 | * This function is called only once at driver load to initialize basic | |
5488 | * DRRS stuff. | |
5489 | * | |
5490 | * Returns: | |
5491 | * Downclock mode if panel supports it, else return NULL. | |
5492 | * DRRS support is determined by the presence of downclock mode (apart | |
5493 | * from VBT setting). | |
5494 | */ | |
4f9db5b5 | 5495 | static struct drm_display_mode * |
96178eeb VK |
5496 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5497 | struct drm_display_mode *fixed_mode) | |
4f9db5b5 PB |
5498 | { |
5499 | struct drm_connector *connector = &intel_connector->base; | |
96178eeb | 5500 | struct drm_device *dev = connector->dev; |
fac5e23e | 5501 | struct drm_i915_private *dev_priv = to_i915(dev); |
4f9db5b5 PB |
5502 | struct drm_display_mode *downclock_mode = NULL; |
5503 | ||
9da7d693 DV |
5504 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5505 | mutex_init(&dev_priv->drrs.mutex); | |
5506 | ||
dd11bc10 | 5507 | if (INTEL_GEN(dev_priv) <= 6) { |
4f9db5b5 PB |
5508 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
5509 | return NULL; | |
5510 | } | |
5511 | ||
5512 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
4079b8d1 | 5513 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
4f9db5b5 PB |
5514 | return NULL; |
5515 | } | |
5516 | ||
5517 | downclock_mode = intel_find_panel_downclock | |
5518 | (dev, fixed_mode, connector); | |
5519 | ||
5520 | if (!downclock_mode) { | |
a1d26342 | 5521 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
4f9db5b5 PB |
5522 | return NULL; |
5523 | } | |
5524 | ||
96178eeb | 5525 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
4f9db5b5 | 5526 | |
96178eeb | 5527 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
4079b8d1 | 5528 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
4f9db5b5 PB |
5529 | return downclock_mode; |
5530 | } | |
5531 | ||
ed92f0b2 | 5532 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 5533 | struct intel_connector *intel_connector) |
ed92f0b2 PZ |
5534 | { |
5535 | struct drm_connector *connector = &intel_connector->base; | |
5536 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
63635217 PZ |
5537 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5538 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 5539 | struct drm_i915_private *dev_priv = to_i915(dev); |
ed92f0b2 | 5540 | struct drm_display_mode *fixed_mode = NULL; |
4f9db5b5 | 5541 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 PZ |
5542 | bool has_dpcd; |
5543 | struct drm_display_mode *scan; | |
5544 | struct edid *edid; | |
6517d273 | 5545 | enum pipe pipe = INVALID_PIPE; |
ed92f0b2 PZ |
5546 | |
5547 | if (!is_edp(intel_dp)) | |
5548 | return true; | |
5549 | ||
97a824e1 ID |
5550 | /* |
5551 | * On IBX/CPT we may get here with LVDS already registered. Since the | |
5552 | * driver uses the only internal power sequencer available for both | |
5553 | * eDP and LVDS bail out early in this case to prevent interfering | |
5554 | * with an already powered-on LVDS power sequencer. | |
5555 | */ | |
5556 | if (intel_get_lvds_encoder(dev)) { | |
5557 | WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); | |
5558 | DRM_INFO("LVDS was detected, not registering eDP\n"); | |
5559 | ||
5560 | return false; | |
5561 | } | |
5562 | ||
49e6bc51 | 5563 | pps_lock(intel_dp); |
b4d06ede ID |
5564 | |
5565 | intel_dp_init_panel_power_timestamps(intel_dp); | |
335f752b | 5566 | intel_dp_pps_init(dev, intel_dp); |
49e6bc51 | 5567 | intel_edp_panel_vdd_sanitize(intel_dp); |
b4d06ede | 5568 | |
49e6bc51 | 5569 | pps_unlock(intel_dp); |
63635217 | 5570 | |
ed92f0b2 | 5571 | /* Cache DPCD and EDID for edp. */ |
fe5a66f9 | 5572 | has_dpcd = intel_edp_init_dpcd(intel_dp); |
ed92f0b2 | 5573 | |
fe5a66f9 | 5574 | if (!has_dpcd) { |
ed92f0b2 PZ |
5575 | /* if this fails, presume the device is a ghost */ |
5576 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
b4d06ede | 5577 | goto out_vdd_off; |
ed92f0b2 PZ |
5578 | } |
5579 | ||
060c8778 | 5580 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 5581 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
5582 | if (edid) { |
5583 | if (drm_add_edid_modes(connector, edid)) { | |
5584 | drm_mode_connector_update_edid_property(connector, | |
5585 | edid); | |
5586 | drm_edid_to_eld(connector, edid); | |
5587 | } else { | |
5588 | kfree(edid); | |
5589 | edid = ERR_PTR(-EINVAL); | |
5590 | } | |
5591 | } else { | |
5592 | edid = ERR_PTR(-ENOENT); | |
5593 | } | |
5594 | intel_connector->edid = edid; | |
5595 | ||
5596 | /* prefer fixed mode from EDID if available */ | |
5597 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
5598 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
5599 | fixed_mode = drm_mode_duplicate(dev, scan); | |
4f9db5b5 | 5600 | downclock_mode = intel_dp_drrs_init( |
4f9db5b5 | 5601 | intel_connector, fixed_mode); |
ed92f0b2 PZ |
5602 | break; |
5603 | } | |
5604 | } | |
5605 | ||
5606 | /* fallback to VBT if available for eDP */ | |
5607 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
5608 | fixed_mode = drm_mode_duplicate(dev, | |
5609 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
df457245 | 5610 | if (fixed_mode) { |
ed92f0b2 | 5611 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
df457245 VS |
5612 | connector->display_info.width_mm = fixed_mode->width_mm; |
5613 | connector->display_info.height_mm = fixed_mode->height_mm; | |
5614 | } | |
ed92f0b2 | 5615 | } |
060c8778 | 5616 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 5617 | |
920a14b2 | 5618 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
01527b31 CT |
5619 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
5620 | register_reboot_notifier(&intel_dp->edp_notifier); | |
6517d273 VS |
5621 | |
5622 | /* | |
5623 | * Figure out the current pipe for the initial backlight setup. | |
5624 | * If the current pipe isn't valid, try the PPS pipe, and if that | |
5625 | * fails just assume pipe A. | |
5626 | */ | |
920a14b2 | 5627 | if (IS_CHERRYVIEW(dev_priv)) |
6517d273 VS |
5628 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); |
5629 | else | |
5630 | pipe = PORT_TO_PIPE(intel_dp->DP); | |
5631 | ||
5632 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5633 | pipe = intel_dp->pps_pipe; | |
5634 | ||
5635 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5636 | pipe = PIPE_A; | |
5637 | ||
5638 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", | |
5639 | pipe_name(pipe)); | |
01527b31 CT |
5640 | } |
5641 | ||
4f9db5b5 | 5642 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5507faeb | 5643 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
6517d273 | 5644 | intel_panel_setup_backlight(connector, pipe); |
ed92f0b2 PZ |
5645 | |
5646 | return true; | |
b4d06ede ID |
5647 | |
5648 | out_vdd_off: | |
5649 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
5650 | /* | |
5651 | * vdd might still be enabled do to the delayed vdd off. | |
5652 | * Make sure vdd is actually turned off here. | |
5653 | */ | |
5654 | pps_lock(intel_dp); | |
5655 | edp_panel_vdd_off_sync(intel_dp); | |
5656 | pps_unlock(intel_dp); | |
5657 | ||
5658 | return false; | |
ed92f0b2 PZ |
5659 | } |
5660 | ||
16c25533 | 5661 | bool |
f0fec3f2 PZ |
5662 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5663 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 5664 | { |
f0fec3f2 PZ |
5665 | struct drm_connector *connector = &intel_connector->base; |
5666 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
5667 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
5668 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 5669 | struct drm_i915_private *dev_priv = to_i915(dev); |
174edf1f | 5670 | enum port port = intel_dig_port->port; |
7a418e34 | 5671 | int type; |
a4fc5ed6 | 5672 | |
ccb1a831 VS |
5673 | if (WARN(intel_dig_port->max_lanes < 1, |
5674 | "Not enough lanes (%d) for DP on port %c\n", | |
5675 | intel_dig_port->max_lanes, port_name(port))) | |
5676 | return false; | |
5677 | ||
a4a5d2f8 VS |
5678 | intel_dp->pps_pipe = INVALID_PIPE; |
5679 | ||
ec5b01dd | 5680 | /* intel_dp vfuncs */ |
dd11bc10 | 5681 | if (INTEL_GEN(dev_priv) >= 9) |
b6b5e383 | 5682 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
8652744b | 5683 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ec5b01dd | 5684 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
6e266956 | 5685 | else if (HAS_PCH_SPLIT(dev_priv)) |
ec5b01dd DL |
5686 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
5687 | else | |
6ffb1be7 | 5688 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; |
ec5b01dd | 5689 | |
dd11bc10 | 5690 | if (INTEL_GEN(dev_priv) >= 9) |
b9ca5fad DL |
5691 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
5692 | else | |
6ffb1be7 | 5693 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; |
153b1100 | 5694 | |
4f8036a2 | 5695 | if (HAS_DDI(dev_priv)) |
ad64217b ACO |
5696 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; |
5697 | ||
0767935e DV |
5698 | /* Preserve the current hw state. */ |
5699 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 5700 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 5701 | |
dd11bc10 | 5702 | if (intel_dp_is_edp(dev_priv, port)) |
b329530c | 5703 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
5704 | else |
5705 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 5706 | |
f7d24902 ID |
5707 | /* |
5708 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
5709 | * for DP the encoder type can be set by the caller to | |
5710 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
5711 | */ | |
5712 | if (type == DRM_MODE_CONNECTOR_eDP) | |
5713 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
5714 | ||
c17ed5b5 | 5715 | /* eDP only on port B and/or C on vlv/chv */ |
920a14b2 | 5716 | if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 5717 | is_edp(intel_dp) && port != PORT_B && port != PORT_C)) |
c17ed5b5 VS |
5718 | return false; |
5719 | ||
e7281eab ID |
5720 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
5721 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
5722 | port_name(port)); | |
5723 | ||
b329530c | 5724 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
5725 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
5726 | ||
a4fc5ed6 KP |
5727 | connector->interlace_allowed = true; |
5728 | connector->doublescan_allowed = 0; | |
5729 | ||
b6339585 | 5730 | intel_dp_aux_init(intel_dp); |
7a418e34 | 5731 | |
f0fec3f2 | 5732 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 5733 | edp_panel_vdd_work); |
a4fc5ed6 | 5734 | |
df0e9248 | 5735 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 | 5736 | |
4f8036a2 | 5737 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
5738 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
5739 | else | |
5740 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
5741 | ||
0b99836f | 5742 | /* Set up the hotplug pin. */ |
ab9d7c30 PZ |
5743 | switch (port) { |
5744 | case PORT_A: | |
1d843f9d | 5745 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
5746 | break; |
5747 | case PORT_B: | |
1d843f9d | 5748 | intel_encoder->hpd_pin = HPD_PORT_B; |
e2d214ae | 5749 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
cf1d5883 | 5750 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
5751 | break; |
5752 | case PORT_C: | |
1d843f9d | 5753 | intel_encoder->hpd_pin = HPD_PORT_C; |
ab9d7c30 PZ |
5754 | break; |
5755 | case PORT_D: | |
1d843f9d | 5756 | intel_encoder->hpd_pin = HPD_PORT_D; |
ab9d7c30 | 5757 | break; |
26951caf XZ |
5758 | case PORT_E: |
5759 | intel_encoder->hpd_pin = HPD_PORT_E; | |
5760 | break; | |
ab9d7c30 | 5761 | default: |
ad1c0b19 | 5762 | BUG(); |
5eb08b69 ZW |
5763 | } |
5764 | ||
0e32b39c | 5765 | /* init MST on ports that can support it */ |
56b857a5 | 5766 | if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) && |
0c9b3715 JN |
5767 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
5768 | intel_dp_mst_encoder_init(intel_dig_port, | |
5769 | intel_connector->base.base.id); | |
0e32b39c | 5770 | |
36b5f425 | 5771 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
a121f4e5 VS |
5772 | intel_dp_aux_fini(intel_dp); |
5773 | intel_dp_mst_encoder_cleanup(intel_dig_port); | |
5774 | goto fail; | |
b2f246a8 | 5775 | } |
32f9d658 | 5776 | |
f684960e CW |
5777 | intel_dp_add_properties(intel_dp, connector); |
5778 | ||
a4fc5ed6 KP |
5779 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
5780 | * 0xd. Failure to do so will result in spurious interrupts being | |
5781 | * generated on the port when a cable is not attached. | |
5782 | */ | |
50a0bc90 | 5783 | if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { |
a4fc5ed6 KP |
5784 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
5785 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
5786 | } | |
16c25533 PZ |
5787 | |
5788 | return true; | |
a121f4e5 VS |
5789 | |
5790 | fail: | |
a121f4e5 VS |
5791 | drm_connector_cleanup(connector); |
5792 | ||
5793 | return false; | |
a4fc5ed6 | 5794 | } |
f0fec3f2 | 5795 | |
457c52d8 CW |
5796 | bool intel_dp_init(struct drm_device *dev, |
5797 | i915_reg_t output_reg, | |
5798 | enum port port) | |
f0fec3f2 | 5799 | { |
fac5e23e | 5800 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0fec3f2 PZ |
5801 | struct intel_digital_port *intel_dig_port; |
5802 | struct intel_encoder *intel_encoder; | |
5803 | struct drm_encoder *encoder; | |
5804 | struct intel_connector *intel_connector; | |
5805 | ||
b14c5679 | 5806 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 | 5807 | if (!intel_dig_port) |
457c52d8 | 5808 | return false; |
f0fec3f2 | 5809 | |
08d9bc92 | 5810 | intel_connector = intel_connector_alloc(); |
11aee0f6 SM |
5811 | if (!intel_connector) |
5812 | goto err_connector_alloc; | |
f0fec3f2 PZ |
5813 | |
5814 | intel_encoder = &intel_dig_port->base; | |
5815 | encoder = &intel_encoder->base; | |
5816 | ||
893da0c9 | 5817 | if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
580d8ed5 | 5818 | DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port))) |
893da0c9 | 5819 | goto err_encoder_init; |
f0fec3f2 | 5820 | |
5bfe2ac0 | 5821 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 5822 | intel_encoder->disable = intel_disable_dp; |
00c09d70 | 5823 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 5824 | intel_encoder->get_config = intel_dp_get_config; |
07f9cd0b | 5825 | intel_encoder->suspend = intel_dp_encoder_suspend; |
920a14b2 | 5826 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 5827 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
e4a1d846 CML |
5828 | intel_encoder->pre_enable = chv_pre_enable_dp; |
5829 | intel_encoder->enable = vlv_enable_dp; | |
580d3811 | 5830 | intel_encoder->post_disable = chv_post_disable_dp; |
d6db995f | 5831 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
11a914c2 | 5832 | } else if (IS_VALLEYVIEW(dev_priv)) { |
ecff4f3b | 5833 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
5834 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
5835 | intel_encoder->enable = vlv_enable_dp; | |
49277c31 | 5836 | intel_encoder->post_disable = vlv_post_disable_dp; |
ab1f90f9 | 5837 | } else { |
ecff4f3b JN |
5838 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
5839 | intel_encoder->enable = g4x_enable_dp; | |
dd11bc10 | 5840 | if (INTEL_GEN(dev_priv) >= 5) |
08aff3fe | 5841 | intel_encoder->post_disable = ilk_post_disable_dp; |
ab1f90f9 | 5842 | } |
f0fec3f2 | 5843 | |
174edf1f | 5844 | intel_dig_port->port = port; |
f0fec3f2 | 5845 | intel_dig_port->dp.output_reg = output_reg; |
ccb1a831 | 5846 | intel_dig_port->max_lanes = 4; |
f0fec3f2 | 5847 | |
cca0502b | 5848 | intel_encoder->type = INTEL_OUTPUT_DP; |
920a14b2 | 5849 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 VS |
5850 | if (port == PORT_D) |
5851 | intel_encoder->crtc_mask = 1 << 2; | |
5852 | else | |
5853 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
5854 | } else { | |
5855 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
5856 | } | |
bc079e8b | 5857 | intel_encoder->cloneable = 0; |
03cdc1d4 | 5858 | intel_encoder->port = port; |
f0fec3f2 | 5859 | |
13cf5504 | 5860 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
5fcece80 | 5861 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
13cf5504 | 5862 | |
11aee0f6 SM |
5863 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
5864 | goto err_init_connector; | |
5865 | ||
457c52d8 | 5866 | return true; |
11aee0f6 SM |
5867 | |
5868 | err_init_connector: | |
5869 | drm_encoder_cleanup(encoder); | |
893da0c9 | 5870 | err_encoder_init: |
11aee0f6 SM |
5871 | kfree(intel_connector); |
5872 | err_connector_alloc: | |
5873 | kfree(intel_dig_port); | |
457c52d8 | 5874 | return false; |
f0fec3f2 | 5875 | } |
0e32b39c DA |
5876 | |
5877 | void intel_dp_mst_suspend(struct drm_device *dev) | |
5878 | { | |
fac5e23e | 5879 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
5880 | int i; |
5881 | ||
5882 | /* disable MST */ | |
5883 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 5884 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 VS |
5885 | |
5886 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) | |
0e32b39c DA |
5887 | continue; |
5888 | ||
5aa56969 VS |
5889 | if (intel_dig_port->dp.is_mst) |
5890 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); | |
0e32b39c DA |
5891 | } |
5892 | } | |
5893 | ||
5894 | void intel_dp_mst_resume(struct drm_device *dev) | |
5895 | { | |
fac5e23e | 5896 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
5897 | int i; |
5898 | ||
5899 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 5900 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 | 5901 | int ret; |
0e32b39c | 5902 | |
5aa56969 VS |
5903 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) |
5904 | continue; | |
0e32b39c | 5905 | |
5aa56969 VS |
5906 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
5907 | if (ret) | |
5908 | intel_dp_check_mst_status(&intel_dig_port->dp); | |
0e32b39c DA |
5909 | } |
5910 | } |