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0e32b39c DA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * 2014 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
27 | #include "i915_drv.h" | |
28 | #include "intel_drv.h" | |
c6f95f27 | 29 | #include <drm/drm_atomic_helper.h> |
0e32b39c DA |
30 | #include <drm/drm_crtc_helper.h> |
31 | #include <drm/drm_edid.h> | |
32 | ||
33 | static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, | |
0a478c27 ML |
34 | struct intel_crtc_state *pipe_config, |
35 | struct drm_connector_state *conn_state) | |
0e32b39c DA |
36 | { |
37 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
38 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
39 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
7f9e7754 LY |
40 | struct intel_connector *connector = |
41 | to_intel_connector(conn_state->connector); | |
e75f4771 | 42 | struct drm_atomic_state *state; |
1189e4f4 | 43 | int bpp; |
04a60f9f | 44 | int lane_count, slots; |
7c5f93b0 | 45 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
0e32b39c DA |
46 | int mst_pbn; |
47 | ||
0e32b39c | 48 | pipe_config->has_pch_encoder = false; |
0e32b39c | 49 | bpp = 24; |
611032bf MN |
50 | if (intel_dp->compliance.test_data.bpc) { |
51 | bpp = intel_dp->compliance.test_data.bpc * 3; | |
52 | DRM_DEBUG_KMS("Setting pipe bpp to %d\n", | |
53 | bpp); | |
54 | } | |
0e32b39c DA |
55 | /* |
56 | * for MST we always configure max link bw - the spec doesn't | |
57 | * seem to suggest we should do otherwise. | |
58 | */ | |
59 | lane_count = drm_dp_max_lane_count(intel_dp->dpcd); | |
ed4e9c1d | 60 | |
90a6b7b0 | 61 | pipe_config->lane_count = lane_count; |
0e32b39c | 62 | |
611032bf | 63 | pipe_config->pipe_bpp = bpp; |
04a60f9f | 64 | pipe_config->port_clock = intel_dp_max_link_rate(intel_dp); |
0e32b39c | 65 | |
e75f4771 ACO |
66 | state = pipe_config->base.state; |
67 | ||
7f9e7754 LY |
68 | if (drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, connector->port)) |
69 | pipe_config->has_audio = true; | |
aad941d5 | 70 | mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp); |
0e32b39c DA |
71 | |
72 | pipe_config->pbn = mst_pbn; | |
73 | slots = drm_dp_find_vcpi_slots(&intel_dp->mst_mgr, mst_pbn); | |
74 | ||
75 | intel_link_compute_m_n(bpp, lane_count, | |
76 | adjusted_mode->crtc_clock, | |
77 | pipe_config->port_clock, | |
78 | &pipe_config->dp_m_n); | |
79 | ||
80 | pipe_config->dp_m_n.tu = slots; | |
6fa2d197 | 81 | |
0e32b39c DA |
82 | return true; |
83 | ||
84 | } | |
85 | ||
fd6bbda9 ML |
86 | static void intel_mst_disable_dp(struct intel_encoder *encoder, |
87 | struct intel_crtc_state *old_crtc_state, | |
88 | struct drm_connector_state *old_conn_state) | |
0e32b39c DA |
89 | { |
90 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
91 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
92 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1e7bfa0b ML |
93 | struct intel_connector *connector = |
94 | to_intel_connector(old_conn_state->connector); | |
0e32b39c DA |
95 | int ret; |
96 | ||
19e0b4ca | 97 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); |
0e32b39c | 98 | |
1e7bfa0b | 99 | drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, connector->port); |
0e32b39c DA |
100 | |
101 | ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); | |
102 | if (ret) { | |
103 | DRM_ERROR("failed to update payload %d\n", ret); | |
104 | } | |
37255d8d | 105 | if (old_crtc_state->has_audio) |
7f9e7754 | 106 | intel_audio_codec_disable(encoder); |
0e32b39c DA |
107 | } |
108 | ||
fd6bbda9 ML |
109 | static void intel_mst_post_disable_dp(struct intel_encoder *encoder, |
110 | struct intel_crtc_state *old_crtc_state, | |
111 | struct drm_connector_state *old_conn_state) | |
0e32b39c DA |
112 | { |
113 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
114 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
115 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1e7bfa0b ML |
116 | struct intel_connector *connector = |
117 | to_intel_connector(old_conn_state->connector); | |
0e32b39c | 118 | |
19e0b4ca | 119 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); |
0e32b39c DA |
120 | |
121 | /* this can fail */ | |
122 | drm_dp_check_act_status(&intel_dp->mst_mgr); | |
123 | /* and this can also fail */ | |
124 | drm_dp_update_payload_part2(&intel_dp->mst_mgr); | |
125 | ||
1e7bfa0b | 126 | drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port); |
0e32b39c | 127 | |
19e0b4ca | 128 | intel_dp->active_mst_links--; |
0552f765 DA |
129 | |
130 | intel_mst->connector = NULL; | |
19e0b4ca | 131 | if (intel_dp->active_mst_links == 0) { |
fd6bbda9 ML |
132 | intel_dig_port->base.post_disable(&intel_dig_port->base, |
133 | NULL, NULL); | |
134 | ||
0e32b39c DA |
135 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
136 | } | |
137 | } | |
138 | ||
fd6bbda9 ML |
139 | static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, |
140 | struct intel_crtc_state *pipe_config, | |
141 | struct drm_connector_state *conn_state) | |
0e32b39c DA |
142 | { |
143 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
144 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
145 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1e7bfa0b | 146 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
0e32b39c | 147 | enum port port = intel_dig_port->port; |
1e7bfa0b ML |
148 | struct intel_connector *connector = |
149 | to_intel_connector(conn_state->connector); | |
0e32b39c DA |
150 | int ret; |
151 | uint32_t temp; | |
0e32b39c | 152 | int slots; |
0e32b39c | 153 | |
e85376cb ML |
154 | /* MST encoders are bound to a crtc, not to a connector, |
155 | * force the mapping here for get_hw_state. | |
156 | */ | |
1e7bfa0b ML |
157 | connector->encoder = encoder; |
158 | intel_mst->connector = connector; | |
e85376cb | 159 | |
19e0b4ca | 160 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); |
0552f765 | 161 | |
19e0b4ca | 162 | if (intel_dp->active_mst_links == 0) { |
c856052a ACO |
163 | intel_ddi_clk_select(&intel_dig_port->base, |
164 | pipe_config->shared_dpll); | |
0e32b39c | 165 | |
32bdc400 | 166 | intel_prepare_dp_ddi_buffers(&intel_dig_port->base); |
dfa10480 ACO |
167 | intel_dp_set_link_params(intel_dp, |
168 | pipe_config->port_clock, | |
169 | pipe_config->lane_count, | |
170 | true); | |
901c2daf | 171 | |
0e32b39c DA |
172 | intel_ddi_init_dp_buf_reg(&intel_dig_port->base); |
173 | ||
174 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
175 | ||
0e32b39c | 176 | intel_dp_start_link_train(intel_dp); |
0e32b39c DA |
177 | intel_dp_stop_link_train(intel_dp); |
178 | } | |
179 | ||
180 | ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, | |
1e7bfa0b ML |
181 | connector->port, |
182 | pipe_config->pbn, &slots); | |
0e32b39c DA |
183 | if (ret == false) { |
184 | DRM_ERROR("failed to allocate vcpi\n"); | |
185 | return; | |
186 | } | |
187 | ||
188 | ||
19e0b4ca | 189 | intel_dp->active_mst_links++; |
0e32b39c DA |
190 | temp = I915_READ(DP_TP_STATUS(port)); |
191 | I915_WRITE(DP_TP_STATUS(port), temp); | |
192 | ||
193 | ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); | |
194 | } | |
195 | ||
fd6bbda9 ML |
196 | static void intel_mst_enable_dp(struct intel_encoder *encoder, |
197 | struct intel_crtc_state *pipe_config, | |
198 | struct drm_connector_state *conn_state) | |
0e32b39c DA |
199 | { |
200 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
201 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
202 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1e7bfa0b | 203 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
0e32b39c DA |
204 | enum port port = intel_dig_port->port; |
205 | int ret; | |
206 | ||
19e0b4ca | 207 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); |
0e32b39c | 208 | |
3016a31f CW |
209 | if (intel_wait_for_register(dev_priv, |
210 | DP_TP_STATUS(port), | |
211 | DP_TP_STATUS_ACT_SENT, | |
212 | DP_TP_STATUS_ACT_SENT, | |
213 | 1)) | |
0e32b39c DA |
214 | DRM_ERROR("Timed out waiting for ACT sent\n"); |
215 | ||
216 | ret = drm_dp_check_act_status(&intel_dp->mst_mgr); | |
217 | ||
218 | ret = drm_dp_update_payload_part2(&intel_dp->mst_mgr); | |
37255d8d | 219 | if (pipe_config->has_audio) |
7f9e7754 | 220 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
0e32b39c DA |
221 | } |
222 | ||
223 | static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder, | |
224 | enum pipe *pipe) | |
225 | { | |
226 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
227 | *pipe = intel_mst->pipe; | |
0552f765 | 228 | if (intel_mst->connector) |
0e32b39c DA |
229 | return true; |
230 | return false; | |
231 | } | |
232 | ||
233 | static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, | |
5cec258b | 234 | struct intel_crtc_state *pipe_config) |
0e32b39c DA |
235 | { |
236 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
237 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
1e7bfa0b ML |
238 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
239 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
0cb09a97 | 240 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
0e32b39c DA |
241 | u32 temp, flags = 0; |
242 | ||
7f9e7754 LY |
243 | pipe_config->has_audio = |
244 | intel_ddi_is_audio_enabled(dev_priv, crtc); | |
245 | ||
0e32b39c DA |
246 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
247 | if (temp & TRANS_DDI_PHSYNC) | |
248 | flags |= DRM_MODE_FLAG_PHSYNC; | |
249 | else | |
250 | flags |= DRM_MODE_FLAG_NHSYNC; | |
251 | if (temp & TRANS_DDI_PVSYNC) | |
252 | flags |= DRM_MODE_FLAG_PVSYNC; | |
253 | else | |
254 | flags |= DRM_MODE_FLAG_NVSYNC; | |
255 | ||
256 | switch (temp & TRANS_DDI_BPC_MASK) { | |
257 | case TRANS_DDI_BPC_6: | |
258 | pipe_config->pipe_bpp = 18; | |
259 | break; | |
260 | case TRANS_DDI_BPC_8: | |
261 | pipe_config->pipe_bpp = 24; | |
262 | break; | |
263 | case TRANS_DDI_BPC_10: | |
264 | pipe_config->pipe_bpp = 30; | |
265 | break; | |
266 | case TRANS_DDI_BPC_12: | |
267 | pipe_config->pipe_bpp = 36; | |
268 | break; | |
269 | default: | |
270 | break; | |
271 | } | |
2d112de7 | 272 | pipe_config->base.adjusted_mode.flags |= flags; |
90a6b7b0 VS |
273 | |
274 | pipe_config->lane_count = | |
275 | ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; | |
276 | ||
0e32b39c DA |
277 | intel_dp_get_m_n(crtc, pipe_config); |
278 | ||
279 | intel_ddi_clock_get(&intel_dig_port->base, pipe_config); | |
280 | } | |
281 | ||
282 | static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) | |
283 | { | |
284 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
285 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
286 | struct edid *edid; | |
287 | int ret; | |
288 | ||
0552f765 DA |
289 | if (!intel_dp) { |
290 | return intel_connector_update_modes(connector, NULL); | |
291 | } | |
0e32b39c | 292 | |
0552f765 | 293 | edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port); |
0e32b39c DA |
294 | ret = intel_connector_update_modes(connector, edid); |
295 | kfree(edid); | |
296 | ||
297 | return ret; | |
298 | } | |
299 | ||
300 | static enum drm_connector_status | |
f7f3d48a | 301 | intel_dp_mst_detect(struct drm_connector *connector, bool force) |
0e32b39c DA |
302 | { |
303 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
304 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
305 | ||
0552f765 DA |
306 | if (!intel_dp) |
307 | return connector_status_disconnected; | |
c6a0aed4 | 308 | return drm_dp_mst_detect_port(connector, &intel_dp->mst_mgr, intel_connector->port); |
0e32b39c DA |
309 | } |
310 | ||
0e32b39c DA |
311 | static int |
312 | intel_dp_mst_set_property(struct drm_connector *connector, | |
313 | struct drm_property *property, | |
314 | uint64_t val) | |
315 | { | |
316 | return 0; | |
317 | } | |
318 | ||
319 | static void | |
320 | intel_dp_mst_connector_destroy(struct drm_connector *connector) | |
321 | { | |
322 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
323 | ||
324 | if (!IS_ERR_OR_NULL(intel_connector->edid)) | |
325 | kfree(intel_connector->edid); | |
326 | ||
327 | drm_connector_cleanup(connector); | |
328 | kfree(connector); | |
329 | } | |
330 | ||
331 | static const struct drm_connector_funcs intel_dp_mst_connector_funcs = { | |
4d688a2a | 332 | .dpms = drm_atomic_helper_connector_dpms, |
0e32b39c DA |
333 | .detect = intel_dp_mst_detect, |
334 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335 | .set_property = intel_dp_mst_set_property, | |
2545e4a6 | 336 | .atomic_get_property = intel_connector_atomic_get_property, |
1ebaa0b9 | 337 | .late_register = intel_connector_register, |
c191eca1 | 338 | .early_unregister = intel_connector_unregister, |
0e32b39c | 339 | .destroy = intel_dp_mst_connector_destroy, |
c6f95f27 | 340 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 341 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
0e32b39c DA |
342 | }; |
343 | ||
344 | static int intel_dp_mst_get_modes(struct drm_connector *connector) | |
345 | { | |
346 | return intel_dp_mst_get_ddc_modes(connector); | |
347 | } | |
348 | ||
349 | static enum drm_mode_status | |
350 | intel_dp_mst_mode_valid(struct drm_connector *connector, | |
351 | struct drm_display_mode *mode) | |
352 | { | |
22a2c8e0 DP |
353 | struct intel_connector *intel_connector = to_intel_connector(connector); |
354 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
832d5bfd | 355 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
22a2c8e0 DP |
356 | int bpp = 24; /* MST uses fixed bpp */ |
357 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
358 | ||
359 | max_link_clock = intel_dp_max_link_rate(intel_dp); | |
360 | max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); | |
361 | ||
362 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
363 | mode_rate = intel_dp_link_required(mode->clock, bpp); | |
832d5bfd | 364 | |
0e32b39c DA |
365 | /* TODO - validate mode against available PBN for link */ |
366 | if (mode->clock < 10000) | |
367 | return MODE_CLOCK_LOW; | |
368 | ||
369 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) | |
370 | return MODE_H_ILLEGAL; | |
371 | ||
22a2c8e0 | 372 | if (mode_rate > max_rate || mode->clock > max_dotclk) |
832d5bfd MK |
373 | return MODE_CLOCK_HIGH; |
374 | ||
0e32b39c DA |
375 | return MODE_OK; |
376 | } | |
377 | ||
459485ad DV |
378 | static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector, |
379 | struct drm_connector_state *state) | |
380 | { | |
381 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
382 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
383 | struct intel_crtc *crtc = to_intel_crtc(state->crtc); | |
384 | ||
0552f765 DA |
385 | if (!intel_dp) |
386 | return NULL; | |
459485ad DV |
387 | return &intel_dp->mst_encoders[crtc->pipe]->base.base; |
388 | } | |
389 | ||
0e32b39c DA |
390 | static struct drm_encoder *intel_mst_best_encoder(struct drm_connector *connector) |
391 | { | |
392 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
393 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
0552f765 DA |
394 | if (!intel_dp) |
395 | return NULL; | |
0e32b39c DA |
396 | return &intel_dp->mst_encoders[0]->base.base; |
397 | } | |
398 | ||
399 | static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = { | |
400 | .get_modes = intel_dp_mst_get_modes, | |
401 | .mode_valid = intel_dp_mst_mode_valid, | |
459485ad | 402 | .atomic_best_encoder = intel_mst_atomic_best_encoder, |
0e32b39c DA |
403 | .best_encoder = intel_mst_best_encoder, |
404 | }; | |
405 | ||
406 | static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder) | |
407 | { | |
408 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); | |
409 | ||
410 | drm_encoder_cleanup(encoder); | |
411 | kfree(intel_mst); | |
412 | } | |
413 | ||
414 | static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = { | |
415 | .destroy = intel_dp_mst_encoder_destroy, | |
416 | }; | |
417 | ||
418 | static bool intel_dp_mst_get_hw_state(struct intel_connector *connector) | |
419 | { | |
e85376cb | 420 | if (connector->encoder && connector->base.state->crtc) { |
0e32b39c DA |
421 | enum pipe pipe; |
422 | if (!connector->encoder->get_hw_state(connector->encoder, &pipe)) | |
423 | return false; | |
424 | return true; | |
425 | } | |
426 | return false; | |
427 | } | |
428 | ||
7296c849 CW |
429 | static void intel_connector_add_to_fbdev(struct intel_connector *connector) |
430 | { | |
0695726e | 431 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
7296c849 | 432 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
54632abe LW |
433 | |
434 | if (dev_priv->fbdev) | |
435 | drm_fb_helper_add_one_connector(&dev_priv->fbdev->helper, | |
436 | &connector->base); | |
7296c849 CW |
437 | #endif |
438 | } | |
439 | ||
440 | static void intel_connector_remove_from_fbdev(struct intel_connector *connector) | |
441 | { | |
0695726e | 442 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
7296c849 | 443 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
54632abe LW |
444 | |
445 | if (dev_priv->fbdev) | |
446 | drm_fb_helper_remove_one_connector(&dev_priv->fbdev->helper, | |
447 | &connector->base); | |
7296c849 CW |
448 | #endif |
449 | } | |
450 | ||
12e6cecd | 451 | static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *pathprop) |
0e32b39c DA |
452 | { |
453 | struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); | |
454 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
455 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
0e32b39c DA |
456 | struct intel_connector *intel_connector; |
457 | struct drm_connector *connector; | |
458 | int i; | |
459 | ||
9bdbd0b9 | 460 | intel_connector = intel_connector_alloc(); |
0e32b39c DA |
461 | if (!intel_connector) |
462 | return NULL; | |
463 | ||
464 | connector = &intel_connector->base; | |
465 | drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort); | |
466 | drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs); | |
467 | ||
0e32b39c DA |
468 | intel_connector->get_hw_state = intel_dp_mst_get_hw_state; |
469 | intel_connector->mst_port = intel_dp; | |
470 | intel_connector->port = port; | |
471 | ||
472 | for (i = PIPE_A; i <= PIPE_C; i++) { | |
473 | drm_mode_connector_attach_encoder(&intel_connector->base, | |
474 | &intel_dp->mst_encoders[i]->base.base); | |
475 | } | |
476 | intel_dp_add_properties(intel_dp, connector); | |
477 | ||
478 | drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); | |
6f134d7b DA |
479 | drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); |
480 | ||
0e32b39c | 481 | drm_mode_connector_set_path_property(connector, pathprop); |
d9515c5e DA |
482 | return connector; |
483 | } | |
484 | ||
485 | static void intel_dp_register_mst_connector(struct drm_connector *connector) | |
486 | { | |
487 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
488 | struct drm_device *dev = connector->dev; | |
7a418e34 | 489 | |
8bb4da1d | 490 | drm_modeset_lock_all(dev); |
7296c849 | 491 | intel_connector_add_to_fbdev(intel_connector); |
8bb4da1d | 492 | drm_modeset_unlock_all(dev); |
7a418e34 | 493 | |
0e32b39c | 494 | drm_connector_register(&intel_connector->base); |
0e32b39c DA |
495 | } |
496 | ||
497 | static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, | |
498 | struct drm_connector *connector) | |
499 | { | |
500 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
501 | struct drm_device *dev = connector->dev; | |
20fae983 | 502 | |
c191eca1 | 503 | drm_connector_unregister(connector); |
1f771755 | 504 | |
0e32b39c | 505 | /* need to nuke the connector */ |
8bb4da1d | 506 | drm_modeset_lock_all(dev); |
7296c849 | 507 | intel_connector_remove_from_fbdev(intel_connector); |
0552f765 | 508 | intel_connector->mst_port = NULL; |
8bb4da1d | 509 | drm_modeset_unlock_all(dev); |
0e32b39c | 510 | |
0552f765 | 511 | drm_connector_unreference(&intel_connector->base); |
0e32b39c DA |
512 | DRM_DEBUG_KMS("\n"); |
513 | } | |
514 | ||
515 | static void intel_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) | |
516 | { | |
517 | struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); | |
518 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
519 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
520 | ||
521 | drm_kms_helper_hotplug_event(dev); | |
522 | } | |
523 | ||
69a0f89c | 524 | static const struct drm_dp_mst_topology_cbs mst_cbs = { |
0e32b39c | 525 | .add_connector = intel_dp_add_mst_connector, |
d9515c5e | 526 | .register_connector = intel_dp_register_mst_connector, |
0e32b39c DA |
527 | .destroy_connector = intel_dp_destroy_mst_connector, |
528 | .hotplug = intel_dp_mst_hotplug, | |
529 | }; | |
530 | ||
531 | static struct intel_dp_mst_encoder * | |
532 | intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum pipe pipe) | |
533 | { | |
534 | struct intel_dp_mst_encoder *intel_mst; | |
535 | struct intel_encoder *intel_encoder; | |
536 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
537 | ||
538 | intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL); | |
539 | ||
540 | if (!intel_mst) | |
541 | return NULL; | |
542 | ||
543 | intel_mst->pipe = pipe; | |
544 | intel_encoder = &intel_mst->base; | |
545 | intel_mst->primary = intel_dig_port; | |
546 | ||
547 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs, | |
580d8ed5 | 548 | DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe)); |
0e32b39c DA |
549 | |
550 | intel_encoder->type = INTEL_OUTPUT_DP_MST; | |
79f255a0 | 551 | intel_encoder->power_domain = intel_dig_port->base.power_domain; |
03cdc1d4 | 552 | intel_encoder->port = intel_dig_port->port; |
0e32b39c DA |
553 | intel_encoder->crtc_mask = 0x7; |
554 | intel_encoder->cloneable = 0; | |
555 | ||
556 | intel_encoder->compute_config = intel_dp_mst_compute_config; | |
557 | intel_encoder->disable = intel_mst_disable_dp; | |
558 | intel_encoder->post_disable = intel_mst_post_disable_dp; | |
559 | intel_encoder->pre_enable = intel_mst_pre_enable_dp; | |
560 | intel_encoder->enable = intel_mst_enable_dp; | |
561 | intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state; | |
562 | intel_encoder->get_config = intel_dp_mst_enc_get_config; | |
563 | ||
564 | return intel_mst; | |
565 | ||
566 | } | |
567 | ||
568 | static bool | |
569 | intel_dp_create_fake_mst_encoders(struct intel_digital_port *intel_dig_port) | |
570 | { | |
571 | int i; | |
572 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
573 | ||
574 | for (i = PIPE_A; i <= PIPE_C; i++) | |
575 | intel_dp->mst_encoders[i] = intel_dp_create_fake_mst_encoder(intel_dig_port, i); | |
576 | return true; | |
577 | } | |
578 | ||
579 | int | |
580 | intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_base_id) | |
581 | { | |
582 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
583 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
584 | int ret; | |
585 | ||
586 | intel_dp->can_mst = true; | |
587 | intel_dp->mst_mgr.cbs = &mst_cbs; | |
588 | ||
589 | /* create encoders */ | |
590 | intel_dp_create_fake_mst_encoders(intel_dig_port); | |
7b0a89a6 DP |
591 | ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, dev, |
592 | &intel_dp->aux, 16, 3, conn_base_id); | |
0e32b39c DA |
593 | if (ret) { |
594 | intel_dp->can_mst = false; | |
595 | return ret; | |
596 | } | |
597 | return 0; | |
598 | } | |
599 | ||
600 | void | |
601 | intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port) | |
602 | { | |
603 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
604 | ||
605 | if (!intel_dp->can_mst) | |
606 | return; | |
607 | ||
608 | drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr); | |
609 | /* encoders will get killed by normal cleanup */ | |
610 | } |