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0e32b39c DA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * 2014 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
27 | #include "i915_drv.h" | |
28 | #include "intel_drv.h" | |
c6f95f27 | 29 | #include <drm/drm_atomic_helper.h> |
0e32b39c DA |
30 | #include <drm/drm_crtc_helper.h> |
31 | #include <drm/drm_edid.h> | |
32 | ||
33 | static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, | |
5cec258b | 34 | struct intel_crtc_state *pipe_config) |
0e32b39c | 35 | { |
6fa2d197 | 36 | struct drm_device *dev = encoder->base.dev; |
0e32b39c DA |
37 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); |
38 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
39 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
e75f4771 ACO |
40 | struct drm_atomic_state *state; |
41 | int bpp, i; | |
ed4e9c1d | 42 | int lane_count, slots, rate; |
2d112de7 | 43 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
da3ced29 ACO |
44 | struct drm_connector *drm_connector; |
45 | struct intel_connector *connector, *found = NULL; | |
46 | struct drm_connector_state *connector_state; | |
0e32b39c DA |
47 | int mst_pbn; |
48 | ||
49 | pipe_config->dp_encoder_is_mst = true; | |
50 | pipe_config->has_pch_encoder = false; | |
51 | pipe_config->has_dp_encoder = true; | |
52 | bpp = 24; | |
53 | /* | |
54 | * for MST we always configure max link bw - the spec doesn't | |
55 | * seem to suggest we should do otherwise. | |
56 | */ | |
57 | lane_count = drm_dp_max_lane_count(intel_dp->dpcd); | |
ed4e9c1d VS |
58 | |
59 | rate = intel_dp_max_link_rate(intel_dp); | |
60 | ||
94ca719e | 61 | if (intel_dp->num_sink_rates) { |
ed4e9c1d VS |
62 | intel_dp->link_bw = 0; |
63 | intel_dp->rate_select = intel_dp_rate_select(intel_dp, rate); | |
64 | } else { | |
65 | intel_dp->link_bw = drm_dp_link_rate_to_bw_code(rate); | |
66 | intel_dp->rate_select = 0; | |
67 | } | |
68 | ||
0e32b39c DA |
69 | intel_dp->lane_count = lane_count; |
70 | ||
71 | pipe_config->pipe_bpp = 24; | |
ed4e9c1d | 72 | pipe_config->port_clock = rate; |
0e32b39c | 73 | |
e75f4771 ACO |
74 | state = pipe_config->base.state; |
75 | ||
da3ced29 ACO |
76 | for_each_connector_in_state(state, drm_connector, connector_state, i) { |
77 | connector = to_intel_connector(drm_connector); | |
e75f4771 | 78 | |
da3ced29 ACO |
79 | if (connector_state->best_encoder == &encoder->base) { |
80 | found = connector; | |
0e32b39c DA |
81 | break; |
82 | } | |
83 | } | |
84 | ||
85 | if (!found) { | |
86 | DRM_ERROR("can't find connector\n"); | |
87 | return false; | |
88 | } | |
89 | ||
90 | mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp); | |
91 | ||
92 | pipe_config->pbn = mst_pbn; | |
93 | slots = drm_dp_find_vcpi_slots(&intel_dp->mst_mgr, mst_pbn); | |
94 | ||
95 | intel_link_compute_m_n(bpp, lane_count, | |
96 | adjusted_mode->crtc_clock, | |
97 | pipe_config->port_clock, | |
98 | &pipe_config->dp_m_n); | |
99 | ||
100 | pipe_config->dp_m_n.tu = slots; | |
6fa2d197 ACO |
101 | |
102 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
103 | hsw_dp_set_ddi_pll_sel(pipe_config); | |
104 | ||
0e32b39c DA |
105 | return true; |
106 | ||
107 | } | |
108 | ||
109 | static void intel_mst_disable_dp(struct intel_encoder *encoder) | |
110 | { | |
111 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
112 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
113 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
114 | int ret; | |
115 | ||
116 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); | |
117 | ||
118 | drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, intel_mst->port); | |
119 | ||
120 | ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); | |
121 | if (ret) { | |
122 | DRM_ERROR("failed to update payload %d\n", ret); | |
123 | } | |
124 | } | |
125 | ||
126 | static void intel_mst_post_disable_dp(struct intel_encoder *encoder) | |
127 | { | |
128 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
129 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
130 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
131 | ||
132 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); | |
133 | ||
134 | /* this can fail */ | |
135 | drm_dp_check_act_status(&intel_dp->mst_mgr); | |
136 | /* and this can also fail */ | |
137 | drm_dp_update_payload_part2(&intel_dp->mst_mgr); | |
138 | ||
139 | drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, intel_mst->port); | |
140 | ||
141 | intel_dp->active_mst_links--; | |
142 | intel_mst->port = NULL; | |
143 | if (intel_dp->active_mst_links == 0) { | |
144 | intel_dig_port->base.post_disable(&intel_dig_port->base); | |
145 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); | |
146 | } | |
147 | } | |
148 | ||
149 | static void intel_mst_pre_enable_dp(struct intel_encoder *encoder) | |
150 | { | |
151 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
152 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
153 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
154 | struct drm_device *dev = encoder->base.dev; | |
155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
156 | enum port port = intel_dig_port->port; | |
157 | int ret; | |
158 | uint32_t temp; | |
9b4fd8f2 | 159 | struct intel_connector *found = NULL, *connector; |
0e32b39c DA |
160 | int slots; |
161 | struct drm_crtc *crtc = encoder->base.crtc; | |
162 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
163 | ||
9b4fd8f2 ACO |
164 | for_each_intel_connector(dev, connector) { |
165 | if (connector->base.state->best_encoder == &encoder->base) { | |
166 | found = connector; | |
0e32b39c DA |
167 | break; |
168 | } | |
169 | } | |
170 | ||
171 | if (!found) { | |
172 | DRM_ERROR("can't find connector\n"); | |
173 | return; | |
174 | } | |
175 | ||
e85376cb ML |
176 | /* MST encoders are bound to a crtc, not to a connector, |
177 | * force the mapping here for get_hw_state. | |
178 | */ | |
179 | found->encoder = encoder; | |
180 | ||
0e32b39c DA |
181 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); |
182 | intel_mst->port = found->port; | |
183 | ||
184 | if (intel_dp->active_mst_links == 0) { | |
185 | enum port port = intel_ddi_get_encoder_port(encoder); | |
186 | ||
1ab23380 S |
187 | /* FIXME: add support for SKL */ |
188 | if (INTEL_INFO(dev)->gen < 9) | |
189 | I915_WRITE(PORT_CLK_SEL(port), | |
190 | intel_crtc->config->ddi_pll_sel); | |
0e32b39c DA |
191 | |
192 | intel_ddi_init_dp_buf_reg(&intel_dig_port->base); | |
193 | ||
194 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
195 | ||
196 | ||
197 | intel_dp_start_link_train(intel_dp); | |
198 | intel_dp_complete_link_train(intel_dp); | |
199 | intel_dp_stop_link_train(intel_dp); | |
200 | } | |
201 | ||
202 | ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, | |
6e3c9717 ACO |
203 | intel_mst->port, |
204 | intel_crtc->config->pbn, &slots); | |
0e32b39c DA |
205 | if (ret == false) { |
206 | DRM_ERROR("failed to allocate vcpi\n"); | |
207 | return; | |
208 | } | |
209 | ||
210 | ||
211 | intel_dp->active_mst_links++; | |
212 | temp = I915_READ(DP_TP_STATUS(port)); | |
213 | I915_WRITE(DP_TP_STATUS(port), temp); | |
214 | ||
215 | ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); | |
216 | } | |
217 | ||
218 | static void intel_mst_enable_dp(struct intel_encoder *encoder) | |
219 | { | |
220 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
221 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
222 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
223 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
225 | enum port port = intel_dig_port->port; | |
226 | int ret; | |
227 | ||
228 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); | |
229 | ||
230 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_ACT_SENT), | |
231 | 1)) | |
232 | DRM_ERROR("Timed out waiting for ACT sent\n"); | |
233 | ||
234 | ret = drm_dp_check_act_status(&intel_dp->mst_mgr); | |
235 | ||
236 | ret = drm_dp_update_payload_part2(&intel_dp->mst_mgr); | |
237 | } | |
238 | ||
239 | static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder, | |
240 | enum pipe *pipe) | |
241 | { | |
242 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
243 | *pipe = intel_mst->pipe; | |
244 | if (intel_mst->port) | |
245 | return true; | |
246 | return false; | |
247 | } | |
248 | ||
249 | static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, | |
5cec258b | 250 | struct intel_crtc_state *pipe_config) |
0e32b39c DA |
251 | { |
252 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
253 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
254 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
255 | struct drm_device *dev = encoder->base.dev; | |
256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0cb09a97 | 257 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
0e32b39c DA |
258 | u32 temp, flags = 0; |
259 | ||
260 | pipe_config->has_dp_encoder = true; | |
261 | ||
262 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
263 | if (temp & TRANS_DDI_PHSYNC) | |
264 | flags |= DRM_MODE_FLAG_PHSYNC; | |
265 | else | |
266 | flags |= DRM_MODE_FLAG_NHSYNC; | |
267 | if (temp & TRANS_DDI_PVSYNC) | |
268 | flags |= DRM_MODE_FLAG_PVSYNC; | |
269 | else | |
270 | flags |= DRM_MODE_FLAG_NVSYNC; | |
271 | ||
272 | switch (temp & TRANS_DDI_BPC_MASK) { | |
273 | case TRANS_DDI_BPC_6: | |
274 | pipe_config->pipe_bpp = 18; | |
275 | break; | |
276 | case TRANS_DDI_BPC_8: | |
277 | pipe_config->pipe_bpp = 24; | |
278 | break; | |
279 | case TRANS_DDI_BPC_10: | |
280 | pipe_config->pipe_bpp = 30; | |
281 | break; | |
282 | case TRANS_DDI_BPC_12: | |
283 | pipe_config->pipe_bpp = 36; | |
284 | break; | |
285 | default: | |
286 | break; | |
287 | } | |
2d112de7 | 288 | pipe_config->base.adjusted_mode.flags |= flags; |
0e32b39c DA |
289 | intel_dp_get_m_n(crtc, pipe_config); |
290 | ||
291 | intel_ddi_clock_get(&intel_dig_port->base, pipe_config); | |
292 | } | |
293 | ||
294 | static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) | |
295 | { | |
296 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
297 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
298 | struct edid *edid; | |
299 | int ret; | |
300 | ||
301 | edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port); | |
302 | if (!edid) | |
303 | return 0; | |
304 | ||
305 | ret = intel_connector_update_modes(connector, edid); | |
306 | kfree(edid); | |
307 | ||
308 | return ret; | |
309 | } | |
310 | ||
311 | static enum drm_connector_status | |
f7f3d48a | 312 | intel_dp_mst_detect(struct drm_connector *connector, bool force) |
0e32b39c DA |
313 | { |
314 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
315 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
316 | ||
c6a0aed4 | 317 | return drm_dp_mst_detect_port(connector, &intel_dp->mst_mgr, intel_connector->port); |
0e32b39c DA |
318 | } |
319 | ||
0e32b39c DA |
320 | static int |
321 | intel_dp_mst_set_property(struct drm_connector *connector, | |
322 | struct drm_property *property, | |
323 | uint64_t val) | |
324 | { | |
325 | return 0; | |
326 | } | |
327 | ||
328 | static void | |
329 | intel_dp_mst_connector_destroy(struct drm_connector *connector) | |
330 | { | |
331 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
332 | ||
333 | if (!IS_ERR_OR_NULL(intel_connector->edid)) | |
334 | kfree(intel_connector->edid); | |
335 | ||
336 | drm_connector_cleanup(connector); | |
337 | kfree(connector); | |
338 | } | |
339 | ||
340 | static const struct drm_connector_funcs intel_dp_mst_connector_funcs = { | |
4d688a2a | 341 | .dpms = drm_atomic_helper_connector_dpms, |
0e32b39c DA |
342 | .detect = intel_dp_mst_detect, |
343 | .fill_modes = drm_helper_probe_single_connector_modes, | |
344 | .set_property = intel_dp_mst_set_property, | |
2545e4a6 | 345 | .atomic_get_property = intel_connector_atomic_get_property, |
0e32b39c | 346 | .destroy = intel_dp_mst_connector_destroy, |
c6f95f27 | 347 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 348 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
0e32b39c DA |
349 | }; |
350 | ||
351 | static int intel_dp_mst_get_modes(struct drm_connector *connector) | |
352 | { | |
353 | return intel_dp_mst_get_ddc_modes(connector); | |
354 | } | |
355 | ||
356 | static enum drm_mode_status | |
357 | intel_dp_mst_mode_valid(struct drm_connector *connector, | |
358 | struct drm_display_mode *mode) | |
359 | { | |
360 | /* TODO - validate mode against available PBN for link */ | |
361 | if (mode->clock < 10000) | |
362 | return MODE_CLOCK_LOW; | |
363 | ||
364 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) | |
365 | return MODE_H_ILLEGAL; | |
366 | ||
367 | return MODE_OK; | |
368 | } | |
369 | ||
459485ad DV |
370 | static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector, |
371 | struct drm_connector_state *state) | |
372 | { | |
373 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
374 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
375 | struct intel_crtc *crtc = to_intel_crtc(state->crtc); | |
376 | ||
377 | return &intel_dp->mst_encoders[crtc->pipe]->base.base; | |
378 | } | |
379 | ||
0e32b39c DA |
380 | static struct drm_encoder *intel_mst_best_encoder(struct drm_connector *connector) |
381 | { | |
382 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
383 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
384 | return &intel_dp->mst_encoders[0]->base.base; | |
385 | } | |
386 | ||
387 | static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = { | |
388 | .get_modes = intel_dp_mst_get_modes, | |
389 | .mode_valid = intel_dp_mst_mode_valid, | |
459485ad | 390 | .atomic_best_encoder = intel_mst_atomic_best_encoder, |
0e32b39c DA |
391 | .best_encoder = intel_mst_best_encoder, |
392 | }; | |
393 | ||
394 | static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder) | |
395 | { | |
396 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); | |
397 | ||
398 | drm_encoder_cleanup(encoder); | |
399 | kfree(intel_mst); | |
400 | } | |
401 | ||
402 | static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = { | |
403 | .destroy = intel_dp_mst_encoder_destroy, | |
404 | }; | |
405 | ||
406 | static bool intel_dp_mst_get_hw_state(struct intel_connector *connector) | |
407 | { | |
e85376cb | 408 | if (connector->encoder && connector->base.state->crtc) { |
0e32b39c DA |
409 | enum pipe pipe; |
410 | if (!connector->encoder->get_hw_state(connector->encoder, &pipe)) | |
411 | return false; | |
412 | return true; | |
413 | } | |
414 | return false; | |
415 | } | |
416 | ||
7296c849 CW |
417 | static void intel_connector_add_to_fbdev(struct intel_connector *connector) |
418 | { | |
0695726e | 419 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
7296c849 CW |
420 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
421 | drm_fb_helper_add_one_connector(&dev_priv->fbdev->helper, &connector->base); | |
422 | #endif | |
423 | } | |
424 | ||
425 | static void intel_connector_remove_from_fbdev(struct intel_connector *connector) | |
426 | { | |
0695726e | 427 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
7296c849 CW |
428 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
429 | drm_fb_helper_remove_one_connector(&dev_priv->fbdev->helper, &connector->base); | |
430 | #endif | |
431 | } | |
432 | ||
12e6cecd | 433 | static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *pathprop) |
0e32b39c DA |
434 | { |
435 | struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); | |
436 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
437 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
0e32b39c DA |
438 | struct intel_connector *intel_connector; |
439 | struct drm_connector *connector; | |
440 | int i; | |
441 | ||
9bdbd0b9 | 442 | intel_connector = intel_connector_alloc(); |
0e32b39c DA |
443 | if (!intel_connector) |
444 | return NULL; | |
445 | ||
446 | connector = &intel_connector->base; | |
447 | drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort); | |
448 | drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs); | |
449 | ||
450 | intel_connector->unregister = intel_connector_unregister; | |
451 | intel_connector->get_hw_state = intel_dp_mst_get_hw_state; | |
452 | intel_connector->mst_port = intel_dp; | |
453 | intel_connector->port = port; | |
454 | ||
455 | for (i = PIPE_A; i <= PIPE_C; i++) { | |
456 | drm_mode_connector_attach_encoder(&intel_connector->base, | |
457 | &intel_dp->mst_encoders[i]->base.base); | |
458 | } | |
459 | intel_dp_add_properties(intel_dp, connector); | |
460 | ||
461 | drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); | |
6f134d7b DA |
462 | drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); |
463 | ||
0e32b39c | 464 | drm_mode_connector_set_path_property(connector, pathprop); |
d9515c5e DA |
465 | return connector; |
466 | } | |
467 | ||
468 | static void intel_dp_register_mst_connector(struct drm_connector *connector) | |
469 | { | |
470 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
471 | struct drm_device *dev = connector->dev; | |
8bb4da1d | 472 | drm_modeset_lock_all(dev); |
7296c849 | 473 | intel_connector_add_to_fbdev(intel_connector); |
8bb4da1d | 474 | drm_modeset_unlock_all(dev); |
0e32b39c | 475 | drm_connector_register(&intel_connector->base); |
0e32b39c DA |
476 | } |
477 | ||
478 | static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, | |
479 | struct drm_connector *connector) | |
480 | { | |
481 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
482 | struct drm_device *dev = connector->dev; | |
20fae983 | 483 | |
0e32b39c | 484 | /* need to nuke the connector */ |
8bb4da1d | 485 | drm_modeset_lock_all(dev); |
20fae983 ML |
486 | if (connector->state->crtc) { |
487 | struct drm_mode_set set; | |
488 | int ret; | |
489 | ||
490 | memset(&set, 0, sizeof(set)); | |
491 | set.crtc = connector->state->crtc, | |
492 | ||
493 | ret = drm_atomic_helper_set_config(&set); | |
494 | ||
495 | WARN(ret, "Disabling mst crtc failed with %i\n", ret); | |
496 | } | |
8bb4da1d | 497 | drm_modeset_unlock_all(dev); |
0e32b39c DA |
498 | |
499 | intel_connector->unregister(intel_connector); | |
500 | ||
8bb4da1d | 501 | drm_modeset_lock_all(dev); |
7296c849 | 502 | intel_connector_remove_from_fbdev(intel_connector); |
0e32b39c | 503 | drm_connector_cleanup(connector); |
8bb4da1d | 504 | drm_modeset_unlock_all(dev); |
0e32b39c | 505 | |
0e32b39c DA |
506 | kfree(intel_connector); |
507 | DRM_DEBUG_KMS("\n"); | |
508 | } | |
509 | ||
510 | static void intel_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) | |
511 | { | |
512 | struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); | |
513 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
514 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
515 | ||
516 | drm_kms_helper_hotplug_event(dev); | |
517 | } | |
518 | ||
519 | static struct drm_dp_mst_topology_cbs mst_cbs = { | |
520 | .add_connector = intel_dp_add_mst_connector, | |
d9515c5e | 521 | .register_connector = intel_dp_register_mst_connector, |
0e32b39c DA |
522 | .destroy_connector = intel_dp_destroy_mst_connector, |
523 | .hotplug = intel_dp_mst_hotplug, | |
524 | }; | |
525 | ||
526 | static struct intel_dp_mst_encoder * | |
527 | intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum pipe pipe) | |
528 | { | |
529 | struct intel_dp_mst_encoder *intel_mst; | |
530 | struct intel_encoder *intel_encoder; | |
531 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
532 | ||
533 | intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL); | |
534 | ||
535 | if (!intel_mst) | |
536 | return NULL; | |
537 | ||
538 | intel_mst->pipe = pipe; | |
539 | intel_encoder = &intel_mst->base; | |
540 | intel_mst->primary = intel_dig_port; | |
541 | ||
542 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs, | |
543 | DRM_MODE_ENCODER_DPMST); | |
544 | ||
545 | intel_encoder->type = INTEL_OUTPUT_DP_MST; | |
546 | intel_encoder->crtc_mask = 0x7; | |
547 | intel_encoder->cloneable = 0; | |
548 | ||
549 | intel_encoder->compute_config = intel_dp_mst_compute_config; | |
550 | intel_encoder->disable = intel_mst_disable_dp; | |
551 | intel_encoder->post_disable = intel_mst_post_disable_dp; | |
552 | intel_encoder->pre_enable = intel_mst_pre_enable_dp; | |
553 | intel_encoder->enable = intel_mst_enable_dp; | |
554 | intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state; | |
555 | intel_encoder->get_config = intel_dp_mst_enc_get_config; | |
556 | ||
557 | return intel_mst; | |
558 | ||
559 | } | |
560 | ||
561 | static bool | |
562 | intel_dp_create_fake_mst_encoders(struct intel_digital_port *intel_dig_port) | |
563 | { | |
564 | int i; | |
565 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
566 | ||
567 | for (i = PIPE_A; i <= PIPE_C; i++) | |
568 | intel_dp->mst_encoders[i] = intel_dp_create_fake_mst_encoder(intel_dig_port, i); | |
569 | return true; | |
570 | } | |
571 | ||
572 | int | |
573 | intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_base_id) | |
574 | { | |
575 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
576 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
577 | int ret; | |
578 | ||
579 | intel_dp->can_mst = true; | |
580 | intel_dp->mst_mgr.cbs = &mst_cbs; | |
581 | ||
582 | /* create encoders */ | |
583 | intel_dp_create_fake_mst_encoders(intel_dig_port); | |
584 | ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, dev->dev, &intel_dp->aux, 16, 3, conn_base_id); | |
585 | if (ret) { | |
586 | intel_dp->can_mst = false; | |
587 | return ret; | |
588 | } | |
589 | return 0; | |
590 | } | |
591 | ||
592 | void | |
593 | intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port) | |
594 | { | |
595 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
596 | ||
597 | if (!intel_dp->can_mst) | |
598 | return; | |
599 | ||
600 | drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr); | |
601 | /* encoders will get killed by normal cleanup */ | |
602 | } |