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0e32b39c DA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * 2014 Red Hat Inc. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
27 | #include "i915_drv.h" | |
28 | #include "intel_drv.h" | |
c6f95f27 | 29 | #include <drm/drm_atomic_helper.h> |
0e32b39c DA |
30 | #include <drm/drm_crtc_helper.h> |
31 | #include <drm/drm_edid.h> | |
32 | ||
33 | static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, | |
0a478c27 ML |
34 | struct intel_crtc_state *pipe_config, |
35 | struct drm_connector_state *conn_state) | |
0e32b39c DA |
36 | { |
37 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
38 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
39 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
7f9e7754 LY |
40 | struct intel_connector *connector = |
41 | to_intel_connector(conn_state->connector); | |
f424f55e | 42 | struct drm_atomic_state *state = pipe_config->base.state; |
1189e4f4 | 43 | int bpp; |
04a60f9f | 44 | int lane_count, slots; |
7c5f93b0 | 45 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
0e32b39c | 46 | int mst_pbn; |
b31e85ed JN |
47 | bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc, |
48 | DP_DPCD_QUIRK_LIMITED_M_N); | |
0e32b39c | 49 | |
0e32b39c | 50 | pipe_config->has_pch_encoder = false; |
0e32b39c | 51 | bpp = 24; |
611032bf MN |
52 | if (intel_dp->compliance.test_data.bpc) { |
53 | bpp = intel_dp->compliance.test_data.bpc * 3; | |
54 | DRM_DEBUG_KMS("Setting pipe bpp to %d\n", | |
55 | bpp); | |
56 | } | |
0e32b39c DA |
57 | /* |
58 | * for MST we always configure max link bw - the spec doesn't | |
59 | * seem to suggest we should do otherwise. | |
60 | */ | |
3d65a735 | 61 | lane_count = intel_dp_max_lane_count(intel_dp); |
ed4e9c1d | 62 | |
90a6b7b0 | 63 | pipe_config->lane_count = lane_count; |
0e32b39c | 64 | |
611032bf | 65 | pipe_config->pipe_bpp = bpp; |
0e32b39c | 66 | |
f424f55e | 67 | pipe_config->port_clock = intel_dp_max_link_rate(intel_dp); |
e75f4771 | 68 | |
7f9e7754 LY |
69 | if (drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, connector->port)) |
70 | pipe_config->has_audio = true; | |
0e32b39c | 71 | |
f424f55e | 72 | mst_pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, bpp); |
0e32b39c | 73 | pipe_config->pbn = mst_pbn; |
f424f55e PD |
74 | |
75 | slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, | |
76 | connector->port, mst_pbn); | |
77 | if (slots < 0) { | |
78 | DRM_DEBUG_KMS("failed finding vcpi slots:%d\n", slots); | |
79 | return false; | |
80 | } | |
0e32b39c DA |
81 | |
82 | intel_link_compute_m_n(bpp, lane_count, | |
83 | adjusted_mode->crtc_clock, | |
84 | pipe_config->port_clock, | |
b31e85ed JN |
85 | &pipe_config->dp_m_n, |
86 | reduce_m_n); | |
0e32b39c DA |
87 | |
88 | pipe_config->dp_m_n.tu = slots; | |
6fa2d197 | 89 | |
0e32b39c | 90 | return true; |
f424f55e | 91 | } |
0e32b39c | 92 | |
f424f55e PD |
93 | static int intel_dp_mst_atomic_check(struct drm_connector *connector, |
94 | struct drm_connector_state *new_conn_state) | |
95 | { | |
96 | struct drm_atomic_state *state = new_conn_state->state; | |
97 | struct drm_connector_state *old_conn_state; | |
98 | struct drm_crtc *old_crtc; | |
99 | struct drm_crtc_state *crtc_state; | |
100 | int slots, ret = 0; | |
101 | ||
102 | old_conn_state = drm_atomic_get_old_connector_state(state, connector); | |
103 | old_crtc = old_conn_state->crtc; | |
104 | if (!old_crtc) | |
105 | return ret; | |
106 | ||
107 | crtc_state = drm_atomic_get_new_crtc_state(state, old_crtc); | |
108 | slots = to_intel_crtc_state(crtc_state)->dp_m_n.tu; | |
109 | if (drm_atomic_crtc_needs_modeset(crtc_state) && slots > 0) { | |
110 | struct drm_dp_mst_topology_mgr *mgr; | |
111 | struct drm_encoder *old_encoder; | |
112 | ||
113 | old_encoder = old_conn_state->best_encoder; | |
114 | mgr = &enc_to_mst(old_encoder)->primary->dp.mst_mgr; | |
115 | ||
116 | ret = drm_dp_atomic_release_vcpi_slots(state, mgr, slots); | |
117 | if (ret) | |
118 | DRM_DEBUG_KMS("failed releasing %d vcpi slots:%d\n", slots, ret); | |
119 | else | |
120 | to_intel_crtc_state(crtc_state)->dp_m_n.tu = 0; | |
121 | } | |
122 | return ret; | |
0e32b39c DA |
123 | } |
124 | ||
fd6bbda9 ML |
125 | static void intel_mst_disable_dp(struct intel_encoder *encoder, |
126 | struct intel_crtc_state *old_crtc_state, | |
127 | struct drm_connector_state *old_conn_state) | |
0e32b39c DA |
128 | { |
129 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
130 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
131 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1e7bfa0b ML |
132 | struct intel_connector *connector = |
133 | to_intel_connector(old_conn_state->connector); | |
0e32b39c DA |
134 | int ret; |
135 | ||
19e0b4ca | 136 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); |
0e32b39c | 137 | |
1e7bfa0b | 138 | drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, connector->port); |
0e32b39c DA |
139 | |
140 | ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); | |
141 | if (ret) { | |
142 | DRM_ERROR("failed to update payload %d\n", ret); | |
143 | } | |
37255d8d | 144 | if (old_crtc_state->has_audio) |
7f9e7754 | 145 | intel_audio_codec_disable(encoder); |
0e32b39c DA |
146 | } |
147 | ||
fd6bbda9 ML |
148 | static void intel_mst_post_disable_dp(struct intel_encoder *encoder, |
149 | struct intel_crtc_state *old_crtc_state, | |
150 | struct drm_connector_state *old_conn_state) | |
0e32b39c DA |
151 | { |
152 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
153 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
154 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1e7bfa0b ML |
155 | struct intel_connector *connector = |
156 | to_intel_connector(old_conn_state->connector); | |
0e32b39c | 157 | |
19e0b4ca | 158 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); |
0e32b39c DA |
159 | |
160 | /* this can fail */ | |
161 | drm_dp_check_act_status(&intel_dp->mst_mgr); | |
162 | /* and this can also fail */ | |
163 | drm_dp_update_payload_part2(&intel_dp->mst_mgr); | |
164 | ||
1e7bfa0b | 165 | drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port); |
0e32b39c | 166 | |
19e0b4ca | 167 | intel_dp->active_mst_links--; |
0552f765 DA |
168 | |
169 | intel_mst->connector = NULL; | |
19e0b4ca | 170 | if (intel_dp->active_mst_links == 0) { |
fd6bbda9 ML |
171 | intel_dig_port->base.post_disable(&intel_dig_port->base, |
172 | NULL, NULL); | |
173 | ||
0e32b39c DA |
174 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
175 | } | |
176 | } | |
177 | ||
fd6bbda9 ML |
178 | static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, |
179 | struct intel_crtc_state *pipe_config, | |
180 | struct drm_connector_state *conn_state) | |
0e32b39c DA |
181 | { |
182 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
183 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
184 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1e7bfa0b | 185 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
0e32b39c | 186 | enum port port = intel_dig_port->port; |
1e7bfa0b ML |
187 | struct intel_connector *connector = |
188 | to_intel_connector(conn_state->connector); | |
0e32b39c DA |
189 | int ret; |
190 | uint32_t temp; | |
0e32b39c | 191 | |
e85376cb ML |
192 | /* MST encoders are bound to a crtc, not to a connector, |
193 | * force the mapping here for get_hw_state. | |
194 | */ | |
1e7bfa0b ML |
195 | connector->encoder = encoder; |
196 | intel_mst->connector = connector; | |
e85376cb | 197 | |
19e0b4ca | 198 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); |
0552f765 | 199 | |
e081c846 ACO |
200 | if (intel_dp->active_mst_links == 0) |
201 | intel_dig_port->base.pre_enable(&intel_dig_port->base, | |
202 | pipe_config, NULL); | |
0e32b39c DA |
203 | |
204 | ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, | |
1e7bfa0b | 205 | connector->port, |
1e797f55 PD |
206 | pipe_config->pbn, |
207 | pipe_config->dp_m_n.tu); | |
0e32b39c DA |
208 | if (ret == false) { |
209 | DRM_ERROR("failed to allocate vcpi\n"); | |
210 | return; | |
211 | } | |
212 | ||
213 | ||
19e0b4ca | 214 | intel_dp->active_mst_links++; |
0e32b39c DA |
215 | temp = I915_READ(DP_TP_STATUS(port)); |
216 | I915_WRITE(DP_TP_STATUS(port), temp); | |
217 | ||
218 | ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); | |
219 | } | |
220 | ||
fd6bbda9 ML |
221 | static void intel_mst_enable_dp(struct intel_encoder *encoder, |
222 | struct intel_crtc_state *pipe_config, | |
223 | struct drm_connector_state *conn_state) | |
0e32b39c DA |
224 | { |
225 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
226 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
227 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1e7bfa0b | 228 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
0e32b39c DA |
229 | enum port port = intel_dig_port->port; |
230 | int ret; | |
231 | ||
19e0b4ca | 232 | DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); |
0e32b39c | 233 | |
3016a31f CW |
234 | if (intel_wait_for_register(dev_priv, |
235 | DP_TP_STATUS(port), | |
236 | DP_TP_STATUS_ACT_SENT, | |
237 | DP_TP_STATUS_ACT_SENT, | |
238 | 1)) | |
0e32b39c DA |
239 | DRM_ERROR("Timed out waiting for ACT sent\n"); |
240 | ||
241 | ret = drm_dp_check_act_status(&intel_dp->mst_mgr); | |
242 | ||
243 | ret = drm_dp_update_payload_part2(&intel_dp->mst_mgr); | |
37255d8d | 244 | if (pipe_config->has_audio) |
7f9e7754 | 245 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
0e32b39c DA |
246 | } |
247 | ||
248 | static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder, | |
249 | enum pipe *pipe) | |
250 | { | |
251 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
252 | *pipe = intel_mst->pipe; | |
0552f765 | 253 | if (intel_mst->connector) |
0e32b39c DA |
254 | return true; |
255 | return false; | |
256 | } | |
257 | ||
258 | static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, | |
5cec258b | 259 | struct intel_crtc_state *pipe_config) |
0e32b39c DA |
260 | { |
261 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); | |
262 | struct intel_digital_port *intel_dig_port = intel_mst->primary; | |
1e7bfa0b ML |
263 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
264 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
0cb09a97 | 265 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
0e32b39c DA |
266 | u32 temp, flags = 0; |
267 | ||
7f9e7754 LY |
268 | pipe_config->has_audio = |
269 | intel_ddi_is_audio_enabled(dev_priv, crtc); | |
270 | ||
0e32b39c DA |
271 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
272 | if (temp & TRANS_DDI_PHSYNC) | |
273 | flags |= DRM_MODE_FLAG_PHSYNC; | |
274 | else | |
275 | flags |= DRM_MODE_FLAG_NHSYNC; | |
276 | if (temp & TRANS_DDI_PVSYNC) | |
277 | flags |= DRM_MODE_FLAG_PVSYNC; | |
278 | else | |
279 | flags |= DRM_MODE_FLAG_NVSYNC; | |
280 | ||
281 | switch (temp & TRANS_DDI_BPC_MASK) { | |
282 | case TRANS_DDI_BPC_6: | |
283 | pipe_config->pipe_bpp = 18; | |
284 | break; | |
285 | case TRANS_DDI_BPC_8: | |
286 | pipe_config->pipe_bpp = 24; | |
287 | break; | |
288 | case TRANS_DDI_BPC_10: | |
289 | pipe_config->pipe_bpp = 30; | |
290 | break; | |
291 | case TRANS_DDI_BPC_12: | |
292 | pipe_config->pipe_bpp = 36; | |
293 | break; | |
294 | default: | |
295 | break; | |
296 | } | |
2d112de7 | 297 | pipe_config->base.adjusted_mode.flags |= flags; |
90a6b7b0 VS |
298 | |
299 | pipe_config->lane_count = | |
300 | ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1; | |
301 | ||
0e32b39c DA |
302 | intel_dp_get_m_n(crtc, pipe_config); |
303 | ||
304 | intel_ddi_clock_get(&intel_dig_port->base, pipe_config); | |
305 | } | |
306 | ||
307 | static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) | |
308 | { | |
309 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
310 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
311 | struct edid *edid; | |
312 | int ret; | |
313 | ||
0552f765 DA |
314 | if (!intel_dp) { |
315 | return intel_connector_update_modes(connector, NULL); | |
316 | } | |
0e32b39c | 317 | |
0552f765 | 318 | edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port); |
0e32b39c DA |
319 | ret = intel_connector_update_modes(connector, edid); |
320 | kfree(edid); | |
321 | ||
322 | return ret; | |
323 | } | |
324 | ||
325 | static enum drm_connector_status | |
f7f3d48a | 326 | intel_dp_mst_detect(struct drm_connector *connector, bool force) |
0e32b39c DA |
327 | { |
328 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
329 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
330 | ||
0552f765 DA |
331 | if (!intel_dp) |
332 | return connector_status_disconnected; | |
c6a0aed4 | 333 | return drm_dp_mst_detect_port(connector, &intel_dp->mst_mgr, intel_connector->port); |
0e32b39c DA |
334 | } |
335 | ||
0e32b39c DA |
336 | static void |
337 | intel_dp_mst_connector_destroy(struct drm_connector *connector) | |
338 | { | |
339 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
340 | ||
341 | if (!IS_ERR_OR_NULL(intel_connector->edid)) | |
342 | kfree(intel_connector->edid); | |
343 | ||
344 | drm_connector_cleanup(connector); | |
345 | kfree(connector); | |
346 | } | |
347 | ||
348 | static const struct drm_connector_funcs intel_dp_mst_connector_funcs = { | |
4d688a2a | 349 | .dpms = drm_atomic_helper_connector_dpms, |
0e32b39c DA |
350 | .detect = intel_dp_mst_detect, |
351 | .fill_modes = drm_helper_probe_single_connector_modes, | |
2e222eda | 352 | .set_property = drm_atomic_helper_connector_set_property, |
1ebaa0b9 | 353 | .late_register = intel_connector_register, |
c191eca1 | 354 | .early_unregister = intel_connector_unregister, |
0e32b39c | 355 | .destroy = intel_dp_mst_connector_destroy, |
c6f95f27 | 356 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 357 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
0e32b39c DA |
358 | }; |
359 | ||
360 | static int intel_dp_mst_get_modes(struct drm_connector *connector) | |
361 | { | |
362 | return intel_dp_mst_get_ddc_modes(connector); | |
363 | } | |
364 | ||
365 | static enum drm_mode_status | |
366 | intel_dp_mst_mode_valid(struct drm_connector *connector, | |
367 | struct drm_display_mode *mode) | |
368 | { | |
22a2c8e0 DP |
369 | struct intel_connector *intel_connector = to_intel_connector(connector); |
370 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
832d5bfd | 371 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
22a2c8e0 DP |
372 | int bpp = 24; /* MST uses fixed bpp */ |
373 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
374 | ||
375 | max_link_clock = intel_dp_max_link_rate(intel_dp); | |
3d65a735 | 376 | max_lanes = intel_dp_max_lane_count(intel_dp); |
22a2c8e0 DP |
377 | |
378 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
379 | mode_rate = intel_dp_link_required(mode->clock, bpp); | |
832d5bfd | 380 | |
0e32b39c DA |
381 | /* TODO - validate mode against available PBN for link */ |
382 | if (mode->clock < 10000) | |
383 | return MODE_CLOCK_LOW; | |
384 | ||
385 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) | |
386 | return MODE_H_ILLEGAL; | |
387 | ||
22a2c8e0 | 388 | if (mode_rate > max_rate || mode->clock > max_dotclk) |
832d5bfd MK |
389 | return MODE_CLOCK_HIGH; |
390 | ||
0e32b39c DA |
391 | return MODE_OK; |
392 | } | |
393 | ||
459485ad DV |
394 | static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector, |
395 | struct drm_connector_state *state) | |
396 | { | |
397 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
398 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
399 | struct intel_crtc *crtc = to_intel_crtc(state->crtc); | |
400 | ||
0552f765 DA |
401 | if (!intel_dp) |
402 | return NULL; | |
459485ad DV |
403 | return &intel_dp->mst_encoders[crtc->pipe]->base.base; |
404 | } | |
405 | ||
0e32b39c DA |
406 | static struct drm_encoder *intel_mst_best_encoder(struct drm_connector *connector) |
407 | { | |
408 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
409 | struct intel_dp *intel_dp = intel_connector->mst_port; | |
0552f765 DA |
410 | if (!intel_dp) |
411 | return NULL; | |
0e32b39c DA |
412 | return &intel_dp->mst_encoders[0]->base.base; |
413 | } | |
414 | ||
415 | static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = { | |
416 | .get_modes = intel_dp_mst_get_modes, | |
417 | .mode_valid = intel_dp_mst_mode_valid, | |
459485ad | 418 | .atomic_best_encoder = intel_mst_atomic_best_encoder, |
0e32b39c | 419 | .best_encoder = intel_mst_best_encoder, |
f424f55e | 420 | .atomic_check = intel_dp_mst_atomic_check, |
0e32b39c DA |
421 | }; |
422 | ||
423 | static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder) | |
424 | { | |
425 | struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); | |
426 | ||
427 | drm_encoder_cleanup(encoder); | |
428 | kfree(intel_mst); | |
429 | } | |
430 | ||
431 | static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = { | |
432 | .destroy = intel_dp_mst_encoder_destroy, | |
433 | }; | |
434 | ||
435 | static bool intel_dp_mst_get_hw_state(struct intel_connector *connector) | |
436 | { | |
e85376cb | 437 | if (connector->encoder && connector->base.state->crtc) { |
0e32b39c DA |
438 | enum pipe pipe; |
439 | if (!connector->encoder->get_hw_state(connector->encoder, &pipe)) | |
440 | return false; | |
441 | return true; | |
442 | } | |
443 | return false; | |
444 | } | |
445 | ||
7296c849 CW |
446 | static void intel_connector_add_to_fbdev(struct intel_connector *connector) |
447 | { | |
0695726e | 448 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
7296c849 | 449 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
54632abe LW |
450 | |
451 | if (dev_priv->fbdev) | |
452 | drm_fb_helper_add_one_connector(&dev_priv->fbdev->helper, | |
453 | &connector->base); | |
7296c849 CW |
454 | #endif |
455 | } | |
456 | ||
457 | static void intel_connector_remove_from_fbdev(struct intel_connector *connector) | |
458 | { | |
0695726e | 459 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
7296c849 | 460 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
54632abe LW |
461 | |
462 | if (dev_priv->fbdev) | |
463 | drm_fb_helper_remove_one_connector(&dev_priv->fbdev->helper, | |
464 | &connector->base); | |
7296c849 CW |
465 | #endif |
466 | } | |
467 | ||
12e6cecd | 468 | static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *pathprop) |
0e32b39c DA |
469 | { |
470 | struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); | |
471 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
472 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
0e32b39c DA |
473 | struct intel_connector *intel_connector; |
474 | struct drm_connector *connector; | |
475 | int i; | |
476 | ||
9bdbd0b9 | 477 | intel_connector = intel_connector_alloc(); |
0e32b39c DA |
478 | if (!intel_connector) |
479 | return NULL; | |
480 | ||
481 | connector = &intel_connector->base; | |
482 | drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort); | |
483 | drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs); | |
484 | ||
0e32b39c DA |
485 | intel_connector->get_hw_state = intel_dp_mst_get_hw_state; |
486 | intel_connector->mst_port = intel_dp; | |
487 | intel_connector->port = port; | |
488 | ||
489 | for (i = PIPE_A; i <= PIPE_C; i++) { | |
490 | drm_mode_connector_attach_encoder(&intel_connector->base, | |
491 | &intel_dp->mst_encoders[i]->base.base); | |
492 | } | |
0e32b39c DA |
493 | |
494 | drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); | |
6f134d7b DA |
495 | drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); |
496 | ||
0e32b39c | 497 | drm_mode_connector_set_path_property(connector, pathprop); |
d9515c5e DA |
498 | return connector; |
499 | } | |
500 | ||
501 | static void intel_dp_register_mst_connector(struct drm_connector *connector) | |
502 | { | |
503 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
504 | struct drm_device *dev = connector->dev; | |
7a418e34 | 505 | |
8bb4da1d | 506 | drm_modeset_lock_all(dev); |
7296c849 | 507 | intel_connector_add_to_fbdev(intel_connector); |
8bb4da1d | 508 | drm_modeset_unlock_all(dev); |
7a418e34 | 509 | |
0e32b39c | 510 | drm_connector_register(&intel_connector->base); |
0e32b39c DA |
511 | } |
512 | ||
513 | static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, | |
514 | struct drm_connector *connector) | |
515 | { | |
516 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
517 | struct drm_device *dev = connector->dev; | |
20fae983 | 518 | |
c191eca1 | 519 | drm_connector_unregister(connector); |
1f771755 | 520 | |
0e32b39c | 521 | /* need to nuke the connector */ |
8bb4da1d | 522 | drm_modeset_lock_all(dev); |
7296c849 | 523 | intel_connector_remove_from_fbdev(intel_connector); |
0552f765 | 524 | intel_connector->mst_port = NULL; |
8bb4da1d | 525 | drm_modeset_unlock_all(dev); |
0e32b39c | 526 | |
0552f765 | 527 | drm_connector_unreference(&intel_connector->base); |
0e32b39c DA |
528 | DRM_DEBUG_KMS("\n"); |
529 | } | |
530 | ||
531 | static void intel_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) | |
532 | { | |
533 | struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); | |
534 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
535 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
536 | ||
537 | drm_kms_helper_hotplug_event(dev); | |
538 | } | |
539 | ||
69a0f89c | 540 | static const struct drm_dp_mst_topology_cbs mst_cbs = { |
0e32b39c | 541 | .add_connector = intel_dp_add_mst_connector, |
d9515c5e | 542 | .register_connector = intel_dp_register_mst_connector, |
0e32b39c DA |
543 | .destroy_connector = intel_dp_destroy_mst_connector, |
544 | .hotplug = intel_dp_mst_hotplug, | |
545 | }; | |
546 | ||
547 | static struct intel_dp_mst_encoder * | |
548 | intel_dp_create_fake_mst_encoder(struct intel_digital_port *intel_dig_port, enum pipe pipe) | |
549 | { | |
550 | struct intel_dp_mst_encoder *intel_mst; | |
551 | struct intel_encoder *intel_encoder; | |
552 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
553 | ||
554 | intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL); | |
555 | ||
556 | if (!intel_mst) | |
557 | return NULL; | |
558 | ||
559 | intel_mst->pipe = pipe; | |
560 | intel_encoder = &intel_mst->base; | |
561 | intel_mst->primary = intel_dig_port; | |
562 | ||
563 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs, | |
580d8ed5 | 564 | DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe)); |
0e32b39c DA |
565 | |
566 | intel_encoder->type = INTEL_OUTPUT_DP_MST; | |
79f255a0 | 567 | intel_encoder->power_domain = intel_dig_port->base.power_domain; |
03cdc1d4 | 568 | intel_encoder->port = intel_dig_port->port; |
0e32b39c DA |
569 | intel_encoder->crtc_mask = 0x7; |
570 | intel_encoder->cloneable = 0; | |
571 | ||
572 | intel_encoder->compute_config = intel_dp_mst_compute_config; | |
573 | intel_encoder->disable = intel_mst_disable_dp; | |
574 | intel_encoder->post_disable = intel_mst_post_disable_dp; | |
575 | intel_encoder->pre_enable = intel_mst_pre_enable_dp; | |
576 | intel_encoder->enable = intel_mst_enable_dp; | |
577 | intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state; | |
578 | intel_encoder->get_config = intel_dp_mst_enc_get_config; | |
579 | ||
580 | return intel_mst; | |
581 | ||
582 | } | |
583 | ||
584 | static bool | |
585 | intel_dp_create_fake_mst_encoders(struct intel_digital_port *intel_dig_port) | |
586 | { | |
587 | int i; | |
588 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
589 | ||
590 | for (i = PIPE_A; i <= PIPE_C; i++) | |
591 | intel_dp->mst_encoders[i] = intel_dp_create_fake_mst_encoder(intel_dig_port, i); | |
592 | return true; | |
593 | } | |
594 | ||
595 | int | |
596 | intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_base_id) | |
597 | { | |
598 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
599 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
600 | int ret; | |
601 | ||
602 | intel_dp->can_mst = true; | |
603 | intel_dp->mst_mgr.cbs = &mst_cbs; | |
604 | ||
605 | /* create encoders */ | |
606 | intel_dp_create_fake_mst_encoders(intel_dig_port); | |
7b0a89a6 DP |
607 | ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, dev, |
608 | &intel_dp->aux, 16, 3, conn_base_id); | |
0e32b39c DA |
609 | if (ret) { |
610 | intel_dp->can_mst = false; | |
611 | return ret; | |
612 | } | |
613 | return 0; | |
614 | } | |
615 | ||
616 | void | |
617 | intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port) | |
618 | { | |
619 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
620 | ||
621 | if (!intel_dp->can_mst) | |
622 | return; | |
623 | ||
624 | drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr); | |
625 | /* encoders will get killed by normal cleanup */ | |
626 | } |