]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/intel_dpll_mgr.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Use crtc->name in debug messages
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dpll_mgr.c
CommitLineData
7abd4b35
ACO		 1/*
2 * Copyright © 2006-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include "intel_drv.h"
25
26struct intel_shared_dpll *
8106ddbd
ACO		 27intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
28 enum intel_dpll_id id)
7abd4b35 29{
8106ddbd
ACO		 30 return &dev_priv->shared_dplls[id];
31}
7abd4b35 32
8106ddbd
ACO		 33enum intel_dpll_id
34intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
35 struct intel_shared_dpll *pll)
36{
37 if (WARN_ON(pll < dev_priv->shared_dplls||
38 pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll]))
39 return -1;
40
41 return (enum intel_dpll_id) (pll - dev_priv->shared_dplls);
42}
43
44void
45intel_shared_dpll_config_get(struct intel_shared_dpll_config *config,
46 struct intel_shared_dpll *pll,
47 struct intel_crtc *crtc)
48{
49 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
50 enum intel_dpll_id id = intel_get_shared_dpll_id(dev_priv, pll);
51
52 config[id].crtc_mask |= 1 << crtc->pipe;
53}
54
55void
56intel_shared_dpll_config_put(struct intel_shared_dpll_config *config,
57 struct intel_shared_dpll *pll,
58 struct intel_crtc *crtc)
59{
60 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
61 enum intel_dpll_id id = intel_get_shared_dpll_id(dev_priv, pll);
7abd4b35 62
8106ddbd 63 config[id].crtc_mask &= ~(1 << crtc->pipe);
7abd4b35
ACO		 64}
65
66/* For ILK+ */
67void assert_shared_dpll(struct drm_i915_private *dev_priv,
68 struct intel_shared_dpll *pll,
69 bool state)
70{
71 bool cur_state;
72 struct intel_dpll_hw_state hw_state;
73
74 if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
75 return;
76
2edd6443 77 cur_state = pll->funcs.get_hw_state(dev_priv, pll, &hw_state);
7abd4b35
ACO		 78 I915_STATE_WARN(cur_state != state,
79 "%s assertion failure (expected %s, current %s)\n",
80 pll->name, onoff(state), onoff(cur_state));
81}
82
83void intel_prepare_shared_dpll(struct intel_crtc *crtc)
84{
85 struct drm_device *dev = crtc->base.dev;
86 struct drm_i915_private *dev_priv = dev->dev_private;
8106ddbd 87 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
7abd4b35
ACO		 88
89 if (WARN_ON(pll == NULL))
90 return;
91
fbf6d879 92 mutex_lock(&dev_priv->dpll_lock);
7abd4b35 93 WARN_ON(!pll->config.crtc_mask);
fbf6d879 94 if (!pll->active_mask) {
7abd4b35
ACO		 95 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
96 WARN_ON(pll->on);
97 assert_shared_dpll_disabled(dev_priv, pll);
98
2edd6443 99 pll->funcs.mode_set(dev_priv, pll);
7abd4b35 100 }
fbf6d879 101 mutex_unlock(&dev_priv->dpll_lock);
7abd4b35
ACO		 102}
103
104/**
105 * intel_enable_shared_dpll - enable PCH PLL
106 * @dev_priv: i915 private structure
107 * @pipe: pipe PLL to enable
108 *
109 * The PCH PLL needs to be enabled before the PCH transcoder, since it
110 * drives the transcoder clock.
111 */
112void intel_enable_shared_dpll(struct intel_crtc *crtc)
113{
114 struct drm_device *dev = crtc->base.dev;
115 struct drm_i915_private *dev_priv = dev->dev_private;
8106ddbd 116 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
2dd66ebd 117 unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);
fbf6d879 118 unsigned old_mask;
7abd4b35
ACO		 119
120 if (WARN_ON(pll == NULL))
121 return;
122
fbf6d879
ML		 123 mutex_lock(&dev_priv->dpll_lock);
124 old_mask = pll->active_mask;
125
2dd66ebd
ML		 126 if (WARN_ON(!(pll->config.crtc_mask & crtc_mask)) ||
127 WARN_ON(pll->active_mask & crtc_mask))
fbf6d879 128 goto out;
7abd4b35 129
2dd66ebd
ML		 130 pll->active_mask |= crtc_mask;
131
132 DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n",
133 pll->name, pll->active_mask, pll->on,
7abd4b35
ACO		 134 crtc->base.base.id);
135
2dd66ebd 136 if (old_mask) {
7abd4b35
ACO		 137 WARN_ON(!pll->on);
138 assert_shared_dpll_enabled(dev_priv, pll);
fbf6d879 139 goto out;
7abd4b35
ACO		 140 }
141 WARN_ON(pll->on);
142
7abd4b35 143 DRM_DEBUG_KMS("enabling %s\n", pll->name);
2edd6443 144 pll->funcs.enable(dev_priv, pll);
7abd4b35 145 pll->on = true;
fbf6d879
ML		 146
147out:
148 mutex_unlock(&dev_priv->dpll_lock);
7abd4b35
ACO		 149}
150
151void intel_disable_shared_dpll(struct intel_crtc *crtc)
152{
153 struct drm_device *dev = crtc->base.dev;
154 struct drm_i915_private *dev_priv = dev->dev_private;
8106ddbd 155 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
2dd66ebd 156 unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);
7abd4b35
ACO		 157
158 /* PCH only available on ILK+ */
159 if (INTEL_INFO(dev)->gen < 5)
160 return;
161
162 if (pll == NULL)
163 return;
164
fbf6d879 165 mutex_lock(&dev_priv->dpll_lock);
a1475e77 166 if (WARN_ON(!(pll->active_mask & crtc_mask)))
fbf6d879 167 goto out;
7abd4b35 168
2dd66ebd
ML		 169 DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n",
170 pll->name, pll->active_mask, pll->on,
7abd4b35
ACO		 171 crtc->base.base.id);
172
7abd4b35
ACO		 173 assert_shared_dpll_enabled(dev_priv, pll);
174 WARN_ON(!pll->on);
2dd66ebd
ML		 175
176 pll->active_mask &= ~crtc_mask;
177 if (pll->active_mask)
fbf6d879 178 goto out;
7abd4b35
ACO		 179
180 DRM_DEBUG_KMS("disabling %s\n", pll->name);
2edd6443 181 pll->funcs.disable(dev_priv, pll);
7abd4b35 182 pll->on = false;
fbf6d879
ML		 183
184out:
185 mutex_unlock(&dev_priv->dpll_lock);
7abd4b35
ACO		 186}
187
f9476a6c 188static struct intel_shared_dpll *
a4780b77 189intel_find_shared_dpll(struct intel_crtc *crtc,
f9476a6c
ACO		 190 struct intel_crtc_state *crtc_state,
191 enum intel_dpll_id range_min,
192 enum intel_dpll_id range_max)
a4780b77
ACO		 193{
194 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
195 struct intel_shared_dpll *pll;
196 struct intel_shared_dpll_config *shared_dpll;
197 enum intel_dpll_id i;
7abd4b35 198
a4780b77
ACO		 199 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
200
f9476a6c 201 for (i = range_min; i <= range_max; i++) {
7abd4b35
ACO		 202 pll = &dev_priv->shared_dplls[i];
203
204 /* Only want to check enabled timings first */
205 if (shared_dpll[i].crtc_mask == 0)
206 continue;
207
208 if (memcmp(&crtc_state->dpll_hw_state,
209 &shared_dpll[i].hw_state,
210 sizeof(crtc_state->dpll_hw_state)) == 0) {
78108b7c
VS		 211 DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",
212 crtc->base.base.id, crtc->base.name, pll->name,
7abd4b35 213 shared_dpll[i].crtc_mask,
2dd66ebd 214 pll->active_mask);
f9476a6c 215 return pll;
7abd4b35
ACO		 216 }
217 }
218
219 /* Ok no matching timings, maybe there's a free one? */
f9476a6c 220 for (i = range_min; i <= range_max; i++) {
7abd4b35
ACO		 221 pll = &dev_priv->shared_dplls[i];
222 if (shared_dpll[i].crtc_mask == 0) {
78108b7c
VS		 223 DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n",
224 crtc->base.base.id, crtc->base.name, pll->name);
f9476a6c 225 return pll;
7abd4b35
ACO		 226 }
227 }
228
f9476a6c 229 return NULL;
a4780b77
ACO		 230}
231
f9476a6c
ACO		 232static void
233intel_reference_shared_dpll(struct intel_shared_dpll *pll,
234 struct intel_crtc_state *crtc_state)
a4780b77 235{
a4780b77 236 struct intel_shared_dpll_config *shared_dpll;
f9476a6c
ACO		 237 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
238 enum intel_dpll_id i = pll->id;
a4780b77
ACO		 239
240 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
241
7abd4b35
ACO		 242 if (shared_dpll[i].crtc_mask == 0)
243 shared_dpll[i].hw_state =
244 crtc_state->dpll_hw_state;
245
8106ddbd 246 crtc_state->shared_dpll = pll;
7abd4b35
ACO		 247 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
248 pipe_name(crtc->pipe));
249
8106ddbd 250 intel_shared_dpll_config_get(shared_dpll, pll, crtc);
7abd4b35
ACO		 251}
252
253void intel_shared_dpll_commit(struct drm_atomic_state *state)
254{
255 struct drm_i915_private *dev_priv = to_i915(state->dev);
256 struct intel_shared_dpll_config *shared_dpll;
257 struct intel_shared_dpll *pll;
258 enum intel_dpll_id i;
259
260 if (!to_intel_atomic_state(state)->dpll_set)
261 return;
262
263 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
264 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
265 pll = &dev_priv->shared_dplls[i];
266 pll->config = shared_dpll[i];
267 }
268}
269
270static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
271 struct intel_shared_dpll *pll,
272 struct intel_dpll_hw_state *hw_state)
273{
274 uint32_t val;
275
276 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
277 return false;
278
279 val = I915_READ(PCH_DPLL(pll->id));
280 hw_state->dpll = val;
281 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
282 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
283
284 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
285
286 return val & DPLL_VCO_ENABLE;
287}
288
289static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
290 struct intel_shared_dpll *pll)
291{
292 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
293 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
294}
295
296static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
297{
298 u32 val;
299 bool enabled;
300
2d1fe073 301 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7abd4b35
ACO		 302
303 val = I915_READ(PCH_DREF_CONTROL);
304 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
305 DREF_SUPERSPREAD_SOURCE_MASK));
306 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
307}
308
309static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
310 struct intel_shared_dpll *pll)
311{
312 /* PCH refclock must be enabled first */
313 ibx_assert_pch_refclk_enabled(dev_priv);
314
315 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
316
317 /* Wait for the clocks to stabilize. */
318 POSTING_READ(PCH_DPLL(pll->id));
319 udelay(150);
320
321 /* The pixel multiplier can only be updated once the
322 * DPLL is enabled and the clocks are stable.
323 *
324 * So write it again.
325 */
326 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
327 POSTING_READ(PCH_DPLL(pll->id));
328 udelay(200);
329}
330
331static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
332 struct intel_shared_dpll *pll)
333{
334 struct drm_device *dev = dev_priv->dev;
335 struct intel_crtc *crtc;
336
337 /* Make sure no transcoder isn't still depending on us. */
338 for_each_intel_crtc(dev, crtc) {
8106ddbd 339 if (crtc->config->shared_dpll == pll)
7abd4b35
ACO		 340 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
341 }
342
343 I915_WRITE(PCH_DPLL(pll->id), 0);
344 POSTING_READ(PCH_DPLL(pll->id));
345 udelay(200);
346}
347
f9476a6c 348static struct intel_shared_dpll *
daedf20a
ACO		 349ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
350 struct intel_encoder *encoder)
f9476a6c
ACO		 351{
352 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
353 struct intel_shared_dpll *pll;
354 enum intel_dpll_id i;
355
356 if (HAS_PCH_IBX(dev_priv)) {
357 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
358 i = (enum intel_dpll_id) crtc->pipe;
359 pll = &dev_priv->shared_dplls[i];
360
78108b7c
VS		 361 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
362 crtc->base.base.id, crtc->base.name, pll->name);
f9476a6c
ACO		 363 } else {
364 pll = intel_find_shared_dpll(crtc, crtc_state,
365 DPLL_ID_PCH_PLL_A,
366 DPLL_ID_PCH_PLL_B);
367 }
368
bb143165
ACO		 369 if (!pll)
370 return NULL;
371
f9476a6c
ACO		 372 /* reference the pll */
373 intel_reference_shared_dpll(pll, crtc_state);
374
375 return pll;
376}
377
2edd6443
ACO		 378static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
379 .mode_set = ibx_pch_dpll_mode_set,
380 .enable = ibx_pch_dpll_enable,
381 .disable = ibx_pch_dpll_disable,
382 .get_hw_state = ibx_pch_dpll_get_hw_state,
7abd4b35
ACO		 383};
384
55be2f08
ACO		 385static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
386 struct intel_shared_dpll *pll)
387{
388 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
389 POSTING_READ(WRPLL_CTL(pll->id));
390 udelay(20);
391}
392
393static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
394 struct intel_shared_dpll *pll)
395{
396 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
397 POSTING_READ(SPLL_CTL);
398 udelay(20);
399}
400
401static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
402 struct intel_shared_dpll *pll)
403{
404 uint32_t val;
405
406 val = I915_READ(WRPLL_CTL(pll->id));
407 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
408 POSTING_READ(WRPLL_CTL(pll->id));
409}
410
411static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
412 struct intel_shared_dpll *pll)
413{
414 uint32_t val;
415
416 val = I915_READ(SPLL_CTL);
417 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
418 POSTING_READ(SPLL_CTL);
419}
420
421static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
422 struct intel_shared_dpll *pll,
423 struct intel_dpll_hw_state *hw_state)
424{
425 uint32_t val;
426
427 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
428 return false;
429
430 val = I915_READ(WRPLL_CTL(pll->id));
431 hw_state->wrpll = val;
432
433 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
434
435 return val & WRPLL_PLL_ENABLE;
436}
437
438static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
439 struct intel_shared_dpll *pll,
440 struct intel_dpll_hw_state *hw_state)
441{
442 uint32_t val;
443
444 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
445 return false;
446
447 val = I915_READ(SPLL_CTL);
448 hw_state->spll = val;
449
450 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
451
452 return val & SPLL_PLL_ENABLE;
453}
454
daedf20a
ACO		 455static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
456{
457 switch (pll->id) {
458 case DPLL_ID_WRPLL1:
459 return PORT_CLK_SEL_WRPLL1;
460 case DPLL_ID_WRPLL2:
461 return PORT_CLK_SEL_WRPLL2;
462 case DPLL_ID_SPLL:
463 return PORT_CLK_SEL_SPLL;
9d16da65
ACO		 464 case DPLL_ID_LCPLL_810:
465 return PORT_CLK_SEL_LCPLL_810;
466 case DPLL_ID_LCPLL_1350:
467 return PORT_CLK_SEL_LCPLL_1350;
468 case DPLL_ID_LCPLL_2700:
469 return PORT_CLK_SEL_LCPLL_2700;
daedf20a
ACO		 470 default:
471 return PORT_CLK_SEL_NONE;
472 }
473}
474
475#define LC_FREQ 2700
476#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
477
478#define P_MIN 2
479#define P_MAX 64
480#define P_INC 2
481
482/* Constraints for PLL good behavior */
483#define REF_MIN 48
484#define REF_MAX 400
485#define VCO_MIN 2400
486#define VCO_MAX 4800
487
488struct hsw_wrpll_rnp {
489 unsigned p, n2, r2;
490};
491
492static unsigned hsw_wrpll_get_budget_for_freq(int clock)
493{
494 unsigned budget;
495
496 switch (clock) {
497 case 25175000:
498 case 25200000:
499 case 27000000:
500 case 27027000:
501 case 37762500:
502 case 37800000:
503 case 40500000:
504 case 40541000:
505 case 54000000:
506 case 54054000:
507 case 59341000:
508 case 59400000:
509 case 72000000:
510 case 74176000:
511 case 74250000:
512 case 81000000:
513 case 81081000:
514 case 89012000:
515 case 89100000:
516 case 108000000:
517 case 108108000:
518 case 111264000:
519 case 111375000:
520 case 148352000:
521 case 148500000:
522 case 162000000:
523 case 162162000:
524 case 222525000:
525 case 222750000:
526 case 296703000:
527 case 297000000:
528 budget = 0;
529 break;
530 case 233500000:
531 case 245250000:
532 case 247750000:
533 case 253250000:
534 case 298000000:
535 budget = 1500;
536 break;
537 case 169128000:
538 case 169500000:
539 case 179500000:
540 case 202000000:
541 budget = 2000;
542 break;
543 case 256250000:
544 case 262500000:
545 case 270000000:
546 case 272500000:
547 case 273750000:
548 case 280750000:
549 case 281250000:
550 case 286000000:
551 case 291750000:
552 budget = 4000;
553 break;
554 case 267250000:
555 case 268500000:
556 budget = 5000;
557 break;
558 default:
559 budget = 1000;
560 break;
561 }
562
563 return budget;
564}
565
566static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
567 unsigned r2, unsigned n2, unsigned p,
568 struct hsw_wrpll_rnp *best)
569{
570 uint64_t a, b, c, d, diff, diff_best;
571
572 /* No best (r,n,p) yet */
573 if (best->p == 0) {
574 best->p = p;
575 best->n2 = n2;
576 best->r2 = r2;
577 return;
578 }
579
580 /*
581 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
582 * freq2k.
583 *
584 * delta = 1e6 *
585 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
586 * freq2k;
587 *
588 * and we would like delta <= budget.
589 *
590 * If the discrepancy is above the PPM-based budget, always prefer to
591 * improve upon the previous solution. However, if you're within the
592 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
593 */
594 a = freq2k * budget * p * r2;
595 b = freq2k * budget * best->p * best->r2;
596 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
597 diff_best = abs_diff(freq2k * best->p * best->r2,
598 LC_FREQ_2K * best->n2);
599 c = 1000000 * diff;
600 d = 1000000 * diff_best;
601
602 if (a < c && b < d) {
603 /* If both are above the budget, pick the closer */
604 if (best->p * best->r2 * diff < p * r2 * diff_best) {
605 best->p = p;
606 best->n2 = n2;
607 best->r2 = r2;
608 }
609 } else if (a >= c && b < d) {
610 /* If A is below the threshold but B is above it? Update. */
611 best->p = p;
612 best->n2 = n2;
613 best->r2 = r2;
614 } else if (a >= c && b >= d) {
615 /* Both are below the limit, so pick the higher n2/(r2*r2) */
616 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
617 best->p = p;
618 best->n2 = n2;
619 best->r2 = r2;
620 }
621 }
622 /* Otherwise a < c && b >= d, do nothing */
623}
624
625static void
626hsw_ddi_calculate_wrpll(int clock /* in Hz */,
627 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
628{
629 uint64_t freq2k;
630 unsigned p, n2, r2;
631 struct hsw_wrpll_rnp best = { 0, 0, 0 };
632 unsigned budget;
633
634 freq2k = clock / 100;
635
636 budget = hsw_wrpll_get_budget_for_freq(clock);
637
638 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
639 * and directly pass the LC PLL to it. */
640 if (freq2k == 5400000) {
641 *n2_out = 2;
642 *p_out = 1;
643 *r2_out = 2;
644 return;
645 }
646
647 /*
648 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
649 * the WR PLL.
650 *
651 * We want R so that REF_MIN <= Ref <= REF_MAX.
652 * Injecting R2 = 2 * R gives:
653 * REF_MAX * r2 > LC_FREQ * 2 and
654 * REF_MIN * r2 < LC_FREQ * 2
655 *
656 * Which means the desired boundaries for r2 are:
657 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
658 *
659 */
660 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
661 r2 <= LC_FREQ * 2 / REF_MIN;
662 r2++) {
663
664 /*
665 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
666 *
667 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
668 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
669 * VCO_MAX * r2 > n2 * LC_FREQ and
670 * VCO_MIN * r2 < n2 * LC_FREQ)
671 *
672 * Which means the desired boundaries for n2 are:
673 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
674 */
675 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
676 n2 <= VCO_MAX * r2 / LC_FREQ;
677 n2++) {
678
679 for (p = P_MIN; p <= P_MAX; p += P_INC)
680 hsw_wrpll_update_rnp(freq2k, budget,
681 r2, n2, p, &best);
682 }
683 }
684
685 *n2_out = best.n2;
686 *p_out = best.p;
687 *r2_out = best.r2;
688}
689
f9476a6c 690static struct intel_shared_dpll *
daedf20a
ACO		 691hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
692 struct intel_encoder *encoder)
f9476a6c 693{
9d16da65 694 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
f9476a6c 695 struct intel_shared_dpll *pll;
daedf20a 696 int clock = crtc_state->port_clock;
f9476a6c 697
9d16da65
ACO		 698 memset(&crtc_state->dpll_hw_state, 0,
699 sizeof(crtc_state->dpll_hw_state));
700
daedf20a
ACO		 701 if (encoder->type == INTEL_OUTPUT_HDMI) {
702 uint32_t val;
703 unsigned p, n2, r2;
704
705 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
706
707 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
708 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
709 WRPLL_DIVIDER_POST(p);
710
daedf20a
ACO		 711 crtc_state->dpll_hw_state.wrpll = val;
712
713 pll = intel_find_shared_dpll(crtc, crtc_state,
714 DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
715
9d16da65
ACO		 716 } else if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
717 encoder->type == INTEL_OUTPUT_DP_MST ||
718 encoder->type == INTEL_OUTPUT_EDP) {
719 enum intel_dpll_id pll_id;
720
721 switch (clock / 2) {
722 case 81000:
723 pll_id = DPLL_ID_LCPLL_810;
724 break;
725 case 135000:
726 pll_id = DPLL_ID_LCPLL_1350;
727 break;
728 case 270000:
729 pll_id = DPLL_ID_LCPLL_2700;
730 break;
731 default:
732 DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock);
733 return NULL;
734 }
735
736 pll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
737
daedf20a
ACO		 738 } else if (encoder->type == INTEL_OUTPUT_ANALOG) {
739 if (WARN_ON(crtc_state->port_clock / 2 != 135000))
740 return NULL;
741
daedf20a
ACO		 742 crtc_state->dpll_hw_state.spll =
743 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
744
745 pll = intel_find_shared_dpll(crtc, crtc_state,
746 DPLL_ID_SPLL, DPLL_ID_SPLL);
747 } else {
748 return NULL;
749 }
750
751 if (!pll)
752 return NULL;
753
754 crtc_state->ddi_pll_sel = hsw_pll_to_ddi_pll_sel(pll);
755
756 intel_reference_shared_dpll(pll, crtc_state);
f9476a6c
ACO		 757
758 return pll;
759}
760
55be2f08 761
2edd6443
ACO		 762static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
763 .enable = hsw_ddi_wrpll_enable,
764 .disable = hsw_ddi_wrpll_disable,
765 .get_hw_state = hsw_ddi_wrpll_get_hw_state,
55be2f08
ACO		 766};
767
2edd6443
ACO		 768static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
769 .enable = hsw_ddi_spll_enable,
770 .disable = hsw_ddi_spll_disable,
771 .get_hw_state = hsw_ddi_spll_get_hw_state,
55be2f08
ACO		 772};
773
9d16da65
ACO		 774static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
775 struct intel_shared_dpll *pll)
776{
777}
778
779static void hsw_ddi_lcpll_disable(struct drm_i915_private *dev_priv,
780 struct intel_shared_dpll *pll)
781{
782}
783
784static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv,
785 struct intel_shared_dpll *pll,
786 struct intel_dpll_hw_state *hw_state)
787{
788 return true;
789}
790
791static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
792 .enable = hsw_ddi_lcpll_enable,
793 .disable = hsw_ddi_lcpll_disable,
794 .get_hw_state = hsw_ddi_lcpll_get_hw_state,
795};
796
55be2f08
ACO		 797struct skl_dpll_regs {
798 i915_reg_t ctl, cfgcr1, cfgcr2;
799};
800
801/* this array is indexed by the *shared* pll id */
a3c988ea
ACO		 802static const struct skl_dpll_regs skl_dpll_regs[4] = {
803 {
804 /* DPLL 0 */
805 .ctl = LCPLL1_CTL,
806 /* DPLL 0 doesn't support HDMI mode */
807 },
55be2f08
ACO		 808 {
809 /* DPLL 1 */
810 .ctl = LCPLL2_CTL,
811 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
812 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
813 },
814 {
815 /* DPLL 2 */
816 .ctl = WRPLL_CTL(0),
817 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
818 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
819 },
820 {
821 /* DPLL 3 */
822 .ctl = WRPLL_CTL(1),
823 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
824 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
825 },
826};
827
a3c988ea
ACO		 828static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
829 struct intel_shared_dpll *pll)
55be2f08
ACO		 830{
831 uint32_t val;
55be2f08
ACO		 832
833 val = I915_READ(DPLL_CTRL1);
834
a3c988ea
ACO		 835 val &= ~(DPLL_CTRL1_HDMI_MODE(pll->id) | DPLL_CTRL1_SSC(pll->id) |
836 DPLL_CTRL1_LINK_RATE_MASK(pll->id));
837 val |= pll->config.hw_state.ctrl1 << (pll->id * 6);
55be2f08
ACO		 838
839 I915_WRITE(DPLL_CTRL1, val);
840 POSTING_READ(DPLL_CTRL1);
a3c988ea
ACO		 841}
842
843static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
844 struct intel_shared_dpll *pll)
845{
846 const struct skl_dpll_regs *regs = skl_dpll_regs;
847
848 skl_ddi_pll_write_ctrl1(dev_priv, pll);
55be2f08
ACO		 849
850 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
851 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
852 POSTING_READ(regs[pll->id].cfgcr1);
853 POSTING_READ(regs[pll->id].cfgcr2);
854
855 /* the enable bit is always bit 31 */
856 I915_WRITE(regs[pll->id].ctl,
857 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
858
a3c988ea
ACO		 859 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(pll->id), 5))
860 DRM_ERROR("DPLL %d not locked\n", pll->id);
861}
862
863static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv,
864 struct intel_shared_dpll *pll)
865{
866 skl_ddi_pll_write_ctrl1(dev_priv, pll);
55be2f08
ACO		 867}
868
869static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
870 struct intel_shared_dpll *pll)
871{
872 const struct skl_dpll_regs *regs = skl_dpll_regs;
873
874 /* the enable bit is always bit 31 */
875 I915_WRITE(regs[pll->id].ctl,
876 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
877 POSTING_READ(regs[pll->id].ctl);
878}
879
a3c988ea
ACO		 880static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv,
881 struct intel_shared_dpll *pll)
882{
883}
884
55be2f08
ACO		 885static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
886 struct intel_shared_dpll *pll,
887 struct intel_dpll_hw_state *hw_state)
888{
889 uint32_t val;
55be2f08
ACO		 890 const struct skl_dpll_regs *regs = skl_dpll_regs;
891 bool ret;
892
893 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
894 return false;
895
896 ret = false;
897
55be2f08
ACO		 898 val = I915_READ(regs[pll->id].ctl);
899 if (!(val & LCPLL_PLL_ENABLE))
900 goto out;
901
902 val = I915_READ(DPLL_CTRL1);
a3c988ea 903 hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f;
55be2f08
ACO		 904
905 /* avoid reading back stale values if HDMI mode is not enabled */
a3c988ea 906 if (val & DPLL_CTRL1_HDMI_MODE(pll->id)) {
55be2f08
ACO		 907 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
908 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
909 }
910 ret = true;
911
912out:
913 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
914
915 return ret;
916}
917
a3c988ea
ACO		 918static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
919 struct intel_shared_dpll *pll,
920 struct intel_dpll_hw_state *hw_state)
921{
922 uint32_t val;
923 const struct skl_dpll_regs *regs = skl_dpll_regs;
924 bool ret;
925
926 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
927 return false;
928
929 ret = false;
930
931 /* DPLL0 is always enabled since it drives CDCLK */
932 val = I915_READ(regs[pll->id].ctl);
933 if (WARN_ON(!(val & LCPLL_PLL_ENABLE)))
934 goto out;
935
936 val = I915_READ(DPLL_CTRL1);
937 hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f;
938
939 ret = true;
940
941out:
942 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
943
944 return ret;
945}
946
304b65cb
ACO		 947struct skl_wrpll_context {
948 uint64_t min_deviation; /* current minimal deviation */
949 uint64_t central_freq; /* chosen central freq */
950 uint64_t dco_freq; /* chosen dco freq */
951 unsigned int p; /* chosen divider */
952};
953
954static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
955{
956 memset(ctx, 0, sizeof(*ctx));
957
958 ctx->min_deviation = U64_MAX;
959}
960
961/* DCO freq must be within +1%/-6% of the DCO central freq */
962#define SKL_DCO_MAX_PDEVIATION 100
963#define SKL_DCO_MAX_NDEVIATION 600
964
965static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
966 uint64_t central_freq,
967 uint64_t dco_freq,
968 unsigned int divider)
969{
970 uint64_t deviation;
971
972 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
973 central_freq);
974
975 /* positive deviation */
976 if (dco_freq >= central_freq) {
977 if (deviation < SKL_DCO_MAX_PDEVIATION &&
978 deviation < ctx->min_deviation) {
979 ctx->min_deviation = deviation;
980 ctx->central_freq = central_freq;
981 ctx->dco_freq = dco_freq;
982 ctx->p = divider;
983 }
984 /* negative deviation */
985 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
986 deviation < ctx->min_deviation) {
987 ctx->min_deviation = deviation;
988 ctx->central_freq = central_freq;
989 ctx->dco_freq = dco_freq;
990 ctx->p = divider;
991 }
992}
993
994static void skl_wrpll_get_multipliers(unsigned int p,
995 unsigned int *p0 /* out */,
996 unsigned int *p1 /* out */,
997 unsigned int *p2 /* out */)
998{
999 /* even dividers */
1000 if (p % 2 == 0) {
1001 unsigned int half = p / 2;
1002
1003 if (half == 1 || half == 2 || half == 3 || half == 5) {
1004 *p0 = 2;
1005 *p1 = 1;
1006 *p2 = half;
1007 } else if (half % 2 == 0) {
1008 *p0 = 2;
1009 *p1 = half / 2;
1010 *p2 = 2;
1011 } else if (half % 3 == 0) {
1012 *p0 = 3;
1013 *p1 = half / 3;
1014 *p2 = 2;
1015 } else if (half % 7 == 0) {
1016 *p0 = 7;
1017 *p1 = half / 7;
1018 *p2 = 2;
1019 }
1020 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1021 *p0 = 3;
1022 *p1 = 1;
1023 *p2 = p / 3;
1024 } else if (p == 5 || p == 7) {
1025 *p0 = p;
1026 *p1 = 1;
1027 *p2 = 1;
1028 } else if (p == 15) {
1029 *p0 = 3;
1030 *p1 = 1;
1031 *p2 = 5;
1032 } else if (p == 21) {
1033 *p0 = 7;
1034 *p1 = 1;
1035 *p2 = 3;
1036 } else if (p == 35) {
1037 *p0 = 7;
1038 *p1 = 1;
1039 *p2 = 5;
1040 }
1041}
1042
1043struct skl_wrpll_params {
1044 uint32_t dco_fraction;
1045 uint32_t dco_integer;
1046 uint32_t qdiv_ratio;
1047 uint32_t qdiv_mode;
1048 uint32_t kdiv;
1049 uint32_t pdiv;
1050 uint32_t central_freq;
1051};
1052
1053static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1054 uint64_t afe_clock,
1055 uint64_t central_freq,
1056 uint32_t p0, uint32_t p1, uint32_t p2)
1057{
1058 uint64_t dco_freq;
1059
1060 switch (central_freq) {
1061 case 9600000000ULL:
1062 params->central_freq = 0;
1063 break;
1064 case 9000000000ULL:
1065 params->central_freq = 1;
1066 break;
1067 case 8400000000ULL:
1068 params->central_freq = 3;
1069 }
1070
1071 switch (p0) {
1072 case 1:
1073 params->pdiv = 0;
1074 break;
1075 case 2:
1076 params->pdiv = 1;
1077 break;
1078 case 3:
1079 params->pdiv = 2;
1080 break;
1081 case 7:
1082 params->pdiv = 4;
1083 break;
1084 default:
1085 WARN(1, "Incorrect PDiv\n");
1086 }
1087
1088 switch (p2) {
1089 case 5:
1090 params->kdiv = 0;
1091 break;
1092 case 2:
1093 params->kdiv = 1;
1094 break;
1095 case 3:
1096 params->kdiv = 2;
1097 break;
1098 case 1:
1099 params->kdiv = 3;
1100 break;
1101 default:
1102 WARN(1, "Incorrect KDiv\n");
1103 }
1104
1105 params->qdiv_ratio = p1;
1106 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1107
1108 dco_freq = p0 * p1 * p2 * afe_clock;
1109
1110 /*
1111 * Intermediate values are in Hz.
1112 * Divide by MHz to match bsepc
1113 */
1114 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
1115 params->dco_fraction =
1116 div_u64((div_u64(dco_freq, 24) -
1117 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1118}
1119
1120static bool
1121skl_ddi_calculate_wrpll(int clock /* in Hz */,
1122 struct skl_wrpll_params *wrpll_params)
1123{
1124 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1125 uint64_t dco_central_freq[3] = {8400000000ULL,
1126 9000000000ULL,
1127 9600000000ULL};
1128 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1129 24, 28, 30, 32, 36, 40, 42, 44,
1130 48, 52, 54, 56, 60, 64, 66, 68,
1131 70, 72, 76, 78, 80, 84, 88, 90,
1132 92, 96, 98 };
1133 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1134 static const struct {
1135 const int *list;
1136 int n_dividers;
1137 } dividers[] = {
1138 { even_dividers, ARRAY_SIZE(even_dividers) },
1139 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1140 };
1141 struct skl_wrpll_context ctx;
1142 unsigned int dco, d, i;
1143 unsigned int p0, p1, p2;
1144
1145 skl_wrpll_context_init(&ctx);
1146
1147 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1148 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1149 for (i = 0; i < dividers[d].n_dividers; i++) {
1150 unsigned int p = dividers[d].list[i];
1151 uint64_t dco_freq = p * afe_clock;
1152
1153 skl_wrpll_try_divider(&ctx,
1154 dco_central_freq[dco],
1155 dco_freq,
1156 p);
1157 /*
1158 * Skip the remaining dividers if we're sure to
1159 * have found the definitive divider, we can't
1160 * improve a 0 deviation.
1161 */
1162 if (ctx.min_deviation == 0)
1163 goto skip_remaining_dividers;
1164 }
1165 }
1166
1167skip_remaining_dividers:
1168 /*
1169 * If a solution is found with an even divider, prefer
1170 * this one.
1171 */
1172 if (d == 0 && ctx.p)
1173 break;
1174 }
1175
1176 if (!ctx.p) {
1177 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
1178 return false;
1179 }
1180
1181 /*
1182 * gcc incorrectly analyses that these can be used without being
1183 * initialized. To be fair, it's hard to guess.
1184 */
1185 p0 = p1 = p2 = 0;
1186 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1187 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1188 p0, p1, p2);
1189
1190 return true;
1191}
1192
f9476a6c 1193static struct intel_shared_dpll *
daedf20a
ACO		 1194skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1195 struct intel_encoder *encoder)
f9476a6c
ACO		 1196{
1197 struct intel_shared_dpll *pll;
304b65cb
ACO		 1198 uint32_t ctrl1, cfgcr1, cfgcr2;
1199 int clock = crtc_state->port_clock;
1200
1201 /*
1202 * See comment in intel_dpll_hw_state to understand why we always use 0
1203 * as the DPLL id in this function.
1204 */
1205
1206 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1207
1208 if (encoder->type == INTEL_OUTPUT_HDMI) {
1209 struct skl_wrpll_params wrpll_params = { 0, };
1210
1211 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1212
1213 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
52e2abb3 1214 return NULL;
304b65cb
ACO		 1215
1216 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1217 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1218 wrpll_params.dco_integer;
1219
1220 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1221 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1222 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1223 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1224 wrpll_params.central_freq;
1225 } else if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
a3c988ea
ACO		 1226 encoder->type == INTEL_OUTPUT_DP_MST ||
1227 encoder->type == INTEL_OUTPUT_EDP) {
304b65cb
ACO		 1228 switch (crtc_state->port_clock / 2) {
1229 case 81000:
1230 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1231 break;
1232 case 135000:
1233 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1234 break;
1235 case 270000:
1236 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1237 break;
a3c988ea
ACO		 1238 /* eDP 1.4 rates */
1239 case 162000:
1240 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
1241 break;
a3c988ea
ACO		 1242 case 108000:
1243 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
1244 break;
1245 case 216000:
1246 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
1247 break;
304b65cb
ACO		 1248 }
1249
1250 cfgcr1 = cfgcr2 = 0;
1251 } else {
1252 return NULL;
1253 }
1254
1255 memset(&crtc_state->dpll_hw_state, 0,
1256 sizeof(crtc_state->dpll_hw_state));
1257
1258 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1259 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1260 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
f9476a6c 1261
a3c988ea
ACO		 1262 if (encoder->type == INTEL_OUTPUT_EDP)
1263 pll = intel_find_shared_dpll(crtc, crtc_state,
1264 DPLL_ID_SKL_DPLL0,
1265 DPLL_ID_SKL_DPLL0);
1266 else
1267 pll = intel_find_shared_dpll(crtc, crtc_state,
1268 DPLL_ID_SKL_DPLL1,
1269 DPLL_ID_SKL_DPLL3);
304b65cb
ACO		 1270 if (!pll)
1271 return NULL;
1272
a3c988ea 1273 crtc_state->ddi_pll_sel = pll->id;
304b65cb
ACO		 1274
1275 intel_reference_shared_dpll(pll, crtc_state);
f9476a6c
ACO		 1276
1277 return pll;
1278}
1279
2edd6443
ACO		 1280static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
1281 .enable = skl_ddi_pll_enable,
1282 .disable = skl_ddi_pll_disable,
1283 .get_hw_state = skl_ddi_pll_get_hw_state,
55be2f08
ACO		 1284};
1285
a3c988ea
ACO		 1286static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
1287 .enable = skl_ddi_dpll0_enable,
1288 .disable = skl_ddi_dpll0_disable,
1289 .get_hw_state = skl_ddi_dpll0_get_hw_state,
1290};
1291
55be2f08
ACO		 1292static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
1293 struct intel_shared_dpll *pll)
1294{
1295 uint32_t temp;
1296 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
1297
55be2f08 1298 /* Non-SSC reference */
da6110bc
DK		 1299 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1300 temp |= PORT_PLL_REF_SEL;
55be2f08
ACO		 1301 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1302
1303 /* Disable 10 bit clock */
1304 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
1305 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1306 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
1307
1308 /* Write P1 & P2 */
1309 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
1310 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
1311 temp |= pll->config.hw_state.ebb0;
1312 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
1313
1314 /* Write M2 integer */
1315 temp = I915_READ(BXT_PORT_PLL(port, 0));
1316 temp &= ~PORT_PLL_M2_MASK;
1317 temp |= pll->config.hw_state.pll0;
1318 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
1319
1320 /* Write N */
1321 temp = I915_READ(BXT_PORT_PLL(port, 1));
1322 temp &= ~PORT_PLL_N_MASK;
1323 temp |= pll->config.hw_state.pll1;
1324 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
1325
1326 /* Write M2 fraction */
1327 temp = I915_READ(BXT_PORT_PLL(port, 2));
1328 temp &= ~PORT_PLL_M2_FRAC_MASK;
1329 temp |= pll->config.hw_state.pll2;
1330 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
1331
1332 /* Write M2 fraction enable */
1333 temp = I915_READ(BXT_PORT_PLL(port, 3));
1334 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
1335 temp |= pll->config.hw_state.pll3;
1336 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
1337
1338 /* Write coeff */
1339 temp = I915_READ(BXT_PORT_PLL(port, 6));
1340 temp &= ~PORT_PLL_PROP_COEFF_MASK;
1341 temp &= ~PORT_PLL_INT_COEFF_MASK;
1342 temp &= ~PORT_PLL_GAIN_CTL_MASK;
1343 temp |= pll->config.hw_state.pll6;
1344 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
1345
1346 /* Write calibration val */
1347 temp = I915_READ(BXT_PORT_PLL(port, 8));
1348 temp &= ~PORT_PLL_TARGET_CNT_MASK;
1349 temp |= pll->config.hw_state.pll8;
1350 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
1351
1352 temp = I915_READ(BXT_PORT_PLL(port, 9));
1353 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
1354 temp |= pll->config.hw_state.pll9;
1355 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
1356
1357 temp = I915_READ(BXT_PORT_PLL(port, 10));
1358 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
1359 temp &= ~PORT_PLL_DCO_AMP_MASK;
1360 temp |= pll->config.hw_state.pll10;
1361 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
1362
1363 /* Recalibrate with new settings */
1364 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
1365 temp |= PORT_PLL_RECALIBRATE;
1366 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
1367 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1368 temp |= pll->config.hw_state.ebb4;
1369 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
1370
1371 /* Enable PLL */
1372 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1373 temp |= PORT_PLL_ENABLE;
1374 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1375 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1376
1377 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
1378 PORT_PLL_LOCK), 200))
1379 DRM_ERROR("PLL %d not locked\n", port);
1380
1381 /*
1382 * While we write to the group register to program all lanes at once we
1383 * can read only lane registers and we pick lanes 0/1 for that.
1384 */
1385 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
1386 temp &= ~LANE_STAGGER_MASK;
1387 temp &= ~LANESTAGGER_STRAP_OVRD;
1388 temp |= pll->config.hw_state.pcsdw12;
1389 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
1390}
1391
1392static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
1393 struct intel_shared_dpll *pll)
1394{
1395 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
1396 uint32_t temp;
1397
1398 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1399 temp &= ~PORT_PLL_ENABLE;
1400 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1401 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1402}
1403
1404static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1405 struct intel_shared_dpll *pll,
1406 struct intel_dpll_hw_state *hw_state)
1407{
1408 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
1409 uint32_t val;
1410 bool ret;
1411
1412 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
1413 return false;
1414
1415 ret = false;
1416
1417 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
1418 if (!(val & PORT_PLL_ENABLE))
1419 goto out;
1420
1421 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
1422 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
1423
1424 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
1425 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
1426
1427 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
1428 hw_state->pll0 &= PORT_PLL_M2_MASK;
1429
1430 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
1431 hw_state->pll1 &= PORT_PLL_N_MASK;
1432
1433 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
1434 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
1435
1436 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
1437 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
1438
1439 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
1440 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
1441 PORT_PLL_INT_COEFF_MASK |
1442 PORT_PLL_GAIN_CTL_MASK;
1443
1444 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
1445 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
1446
1447 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
1448 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
1449
1450 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
1451 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
1452 PORT_PLL_DCO_AMP_MASK;
1453
1454 /*
1455 * While we write to the group register to program all lanes at once we
1456 * can read only lane registers. We configure all lanes the same way, so
1457 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
1458 */
1459 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
1460 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
1461 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
1462 hw_state->pcsdw12,
1463 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
1464 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
1465
1466 ret = true;
1467
1468out:
1469 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1470
1471 return ret;
1472}
1473
34177c24
ACO		 1474/* bxt clock parameters */
1475struct bxt_clk_div {
1476 int clock;
1477 uint32_t p1;
1478 uint32_t p2;
1479 uint32_t m2_int;
1480 uint32_t m2_frac;
1481 bool m2_frac_en;
1482 uint32_t n;
1483};
1484
1485/* pre-calculated values for DP linkrates */
1486static const struct bxt_clk_div bxt_dp_clk_val[] = {
1487 {162000, 4, 2, 32, 1677722, 1, 1},
1488 {270000, 4, 1, 27, 0, 0, 1},
1489 {540000, 2, 1, 27, 0, 0, 1},
1490 {216000, 3, 2, 32, 1677722, 1, 1},
1491 {243000, 4, 1, 24, 1258291, 1, 1},
1492 {324000, 4, 1, 32, 1677722, 1, 1},
1493 {432000, 3, 1, 32, 1677722, 1, 1}
1494};
1495
f9476a6c 1496static struct intel_shared_dpll *
daedf20a
ACO		 1497bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1498 struct intel_encoder *encoder)
f9476a6c
ACO		 1499{
1500 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
f9476a6c
ACO		 1501 struct intel_shared_dpll *pll;
1502 enum intel_dpll_id i;
34177c24
ACO		 1503 struct intel_digital_port *intel_dig_port;
1504 struct bxt_clk_div clk_div = {0};
1505 int vco = 0;
1506 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
1507 uint32_t lanestagger;
1508 int clock = crtc_state->port_clock;
f9476a6c 1509
34177c24 1510 if (encoder->type == INTEL_OUTPUT_HDMI) {
9e2c8475 1511 struct dpll best_clock;
34177c24
ACO		 1512
1513 /* Calculate HDMI div */
1514 /*
1515 * FIXME: tie the following calculation into
1516 * i9xx_crtc_compute_clock
1517 */
1518 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1519 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1520 clock, pipe_name(crtc->pipe));
1521 return NULL;
1522 }
1523
1524 clk_div.p1 = best_clock.p1;
1525 clk_div.p2 = best_clock.p2;
1526 WARN_ON(best_clock.m1 != 2);
1527 clk_div.n = best_clock.n;
1528 clk_div.m2_int = best_clock.m2 >> 22;
1529 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1530 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1531
1532 vco = best_clock.vco;
1533 } else if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1534 encoder->type == INTEL_OUTPUT_EDP) {
1535 int i;
1536
1537 clk_div = bxt_dp_clk_val[0];
1538 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1539 if (bxt_dp_clk_val[i].clock == clock) {
1540 clk_div = bxt_dp_clk_val[i];
1541 break;
1542 }
1543 }
1544 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1545 }
1546
1547 if (vco >= 6200000 && vco <= 6700000) {
1548 prop_coef = 4;
1549 int_coef = 9;
1550 gain_ctl = 3;
1551 targ_cnt = 8;
1552 } else if ((vco > 5400000 && vco < 6200000) ||
1553 (vco >= 4800000 && vco < 5400000)) {
1554 prop_coef = 5;
1555 int_coef = 11;
1556 gain_ctl = 3;
1557 targ_cnt = 9;
1558 } else if (vco == 5400000) {
1559 prop_coef = 3;
1560 int_coef = 8;
1561 gain_ctl = 1;
1562 targ_cnt = 9;
1563 } else {
1564 DRM_ERROR("Invalid VCO\n");
f9476a6c 1565 return NULL;
34177c24
ACO		 1566 }
1567
1568 memset(&crtc_state->dpll_hw_state, 0,
1569 sizeof(crtc_state->dpll_hw_state));
1570
1571 if (clock > 270000)
1572 lanestagger = 0x18;
1573 else if (clock > 135000)
1574 lanestagger = 0x0d;
1575 else if (clock > 67000)
1576 lanestagger = 0x07;
1577 else if (clock > 33000)
1578 lanestagger = 0x04;
1579 else
1580 lanestagger = 0x02;
1581
1582 crtc_state->dpll_hw_state.ebb0 =
1583 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1584 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1585 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1586 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1587
1588 if (clk_div.m2_frac_en)
1589 crtc_state->dpll_hw_state.pll3 =
1590 PORT_PLL_M2_FRAC_ENABLE;
1591
1592 crtc_state->dpll_hw_state.pll6 =
1593 prop_coef | PORT_PLL_INT_COEFF(int_coef);
1594 crtc_state->dpll_hw_state.pll6 |=
1595 PORT_PLL_GAIN_CTL(gain_ctl);
1596
1597 crtc_state->dpll_hw_state.pll8 = targ_cnt;
1598
1599 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
1600
1601 crtc_state->dpll_hw_state.pll10 =
1602 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1603 | PORT_PLL_DCO_AMP_OVR_EN_H;
1604
1605 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1606
1607 crtc_state->dpll_hw_state.pcsdw12 =
1608 LANESTAGGER_STRAP_OVRD | lanestagger;
f9476a6c
ACO		 1609
1610 intel_dig_port = enc_to_dig_port(&encoder->base);
34177c24 1611
f9476a6c 1612 /* 1:1 mapping between ports and PLLs */
34177c24
ACO		 1613 i = (enum intel_dpll_id) intel_dig_port->port;
1614 pll = intel_get_shared_dpll_by_id(dev_priv, i);
1615
78108b7c
VS		 1616 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
1617 crtc->base.base.id, crtc->base.name, pll->name);
f9476a6c
ACO		 1618
1619 intel_reference_shared_dpll(pll, crtc_state);
1620
34177c24
ACO		 1621 /* shared DPLL id 0 is DPLL A */
1622 crtc_state->ddi_pll_sel = pll->id;
1623
f9476a6c
ACO		 1624 return pll;
1625}
1626
2edd6443
ACO		 1627static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
1628 .enable = bxt_ddi_pll_enable,
1629 .disable = bxt_ddi_pll_disable,
1630 .get_hw_state = bxt_ddi_pll_get_hw_state,
1631};
55be2f08
ACO		 1632
1633static void intel_ddi_pll_init(struct drm_device *dev)
1634{
1635 struct drm_i915_private *dev_priv = dev->dev_private;
55be2f08 1636
9f7eb31a
VS		 1637 if (INTEL_GEN(dev_priv) < 9) {
1638 uint32_t val = I915_READ(LCPLL_CTL);
b2045352 1639
55be2f08
ACO		 1640 /*
1641 * The LCPLL register should be turned on by the BIOS. For now
1642 * let's just check its state and print errors in case
1643 * something is wrong. Don't even try to turn it on.
1644 */
1645
1646 if (val & LCPLL_CD_SOURCE_FCLK)
1647 DRM_ERROR("CDCLK source is not LCPLL\n");
1648
1649 if (val & LCPLL_PLL_DISABLE)
1650 DRM_ERROR("LCPLL is disabled\n");
1651 }
1652}
1653
2edd6443
ACO		 1654struct dpll_info {
1655 const char *name;
1656 const int id;
1657 const struct intel_shared_dpll_funcs *funcs;
9d16da65 1658 uint32_t flags;
2edd6443
ACO		 1659};
1660
f9476a6c
ACO		 1661struct intel_dpll_mgr {
1662 const struct dpll_info *dpll_info;
1663
1664 struct intel_shared_dpll *(*get_dpll)(struct intel_crtc *crtc,
daedf20a
ACO		 1665 struct intel_crtc_state *crtc_state,
1666 struct intel_encoder *encoder);
f9476a6c
ACO		 1667};
1668
2edd6443 1669static const struct dpll_info pch_plls[] = {
9d16da65
ACO		 1670 { "PCH DPLL A", DPLL_ID_PCH_PLL_A, &ibx_pch_dpll_funcs, 0 },
1671 { "PCH DPLL B", DPLL_ID_PCH_PLL_B, &ibx_pch_dpll_funcs, 0 },
1672 { NULL, -1, NULL, 0 },
2edd6443
ACO		 1673};
1674
f9476a6c
ACO		 1675static const struct intel_dpll_mgr pch_pll_mgr = {
1676 .dpll_info = pch_plls,
1677 .get_dpll = ibx_get_dpll,
1678};
1679
2edd6443 1680static const struct dpll_info hsw_plls[] = {
9d16da65
ACO		 1681 { "WRPLL 1", DPLL_ID_WRPLL1, &hsw_ddi_wrpll_funcs, 0 },
1682 { "WRPLL 2", DPLL_ID_WRPLL2, &hsw_ddi_wrpll_funcs, 0 },
1683 { "SPLL", DPLL_ID_SPLL, &hsw_ddi_spll_funcs, 0 },
1684 { "LCPLL 810", DPLL_ID_LCPLL_810, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
1685 { "LCPLL 1350", DPLL_ID_LCPLL_1350, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
1686 { "LCPLL 2700", DPLL_ID_LCPLL_2700, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
2edd6443
ACO		 1687 { NULL, -1, NULL, },
1688};
1689
f9476a6c
ACO		 1690static const struct intel_dpll_mgr hsw_pll_mgr = {
1691 .dpll_info = hsw_plls,
1692 .get_dpll = hsw_get_dpll,
1693};
1694
2edd6443 1695static const struct dpll_info skl_plls[] = {
a3c988ea 1696 { "DPLL 0", DPLL_ID_SKL_DPLL0, &skl_ddi_dpll0_funcs, INTEL_DPLL_ALWAYS_ON },
d5aab9d4
VS		 1697 { "DPLL 1", DPLL_ID_SKL_DPLL1, &skl_ddi_pll_funcs, 0 },
1698 { "DPLL 2", DPLL_ID_SKL_DPLL2, &skl_ddi_pll_funcs, 0 },
1699 { "DPLL 3", DPLL_ID_SKL_DPLL3, &skl_ddi_pll_funcs, 0 },
2edd6443
ACO		 1700 { NULL, -1, NULL, },
1701};
1702
f9476a6c
ACO		 1703static const struct intel_dpll_mgr skl_pll_mgr = {
1704 .dpll_info = skl_plls,
1705 .get_dpll = skl_get_dpll,
1706};
1707
2edd6443 1708static const struct dpll_info bxt_plls[] = {
08250c4b
ID		 1709 { "PORT PLL A", DPLL_ID_SKL_DPLL0, &bxt_ddi_pll_funcs, 0 },
1710 { "PORT PLL B", DPLL_ID_SKL_DPLL1, &bxt_ddi_pll_funcs, 0 },
1711 { "PORT PLL C", DPLL_ID_SKL_DPLL2, &bxt_ddi_pll_funcs, 0 },
2edd6443
ACO		 1712 { NULL, -1, NULL, },
1713};
1714
f9476a6c
ACO		 1715static const struct intel_dpll_mgr bxt_pll_mgr = {
1716 .dpll_info = bxt_plls,
1717 .get_dpll = bxt_get_dpll,
1718};
1719
7abd4b35
ACO		 1720void intel_shared_dpll_init(struct drm_device *dev)
1721{
1722 struct drm_i915_private *dev_priv = dev->dev_private;
f9476a6c
ACO		 1723 const struct intel_dpll_mgr *dpll_mgr = NULL;
1724 const struct dpll_info *dpll_info;
2edd6443 1725 int i;
7abd4b35 1726
2edd6443 1727 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
f9476a6c 1728 dpll_mgr = &skl_pll_mgr;
08250c4b 1729 else if (IS_BROXTON(dev))
f9476a6c 1730 dpll_mgr = &bxt_pll_mgr;
2edd6443 1731 else if (HAS_DDI(dev))
f9476a6c 1732 dpll_mgr = &hsw_pll_mgr;
7abd4b35 1733 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
f9476a6c 1734 dpll_mgr = &pch_pll_mgr;
2edd6443 1735
f9476a6c 1736 if (!dpll_mgr) {
7abd4b35 1737 dev_priv->num_shared_dpll = 0;
2edd6443
ACO		 1738 return;
1739 }
1740
f9476a6c
ACO		 1741 dpll_info = dpll_mgr->dpll_info;
1742
2edd6443
ACO		 1743 for (i = 0; dpll_info[i].id >= 0; i++) {
1744 WARN_ON(i != dpll_info[i].id);
1745
1746 dev_priv->shared_dplls[i].id = dpll_info[i].id;
1747 dev_priv->shared_dplls[i].name = dpll_info[i].name;
1748 dev_priv->shared_dplls[i].funcs = *dpll_info[i].funcs;
9d16da65 1749 dev_priv->shared_dplls[i].flags = dpll_info[i].flags;
2edd6443
ACO		 1750 }
1751
f9476a6c 1752 dev_priv->dpll_mgr = dpll_mgr;
2edd6443 1753 dev_priv->num_shared_dpll = i;
fbf6d879 1754 mutex_init(&dev_priv->dpll_lock);
7abd4b35
ACO		 1755
1756 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
2edd6443
ACO		 1757
1758 /* FIXME: Move this to a more suitable place */
1759 if (HAS_DDI(dev))
1760 intel_ddi_pll_init(dev);
7abd4b35 1761}
f9476a6c
ACO		 1762
1763struct intel_shared_dpll *
1764intel_get_shared_dpll(struct intel_crtc *crtc,
daedf20a
ACO		 1765 struct intel_crtc_state *crtc_state,
1766 struct intel_encoder *encoder)
f9476a6c
ACO		 1767{
1768 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1769 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
1770
1771 if (WARN_ON(!dpll_mgr))
1772 return NULL;
1773
daedf20a 1774 return dpll_mgr->get_dpll(crtc, crtc_state, encoder);
f9476a6c 1775}
ubuntu-bionic-kernel mirror