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drm/i915: Split skl_get_dpll()
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / i915 / intel_dpll_mgr.c
CommitLineData
7abd4b35
ACO		 1/*
2 * Copyright © 2006-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include "intel_drv.h"
25
26struct intel_shared_dpll *
8106ddbd
ACO		 27intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
28 enum intel_dpll_id id)
7abd4b35 29{
8106ddbd
ACO		 30 return &dev_priv->shared_dplls[id];
31}
7abd4b35 32
8106ddbd
ACO		 33enum intel_dpll_id
34intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
35 struct intel_shared_dpll *pll)
36{
37 if (WARN_ON(pll < dev_priv->shared_dplls||
38 pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll]))
39 return -1;
40
41 return (enum intel_dpll_id) (pll - dev_priv->shared_dplls);
42}
43
44void
45intel_shared_dpll_config_get(struct intel_shared_dpll_config *config,
46 struct intel_shared_dpll *pll,
47 struct intel_crtc *crtc)
48{
49 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
50 enum intel_dpll_id id = intel_get_shared_dpll_id(dev_priv, pll);
51
52 config[id].crtc_mask |= 1 << crtc->pipe;
53}
54
55void
56intel_shared_dpll_config_put(struct intel_shared_dpll_config *config,
57 struct intel_shared_dpll *pll,
58 struct intel_crtc *crtc)
59{
60 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
61 enum intel_dpll_id id = intel_get_shared_dpll_id(dev_priv, pll);
7abd4b35 62
8106ddbd 63 config[id].crtc_mask &= ~(1 << crtc->pipe);
7abd4b35
ACO		 64}
65
66/* For ILK+ */
67void assert_shared_dpll(struct drm_i915_private *dev_priv,
68 struct intel_shared_dpll *pll,
69 bool state)
70{
71 bool cur_state;
72 struct intel_dpll_hw_state hw_state;
73
74 if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
75 return;
76
2edd6443 77 cur_state = pll->funcs.get_hw_state(dev_priv, pll, &hw_state);
7abd4b35
ACO		 78 I915_STATE_WARN(cur_state != state,
79 "%s assertion failure (expected %s, current %s)\n",
80 pll->name, onoff(state), onoff(cur_state));
81}
82
83void intel_prepare_shared_dpll(struct intel_crtc *crtc)
84{
85 struct drm_device *dev = crtc->base.dev;
fac5e23e 86 struct drm_i915_private *dev_priv = to_i915(dev);
8106ddbd 87 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
7abd4b35
ACO		 88
89 if (WARN_ON(pll == NULL))
90 return;
91
fbf6d879 92 mutex_lock(&dev_priv->dpll_lock);
7abd4b35 93 WARN_ON(!pll->config.crtc_mask);
fbf6d879 94 if (!pll->active_mask) {
7abd4b35
ACO		 95 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
96 WARN_ON(pll->on);
97 assert_shared_dpll_disabled(dev_priv, pll);
98
2edd6443 99 pll->funcs.mode_set(dev_priv, pll);
7abd4b35 100 }
fbf6d879 101 mutex_unlock(&dev_priv->dpll_lock);
7abd4b35
ACO		 102}
103
104/**
105 * intel_enable_shared_dpll - enable PCH PLL
106 * @dev_priv: i915 private structure
107 * @pipe: pipe PLL to enable
108 *
109 * The PCH PLL needs to be enabled before the PCH transcoder, since it
110 * drives the transcoder clock.
111 */
112void intel_enable_shared_dpll(struct intel_crtc *crtc)
113{
114 struct drm_device *dev = crtc->base.dev;
fac5e23e 115 struct drm_i915_private *dev_priv = to_i915(dev);
8106ddbd 116 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
2dd66ebd 117 unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);
fbf6d879 118 unsigned old_mask;
7abd4b35
ACO		 119
120 if (WARN_ON(pll == NULL))
121 return;
122
fbf6d879
ML		 123 mutex_lock(&dev_priv->dpll_lock);
124 old_mask = pll->active_mask;
125
2dd66ebd
ML		 126 if (WARN_ON(!(pll->config.crtc_mask & crtc_mask)) ||
127 WARN_ON(pll->active_mask & crtc_mask))
fbf6d879 128 goto out;
7abd4b35 129
2dd66ebd
ML		 130 pll->active_mask |= crtc_mask;
131
132 DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n",
133 pll->name, pll->active_mask, pll->on,
7abd4b35
ACO		 134 crtc->base.base.id);
135
2dd66ebd 136 if (old_mask) {
7abd4b35
ACO		 137 WARN_ON(!pll->on);
138 assert_shared_dpll_enabled(dev_priv, pll);
fbf6d879 139 goto out;
7abd4b35
ACO		 140 }
141 WARN_ON(pll->on);
142
7abd4b35 143 DRM_DEBUG_KMS("enabling %s\n", pll->name);
2edd6443 144 pll->funcs.enable(dev_priv, pll);
7abd4b35 145 pll->on = true;
fbf6d879
ML		 146
147out:
148 mutex_unlock(&dev_priv->dpll_lock);
7abd4b35
ACO		 149}
150
151void intel_disable_shared_dpll(struct intel_crtc *crtc)
152{
153 struct drm_device *dev = crtc->base.dev;
fac5e23e 154 struct drm_i915_private *dev_priv = to_i915(dev);
8106ddbd 155 struct intel_shared_dpll *pll = crtc->config->shared_dpll;
2dd66ebd 156 unsigned crtc_mask = 1 << drm_crtc_index(&crtc->base);
7abd4b35
ACO		 157
158 /* PCH only available on ILK+ */
159 if (INTEL_INFO(dev)->gen < 5)
160 return;
161
162 if (pll == NULL)
163 return;
164
fbf6d879 165 mutex_lock(&dev_priv->dpll_lock);
a1475e77 166 if (WARN_ON(!(pll->active_mask & crtc_mask)))
fbf6d879 167 goto out;
7abd4b35 168
2dd66ebd
ML		 169 DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n",
170 pll->name, pll->active_mask, pll->on,
7abd4b35
ACO		 171 crtc->base.base.id);
172
7abd4b35
ACO		 173 assert_shared_dpll_enabled(dev_priv, pll);
174 WARN_ON(!pll->on);
2dd66ebd
ML		 175
176 pll->active_mask &= ~crtc_mask;
177 if (pll->active_mask)
fbf6d879 178 goto out;
7abd4b35
ACO		 179
180 DRM_DEBUG_KMS("disabling %s\n", pll->name);
2edd6443 181 pll->funcs.disable(dev_priv, pll);
7abd4b35 182 pll->on = false;
fbf6d879
ML		 183
184out:
185 mutex_unlock(&dev_priv->dpll_lock);
7abd4b35
ACO		 186}
187
f9476a6c 188static struct intel_shared_dpll *
a4780b77 189intel_find_shared_dpll(struct intel_crtc *crtc,
f9476a6c
ACO		 190 struct intel_crtc_state *crtc_state,
191 enum intel_dpll_id range_min,
192 enum intel_dpll_id range_max)
a4780b77 193{
fac5e23e 194 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
a4780b77
ACO		 195 struct intel_shared_dpll *pll;
196 struct intel_shared_dpll_config *shared_dpll;
197 enum intel_dpll_id i;
7abd4b35 198
a4780b77
ACO		 199 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
200
f9476a6c 201 for (i = range_min; i <= range_max; i++) {
7abd4b35
ACO		 202 pll = &dev_priv->shared_dplls[i];
203
204 /* Only want to check enabled timings first */
205 if (shared_dpll[i].crtc_mask == 0)
206 continue;
207
208 if (memcmp(&crtc_state->dpll_hw_state,
209 &shared_dpll[i].hw_state,
210 sizeof(crtc_state->dpll_hw_state)) == 0) {
78108b7c
VS		 211 DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n",
212 crtc->base.base.id, crtc->base.name, pll->name,
7abd4b35 213 shared_dpll[i].crtc_mask,
2dd66ebd 214 pll->active_mask);
f9476a6c 215 return pll;
7abd4b35
ACO		 216 }
217 }
218
219 /* Ok no matching timings, maybe there's a free one? */
f9476a6c 220 for (i = range_min; i <= range_max; i++) {
7abd4b35
ACO		 221 pll = &dev_priv->shared_dplls[i];
222 if (shared_dpll[i].crtc_mask == 0) {
78108b7c
VS		 223 DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n",
224 crtc->base.base.id, crtc->base.name, pll->name);
f9476a6c 225 return pll;
7abd4b35
ACO		 226 }
227 }
228
f9476a6c 229 return NULL;
a4780b77
ACO		 230}
231
f9476a6c
ACO		 232static void
233intel_reference_shared_dpll(struct intel_shared_dpll *pll,
234 struct intel_crtc_state *crtc_state)
a4780b77 235{
a4780b77 236 struct intel_shared_dpll_config *shared_dpll;
f9476a6c
ACO		 237 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
238 enum intel_dpll_id i = pll->id;
a4780b77
ACO		 239
240 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
241
7abd4b35
ACO		 242 if (shared_dpll[i].crtc_mask == 0)
243 shared_dpll[i].hw_state =
244 crtc_state->dpll_hw_state;
245
8106ddbd 246 crtc_state->shared_dpll = pll;
7abd4b35
ACO		 247 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
248 pipe_name(crtc->pipe));
249
8106ddbd 250 intel_shared_dpll_config_get(shared_dpll, pll, crtc);
7abd4b35
ACO		 251}
252
253void intel_shared_dpll_commit(struct drm_atomic_state *state)
254{
255 struct drm_i915_private *dev_priv = to_i915(state->dev);
256 struct intel_shared_dpll_config *shared_dpll;
257 struct intel_shared_dpll *pll;
258 enum intel_dpll_id i;
259
260 if (!to_intel_atomic_state(state)->dpll_set)
261 return;
262
263 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
264 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
265 pll = &dev_priv->shared_dplls[i];
266 pll->config = shared_dpll[i];
267 }
268}
269
270static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
271 struct intel_shared_dpll *pll,
272 struct intel_dpll_hw_state *hw_state)
273{
274 uint32_t val;
275
276 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
277 return false;
278
279 val = I915_READ(PCH_DPLL(pll->id));
280 hw_state->dpll = val;
281 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
282 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
283
284 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
285
286 return val & DPLL_VCO_ENABLE;
287}
288
289static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
290 struct intel_shared_dpll *pll)
291{
292 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
293 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
294}
295
296static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
297{
298 u32 val;
299 bool enabled;
300
2d1fe073 301 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7abd4b35
ACO		 302
303 val = I915_READ(PCH_DREF_CONTROL);
304 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
305 DREF_SUPERSPREAD_SOURCE_MASK));
306 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
307}
308
309static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
310 struct intel_shared_dpll *pll)
311{
312 /* PCH refclock must be enabled first */
313 ibx_assert_pch_refclk_enabled(dev_priv);
314
315 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
316
317 /* Wait for the clocks to stabilize. */
318 POSTING_READ(PCH_DPLL(pll->id));
319 udelay(150);
320
321 /* The pixel multiplier can only be updated once the
322 * DPLL is enabled and the clocks are stable.
323 *
324 * So write it again.
325 */
326 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
327 POSTING_READ(PCH_DPLL(pll->id));
328 udelay(200);
329}
330
331static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
332 struct intel_shared_dpll *pll)
333{
91c8a326 334 struct drm_device *dev = &dev_priv->drm;
7abd4b35
ACO		 335 struct intel_crtc *crtc;
336
337 /* Make sure no transcoder isn't still depending on us. */
338 for_each_intel_crtc(dev, crtc) {
8106ddbd 339 if (crtc->config->shared_dpll == pll)
7abd4b35
ACO		 340 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
341 }
342
343 I915_WRITE(PCH_DPLL(pll->id), 0);
344 POSTING_READ(PCH_DPLL(pll->id));
345 udelay(200);
346}
347
f9476a6c 348static struct intel_shared_dpll *
daedf20a
ACO		 349ibx_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
350 struct intel_encoder *encoder)
f9476a6c
ACO		 351{
352 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
353 struct intel_shared_dpll *pll;
354 enum intel_dpll_id i;
355
356 if (HAS_PCH_IBX(dev_priv)) {
357 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
358 i = (enum intel_dpll_id) crtc->pipe;
359 pll = &dev_priv->shared_dplls[i];
360
78108b7c
VS		 361 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
362 crtc->base.base.id, crtc->base.name, pll->name);
f9476a6c
ACO		 363 } else {
364 pll = intel_find_shared_dpll(crtc, crtc_state,
365 DPLL_ID_PCH_PLL_A,
366 DPLL_ID_PCH_PLL_B);
367 }
368
bb143165
ACO		 369 if (!pll)
370 return NULL;
371
f9476a6c
ACO		 372 /* reference the pll */
373 intel_reference_shared_dpll(pll, crtc_state);
374
375 return pll;
376}
377
2edd6443
ACO		 378static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
379 .mode_set = ibx_pch_dpll_mode_set,
380 .enable = ibx_pch_dpll_enable,
381 .disable = ibx_pch_dpll_disable,
382 .get_hw_state = ibx_pch_dpll_get_hw_state,
7abd4b35
ACO		 383};
384
55be2f08
ACO		 385static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
386 struct intel_shared_dpll *pll)
387{
388 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
389 POSTING_READ(WRPLL_CTL(pll->id));
390 udelay(20);
391}
392
393static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
394 struct intel_shared_dpll *pll)
395{
396 I915_WRITE(SPLL_CTL, pll->config.hw_state.spll);
397 POSTING_READ(SPLL_CTL);
398 udelay(20);
399}
400
401static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
402 struct intel_shared_dpll *pll)
403{
404 uint32_t val;
405
406 val = I915_READ(WRPLL_CTL(pll->id));
407 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
408 POSTING_READ(WRPLL_CTL(pll->id));
409}
410
411static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
412 struct intel_shared_dpll *pll)
413{
414 uint32_t val;
415
416 val = I915_READ(SPLL_CTL);
417 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE);
418 POSTING_READ(SPLL_CTL);
419}
420
421static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
422 struct intel_shared_dpll *pll,
423 struct intel_dpll_hw_state *hw_state)
424{
425 uint32_t val;
426
427 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
428 return false;
429
430 val = I915_READ(WRPLL_CTL(pll->id));
431 hw_state->wrpll = val;
432
433 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
434
435 return val & WRPLL_PLL_ENABLE;
436}
437
438static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
439 struct intel_shared_dpll *pll,
440 struct intel_dpll_hw_state *hw_state)
441{
442 uint32_t val;
443
444 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
445 return false;
446
447 val = I915_READ(SPLL_CTL);
448 hw_state->spll = val;
449
450 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
451
452 return val & SPLL_PLL_ENABLE;
453}
454
daedf20a
ACO		 455#define LC_FREQ 2700
456#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
457
458#define P_MIN 2
459#define P_MAX 64
460#define P_INC 2
461
462/* Constraints for PLL good behavior */
463#define REF_MIN 48
464#define REF_MAX 400
465#define VCO_MIN 2400
466#define VCO_MAX 4800
467
468struct hsw_wrpll_rnp {
469 unsigned p, n2, r2;
470};
471
472static unsigned hsw_wrpll_get_budget_for_freq(int clock)
473{
474 unsigned budget;
475
476 switch (clock) {
477 case 25175000:
478 case 25200000:
479 case 27000000:
480 case 27027000:
481 case 37762500:
482 case 37800000:
483 case 40500000:
484 case 40541000:
485 case 54000000:
486 case 54054000:
487 case 59341000:
488 case 59400000:
489 case 72000000:
490 case 74176000:
491 case 74250000:
492 case 81000000:
493 case 81081000:
494 case 89012000:
495 case 89100000:
496 case 108000000:
497 case 108108000:
498 case 111264000:
499 case 111375000:
500 case 148352000:
501 case 148500000:
502 case 162000000:
503 case 162162000:
504 case 222525000:
505 case 222750000:
506 case 296703000:
507 case 297000000:
508 budget = 0;
509 break;
510 case 233500000:
511 case 245250000:
512 case 247750000:
513 case 253250000:
514 case 298000000:
515 budget = 1500;
516 break;
517 case 169128000:
518 case 169500000:
519 case 179500000:
520 case 202000000:
521 budget = 2000;
522 break;
523 case 256250000:
524 case 262500000:
525 case 270000000:
526 case 272500000:
527 case 273750000:
528 case 280750000:
529 case 281250000:
530 case 286000000:
531 case 291750000:
532 budget = 4000;
533 break;
534 case 267250000:
535 case 268500000:
536 budget = 5000;
537 break;
538 default:
539 budget = 1000;
540 break;
541 }
542
543 return budget;
544}
545
546static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
547 unsigned r2, unsigned n2, unsigned p,
548 struct hsw_wrpll_rnp *best)
549{
550 uint64_t a, b, c, d, diff, diff_best;
551
552 /* No best (r,n,p) yet */
553 if (best->p == 0) {
554 best->p = p;
555 best->n2 = n2;
556 best->r2 = r2;
557 return;
558 }
559
560 /*
561 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
562 * freq2k.
563 *
564 * delta = 1e6 *
565 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
566 * freq2k;
567 *
568 * and we would like delta <= budget.
569 *
570 * If the discrepancy is above the PPM-based budget, always prefer to
571 * improve upon the previous solution. However, if you're within the
572 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
573 */
574 a = freq2k * budget * p * r2;
575 b = freq2k * budget * best->p * best->r2;
576 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
577 diff_best = abs_diff(freq2k * best->p * best->r2,
578 LC_FREQ_2K * best->n2);
579 c = 1000000 * diff;
580 d = 1000000 * diff_best;
581
582 if (a < c && b < d) {
583 /* If both are above the budget, pick the closer */
584 if (best->p * best->r2 * diff < p * r2 * diff_best) {
585 best->p = p;
586 best->n2 = n2;
587 best->r2 = r2;
588 }
589 } else if (a >= c && b < d) {
590 /* If A is below the threshold but B is above it? Update. */
591 best->p = p;
592 best->n2 = n2;
593 best->r2 = r2;
594 } else if (a >= c && b >= d) {
595 /* Both are below the limit, so pick the higher n2/(r2*r2) */
596 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
597 best->p = p;
598 best->n2 = n2;
599 best->r2 = r2;
600 }
601 }
602 /* Otherwise a < c && b >= d, do nothing */
603}
604
605static void
606hsw_ddi_calculate_wrpll(int clock /* in Hz */,
607 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
608{
609 uint64_t freq2k;
610 unsigned p, n2, r2;
611 struct hsw_wrpll_rnp best = { 0, 0, 0 };
612 unsigned budget;
613
614 freq2k = clock / 100;
615
616 budget = hsw_wrpll_get_budget_for_freq(clock);
617
618 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
619 * and directly pass the LC PLL to it. */
620 if (freq2k == 5400000) {
621 *n2_out = 2;
622 *p_out = 1;
623 *r2_out = 2;
624 return;
625 }
626
627 /*
628 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
629 * the WR PLL.
630 *
631 * We want R so that REF_MIN <= Ref <= REF_MAX.
632 * Injecting R2 = 2 * R gives:
633 * REF_MAX * r2 > LC_FREQ * 2 and
634 * REF_MIN * r2 < LC_FREQ * 2
635 *
636 * Which means the desired boundaries for r2 are:
637 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
638 *
639 */
640 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
641 r2 <= LC_FREQ * 2 / REF_MIN;
642 r2++) {
643
644 /*
645 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
646 *
647 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
648 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
649 * VCO_MAX * r2 > n2 * LC_FREQ and
650 * VCO_MIN * r2 < n2 * LC_FREQ)
651 *
652 * Which means the desired boundaries for n2 are:
653 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
654 */
655 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
656 n2 <= VCO_MAX * r2 / LC_FREQ;
657 n2++) {
658
659 for (p = P_MIN; p <= P_MAX; p += P_INC)
660 hsw_wrpll_update_rnp(freq2k, budget,
661 r2, n2, p, &best);
662 }
663 }
664
665 *n2_out = best.n2;
666 *p_out = best.p;
667 *r2_out = best.r2;
668}
669
f9476a6c 670static struct intel_shared_dpll *
daedf20a
ACO		 671hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
672 struct intel_encoder *encoder)
f9476a6c 673{
9d16da65 674 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
f9476a6c 675 struct intel_shared_dpll *pll;
daedf20a 676 int clock = crtc_state->port_clock;
f9476a6c 677
9d16da65
ACO		 678 memset(&crtc_state->dpll_hw_state, 0,
679 sizeof(crtc_state->dpll_hw_state));
680
daedf20a
ACO		 681 if (encoder->type == INTEL_OUTPUT_HDMI) {
682 uint32_t val;
683 unsigned p, n2, r2;
684
685 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
686
687 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
688 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
689 WRPLL_DIVIDER_POST(p);
690
daedf20a
ACO		 691 crtc_state->dpll_hw_state.wrpll = val;
692
693 pll = intel_find_shared_dpll(crtc, crtc_state,
694 DPLL_ID_WRPLL1, DPLL_ID_WRPLL2);
695
cca0502b 696 } else if (encoder->type == INTEL_OUTPUT_DP ||
9d16da65
ACO		 697 encoder->type == INTEL_OUTPUT_DP_MST ||
698 encoder->type == INTEL_OUTPUT_EDP) {
699 enum intel_dpll_id pll_id;
700
701 switch (clock / 2) {
702 case 81000:
703 pll_id = DPLL_ID_LCPLL_810;
704 break;
705 case 135000:
706 pll_id = DPLL_ID_LCPLL_1350;
707 break;
708 case 270000:
709 pll_id = DPLL_ID_LCPLL_2700;
710 break;
711 default:
712 DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock);
713 return NULL;
714 }
715
716 pll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
717
daedf20a
ACO		 718 } else if (encoder->type == INTEL_OUTPUT_ANALOG) {
719 if (WARN_ON(crtc_state->port_clock / 2 != 135000))
720 return NULL;
721
daedf20a
ACO		 722 crtc_state->dpll_hw_state.spll =
723 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
724
725 pll = intel_find_shared_dpll(crtc, crtc_state,
726 DPLL_ID_SPLL, DPLL_ID_SPLL);
727 } else {
728 return NULL;
729 }
730
731 if (!pll)
732 return NULL;
733
daedf20a 734 intel_reference_shared_dpll(pll, crtc_state);
f9476a6c
ACO		 735
736 return pll;
737}
738
55be2f08 739
2edd6443
ACO		 740static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
741 .enable = hsw_ddi_wrpll_enable,
742 .disable = hsw_ddi_wrpll_disable,
743 .get_hw_state = hsw_ddi_wrpll_get_hw_state,
55be2f08
ACO		 744};
745
2edd6443
ACO		 746static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
747 .enable = hsw_ddi_spll_enable,
748 .disable = hsw_ddi_spll_disable,
749 .get_hw_state = hsw_ddi_spll_get_hw_state,
55be2f08
ACO		 750};
751
9d16da65
ACO		 752static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
753 struct intel_shared_dpll *pll)
754{
755}
756
757static void hsw_ddi_lcpll_disable(struct drm_i915_private *dev_priv,
758 struct intel_shared_dpll *pll)
759{
760}
761
762static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv,
763 struct intel_shared_dpll *pll,
764 struct intel_dpll_hw_state *hw_state)
765{
766 return true;
767}
768
769static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
770 .enable = hsw_ddi_lcpll_enable,
771 .disable = hsw_ddi_lcpll_disable,
772 .get_hw_state = hsw_ddi_lcpll_get_hw_state,
773};
774
55be2f08
ACO		 775struct skl_dpll_regs {
776 i915_reg_t ctl, cfgcr1, cfgcr2;
777};
778
779/* this array is indexed by the *shared* pll id */
a3c988ea
ACO		 780static const struct skl_dpll_regs skl_dpll_regs[4] = {
781 {
782 /* DPLL 0 */
783 .ctl = LCPLL1_CTL,
784 /* DPLL 0 doesn't support HDMI mode */
785 },
55be2f08
ACO		 786 {
787 /* DPLL 1 */
788 .ctl = LCPLL2_CTL,
789 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
790 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
791 },
792 {
793 /* DPLL 2 */
794 .ctl = WRPLL_CTL(0),
795 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
796 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
797 },
798 {
799 /* DPLL 3 */
800 .ctl = WRPLL_CTL(1),
801 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
802 .cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
803 },
804};
805
a3c988ea
ACO		 806static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
807 struct intel_shared_dpll *pll)
55be2f08
ACO		 808{
809 uint32_t val;
55be2f08
ACO		 810
811 val = I915_READ(DPLL_CTRL1);
812
a3c988ea
ACO		 813 val &= ~(DPLL_CTRL1_HDMI_MODE(pll->id) | DPLL_CTRL1_SSC(pll->id) |
814 DPLL_CTRL1_LINK_RATE_MASK(pll->id));
815 val |= pll->config.hw_state.ctrl1 << (pll->id * 6);
55be2f08
ACO		 816
817 I915_WRITE(DPLL_CTRL1, val);
818 POSTING_READ(DPLL_CTRL1);
a3c988ea
ACO		 819}
820
821static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
822 struct intel_shared_dpll *pll)
823{
824 const struct skl_dpll_regs *regs = skl_dpll_regs;
825
826 skl_ddi_pll_write_ctrl1(dev_priv, pll);
55be2f08
ACO		 827
828 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
829 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
830 POSTING_READ(regs[pll->id].cfgcr1);
831 POSTING_READ(regs[pll->id].cfgcr2);
832
833 /* the enable bit is always bit 31 */
834 I915_WRITE(regs[pll->id].ctl,
835 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
836
27bf23a9
CW		 837 if (intel_wait_for_register(dev_priv,
838 DPLL_STATUS,
839 DPLL_LOCK(pll->id),
840 DPLL_LOCK(pll->id),
841 5))
a3c988ea
ACO		 842 DRM_ERROR("DPLL %d not locked\n", pll->id);
843}
844
845static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv,
846 struct intel_shared_dpll *pll)
847{
848 skl_ddi_pll_write_ctrl1(dev_priv, pll);
55be2f08
ACO		 849}
850
851static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
852 struct intel_shared_dpll *pll)
853{
854 const struct skl_dpll_regs *regs = skl_dpll_regs;
855
856 /* the enable bit is always bit 31 */
857 I915_WRITE(regs[pll->id].ctl,
858 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
859 POSTING_READ(regs[pll->id].ctl);
860}
861
a3c988ea
ACO		 862static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv,
863 struct intel_shared_dpll *pll)
864{
865}
866
55be2f08
ACO		 867static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
868 struct intel_shared_dpll *pll,
869 struct intel_dpll_hw_state *hw_state)
870{
871 uint32_t val;
55be2f08
ACO		 872 const struct skl_dpll_regs *regs = skl_dpll_regs;
873 bool ret;
874
875 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
876 return false;
877
878 ret = false;
879
55be2f08
ACO		 880 val = I915_READ(regs[pll->id].ctl);
881 if (!(val & LCPLL_PLL_ENABLE))
882 goto out;
883
884 val = I915_READ(DPLL_CTRL1);
a3c988ea 885 hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f;
55be2f08
ACO		 886
887 /* avoid reading back stale values if HDMI mode is not enabled */
a3c988ea 888 if (val & DPLL_CTRL1_HDMI_MODE(pll->id)) {
55be2f08
ACO		 889 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
890 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
891 }
892 ret = true;
893
894out:
895 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
896
897 return ret;
898}
899
a3c988ea
ACO		 900static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
901 struct intel_shared_dpll *pll,
902 struct intel_dpll_hw_state *hw_state)
903{
904 uint32_t val;
905 const struct skl_dpll_regs *regs = skl_dpll_regs;
906 bool ret;
907
908 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
909 return false;
910
911 ret = false;
912
913 /* DPLL0 is always enabled since it drives CDCLK */
914 val = I915_READ(regs[pll->id].ctl);
915 if (WARN_ON(!(val & LCPLL_PLL_ENABLE)))
916 goto out;
917
918 val = I915_READ(DPLL_CTRL1);
919 hw_state->ctrl1 = (val >> (pll->id * 6)) & 0x3f;
920
921 ret = true;
922
923out:
924 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
925
926 return ret;
927}
928
304b65cb
ACO		 929struct skl_wrpll_context {
930 uint64_t min_deviation; /* current minimal deviation */
931 uint64_t central_freq; /* chosen central freq */
932 uint64_t dco_freq; /* chosen dco freq */
933 unsigned int p; /* chosen divider */
934};
935
936static void skl_wrpll_context_init(struct skl_wrpll_context *ctx)
937{
938 memset(ctx, 0, sizeof(*ctx));
939
940 ctx->min_deviation = U64_MAX;
941}
942
943/* DCO freq must be within +1%/-6% of the DCO central freq */
944#define SKL_DCO_MAX_PDEVIATION 100
945#define SKL_DCO_MAX_NDEVIATION 600
946
947static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
948 uint64_t central_freq,
949 uint64_t dco_freq,
950 unsigned int divider)
951{
952 uint64_t deviation;
953
954 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
955 central_freq);
956
957 /* positive deviation */
958 if (dco_freq >= central_freq) {
959 if (deviation < SKL_DCO_MAX_PDEVIATION &&
960 deviation < ctx->min_deviation) {
961 ctx->min_deviation = deviation;
962 ctx->central_freq = central_freq;
963 ctx->dco_freq = dco_freq;
964 ctx->p = divider;
965 }
966 /* negative deviation */
967 } else if (deviation < SKL_DCO_MAX_NDEVIATION &&
968 deviation < ctx->min_deviation) {
969 ctx->min_deviation = deviation;
970 ctx->central_freq = central_freq;
971 ctx->dco_freq = dco_freq;
972 ctx->p = divider;
973 }
974}
975
976static void skl_wrpll_get_multipliers(unsigned int p,
977 unsigned int *p0 /* out */,
978 unsigned int *p1 /* out */,
979 unsigned int *p2 /* out */)
980{
981 /* even dividers */
982 if (p % 2 == 0) {
983 unsigned int half = p / 2;
984
985 if (half == 1 || half == 2 || half == 3 || half == 5) {
986 *p0 = 2;
987 *p1 = 1;
988 *p2 = half;
989 } else if (half % 2 == 0) {
990 *p0 = 2;
991 *p1 = half / 2;
992 *p2 = 2;
993 } else if (half % 3 == 0) {
994 *p0 = 3;
995 *p1 = half / 3;
996 *p2 = 2;
997 } else if (half % 7 == 0) {
998 *p0 = 7;
999 *p1 = half / 7;
1000 *p2 = 2;
1001 }
1002 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */
1003 *p0 = 3;
1004 *p1 = 1;
1005 *p2 = p / 3;
1006 } else if (p == 5 || p == 7) {
1007 *p0 = p;
1008 *p1 = 1;
1009 *p2 = 1;
1010 } else if (p == 15) {
1011 *p0 = 3;
1012 *p1 = 1;
1013 *p2 = 5;
1014 } else if (p == 21) {
1015 *p0 = 7;
1016 *p1 = 1;
1017 *p2 = 3;
1018 } else if (p == 35) {
1019 *p0 = 7;
1020 *p1 = 1;
1021 *p2 = 5;
1022 }
1023}
1024
1025struct skl_wrpll_params {
1026 uint32_t dco_fraction;
1027 uint32_t dco_integer;
1028 uint32_t qdiv_ratio;
1029 uint32_t qdiv_mode;
1030 uint32_t kdiv;
1031 uint32_t pdiv;
1032 uint32_t central_freq;
1033};
1034
1035static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1036 uint64_t afe_clock,
1037 uint64_t central_freq,
1038 uint32_t p0, uint32_t p1, uint32_t p2)
1039{
1040 uint64_t dco_freq;
1041
1042 switch (central_freq) {
1043 case 9600000000ULL:
1044 params->central_freq = 0;
1045 break;
1046 case 9000000000ULL:
1047 params->central_freq = 1;
1048 break;
1049 case 8400000000ULL:
1050 params->central_freq = 3;
1051 }
1052
1053 switch (p0) {
1054 case 1:
1055 params->pdiv = 0;
1056 break;
1057 case 2:
1058 params->pdiv = 1;
1059 break;
1060 case 3:
1061 params->pdiv = 2;
1062 break;
1063 case 7:
1064 params->pdiv = 4;
1065 break;
1066 default:
1067 WARN(1, "Incorrect PDiv\n");
1068 }
1069
1070 switch (p2) {
1071 case 5:
1072 params->kdiv = 0;
1073 break;
1074 case 2:
1075 params->kdiv = 1;
1076 break;
1077 case 3:
1078 params->kdiv = 2;
1079 break;
1080 case 1:
1081 params->kdiv = 3;
1082 break;
1083 default:
1084 WARN(1, "Incorrect KDiv\n");
1085 }
1086
1087 params->qdiv_ratio = p1;
1088 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1089
1090 dco_freq = p0 * p1 * p2 * afe_clock;
1091
1092 /*
1093 * Intermediate values are in Hz.
1094 * Divide by MHz to match bsepc
1095 */
1096 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
1097 params->dco_fraction =
1098 div_u64((div_u64(dco_freq, 24) -
1099 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1100}
1101
1102static bool
1103skl_ddi_calculate_wrpll(int clock /* in Hz */,
1104 struct skl_wrpll_params *wrpll_params)
1105{
1106 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1107 uint64_t dco_central_freq[3] = {8400000000ULL,
1108 9000000000ULL,
1109 9600000000ULL};
1110 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20,
1111 24, 28, 30, 32, 36, 40, 42, 44,
1112 48, 52, 54, 56, 60, 64, 66, 68,
1113 70, 72, 76, 78, 80, 84, 88, 90,
1114 92, 96, 98 };
1115 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1116 static const struct {
1117 const int *list;
1118 int n_dividers;
1119 } dividers[] = {
1120 { even_dividers, ARRAY_SIZE(even_dividers) },
1121 { odd_dividers, ARRAY_SIZE(odd_dividers) },
1122 };
1123 struct skl_wrpll_context ctx;
1124 unsigned int dco, d, i;
1125 unsigned int p0, p1, p2;
1126
1127 skl_wrpll_context_init(&ctx);
1128
1129 for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1130 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1131 for (i = 0; i < dividers[d].n_dividers; i++) {
1132 unsigned int p = dividers[d].list[i];
1133 uint64_t dco_freq = p * afe_clock;
1134
1135 skl_wrpll_try_divider(&ctx,
1136 dco_central_freq[dco],
1137 dco_freq,
1138 p);
1139 /*
1140 * Skip the remaining dividers if we're sure to
1141 * have found the definitive divider, we can't
1142 * improve a 0 deviation.
1143 */
1144 if (ctx.min_deviation == 0)
1145 goto skip_remaining_dividers;
1146 }
1147 }
1148
1149skip_remaining_dividers:
1150 /*
1151 * If a solution is found with an even divider, prefer
1152 * this one.
1153 */
1154 if (d == 0 && ctx.p)
1155 break;
1156 }
1157
1158 if (!ctx.p) {
1159 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
1160 return false;
1161 }
1162
1163 /*
1164 * gcc incorrectly analyses that these can be used without being
1165 * initialized. To be fair, it's hard to guess.
1166 */
1167 p0 = p1 = p2 = 0;
1168 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1169 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq,
1170 p0, p1, p2);
1171
1172 return true;
1173}
1174
9a4edada
JB		 1175static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
1176 struct intel_crtc_state *crtc_state,
1177 int clock)
f9476a6c 1178{
304b65cb 1179 uint32_t ctrl1, cfgcr1, cfgcr2;
9a4edada 1180 struct skl_wrpll_params wrpll_params = { 0, };
304b65cb
ACO		 1181
1182 /*
1183 * See comment in intel_dpll_hw_state to understand why we always use 0
1184 * as the DPLL id in this function.
1185 */
304b65cb
ACO		 1186 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1187
9a4edada 1188 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
304b65cb 1189
9a4edada
JB		 1190 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1191 return false;
304b65cb 1192
9a4edada
JB		 1193 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1194 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1195 wrpll_params.dco_integer;
1196
1197 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1198 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1199 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1200 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1201 wrpll_params.central_freq;
1202
1203 memset(&crtc_state->dpll_hw_state, 0,
1204 sizeof(crtc_state->dpll_hw_state));
1205
1206 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1207 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1208 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1209 return true;
1210}
1211
1212
1213bool skl_ddi_dp_set_dpll_hw_state(int clock,
1214 struct intel_dpll_hw_state *dpll_hw_state)
1215{
1216 uint32_t ctrl1;
1217
1218 /*
1219 * See comment in intel_dpll_hw_state to understand why we always use 0
1220 * as the DPLL id in this function.
1221 */
1222 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1223 switch (clock / 2) {
1224 case 81000:
1225 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1226 break;
1227 case 135000:
1228 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1229 break;
1230 case 270000:
1231 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1232 break;
1233 /* eDP 1.4 rates */
1234 case 162000:
1235 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
1236 break;
1237 case 108000:
1238 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
1239 break;
1240 case 216000:
1241 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
1242 break;
1243 }
304b65cb 1244
9a4edada
JB		 1245 dpll_hw_state->ctrl1 = ctrl1;
1246 return true;
1247}
304b65cb 1248
9a4edada
JB		 1249static struct intel_shared_dpll *
1250skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1251 struct intel_encoder *encoder)
1252{
1253 struct intel_shared_dpll *pll;
1254 int clock = crtc_state->port_clock;
1255 bool bret;
1256 struct intel_dpll_hw_state dpll_hw_state;
1257
1258 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
1259
1260 if (encoder->type == INTEL_OUTPUT_HDMI) {
1261 bret = skl_ddi_hdmi_pll_dividers(crtc, crtc_state, clock);
1262 if (!bret) {
1263 DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n");
1264 return NULL;
1265 }
cca0502b 1266 } else if (encoder->type == INTEL_OUTPUT_DP ||
a3c988ea
ACO		 1267 encoder->type == INTEL_OUTPUT_DP_MST ||
1268 encoder->type == INTEL_OUTPUT_EDP) {
9a4edada
JB		 1269 bret = skl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state);
1270 if (!bret) {
1271 DRM_DEBUG_KMS("Could not set DP dpll HW state.\n");
1272 return NULL;
304b65cb 1273 }
9a4edada 1274 crtc_state->dpll_hw_state = dpll_hw_state;
304b65cb
ACO		 1275 } else {
1276 return NULL;
1277 }
1278
a3c988ea
ACO		 1279 if (encoder->type == INTEL_OUTPUT_EDP)
1280 pll = intel_find_shared_dpll(crtc, crtc_state,
1281 DPLL_ID_SKL_DPLL0,
1282 DPLL_ID_SKL_DPLL0);
1283 else
1284 pll = intel_find_shared_dpll(crtc, crtc_state,
1285 DPLL_ID_SKL_DPLL1,
1286 DPLL_ID_SKL_DPLL3);
304b65cb
ACO		 1287 if (!pll)
1288 return NULL;
1289
304b65cb 1290 intel_reference_shared_dpll(pll, crtc_state);
f9476a6c
ACO		 1291
1292 return pll;
1293}
1294
2edd6443
ACO		 1295static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
1296 .enable = skl_ddi_pll_enable,
1297 .disable = skl_ddi_pll_disable,
1298 .get_hw_state = skl_ddi_pll_get_hw_state,
55be2f08
ACO		 1299};
1300
a3c988ea
ACO		 1301static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
1302 .enable = skl_ddi_dpll0_enable,
1303 .disable = skl_ddi_dpll0_disable,
1304 .get_hw_state = skl_ddi_dpll0_get_hw_state,
1305};
1306
55be2f08
ACO		 1307static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
1308 struct intel_shared_dpll *pll)
1309{
1310 uint32_t temp;
1311 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
1312
55be2f08 1313 /* Non-SSC reference */
da6110bc
DK		 1314 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1315 temp |= PORT_PLL_REF_SEL;
55be2f08
ACO		 1316 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1317
1318 /* Disable 10 bit clock */
1319 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
1320 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1321 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
1322
1323 /* Write P1 & P2 */
1324 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
1325 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
1326 temp |= pll->config.hw_state.ebb0;
1327 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
1328
1329 /* Write M2 integer */
1330 temp = I915_READ(BXT_PORT_PLL(port, 0));
1331 temp &= ~PORT_PLL_M2_MASK;
1332 temp |= pll->config.hw_state.pll0;
1333 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
1334
1335 /* Write N */
1336 temp = I915_READ(BXT_PORT_PLL(port, 1));
1337 temp &= ~PORT_PLL_N_MASK;
1338 temp |= pll->config.hw_state.pll1;
1339 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
1340
1341 /* Write M2 fraction */
1342 temp = I915_READ(BXT_PORT_PLL(port, 2));
1343 temp &= ~PORT_PLL_M2_FRAC_MASK;
1344 temp |= pll->config.hw_state.pll2;
1345 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
1346
1347 /* Write M2 fraction enable */
1348 temp = I915_READ(BXT_PORT_PLL(port, 3));
1349 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
1350 temp |= pll->config.hw_state.pll3;
1351 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
1352
1353 /* Write coeff */
1354 temp = I915_READ(BXT_PORT_PLL(port, 6));
1355 temp &= ~PORT_PLL_PROP_COEFF_MASK;
1356 temp &= ~PORT_PLL_INT_COEFF_MASK;
1357 temp &= ~PORT_PLL_GAIN_CTL_MASK;
1358 temp |= pll->config.hw_state.pll6;
1359 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
1360
1361 /* Write calibration val */
1362 temp = I915_READ(BXT_PORT_PLL(port, 8));
1363 temp &= ~PORT_PLL_TARGET_CNT_MASK;
1364 temp |= pll->config.hw_state.pll8;
1365 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
1366
1367 temp = I915_READ(BXT_PORT_PLL(port, 9));
1368 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
1369 temp |= pll->config.hw_state.pll9;
1370 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
1371
1372 temp = I915_READ(BXT_PORT_PLL(port, 10));
1373 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
1374 temp &= ~PORT_PLL_DCO_AMP_MASK;
1375 temp |= pll->config.hw_state.pll10;
1376 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
1377
1378 /* Recalibrate with new settings */
1379 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
1380 temp |= PORT_PLL_RECALIBRATE;
1381 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
1382 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1383 temp |= pll->config.hw_state.ebb4;
1384 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
1385
1386 /* Enable PLL */
1387 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1388 temp |= PORT_PLL_ENABLE;
1389 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1390 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1391
0b786e41
ID		 1392 if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
1393 200))
55be2f08
ACO		 1394 DRM_ERROR("PLL %d not locked\n", port);
1395
1396 /*
1397 * While we write to the group register to program all lanes at once we
1398 * can read only lane registers and we pick lanes 0/1 for that.
1399 */
1400 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
1401 temp &= ~LANE_STAGGER_MASK;
1402 temp &= ~LANESTAGGER_STRAP_OVRD;
1403 temp |= pll->config.hw_state.pcsdw12;
1404 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
1405}
1406
1407static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
1408 struct intel_shared_dpll *pll)
1409{
1410 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
1411 uint32_t temp;
1412
1413 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
1414 temp &= ~PORT_PLL_ENABLE;
1415 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
1416 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
1417}
1418
1419static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1420 struct intel_shared_dpll *pll,
1421 struct intel_dpll_hw_state *hw_state)
1422{
1423 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
1424 uint32_t val;
1425 bool ret;
1426
1427 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_PLLS))
1428 return false;
1429
1430 ret = false;
1431
1432 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
1433 if (!(val & PORT_PLL_ENABLE))
1434 goto out;
1435
1436 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
1437 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
1438
1439 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port));
1440 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
1441
1442 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
1443 hw_state->pll0 &= PORT_PLL_M2_MASK;
1444
1445 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
1446 hw_state->pll1 &= PORT_PLL_N_MASK;
1447
1448 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
1449 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
1450
1451 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
1452 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
1453
1454 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
1455 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
1456 PORT_PLL_INT_COEFF_MASK |
1457 PORT_PLL_GAIN_CTL_MASK;
1458
1459 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
1460 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
1461
1462 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9));
1463 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
1464
1465 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
1466 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
1467 PORT_PLL_DCO_AMP_MASK;
1468
1469 /*
1470 * While we write to the group register to program all lanes at once we
1471 * can read only lane registers. We configure all lanes the same way, so
1472 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
1473 */
1474 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
1475 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port)) != hw_state->pcsdw12)
1476 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
1477 hw_state->pcsdw12,
1478 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
1479 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
1480
1481 ret = true;
1482
1483out:
1484 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1485
1486 return ret;
1487}
1488
34177c24
ACO		 1489/* bxt clock parameters */
1490struct bxt_clk_div {
1491 int clock;
1492 uint32_t p1;
1493 uint32_t p2;
1494 uint32_t m2_int;
1495 uint32_t m2_frac;
1496 bool m2_frac_en;
1497 uint32_t n;
a277ca7d
D		 1498
1499 int vco;
34177c24
ACO		 1500};
1501
1502/* pre-calculated values for DP linkrates */
1503static const struct bxt_clk_div bxt_dp_clk_val[] = {
1504 {162000, 4, 2, 32, 1677722, 1, 1},
1505 {270000, 4, 1, 27, 0, 0, 1},
1506 {540000, 2, 1, 27, 0, 0, 1},
1507 {216000, 3, 2, 32, 1677722, 1, 1},
1508 {243000, 4, 1, 24, 1258291, 1, 1},
1509 {324000, 4, 1, 32, 1677722, 1, 1},
1510 {432000, 3, 1, 32, 1677722, 1, 1}
1511};
1512
a277ca7d
D		 1513static bool
1514bxt_ddi_hdmi_pll_dividers(struct intel_crtc *intel_crtc,
1515 struct intel_crtc_state *crtc_state, int clock,
1516 struct bxt_clk_div *clk_div)
f9476a6c 1517{
a277ca7d 1518 struct dpll best_clock;
f9476a6c 1519
a277ca7d
D		 1520 /* Calculate HDMI div */
1521 /*
1522 * FIXME: tie the following calculation into
1523 * i9xx_crtc_compute_clock
1524 */
1525 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1526 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1527 clock, pipe_name(intel_crtc->pipe));
1528 return false;
1529 }
34177c24 1530
a277ca7d
D		 1531 clk_div->p1 = best_clock.p1;
1532 clk_div->p2 = best_clock.p2;
1533 WARN_ON(best_clock.m1 != 2);
1534 clk_div->n = best_clock.n;
1535 clk_div->m2_int = best_clock.m2 >> 22;
1536 clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
1537 clk_div->m2_frac_en = clk_div->m2_frac != 0;
34177c24 1538
a277ca7d 1539 clk_div->vco = best_clock.vco;
34177c24 1540
a277ca7d
D		 1541 return true;
1542}
1543
1544static void bxt_ddi_dp_pll_dividers(int clock, struct bxt_clk_div *clk_div)
1545{
1546 int i;
1547
1548 *clk_div = bxt_dp_clk_val[0];
1549 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
1550 if (bxt_dp_clk_val[i].clock == clock) {
1551 *clk_div = bxt_dp_clk_val[i];
1552 break;
34177c24 1553 }
34177c24
ACO		 1554 }
1555
a277ca7d
D		 1556 clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
1557}
1558
1559static bool bxt_ddi_set_dpll_hw_state(int clock,
1560 struct bxt_clk_div *clk_div,
1561 struct intel_dpll_hw_state *dpll_hw_state)
1562{
1563 int vco = clk_div->vco;
1564 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
1565 uint32_t lanestagger;
1566
34177c24
ACO		 1567 if (vco >= 6200000 && vco <= 6700000) {
1568 prop_coef = 4;
1569 int_coef = 9;
1570 gain_ctl = 3;
1571 targ_cnt = 8;
1572 } else if ((vco > 5400000 && vco < 6200000) ||
1573 (vco >= 4800000 && vco < 5400000)) {
1574 prop_coef = 5;
1575 int_coef = 11;
1576 gain_ctl = 3;
1577 targ_cnt = 9;
1578 } else if (vco == 5400000) {
1579 prop_coef = 3;
1580 int_coef = 8;
1581 gain_ctl = 1;
1582 targ_cnt = 9;
1583 } else {
1584 DRM_ERROR("Invalid VCO\n");
a277ca7d 1585 return false;
34177c24
ACO		 1586 }
1587
34177c24
ACO		 1588 if (clock > 270000)
1589 lanestagger = 0x18;
1590 else if (clock > 135000)
1591 lanestagger = 0x0d;
1592 else if (clock > 67000)
1593 lanestagger = 0x07;
1594 else if (clock > 33000)
1595 lanestagger = 0x04;
1596 else
1597 lanestagger = 0x02;
1598
a277ca7d
D		 1599 dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
1600 dpll_hw_state->pll0 = clk_div->m2_int;
1601 dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
1602 dpll_hw_state->pll2 = clk_div->m2_frac;
34177c24 1603
a277ca7d
D		 1604 if (clk_div->m2_frac_en)
1605 dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
34177c24 1606
a277ca7d
D		 1607 dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef);
1608 dpll_hw_state->pll6 |= PORT_PLL_GAIN_CTL(gain_ctl);
34177c24 1609
a277ca7d 1610 dpll_hw_state->pll8 = targ_cnt;
34177c24 1611
a277ca7d 1612 dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT;
34177c24 1613
a277ca7d 1614 dpll_hw_state->pll10 =
34177c24
ACO		 1615 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT)
1616 | PORT_PLL_DCO_AMP_OVR_EN_H;
1617
a277ca7d
D		 1618 dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
1619
1620 dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger;
1621
1622 return true;
1623}
1624
1625bool bxt_ddi_dp_set_dpll_hw_state(int clock,
1626 struct intel_dpll_hw_state *dpll_hw_state)
1627{
1628 struct bxt_clk_div clk_div = {0};
1629
1630 bxt_ddi_dp_pll_dividers(clock, &clk_div);
1631
1632 return bxt_ddi_set_dpll_hw_state(clock, &clk_div, dpll_hw_state);
1633}
1634
1635static struct intel_shared_dpll *
1636bxt_get_dpll(struct intel_crtc *crtc,
1637 struct intel_crtc_state *crtc_state,
1638 struct intel_encoder *encoder)
1639{
1640 struct bxt_clk_div clk_div = {0};
1641 struct intel_dpll_hw_state dpll_hw_state = {0};
1642 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1643 struct intel_digital_port *intel_dig_port;
1644 struct intel_shared_dpll *pll;
1645 int i, clock = crtc_state->port_clock;
1646
1647 if (encoder->type == INTEL_OUTPUT_HDMI
1648 && !bxt_ddi_hdmi_pll_dividers(crtc, crtc_state,
1649 clock, &clk_div))
1650 return false;
1651
1652 if ((encoder->type == INTEL_OUTPUT_DP ||
1653 encoder->type == INTEL_OUTPUT_EDP) &&
1654 !bxt_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state))
1655 return false;
1656
1657 memset(&crtc_state->dpll_hw_state, 0,
1658 sizeof(crtc_state->dpll_hw_state));
34177c24 1659
a277ca7d 1660 crtc_state->dpll_hw_state = dpll_hw_state;
f9476a6c 1661
a79e8cc7
ML		 1662 if (encoder->type == INTEL_OUTPUT_DP_MST) {
1663 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base);
1664
1665 intel_dig_port = intel_mst->primary;
1666 } else
1667 intel_dig_port = enc_to_dig_port(&encoder->base);
34177c24 1668
f9476a6c 1669 /* 1:1 mapping between ports and PLLs */
34177c24
ACO		 1670 i = (enum intel_dpll_id) intel_dig_port->port;
1671 pll = intel_get_shared_dpll_by_id(dev_priv, i);
1672
78108b7c
VS		 1673 DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n",
1674 crtc->base.base.id, crtc->base.name, pll->name);
f9476a6c
ACO		 1675
1676 intel_reference_shared_dpll(pll, crtc_state);
1677
1678 return pll;
1679}
1680
2edd6443
ACO		 1681static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
1682 .enable = bxt_ddi_pll_enable,
1683 .disable = bxt_ddi_pll_disable,
1684 .get_hw_state = bxt_ddi_pll_get_hw_state,
1685};
55be2f08
ACO		 1686
1687static void intel_ddi_pll_init(struct drm_device *dev)
1688{
fac5e23e 1689 struct drm_i915_private *dev_priv = to_i915(dev);
55be2f08 1690
9f7eb31a
VS		 1691 if (INTEL_GEN(dev_priv) < 9) {
1692 uint32_t val = I915_READ(LCPLL_CTL);
b2045352 1693
55be2f08
ACO		 1694 /*
1695 * The LCPLL register should be turned on by the BIOS. For now
1696 * let's just check its state and print errors in case
1697 * something is wrong. Don't even try to turn it on.
1698 */
1699
1700 if (val & LCPLL_CD_SOURCE_FCLK)
1701 DRM_ERROR("CDCLK source is not LCPLL\n");
1702
1703 if (val & LCPLL_PLL_DISABLE)
1704 DRM_ERROR("LCPLL is disabled\n");
1705 }
1706}
1707
2edd6443
ACO		 1708struct dpll_info {
1709 const char *name;
1710 const int id;
1711 const struct intel_shared_dpll_funcs *funcs;
9d16da65 1712 uint32_t flags;
2edd6443
ACO		 1713};
1714
f9476a6c
ACO		 1715struct intel_dpll_mgr {
1716 const struct dpll_info *dpll_info;
1717
1718 struct intel_shared_dpll *(*get_dpll)(struct intel_crtc *crtc,
daedf20a
ACO		 1719 struct intel_crtc_state *crtc_state,
1720 struct intel_encoder *encoder);
f9476a6c
ACO		 1721};
1722
2edd6443 1723static const struct dpll_info pch_plls[] = {
9d16da65
ACO		 1724 { "PCH DPLL A", DPLL_ID_PCH_PLL_A, &ibx_pch_dpll_funcs, 0 },
1725 { "PCH DPLL B", DPLL_ID_PCH_PLL_B, &ibx_pch_dpll_funcs, 0 },
1726 { NULL, -1, NULL, 0 },
2edd6443
ACO		 1727};
1728
f9476a6c
ACO		 1729static const struct intel_dpll_mgr pch_pll_mgr = {
1730 .dpll_info = pch_plls,
1731 .get_dpll = ibx_get_dpll,
1732};
1733
2edd6443 1734static const struct dpll_info hsw_plls[] = {
9d16da65
ACO		 1735 { "WRPLL 1", DPLL_ID_WRPLL1, &hsw_ddi_wrpll_funcs, 0 },
1736 { "WRPLL 2", DPLL_ID_WRPLL2, &hsw_ddi_wrpll_funcs, 0 },
1737 { "SPLL", DPLL_ID_SPLL, &hsw_ddi_spll_funcs, 0 },
1738 { "LCPLL 810", DPLL_ID_LCPLL_810, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
1739 { "LCPLL 1350", DPLL_ID_LCPLL_1350, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
1740 { "LCPLL 2700", DPLL_ID_LCPLL_2700, &hsw_ddi_lcpll_funcs, INTEL_DPLL_ALWAYS_ON },
2edd6443
ACO		 1741 { NULL, -1, NULL, },
1742};
1743
f9476a6c
ACO		 1744static const struct intel_dpll_mgr hsw_pll_mgr = {
1745 .dpll_info = hsw_plls,
1746 .get_dpll = hsw_get_dpll,
1747};
1748
2edd6443 1749static const struct dpll_info skl_plls[] = {
a3c988ea 1750 { "DPLL 0", DPLL_ID_SKL_DPLL0, &skl_ddi_dpll0_funcs, INTEL_DPLL_ALWAYS_ON },
d5aab9d4
VS		 1751 { "DPLL 1", DPLL_ID_SKL_DPLL1, &skl_ddi_pll_funcs, 0 },
1752 { "DPLL 2", DPLL_ID_SKL_DPLL2, &skl_ddi_pll_funcs, 0 },
1753 { "DPLL 3", DPLL_ID_SKL_DPLL3, &skl_ddi_pll_funcs, 0 },
2edd6443
ACO		 1754 { NULL, -1, NULL, },
1755};
1756
f9476a6c
ACO		 1757static const struct intel_dpll_mgr skl_pll_mgr = {
1758 .dpll_info = skl_plls,
1759 .get_dpll = skl_get_dpll,
1760};
1761
2edd6443 1762static const struct dpll_info bxt_plls[] = {
08250c4b
ID		 1763 { "PORT PLL A", DPLL_ID_SKL_DPLL0, &bxt_ddi_pll_funcs, 0 },
1764 { "PORT PLL B", DPLL_ID_SKL_DPLL1, &bxt_ddi_pll_funcs, 0 },
1765 { "PORT PLL C", DPLL_ID_SKL_DPLL2, &bxt_ddi_pll_funcs, 0 },
2edd6443
ACO		 1766 { NULL, -1, NULL, },
1767};
1768
f9476a6c
ACO		 1769static const struct intel_dpll_mgr bxt_pll_mgr = {
1770 .dpll_info = bxt_plls,
1771 .get_dpll = bxt_get_dpll,
1772};
1773
7abd4b35
ACO		 1774void intel_shared_dpll_init(struct drm_device *dev)
1775{
fac5e23e 1776 struct drm_i915_private *dev_priv = to_i915(dev);
f9476a6c
ACO		 1777 const struct intel_dpll_mgr *dpll_mgr = NULL;
1778 const struct dpll_info *dpll_info;
2edd6443 1779 int i;
7abd4b35 1780
2edd6443 1781 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
f9476a6c 1782 dpll_mgr = &skl_pll_mgr;
08250c4b 1783 else if (IS_BROXTON(dev))
f9476a6c 1784 dpll_mgr = &bxt_pll_mgr;
2edd6443 1785 else if (HAS_DDI(dev))
f9476a6c 1786 dpll_mgr = &hsw_pll_mgr;
7abd4b35 1787 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
f9476a6c 1788 dpll_mgr = &pch_pll_mgr;
2edd6443 1789
f9476a6c 1790 if (!dpll_mgr) {
7abd4b35 1791 dev_priv->num_shared_dpll = 0;
2edd6443
ACO		 1792 return;
1793 }
1794
f9476a6c
ACO		 1795 dpll_info = dpll_mgr->dpll_info;
1796
2edd6443
ACO		 1797 for (i = 0; dpll_info[i].id >= 0; i++) {
1798 WARN_ON(i != dpll_info[i].id);
1799
1800 dev_priv->shared_dplls[i].id = dpll_info[i].id;
1801 dev_priv->shared_dplls[i].name = dpll_info[i].name;
1802 dev_priv->shared_dplls[i].funcs = *dpll_info[i].funcs;
9d16da65 1803 dev_priv->shared_dplls[i].flags = dpll_info[i].flags;
2edd6443
ACO		 1804 }
1805
f9476a6c 1806 dev_priv->dpll_mgr = dpll_mgr;
2edd6443 1807 dev_priv->num_shared_dpll = i;
fbf6d879 1808 mutex_init(&dev_priv->dpll_lock);
7abd4b35
ACO		 1809
1810 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
2edd6443
ACO		 1811
1812 /* FIXME: Move this to a more suitable place */
1813 if (HAS_DDI(dev))
1814 intel_ddi_pll_init(dev);
7abd4b35 1815}
f9476a6c
ACO		 1816
1817struct intel_shared_dpll *
1818intel_get_shared_dpll(struct intel_crtc *crtc,
daedf20a
ACO		 1819 struct intel_crtc_state *crtc_state,
1820 struct intel_encoder *encoder)
f9476a6c
ACO		 1821{
1822 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1823 const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr;
1824
1825 if (WARN_ON(!dpll_mgr))
1826 return NULL;
1827
daedf20a 1828 return dpll_mgr->get_dpll(crtc, crtc_state, encoder);
f9476a6c 1829}
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