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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
28 | #include <linux/i2c.h> | |
178f736a | 29 | #include <linux/hdmi.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
80824003 | 31 | #include "i915_drv.h" |
760285e7 DH |
32 | #include <drm/drm_crtc.h> |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_fb_helper.h> | |
612a9aab | 35 | #include <drm/drm_dp_helper.h> |
913d8d11 | 36 | |
1d5bfac9 DV |
37 | /** |
38 | * _wait_for - magic (register) wait macro | |
39 | * | |
40 | * Does the right thing for modeset paths when run under kdgb or similar atomic | |
41 | * contexts. Note that it's important that we check the condition again after | |
42 | * having timed out, since the timeout could be due to preemption or similar and | |
43 | * we've never had a chance to check the condition before the timeout. | |
44 | */ | |
481b6af3 | 45 | #define _wait_for(COND, MS, W) ({ \ |
1d5bfac9 | 46 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
913d8d11 | 47 | int ret__ = 0; \ |
0206e353 | 48 | while (!(COND)) { \ |
913d8d11 | 49 | if (time_after(jiffies, timeout__)) { \ |
1d5bfac9 DV |
50 | if (!(COND)) \ |
51 | ret__ = -ETIMEDOUT; \ | |
913d8d11 CW |
52 | break; \ |
53 | } \ | |
0cc2764c BW |
54 | if (W && drm_can_sleep()) { \ |
55 | msleep(W); \ | |
56 | } else { \ | |
57 | cpu_relax(); \ | |
58 | } \ | |
913d8d11 CW |
59 | } \ |
60 | ret__; \ | |
61 | }) | |
62 | ||
481b6af3 CW |
63 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
64 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) | |
6effa33b DV |
65 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
66 | DIV_ROUND_UP((US), 1000), 0) | |
481b6af3 | 67 | |
021357ac CW |
68 | #define KHz(x) (1000*x) |
69 | #define MHz(x) KHz(1000*x) | |
70 | ||
79e53945 JB |
71 | /* |
72 | * Display related stuff | |
73 | */ | |
74 | ||
75 | /* store information about an Ixxx DVO */ | |
76 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
77 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
78 | #define MAX_OUTPUTS 6 | |
79 | /* maximum connectors per crtcs in the mode set */ | |
80 | #define INTELFB_CONN_LIMIT 4 | |
81 | ||
82 | #define INTEL_I2C_BUS_DVO 1 | |
83 | #define INTEL_I2C_BUS_SDVO 2 | |
84 | ||
85 | /* these are outputs from the chip - integrated only | |
86 | external chips are via DVO or SDVO output */ | |
87 | #define INTEL_OUTPUT_UNUSED 0 | |
88 | #define INTEL_OUTPUT_ANALOG 1 | |
89 | #define INTEL_OUTPUT_DVO 2 | |
90 | #define INTEL_OUTPUT_SDVO 3 | |
91 | #define INTEL_OUTPUT_LVDS 4 | |
92 | #define INTEL_OUTPUT_TVOUT 5 | |
7d57382e | 93 | #define INTEL_OUTPUT_HDMI 6 |
a4fc5ed6 | 94 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
32f9d658 | 95 | #define INTEL_OUTPUT_EDP 8 |
72ffa333 JN |
96 | #define INTEL_OUTPUT_DSI 9 |
97 | #define INTEL_OUTPUT_UNKNOWN 10 | |
79e53945 JB |
98 | |
99 | #define INTEL_DVO_CHIP_NONE 0 | |
100 | #define INTEL_DVO_CHIP_LVDS 1 | |
101 | #define INTEL_DVO_CHIP_TMDS 2 | |
102 | #define INTEL_DVO_CHIP_TVOUT 4 | |
103 | ||
72ffa333 JN |
104 | #define INTEL_DSI_COMMAND_MODE 0 |
105 | #define INTEL_DSI_VIDEO_MODE 1 | |
106 | ||
79e53945 JB |
107 | struct intel_framebuffer { |
108 | struct drm_framebuffer base; | |
05394f39 | 109 | struct drm_i915_gem_object *obj; |
79e53945 JB |
110 | }; |
111 | ||
37811fcc CW |
112 | struct intel_fbdev { |
113 | struct drm_fb_helper helper; | |
114 | struct intel_framebuffer ifb; | |
115 | struct list_head fbdev_list; | |
116 | struct drm_display_mode *our_mode; | |
117 | }; | |
79e53945 | 118 | |
21d40d37 | 119 | struct intel_encoder { |
4ef69c7a | 120 | struct drm_encoder base; |
9a935856 DV |
121 | /* |
122 | * The new crtc this encoder will be driven from. Only differs from | |
123 | * base->crtc while a modeset is in progress. | |
124 | */ | |
125 | struct intel_crtc *new_crtc; | |
126 | ||
79e53945 | 127 | int type; |
66a9278e DV |
128 | /* |
129 | * Intel hw has only one MUX where encoders could be clone, hence a | |
130 | * simple flag is enough to compute the possible_clones mask. | |
131 | */ | |
132 | bool cloneable; | |
5ab432ef | 133 | bool connectors_active; |
21d40d37 | 134 | void (*hot_plug)(struct intel_encoder *); |
7ae89233 DV |
135 | bool (*compute_config)(struct intel_encoder *, |
136 | struct intel_crtc_config *); | |
dafd226c | 137 | void (*pre_pll_enable)(struct intel_encoder *); |
bf49ec8c | 138 | void (*pre_enable)(struct intel_encoder *); |
ef9c3aee | 139 | void (*enable)(struct intel_encoder *); |
6cc5f341 | 140 | void (*mode_set)(struct intel_encoder *intel_encoder); |
ef9c3aee | 141 | void (*disable)(struct intel_encoder *); |
bf49ec8c | 142 | void (*post_disable)(struct intel_encoder *); |
f0947c37 DV |
143 | /* Read out the current hw state of this connector, returning true if |
144 | * the encoder is active. If the encoder is enabled it also set the pipe | |
145 | * it is connected to in the pipe parameter. */ | |
146 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
045ac3b5 | 147 | /* Reconstructs the equivalent mode flags for the current hardware |
fdafa9e2 | 148 | * state. This must be called _after_ display->get_pipe_config has |
63000ef6 XZ |
149 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
150 | * be set correctly before calling this function. */ | |
045ac3b5 JB |
151 | void (*get_config)(struct intel_encoder *, |
152 | struct intel_crtc_config *pipe_config); | |
f8aed700 | 153 | int crtc_mask; |
1d843f9d | 154 | enum hpd_pin hpd_pin; |
79e53945 JB |
155 | }; |
156 | ||
1d508706 | 157 | struct intel_panel { |
dd06f90e | 158 | struct drm_display_mode *fixed_mode; |
4d891523 | 159 | int fitting_mode; |
1d508706 JN |
160 | }; |
161 | ||
5daa55eb ZW |
162 | struct intel_connector { |
163 | struct drm_connector base; | |
9a935856 DV |
164 | /* |
165 | * The fixed encoder this connector is connected to. | |
166 | */ | |
df0e9248 | 167 | struct intel_encoder *encoder; |
9a935856 DV |
168 | |
169 | /* | |
170 | * The new encoder this connector will be driven. Only differs from | |
171 | * encoder while a modeset is in progress. | |
172 | */ | |
173 | struct intel_encoder *new_encoder; | |
174 | ||
f0947c37 DV |
175 | /* Reads out the current hw, returning true if the connector is enabled |
176 | * and active (i.e. dpms ON state). */ | |
177 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 JN |
178 | |
179 | /* Panel info for eDP and LVDS */ | |
180 | struct intel_panel panel; | |
9cd300e0 JN |
181 | |
182 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
183 | struct edid *edid; | |
821450c6 EE |
184 | |
185 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
186 | state of connector->polled in case hotplug storm detection changes it */ | |
187 | u8 polled; | |
5daa55eb ZW |
188 | }; |
189 | ||
80ad9206 VS |
190 | typedef struct dpll { |
191 | /* given values */ | |
192 | int n; | |
193 | int m1, m2; | |
194 | int p1, p2; | |
195 | /* derived values */ | |
196 | int dot; | |
197 | int vco; | |
198 | int m; | |
199 | int p; | |
200 | } intel_clock_t; | |
201 | ||
b8cecdf5 | 202 | struct intel_crtc_config { |
bb760063 DV |
203 | /** |
204 | * quirks - bitfield with hw state readout quirks | |
205 | * | |
206 | * For various reasons the hw state readout code might not be able to | |
207 | * completely faithfully read out the current state. These cases are | |
208 | * tracked with quirk flags so that fastboot and state checker can act | |
209 | * accordingly. | |
210 | */ | |
211 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ | |
212 | unsigned long quirks; | |
213 | ||
b8cecdf5 | 214 | struct drm_display_mode requested_mode; |
3c52f4eb VS |
215 | /* Actual pipe timings ie. what we program into the pipe timing |
216 | * registers. adjusted_mode.clock is the pipe pixel clock. */ | |
b8cecdf5 | 217 | struct drm_display_mode adjusted_mode; |
5bfe2ac0 DV |
218 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
219 | * between pch encoders and cpu encoders. */ | |
220 | bool has_pch_encoder; | |
50f3b016 | 221 | |
3b117c8f DV |
222 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
223 | * pipe on Haswell (where we have a special eDP transcoder). */ | |
224 | enum transcoder cpu_transcoder; | |
225 | ||
50f3b016 DV |
226 | /* |
227 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
228 | * range fed into the crtcs. | |
229 | */ | |
230 | bool limited_color_range; | |
231 | ||
03afc4a2 DV |
232 | /* DP has a bunch of special case unfortunately, so mark the pipe |
233 | * accordingly. */ | |
234 | bool has_dp_encoder; | |
d8b32247 DV |
235 | |
236 | /* | |
237 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
238 | * plane bpp. | |
239 | */ | |
965e0c48 | 240 | bool dither; |
f47709a9 DV |
241 | |
242 | /* Controls for the clock computation, to override various stages. */ | |
243 | bool clock_set; | |
244 | ||
09ede541 DV |
245 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
246 | * work correctly, we need to track this at runtime.*/ | |
247 | bool sdvo_tv_clock; | |
248 | ||
e29c22c0 DV |
249 | /* |
250 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
251 | * required. This is set in the 2nd loop of calling encoder's | |
252 | * ->compute_config if the first pick doesn't work out. | |
253 | */ | |
254 | bool bw_constrained; | |
255 | ||
f47709a9 DV |
256 | /* Settings for the intel dpll used on pretty much everything but |
257 | * haswell. */ | |
80ad9206 | 258 | struct dpll dpll; |
f47709a9 | 259 | |
a43f6e0f DV |
260 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
261 | enum intel_dpll_id shared_dpll; | |
262 | ||
66e985c0 DV |
263 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
264 | struct intel_dpll_hw_state dpll_hw_state; | |
265 | ||
965e0c48 | 266 | int pipe_bpp; |
6cf86a5e | 267 | struct intel_link_m_n dp_m_n; |
ff9a6750 DV |
268 | |
269 | /* | |
270 | * Frequence the dpll for the port should run at. Differs from the | |
3c52f4eb VS |
271 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
272 | * already multiplied by pixel_multiplier. | |
df92b1e6 | 273 | */ |
ff9a6750 DV |
274 | int port_clock; |
275 | ||
6cc5f341 DV |
276 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
277 | unsigned pixel_multiplier; | |
2dd24552 JB |
278 | |
279 | /* Panel fitter controls for gen2-gen4 + VLV */ | |
b074cec8 JB |
280 | struct { |
281 | u32 control; | |
282 | u32 pgm_ratios; | |
68fc8742 | 283 | u32 lvds_border_bits; |
b074cec8 JB |
284 | } gmch_pfit; |
285 | ||
286 | /* Panel fitter placement and size for Ironlake+ */ | |
287 | struct { | |
288 | u32 pos; | |
289 | u32 size; | |
290 | } pch_pfit; | |
33d29b14 | 291 | |
ca3a0ff8 | 292 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
33d29b14 | 293 | int fdi_lanes; |
ca3a0ff8 | 294 | struct intel_link_m_n fdi_m_n; |
42db64ef PZ |
295 | |
296 | bool ips_enabled; | |
b8cecdf5 DV |
297 | }; |
298 | ||
79e53945 JB |
299 | struct intel_crtc { |
300 | struct drm_crtc base; | |
80824003 JB |
301 | enum pipe pipe; |
302 | enum plane plane; | |
79e53945 | 303 | u8 lut_r[256], lut_g[256], lut_b[256]; |
08a48469 DV |
304 | /* |
305 | * Whether the crtc and the connected output pipeline is active. Implies | |
306 | * that crtc->enabled is set, i.e. the current mode configuration has | |
307 | * some outputs connected to this crtc. | |
08a48469 DV |
308 | */ |
309 | bool active; | |
7b9f35a6 | 310 | bool eld_vld; |
93314b5b | 311 | bool primary_disabled; /* is the crtc obscured by a plane? */ |
652c393a | 312 | bool lowfreq_avail; |
02e792fb | 313 | struct intel_overlay *overlay; |
6b95a207 | 314 | struct intel_unpin_work *unpin_work; |
cda4b7d3 | 315 | |
b4a98e57 CW |
316 | atomic_t unpin_work_count; |
317 | ||
e506a0c6 DV |
318 | /* Display surface base address adjustement for pageflips. Note that on |
319 | * gen4+ this only adjusts up to a tile, offsets within a tile are | |
320 | * handled in the hw itself (with the TILEOFF register). */ | |
321 | unsigned long dspaddr_offset; | |
322 | ||
05394f39 | 323 | struct drm_i915_gem_object *cursor_bo; |
cda4b7d3 CW |
324 | uint32_t cursor_addr; |
325 | int16_t cursor_x, cursor_y; | |
326 | int16_t cursor_width, cursor_height; | |
6b383a7f | 327 | bool cursor_visible; |
4b645f14 | 328 | |
b8cecdf5 DV |
329 | struct intel_crtc_config config; |
330 | ||
6441ab5f | 331 | uint32_t ddi_pll_sel; |
10d83730 VS |
332 | |
333 | /* reset counter value when the last flip was submitted */ | |
334 | unsigned int reset_counter; | |
8664281b PZ |
335 | |
336 | /* Access to these should be protected by dev_priv->irq_lock. */ | |
337 | bool cpu_fifo_underrun_disabled; | |
338 | bool pch_fifo_underrun_disabled; | |
79e53945 JB |
339 | }; |
340 | ||
c35426d2 VS |
341 | struct intel_plane_wm_parameters { |
342 | uint32_t horiz_pixels; | |
343 | uint8_t bytes_per_pixel; | |
344 | bool enabled; | |
345 | bool scaled; | |
346 | }; | |
347 | ||
b840d907 JB |
348 | struct intel_plane { |
349 | struct drm_plane base; | |
7f1f3851 | 350 | int plane; |
b840d907 JB |
351 | enum pipe pipe; |
352 | struct drm_i915_gem_object *obj; | |
2d354c34 | 353 | bool can_scale; |
b840d907 JB |
354 | int max_downscale; |
355 | u32 lut_r[1024], lut_g[1024], lut_b[1024]; | |
5e1bac2f JB |
356 | int crtc_x, crtc_y; |
357 | unsigned int crtc_w, crtc_h; | |
358 | uint32_t src_x, src_y; | |
359 | uint32_t src_w, src_h; | |
526682e9 PZ |
360 | |
361 | /* Since we need to change the watermarks before/after | |
362 | * enabling/disabling the planes, we need to store the parameters here | |
363 | * as the other pieces of the struct may not reflect the values we want | |
364 | * for the watermark calculations. Currently only Haswell uses this. | |
365 | */ | |
c35426d2 | 366 | struct intel_plane_wm_parameters wm; |
526682e9 | 367 | |
b840d907 | 368 | void (*update_plane)(struct drm_plane *plane, |
b39d53f6 | 369 | struct drm_crtc *crtc, |
b840d907 JB |
370 | struct drm_framebuffer *fb, |
371 | struct drm_i915_gem_object *obj, | |
372 | int crtc_x, int crtc_y, | |
373 | unsigned int crtc_w, unsigned int crtc_h, | |
374 | uint32_t x, uint32_t y, | |
375 | uint32_t src_w, uint32_t src_h); | |
b39d53f6 VS |
376 | void (*disable_plane)(struct drm_plane *plane, |
377 | struct drm_crtc *crtc); | |
8ea30864 JB |
378 | int (*update_colorkey)(struct drm_plane *plane, |
379 | struct drm_intel_sprite_colorkey *key); | |
380 | void (*get_colorkey)(struct drm_plane *plane, | |
381 | struct drm_intel_sprite_colorkey *key); | |
b840d907 JB |
382 | }; |
383 | ||
b445e3b0 ED |
384 | struct intel_watermark_params { |
385 | unsigned long fifo_size; | |
386 | unsigned long max_wm; | |
387 | unsigned long default_wm; | |
388 | unsigned long guard_size; | |
389 | unsigned long cacheline_size; | |
390 | }; | |
391 | ||
392 | struct cxsr_latency { | |
393 | int is_desktop; | |
394 | int is_ddr3; | |
395 | unsigned long fsb_freq; | |
396 | unsigned long mem_freq; | |
397 | unsigned long display_sr; | |
398 | unsigned long display_hpll_disable; | |
399 | unsigned long cursor_sr; | |
400 | unsigned long cursor_hpll_disable; | |
401 | }; | |
402 | ||
79e53945 | 403 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
5daa55eb | 404 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 405 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 406 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 407 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
79e53945 | 408 | |
f5bbfca3 | 409 | struct intel_hdmi { |
b242b7f7 | 410 | u32 hdmi_reg; |
f5bbfca3 | 411 | int ddc_bus; |
f5bbfca3 | 412 | uint32_t color_range; |
55bc60db | 413 | bool color_range_auto; |
f5bbfca3 ED |
414 | bool has_hdmi_sink; |
415 | bool has_audio; | |
416 | enum hdmi_force_audio force_audio; | |
abedc077 | 417 | bool rgb_quant_range_selectable; |
f5bbfca3 | 418 | void (*write_infoframe)(struct drm_encoder *encoder, |
178f736a DL |
419 | enum hdmi_infoframe_type type, |
420 | const uint8_t *frame, ssize_t len); | |
687f4d06 PZ |
421 | void (*set_infoframes)(struct drm_encoder *encoder, |
422 | struct drm_display_mode *adjusted_mode); | |
f5bbfca3 ED |
423 | }; |
424 | ||
b091cd92 | 425 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 SK |
426 | #define DP_LINK_CONFIGURATION_SIZE 9 |
427 | ||
428 | struct intel_dp { | |
54d63ca6 | 429 | uint32_t output_reg; |
9ed35ab1 | 430 | uint32_t aux_ch_ctl_reg; |
54d63ca6 SK |
431 | uint32_t DP; |
432 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
433 | bool has_audio; | |
434 | enum hdmi_force_audio force_audio; | |
435 | uint32_t color_range; | |
55bc60db | 436 | bool color_range_auto; |
54d63ca6 SK |
437 | uint8_t link_bw; |
438 | uint8_t lane_count; | |
439 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; | |
2293bb5c | 440 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
b091cd92 | 441 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
54d63ca6 SK |
442 | struct i2c_adapter adapter; |
443 | struct i2c_algo_dp_aux_data algo; | |
54d63ca6 SK |
444 | uint8_t train_set[4]; |
445 | int panel_power_up_delay; | |
446 | int panel_power_down_delay; | |
447 | int panel_power_cycle_delay; | |
448 | int backlight_on_delay; | |
449 | int backlight_off_delay; | |
54d63ca6 SK |
450 | struct delayed_work panel_vdd_work; |
451 | bool want_panel_vdd; | |
2b28bb1b | 452 | bool psr_setup_done; |
dd06f90e | 453 | struct intel_connector *attached_connector; |
54d63ca6 SK |
454 | }; |
455 | ||
da63a9f2 PZ |
456 | struct intel_digital_port { |
457 | struct intel_encoder base; | |
174edf1f | 458 | enum port port; |
bcf53de4 | 459 | u32 saved_port_bits; |
da63a9f2 PZ |
460 | struct intel_dp dp; |
461 | struct intel_hdmi hdmi; | |
462 | }; | |
463 | ||
89b667f8 JB |
464 | static inline int |
465 | vlv_dport_to_channel(struct intel_digital_port *dport) | |
466 | { | |
467 | switch (dport->port) { | |
468 | case PORT_B: | |
469 | return 0; | |
470 | case PORT_C: | |
471 | return 1; | |
472 | default: | |
473 | BUG(); | |
474 | } | |
475 | } | |
476 | ||
f875c15a CW |
477 | static inline struct drm_crtc * |
478 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
479 | { | |
480 | struct drm_i915_private *dev_priv = dev->dev_private; | |
481 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
482 | } | |
483 | ||
417ae147 CW |
484 | static inline struct drm_crtc * |
485 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) | |
486 | { | |
487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
488 | return dev_priv->plane_to_crtc_mapping[plane]; | |
489 | } | |
490 | ||
4e5359cd SF |
491 | struct intel_unpin_work { |
492 | struct work_struct work; | |
b4a98e57 | 493 | struct drm_crtc *crtc; |
05394f39 CW |
494 | struct drm_i915_gem_object *old_fb_obj; |
495 | struct drm_i915_gem_object *pending_flip_obj; | |
4e5359cd | 496 | struct drm_pending_vblank_event *event; |
e7d841ca CW |
497 | atomic_t pending; |
498 | #define INTEL_FLIP_INACTIVE 0 | |
499 | #define INTEL_FLIP_PENDING 1 | |
500 | #define INTEL_FLIP_COMPLETE 2 | |
4e5359cd SF |
501 | bool enable_stall_check; |
502 | }; | |
503 | ||
d2acd215 DV |
504 | int intel_pch_rawclk(struct drm_device *dev); |
505 | ||
4eab8136 JN |
506 | int intel_connector_update_modes(struct drm_connector *connector, |
507 | struct edid *edid); | |
335af9a2 | 508 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
f0217c42 | 509 | |
3f43c48d | 510 | extern void intel_attach_force_audio_property(struct drm_connector *connector); |
e953fd7b CW |
511 | extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); |
512 | ||
8664281b | 513 | extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
79e53945 | 514 | extern void intel_crt_init(struct drm_device *dev); |
08d644ad | 515 | extern void intel_hdmi_init(struct drm_device *dev, |
b242b7f7 | 516 | int hdmi_reg, enum port port); |
00c09d70 PZ |
517 | extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
518 | struct intel_connector *intel_connector); | |
f5bbfca3 | 519 | extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
5bfe2ac0 DV |
520 | extern bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
521 | struct intel_crtc_config *pipe_config); | |
eef4eacb DV |
522 | extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, |
523 | bool is_sdvob); | |
79e53945 JB |
524 | extern void intel_dvo_init(struct drm_device *dev); |
525 | extern void intel_tv_init(struct drm_device *dev); | |
f047e395 | 526 | extern void intel_mark_busy(struct drm_device *dev); |
c65355bb CW |
527 | extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
528 | struct intel_ring_buffer *ring); | |
725a5b54 | 529 | extern void intel_mark_idle(struct drm_device *dev); |
c9093354 | 530 | extern void intel_lvds_init(struct drm_device *dev); |
4e646495 | 531 | extern bool intel_dsi_init(struct drm_device *dev); |
1974cad0 | 532 | extern bool intel_is_dual_link_lvds(struct drm_device *dev); |
ab9d7c30 PZ |
533 | extern void intel_dp_init(struct drm_device *dev, int output_reg, |
534 | enum port port); | |
16c25533 | 535 | extern bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
00c09d70 | 536 | struct intel_connector *intel_connector); |
247d89f6 | 537 | extern void intel_dp_init_link_config(struct intel_dp *intel_dp); |
c19b0669 PZ |
538 | extern void intel_dp_start_link_train(struct intel_dp *intel_dp); |
539 | extern void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
3ab9c637 | 540 | extern void intel_dp_stop_link_train(struct intel_dp *intel_dp); |
c19b0669 | 541 | extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
00c09d70 PZ |
542 | extern void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
543 | extern void intel_dp_check_link_status(struct intel_dp *intel_dp); | |
5bfe2ac0 DV |
544 | extern bool intel_dp_compute_config(struct intel_encoder *encoder, |
545 | struct intel_crtc_config *pipe_config); | |
cb0953d7 | 546 | extern bool intel_dpd_is_edp(struct drm_device *dev); |
d6c50ff8 PZ |
547 | extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp); |
548 | extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp); | |
82a4d9c0 PZ |
549 | extern void ironlake_edp_panel_on(struct intel_dp *intel_dp); |
550 | extern void ironlake_edp_panel_off(struct intel_dp *intel_dp); | |
551 | extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); | |
552 | extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); | |
7f1f3851 | 553 | extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
6f1d69b0 ED |
554 | extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
555 | enum plane plane); | |
32f9d658 | 556 | |
a9573556 | 557 | /* intel_panel.c */ |
dd06f90e JN |
558 | extern int intel_panel_init(struct intel_panel *panel, |
559 | struct drm_display_mode *fixed_mode); | |
1d508706 JN |
560 | extern void intel_panel_fini(struct intel_panel *panel); |
561 | ||
4c6df4b4 | 562 | extern void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
1d8e1c75 | 563 | struct drm_display_mode *adjusted_mode); |
b074cec8 JB |
564 | extern void intel_pch_panel_fitting(struct intel_crtc *crtc, |
565 | struct intel_crtc_config *pipe_config, | |
566 | int fitting_mode); | |
2dd24552 JB |
567 | extern void intel_gmch_panel_fitting(struct intel_crtc *crtc, |
568 | struct intel_crtc_config *pipe_config, | |
569 | int fitting_mode); | |
d6540632 JN |
570 | extern void intel_panel_set_backlight(struct drm_device *dev, |
571 | u32 level, u32 max); | |
0657b6b1 | 572 | extern int intel_panel_setup_backlight(struct drm_connector *connector); |
24ded204 DV |
573 | extern void intel_panel_enable_backlight(struct drm_device *dev, |
574 | enum pipe pipe); | |
47356eb6 | 575 | extern void intel_panel_disable_backlight(struct drm_device *dev); |
aaa6fd2a | 576 | extern void intel_panel_destroy_backlight(struct drm_device *dev); |
fe16d949 | 577 | extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
1d8e1c75 | 578 | |
d9e55608 | 579 | struct intel_set_config { |
1aa4b628 DV |
580 | struct drm_encoder **save_connector_encoders; |
581 | struct drm_crtc **save_encoder_crtcs; | |
5e2b584e DV |
582 | |
583 | bool fb_changed; | |
584 | bool mode_changed; | |
d9e55608 DV |
585 | }; |
586 | ||
c0c36b94 | 587 | extern void intel_crtc_restore_mode(struct drm_crtc *crtc); |
79e53945 | 588 | extern void intel_crtc_load_lut(struct drm_crtc *crtc); |
b2cabb0e | 589 | extern void intel_crtc_update_dpms(struct drm_crtc *crtc); |
ea5b213a | 590 | extern void intel_encoder_destroy(struct drm_encoder *encoder); |
5ab432ef | 591 | extern void intel_connector_dpms(struct drm_connector *, int mode); |
f0947c37 | 592 | extern bool intel_connector_get_hw_state(struct intel_connector *connector); |
b980514c | 593 | extern void intel_modeset_check_state(struct drm_device *dev); |
5e1bac2f | 594 | extern void intel_plane_restore(struct drm_plane *plane); |
bb53d4ae | 595 | extern void intel_plane_disable(struct drm_plane *plane); |
b980514c | 596 | |
79e53945 | 597 | |
df0e9248 CW |
598 | static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) |
599 | { | |
600 | return to_intel_connector(connector)->encoder; | |
601 | } | |
602 | ||
da63a9f2 PZ |
603 | static inline struct intel_digital_port * |
604 | enc_to_dig_port(struct drm_encoder *encoder) | |
605 | { | |
606 | return container_of(encoder, struct intel_digital_port, base.base); | |
9ff8c9ba ID |
607 | } |
608 | ||
609 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) | |
610 | { | |
611 | return &enc_to_dig_port(encoder)->dp; | |
da63a9f2 PZ |
612 | } |
613 | ||
614 | static inline struct intel_digital_port * | |
615 | dp_to_dig_port(struct intel_dp *intel_dp) | |
616 | { | |
617 | return container_of(intel_dp, struct intel_digital_port, dp); | |
618 | } | |
619 | ||
620 | static inline struct intel_digital_port * | |
621 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
622 | { | |
623 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
624 | } |
625 | ||
b0ea7d37 DL |
626 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
627 | struct intel_digital_port *port); | |
628 | ||
df0e9248 CW |
629 | extern void intel_connector_attach_encoder(struct intel_connector *connector, |
630 | struct intel_encoder *encoder); | |
631 | extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
79e53945 JB |
632 | |
633 | extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
634 | struct drm_crtc *crtc); | |
08d7b3d1 CW |
635 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
636 | struct drm_file *file_priv); | |
a5c961d1 PZ |
637 | extern enum transcoder |
638 | intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, | |
639 | enum pipe pipe); | |
9d0498a2 | 640 | extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
58e10eb9 | 641 | extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
d4b1931c | 642 | extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
89b667f8 | 643 | extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port); |
8261b191 CW |
644 | |
645 | struct intel_load_detect_pipe { | |
d2dff872 | 646 | struct drm_framebuffer *release_fb; |
8261b191 CW |
647 | bool load_detect_temp; |
648 | int dpms_mode; | |
649 | }; | |
d2434ab7 | 650 | extern bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 651 | struct drm_display_mode *mode, |
8261b191 | 652 | struct intel_load_detect_pipe *old); |
d2434ab7 | 653 | extern void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 654 | struct intel_load_detect_pipe *old); |
79e53945 | 655 | |
79e53945 JB |
656 | extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
657 | u16 blue, int regno); | |
b8c00ac5 DA |
658 | extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
659 | u16 *blue, int regno); | |
79e53945 | 660 | |
127bd2ac | 661 | extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 662 | struct drm_i915_gem_object *obj, |
919926ae | 663 | struct intel_ring_buffer *pipelined); |
1690e1eb | 664 | extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
127bd2ac | 665 | |
38651674 DA |
666 | extern int intel_framebuffer_init(struct drm_device *dev, |
667 | struct intel_framebuffer *ifb, | |
308e5bcb | 668 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 669 | struct drm_i915_gem_object *obj); |
ddfe1567 | 670 | extern void intel_framebuffer_fini(struct intel_framebuffer *fb); |
38651674 | 671 | extern int intel_fbdev_init(struct drm_device *dev); |
20afbda2 | 672 | extern void intel_fbdev_initial_config(struct drm_device *dev); |
38651674 | 673 | extern void intel_fbdev_fini(struct drm_device *dev); |
3fa016a0 | 674 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); |
6b95a207 KH |
675 | extern void intel_prepare_page_flip(struct drm_device *dev, int plane); |
676 | extern void intel_finish_page_flip(struct drm_device *dev, int pipe); | |
1afe3e9d | 677 | extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
6b95a207 | 678 | |
02e792fb DV |
679 | extern void intel_setup_overlay(struct drm_device *dev); |
680 | extern void intel_cleanup_overlay(struct drm_device *dev); | |
ce453d81 | 681 | extern int intel_overlay_switch_off(struct intel_overlay *overlay); |
02e792fb DV |
682 | extern int intel_overlay_put_image(struct drm_device *dev, void *data, |
683 | struct drm_file *file_priv); | |
684 | extern int intel_overlay_attrs(struct drm_device *dev, void *data, | |
685 | struct drm_file *file_priv); | |
4abe3520 | 686 | |
eb1f8e4f | 687 | extern void intel_fb_output_poll_changed(struct drm_device *dev); |
e8e7a2b8 | 688 | extern void intel_fb_restore_mode(struct drm_device *dev); |
645c62a5 | 689 | |
55607e8a DV |
690 | struct intel_shared_dpll * |
691 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc); | |
692 | ||
693 | void assert_shared_dpll(struct drm_i915_private *dev_priv, | |
694 | struct intel_shared_dpll *pll, | |
695 | bool state); | |
696 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) | |
697 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) | |
698 | void assert_pll(struct drm_i915_private *dev_priv, | |
699 | enum pipe pipe, bool state); | |
700 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
701 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
702 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, | |
703 | enum pipe pipe, bool state); | |
704 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
705 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
b840d907 JB |
706 | extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
707 | bool state); | |
708 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) | |
709 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
710 | ||
645c62a5 | 711 | extern void intel_init_clock_gating(struct drm_device *dev); |
7d708ee4 | 712 | extern void intel_suspend_hw(struct drm_device *dev); |
e0dac65e WF |
713 | extern void intel_write_eld(struct drm_encoder *encoder, |
714 | struct drm_display_mode *mode); | |
45244b87 | 715 | extern void intel_prepare_ddi(struct drm_device *dev); |
c82e4d26 | 716 | extern void hsw_fdi_link_train(struct drm_crtc *crtc); |
0e72a5b5 | 717 | extern void intel_ddi_init(struct drm_device *dev, enum port port); |
20f4dbe4 | 718 | extern enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); |
d4270e57 | 719 | |
b840d907 | 720 | /* For use by IVB LP watermark workaround in intel_sprite.c */ |
46ba614c | 721 | extern void intel_update_watermarks(struct drm_crtc *crtc); |
adf3d35e VS |
722 | extern void intel_update_sprite_watermarks(struct drm_plane *plane, |
723 | struct drm_crtc *crtc, | |
bdd57d03 VS |
724 | uint32_t sprite_width, int pixel_size, |
725 | bool enabled, bool scaled); | |
8ea30864 | 726 | |
bc752862 CW |
727 | extern unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
728 | unsigned int tiling_mode, | |
729 | unsigned int bpp, | |
730 | unsigned int pitch); | |
5a35e99e | 731 | |
8ea30864 JB |
732 | extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
733 | struct drm_file *file_priv); | |
734 | extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
735 | struct drm_file *file_priv); | |
736 | ||
85208be0 | 737 | /* Power-related functions, located in intel_pm.c */ |
1fa61106 | 738 | extern void intel_init_pm(struct drm_device *dev); |
85208be0 | 739 | /* FBC */ |
85208be0 | 740 | extern bool intel_fbc_enabled(struct drm_device *dev); |
85208be0 | 741 | extern void intel_update_fbc(struct drm_device *dev); |
eb48eb00 DV |
742 | /* IPS */ |
743 | extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); | |
744 | extern void intel_gpu_ips_teardown(void); | |
85208be0 | 745 | |
a38911a3 WX |
746 | /* Power well */ |
747 | extern int i915_init_power_well(struct drm_device *dev); | |
748 | extern void i915_remove_power_well(struct drm_device *dev); | |
749 | ||
b97186f0 PZ |
750 | extern bool intel_display_power_enabled(struct drm_device *dev, |
751 | enum intel_display_power_domain domain); | |
fa42e23c | 752 | extern void intel_init_power_well(struct drm_device *dev); |
cb10799c | 753 | extern void intel_set_power_well(struct drm_device *dev, bool enable); |
8090c6b9 DV |
754 | extern void intel_enable_gt_powersave(struct drm_device *dev); |
755 | extern void intel_disable_gt_powersave(struct drm_device *dev); | |
930ebb46 | 756 | extern void ironlake_teardown_rc6(struct drm_device *dev); |
c67a470b | 757 | void gen6_update_ring_freq(struct drm_device *dev); |
b3daeaef | 758 | |
85234cdc DV |
759 | extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
760 | enum pipe *pipe); | |
b8fc2f6a | 761 | extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); |
79f689aa | 762 | extern void intel_ddi_pll_init(struct drm_device *dev); |
8228c251 | 763 | extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); |
ad80a810 PZ |
764 | extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
765 | enum transcoder cpu_transcoder); | |
fc914639 PZ |
766 | extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
767 | extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); | |
6441ab5f | 768 | extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev); |
ff9a6750 | 769 | extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc); |
6441ab5f | 770 | extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); |
dae84799 | 771 | extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
c19b0669 | 772 | extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
1ad960f2 PZ |
773 | extern bool |
774 | intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); | |
775 | extern void intel_ddi_fdi_disable(struct drm_crtc *crtc); | |
72662e10 | 776 | |
96a02917 | 777 | extern void intel_display_handle_reset(struct drm_device *dev); |
8664281b PZ |
778 | extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
779 | enum pipe pipe, | |
780 | bool enable); | |
781 | extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, | |
782 | enum transcoder pch_transcoder, | |
783 | bool enable); | |
96a02917 | 784 | |
2b28bb1b RV |
785 | extern void intel_edp_psr_enable(struct intel_dp *intel_dp); |
786 | extern void intel_edp_psr_disable(struct intel_dp *intel_dp); | |
3d739d92 | 787 | extern void intel_edp_psr_update(struct drm_device *dev); |
be256dc7 PZ |
788 | extern void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
789 | bool switch_to_fclk, bool allow_power_down); | |
790 | extern void hsw_restore_lcpll(struct drm_i915_private *dev_priv); | |
43eaea13 PZ |
791 | extern void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
792 | extern void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, | |
793 | uint32_t mask); | |
edbfdb45 PZ |
794 | extern void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
795 | extern void snb_disable_pm_irq(struct drm_i915_private *dev_priv, | |
796 | uint32_t mask); | |
c67a470b PZ |
797 | extern void hsw_enable_pc8_work(struct work_struct *__work); |
798 | extern void hsw_enable_package_c8(struct drm_i915_private *dev_priv); | |
799 | extern void hsw_disable_package_c8(struct drm_i915_private *dev_priv); | |
800 | extern void hsw_pc8_disable_interrupts(struct drm_device *dev); | |
801 | extern void hsw_pc8_restore_interrupts(struct drm_device *dev); | |
802 | extern void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); | |
803 | extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); | |
eb14cb74 VS |
804 | extern void intel_dp_get_m_n(struct intel_crtc *crtc, |
805 | struct intel_crtc_config *pipe_config); | |
6878da05 VS |
806 | extern int intel_dotclock_calculate(int link_freq, |
807 | const struct intel_link_m_n *m_n); | |
18442d08 VS |
808 | extern void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
809 | int dotclock); | |
2b28bb1b | 810 | |
79e53945 | 811 | #endif /* __INTEL_DRV_H__ */ |