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drm/i915: prepare load-detect pipe code for dpms changes
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_drv.h
CommitLineData
79e53945
JB		 1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
8ea30864 29#include "i915_drm.h"
80824003 30#include "i915_drv.h"
79e53945 31#include "drm_crtc.h"
79e53945 32#include "drm_crtc_helper.h"
37811fcc 33#include "drm_fb_helper.h"
54d63ca6 34#include "drm_dp_helper.h"
913d8d11 35
481b6af3 36#define _wait_for(COND, MS, W) ({ \
913d8d11
CW		 37 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
38 int ret__ = 0; \
0206e353 39 while (!(COND)) { \
913d8d11
CW		 40 if (time_after(jiffies, timeout__)) { \
41 ret__ = -ETIMEDOUT; \
42 break; \
43 } \
cc1f7194 44 if (W && drm_can_sleep()) msleep(W); \
913d8d11
CW		 45 } \
46 ret__; \
47})
48
57f350b6 49#define wait_for_atomic_us(COND, US) ({ \
bcf9dcc1
CW		 50 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
51 int ret__ = 0; \
52 while (!(COND)) { \
53 if (time_after(jiffies, timeout__)) { \
54 ret__ = -ETIMEDOUT; \
55 break; \
56 } \
57 cpu_relax(); \
58 } \
59 ret__; \
57f350b6
JB		 60})
61
481b6af3
CW		 62#define wait_for(COND, MS) _wait_for(COND, MS, 1)
63#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
64
021357ac
CW		 65#define KHz(x) (1000*x)
66#define MHz(x) KHz(1000*x)
67
79e53945
JB		 68/*
69 * Display related stuff
70 */
71
72/* store information about an Ixxx DVO */
73/* The i830->i865 use multiple DVOs with multiple i2cs */
74/* the i915, i945 have a single sDVO i2c bus - which is different */
75#define MAX_OUTPUTS 6
76/* maximum connectors per crtcs in the mode set */
77#define INTELFB_CONN_LIMIT 4
78
79#define INTEL_I2C_BUS_DVO 1
80#define INTEL_I2C_BUS_SDVO 2
81
82/* these are outputs from the chip - integrated only
83 external chips are via DVO or SDVO output */
84#define INTEL_OUTPUT_UNUSED 0
85#define INTEL_OUTPUT_ANALOG 1
86#define INTEL_OUTPUT_DVO 2
87#define INTEL_OUTPUT_SDVO 3
88#define INTEL_OUTPUT_LVDS 4
89#define INTEL_OUTPUT_TVOUT 5
7d57382e 90#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 91#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 92#define INTEL_OUTPUT_EDP 8
79e53945
JB		 93
94#define INTEL_DVO_CHIP_NONE 0
95#define INTEL_DVO_CHIP_LVDS 1
96#define INTEL_DVO_CHIP_TMDS 2
97#define INTEL_DVO_CHIP_TVOUT 4
98
6c9547ff
CW		 99/* drm_display_mode->private_flags */
100#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
101#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
3b5c78a3 102#define INTEL_MODE_DP_FORCE_6BPC (0x10)
f9bef081
DV		 103/* This flag must be set by the encoder's mode_fixup if it changes the crtc
104 * timings in the mode to prevent the crtc fixup from overwriting them.
105 * Currently only lvds needs that. */
106#define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
6c9547ff
CW		 107
108static inline void
109intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
110 int multiplier)
111{
112 mode->clock *= multiplier;
113 mode->private_flags |= multiplier;
114}
115
116static inline int
117intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
118{
119 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
120}
121
79e53945
JB		 122struct intel_framebuffer {
123 struct drm_framebuffer base;
05394f39 124 struct drm_i915_gem_object *obj;
79e53945
JB		 125};
126
37811fcc
CW		 127struct intel_fbdev {
128 struct drm_fb_helper helper;
129 struct intel_framebuffer ifb;
130 struct list_head fbdev_list;
131 struct drm_display_mode *our_mode;
132};
79e53945 133
21d40d37 134struct intel_encoder {
4ef69c7a 135 struct drm_encoder base;
79e53945 136 int type;
e2f0ba97 137 bool needs_tv_clock;
66a9278e
DV		 138 /*
139 * Intel hw has only one MUX where encoders could be clone, hence a
140 * simple flag is enough to compute the possible_clones mask.
141 */
142 bool cloneable;
21d40d37 143 void (*hot_plug)(struct intel_encoder *);
f8aed700 144 int crtc_mask;
79e53945
JB		 145};
146
5daa55eb
ZW		 147struct intel_connector {
148 struct drm_connector base;
df0e9248 149 struct intel_encoder *encoder;
5daa55eb
ZW		 150};
151
79e53945
JB		 152struct intel_crtc {
153 struct drm_crtc base;
80824003
JB		 154 enum pipe pipe;
155 enum plane plane;
79e53945
JB		 156 u8 lut_r[256], lut_g[256], lut_b[256];
157 int dpms_mode;
f7abfe8b 158 bool active; /* is the crtc on? independent of the dpms mode */
93314b5b 159 bool primary_disabled; /* is the crtc obscured by a plane? */
652c393a 160 bool lowfreq_avail;
02e792fb 161 struct intel_overlay *overlay;
6b95a207 162 struct intel_unpin_work *unpin_work;
77ffb597 163 int fdi_lanes;
cda4b7d3 164
e506a0c6
DV		 165 /* Display surface base address adjustement for pageflips. Note that on
166 * gen4+ this only adjusts up to a tile, offsets within a tile are
167 * handled in the hw itself (with the TILEOFF register). */
168 unsigned long dspaddr_offset;
169
05394f39 170 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW		 171 uint32_t cursor_addr;
172 int16_t cursor_x, cursor_y;
173 int16_t cursor_width, cursor_height;
6b383a7f 174 bool cursor_visible;
5a354204 175 unsigned int bpp;
4b645f14 176
ee7b9f93
JB		 177 /* We can share PLLs across outputs if the timings match */
178 struct intel_pch_pll *pch_pll;
79e53945
JB		 179};
180
b840d907
JB		 181struct intel_plane {
182 struct drm_plane base;
183 enum pipe pipe;
184 struct drm_i915_gem_object *obj;
185 int max_downscale;
186 u32 lut_r[1024], lut_g[1024], lut_b[1024];
187 void (*update_plane)(struct drm_plane *plane,
188 struct drm_framebuffer *fb,
189 struct drm_i915_gem_object *obj,
190 int crtc_x, int crtc_y,
191 unsigned int crtc_w, unsigned int crtc_h,
192 uint32_t x, uint32_t y,
193 uint32_t src_w, uint32_t src_h);
194 void (*disable_plane)(struct drm_plane *plane);
8ea30864
JB		 195 int (*update_colorkey)(struct drm_plane *plane,
196 struct drm_intel_sprite_colorkey *key);
197 void (*get_colorkey)(struct drm_plane *plane,
198 struct drm_intel_sprite_colorkey *key);
b840d907
JB		 199};
200
b445e3b0
ED		 201struct intel_watermark_params {
202 unsigned long fifo_size;
203 unsigned long max_wm;
204 unsigned long default_wm;
205 unsigned long guard_size;
206 unsigned long cacheline_size;
207};
208
209struct cxsr_latency {
210 int is_desktop;
211 int is_ddr3;
212 unsigned long fsb_freq;
213 unsigned long mem_freq;
214 unsigned long display_sr;
215 unsigned long display_hpll_disable;
216 unsigned long cursor_sr;
217 unsigned long cursor_hpll_disable;
218};
219
79e53945 220#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 221#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 222#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 223#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 224#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 225
45187ace
JB		 226#define DIP_HEADER_SIZE 5
227
3c17fe4b
DH		 228#define DIP_TYPE_AVI 0x82
229#define DIP_VERSION_AVI 0x2
230#define DIP_LEN_AVI 13
c846b619
PZ		 231#define DIP_AVI_PR_1 0
232#define DIP_AVI_PR_2 1
3c17fe4b 233
26005210 234#define DIP_TYPE_SPD 0x83
c0864cb3
JB		 235#define DIP_VERSION_SPD 0x1
236#define DIP_LEN_SPD 25
237#define DIP_SPD_UNKNOWN 0
238#define DIP_SPD_DSTB 0x1
239#define DIP_SPD_DVDP 0x2
240#define DIP_SPD_DVHS 0x3
241#define DIP_SPD_HDDVR 0x4
242#define DIP_SPD_DVC 0x5
243#define DIP_SPD_DSC 0x6
244#define DIP_SPD_VCD 0x7
245#define DIP_SPD_GAME 0x8
246#define DIP_SPD_PC 0x9
247#define DIP_SPD_BD 0xa
248#define DIP_SPD_SCD 0xb
249
3c17fe4b
DH		 250struct dip_infoframe {
251 uint8_t type; /* HB0 */
252 uint8_t ver; /* HB1 */
253 uint8_t len; /* HB2 - body len, not including checksum */
254 uint8_t ecc; /* Header ECC */
255 uint8_t checksum; /* PB0 */
256 union {
257 struct {
258 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
259 uint8_t Y_A_B_S;
260 /* PB2 - C 7:6, M 5:4, R 3:0 */
261 uint8_t C_M_R;
262 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
263 uint8_t ITC_EC_Q_SC;
264 /* PB4 - VIC 6:0 */
265 uint8_t VIC;
0aa534df
PZ		 266 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
267 uint8_t YQ_CN_PR;
3c17fe4b
DH		 268 /* PB6 to PB13 */
269 uint16_t top_bar_end;
270 uint16_t bottom_bar_start;
271 uint16_t left_bar_end;
272 uint16_t right_bar_start;
81014b9d 273 } __attribute__ ((packed)) avi;
c0864cb3
JB		 274 struct {
275 uint8_t vn[8];
276 uint8_t pd[16];
277 uint8_t sdi;
81014b9d 278 } __attribute__ ((packed)) spd;
3c17fe4b
DH		 279 uint8_t payload[27];
280 } __attribute__ ((packed)) body;
281} __attribute__((packed));
282
f5bbfca3
ED		 283struct intel_hdmi {
284 struct intel_encoder base;
285 u32 sdvox_reg;
286 int ddc_bus;
287 int ddi_port;
288 uint32_t color_range;
289 bool has_hdmi_sink;
290 bool has_audio;
291 enum hdmi_force_audio force_audio;
292 void (*write_infoframe)(struct drm_encoder *encoder,
293 struct dip_infoframe *frame);
687f4d06
PZ		 294 void (*set_infoframes)(struct drm_encoder *encoder,
295 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED		 296};
297
54d63ca6
SK		 298#define DP_RECEIVER_CAP_SIZE 0xf
299#define DP_LINK_CONFIGURATION_SIZE 9
300
301struct intel_dp {
302 struct intel_encoder base;
303 uint32_t output_reg;
304 uint32_t DP;
305 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
306 bool has_audio;
307 enum hdmi_force_audio force_audio;
ab9d7c30 308 enum port port;
54d63ca6
SK		 309 uint32_t color_range;
310 int dpms_mode;
311 uint8_t link_bw;
312 uint8_t lane_count;
313 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
314 struct i2c_adapter adapter;
315 struct i2c_algo_dp_aux_data algo;
316 bool is_pch_edp;
317 uint8_t train_set[4];
318 int panel_power_up_delay;
319 int panel_power_down_delay;
320 int panel_power_cycle_delay;
321 int backlight_on_delay;
322 int backlight_off_delay;
323 struct drm_display_mode *panel_fixed_mode; /* for eDP */
324 struct delayed_work panel_vdd_work;
325 bool want_panel_vdd;
326 struct edid *edid; /* cached EDID for eDP */
327 int edid_mode_count;
328};
329
f875c15a
CW		 330static inline struct drm_crtc *
331intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
332{
333 struct drm_i915_private *dev_priv = dev->dev_private;
334 return dev_priv->pipe_to_crtc_mapping[pipe];
335}
336
417ae147
CW		 337static inline struct drm_crtc *
338intel_get_crtc_for_plane(struct drm_device *dev, int plane)
339{
340 struct drm_i915_private *dev_priv = dev->dev_private;
341 return dev_priv->plane_to_crtc_mapping[plane];
342}
343
4e5359cd
SF		 344struct intel_unpin_work {
345 struct work_struct work;
346 struct drm_device *dev;
05394f39
CW		 347 struct drm_i915_gem_object *old_fb_obj;
348 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd
SF		 349 struct drm_pending_vblank_event *event;
350 int pending;
351 bool enable_stall_check;
352};
353
1630fe75
CW		 354struct intel_fbc_work {
355 struct delayed_work work;
356 struct drm_crtc *crtc;
357 struct drm_framebuffer *fb;
358 int interval;
359};
360
335af9a2 361int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
f0217c42 362
3f43c48d 363extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b
CW		 364extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
365
79e53945 366extern void intel_crt_init(struct drm_device *dev);
08d644ad
DV		 367extern void intel_hdmi_init(struct drm_device *dev,
368 int sdvox_reg, enum port port);
f5bbfca3 369extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
f5bbfca3 370extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
eef4eacb
DV		 371extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
372 bool is_sdvob);
79e53945
JB		 373extern void intel_dvo_init(struct drm_device *dev);
374extern void intel_tv_init(struct drm_device *dev);
f047e395
CW		 375extern void intel_mark_busy(struct drm_device *dev);
376extern void intel_mark_idle(struct drm_device *dev);
377extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
378extern void intel_mark_fb_idle(struct drm_i915_gem_object *obj);
c5d1b51d 379extern bool intel_lvds_init(struct drm_device *dev);
ab9d7c30
PZ		 380extern void intel_dp_init(struct drm_device *dev, int output_reg,
381 enum port port);
a4fc5ed6
KP		 382void
383intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
384 struct drm_display_mode *adjusted_mode);
cb0953d7 385extern bool intel_dpd_is_edp(struct drm_device *dev);
0206e353 386extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
94bf2ced
DV		 387extern int intel_edp_target_clock(struct intel_encoder *,
388 struct drm_display_mode *mode);
814948ad 389extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
b840d907 390extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
6f1d69b0
ED		 391extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
392 enum plane plane);
32f9d658 393
a9573556 394/* intel_panel.c */
1d8e1c75
CW		 395extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
396 struct drm_display_mode *adjusted_mode);
397extern void intel_pch_panel_fitting(struct drm_device *dev,
398 int fitting_mode,
cb1793ce 399 const struct drm_display_mode *mode,
1d8e1c75 400 struct drm_display_mode *adjusted_mode);
a9573556 401extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
a9573556 402extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
aaa6fd2a 403extern int intel_panel_setup_backlight(struct drm_device *dev);
24ded204
DV		 404extern void intel_panel_enable_backlight(struct drm_device *dev,
405 enum pipe pipe);
47356eb6 406extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a 407extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949 408extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75 409
79e53945 410extern void intel_crtc_load_lut(struct drm_crtc *crtc);
0206e353
AJ		 411extern void intel_encoder_prepare(struct drm_encoder *encoder);
412extern void intel_encoder_commit(struct drm_encoder *encoder);
ea5b213a 413extern void intel_encoder_destroy(struct drm_encoder *encoder);
79e53945 414
df0e9248
CW		 415static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
416{
417 return to_intel_connector(connector)->encoder;
418}
419
420extern void intel_connector_attach_encoder(struct intel_connector *connector,
421 struct intel_encoder *encoder);
422extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
79e53945
JB		 423
424extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
425 struct drm_crtc *crtc);
08d7b3d1
CW		 426int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
427 struct drm_file *file_priv);
9d0498a2 428extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9 429extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
8261b191
CW		 430
431struct intel_load_detect_pipe {
d2dff872 432 struct drm_framebuffer *release_fb;
8261b191
CW		 433 bool load_detect_temp;
434 int dpms_mode;
435};
7173188d
CW		 436extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
437 struct drm_connector *connector,
438 struct drm_display_mode *mode,
8261b191 439 struct intel_load_detect_pipe *old);
21d40d37 440extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
c1c43977 441 struct drm_connector *connector,
8261b191 442 struct intel_load_detect_pipe *old);
79e53945 443
79e53945
JB		 444extern void intelfb_restore(void);
445extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
446 u16 blue, int regno);
b8c00ac5
DA		 447extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
448 u16 *blue, int regno);
0cdab21f 449extern void intel_enable_clock_gating(struct drm_device *dev);
79e53945 450
127bd2ac 451extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 452 struct drm_i915_gem_object *obj,
919926ae 453 struct intel_ring_buffer *pipelined);
1690e1eb 454extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
127bd2ac 455
38651674
DA		 456extern int intel_framebuffer_init(struct drm_device *dev,
457 struct intel_framebuffer *ifb,
308e5bcb 458 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 459 struct drm_i915_gem_object *obj);
38651674
DA		 460extern int intel_fbdev_init(struct drm_device *dev);
461extern void intel_fbdev_fini(struct drm_device *dev);
3fa016a0 462extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
6b95a207
KH		 463extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
464extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d 465extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207 466
02e792fb
DV		 467extern void intel_setup_overlay(struct drm_device *dev);
468extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81 469extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb
DV		 470extern int intel_overlay_put_image(struct drm_device *dev, void *data,
471 struct drm_file *file_priv);
472extern int intel_overlay_attrs(struct drm_device *dev, void *data,
473 struct drm_file *file_priv);
4abe3520 474
eb1f8e4f 475extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8 476extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5 477
b840d907
JB		 478extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
479 bool state);
480#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
481#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
482
645c62a5 483extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e
WF		 484extern void intel_write_eld(struct drm_encoder *encoder,
485 struct drm_display_mode *mode);
d4270e57 486extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
45244b87 487extern void intel_prepare_ddi(struct drm_device *dev);
c82e4d26 488extern void hsw_fdi_link_train(struct drm_crtc *crtc);
0e72a5b5 489extern void intel_ddi_init(struct drm_device *dev, enum port port);
d4270e57 490
b840d907 491/* For use by IVB LP watermark workaround in intel_sprite.c */
f681fa23 492extern void intel_update_watermarks(struct drm_device *dev);
b840d907
JB		 493extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
494 uint32_t sprite_width,
495 int pixel_size);
1f8eeabf
ED		 496extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
497 struct drm_display_mode *mode);
8ea30864
JB		 498
499extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
500 struct drm_file *file_priv);
501extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
502 struct drm_file *file_priv);
503
57f350b6
JB		 504extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
505
85208be0 506/* Power-related functions, located in intel_pm.c */
1fa61106 507extern void intel_init_pm(struct drm_device *dev);
85208be0 508/* FBC */
85208be0
ED		 509extern bool intel_fbc_enabled(struct drm_device *dev);
510extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
511extern void intel_update_fbc(struct drm_device *dev);
eb48eb00
DV		 512/* IPS */
513extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
514extern void intel_gpu_ips_teardown(void);
85208be0 515
0232e927 516extern void intel_init_power_wells(struct drm_device *dev);
8090c6b9
DV		 517extern void intel_enable_gt_powersave(struct drm_device *dev);
518extern void intel_disable_gt_powersave(struct drm_device *dev);
6590190d 519extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
930ebb46 520extern void ironlake_teardown_rc6(struct drm_device *dev);
b3daeaef 521
72662e10
ED		 522extern void intel_ddi_dpms(struct drm_encoder *encoder, int mode);
523extern void intel_ddi_mode_set(struct drm_encoder *encoder,
524 struct drm_display_mode *mode,
525 struct drm_display_mode *adjusted_mode);
526
79e53945 527#endif /* __INTEL_DRV_H__ */
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