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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007-2008 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
23 | * IN THE SOFTWARE. | |
24 | */ | |
25 | #ifndef __INTEL_DRV_H__ | |
26 | #define __INTEL_DRV_H__ | |
27 | ||
28 | #include <linux/i2c.h> | |
178f736a | 29 | #include <linux/hdmi.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
80824003 | 31 | #include "i915_drv.h" |
760285e7 DH |
32 | #include <drm/drm_crtc.h> |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_fb_helper.h> | |
612a9aab | 35 | #include <drm/drm_dp_helper.h> |
913d8d11 | 36 | |
1d5bfac9 DV |
37 | /** |
38 | * _wait_for - magic (register) wait macro | |
39 | * | |
40 | * Does the right thing for modeset paths when run under kdgb or similar atomic | |
41 | * contexts. Note that it's important that we check the condition again after | |
42 | * having timed out, since the timeout could be due to preemption or similar and | |
43 | * we've never had a chance to check the condition before the timeout. | |
44 | */ | |
481b6af3 | 45 | #define _wait_for(COND, MS, W) ({ \ |
1d5bfac9 | 46 | unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
913d8d11 | 47 | int ret__ = 0; \ |
0206e353 | 48 | while (!(COND)) { \ |
913d8d11 | 49 | if (time_after(jiffies, timeout__)) { \ |
1d5bfac9 DV |
50 | if (!(COND)) \ |
51 | ret__ = -ETIMEDOUT; \ | |
913d8d11 CW |
52 | break; \ |
53 | } \ | |
0cc2764c BW |
54 | if (W && drm_can_sleep()) { \ |
55 | msleep(W); \ | |
56 | } else { \ | |
57 | cpu_relax(); \ | |
58 | } \ | |
913d8d11 CW |
59 | } \ |
60 | ret__; \ | |
61 | }) | |
62 | ||
481b6af3 CW |
63 | #define wait_for(COND, MS) _wait_for(COND, MS, 1) |
64 | #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) | |
6effa33b DV |
65 | #define wait_for_atomic_us(COND, US) _wait_for((COND), \ |
66 | DIV_ROUND_UP((US), 1000), 0) | |
481b6af3 | 67 | |
49938ac4 JN |
68 | #define KHz(x) (1000 * (x)) |
69 | #define MHz(x) KHz(1000 * (x)) | |
021357ac | 70 | |
79e53945 JB |
71 | /* |
72 | * Display related stuff | |
73 | */ | |
74 | ||
75 | /* store information about an Ixxx DVO */ | |
76 | /* The i830->i865 use multiple DVOs with multiple i2cs */ | |
77 | /* the i915, i945 have a single sDVO i2c bus - which is different */ | |
78 | #define MAX_OUTPUTS 6 | |
79 | /* maximum connectors per crtcs in the mode set */ | |
79e53945 | 80 | |
4726e0b0 SK |
81 | /* Maximum cursor sizes */ |
82 | #define GEN2_CURSOR_WIDTH 64 | |
83 | #define GEN2_CURSOR_HEIGHT 64 | |
068be561 DL |
84 | #define MAX_CURSOR_WIDTH 256 |
85 | #define MAX_CURSOR_HEIGHT 256 | |
4726e0b0 | 86 | |
79e53945 JB |
87 | #define INTEL_I2C_BUS_DVO 1 |
88 | #define INTEL_I2C_BUS_SDVO 2 | |
89 | ||
90 | /* these are outputs from the chip - integrated only | |
91 | external chips are via DVO or SDVO output */ | |
92 | #define INTEL_OUTPUT_UNUSED 0 | |
93 | #define INTEL_OUTPUT_ANALOG 1 | |
94 | #define INTEL_OUTPUT_DVO 2 | |
95 | #define INTEL_OUTPUT_SDVO 3 | |
96 | #define INTEL_OUTPUT_LVDS 4 | |
97 | #define INTEL_OUTPUT_TVOUT 5 | |
7d57382e | 98 | #define INTEL_OUTPUT_HDMI 6 |
a4fc5ed6 | 99 | #define INTEL_OUTPUT_DISPLAYPORT 7 |
32f9d658 | 100 | #define INTEL_OUTPUT_EDP 8 |
72ffa333 JN |
101 | #define INTEL_OUTPUT_DSI 9 |
102 | #define INTEL_OUTPUT_UNKNOWN 10 | |
79e53945 JB |
103 | |
104 | #define INTEL_DVO_CHIP_NONE 0 | |
105 | #define INTEL_DVO_CHIP_LVDS 1 | |
106 | #define INTEL_DVO_CHIP_TMDS 2 | |
107 | #define INTEL_DVO_CHIP_TVOUT 4 | |
108 | ||
72ffa333 JN |
109 | #define INTEL_DSI_COMMAND_MODE 0 |
110 | #define INTEL_DSI_VIDEO_MODE 1 | |
111 | ||
79e53945 JB |
112 | struct intel_framebuffer { |
113 | struct drm_framebuffer base; | |
05394f39 | 114 | struct drm_i915_gem_object *obj; |
79e53945 JB |
115 | }; |
116 | ||
37811fcc CW |
117 | struct intel_fbdev { |
118 | struct drm_fb_helper helper; | |
8bcd4553 | 119 | struct intel_framebuffer *fb; |
37811fcc CW |
120 | struct list_head fbdev_list; |
121 | struct drm_display_mode *our_mode; | |
d978ef14 | 122 | int preferred_bpp; |
37811fcc | 123 | }; |
79e53945 | 124 | |
21d40d37 | 125 | struct intel_encoder { |
4ef69c7a | 126 | struct drm_encoder base; |
9a935856 DV |
127 | /* |
128 | * The new crtc this encoder will be driven from. Only differs from | |
129 | * base->crtc while a modeset is in progress. | |
130 | */ | |
131 | struct intel_crtc *new_crtc; | |
132 | ||
79e53945 | 133 | int type; |
bc079e8b | 134 | unsigned int cloneable; |
5ab432ef | 135 | bool connectors_active; |
21d40d37 | 136 | void (*hot_plug)(struct intel_encoder *); |
7ae89233 DV |
137 | bool (*compute_config)(struct intel_encoder *, |
138 | struct intel_crtc_config *); | |
dafd226c | 139 | void (*pre_pll_enable)(struct intel_encoder *); |
bf49ec8c | 140 | void (*pre_enable)(struct intel_encoder *); |
ef9c3aee | 141 | void (*enable)(struct intel_encoder *); |
6cc5f341 | 142 | void (*mode_set)(struct intel_encoder *intel_encoder); |
ef9c3aee | 143 | void (*disable)(struct intel_encoder *); |
bf49ec8c | 144 | void (*post_disable)(struct intel_encoder *); |
f0947c37 DV |
145 | /* Read out the current hw state of this connector, returning true if |
146 | * the encoder is active. If the encoder is enabled it also set the pipe | |
147 | * it is connected to in the pipe parameter. */ | |
148 | bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe); | |
045ac3b5 | 149 | /* Reconstructs the equivalent mode flags for the current hardware |
fdafa9e2 | 150 | * state. This must be called _after_ display->get_pipe_config has |
63000ef6 XZ |
151 | * pre-filled the pipe config. Note that intel_encoder->base.crtc must |
152 | * be set correctly before calling this function. */ | |
045ac3b5 JB |
153 | void (*get_config)(struct intel_encoder *, |
154 | struct intel_crtc_config *pipe_config); | |
f8aed700 | 155 | int crtc_mask; |
1d843f9d | 156 | enum hpd_pin hpd_pin; |
79e53945 JB |
157 | }; |
158 | ||
1d508706 | 159 | struct intel_panel { |
dd06f90e | 160 | struct drm_display_mode *fixed_mode; |
ec9ed197 | 161 | struct drm_display_mode *downclock_mode; |
4d891523 | 162 | int fitting_mode; |
58c68779 JN |
163 | |
164 | /* backlight */ | |
165 | struct { | |
c91c9f32 | 166 | bool present; |
58c68779 | 167 | u32 level; |
7bd688cd | 168 | u32 max; |
58c68779 | 169 | bool enabled; |
636baebf JN |
170 | bool combination_mode; /* gen 2/4 only */ |
171 | bool active_low_pwm; | |
58c68779 JN |
172 | struct backlight_device *device; |
173 | } backlight; | |
1d508706 JN |
174 | }; |
175 | ||
5daa55eb ZW |
176 | struct intel_connector { |
177 | struct drm_connector base; | |
9a935856 DV |
178 | /* |
179 | * The fixed encoder this connector is connected to. | |
180 | */ | |
df0e9248 | 181 | struct intel_encoder *encoder; |
9a935856 DV |
182 | |
183 | /* | |
184 | * The new encoder this connector will be driven. Only differs from | |
185 | * encoder while a modeset is in progress. | |
186 | */ | |
187 | struct intel_encoder *new_encoder; | |
188 | ||
f0947c37 DV |
189 | /* Reads out the current hw, returning true if the connector is enabled |
190 | * and active (i.e. dpms ON state). */ | |
191 | bool (*get_hw_state)(struct intel_connector *); | |
1d508706 | 192 | |
4932e2c3 ID |
193 | /* |
194 | * Removes all interfaces through which the connector is accessible | |
195 | * - like sysfs, debugfs entries -, so that no new operations can be | |
196 | * started on the connector. Also makes sure all currently pending | |
197 | * operations finish before returing. | |
198 | */ | |
199 | void (*unregister)(struct intel_connector *); | |
200 | ||
1d508706 JN |
201 | /* Panel info for eDP and LVDS */ |
202 | struct intel_panel panel; | |
9cd300e0 JN |
203 | |
204 | /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ | |
205 | struct edid *edid; | |
821450c6 EE |
206 | |
207 | /* since POLL and HPD connectors may use the same HPD line keep the native | |
208 | state of connector->polled in case hotplug storm detection changes it */ | |
209 | u8 polled; | |
5daa55eb ZW |
210 | }; |
211 | ||
80ad9206 VS |
212 | typedef struct dpll { |
213 | /* given values */ | |
214 | int n; | |
215 | int m1, m2; | |
216 | int p1, p2; | |
217 | /* derived values */ | |
218 | int dot; | |
219 | int vco; | |
220 | int m; | |
221 | int p; | |
222 | } intel_clock_t; | |
223 | ||
46f297fb | 224 | struct intel_plane_config { |
46f297fb JB |
225 | bool tiled; |
226 | int size; | |
227 | u32 base; | |
228 | }; | |
229 | ||
b8cecdf5 | 230 | struct intel_crtc_config { |
bb760063 DV |
231 | /** |
232 | * quirks - bitfield with hw state readout quirks | |
233 | * | |
234 | * For various reasons the hw state readout code might not be able to | |
235 | * completely faithfully read out the current state. These cases are | |
236 | * tracked with quirk flags so that fastboot and state checker can act | |
237 | * accordingly. | |
238 | */ | |
239 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ | |
240 | unsigned long quirks; | |
241 | ||
5113bc9b VS |
242 | /* User requested mode, only valid as a starting point to |
243 | * compute adjusted_mode, except in the case of (S)DVO where | |
244 | * it's also for the output timings of the (S)DVO chip. | |
245 | * adjusted_mode will then correspond to the S(DVO) chip's | |
246 | * preferred input timings. */ | |
b8cecdf5 | 247 | struct drm_display_mode requested_mode; |
3c52f4eb | 248 | /* Actual pipe timings ie. what we program into the pipe timing |
241bfc38 | 249 | * registers. adjusted_mode.crtc_clock is the pipe pixel clock. */ |
b8cecdf5 | 250 | struct drm_display_mode adjusted_mode; |
37327abd VS |
251 | |
252 | /* Pipe source size (ie. panel fitter input size) | |
253 | * All planes will be positioned inside this space, | |
254 | * and get clipped at the edges. */ | |
255 | int pipe_src_w, pipe_src_h; | |
256 | ||
5bfe2ac0 DV |
257 | /* Whether to set up the PCH/FDI. Note that we never allow sharing |
258 | * between pch encoders and cpu encoders. */ | |
259 | bool has_pch_encoder; | |
50f3b016 | 260 | |
3b117c8f DV |
261 | /* CPU Transcoder for the pipe. Currently this can only differ from the |
262 | * pipe on Haswell (where we have a special eDP transcoder). */ | |
263 | enum transcoder cpu_transcoder; | |
264 | ||
50f3b016 DV |
265 | /* |
266 | * Use reduced/limited/broadcast rbg range, compressing from the full | |
267 | * range fed into the crtcs. | |
268 | */ | |
269 | bool limited_color_range; | |
270 | ||
03afc4a2 DV |
271 | /* DP has a bunch of special case unfortunately, so mark the pipe |
272 | * accordingly. */ | |
273 | bool has_dp_encoder; | |
d8b32247 DV |
274 | |
275 | /* | |
276 | * Enable dithering, used when the selected pipe bpp doesn't match the | |
277 | * plane bpp. | |
278 | */ | |
965e0c48 | 279 | bool dither; |
f47709a9 DV |
280 | |
281 | /* Controls for the clock computation, to override various stages. */ | |
282 | bool clock_set; | |
283 | ||
09ede541 DV |
284 | /* SDVO TV has a bunch of special case. To make multifunction encoders |
285 | * work correctly, we need to track this at runtime.*/ | |
286 | bool sdvo_tv_clock; | |
287 | ||
e29c22c0 DV |
288 | /* |
289 | * crtc bandwidth limit, don't increase pipe bpp or clock if not really | |
290 | * required. This is set in the 2nd loop of calling encoder's | |
291 | * ->compute_config if the first pick doesn't work out. | |
292 | */ | |
293 | bool bw_constrained; | |
294 | ||
f47709a9 DV |
295 | /* Settings for the intel dpll used on pretty much everything but |
296 | * haswell. */ | |
80ad9206 | 297 | struct dpll dpll; |
f47709a9 | 298 | |
a43f6e0f DV |
299 | /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
300 | enum intel_dpll_id shared_dpll; | |
301 | ||
66e985c0 DV |
302 | /* Actual register state of the dpll, for shared dpll cross-checking. */ |
303 | struct intel_dpll_hw_state dpll_hw_state; | |
304 | ||
965e0c48 | 305 | int pipe_bpp; |
6cf86a5e | 306 | struct intel_link_m_n dp_m_n; |
ff9a6750 DV |
307 | |
308 | /* | |
309 | * Frequence the dpll for the port should run at. Differs from the | |
3c52f4eb VS |
310 | * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
311 | * already multiplied by pixel_multiplier. | |
df92b1e6 | 312 | */ |
ff9a6750 DV |
313 | int port_clock; |
314 | ||
6cc5f341 DV |
315 | /* Used by SDVO (and if we ever fix it, HDMI). */ |
316 | unsigned pixel_multiplier; | |
2dd24552 JB |
317 | |
318 | /* Panel fitter controls for gen2-gen4 + VLV */ | |
b074cec8 JB |
319 | struct { |
320 | u32 control; | |
321 | u32 pgm_ratios; | |
68fc8742 | 322 | u32 lvds_border_bits; |
b074cec8 JB |
323 | } gmch_pfit; |
324 | ||
325 | /* Panel fitter placement and size for Ironlake+ */ | |
326 | struct { | |
327 | u32 pos; | |
328 | u32 size; | |
fd4daa9c | 329 | bool enabled; |
b074cec8 | 330 | } pch_pfit; |
33d29b14 | 331 | |
ca3a0ff8 | 332 | /* FDI configuration, only valid if has_pch_encoder is set. */ |
33d29b14 | 333 | int fdi_lanes; |
ca3a0ff8 | 334 | struct intel_link_m_n fdi_m_n; |
42db64ef PZ |
335 | |
336 | bool ips_enabled; | |
cf532bb2 VS |
337 | |
338 | bool double_wide; | |
b8cecdf5 DV |
339 | }; |
340 | ||
0b2ae6d7 VS |
341 | struct intel_pipe_wm { |
342 | struct intel_wm_level wm[5]; | |
343 | uint32_t linetime; | |
344 | bool fbc_wm_enabled; | |
2a44b76b VS |
345 | bool pipe_enabled; |
346 | bool sprites_enabled; | |
347 | bool sprites_scaled; | |
0b2ae6d7 VS |
348 | }; |
349 | ||
79e53945 JB |
350 | struct intel_crtc { |
351 | struct drm_crtc base; | |
80824003 JB |
352 | enum pipe pipe; |
353 | enum plane plane; | |
79e53945 | 354 | u8 lut_r[256], lut_g[256], lut_b[256]; |
08a48469 DV |
355 | /* |
356 | * Whether the crtc and the connected output pipeline is active. Implies | |
357 | * that crtc->enabled is set, i.e. the current mode configuration has | |
358 | * some outputs connected to this crtc. | |
08a48469 DV |
359 | */ |
360 | bool active; | |
6efdf354 | 361 | unsigned long enabled_power_domains; |
7b9f35a6 | 362 | bool eld_vld; |
4c445e0e | 363 | bool primary_enabled; /* is the primary plane (partially) visible? */ |
652c393a | 364 | bool lowfreq_avail; |
02e792fb | 365 | struct intel_overlay *overlay; |
6b95a207 | 366 | struct intel_unpin_work *unpin_work; |
cda4b7d3 | 367 | |
b4a98e57 CW |
368 | atomic_t unpin_work_count; |
369 | ||
e506a0c6 DV |
370 | /* Display surface base address adjustement for pageflips. Note that on |
371 | * gen4+ this only adjusts up to a tile, offsets within a tile are | |
372 | * handled in the hw itself (with the TILEOFF register). */ | |
373 | unsigned long dspaddr_offset; | |
374 | ||
05394f39 | 375 | struct drm_i915_gem_object *cursor_bo; |
cda4b7d3 CW |
376 | uint32_t cursor_addr; |
377 | int16_t cursor_x, cursor_y; | |
378 | int16_t cursor_width, cursor_height; | |
6b383a7f | 379 | bool cursor_visible; |
4b645f14 | 380 | |
46f297fb | 381 | struct intel_plane_config plane_config; |
b8cecdf5 | 382 | struct intel_crtc_config config; |
50741abc | 383 | struct intel_crtc_config *new_config; |
7668851f | 384 | bool new_enabled; |
b8cecdf5 | 385 | |
6441ab5f | 386 | uint32_t ddi_pll_sel; |
10d83730 VS |
387 | |
388 | /* reset counter value when the last flip was submitted */ | |
389 | unsigned int reset_counter; | |
8664281b PZ |
390 | |
391 | /* Access to these should be protected by dev_priv->irq_lock. */ | |
392 | bool cpu_fifo_underrun_disabled; | |
393 | bool pch_fifo_underrun_disabled; | |
0b2ae6d7 VS |
394 | |
395 | /* per-pipe watermark state */ | |
396 | struct { | |
397 | /* watermarks currently being used */ | |
398 | struct intel_pipe_wm active; | |
399 | } wm; | |
79e53945 JB |
400 | }; |
401 | ||
c35426d2 VS |
402 | struct intel_plane_wm_parameters { |
403 | uint32_t horiz_pixels; | |
404 | uint8_t bytes_per_pixel; | |
405 | bool enabled; | |
406 | bool scaled; | |
407 | }; | |
408 | ||
b840d907 JB |
409 | struct intel_plane { |
410 | struct drm_plane base; | |
7f1f3851 | 411 | int plane; |
b840d907 JB |
412 | enum pipe pipe; |
413 | struct drm_i915_gem_object *obj; | |
2d354c34 | 414 | bool can_scale; |
b840d907 JB |
415 | int max_downscale; |
416 | u32 lut_r[1024], lut_g[1024], lut_b[1024]; | |
5e1bac2f JB |
417 | int crtc_x, crtc_y; |
418 | unsigned int crtc_w, crtc_h; | |
419 | uint32_t src_x, src_y; | |
420 | uint32_t src_w, src_h; | |
526682e9 PZ |
421 | |
422 | /* Since we need to change the watermarks before/after | |
423 | * enabling/disabling the planes, we need to store the parameters here | |
424 | * as the other pieces of the struct may not reflect the values we want | |
425 | * for the watermark calculations. Currently only Haswell uses this. | |
426 | */ | |
c35426d2 | 427 | struct intel_plane_wm_parameters wm; |
526682e9 | 428 | |
b840d907 | 429 | void (*update_plane)(struct drm_plane *plane, |
b39d53f6 | 430 | struct drm_crtc *crtc, |
b840d907 JB |
431 | struct drm_framebuffer *fb, |
432 | struct drm_i915_gem_object *obj, | |
433 | int crtc_x, int crtc_y, | |
434 | unsigned int crtc_w, unsigned int crtc_h, | |
435 | uint32_t x, uint32_t y, | |
436 | uint32_t src_w, uint32_t src_h); | |
b39d53f6 VS |
437 | void (*disable_plane)(struct drm_plane *plane, |
438 | struct drm_crtc *crtc); | |
8ea30864 JB |
439 | int (*update_colorkey)(struct drm_plane *plane, |
440 | struct drm_intel_sprite_colorkey *key); | |
441 | void (*get_colorkey)(struct drm_plane *plane, | |
442 | struct drm_intel_sprite_colorkey *key); | |
b840d907 JB |
443 | }; |
444 | ||
b445e3b0 ED |
445 | struct intel_watermark_params { |
446 | unsigned long fifo_size; | |
447 | unsigned long max_wm; | |
448 | unsigned long default_wm; | |
449 | unsigned long guard_size; | |
450 | unsigned long cacheline_size; | |
451 | }; | |
452 | ||
453 | struct cxsr_latency { | |
454 | int is_desktop; | |
455 | int is_ddr3; | |
456 | unsigned long fsb_freq; | |
457 | unsigned long mem_freq; | |
458 | unsigned long display_sr; | |
459 | unsigned long display_hpll_disable; | |
460 | unsigned long cursor_sr; | |
461 | unsigned long cursor_hpll_disable; | |
462 | }; | |
463 | ||
79e53945 | 464 | #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) |
5daa55eb | 465 | #define to_intel_connector(x) container_of(x, struct intel_connector, base) |
4ef69c7a | 466 | #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
79e53945 | 467 | #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
b840d907 | 468 | #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
79e53945 | 469 | |
f5bbfca3 | 470 | struct intel_hdmi { |
b242b7f7 | 471 | u32 hdmi_reg; |
f5bbfca3 | 472 | int ddc_bus; |
f5bbfca3 | 473 | uint32_t color_range; |
55bc60db | 474 | bool color_range_auto; |
f5bbfca3 ED |
475 | bool has_hdmi_sink; |
476 | bool has_audio; | |
477 | enum hdmi_force_audio force_audio; | |
abedc077 | 478 | bool rgb_quant_range_selectable; |
f5bbfca3 | 479 | void (*write_infoframe)(struct drm_encoder *encoder, |
178f736a | 480 | enum hdmi_infoframe_type type, |
fff63867 | 481 | const void *frame, ssize_t len); |
687f4d06 PZ |
482 | void (*set_infoframes)(struct drm_encoder *encoder, |
483 | struct drm_display_mode *adjusted_mode); | |
f5bbfca3 ED |
484 | }; |
485 | ||
b091cd92 | 486 | #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
54d63ca6 | 487 | |
4f9db5b5 PB |
488 | /** |
489 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
490 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
491 | * parsing for same resolution. | |
492 | */ | |
493 | enum edp_drrs_refresh_rate_type { | |
494 | DRRS_HIGH_RR, | |
495 | DRRS_LOW_RR, | |
496 | DRRS_MAX_RR, /* RR count */ | |
497 | }; | |
498 | ||
54d63ca6 | 499 | struct intel_dp { |
54d63ca6 | 500 | uint32_t output_reg; |
9ed35ab1 | 501 | uint32_t aux_ch_ctl_reg; |
54d63ca6 | 502 | uint32_t DP; |
54d63ca6 SK |
503 | bool has_audio; |
504 | enum hdmi_force_audio force_audio; | |
505 | uint32_t color_range; | |
55bc60db | 506 | bool color_range_auto; |
54d63ca6 SK |
507 | uint8_t link_bw; |
508 | uint8_t lane_count; | |
509 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; | |
2293bb5c | 510 | uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
b091cd92 | 511 | uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
9d1a1031 | 512 | struct drm_dp_aux aux; |
54d63ca6 SK |
513 | uint8_t train_set[4]; |
514 | int panel_power_up_delay; | |
515 | int panel_power_down_delay; | |
516 | int panel_power_cycle_delay; | |
517 | int backlight_on_delay; | |
518 | int backlight_off_delay; | |
54d63ca6 SK |
519 | struct delayed_work panel_vdd_work; |
520 | bool want_panel_vdd; | |
dce56b3c PZ |
521 | unsigned long last_power_cycle; |
522 | unsigned long last_power_on; | |
523 | unsigned long last_backlight_off; | |
2b28bb1b | 524 | bool psr_setup_done; |
06ea66b6 | 525 | bool use_tps3; |
dd06f90e | 526 | struct intel_connector *attached_connector; |
ec5b01dd DL |
527 | |
528 | uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); | |
153b1100 DL |
529 | /* |
530 | * This function returns the value we have to program the AUX_CTL | |
531 | * register with to kick off an AUX transaction. | |
532 | */ | |
533 | uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, | |
534 | bool has_aux_irq, | |
535 | int send_bytes, | |
536 | uint32_t aux_clock_divider); | |
4f9db5b5 PB |
537 | struct { |
538 | enum drrs_support_type type; | |
539 | enum edp_drrs_refresh_rate_type refresh_rate_type; | |
540 | } drrs_state; | |
541 | ||
54d63ca6 SK |
542 | }; |
543 | ||
da63a9f2 PZ |
544 | struct intel_digital_port { |
545 | struct intel_encoder base; | |
174edf1f | 546 | enum port port; |
bcf53de4 | 547 | u32 saved_port_bits; |
da63a9f2 PZ |
548 | struct intel_dp dp; |
549 | struct intel_hdmi hdmi; | |
550 | }; | |
551 | ||
89b667f8 JB |
552 | static inline int |
553 | vlv_dport_to_channel(struct intel_digital_port *dport) | |
554 | { | |
555 | switch (dport->port) { | |
556 | case PORT_B: | |
e4607fcf | 557 | return DPIO_CH0; |
89b667f8 | 558 | case PORT_C: |
e4607fcf | 559 | return DPIO_CH1; |
89b667f8 JB |
560 | default: |
561 | BUG(); | |
562 | } | |
563 | } | |
564 | ||
f875c15a CW |
565 | static inline struct drm_crtc * |
566 | intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) | |
567 | { | |
568 | struct drm_i915_private *dev_priv = dev->dev_private; | |
569 | return dev_priv->pipe_to_crtc_mapping[pipe]; | |
570 | } | |
571 | ||
417ae147 CW |
572 | static inline struct drm_crtc * |
573 | intel_get_crtc_for_plane(struct drm_device *dev, int plane) | |
574 | { | |
575 | struct drm_i915_private *dev_priv = dev->dev_private; | |
576 | return dev_priv->plane_to_crtc_mapping[plane]; | |
577 | } | |
578 | ||
4e5359cd SF |
579 | struct intel_unpin_work { |
580 | struct work_struct work; | |
b4a98e57 | 581 | struct drm_crtc *crtc; |
05394f39 CW |
582 | struct drm_i915_gem_object *old_fb_obj; |
583 | struct drm_i915_gem_object *pending_flip_obj; | |
4e5359cd | 584 | struct drm_pending_vblank_event *event; |
e7d841ca CW |
585 | atomic_t pending; |
586 | #define INTEL_FLIP_INACTIVE 0 | |
587 | #define INTEL_FLIP_PENDING 1 | |
588 | #define INTEL_FLIP_COMPLETE 2 | |
4e5359cd SF |
589 | bool enable_stall_check; |
590 | }; | |
591 | ||
d9e55608 | 592 | struct intel_set_config { |
1aa4b628 DV |
593 | struct drm_encoder **save_connector_encoders; |
594 | struct drm_crtc **save_encoder_crtcs; | |
7668851f | 595 | bool *save_crtc_enabled; |
5e2b584e DV |
596 | |
597 | bool fb_changed; | |
598 | bool mode_changed; | |
d9e55608 DV |
599 | }; |
600 | ||
5f1aae65 PZ |
601 | struct intel_load_detect_pipe { |
602 | struct drm_framebuffer *release_fb; | |
603 | bool load_detect_temp; | |
604 | int dpms_mode; | |
605 | }; | |
79e53945 | 606 | |
5f1aae65 PZ |
607 | static inline struct intel_encoder * |
608 | intel_attached_encoder(struct drm_connector *connector) | |
df0e9248 CW |
609 | { |
610 | return to_intel_connector(connector)->encoder; | |
611 | } | |
612 | ||
da63a9f2 PZ |
613 | static inline struct intel_digital_port * |
614 | enc_to_dig_port(struct drm_encoder *encoder) | |
615 | { | |
616 | return container_of(encoder, struct intel_digital_port, base.base); | |
9ff8c9ba ID |
617 | } |
618 | ||
619 | static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) | |
620 | { | |
621 | return &enc_to_dig_port(encoder)->dp; | |
da63a9f2 PZ |
622 | } |
623 | ||
624 | static inline struct intel_digital_port * | |
625 | dp_to_dig_port(struct intel_dp *intel_dp) | |
626 | { | |
627 | return container_of(intel_dp, struct intel_digital_port, dp); | |
628 | } | |
629 | ||
630 | static inline struct intel_digital_port * | |
631 | hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) | |
632 | { | |
633 | return container_of(intel_hdmi, struct intel_digital_port, hdmi); | |
7739c33b PZ |
634 | } |
635 | ||
5f1aae65 PZ |
636 | |
637 | /* i915_irq.c */ | |
87440425 PZ |
638 | bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
639 | enum pipe pipe, bool enable); | |
77961eb9 ID |
640 | bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, |
641 | enum pipe pipe, bool enable); | |
87440425 PZ |
642 | bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, |
643 | enum transcoder pch_transcoder, | |
644 | bool enable); | |
645 | void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
646 | void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
647 | void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
648 | void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); | |
730488b2 PZ |
649 | void intel_runtime_pm_disable_interrupts(struct drm_device *dev); |
650 | void intel_runtime_pm_restore_interrupts(struct drm_device *dev); | |
5f1aae65 PZ |
651 | |
652 | ||
653 | /* intel_crt.c */ | |
87440425 | 654 | void intel_crt_init(struct drm_device *dev); |
5f1aae65 PZ |
655 | |
656 | ||
657 | /* intel_ddi.c */ | |
87440425 PZ |
658 | void intel_prepare_ddi(struct drm_device *dev); |
659 | void hsw_fdi_link_train(struct drm_crtc *crtc); | |
660 | void intel_ddi_init(struct drm_device *dev, enum port port); | |
661 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder); | |
662 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); | |
663 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); | |
664 | void intel_ddi_pll_init(struct drm_device *dev); | |
665 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc); | |
666 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, | |
667 | enum transcoder cpu_transcoder); | |
668 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); | |
669 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); | |
670 | void intel_ddi_setup_hw_pll_state(struct drm_device *dev); | |
566b734a PZ |
671 | bool intel_ddi_pll_select(struct intel_crtc *crtc); |
672 | void intel_ddi_pll_enable(struct intel_crtc *crtc); | |
87440425 PZ |
673 | void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); |
674 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); | |
675 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); | |
676 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); | |
677 | void intel_ddi_fdi_disable(struct drm_crtc *crtc); | |
678 | void intel_ddi_get_config(struct intel_encoder *encoder, | |
679 | struct intel_crtc_config *pipe_config); | |
5f1aae65 PZ |
680 | |
681 | ||
682 | /* intel_display.c */ | |
ba0fbca4 | 683 | const char *intel_output_name(int output); |
5dce5b93 | 684 | bool intel_has_pending_fb_unpin(struct drm_device *dev); |
5f1aae65 | 685 | int intel_pch_rawclk(struct drm_device *dev); |
d60c4473 | 686 | int valleyview_cur_cdclk(struct drm_i915_private *dev_priv); |
87440425 PZ |
687 | void intel_mark_busy(struct drm_device *dev); |
688 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, | |
689 | struct intel_ring_buffer *ring); | |
690 | void intel_mark_idle(struct drm_device *dev); | |
691 | void intel_crtc_restore_mode(struct drm_crtc *crtc); | |
692 | void intel_crtc_update_dpms(struct drm_crtc *crtc); | |
693 | void intel_encoder_destroy(struct drm_encoder *encoder); | |
694 | void intel_connector_dpms(struct drm_connector *, int mode); | |
695 | bool intel_connector_get_hw_state(struct intel_connector *connector); | |
696 | void intel_modeset_check_state(struct drm_device *dev); | |
b0ea7d37 DL |
697 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
698 | struct intel_digital_port *port); | |
87440425 PZ |
699 | void intel_connector_attach_encoder(struct intel_connector *connector, |
700 | struct intel_encoder *encoder); | |
701 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector); | |
702 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
703 | struct drm_crtc *crtc); | |
752aa88a | 704 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector); |
08d7b3d1 CW |
705 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
706 | struct drm_file *file_priv); | |
87440425 PZ |
707 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
708 | enum pipe pipe); | |
709 | void intel_wait_for_vblank(struct drm_device *dev, int pipe); | |
710 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); | |
711 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); | |
e4607fcf CML |
712 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
713 | struct intel_digital_port *dport); | |
87440425 PZ |
714 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
715 | struct drm_display_mode *mode, | |
716 | struct intel_load_detect_pipe *old); | |
717 | void intel_release_load_detect_pipe(struct drm_connector *connector, | |
718 | struct intel_load_detect_pipe *old); | |
719 | int intel_pin_and_fence_fb_obj(struct drm_device *dev, | |
720 | struct drm_i915_gem_object *obj, | |
721 | struct intel_ring_buffer *pipelined); | |
722 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); | |
a8bb6818 DV |
723 | struct drm_framebuffer * |
724 | __intel_framebuffer_create(struct drm_device *dev, | |
87440425 PZ |
725 | struct drm_mode_fb_cmd2 *mode_cmd, |
726 | struct drm_i915_gem_object *obj); | |
87440425 PZ |
727 | void intel_prepare_page_flip(struct drm_device *dev, int plane); |
728 | void intel_finish_page_flip(struct drm_device *dev, int pipe); | |
729 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane); | |
5f1aae65 | 730 | struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); |
55607e8a DV |
731 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
732 | struct intel_shared_dpll *pll, | |
733 | bool state); | |
734 | #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) | |
735 | #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) | |
736 | void assert_pll(struct drm_i915_private *dev_priv, | |
737 | enum pipe pipe, bool state); | |
738 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
739 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
740 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, | |
741 | enum pipe pipe, bool state); | |
742 | #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true) | |
743 | #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false) | |
87440425 | 744 | void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); |
b840d907 JB |
745 | #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) |
746 | #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) | |
87440425 PZ |
747 | void intel_write_eld(struct drm_encoder *encoder, |
748 | struct drm_display_mode *mode); | |
749 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, | |
750 | unsigned int tiling_mode, | |
751 | unsigned int bpp, | |
752 | unsigned int pitch); | |
753 | void intel_display_handle_reset(struct drm_device *dev); | |
a14cb6fc PZ |
754 | void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
755 | void hsw_disable_pc8(struct drm_i915_private *dev_priv); | |
87440425 PZ |
756 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
757 | struct intel_crtc_config *pipe_config); | |
758 | int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); | |
759 | void | |
5f1aae65 PZ |
760 | ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
761 | int dotclock); | |
87440425 | 762 | bool intel_crtc_active(struct drm_crtc *crtc); |
20bc8673 VS |
763 | void hsw_enable_ips(struct intel_crtc *crtc); |
764 | void hsw_disable_ips(struct intel_crtc *crtc); | |
da7e29bd | 765 | void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); |
319be8ae ID |
766 | enum intel_display_power_domain |
767 | intel_display_port_power_domain(struct intel_encoder *intel_encoder); | |
586f49dc | 768 | int valleyview_get_vco(struct drm_i915_private *dev_priv); |
f6a83288 DV |
769 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
770 | struct intel_crtc_config *pipe_config); | |
46f297fb | 771 | int intel_format_to_fourcc(int format); |
8ea30864 | 772 | |
5f1aae65 | 773 | /* intel_dp.c */ |
87440425 PZ |
774 | void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); |
775 | bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, | |
776 | struct intel_connector *intel_connector); | |
87440425 PZ |
777 | void intel_dp_start_link_train(struct intel_dp *intel_dp); |
778 | void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
779 | void intel_dp_stop_link_train(struct intel_dp *intel_dp); | |
780 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); | |
781 | void intel_dp_encoder_destroy(struct drm_encoder *encoder); | |
782 | void intel_dp_check_link_status(struct intel_dp *intel_dp); | |
d2e216d0 | 783 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); |
87440425 PZ |
784 | bool intel_dp_compute_config(struct intel_encoder *encoder, |
785 | struct intel_crtc_config *pipe_config); | |
5d8a7752 | 786 | bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
4be73780 DV |
787 | void intel_edp_backlight_on(struct intel_dp *intel_dp); |
788 | void intel_edp_backlight_off(struct intel_dp *intel_dp); | |
24f3e092 | 789 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 DV |
790 | void intel_edp_panel_on(struct intel_dp *intel_dp); |
791 | void intel_edp_panel_off(struct intel_dp *intel_dp); | |
87440425 PZ |
792 | void intel_edp_psr_enable(struct intel_dp *intel_dp); |
793 | void intel_edp_psr_disable(struct intel_dp *intel_dp); | |
794 | void intel_edp_psr_update(struct drm_device *dev); | |
5f1aae65 PZ |
795 | |
796 | ||
797 | /* intel_dsi.c */ | |
87440425 | 798 | bool intel_dsi_init(struct drm_device *dev); |
5f1aae65 PZ |
799 | |
800 | ||
801 | /* intel_dvo.c */ | |
87440425 | 802 | void intel_dvo_init(struct drm_device *dev); |
5f1aae65 PZ |
803 | |
804 | ||
0632fef6 | 805 | /* legacy fbdev emulation in intel_fbdev.c */ |
4520f53a DV |
806 | #ifdef CONFIG_DRM_I915_FBDEV |
807 | extern int intel_fbdev_init(struct drm_device *dev); | |
808 | extern void intel_fbdev_initial_config(struct drm_device *dev); | |
809 | extern void intel_fbdev_fini(struct drm_device *dev); | |
810 | extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); | |
0632fef6 DV |
811 | extern void intel_fbdev_output_poll_changed(struct drm_device *dev); |
812 | extern void intel_fbdev_restore_mode(struct drm_device *dev); | |
4520f53a DV |
813 | #else |
814 | static inline int intel_fbdev_init(struct drm_device *dev) | |
815 | { | |
816 | return 0; | |
817 | } | |
5f1aae65 | 818 | |
4520f53a DV |
819 | static inline void intel_fbdev_initial_config(struct drm_device *dev) |
820 | { | |
821 | } | |
822 | ||
823 | static inline void intel_fbdev_fini(struct drm_device *dev) | |
824 | { | |
825 | } | |
826 | ||
827 | static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state) | |
828 | { | |
829 | } | |
830 | ||
0632fef6 | 831 | static inline void intel_fbdev_restore_mode(struct drm_device *dev) |
4520f53a DV |
832 | { |
833 | } | |
834 | #endif | |
5f1aae65 PZ |
835 | |
836 | /* intel_hdmi.c */ | |
87440425 PZ |
837 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port); |
838 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, | |
839 | struct intel_connector *intel_connector); | |
840 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); | |
841 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |
842 | struct intel_crtc_config *pipe_config); | |
5f1aae65 PZ |
843 | |
844 | ||
845 | /* intel_lvds.c */ | |
87440425 PZ |
846 | void intel_lvds_init(struct drm_device *dev); |
847 | bool intel_is_dual_link_lvds(struct drm_device *dev); | |
5f1aae65 PZ |
848 | |
849 | ||
850 | /* intel_modes.c */ | |
851 | int intel_connector_update_modes(struct drm_connector *connector, | |
87440425 | 852 | struct edid *edid); |
5f1aae65 | 853 | int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
87440425 PZ |
854 | void intel_attach_force_audio_property(struct drm_connector *connector); |
855 | void intel_attach_broadcast_rgb_property(struct drm_connector *connector); | |
5f1aae65 PZ |
856 | |
857 | ||
858 | /* intel_overlay.c */ | |
87440425 PZ |
859 | void intel_setup_overlay(struct drm_device *dev); |
860 | void intel_cleanup_overlay(struct drm_device *dev); | |
861 | int intel_overlay_switch_off(struct intel_overlay *overlay); | |
862 | int intel_overlay_put_image(struct drm_device *dev, void *data, | |
863 | struct drm_file *file_priv); | |
864 | int intel_overlay_attrs(struct drm_device *dev, void *data, | |
865 | struct drm_file *file_priv); | |
5f1aae65 PZ |
866 | |
867 | ||
868 | /* intel_panel.c */ | |
87440425 | 869 | int intel_panel_init(struct intel_panel *panel, |
4b6ed685 VK |
870 | struct drm_display_mode *fixed_mode, |
871 | struct drm_display_mode *downclock_mode); | |
87440425 PZ |
872 | void intel_panel_fini(struct intel_panel *panel); |
873 | void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, | |
874 | struct drm_display_mode *adjusted_mode); | |
875 | void intel_pch_panel_fitting(struct intel_crtc *crtc, | |
876 | struct intel_crtc_config *pipe_config, | |
877 | int fitting_mode); | |
878 | void intel_gmch_panel_fitting(struct intel_crtc *crtc, | |
879 | struct intel_crtc_config *pipe_config, | |
880 | int fitting_mode); | |
752aa88a JB |
881 | void intel_panel_set_backlight(struct intel_connector *connector, u32 level, |
882 | u32 max); | |
87440425 | 883 | int intel_panel_setup_backlight(struct drm_connector *connector); |
752aa88a JB |
884 | void intel_panel_enable_backlight(struct intel_connector *connector); |
885 | void intel_panel_disable_backlight(struct intel_connector *connector); | |
db31af1d | 886 | void intel_panel_destroy_backlight(struct drm_connector *connector); |
7bd688cd | 887 | void intel_panel_init_backlight_funcs(struct drm_device *dev); |
87440425 | 888 | enum drm_connector_status intel_panel_detect(struct drm_device *dev); |
ec9ed197 VK |
889 | extern struct drm_display_mode *intel_find_panel_downclock( |
890 | struct drm_device *dev, | |
891 | struct drm_display_mode *fixed_mode, | |
892 | struct drm_connector *connector); | |
5f1aae65 PZ |
893 | |
894 | /* intel_pm.c */ | |
87440425 PZ |
895 | void intel_init_clock_gating(struct drm_device *dev); |
896 | void intel_suspend_hw(struct drm_device *dev); | |
897 | void intel_update_watermarks(struct drm_crtc *crtc); | |
898 | void intel_update_sprite_watermarks(struct drm_plane *plane, | |
899 | struct drm_crtc *crtc, | |
900 | uint32_t sprite_width, int pixel_size, | |
901 | bool enabled, bool scaled); | |
902 | void intel_init_pm(struct drm_device *dev); | |
f742a552 | 903 | void intel_pm_setup(struct drm_device *dev); |
87440425 PZ |
904 | bool intel_fbc_enabled(struct drm_device *dev); |
905 | void intel_update_fbc(struct drm_device *dev); | |
906 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv); | |
907 | void intel_gpu_ips_teardown(void); | |
da7e29bd ID |
908 | int intel_power_domains_init(struct drm_i915_private *); |
909 | void intel_power_domains_remove(struct drm_i915_private *); | |
910 | bool intel_display_power_enabled(struct drm_i915_private *dev_priv, | |
87440425 | 911 | enum intel_display_power_domain domain); |
da7e29bd | 912 | bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv, |
ddf9c536 | 913 | enum intel_display_power_domain domain); |
da7e29bd | 914 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
87440425 | 915 | enum intel_display_power_domain domain); |
da7e29bd | 916 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
87440425 | 917 | enum intel_display_power_domain domain); |
da7e29bd | 918 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv); |
ae48434c ID |
919 | void intel_init_gt_powersave(struct drm_device *dev); |
920 | void intel_cleanup_gt_powersave(struct drm_device *dev); | |
87440425 PZ |
921 | void intel_enable_gt_powersave(struct drm_device *dev); |
922 | void intel_disable_gt_powersave(struct drm_device *dev); | |
923 | void ironlake_teardown_rc6(struct drm_device *dev); | |
c67a470b | 924 | void gen6_update_ring_freq(struct drm_device *dev); |
076e29f2 DV |
925 | void gen6_rps_idle(struct drm_i915_private *dev_priv); |
926 | void gen6_rps_boost(struct drm_i915_private *dev_priv); | |
87440425 PZ |
927 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); |
928 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); | |
8a187455 PZ |
929 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
930 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv); | |
931 | void intel_init_runtime_pm(struct drm_i915_private *dev_priv); | |
932 | void intel_fini_runtime_pm(struct drm_i915_private *dev_priv); | |
243e6a44 | 933 | void ilk_wm_get_hw_state(struct drm_device *dev); |
b3daeaef | 934 | |
72662e10 | 935 | |
5f1aae65 | 936 | /* intel_sdvo.c */ |
87440425 | 937 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob); |
96a02917 | 938 | |
2b28bb1b | 939 | |
5f1aae65 | 940 | /* intel_sprite.c */ |
87440425 | 941 | int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); |
1dba99f4 | 942 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
87440425 PZ |
943 | enum plane plane); |
944 | void intel_plane_restore(struct drm_plane *plane); | |
945 | void intel_plane_disable(struct drm_plane *plane); | |
946 | int intel_sprite_set_colorkey(struct drm_device *dev, void *data, | |
947 | struct drm_file *file_priv); | |
948 | int intel_sprite_get_colorkey(struct drm_device *dev, void *data, | |
949 | struct drm_file *file_priv); | |
5f1aae65 PZ |
950 | |
951 | ||
952 | /* intel_tv.c */ | |
87440425 | 953 | void intel_tv_init(struct drm_device *dev); |
20ddf665 | 954 | |
79e53945 | 955 | #endif /* __INTEL_DRV_H__ */ |