[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_drv.h

/*
 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
 * Copyright (c) 2007-2008 Intel Corporation
 *   Jesse Barnes <jesse.barnes@intel.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */
#ifndef __INTEL_DRV_H__
#define __INTEL_DRV_H__

#include <linux/i2c.h>
#include "i915_drm.h"
#include "i915_drv.h"
#include "drm_crtc.h"
#include "drm_crtc_helper.h"
#include "drm_fb_helper.h"

#define _wait_for(COND, MS, W) ({ \
	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS);	\
	int ret__ = 0;							\
	while (!(COND)) {						\
		if (time_after(jiffies, timeout__)) {			\
			ret__ = -ETIMEDOUT;				\
			break;						\
		}							\
		if (W && drm_can_sleep()) msleep(W);	\
	}								\
	ret__;								\
})

#define wait_for(COND, MS) _wait_for(COND, MS, 1)
#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)

#define KHz(x) (1000*x)
#define MHz(x) KHz(1000*x)

/*
 * Display related stuff
 */

/* store information about an Ixxx DVO */
/* The i830->i865 use multiple DVOs with multiple i2cs */
/* the i915, i945 have a single sDVO i2c bus - which is different */
#define MAX_OUTPUTS 6
/* maximum connectors per crtcs in the mode set */
#define INTELFB_CONN_LIMIT 4

#define INTEL_I2C_BUS_DVO 1
#define INTEL_I2C_BUS_SDVO 2

/* these are outputs from the chip - integrated only
   external chips are via DVO or SDVO output */
#define INTEL_OUTPUT_UNUSED 0
#define INTEL_OUTPUT_ANALOG 1
#define INTEL_OUTPUT_DVO 2
#define INTEL_OUTPUT_SDVO 3
#define INTEL_OUTPUT_LVDS 4
#define INTEL_OUTPUT_TVOUT 5
#define INTEL_OUTPUT_HDMI 6
#define INTEL_OUTPUT_DISPLAYPORT 7
#define INTEL_OUTPUT_EDP 8

/* Intel Pipe Clone Bit */
#define INTEL_HDMIB_CLONE_BIT 1
#define INTEL_HDMIC_CLONE_BIT 2
#define INTEL_HDMID_CLONE_BIT 3
#define INTEL_HDMIE_CLONE_BIT 4
#define INTEL_HDMIF_CLONE_BIT 5
#define INTEL_SDVO_NON_TV_CLONE_BIT 6
#define INTEL_SDVO_TV_CLONE_BIT 7
#define INTEL_SDVO_LVDS_CLONE_BIT 8
#define INTEL_ANALOG_CLONE_BIT 9
#define INTEL_TV_CLONE_BIT 10
#define INTEL_DP_B_CLONE_BIT 11
#define INTEL_DP_C_CLONE_BIT 12
#define INTEL_DP_D_CLONE_BIT 13
#define INTEL_LVDS_CLONE_BIT 14
#define INTEL_DVO_TMDS_CLONE_BIT 15
#define INTEL_DVO_LVDS_CLONE_BIT 16
#define INTEL_EDP_CLONE_BIT 17

#define INTEL_DVO_CHIP_NONE 0
#define INTEL_DVO_CHIP_LVDS 1
#define INTEL_DVO_CHIP_TMDS 2
#define INTEL_DVO_CHIP_TVOUT 4

/* drm_display_mode->private_flags */
#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
#define INTEL_MODE_DP_FORCE_6BPC (0x10)

static inline void
intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
				int multiplier)
{
	mode->clock *= multiplier;
	mode->private_flags |= multiplier;
}

static inline int
intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
{
	return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
}

struct intel_framebuffer {
	struct drm_framebuffer base;
	struct drm_i915_gem_object *obj;
};

struct intel_fbdev {
	struct drm_fb_helper helper;
	struct intel_framebuffer ifb;
	struct list_head fbdev_list;
	struct drm_display_mode *our_mode;
};

struct intel_encoder {
	struct drm_encoder base;
	int type;
	bool needs_tv_clock;
	void (*hot_plug)(struct intel_encoder *);
	int crtc_mask;
	int clone_mask;
};

struct intel_connector {
	struct drm_connector base;
	struct intel_encoder *encoder;
};

struct intel_crtc {
	struct drm_crtc base;
	enum pipe pipe;
	enum plane plane;
	u8 lut_r[256], lut_g[256], lut_b[256];
	int dpms_mode;
	bool active; /* is the crtc on? independent of the dpms mode */
	bool busy; /* is scanout buffer being updated frequently? */
	struct timer_list idle_timer;
	bool lowfreq_avail;
	struct intel_overlay *overlay;
	struct intel_unpin_work *unpin_work;
	int fdi_lanes;

	struct drm_i915_gem_object *cursor_bo;
	uint32_t cursor_addr;
	int16_t cursor_x, cursor_y;
	int16_t cursor_width, cursor_height;
	bool cursor_visible;
	unsigned int bpp;

	bool no_pll; /* tertiary pipe for IVB */
	bool use_pll_a;
};

struct intel_plane {
	struct drm_plane base;
	enum pipe pipe;
	struct drm_i915_gem_object *obj;
	bool primary_disabled;
	int max_downscale;
	u32 lut_r[1024], lut_g[1024], lut_b[1024];
	void (*update_plane)(struct drm_plane *plane,
			     struct drm_framebuffer *fb,
			     struct drm_i915_gem_object *obj,
			     int crtc_x, int crtc_y,
			     unsigned int crtc_w, unsigned int crtc_h,
			     uint32_t x, uint32_t y,
			     uint32_t src_w, uint32_t src_h);
	void (*disable_plane)(struct drm_plane *plane);
	int (*update_colorkey)(struct drm_plane *plane,
			       struct drm_intel_sprite_colorkey *key);
	void (*get_colorkey)(struct drm_plane *plane,
			     struct drm_intel_sprite_colorkey *key);
};

#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
#define to_intel_connector(x) container_of(x, struct intel_connector, base)
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
#define to_intel_plane(x) container_of(x, struct intel_plane, base)

#define DIP_HEADER_SIZE	5

#define DIP_TYPE_AVI    0x82
#define DIP_VERSION_AVI 0x2
#define DIP_LEN_AVI     13

#define DIP_TYPE_SPD	0x83
#define DIP_VERSION_SPD	0x1
#define DIP_LEN_SPD	25
#define DIP_SPD_UNKNOWN	0
#define DIP_SPD_DSTB	0x1
#define DIP_SPD_DVDP	0x2
#define DIP_SPD_DVHS	0x3
#define DIP_SPD_HDDVR	0x4
#define DIP_SPD_DVC	0x5
#define DIP_SPD_DSC	0x6
#define DIP_SPD_VCD	0x7
#define DIP_SPD_GAME	0x8
#define DIP_SPD_PC	0x9
#define DIP_SPD_BD	0xa
#define DIP_SPD_SCD	0xb

struct dip_infoframe {
	uint8_t type;		/* HB0 */
	uint8_t ver;		/* HB1 */
	uint8_t len;		/* HB2 - body len, not including checksum */
	uint8_t ecc;		/* Header ECC */
	uint8_t checksum;	/* PB0 */
	union {
		struct {
			/* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
			uint8_t Y_A_B_S;
			/* PB2 - C 7:6, M 5:4, R 3:0 */
			uint8_t C_M_R;
			/* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
			uint8_t ITC_EC_Q_SC;
			/* PB4 - VIC 6:0 */
			uint8_t VIC;
			/* PB5 - PR 3:0 */
			uint8_t PR;
			/* PB6 to PB13 */
			uint16_t top_bar_end;
			uint16_t bottom_bar_start;
			uint16_t left_bar_end;
			uint16_t right_bar_start;
		} avi;
		struct {
			uint8_t vn[8];
			uint8_t pd[16];
			uint8_t sdi;
		} spd;
		uint8_t payload[27];
	} __attribute__ ((packed)) body;
} __attribute__((packed));

static inline struct drm_crtc *
intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	return dev_priv->pipe_to_crtc_mapping[pipe];
}

static inline struct drm_crtc *
intel_get_crtc_for_plane(struct drm_device *dev, int plane)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	return dev_priv->plane_to_crtc_mapping[plane];
}

struct intel_unpin_work {
	struct work_struct work;
	struct drm_device *dev;
	struct drm_i915_gem_object *old_fb_obj;
	struct drm_i915_gem_object *pending_flip_obj;
	struct drm_pending_vblank_event *event;
	int pending;
	bool enable_stall_check;
};

struct intel_fbc_work {
	struct delayed_work work;
	struct drm_crtc *crtc;
	struct drm_framebuffer *fb;
	int interval;
};

int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus);

extern void intel_attach_force_audio_property(struct drm_connector *connector);
extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);

extern void intel_crt_init(struct drm_device *dev);
extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
extern void intel_dvo_init(struct drm_device *dev);
extern void intel_tv_init(struct drm_device *dev);
extern void intel_mark_busy(struct drm_device *dev,
			    struct drm_i915_gem_object *obj);
extern bool intel_lvds_init(struct drm_device *dev);
extern void intel_dp_init(struct drm_device *dev, int dp_reg);
void
intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
		 struct drm_display_mode *adjusted_mode);
extern bool intel_dpd_is_edp(struct drm_device *dev);
extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);

/* intel_panel.c */
extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
				   struct drm_display_mode *adjusted_mode);
extern void intel_pch_panel_fitting(struct drm_device *dev,
				    int fitting_mode,
				    struct drm_display_mode *mode,
				    struct drm_display_mode *adjusted_mode);
extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
extern u32 intel_panel_get_backlight(struct drm_device *dev);
extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
extern int intel_panel_setup_backlight(struct drm_device *dev);
extern void intel_panel_enable_backlight(struct drm_device *dev);
extern void intel_panel_disable_backlight(struct drm_device *dev);
extern void intel_panel_destroy_backlight(struct drm_device *dev);
extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);

extern void intel_crtc_load_lut(struct drm_crtc *crtc);
extern void intel_encoder_prepare(struct drm_encoder *encoder);
extern void intel_encoder_commit(struct drm_encoder *encoder);
extern void intel_encoder_destroy(struct drm_encoder *encoder);

static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
{
	return to_intel_connector(connector)->encoder;
}

extern void intel_connector_attach_encoder(struct intel_connector *connector,
					   struct intel_encoder *encoder);
extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);

extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
						    struct drm_crtc *crtc);
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);

struct intel_load_detect_pipe {
	struct drm_framebuffer *release_fb;
	bool load_detect_temp;
	int dpms_mode;
};
extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
				       struct drm_connector *connector,
				       struct drm_display_mode *mode,
				       struct intel_load_detect_pipe *old);
extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
					   struct drm_connector *connector,
					   struct intel_load_detect_pipe *old);

extern void intelfb_restore(void);
extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
				    u16 blue, int regno);
extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
				    u16 *blue, int regno);
extern void intel_enable_clock_gating(struct drm_device *dev);
extern void ironlake_enable_drps(struct drm_device *dev);
extern void ironlake_disable_drps(struct drm_device *dev);
extern void gen6_enable_rps(struct drm_i915_private *dev_priv);
extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
extern void gen6_disable_rps(struct drm_device *dev);
extern void intel_init_emon(struct drm_device *dev);

extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
				      struct drm_i915_gem_object *obj,
				      struct intel_ring_buffer *pipelined);

extern int intel_framebuffer_init(struct drm_device *dev,
				  struct intel_framebuffer *ifb,
				  struct drm_mode_fb_cmd2 *mode_cmd,
				  struct drm_i915_gem_object *obj);
extern int intel_fbdev_init(struct drm_device *dev);
extern void intel_fbdev_fini(struct drm_device *dev);

extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);

extern void intel_setup_overlay(struct drm_device *dev);
extern void intel_cleanup_overlay(struct drm_device *dev);
extern int intel_overlay_switch_off(struct intel_overlay *overlay);
extern int intel_overlay_put_image(struct drm_device *dev, void *data,
				   struct drm_file *file_priv);
extern int intel_overlay_attrs(struct drm_device *dev, void *data,
			       struct drm_file *file_priv);

extern void intel_fb_output_poll_changed(struct drm_device *dev);
extern void intel_fb_restore_mode(struct drm_device *dev);

extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
			bool state);
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)

extern void intel_init_clock_gating(struct drm_device *dev);
extern void intel_write_eld(struct drm_encoder *encoder,
			    struct drm_display_mode *mode);
extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);

/* For use by IVB LP watermark workaround in intel_sprite.c */
extern void sandybridge_update_wm(struct drm_device *dev);
extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
					   uint32_t sprite_width,
					   int pixel_size);

extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
				     struct drm_file *file_priv);
extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
				     struct drm_file *file_priv);

#endif /* __INTEL_DRV_H__ */
Commit	Line	Data
79e53945 JB	1	/*
	2	* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
	3	* Copyright (c) 2007-2008 Intel Corporation
	4	* Jesse Barnes <jesse.barnes@intel.com>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the next
	14	* paragraph) shall be included in all copies or substantial portions of the
	15	* Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	22	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	23	* IN THE SOFTWARE.
	24	*/
	25	#ifndef __INTEL_DRV_H__
	26	#define __INTEL_DRV_H__
	27
	28	#include <linux/i2c.h>
8ea30864	29	#include "i915_drm.h"
80824003	30	#include "i915_drv.h"
79e53945	31	#include "drm_crtc.h"
79e53945	32	#include "drm_crtc_helper.h"
37811fcc	33	#include "drm_fb_helper.h"
913d8d11	34
481b6af3	35	#define _wait_for(COND, MS, W) ({ \
913d8d11 CW	36	unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
913d8d11 CW	37	int ret__ = 0; \
0206e353	38	while (!(COND)) { \
913d8d11 CW	39	if (time_after(jiffies, timeout__)) { \
	40	ret__ = -ETIMEDOUT; \
	41	break; \
	42	} \
cc1f7194	43	if (W && drm_can_sleep()) msleep(W); \
913d8d11 CW	44	} \
	45	ret__; \
	46	})
	47
481b6af3 CW	48	#define wait_for(COND, MS) _wait_for(COND, MS, 1)
	49	#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
	50
021357ac CW	51	#define KHz(x) (1000*x)
	52	#define MHz(x) KHz(1000*x)
	53
79e53945 JB	54	/*
	55	* Display related stuff
	56	*/
	57
	58	/* store information about an Ixxx DVO */
	59	/* The i830->i865 use multiple DVOs with multiple i2cs */
	60	/* the i915, i945 have a single sDVO i2c bus - which is different */
	61	#define MAX_OUTPUTS 6
	62	/* maximum connectors per crtcs in the mode set */
	63	#define INTELFB_CONN_LIMIT 4
	64
	65	#define INTEL_I2C_BUS_DVO 1
	66	#define INTEL_I2C_BUS_SDVO 2
	67
	68	/* these are outputs from the chip - integrated only
	69	external chips are via DVO or SDVO output */
	70	#define INTEL_OUTPUT_UNUSED 0
	71	#define INTEL_OUTPUT_ANALOG 1
	72	#define INTEL_OUTPUT_DVO 2
	73	#define INTEL_OUTPUT_SDVO 3
	74	#define INTEL_OUTPUT_LVDS 4
	75	#define INTEL_OUTPUT_TVOUT 5
7d57382e	76	#define INTEL_OUTPUT_HDMI 6
a4fc5ed6	77	#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658	78	#define INTEL_OUTPUT_EDP 8
79e53945	79
f8aed700 ML	80	/* Intel Pipe Clone Bit */
	81	#define INTEL_HDMIB_CLONE_BIT 1
	82	#define INTEL_HDMIC_CLONE_BIT 2
	83	#define INTEL_HDMID_CLONE_BIT 3
	84	#define INTEL_HDMIE_CLONE_BIT 4
	85	#define INTEL_HDMIF_CLONE_BIT 5
	86	#define INTEL_SDVO_NON_TV_CLONE_BIT 6
	87	#define INTEL_SDVO_TV_CLONE_BIT 7
	88	#define INTEL_SDVO_LVDS_CLONE_BIT 8
	89	#define INTEL_ANALOG_CLONE_BIT 9
	90	#define INTEL_TV_CLONE_BIT 10
	91	#define INTEL_DP_B_CLONE_BIT 11
	92	#define INTEL_DP_C_CLONE_BIT 12
	93	#define INTEL_DP_D_CLONE_BIT 13
	94	#define INTEL_LVDS_CLONE_BIT 14
	95	#define INTEL_DVO_TMDS_CLONE_BIT 15
	96	#define INTEL_DVO_LVDS_CLONE_BIT 16
7c8460db	97	#define INTEL_EDP_CLONE_BIT 17
f8aed700	98
79e53945 JB	99	#define INTEL_DVO_CHIP_NONE 0
	100	#define INTEL_DVO_CHIP_LVDS 1
	101	#define INTEL_DVO_CHIP_TMDS 2
	102	#define INTEL_DVO_CHIP_TVOUT 4
	103
6c9547ff CW	104	/* drm_display_mode->private_flags */
	105	#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
	106	#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
3b5c78a3	107	#define INTEL_MODE_DP_FORCE_6BPC (0x10)
6c9547ff CW	108
	109	static inline void
	110	intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
	111	int multiplier)
	112	{
	113	mode->clock *= multiplier;
	114	mode->private_flags \|= multiplier;
	115	}
	116
	117	static inline int
	118	intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
	119	{
	120	return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
	121	}
	122
79e53945 JB	123	struct intel_framebuffer {
79e53945 JB	124	struct drm_framebuffer base;
05394f39	125	struct drm_i915_gem_object *obj;
79e53945 JB	126	};
79e53945 JB	127
37811fcc CW	128	struct intel_fbdev {
	129	struct drm_fb_helper helper;
	130	struct intel_framebuffer ifb;
	131	struct list_head fbdev_list;
	132	struct drm_display_mode *our_mode;
	133	};
79e53945	134
21d40d37	135	struct intel_encoder {
4ef69c7a	136	struct drm_encoder base;
79e53945	137	int type;
e2f0ba97	138	bool needs_tv_clock;
21d40d37	139	void (hot_plug)(struct intel_encoder );
f8aed700 ML	140	int crtc_mask;
f8aed700 ML	141	int clone_mask;
79e53945 JB	142	};
79e53945 JB	143
5daa55eb ZW	144	struct intel_connector {
5daa55eb ZW	145	struct drm_connector base;
df0e9248	146	struct intel_encoder *encoder;
5daa55eb ZW	147	};
5daa55eb ZW	148
79e53945 JB	149	struct intel_crtc {
79e53945 JB	150	struct drm_crtc base;
80824003 JB	151	enum pipe pipe;
80824003 JB	152	enum plane plane;
79e53945 JB	153	u8 lut_r[256], lut_g[256], lut_b[256];
79e53945 JB	154	int dpms_mode;
f7abfe8b	155	bool active; /* is the crtc on? independent of the dpms mode */
652c393a JB	156	bool busy; /* is scanout buffer being updated frequently? */
	157	struct timer_list idle_timer;
	158	bool lowfreq_avail;
02e792fb	159	struct intel_overlay *overlay;
6b95a207	160	struct intel_unpin_work *unpin_work;
77ffb597	161	int fdi_lanes;
cda4b7d3	162
05394f39	163	struct drm_i915_gem_object *cursor_bo;
cda4b7d3 CW	164	uint32_t cursor_addr;
	165	int16_t cursor_x, cursor_y;
	166	int16_t cursor_width, cursor_height;
6b383a7f	167	bool cursor_visible;
5a354204	168	unsigned int bpp;
4b645f14 JB	169
	170	bool no_pll; /* tertiary pipe for IVB */
	171	bool use_pll_a;
79e53945 JB	172	};
79e53945 JB	173
b840d907 JB	174	struct intel_plane {
	175	struct drm_plane base;
	176	enum pipe pipe;
	177	struct drm_i915_gem_object *obj;
175bd420	178	bool primary_disabled;
b840d907 JB	179	int max_downscale;
	180	u32 lut_r[1024], lut_g[1024], lut_b[1024];
	181	void (update_plane)(struct drm_plane plane,
	182	struct drm_framebuffer *fb,
	183	struct drm_i915_gem_object *obj,
	184	int crtc_x, int crtc_y,
	185	unsigned int crtc_w, unsigned int crtc_h,
	186	uint32_t x, uint32_t y,
	187	uint32_t src_w, uint32_t src_h);
	188	void (disable_plane)(struct drm_plane plane);
8ea30864 JB	189	int (update_colorkey)(struct drm_plane plane,
	190	struct drm_intel_sprite_colorkey *key);
	191	void (get_colorkey)(struct drm_plane plane,
	192	struct drm_intel_sprite_colorkey *key);
b840d907 JB	193	};
b840d907 JB	194
79e53945	195	#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb	196	#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a	197	#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945	198	#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907	199	#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945	200
45187ace JB	201	#define DIP_HEADER_SIZE 5
45187ace JB	202
3c17fe4b DH	203	#define DIP_TYPE_AVI 0x82
	204	#define DIP_VERSION_AVI 0x2
	205	#define DIP_LEN_AVI 13
	206
26005210	207	#define DIP_TYPE_SPD 0x83
c0864cb3 JB	208	#define DIP_VERSION_SPD 0x1
	209	#define DIP_LEN_SPD 25
	210	#define DIP_SPD_UNKNOWN 0
	211	#define DIP_SPD_DSTB 0x1
	212	#define DIP_SPD_DVDP 0x2
	213	#define DIP_SPD_DVHS 0x3
	214	#define DIP_SPD_HDDVR 0x4
	215	#define DIP_SPD_DVC 0x5
	216	#define DIP_SPD_DSC 0x6
	217	#define DIP_SPD_VCD 0x7
	218	#define DIP_SPD_GAME 0x8
	219	#define DIP_SPD_PC 0x9
	220	#define DIP_SPD_BD 0xa
	221	#define DIP_SPD_SCD 0xb
	222
3c17fe4b DH	223	struct dip_infoframe {
	224	uint8_t type; /* HB0 */
	225	uint8_t ver; /* HB1 */
	226	uint8_t len; /* HB2 - body len, not including checksum */
	227	uint8_t ecc; /* Header ECC */
	228	uint8_t checksum; /* PB0 */
	229	union {
	230	struct {
	231	/* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
	232	uint8_t Y_A_B_S;
	233	/* PB2 - C 7:6, M 5:4, R 3:0 */
	234	uint8_t C_M_R;
	235	/* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
	236	uint8_t ITC_EC_Q_SC;
	237	/* PB4 - VIC 6:0 */
	238	uint8_t VIC;
	239	/* PB5 - PR 3:0 */
	240	uint8_t PR;
	241	/* PB6 to PB13 */
	242	uint16_t top_bar_end;
	243	uint16_t bottom_bar_start;
	244	uint16_t left_bar_end;
	245	uint16_t right_bar_start;
	246	} avi;
c0864cb3 JB	247	struct {
	248	uint8_t vn[8];
	249	uint8_t pd[16];
	250	uint8_t sdi;
	251	} spd;
3c17fe4b DH	252	uint8_t payload[27];
	253	} __attribute__ ((packed)) body;
	254	} __attribute__((packed));
	255
f875c15a CW	256	static inline struct drm_crtc *
	257	intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
	258	{
	259	struct drm_i915_private *dev_priv = dev->dev_private;
	260	return dev_priv->pipe_to_crtc_mapping[pipe];
	261	}
	262
417ae147 CW	263	static inline struct drm_crtc *
	264	intel_get_crtc_for_plane(struct drm_device *dev, int plane)
	265	{
	266	struct drm_i915_private *dev_priv = dev->dev_private;
	267	return dev_priv->plane_to_crtc_mapping[plane];
	268	}
	269
4e5359cd SF	270	struct intel_unpin_work {
	271	struct work_struct work;
	272	struct drm_device *dev;
05394f39 CW	273	struct drm_i915_gem_object *old_fb_obj;
05394f39 CW	274	struct drm_i915_gem_object *pending_flip_obj;
4e5359cd SF	275	struct drm_pending_vblank_event *event;
	276	int pending;
	277	bool enable_stall_check;
	278	};
	279
1630fe75 CW	280	struct intel_fbc_work {
	281	struct delayed_work work;
	282	struct drm_crtc *crtc;
	283	struct drm_framebuffer *fb;
	284	int interval;
	285	};
	286
335af9a2	287	int intel_ddc_get_modes(struct drm_connector c, struct i2c_adapter adapter);
f899fc64	288	extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus);
f0217c42	289
3f43c48d	290	extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b CW	291	extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
e953fd7b CW	292
79e53945	293	extern void intel_crt_init(struct drm_device *dev);
7d57382e	294	extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
3c17fe4b	295	void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
7d57382e	296	extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
79e53945 JB	297	extern void intel_dvo_init(struct drm_device *dev);
79e53945 JB	298	extern void intel_tv_init(struct drm_device *dev);
05394f39 CW	299	extern void intel_mark_busy(struct drm_device *dev,
05394f39 CW	300	struct drm_i915_gem_object *obj);
c5d1b51d	301	extern bool intel_lvds_init(struct drm_device *dev);
a4fc5ed6 KP	302	extern void intel_dp_init(struct drm_device *dev, int dp_reg);
	303	void
	304	intel_dp_set_m_n(struct drm_crtc crtc, struct drm_display_mode mode,
	305	struct drm_display_mode *adjusted_mode);
cb0953d7	306	extern bool intel_dpd_is_edp(struct drm_device *dev);
0206e353	307	extern void intel_edp_link_config(struct intel_encoder , int , int *);
814948ad	308	extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
b840d907	309	extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
32f9d658	310
a9573556	311	/* intel_panel.c */
1d8e1c75 CW	312	extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
	313	struct drm_display_mode *adjusted_mode);
	314	extern void intel_pch_panel_fitting(struct drm_device *dev,
	315	int fitting_mode,
	316	struct drm_display_mode *mode,
	317	struct drm_display_mode *adjusted_mode);
a9573556 CW	318	extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
	319	extern u32 intel_panel_get_backlight(struct drm_device *dev);
	320	extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
aaa6fd2a	321	extern int intel_panel_setup_backlight(struct drm_device *dev);
47356eb6 CW	322	extern void intel_panel_enable_backlight(struct drm_device *dev);
47356eb6 CW	323	extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a	324	extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949	325	extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75	326
79e53945	327	extern void intel_crtc_load_lut(struct drm_crtc *crtc);
0206e353 AJ	328	extern void intel_encoder_prepare(struct drm_encoder *encoder);
0206e353 AJ	329	extern void intel_encoder_commit(struct drm_encoder *encoder);
ea5b213a	330	extern void intel_encoder_destroy(struct drm_encoder *encoder);
79e53945	331
df0e9248 CW	332	static inline struct intel_encoder intel_attached_encoder(struct drm_connector connector)
	333	{
	334	return to_intel_connector(connector)->encoder;
	335	}
	336
	337	extern void intel_connector_attach_encoder(struct intel_connector *connector,
	338	struct intel_encoder *encoder);
	339	extern struct drm_encoder intel_best_encoder(struct drm_connector connector);
79e53945 JB	340
	341	extern struct drm_display_mode intel_crtc_mode_get(struct drm_device dev,
	342	struct drm_crtc *crtc);
08d7b3d1 CW	343	int intel_get_pipe_from_crtc_id(struct drm_device dev, void data,
08d7b3d1 CW	344	struct drm_file *file_priv);
9d0498a2	345	extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9	346	extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
8261b191 CW	347
8261b191 CW	348	struct intel_load_detect_pipe {
d2dff872	349	struct drm_framebuffer *release_fb;
8261b191 CW	350	bool load_detect_temp;
	351	int dpms_mode;
	352	};
7173188d CW	353	extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
	354	struct drm_connector *connector,
	355	struct drm_display_mode *mode,
8261b191	356	struct intel_load_detect_pipe *old);
21d40d37	357	extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
c1c43977	358	struct drm_connector *connector,
8261b191	359	struct intel_load_detect_pipe *old);
79e53945	360
79e53945 JB	361	extern void intelfb_restore(void);
	362	extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
	363	u16 blue, int regno);
b8c00ac5 DA	364	extern void intel_crtc_fb_gamma_get(struct drm_crtc crtc, u16 red, u16 *green,
b8c00ac5 DA	365	u16 *blue, int regno);
0cdab21f	366	extern void intel_enable_clock_gating(struct drm_device *dev);
f97108d1 JB	367	extern void ironlake_enable_drps(struct drm_device *dev);
f97108d1 JB	368	extern void ironlake_disable_drps(struct drm_device *dev);
3b8d8d91	369	extern void gen6_enable_rps(struct drm_i915_private *dev_priv);
23b2f8bb	370	extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
3b8d8d91	371	extern void gen6_disable_rps(struct drm_device *dev);
48fcfc88	372	extern void intel_init_emon(struct drm_device *dev);
79e53945	373
127bd2ac	374	extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39	375	struct drm_i915_gem_object *obj,
919926ae	376	struct intel_ring_buffer *pipelined);
127bd2ac	377
38651674 DA	378	extern int intel_framebuffer_init(struct drm_device *dev,
38651674 DA	379	struct intel_framebuffer *ifb,
308e5bcb	380	struct drm_mode_fb_cmd2 *mode_cmd,
05394f39	381	struct drm_i915_gem_object *obj);
38651674 DA	382	extern int intel_fbdev_init(struct drm_device *dev);
38651674 DA	383	extern void intel_fbdev_fini(struct drm_device *dev);
28d52043	384
6b95a207 KH	385	extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
6b95a207 KH	386	extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d	387	extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207	388
02e792fb DV	389	extern void intel_setup_overlay(struct drm_device *dev);
02e792fb DV	390	extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81	391	extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb DV	392	extern int intel_overlay_put_image(struct drm_device dev, void data,
	393	struct drm_file *file_priv);
	394	extern int intel_overlay_attrs(struct drm_device dev, void data,
	395	struct drm_file *file_priv);
4abe3520	396
eb1f8e4f	397	extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8	398	extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5	399
b840d907 JB	400	extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
	401	bool state);
	402	#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
	403	#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
	404
645c62a5	405	extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e WF	406	extern void intel_write_eld(struct drm_encoder *encoder,
e0dac65e WF	407	struct drm_display_mode *mode);
d4270e57 JB	408	extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
d4270e57 JB	409
b840d907 JB	410	/* For use by IVB LP watermark workaround in intel_sprite.c */
	411	extern void sandybridge_update_wm(struct drm_device *dev);
	412	extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
	413	uint32_t sprite_width,
	414	int pixel_size);
8ea30864 JB	415
	416	extern int intel_sprite_set_colorkey(struct drm_device dev, void data,
	417	struct drm_file *file_priv);
	418	extern int intel_sprite_get_colorkey(struct drm_device dev, void data,
	419	struct drm_file *file_priv);
	420
79e53945	421	#endif /* __INTEL_DRV_H__ */